path: root/drivers/gpu/drm/amd/include/asic_reg/oss/oss_1_0_sh_mask.h

/*
 *
 * Copyright (C) 2016 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included
 * in all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */

#ifndef OSS_1_0_SH_MASK_H
#define OSS_1_0_SH_MASK_H

#define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000L
#define CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT 0x0000001c
#define CC_DRM_ID_STRAPS__DEVICE_ID_MASK 0x000ffff0L
#define CC_DRM_ID_STRAPS__DEVICE_ID__SHIFT 0x00000004
#define CC_DRM_ID_STRAPS__MAJOR_REV_ID_MASK 0x00f00000L
#define CC_DRM_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x00000014
#define CC_DRM_ID_STRAPS__MINOR_REV_ID_MASK 0x0f000000L
#define CC_DRM_ID_STRAPS__MINOR_REV_ID__SHIFT 0x00000018
#define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00ff0000L
#define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x00000010
#define CLIENT0_BM__RESERVED_MASK 0xffffffffL
#define CLIENT0_BM__RESERVED__SHIFT 0x00000000
#define CLIENT0_CD0__RESERVED_MASK 0xffffffffL
#define CLIENT0_CD0__RESERVED__SHIFT 0x00000000
#define CLIENT0_CD1__RESERVED_MASK 0xffffffffL
#define CLIENT0_CD1__RESERVED__SHIFT 0x00000000
#define CLIENT0_CD2__RESERVED_MASK 0xffffffffL
#define CLIENT0_CD2__RESERVED__SHIFT 0x00000000
#define CLIENT0_CD3__RESERVED_MASK 0xffffffffL
#define CLIENT0_CD3__RESERVED__SHIFT 0x00000000
#define CLIENT0_CK0__RESERVED_MASK 0xffffffffL
#define CLIENT0_CK0__RESERVED__SHIFT 0x00000000
#define CLIENT0_CK1__RESERVED_MASK 0xffffffffL
#define CLIENT0_CK1__RESERVED__SHIFT 0x00000000
#define CLIENT0_CK2__RESERVED_MASK 0xffffffffL
#define CLIENT0_CK2__RESERVED__SHIFT 0x00000000
#define CLIENT0_CK3__RESERVED_MASK 0xffffffffL
#define CLIENT0_CK3__RESERVED__SHIFT 0x00000000
#define CLIENT0_K0__RESERVED_MASK 0xffffffffL
#define CLIENT0_K0__RESERVED__SHIFT 0x00000000
#define CLIENT0_K1__RESERVED_MASK 0xffffffffL
#define CLIENT0_K1__RESERVED__SHIFT 0x00000000
#define CLIENT0_K2__RESERVED_MASK 0xffffffffL
#define CLIENT0_K2__RESERVED__SHIFT 0x00000000
#define CLIENT0_K3__RESERVED_MASK 0xffffffffL
#define CLIENT0_K3__RESERVED__SHIFT 0x00000000
#define CLIENT0_OFFSET_HI__RESERVED_MASK 0xffffffffL
#define CLIENT0_OFFSET_HI__RESERVED__SHIFT 0x00000000
#define CLIENT0_OFFSET__RESERVED_MASK 0xffffffffL
#define CLIENT0_OFFSET__RESERVED__SHIFT 0x00000000
#define CLIENT0_STATUS__RESERVED_MASK 0xffffffffL
#define CLIENT0_STATUS__RESERVED__SHIFT 0x00000000
#define CLIENT1_BM__RESERVED_MASK 0xffffffffL
#define CLIENT1_BM__RESERVED__SHIFT 0x00000000
#define CLIENT1_CD0__RESERVED_MASK 0xffffffffL
#define CLIENT1_CD0__RESERVED__SHIFT 0x00000000
#define CLIENT1_CD1__RESERVED_MASK 0xffffffffL
#define CLIENT1_CD1__RESERVED__SHIFT 0x00000000
#define CLIENT1_CD2__RESERVED_MASK 0xffffffffL
#define CLIENT1_CD2__RESERVED__SHIFT 0x00000000
#define CLIENT1_CD3__RESERVED_MASK 0xffffffffL
#define CLIENT1_CD3__RESERVED__SHIFT 0x00000000
#define CLIENT1_CK0__RESERVED_MASK 0xffffffffL
#define CLIENT1_CK0__RESERVED__SHIFT 0x00000000
#define CLIENT1_CK1__RESERVED_MASK 0xffffffffL
#define CLIENT1_CK1__RESERVED__SHIFT 0x00000000
#define CLIENT1_CK2__RESERVED_MASK 0xffffffffL
#define CLIENT1_CK2__RESERVED__SHIFT 0x00000000
#define CLIENT1_CK3__RESERVED_MASK 0xffffffffL
#define CLIENT1_CK3__RESERVED__SHIFT 0x00000000
#define CLIENT1_K0__RESERVED_MASK 0xffffffffL
#define CLIENT1_K0__RESERVED__SHIFT 0x00000000
#define CLIENT1_K1__RESERVED_MASK 0xffffffffL
#define CLIENT1_K1__RESERVED__SHIFT 0x00000000
#define CLIENT1_K2__RESERVED_MASK 0xffffffffL
#define CLIENT1_K2__RESERVED__SHIFT 0x00000000
#define CLIENT1_K3__RESERVED_MASK 0xffffffffL
#define CLIENT1_K3__RESERVED__SHIFT 0x00000000
#define CLIENT1_OFFSET_HI__RESERVED_MASK 0xffffffffL
#define CLIENT1_OFFSET_HI__RESERVED__SHIFT 0x00000000
#define CLIENT1_OFFSET__RESERVED_MASK 0xffffffffL
#define CLIENT1_OFFSET__RESERVED__SHIFT 0x00000000
#define CLIENT1_PORT_STATUS__RESERVED_MASK 0xffffffffL
#define CLIENT1_PORT_STATUS__RESERVED__SHIFT 0x00000000
#define CLIENT2_BM__RESERVED_MASK 0xffffffffL
#define CLIENT2_BM__RESERVED__SHIFT 0x00000000
#define CLIENT2_CD0__RESERVED_MASK 0xffffffffL
#define CLIENT2_CD0__RESERVED__SHIFT 0x00000000
#define CLIENT2_CD1__RESERVED_MASK 0xffffffffL
#define CLIENT2_CD1__RESERVED__SHIFT 0x00000000
#define CLIENT2_CD2__RESERVED_MASK 0xffffffffL
#define CLIENT2_CD2__RESERVED__SHIFT 0x00000000
#define CLIENT2_CD3__RESERVED_MASK 0xffffffffL
#define CLIENT2_CD3__RESERVED__SHIFT 0x00000000
#define CLIENT2_CK0__RESERVED_MASK 0xffffffffL
#define CLIENT2_CK0__RESERVED__SHIFT 0x00000000
#define CLIENT2_CK1__RESERVED_MASK 0xffffffffL
#define CLIENT2_CK1__RESERVED__SHIFT 0x00000000
#define CLIENT2_CK2__RESERVED_MASK 0xffffffffL
#define CLIENT2_CK2__RESERVED__SHIFT 0x00000000
#define CLIENT2_CK3__RESERVED_MASK 0xffffffffL
#define CLIENT2_CK3__RESERVED__SHIFT 0x00000000
#define CLIENT2_K0__RESERVED_MASK 0xffffffffL
#define CLIENT2_K0__RESERVED__SHIFT 0x00000000
#define CLIENT2_K1__RESERVED_MASK 0xffffffffL
#define CLIENT2_K1__RESERVED__SHIFT 0x00000000
#define CLIENT2_K2__RESERVED_MASK 0xffffffffL
#define CLIENT2_K2__RESERVED__SHIFT 0x00000000
#define CLIENT2_K3__RESERVED_MASK 0xffffffffL
#define CLIENT2_K3__RESERVED__SHIFT 0x00000000
#define CLIENT2_OFFSET_HI__RESERVED_MASK 0xffffffffL
#define CLIENT2_OFFSET_HI__RESERVED__SHIFT 0x00000000
#define CLIENT2_OFFSET__RESERVED_MASK 0xffffffffL
#define CLIENT2_OFFSET__RESERVED__SHIFT 0x00000000
#define CLIENT2_STATUS__RESERVED_MASK 0xffffffffL
#define CLIENT2_STATUS__RESERVED__SHIFT 0x00000000
#define CLIENT3_BM__RESERVED_MASK 0xffffffffL
#define CLIENT3_BM__RESERVED__SHIFT 0x00000000
#define CLIENT3_CD0__RESERVED_MASK 0xffffffffL
#define CLIENT3_CD0__RESERVED__SHIFT 0x00000000
#define CLIENT3_CD1__RESERVED_MASK 0xffffffffL
#define CLIENT3_CD1__RESERVED__SHIFT 0x00000000
#define CLIENT3_CD2__RESERVED_MASK 0xffffffffL
#define CLIENT3_CD2__RESERVED__SHIFT 0x00000000
#define CLIENT3_CD3__RESERVED_MASK 0xffffffffL
#define CLIENT3_CD3__RESERVED__SHIFT 0x00000000
#define CLIENT3_CK0__RESERVED_MASK 0xffffffffL
#define CLIENT3_CK0__RESERVED__SHIFT 0x00000000
#define CLIENT3_CK1__RESERVED_MASK 0xffffffffL
#define CLIENT3_CK1__RESERVED__SHIFT 0x00000000
#define CLIENT3_CK2__RESERVED_MASK 0xffffffffL
#define CLIENT3_CK2__RESERVED__SHIFT 0x00000000
#define CLIENT3_CK3__RESERVED_MASK 0xffffffffL
#define CLIENT3_CK3__RESERVED__SHIFT 0x00000000
#define CLIENT3_K0__RESERVED_MASK 0xffffffffL
#define CLIENT3_K0__RESERVED__SHIFT 0x00000000
#define CLIENT3_K1__RESERVED_MASK 0xffffffffL
#define CLIENT3_K1__RESERVED__SHIFT 0x00000000
#define CLIENT3_K2__RESERVED_MASK 0xffffffffL
#define CLIENT3_K2__RESERVED__SHIFT 0x00000000
#define CLIENT3_K3__RESERVED_MASK 0xffffffffL
#define CLIENT3_K3__RESERVED__SHIFT 0x00000000
#define CLIENT3_OFFSET_HI__RESERVED_MASK 0xffffffffL
#define CLIENT3_OFFSET_HI__RESERVED__SHIFT 0x00000000
#define CLIENT3_OFFSET__RESERVED_MASK 0xffffffffL
#define CLIENT3_OFFSET__RESERVED__SHIFT 0x00000000
#define CLIENT3_STATUS__RESERVED_MASK 0xffffffffL
#define CLIENT3_STATUS__RESERVED__SHIFT 0x00000000
#define CP_CONFIG__CP_RDREQ_URG_MASK 0x00000f00L
#define CP_CONFIG__CP_RDREQ_URG__SHIFT 0x00000008
#define CP_CONFIG__CP_REQ_TRAN_MASK 0x00010000L
#define CP_CONFIG__CP_REQ_TRAN__SHIFT 0x00000010
#define DC_TEST_DEBUG_DATA__DC_TEST_DEBUG_DATA_MASK 0xffffffffL
#define DC_TEST_DEBUG_DATA__DC_TEST_DEBUG_DATA__SHIFT 0x00000000
#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_INDEX_MASK 0x000000ffL
#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_INDEX__SHIFT 0x00000000
#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
#define DC_TEST_DEBUG_INDEX__DC_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008
#define DH_TEST__DH_TEST_MASK 0x00000001L
#define DH_TEST__DH_TEST__SHIFT 0x00000000
#define EXP0__RESERVED_MASK 0xffffffffL
#define EXP0__RESERVED__SHIFT 0x00000000
#define EXP1__RESERVED_MASK 0xffffffffL
#define EXP1__RESERVED__SHIFT 0x00000000
#define EXP2__RESERVED_MASK 0xffffffffL
#define EXP2__RESERVED__SHIFT 0x00000000
#define EXP3__RESERVED_MASK 0xffffffffL
#define EXP3__RESERVED__SHIFT 0x00000000
#define EXP4__RESERVED_MASK 0xffffffffL
#define EXP4__RESERVED__SHIFT 0x00000000
#define EXP5__RESERVED_MASK 0xffffffffL
#define EXP5__RESERVED__SHIFT 0x00000000
#define EXP6__RESERVED_MASK 0xffffffffL
#define EXP6__RESERVED__SHIFT 0x00000000
#define EXP7__RESERVED_MASK 0xffffffffL
#define EXP7__RESERVED__SHIFT 0x00000000
#define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00ff0000L
#define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x00000010
#define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
#define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008
#define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
#define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x00000018
#define HDP_ADDR_CONFIG__NUM_GPUS_MASK 0x00700000L
#define HDP_ADDR_CONFIG__NUM_GPUS__SHIFT 0x00000014
#define HDP_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L
#define HDP_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e
#define HDP_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
#define HDP_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000
#define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L
#define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c
#define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L
#define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004
#define HDP_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L
#define HDP_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c
#define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
#define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010
#define HDP_DEBUG0__HDP_DEBUG__SHIFT 0x00000000
#define HDP_DEBUG1__HDP_DEBUG__SHIFT 0x00000000
#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK 0x20000000L
#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x0000001d
#define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT_MASK 0x00000007L
#define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT__SHIFT 0x00000000
#define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE_MASK 0x00400000L
#define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE__SHIFT 0x00000016
#define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK 0x00800000L
#define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS__SHIFT 0x00000017
#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS_MASK 0x80000000L
#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS__SHIFT 0x0000001f
#define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT_MASK 0x000001f8L
#define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT__SHIFT 0x00000003
#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK 0x00001800L
#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT 0x0000000b
#define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT_MASK 0x0f000000L
#define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT__SHIFT 0x00000018
#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK 0x00200000L
#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT 0x00000015
#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK 0x00180000L
#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x00000013
#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS_MASK 0x40000000L
#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS__SHIFT 0x0000001e
#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK 0x00000600L
#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT 0x00000009
#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK 0x0000003fL
#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT 0x00000000
#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK 0xffffffffL
#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT 0x00000000
#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK 0x00003f00L
#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT 0x00000008
#define HDP_MEMIO_CNTL__MEMIO_BE_MASK 0x0000003cL
#define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x00000002
#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK 0x00008000L
#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT 0x0000000f
#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK 0x00004000L
#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT 0x0000000e
#define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x00000002L
#define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT 0x00000001
#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK 0x00000080L
#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT 0x00000007
#define HDP_MEMIO_CNTL__MEMIO_SEND_MASK 0x00000001L
#define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x00000000
#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK 0x00000040L
#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT 0x00000006
#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK 0xffffffffL
#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT 0x00000000
#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK 0x00000008L
#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT 0x00000003
#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x00000002L
#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT 0x00000001
#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK 0x00000004L
#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x00000002
#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK 0x00000001L
#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT 0x00000000
#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK 0xffffffffL
#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT 0x00000000
#define HDP_MEM_POWER_LS__LS_ENABLE_MASK 0x00000001L
#define HDP_MEM_POWER_LS__LS_ENABLE__SHIFT 0x00000000
#define HDP_MEM_POWER_LS__LS_HOLD_MASK 0x00001f80L
#define HDP_MEM_POWER_LS__LS_HOLD__SHIFT 0x00000007
#define HDP_MEM_POWER_LS__LS_SETUP_MASK 0x0000007eL
#define HDP_MEM_POWER_LS__LS_SETUP__SHIFT 0x00000001
#define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS_MASK 0x00100000L
#define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS__SHIFT 0x00000014
#define HDP_MISC_CNTL__FED_ENABLE_MASK 0x00200000L
#define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x00000015
#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK 0x00000001L
#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE__SHIFT 0x00000000
#define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT_MASK 0x00000780L
#define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT__SHIFT 0x00000007
#define HDP_MISC_CNTL__MC_RDREQ_CREDIT_MASK 0x0007e000L
#define HDP_MISC_CNTL__MC_RDREQ_CREDIT__SHIFT 0x0000000d
#define HDP_MISC_CNTL__MULTIPLE_READS_MASK 0x00000040L
#define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT 0x00000006
#define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR_MASK 0x00001000L
#define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR__SHIFT 0x0000000c
#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x00000020L
#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x00000005
#define HDP_MISC_CNTL__READ_CACHE_INVALIDATE_MASK 0x00080000L
#define HDP_MISC_CNTL__READ_CACHE_INVALIDATE__SHIFT 0x00000013
#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x00000800L
#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0x0000000b
#define HDP_MISC_CNTL__VM_ID_MASK 0x0000001eL
#define HDP_MISC_CNTL__VM_ID__SHIFT 0x00000001
#define HDP_NONSURFACE_BASE__NONSURF_BASE_MASK 0xffffffffL
#define HDP_NONSURFACE_BASE__NONSURF_BASE__SHIFT 0x00000000
#define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE_MASK 0x00000001L
#define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE__SHIFT 0x00000000
#define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE_MASK 0x0000001eL
#define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE__SHIFT 0x00000001
#define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT_MASK 0x03000000L
#define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT__SHIFT 0x00000018
#define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH_MASK 0x00c00000L
#define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH__SHIFT 0x00000016
#define HDP_NONSURFACE_INFO__NONSURF_ENDIAN_MASK 0x00000060L
#define HDP_NONSURFACE_INFO__NONSURF_ENDIAN__SHIFT 0x00000005
#define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT_MASK 0x0c000000L
#define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT__SHIFT 0x0000001a
#define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE_MASK 0x30000000L
#define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE__SHIFT 0x0000001c
#define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS_MASK 0x00300000L
#define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS__SHIFT 0x00000014
#define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE_MASK 0x00000380L
#define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE__SHIFT 0x00000007
#define HDP_NONSURFACE_INFO__NONSURF_PRIV_MASK 0x00008000L
#define HDP_NONSURFACE_INFO__NONSURF_PRIV__SHIFT 0x0000000f
#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM_MASK 0x00001c00L
#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM__SHIFT 0x0000000a
#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE_MASK 0x00006000L
#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE__SHIFT 0x0000000d
#define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB_MASK 0x40000000L
#define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB__SHIFT 0x0000001e
#define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT_MASK 0x00010000L
#define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT__SHIFT 0x00000010
#define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT_MASK 0x000e0000L
#define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT__SHIFT 0x00000011
#define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG_MASK 0xf8000000L
#define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG__SHIFT 0x0000001b
#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR_MASK 0x00000038L
#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR__SHIFT 0x00000003
#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z_MASK 0x000ffe00L
#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z__SHIFT 0x00000009
#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM_MASK 0x000001c0L
#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM__SHIFT 0x00000006
#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI_MASK 0x00000007L
#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI__SHIFT 0x00000000
#define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX_MASK 0x000007ffL
#define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX__SHIFT 0x00000000
#define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX_MASK 0xfffff800L
#define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX__SHIFT 0x0000000b
#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x00000002L
#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT 0x00000001
#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK 0x00000001L
#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT 0x00000000
#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x00000002L
#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT 0x00000001
#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK 0x00000001L
#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT 0x00000000
#define HDP_OUTSTANDING_REQ__READ_REQ_MASK 0x0000ff00L
#define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT 0x00000008
#define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK 0x000000ffL
#define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT 0x00000000
#define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS_MASK 0x00000007L
#define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS__SHIFT 0x00000000
#define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE_MASK 0x00000018L
#define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE__SHIFT 0x00000003
#define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK 0xffffffffL
#define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT 0x00000000
#define HDP_TILING_CONFIG__BANK_SWAPS_MASK 0x00003800L
#define HDP_TILING_CONFIG__BANK_SWAPS__SHIFT 0x0000000b
#define HDP_TILING_CONFIG__BANK_TILING_MASK 0x00000030L
#define HDP_TILING_CONFIG__BANK_TILING__SHIFT 0x00000004
#define HDP_TILING_CONFIG__GROUP_SIZE_MASK 0x000000c0L
#define HDP_TILING_CONFIG__GROUP_SIZE__SHIFT 0x00000006
#define HDP_TILING_CONFIG__PIPE_TILING_MASK 0x0000000eL
#define HDP_TILING_CONFIG__PIPE_TILING__SHIFT 0x00000001
#define HDP_TILING_CONFIG__ROW_TILING_MASK 0x00000700L
#define HDP_TILING_CONFIG__ROW_TILING__SHIFT 0x00000008
#define HDP_TILING_CONFIG__SAMPLE_SPLIT_MASK 0x0000c000L
#define HDP_TILING_CONFIG__SAMPLE_SPLIT__SHIFT 0x0000000e
#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK 0x0000000fL
#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT 0x00000000
#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK 0x000000f0L
#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT 0x00000004
#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK 0x00000f00L
#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT 0x00000008
#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK 0x0000f000L
#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT 0x0000000c
#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK 0x000f0000L
#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT 0x00000010
#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK 0x00f00000L
#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT 0x00000014
#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK 0x0f000000L
#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT 0x00000018
#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK 0xf0000000L
#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT 0x0000001c
#define HDP_XDP_BUSY_STS__BUSY_BITS_MASK 0x0003ffffL
#define HDP_XDP_BUSY_STS__BUSY_BITS__SHIFT 0x00000000
#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY_MASK 0x0000000fL
#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY__SHIFT 0x00000000
#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY_MASK 0x00000ff0L
#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY__SHIFT 0x00000004
#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD_MASK 0x3ffff000L
#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD__SHIFT 0x0000000c
#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE_MASK 0x40000000L
#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE__SHIFT 0x0000001e
#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE_MASK 0x80000000L
#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE__SHIFT 0x0000001f
#define HDP_XDP_CHKN__CHKN_0_RSVD_MASK 0x000000ffL
#define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT 0x00000000
#define HDP_XDP_CHKN__CHKN_1_RSVD_MASK 0x0000ff00L
#define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x00000008
#define HDP_XDP_CHKN__CHKN_2_RSVD_MASK 0x00ff0000L
#define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT 0x00000010
#define HDP_XDP_CHKN__CHKN_3_RSVD_MASK 0xff000000L
#define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT 0x00000018
#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK 0x0000ffffL
#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT 0x00000000
#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK 0x00700000L
#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x00000014
#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK 0x000f0000L
#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x00000010
#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK 0x00040000L
#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT 0x00000012
#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK 0x0000000fL
#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT 0x00000000
#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK 0x00000700L
#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT 0x00000008
#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK 0x000000f0L
#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT 0x00000004
#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK 0x00080000L
#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT 0x00000013
#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK 0x00100000L
#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x00000014
#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK 0x00010000L
#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x00000010
#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE_MASK 0x00020000L
#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE__SHIFT 0x00000011
#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK 0x0000f800L
#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT 0x0000000b
#define HDP_XDP_D2H_RSVD_10__RESERVED_MASK 0xffffffffL
#define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT 0x00000000
#define HDP_XDP_D2H_RSVD_11__RESERVED_MASK 0xffffffffL
#define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT 0x00000000
#define HDP_XDP_D2H_RSVD_12__RESERVED_MASK 0xffffffffL
#define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT 0x00000000
#define HDP_XDP_D2H_RSVD_13__RESERVED_MASK 0xffffffffL
#define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT 0x00000000
#define HDP_XDP_D2H_RSVD_14__RESERVED_MASK 0xffffffffL
#define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT 0x00000000
#define HDP_XDP_D2H_RSVD_15__RESERVED_MASK 0xffffffffL
#define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT 0x00000000
#define HDP_XDP_D2H_RSVD_16__RESERVED_MASK 0xffffffffL
#define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT 0x00000000
#define HDP_XDP_D2H_RSVD_17__RESERVED_MASK 0xffffffffL
#define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT 0x00000000
#define HDP_XDP_D2H_RSVD_18__RESERVED_MASK 0xffffffffL
#define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT 0x00000000
#define HDP_XDP_D2H_RSVD_19__RESERVED_MASK 0xffffffffL
#define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT 0x00000000
#define HDP_XDP_D2H_RSVD_20__RESERVED_MASK 0xffffffffL
#define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT 0x00000000
#define HDP_XDP_D2H_RSVD_21__RESERVED_MASK 0xffffffffL
#define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT 0x00000000
#define HDP_XDP_D2H_RSVD_22__RESERVED_MASK 0xffffffffL
#define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT 0x00000000
#define HDP_XDP_D2H_RSVD_23__RESERVED_MASK 0xffffffffL
#define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT 0x00000000
#define HDP_XDP_D2H_RSVD_24__RESERVED_MASK 0xffffffffL
#define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT 0x00000000
#define HDP_XDP_D2H_RSVD_25__RESERVED_MASK 0xffffffffL
#define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT 0x00000000
#define HDP_XDP_D2H_RSVD_26__RESERVED_MASK 0xffffffffL
#define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT 0x00000000
#define HDP_XDP_D2H_RSVD_27__RESERVED_MASK 0xffffffffL
#define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT 0x00000000
#define HDP_XDP_D2H_RSVD_28__RESERVED_MASK 0xffffffffL
#define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT 0x00000000
#define HDP_XDP_D2H_RSVD_29__RESERVED_MASK 0xffffffffL
#define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT 0x00000000
#define HDP_XDP_D2H_RSVD_30__RESERVED_MASK 0xffffffffL
#define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT 0x00000000
#define HDP_XDP_D2H_RSVD_31__RESERVED_MASK 0xffffffffL
#define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT 0x00000000
#define HDP_XDP_D2H_RSVD_32__RESERVED_MASK 0xffffffffL
#define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT 0x00000000
#define HDP_XDP_D2H_RSVD_33__RESERVED_MASK 0xffffffffL
#define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT 0x00000000
#define HDP_XDP_D2H_RSVD_34__RESERVED_MASK 0xffffffffL
#define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT 0x00000000
#define HDP_XDP_D2H_RSVD_3__RESERVED_MASK 0xffffffffL
#define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT 0x00000000
#define HDP_XDP_D2H_RSVD_4__RESERVED_MASK 0xffffffffL
#define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT 0x00000000
#define HDP_XDP_D2H_RSVD_5__RESERVED_MASK 0xffffffffL
#define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT 0x00000000
#define HDP_XDP_D2H_RSVD_6__RESERVED_MASK 0xffffffffL
#define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT 0x00000000
#define HDP_XDP_D2H_RSVD_7__RESERVED_MASK 0xffffffffL
#define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT 0x00000000
#define HDP_XDP_D2H_RSVD_8__RESERVED_MASK 0xffffffffL
#define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT 0x00000000
#define HDP_XDP_D2H_RSVD_9__RESERVED_MASK 0xffffffffL
#define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT 0x00000000
#define HDP_XDP_DBG_ADDR__CTRL_MASK 0xffff0000L
#define HDP_XDP_DBG_ADDR__CTRL__SHIFT 0x00000010
#define HDP_XDP_DBG_ADDR__STS_MASK 0x0000ffffL
#define HDP_XDP_DBG_ADDR__STS__SHIFT 0x00000000
#define HDP_XDP_DBG_DATA__CTRL_MASK 0xffff0000L
#define HDP_XDP_DBG_DATA__CTRL__SHIFT 0x00000010
#define HDP_XDP_DBG_DATA__STS_MASK 0x0000ffffL
#define HDP_XDP_DBG_DATA__STS__SHIFT 0x00000000
#define HDP_XDP_DBG_MASK__CTRL_MASK 0xffff0000L
#define HDP_XDP_DBG_MASK__CTRL__SHIFT 0x00000010
#define HDP_XDP_DBG_MASK__STS_MASK 0x0000ffffL
#define HDP_XDP_DBG_MASK__STS__SHIFT 0x00000000
#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK 0xffffffffL
#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT 0x00000000
#define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK 0xffffffffL
#define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT 0x00000000
#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK 0xffffffffL
#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT 0x00000000
#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK 0x03ffffffL
#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT 0x00000000
#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK 0x00001000L
#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT 0x0000000c
#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK 0x00002000L
#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT 0x0000000d
#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE_MASK 0x0000003fL
#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE__SHIFT 0x00000000
#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE_MASK 0x00000fc0L
#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE__SHIFT 0x00000006
#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV_MASK 0x00000001L
#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV__SHIFT 0x00000000
#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK 0x00000006L
#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT 0x00000001
#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN_MASK 0x00000008L
#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN__SHIFT 0x00000003
#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK 0x000000f0L
#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT 0x00000004
#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV_MASK 0x00000001L
#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV__SHIFT 0x00000000
#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP_MASK 0x00000006L
#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP__SHIFT 0x00000001
#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN_MASK 0x00000008L
#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN__SHIFT 0x00000003
#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID_MASK 0x07800000L
#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID__SHIFT 0x00000017
#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK_MASK 0x00700000L
#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK__SHIFT 0x00000014
#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV_MASK 0x00000010L
#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV__SHIFT 0x00000004
#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP_MASK 0x00000060L
#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP__SHIFT 0x00000005
#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN_MASK 0x00000080L
#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN__SHIFT 0x00000007
#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID_MASK 0x78000000L
#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID__SHIFT 0x0000001b
#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK 0x000fc000L
#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT 0x0000000e
#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE_MASK 0x00003f00L
#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE__SHIFT 0x00000008
#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK 0x00000001L
#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT 0x00000000
#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK 0x00000006L
#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT 0x00000001
#define HDP_XDP_P2P_BAR0__ADDR_MASK 0x0000ffffL
#define HDP_XDP_P2P_BAR0__ADDR__SHIFT 0x00000000
#define HDP_XDP_P2P_BAR0__FLUSH_MASK 0x000f0000L
#define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x00000010
#define HDP_XDP_P2P_BAR0__VALID_MASK 0x00100000L
#define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x00000014
#define HDP_XDP_P2P_BAR1__ADDR_MASK 0x0000ffffL
#define HDP_XDP_P2P_BAR1__ADDR__SHIFT 0x00000000
#define HDP_XDP_P2P_BAR1__FLUSH_MASK 0x000f0000L
#define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x00000010
#define HDP_XDP_P2P_BAR1__VALID_MASK 0x00100000L
#define HDP_XDP_P2P_BAR1__VALID__SHIFT 0x00000014
#define HDP_XDP_P2P_BAR2__ADDR_MASK 0x0000ffffL
#define HDP_XDP_P2P_BAR2__ADDR__SHIFT 0x00000000
#define HDP_XDP_P2P_BAR2__FLUSH_MASK 0x000f0000L
#define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x00000010
#define HDP_XDP_P2P_BAR2__VALID_MASK 0x00100000L
#define HDP_XDP_P2P_BAR2__VALID__SHIFT 0x00000014
#define HDP_XDP_P2P_BAR3__ADDR_MASK 0x0000ffffL
#define HDP_XDP_P2P_BAR3__ADDR__SHIFT 0x00000000
#define HDP_XDP_P2P_BAR3__FLUSH_MASK 0x000f0000L
#define HDP_XDP_P2P_BAR3__FLUSH__SHIFT 0x00000010
#define HDP_XDP_P2P_BAR3__VALID_MASK 0x00100000L
#define HDP_XDP_P2P_BAR3__VALID__SHIFT 0x00000014
#define HDP_XDP_P2P_BAR4__ADDR_MASK 0x0000ffffL
#define HDP_XDP_P2P_BAR4__ADDR__SHIFT 0x00000000
#define HDP_XDP_P2P_BAR4__FLUSH_MASK 0x000f0000L
#define HDP_XDP_P2P_BAR4__FLUSH__SHIFT 0x00000010
#define HDP_XDP_P2P_BAR4__VALID_MASK 0x00100000L
#define HDP_XDP_P2P_BAR4__VALID__SHIFT 0x00000014
#define HDP_XDP_P2P_BAR5__ADDR_MASK 0x0000ffffL
#define HDP_XDP_P2P_BAR5__ADDR__SHIFT 0x00000000
#define HDP_XDP_P2P_BAR5__FLUSH_MASK 0x000f0000L
#define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x00000010
#define HDP_XDP_P2P_BAR5__VALID_MASK 0x00100000L
#define HDP_XDP_P2P_BAR5__VALID__SHIFT 0x00000014
#define HDP_XDP_P2P_BAR6__ADDR_MASK 0x0000ffffL
#define HDP_XDP_P2P_BAR6__ADDR__SHIFT 0x00000000
#define HDP_XDP_P2P_BAR6__FLUSH_MASK 0x000f0000L
#define HDP_XDP_P2P_BAR6__FLUSH__SHIFT 0x00000010
#define HDP_XDP_P2P_BAR6__VALID_MASK 0x00100000L
#define HDP_XDP_P2P_BAR6__VALID__SHIFT 0x00000014
#define HDP_XDP_P2P_BAR7__ADDR_MASK 0x0000ffffL
#define HDP_XDP_P2P_BAR7__ADDR__SHIFT 0x00000000
#define HDP_XDP_P2P_BAR7__FLUSH_MASK 0x000f0000L
#define HDP_XDP_P2P_BAR7__FLUSH__SHIFT 0x00000010
#define HDP_XDP_P2P_BAR7__VALID_MASK 0x00100000L
#define HDP_XDP_P2P_BAR7__VALID__SHIFT 0x00000014
#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK 0x0000000fL
#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT 0x00000000
#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK 0x00000030L
#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT 0x00000004
#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK 0x01e00000L
#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x00000015
#define HDP_XDP_P2P_MBX_ADDR0__ADDR_MASK 0x001ffffeL
#define HDP_XDP_P2P_MBX_ADDR0__ADDR__SHIFT 0x00000001
#define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK 0x00000001L
#define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT 0x00000000
#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK 0x01e00000L
#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x00000015
#define HDP_XDP_P2P_MBX_ADDR1__ADDR_MASK 0x001ffffeL
#define HDP_XDP_P2P_MBX_ADDR1__ADDR__SHIFT 0x00000001
#define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK 0x00000001L
#define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT 0x00000000
#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK 0x01e00000L
#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x00000015
#define HDP_XDP_P2P_MBX_ADDR2__ADDR_MASK 0x001ffffeL
#define HDP_XDP_P2P_MBX_ADDR2__ADDR__SHIFT 0x00000001
#define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK 0x00000001L
#define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT 0x00000000
#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK 0x01e00000L
#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x00000015
#define HDP_XDP_P2P_MBX_ADDR3__ADDR_MASK 0x001ffffeL
#define HDP_XDP_P2P_MBX_ADDR3__ADDR__SHIFT 0x00000001
#define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK 0x00000001L
#define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT 0x00000000
#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK 0x01e00000L
#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x00000015
#define HDP_XDP_P2P_MBX_ADDR4__ADDR_MASK 0x001ffffeL
#define HDP_XDP_P2P_MBX_ADDR4__ADDR__SHIFT 0x00000001
#define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK 0x00000001L
#define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT 0x00000000
#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK 0x01e00000L
#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x00000015
#define HDP_XDP_P2P_MBX_ADDR5__ADDR_MASK 0x001ffffeL
#define HDP_XDP_P2P_MBX_ADDR5__ADDR__SHIFT 0x00000001
#define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK 0x00000001L
#define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT 0x00000000
#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK 0x01e00000L
#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x00000015
#define HDP_XDP_P2P_MBX_ADDR6__ADDR_MASK 0x001ffffeL
#define HDP_XDP_P2P_MBX_ADDR6__ADDR__SHIFT 0x00000001
#define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK 0x00000001L
#define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT 0x00000000
#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK 0x00003fffL
#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT 0x00000000
#define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL_MASK 0x00000018L
#define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL__SHIFT 0x00000003
#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN_MASK 0x00000001L
#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN__SHIFT 0x00000000
#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER_MASK 0x00000006L
#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER__SHIFT 0x00000001
#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT_MASK 0x0000003fL
#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT__SHIFT 0x00000000
#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS_MASK 0x00000040L
#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS__SHIFT 0x00000006
#define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK_MASK 0x00000080L
#define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK__SHIFT 0x00000007
#define HDP_XDP_STICKY__STICKY_STS_MASK 0x0000ffffL
#define HDP_XDP_STICKY__STICKY_STS__SHIFT 0x00000000
#define HDP_XDP_STICKY__STICKY_W1C_MASK 0xffff0000L
#define HDP_XDP_STICKY__STICKY_W1C__SHIFT 0x00000010
#define HFS_SEED0__RESERVED_MASK 0xffffffffL
#define HFS_SEED0__RESERVED__SHIFT 0x00000000
#define HFS_SEED1__RESERVED_MASK 0xffffffffL
#define HFS_SEED1__RESERVED__SHIFT 0x00000000
#define HFS_SEED2__RESERVED_MASK 0xffffffffL
#define HFS_SEED2__RESERVED__SHIFT 0x00000000
#define HFS_SEED3__RESERVED_MASK 0xffffffffL
#define HFS_SEED3__RESERVED__SHIFT 0x00000000
#define IH_ADVFAULT_CNTL__NUM_FAULTS_DROPPED_MASK 0x0000ff00L
#define IH_ADVFAULT_CNTL__NUM_FAULTS_DROPPED__SHIFT 0x00000008
#define IH_ADVFAULT_CNTL__WAIT_TIMER_MASK 0x3fff0000L
#define IH_ADVFAULT_CNTL__WAIT_TIMER__SHIFT 0x00000010
#define IH_ADVFAULT_CNTL__WATERMARK_ENABLE_MASK 0x00000008L
#define IH_ADVFAULT_CNTL__WATERMARK_ENABLE__SHIFT 0x00000003
#define IH_ADVFAULT_CNTL__WATERMARK_MASK 0x00000007L
#define IH_ADVFAULT_CNTL__WATERMARK_REACHED_MASK 0x00000010L
#define IH_ADVFAULT_CNTL__WATERMARK_REACHED__SHIFT 0x00000004
#define IH_ADVFAULT_CNTL__WATERMARK__SHIFT 0x00000000
#define IH_CNTL__CLIENT_FIFO_HIGHWATER_MASK 0x00000300L
#define IH_CNTL__CLIENT_FIFO_HIGHWATER__SHIFT 0x00000008
#define IH_CNTL__ENABLE_INTR_MASK 0x00000001L
#define IH_CNTL__ENABLE_INTR__SHIFT 0x00000000
#define IH_CNTL__MC_FIFO_HIGHWATER_MASK 0x00007c00L
#define IH_CNTL__MC_FIFO_HIGHWATER__SHIFT 0x0000000a
#define IH_CNTL__MC_SWAP_MASK 0x00000006L
#define IH_CNTL__MC_SWAP__SHIFT 0x00000001
#define IH_CNTL__MC_TRAN_MASK 0x00000008L
#define IH_CNTL__MC_TRAN__SHIFT 0x00000003
#define IH_CNTL__MC_VMID_MASK 0x1e000000L
#define IH_CNTL__MC_VMID__SHIFT 0x00000019
#define IH_CNTL__MC_WR_CLEAN_CNT_MASK 0x01f00000L
#define IH_CNTL__MC_WR_CLEAN_CNT__SHIFT 0x00000014
#define IH_CNTL__MC_WRREQ_CREDIT_MASK 0x000f8000L
#define IH_CNTL__MC_WRREQ_CREDIT__SHIFT 0x0000000f
#define IH_CNTL__RPTR_REARM_MASK 0x00000010L
#define IH_CNTL__RPTR_REARM__SHIFT 0x00000004
#define IH_LEVEL_STATUS__BIF_STATUS_MASK 0x00000010L
#define IH_LEVEL_STATUS__BIF_STATUS__SHIFT 0x00000004
#define IH_LEVEL_STATUS__DC_STATUS_MASK 0x00000001L
#define IH_LEVEL_STATUS__DC_STATUS__SHIFT 0x00000000
#define IH_LEVEL_STATUS__ROM_STATUS_MASK 0x00000004L
#define IH_LEVEL_STATUS__ROM_STATUS__SHIFT 0x00000002
#define IH_LEVEL_STATUS__SRBM_STATUS_MASK 0x00000008L
#define IH_LEVEL_STATUS__SRBM_STATUS__SHIFT 0x00000003
#define IH_LEVEL_STATUS__XDMA_STATUS_MASK 0x00000020L
#define IH_LEVEL_STATUS__XDMA_STATUS__SHIFT 0x00000005
#define IH_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffffL
#define IH_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x00000000
#define IH_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffffL
#define IH_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x00000000
#define IH_PERFMON_CNTL__CLEAR0_MASK 0x00000002L
#define IH_PERFMON_CNTL__CLEAR0__SHIFT 0x00000001
#define IH_PERFMON_CNTL__CLEAR1_MASK 0x00000200L
#define IH_PERFMON_CNTL__CLEAR1__SHIFT 0x00000009
#define IH_PERFMON_CNTL__ENABLE0_MASK 0x00000001L
#define IH_PERFMON_CNTL__ENABLE0__SHIFT 0x00000000
#define IH_PERFMON_CNTL__ENABLE1_MASK 0x00000100L
#define IH_PERFMON_CNTL__ENABLE1__SHIFT 0x00000008
#define IH_PERFMON_CNTL__PERF_SEL0_MASK 0x000000fcL
#define IH_PERFMON_CNTL__PERF_SEL0__SHIFT 0x00000002
#define IH_PERFMON_CNTL__PERF_SEL1_MASK 0x0000fc00L
#define IH_PERFMON_CNTL__PERF_SEL1__SHIFT 0x0000000a
#define IH_RB_BASE__ADDR_MASK 0xffffffffL
#define IH_RB_BASE__ADDR__SHIFT 0x00000000
#define IH_RB_CNTL__RB_ENABLE_MASK 0x00000001L
#define IH_RB_CNTL__RB_ENABLE__SHIFT 0x00000000
#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE_MASK 0x00000040L
#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE__SHIFT 0x00000006
#define IH_RB_CNTL__RB_GPU_TS_ENABLE_MASK 0x00000080L
#define IH_RB_CNTL__RB_GPU_TS_ENABLE__SHIFT 0x00000007
#define IH_RB_CNTL__RB_SIZE_MASK 0x0000003eL
#define IH_RB_CNTL__RB_SIZE__SHIFT 0x00000001
#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L
#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x0000001f
#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK 0x00010000L
#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE__SHIFT 0x00000010
#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L
#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x00000008
#define IH_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x00003e00L
#define IH_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x00000009
#define IH_RB_RPTR__OFFSET_MASK 0x0003fffcL
#define IH_RB_RPTR__OFFSET__SHIFT 0x00000002
#define IH_RB_WPTR_ADDR_HI__ADDR_MASK 0x000000ffL
#define IH_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x00000000
#define IH_RB_WPTR_ADDR_LO__ADDR_MASK 0xfffffffcL
#define IH_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x00000002
#define IH_RB_WPTR__OFFSET_MASK 0x0003fffcL
#define IH_RB_WPTR__OFFSET__SHIFT 0x00000002
#define IH_RB_WPTR__RB_OVERFLOW_MASK 0x00000001L
#define IH_RB_WPTR__RB_OVERFLOW__SHIFT 0x00000000
#define IH_STATUS__BIF_INTERRUPT_LINE_MASK 0x00000400L
#define IH_STATUS__BIF_INTERRUPT_LINE__SHIFT 0x0000000a
#define IH_STATUS__IDLE_MASK 0x00000001L
#define IH_STATUS__IDLE__SHIFT 0x00000000
#define IH_STATUS__INPUT_IDLE_MASK 0x00000002L
#define IH_STATUS__INPUT_IDLE__SHIFT 0x00000001
#define IH_STATUS__MC_WR_CLEAN_PENDING_MASK 0x00000100L
#define IH_STATUS__MC_WR_CLEAN_PENDING__SHIFT 0x00000008
#define IH_STATUS__MC_WR_CLEAN_STALL_MASK 0x00000200L
#define IH_STATUS__MC_WR_CLEAN_STALL__SHIFT 0x00000009
#define IH_STATUS__MC_WR_IDLE_MASK 0x00000040L
#define IH_STATUS__MC_WR_IDLE__SHIFT 0x00000006
#define IH_STATUS__MC_WR_STALL_MASK 0x00000080L
#define IH_STATUS__MC_WR_STALL__SHIFT 0x00000007
#define IH_STATUS__RB_FULL_DRAIN_MASK 0x00000010L
#define IH_STATUS__RB_FULL_DRAIN__SHIFT 0x00000004
#define IH_STATUS__RB_FULL_MASK 0x00000008L
#define IH_STATUS__RB_FULL__SHIFT 0x00000003
#define IH_STATUS__RB_IDLE_MASK 0x00000004L
#define IH_STATUS__RB_IDLE__SHIFT 0x00000002
#define IH_STATUS__RB_OVERFLOW_MASK 0x00000020L
#define IH_STATUS__RB_OVERFLOW__SHIFT 0x00000005
#define KEFUSE0__RESERVED_MASK 0xffffffffL
#define KEFUSE0__RESERVED__SHIFT 0x00000000
#define KEFUSE1__RESERVED_MASK 0xffffffffL
#define KEFUSE1__RESERVED__SHIFT 0x00000000
#define KEFUSE2__RESERVED_MASK 0xffffffffL
#define KEFUSE2__RESERVED__SHIFT 0x00000000
#define KEFUSE3__RESERVED_MASK 0xffffffffL
#define KEFUSE3__RESERVED__SHIFT 0x00000000
#define KHFS0__RESERVED_MASK 0xffffffffL
#define KHFS0__RESERVED__SHIFT 0x00000000
#define KHFS1__RESERVED_MASK 0xffffffffL
#define KHFS1__RESERVED__SHIFT 0x00000000
#define KHFS2__RESERVED_MASK 0xffffffffL
#define KHFS2__RESERVED__SHIFT 0x00000000
#define KHFS3__RESERVED_MASK 0xffffffffL
#define KHFS3__RESERVED__SHIFT 0x00000000
#define KSESSION0__RESERVED_MASK 0xffffffffL
#define KSESSION0__RESERVED__SHIFT 0x00000000
#define KSESSION1__RESERVED_MASK 0xffffffffL
#define KSESSION1__RESERVED__SHIFT 0x00000000
#define KSESSION2__RESERVED_MASK 0xffffffffL
#define KSESSION2__RESERVED__SHIFT 0x00000000
#define KSESSION3__RESERVED_MASK 0xffffffffL
#define KSESSION3__RESERVED__SHIFT 0x00000000
#define KSIG0__RESERVED_MASK 0xffffffffL
#define KSIG0__RESERVED__SHIFT 0x00000000
#define KSIG1__RESERVED_MASK 0xffffffffL
#define KSIG1__RESERVED__SHIFT 0x00000000
#define KSIG2__RESERVED_MASK 0xffffffffL
#define KSIG2__RESERVED__SHIFT 0x00000000
#define KSIG3__RESERVED_MASK 0xffffffffL
#define KSIG3__RESERVED__SHIFT 0x00000000
#define LX0__RESERVED_MASK 0xffffffffL
#define LX0__RESERVED__SHIFT 0x00000000
#define LX1__RESERVED_MASK 0xffffffffL
#define LX1__RESERVED__SHIFT 0x00000000
#define LX2__RESERVED_MASK 0xffffffffL
#define LX2__RESERVED__SHIFT 0x00000000
#define LX3__RESERVED_MASK 0xffffffffL
#define LX3__RESERVED__SHIFT 0x00000000
#define RINGOSC_MASK__MASK_MASK 0x0000ffffL
#define RINGOSC_MASK__MASK__SHIFT 0x00000000
#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0_MASK 0x00000007L
#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0__SHIFT 0x00000000
#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1_MASK 0x00000038L
#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1__SHIFT 0x00000003
#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2_MASK 0x000001c0L
#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2__SHIFT 0x00000006
#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3_MASK 0x00000e00L
#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3__SHIFT 0x00000009
#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0_MASK 0x00038000L
#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT 0x0000000f
#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0_MASK 0x00e00000L
#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0__SHIFT 0x00000015
#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_MASK 0x0000ff00L
#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT 0x00000008
#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_MASK 0x000000ffL
#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE__SHIFT 0x00000000
#define SEM_MAILBOX__HOSTPORT_MASK 0x0000ff00L
#define SEM_MAILBOX__HOSTPORT__SHIFT 0x00000008
#define SEM_MAILBOX__SIDEPORT_MASK 0x000000ffL
#define SEM_MAILBOX__SIDEPORT__SHIFT 0x00000000
#define SEM_MCIF_CONFIG__MC_REQ_SWAP_MASK 0x00000003L
#define SEM_MCIF_CONFIG__MC_REQ_SWAP__SHIFT 0x00000000
#define SPU_PORT_STATUS__RESERVED_MASK 0xffffffffL
#define SPU_PORT_STATUS__RESERVED__SHIFT 0x00000000
#define SRBM_CAM_DATA__CAM_ADDR_MASK 0x0000ffffL
#define SRBM_CAM_DATA__CAM_ADDR__SHIFT 0x00000000
#define SRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000L
#define SRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x00000010
#define SRBM_CAM_INDEX__CAM_INDEX_MASK 0x00000007L
#define SRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x00000000
#define SRBM_CHIP_REVISION__CHIP_REVISION_MASK 0x000000ffL
#define SRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x00000000
#define SRBM_CNTL__COMBINE_SYSTEM_MC_MASK 0x00020000L
#define SRBM_CNTL__COMBINE_SYSTEM_MC__SHIFT 0x00000011
#define SRBM_CNTL__PWR_REQUEST_HALT_MASK 0x00010000L
#define SRBM_CNTL__PWR_REQUEST_HALT__SHIFT 0x00000010
#define SRBM_CNTL__READ_TIMEOUT_MASK 0x000003ffL
#define SRBM_CNTL__READ_TIMEOUT__SHIFT 0x00000000
#define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX_MASK 0x0000003fL
#define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX__SHIFT 0x00000000
#define SRBM_DEBUG_DATA__DATA_MASK 0xffffffffL
#define SRBM_DEBUG_DATA__DATA__SHIFT 0x00000000
#define SRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x00000002L
#define SRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x00000001
#define SRBM_DEBUG__IGNORE_RDY_MASK 0x00000001L
#define SRBM_DEBUG__IGNORE_RDY__SHIFT 0x00000000
#define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE_MASK 0x00000100L
#define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x00000008
#define SRBM_DEBUG_SNAPSHOT__BIF_RDY_MASK 0x00000080L
#define SRBM_DEBUG_SNAPSHOT__BIF_RDY__SHIFT 0x00000007
#define SRBM_DEBUG_SNAPSHOT__DC_RDY_MASK 0x00000040L
#define SRBM_DEBUG_SNAPSHOT__DC_RDY__SHIFT 0x00000006
#define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x00000004L
#define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x00000002
#define SRBM_DEBUG_SNAPSHOT__GRBM_RDY_MASK 0x00000020L
#define SRBM_DEBUG_SNAPSHOT__GRBM_RDY__SHIFT 0x00000005
#define SRBM_DEBUG_SNAPSHOT__MCB_RDY_MASK 0x00000001L
#define SRBM_DEBUG_SNAPSHOT__MCB_RDY__SHIFT 0x00000000
#define SRBM_DEBUG_SNAPSHOT__MCC0_RDY_MASK 0x10000000L
#define SRBM_DEBUG_SNAPSHOT__MCC0_RDY__SHIFT 0x0000001c
#define SRBM_DEBUG_SNAPSHOT__MCC1_RDY_MASK 0x08000000L
#define SRBM_DEBUG_SNAPSHOT__MCC1_RDY__SHIFT 0x0000001b
#define SRBM_DEBUG_SNAPSHOT__MCC2_RDY_MASK 0x04000000L
#define SRBM_DEBUG_SNAPSHOT__MCC2_RDY__SHIFT 0x0000001a
#define SRBM_DEBUG_SNAPSHOT__MCC3_RDY_MASK 0x02000000L
#define SRBM_DEBUG_SNAPSHOT__MCC3_RDY__SHIFT 0x00000019
#define SRBM_DEBUG_SNAPSHOT__MCC4_RDY_MASK 0x01000000L
#define SRBM_DEBUG_SNAPSHOT__MCC4_RDY__SHIFT 0x00000018
#define SRBM_DEBUG_SNAPSHOT__MCC5_RDY_MASK 0x00800000L
#define SRBM_DEBUG_SNAPSHOT__MCC5_RDY__SHIFT 0x00000017
#define SRBM_DEBUG_SNAPSHOT__MCC6_RDY_MASK 0x00400000L
#define SRBM_DEBUG_SNAPSHOT__MCC6_RDY__SHIFT 0x00000016
#define SRBM_DEBUG_SNAPSHOT__MCC7_RDY_MASK 0x00200000L
#define SRBM_DEBUG_SNAPSHOT__MCC7_RDY__SHIFT 0x00000015
#define SRBM_DEBUG_SNAPSHOT__MCD0_RDY_MASK 0x00100000L
#define SRBM_DEBUG_SNAPSHOT__MCD0_RDY__SHIFT 0x00000014
#define SRBM_DEBUG_SNAPSHOT__MCD1_RDY_MASK 0x00080000L
#define SRBM_DEBUG_SNAPSHOT__MCD1_RDY__SHIFT 0x00000013
#define SRBM_DEBUG_SNAPSHOT__MCD2_RDY_MASK 0x00040000L
#define SRBM_DEBUG_SNAPSHOT__MCD2_RDY__SHIFT 0x00000012
#define SRBM_DEBUG_SNAPSHOT__MCD3_RDY_MASK 0x00020000L
#define SRBM_DEBUG_SNAPSHOT__MCD3_RDY__SHIFT 0x00000011
#define SRBM_DEBUG_SNAPSHOT__MCD4_RDY_MASK 0x00010000L
#define SRBM_DEBUG_SNAPSHOT__MCD4_RDY__SHIFT 0x00000010
#define SRBM_DEBUG_SNAPSHOT__MCD5_RDY_MASK 0x00008000L
#define SRBM_DEBUG_SNAPSHOT__MCD5_RDY__SHIFT 0x0000000f
#define SRBM_DEBUG_SNAPSHOT__MCD6_RDY_MASK 0x00004000L
#define SRBM_DEBUG_SNAPSHOT__MCD6_RDY__SHIFT 0x0000000e
#define SRBM_DEBUG_SNAPSHOT__MCD7_RDY_MASK 0x00002000L
#define SRBM_DEBUG_SNAPSHOT__MCD7_RDY__SHIFT 0x0000000d
#define SRBM_DEBUG_SNAPSHOT__ORB_RDY_MASK 0x00001000L
#define SRBM_DEBUG_SNAPSHOT__ORB_RDY__SHIFT 0x0000000c
#define SRBM_DEBUG_SNAPSHOT__REGBB_RDY_MASK 0x00000800L
#define SRBM_DEBUG_SNAPSHOT__REGBB_RDY__SHIFT 0x0000000b
#define SRBM_DEBUG_SNAPSHOT__UVD_RDY_MASK 0x00000200L
#define SRBM_DEBUG_SNAPSHOT__UVD_RDY__SHIFT 0x00000009
#define SRBM_DEBUG_SNAPSHOT__VCE_RDY_MASK 0x20000000L
#define SRBM_DEBUG_SNAPSHOT__VCE_RDY__SHIFT 0x0000001d
#define SRBM_DEBUG_SNAPSHOT__XDMA_RDY_MASK 0x00000100L
#define SRBM_DEBUG_SNAPSHOT__XDMA_RDY__SHIFT 0x00000008
#define SRBM_DEBUG_SNAPSHOT__XSP_RDY_MASK 0x00000400L
#define SRBM_DEBUG_SNAPSHOT__XSP_RDY__SHIFT 0x0000000a
#define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE_MASK 0x00000010L
#define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x00000004
#define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE_MASK 0x00000040L
#define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x00000006
#define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE_MASK 0x00000020L
#define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x00000005
#define SRBM_GFX_CNTL__VMID_MASK 0x000000f0L
#define SRBM_GFX_CNTL__VMID__SHIFT 0x00000004
#define SRBM_INT_ACK__RDERR_INT_ACK_MASK 0x00000001L
#define SRBM_INT_ACK__RDERR_INT_ACK__SHIFT 0x00000000
#define SRBM_INT_CNTL__RDERR_INT_MASK_MASK 0x00000001L
#define SRBM_INT_CNTL__RDERR_INT_MASK__SHIFT 0x00000000
#define SRBM_INT_STATUS__RDERR_INT_STAT_MASK 0x00000001L
#define SRBM_INT_STATUS__RDERR_INT_STAT__SHIFT 0x00000000
#define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001f00L
#define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x00000008
#define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000fL
#define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x00000000
#define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI_MASK 0xffffffffL
#define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI__SHIFT 0x00000000
#define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO_MASK 0xffffffffL
#define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO__SHIFT 0x00000000
#define SRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x0000003fL
#define SRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000
#define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI_MASK 0xffffffffL
#define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI__SHIFT 0x00000000
#define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO_MASK 0xffffffffL
#define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO__SHIFT 0x00000000
#define SRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x0000003fL
#define SRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x00000000
#define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L
#define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x00000008
#define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L
#define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0x0000000a
#define SRBM_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000fL
#define SRBM_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x00000000
#define SRBM_READ_ERROR__READ_ADDRESS_MASK 0x0003fffcL
#define SRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x00000002
#define SRBM_READ_ERROR__READ_ERROR_MASK 0x80000000L
#define SRBM_READ_ERROR__READ_ERROR__SHIFT 0x0000001f
#define SRBM_READ_ERROR__READ_REQUESTER_GRBM_MASK 0x02000000L
#define SRBM_READ_ERROR__READ_REQUESTER_GRBM__SHIFT 0x00000019
#define SRBM_READ_ERROR__READ_REQUESTER_HI_MASK 0x01000000L
#define SRBM_READ_ERROR__READ_REQUESTER_HI__SHIFT 0x00000018
#define SRBM_READ_ERROR__READ_REQUESTER_SMU_MASK 0x04000000L
#define SRBM_READ_ERROR__READ_REQUESTER_SMU__SHIFT 0x0000001a
#define SRBM_READ_ERROR__READ_REQUESTER_TST_MASK 0x00400000L
#define SRBM_READ_ERROR__READ_REQUESTER_TST__SHIFT 0x00000016
#define SRBM_READ_ERROR__READ_REQUESTER_UVD_MASK 0x20000000L
#define SRBM_READ_ERROR__READ_REQUESTER_UVD__SHIFT 0x0000001d
#define SRBM_READ_ERROR__READ_REQUESTER_VCE_MASK 0x00100000L
#define SRBM_READ_ERROR__READ_REQUESTER_VCE__SHIFT 0x00000014
#define SRBM_SOFT_RESET__SOFT_RESET_BIF_MASK 0x00000002L
#define SRBM_SOFT_RESET__SOFT_RESET_BIF__SHIFT 0x00000001
#define SRBM_SOFT_RESET__SOFT_RESET_DC_MASK 0x00000020L
#define SRBM_SOFT_RESET__SOFT_RESET_DC__SHIFT 0x00000005
#define SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK 0x00000100L
#define SRBM_SOFT_RESET__SOFT_RESET_GRBM__SHIFT 0x00000008
#define SRBM_SOFT_RESET__SOFT_RESET_HDP_MASK 0x00000200L
#define SRBM_SOFT_RESET__SOFT_RESET_HDP__SHIFT 0x00000009
#define SRBM_SOFT_RESET__SOFT_RESET_IH_MASK 0x00000400L
#define SRBM_SOFT_RESET__SOFT_RESET_IH__SHIFT 0x0000000a
#define SRBM_SOFT_RESET__SOFT_RESET_MC_MASK 0x00000800L
#define SRBM_SOFT_RESET__SOFT_RESET_MC__SHIFT 0x0000000b
#define SRBM_SOFT_RESET__SOFT_RESET_ORB_MASK 0x00800000L
#define SRBM_SOFT_RESET__SOFT_RESET_ORB__SHIFT 0x00000017
#define SRBM_SOFT_RESET__SOFT_RESET_REGBB_MASK 0x00400000L
#define SRBM_SOFT_RESET__SOFT_RESET_REGBB__SHIFT 0x00000016
#define SRBM_SOFT_RESET__SOFT_RESET_ROM_MASK 0x00004000L
#define SRBM_SOFT_RESET__SOFT_RESET_ROM__SHIFT 0x0000000e
#define SRBM_SOFT_RESET__SOFT_RESET_SEM_MASK 0x00008000L
#define SRBM_SOFT_RESET__SOFT_RESET_SEM__SHIFT 0x0000000f
#define SRBM_SOFT_RESET__SOFT_RESET_TST_MASK 0x00200000L
#define SRBM_SOFT_RESET__SOFT_RESET_TST__SHIFT 0x00000015
#define SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK 0x00040000L
#define SRBM_SOFT_RESET__SOFT_RESET_UVD__SHIFT 0x00000012
#define SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK 0x01000000L
#define SRBM_SOFT_RESET__SOFT_RESET_VCE__SHIFT 0x00000018
#define SRBM_SOFT_RESET__SOFT_RESET_VMC_MASK 0x00020000L
#define SRBM_SOFT_RESET__SOFT_RESET_VMC__SHIFT 0x00000011
#define SRBM_SOFT_RESET__SOFT_RESET_XDMA_MASK 0x02000000L
#define SRBM_SOFT_RESET__SOFT_RESET_XDMA__SHIFT 0x00000019
#define SRBM_SOFT_RESET__SOFT_RESET_XSP_MASK 0x00080000L
#define SRBM_SOFT_RESET__SOFT_RESET_XSP__SHIFT 0x00000013
#define SRBM_STATUS2__TST_RQ_PENDING_MASK 0x00000002L
#define SRBM_STATUS2__TST_RQ_PENDING__SHIFT 0x00000001
#define SRBM_STATUS2__VCE_BUSY_MASK 0x00000080L
#define SRBM_STATUS2__VCE_BUSY__SHIFT 0x00000007
#define SRBM_STATUS2__VCE_RQ_PENDING_MASK 0x00000008L
#define SRBM_STATUS2__VCE_RQ_PENDING__SHIFT 0x00000003
#define SRBM_STATUS2__XDMA_BUSY_MASK 0x00000100L
#define SRBM_STATUS2__XDMA_BUSY__SHIFT 0x00000008
#define SRBM_STATUS2__XSP_BUSY_MASK 0x00000010L
#define SRBM_STATUS2__XSP_BUSY__SHIFT 0x00000004
#define SRBM_STATUS__BIF_BUSY_MASK 0x20000000L
#define SRBM_STATUS__BIF_BUSY__SHIFT 0x0000001d
#define SRBM_STATUS__GRBM_RQ_PENDING_MASK 0x00000020L
#define SRBM_STATUS__GRBM_RQ_PENDING__SHIFT 0x00000005
#define SRBM_STATUS__HI_RQ_PENDING_MASK 0x00000040L
#define SRBM_STATUS__HI_RQ_PENDING__SHIFT 0x00000006
#define SRBM_STATUS__IH_BUSY_MASK 0x00020000L
#define SRBM_STATUS__IH_BUSY__SHIFT 0x00000011
#define SRBM_STATUS__IO_EXTERN_SIGNAL_MASK 0x00000080L
#define SRBM_STATUS__IO_EXTERN_SIGNAL__SHIFT 0x00000007
#define SRBM_STATUS__MCB_BUSY_MASK 0x00000200L
#define SRBM_STATUS__MCB_BUSY__SHIFT 0x00000009
#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK 0x00000400L
#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY__SHIFT 0x0000000a
#define SRBM_STATUS__MCC_BUSY_MASK 0x00000800L
#define SRBM_STATUS__MCC_BUSY__SHIFT 0x0000000b
#define SRBM_STATUS__MCD_BUSY_MASK 0x00001000L
#define SRBM_STATUS__MCD_BUSY__SHIFT 0x0000000c
#define SRBM_STATUS__SEM_BUSY_MASK 0x00004000L
#define SRBM_STATUS__SEM_BUSY__SHIFT 0x0000000e
#define SRBM_STATUS__SMU_RQ_PENDING_MASK 0x00000010L
#define SRBM_STATUS__SMU_RQ_PENDING__SHIFT 0x00000004
#define SRBM_STATUS__UVD_BUSY_MASK 0x00080000L
#define SRBM_STATUS__UVD_BUSY__SHIFT 0x00000013
#define SRBM_STATUS__UVD_RQ_PENDING_MASK 0x00000002L
#define SRBM_STATUS__UVD_RQ_PENDING__SHIFT 0x00000001
#define SRBM_STATUS__VMC_BUSY_MASK 0x00000100L
#define SRBM_STATUS__VMC_BUSY__SHIFT 0x00000008
#define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001f00L
#define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x00000008
#define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000fL
#define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x00000000
#define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001f00L
#define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x00000008
#define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000fL
#define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x00000000
#define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001f00L
#define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x00000008
#define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000fL
#define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x00000000
#define UVD_CONFIG__UVD_RDREQ_URG_MASK 0x00000f00L
#define UVD_CONFIG__UVD_RDREQ_URG__SHIFT 0x00000008
#define UVD_CONFIG__UVD_REQ_TRAN_MASK 0x00010000L
#define UVD_CONFIG__UVD_REQ_TRAN__SHIFT 0x00000010
#define VCE_CONFIG__VCE_RDREQ_URG_MASK 0x00000f00L
#define VCE_CONFIG__VCE_RDREQ_URG__SHIFT 0x00000008
#define VCE_CONFIG__VCE_REQ_TRAN_MASK 0x00010000L
#define VCE_CONFIG__VCE_REQ_TRAN__SHIFT 0x00000010
#define XDMA_MSTR_CNTL__XDMA_MSTR_LAT_TEST_EN_MASK 0x00080000L
#define XDMA_MSTR_CNTL__XDMA_MSTR_LAT_TEST_EN__SHIFT 0x00000013
#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_COUNT_ENABLE_MASK 0x80000000L
#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_COUNT_ENABLE__SHIFT 0x0000001f
#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_COUNT_MASK 0x0000ffffL
#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_COUNT__SHIFT 0x00000000
#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_THRESHOLD_MASK 0x3fff0000L
#define XDMA_MSTR_MEM_OVERFLOW_CNTL__XDMA_MSTR_OVERFLOW_THRESHOLD__SHIFT 0x00000010

#endif