summaryrefslogtreecommitdiffstats
path: root/arch/powerpc/boot/dts/cm5200.dts
blob: c6ca6319e4f7f2a2adeb8b98066d38fdf4f0edac (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
/*
 * CM5200 board Device Tree Source
 *
 * Copyright (C) 2007 Semihalf
 * Marian Balakowicz <m8@semihalf.com>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

/*
 * WARNING: Do not depend on this tree layout remaining static just yet.
 * The MPC5200 device tree conventions are still in flux
 * Keep an eye on the linuxppc-dev mailing list for more details
 */

/ {
	model = "schindler,cm5200";
	compatible = "schindler,cm5200";
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,5200@0 {
			device_type = "cpu";
			reg = <0>;
			d-cache-line-size = <20>;
			i-cache-line-size = <20>;
			d-cache-size = <4000>;		// L1, 16K
			i-cache-size = <4000>;		// L1, 16K
			timebase-frequency = <0>;	// from bootloader
			bus-frequency = <0>;		// from bootloader
			clock-frequency = <0>;		// from bootloader
		};
	};

	memory {
		device_type = "memory";
		reg = <00000000 04000000>;	// 64MB
	};

	soc5200@f0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "fsl,mpc5200b-immr";
		ranges = <0 f0000000 0000c000>;
		reg = <f0000000 00000100>;
		bus-frequency = <0>;		// from bootloader
		system-frequency = <0>;		// from bootloader

		cdm@200 {
			compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
			reg = <200 38>;
		};

		mpc5200_pic: pic@500 {
			// 5200 interrupts are encoded into two levels;
			interrupt-controller;
			#interrupt-cells = <3>;
			compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
			reg = <500 80>;
		};

		timer@600 {	// General Purpose Timer
			compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
			reg = <600 10>;
			interrupts = <1 9 0>;
			interrupt-parent = <&mpc5200_pic>;
			fsl,has-wdt;
		};

		timer@610 {	// General Purpose Timer
			compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
			reg = <610 10>;
			interrupts = <1 a 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		timer@620 {	// General Purpose Timer
			compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
			reg = <620 10>;
			interrupts = <1 b 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		timer@630 {	// General Purpose Timer
			compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
			reg = <630 10>;
			interrupts = <1 c 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		timer@640 {	// General Purpose Timer
			compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
			reg = <640 10>;
			interrupts = <1 d 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		timer@650 {	// General Purpose Timer
			compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
			reg = <650 10>;
			interrupts = <1 e 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		timer@660 {	// General Purpose Timer
			compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
			reg = <660 10>;
			interrupts = <1 f 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		timer@670 {	// General Purpose Timer
			compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
			reg = <670 10>;
			interrupts = <1 10 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		rtc@800 {	// Real time clock
			compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
			reg = <800 100>;
			interrupts = <1 5 0 1 6 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		gpio@b00 {
			compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
			reg = <b00 40>;
			interrupts = <1 7 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		gpio@c00 {
			compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
			reg = <c00 40>;
			interrupts = <1 8 0 0 3 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		spi@f00 {
			compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
			reg = <f00 20>;
			interrupts = <2 d 0 2 e 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		usb@1000 {
			compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
			reg = <1000 ff>;
			interrupts = <2 6 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		dma-controller@1200 {
			compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
			reg = <1200 80>;
			interrupts = <3 0 0  3 1 0  3 2 0  3 3 0
			              3 4 0  3 5 0  3 6 0  3 7 0
			              3 8 0  3 9 0  3 a 0  3 b 0
			              3 c 0  3 d 0  3 e 0  3 f 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		xlb@1f00 {
			compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
			reg = <1f00 100>;
		};

		serial@2000 {		// PSC1
			device_type = "serial";
			compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
			port-number = <0>;  // Logical port assignment
			reg = <2000 100>;
			interrupts = <2 1 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		serial@2200 {		// PSC2
			device_type = "serial";
			compatible = "fsl,mpc5200-psc-uart";
			port-number = <1>;  // Logical port assignment
			reg = <2200 100>;
			interrupts = <2 2 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		serial@2400 {		// PSC3
			device_type = "serial";
			compatible = "fsl,mpc5200-psc-uart";
			port-number = <2>;  // Logical port assignment
			reg = <2400 100>;
			interrupts = <2 3 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		serial@2c00 {		// PSC6
			device_type = "serial";
			compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
			port-number = <5>;  // Logical port assignment
			reg = <2c00 100>;
			interrupts = <2 4 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		ethernet@3000 {
			device_type = "network";
			compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
			reg = <3000 400>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <2 5 0>;
			interrupt-parent = <&mpc5200_pic>;
			phy-handle = <&phy0>;
		};

		mdio@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
			reg = <3000 400>;       // fec range, since we need to setup fec interrupts
			interrupts = <2 5 0>;   // these are for "mii command finished", not link changes & co.
			interrupt-parent = <&mpc5200_pic>;

			phy0: ethernet-phy@0 {
				device_type = "ethernet-phy";
				reg = <0>;
			};
		};

		i2c@3d40 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
			reg = <3d40 40>;
			interrupts = <2 10 0>;
			interrupt-parent = <&mpc5200_pic>;
			fsl5200-clocking;
		};

		sram@8000 {
			compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
			reg = <8000 4000>;
		};
	};

	lpb {
		model = "fsl,lpb";
		compatible = "fsl,lpb";
		#address-cells = <2>;
		#size-cells = <1>;
		ranges = <0 0 fc000000 2000000>;

		// 16-bit flash device at LocalPlus Bus CS0
		flash@0,0 {
			compatible = "cfi-flash";
			reg = <0 0 2000000>;
			bank-width = <2>;
			device-width = <2>;
			#size-cells = <1>;
			#address-cells = <1>;
		};
	};
};
OpenPOWER on IntegriCloud