summaryrefslogtreecommitdiffstats
path: root/arch/mn10300/include/asm/spinlock.h
blob: 93429154e898e72c1f3e39a4e6ac71f8b7cc1ed5 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
/* MN10300 spinlock support
 *
 * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
 * Written by David Howells (dhowells@redhat.com)
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public Licence
 * as published by the Free Software Foundation; either version
 * 2 of the Licence, or (at your option) any later version.
 */
#ifndef _ASM_SPINLOCK_H
#define _ASM_SPINLOCK_H

#include <asm/atomic.h>
#include <asm/rwlock.h>
#include <asm/page.h>

/*
 * Simple spin lock operations.  There are two variants, one clears IRQ's
 * on the local processor, one does not.
 *
 * We make no fairness assumptions. They have a cost.
 */

#define arch_spin_is_locked(x)	(*(volatile signed char *)(&(x)->slock) != 0)
#define arch_spin_unlock_wait(x) do { barrier(); } while (arch_spin_is_locked(x))

static inline void arch_spin_unlock(arch_spinlock_t *lock)
{
	asm volatile(
		"	bclr	1,(0,%0)	\n"
		:
		: "a"(&lock->slock)
		: "memory", "cc");
}

static inline int arch_spin_trylock(arch_spinlock_t *lock)
{
	int ret;

	asm volatile(
		"	mov	1,%0		\n"
		"	bset	%0,(%1)		\n"
		"	bne	1f		\n"
		"	clr	%0		\n"
		"1:	xor	1,%0		\n"
		: "=d"(ret)
		: "a"(&lock->slock)
		: "memory", "cc");

	return ret;
}

static inline void arch_spin_lock(arch_spinlock_t *lock)
{
	asm volatile(
		"1:	bset	1,(0,%0)	\n"
		"	bne	1b		\n"
		:
		: "a"(&lock->slock)
		: "memory", "cc");
}

static inline void arch_spin_lock_flags(arch_spinlock_t *lock,
					 unsigned long flags)
{
	int temp;

	asm volatile(
		"1:	bset	1,(0,%2)	\n"
		"	beq	3f		\n"
		"	mov	%1,epsw		\n"
		"2:	mov	(0,%2),%0	\n"
		"	or	%0,%0		\n"
		"	bne	2b		\n"
		"	mov	%3,%0		\n"
		"	mov	%0,epsw		\n"
		"	nop			\n"
		"	nop			\n"
		"	bra	1b\n"
		"3:				\n"
		: "=&d" (temp)
		: "d" (flags), "a"(&lock->slock), "i"(EPSW_IE | MN10300_CLI_LEVEL)
		: "memory", "cc");
}

#ifdef __KERNEL__

/*
 * Read-write spinlocks, allowing multiple readers
 * but only one writer.
 *
 * NOTE! it is quite common to have readers in interrupts
 * but no interrupt writers. For those circumstances we
 * can "mix" irq-safe locks - any writer needs to get a
 * irq-safe write-lock, but readers can get non-irqsafe
 * read-locks.
 */

/**
 * read_can_lock - would read_trylock() succeed?
 * @lock: the rwlock in question.
 */
#define arch_read_can_lock(x) ((int)(x)->lock > 0)

/**
 * write_can_lock - would write_trylock() succeed?
 * @lock: the rwlock in question.
 */
#define arch_write_can_lock(x) ((x)->lock == RW_LOCK_BIAS)

/*
 * On mn10300, we implement read-write locks as a 32-bit counter
 * with the high bit (sign) being the "contended" bit.
 */
static inline void arch_read_lock(arch_rwlock_t *rw)
{
#if 0 //def CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT
	__build_read_lock(rw, "__read_lock_failed");
#else
	{
		atomic_t *count = (atomic_t *)rw;
		while (atomic_dec_return(count) < 0)
			atomic_inc(count);
	}
#endif
}

static inline void arch_write_lock(arch_rwlock_t *rw)
{
#if 0 //def CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT
	__build_write_lock(rw, "__write_lock_failed");
#else
	{
		atomic_t *count = (atomic_t *)rw;
		while (!atomic_sub_and_test(RW_LOCK_BIAS, count))
			atomic_add(RW_LOCK_BIAS, count);
	}
#endif
}

static inline void arch_read_unlock(arch_rwlock_t *rw)
{
#if 0 //def CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT
	__build_read_unlock(rw);
#else
	{
		atomic_t *count = (atomic_t *)rw;
		atomic_inc(count);
	}
#endif
}

static inline void arch_write_unlock(arch_rwlock_t *rw)
{
#if 0 //def CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT
	__build_write_unlock(rw);
#else
	{
		atomic_t *count = (atomic_t *)rw;
		atomic_add(RW_LOCK_BIAS, count);
	}
#endif
}

static inline int arch_read_trylock(arch_rwlock_t *lock)
{
	atomic_t *count = (atomic_t *)lock;
	atomic_dec(count);
	if (atomic_read(count) >= 0)
		return 1;
	atomic_inc(count);
	return 0;
}

static inline int arch_write_trylock(arch_rwlock_t *lock)
{
	atomic_t *count = (atomic_t *)lock;
	if (atomic_sub_and_test(RW_LOCK_BIAS, count))
		return 1;
	atomic_add(RW_LOCK_BIAS, count);
	return 0;
}

#define arch_read_lock_flags(lock, flags)  arch_read_lock(lock)
#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)

#define _raw_spin_relax(lock)	cpu_relax()
#define _raw_read_relax(lock)	cpu_relax()
#define _raw_write_relax(lock)	cpu_relax()

#endif /* __KERNEL__ */
#endif /* _ASM_SPINLOCK_H */
OpenPOWER on IntegriCloud