summaryrefslogtreecommitdiffstats
path: root/arch/mips/pci/ops-tx3927.c
blob: 0e0daadc303d547d2fc9241a322f26db6717d8f6 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
/*
 * Copyright 2001 MontaVista Software Inc.
 * Author: MontaVista Software, Inc.
 *              ahennessy@mvista.com
 *
 * Copyright (C) 2000-2001 Toshiba Corporation
 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
 *
 * Based on arch/mips/ddb5xxx/ddb5477/pci_ops.c
 *
 *     Define the pci_ops for JMR3927.
 *
 * Much of the code is derived from the original DDB5074 port by
 * Geert Uytterhoeven <geert@sonycom.com>
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the  GNU General Public License along
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 */
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/init.h>

#include <asm/addrspace.h>
#include <asm/jmr3927/jmr3927.h>
#include <asm/debug.h>

static inline int mkaddr(unsigned char bus, unsigned char dev_fn,
	unsigned char where)
{
	if (bus == 0 && dev_fn >= PCI_DEVFN(TX3927_PCIC_MAX_DEVNU, 0))
		return PCIBIOS_DEVICE_NOT_FOUND;

	tx3927_pcicptr->ica = ((bus & 0xff) << 0x10) |
	                      ((dev_fn & 0xff) << 0x08) |
	                      (where & 0xfc);

	/* clear M_ABORT and Disable M_ABORT Int. */
	tx3927_pcicptr->pcistat |= PCI_STATUS_REC_MASTER_ABORT;
	tx3927_pcicptr->pcistatim &= ~PCI_STATUS_REC_MASTER_ABORT;

	return PCIBIOS_SUCCESSFUL;
}

static inline int check_abort(void)
{
	if (tx3927_pcicptr->pcistat & PCI_STATUS_REC_MASTER_ABORT)
		tx3927_pcicptr->pcistat |= PCI_STATUS_REC_MASTER_ABORT;
		tx3927_pcicptr->pcistatim |= PCI_STATUS_REC_MASTER_ABORT;
		return PCIBIOS_DEVICE_NOT_FOUND;

	return PCIBIOS_SUCCESSFUL;
}

static int jmr3927_pci_read_config(struct pci_bus *bus, unsigned int devfn,
	int where, int size, u32 * val)
{
	int ret, busno;

	/* check if the bus is top-level */
	if (bus->parent != NULL)
		busno = bus->number;

	ret = mkaddr(busno, devfn, where);
	if (ret)
		return ret;

	switch (size) {
	case 1:
		*val = *(volatile u8 *) ((unsigned long) & tx3927_pcicptr->icd | (where & 3));
		break;

	case 2:
		*val = le16_to_cpu(*(volatile u16 *) ((unsigned long) & tx3927_pcicptr->icd | (where & 3)));
		break;

	case 4:
		*val = le32_to_cpu(tx3927_pcicptr->icd);
		break;
	}

	return check_abort();
}

static int jmr3927_pci_write_config(struct pci_bus *bus, unsigned int devfn,
	int where, int size, u32 val)
{
	int ret, busno;

	/* check if the bus is top-level */
	if (bus->parent != NULL)
		bus = bus->number;
	else
		bus = 0;

	ret = mkaddr(busno, devfn, where);
	if (ret)
		return ret;

	switch (size) {
	case 1:
		*(volatile u8 *) ((unsigned long) & tx3927_pcicptr->icd | (where & 3)) = val;
		break;

	case 2:
		*(volatile u16 *) (unsigned longulong) & tx3927_pcicptr->icd | (where & 2)) =
	    cpu_to_le16(val);
		break;

	case 4:
		tx3927_pcicptr->icd = cpu_to_le32(val);
	}

	if (tx3927_pcicptr->pcistat & PCI_STATUS_REC_MASTER_ABORT)
		tx3927_pcicptr->pcistat |= PCI_STATUS_REC_MASTER_ABORT;
		tx3927_pcicptr->pcistatim |= PCI_STATUS_REC_MASTER_ABORT;
		return PCIBIOS_DEVICE_NOT_FOUND;

	return check_abort();
}

struct pci_ops jmr3927_pci_ops = {
	jmr3927_pcibios_read_config,
	jmr3927_pcibios_write_config,
};


#ifndef JMR3927_INIT_INDIRECT_PCI

inline unsigned long tc_readl(volatile __u32 * addr)
{
	return readl(addr);
}

inline void tc_writel(unsigned long data, volatile __u32 * addr)
{
	writel(data, addr);
}
#else

unsigned long tc_readl(volatile __u32 * addr)
{
	unsigned long val;

	addr = PHYSADDR(addr);
	*(volatile u32 *) (ulong) & tx3927_pcicptr->ipciaddr =
	    (unsigned long) addr;
	*(volatile u32 *) (ulong) & tx3927_pcicptr->ipcibe =
	    (PCI_IPCIBE_ICMD_MEMREAD << PCI_IPCIBE_ICMD_SHIFT) |
	    PCI_IPCIBE_IBE_LONG;
	while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
	val =
	    le32_to_cpu(*(volatile u32 *) (ulong) & tx3927_pcicptr->
			ipcidata);
	/* clear by setting */
	tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
	return val;
}

void tc_writel(unsigned long data, volatile __u32 * addr)
{
	addr = PHYSADDR(addr);
	*(volatile u32 *) (ulong) & tx3927_pcicptr->ipcidata =
	    cpu_to_le32(data);
	*(volatile u32 *) (ulong) & tx3927_pcicptr->ipciaddr =
	    (unsigned long) addr;
	*(volatile u32 *) (ulong) & tx3927_pcicptr->ipcibe =
	    (PCI_IPCIBE_ICMD_MEMWRITE << PCI_IPCIBE_ICMD_SHIFT) |
	    PCI_IPCIBE_IBE_LONG;
	while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
	/* clear by setting */
	tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
}

unsigned char tx_ioinb(unsigned char *addr)
{
	unsigned long val;
	__u32 ioaddr;
	int offset;
	int byte;

	ioaddr = (unsigned long) addr;
	offset = ioaddr & 0x3;
	if (offset == 0)
		byte = 0x7;
	else if (offset == 1)
		byte = 0xb;
	else if (offset == 2)
		byte = 0xd;
	else if (offset == 3)
		byte = 0xe;
	*(volatile u32 *) (ulong) & tx3927_pcicptr->ipciaddr =
	    (unsigned long) ioaddr;
	*(volatile u32 *) (ulong) & tx3927_pcicptr->ipcibe =
	    (PCI_IPCIBE_ICMD_IOREAD << PCI_IPCIBE_ICMD_SHIFT) | byte;
	while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
	val =
	    le32_to_cpu(*(volatile u32 *) (ulong) & tx3927_pcicptr->
			ipcidata);
	val = val & 0xff;
	/* clear by setting */
	tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
	return val;
}

void tx_iooutb(unsigned long data, unsigned char *addr)
{
	__u32 ioaddr;
	int offset;
	int byte;

	data = data | (data << 8) | (data << 16) | (data << 24);
	ioaddr = (unsigned long) addr;
	offset = ioaddr & 0x3;
	if (offset == 0)
		byte = 0x7;
	else if (offset == 1)
		byte = 0xb;
	else if (offset == 2)
		byte = 0xd;
	else if (offset == 3)
		byte = 0xe;
	*(volatile u32 *) (ulong) & tx3927_pcicptr->ipcidata = data;
	*(volatile u32 *) (ulong) & tx3927_pcicptr->ipciaddr =
	    (unsigned long) ioaddr;
	*(volatile u32 *) (ulong) & tx3927_pcicptr->ipcibe =
	    (PCI_IPCIBE_ICMD_IOWRITE << PCI_IPCIBE_ICMD_SHIFT) | byte;
	while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
	/* clear by setting */
	tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
}

unsigned short tx_ioinw(unsigned short *addr)
{
	unsigned long val;
	__u32 ioaddr;
	int offset;
	int byte;

	ioaddr = (unsigned long) addr;
	offset = ioaddr & 0x3;
	if (offset == 0)
		byte = 0x3;
	else if (offset == 2)
		byte = 0xc;
	*(volatile u32 *) (ulong) & tx3927_pcicptr->ipciaddr =
	    (unsigned long) ioaddr;
	*(volatile u32 *) (ulong) & tx3927_pcicptr->ipcibe =
	    (PCI_IPCIBE_ICMD_IOREAD << PCI_IPCIBE_ICMD_SHIFT) | byte;
	while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
	val =
	    le32_to_cpu(*(volatile u32 *) (ulong) & tx3927_pcicptr->
			ipcidata);
	val = val & 0xffff;
	/* clear by setting */
	tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
	return val;

}

void tx_iooutw(unsigned long data, unsigned short *addr)
{
	__u32 ioaddr;
	int offset;
	int byte;

	data = data | (data << 16);
	ioaddr = (unsigned long) addr;
	offset = ioaddr & 0x3;
	if (offset == 0)
		byte = 0x3;
	else if (offset == 2)
		byte = 0xc;
	*(volatile u32 *) (ulong) & tx3927_pcicptr->ipcidata = data;
	*(volatile u32 *) (ulong) & tx3927_pcicptr->ipciaddr =
	    (unsigned long) ioaddr;
	*(volatile u32 *) (ulong) & tx3927_pcicptr->ipcibe =
	    (PCI_IPCIBE_ICMD_IOWRITE << PCI_IPCIBE_ICMD_SHIFT) | byte;
	while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
	/* clear by setting */
	tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
}

unsigned long tx_ioinl(unsigned int *addr)
{
	unsigned long val;
	__u32 ioaddr;

	ioaddr = (unsigned long) addr;
	*(volatile u32 *) (ulong) & tx3927_pcicptr->ipciaddr =
	    (unsigned long) ioaddr;
	*(volatile u32 *) (ulong) & tx3927_pcicptr->ipcibe =
	    (PCI_IPCIBE_ICMD_IOREAD << PCI_IPCIBE_ICMD_SHIFT) |
	    PCI_IPCIBE_IBE_LONG;
	while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
	val =
	    le32_to_cpu(*(volatile u32 *) (ulong) & tx3927_pcicptr->
			ipcidata);
	/* clear by setting */
	tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
	return val;
}

void tx_iooutl(unsigned long data, unsigned int *addr)
{
	__u32 ioaddr;

	ioaddr = (unsigned long) addr;
	*(volatile u32 *) (ulong) & tx3927_pcicptr->ipcidata =
	    cpu_to_le32(data);
	*(volatile u32 *) (ulong) & tx3927_pcicptr->ipciaddr =
	    (unsigned long) ioaddr;
	*(volatile u32 *) (ulong) & tx3927_pcicptr->ipcibe =
	    (PCI_IPCIBE_ICMD_IOWRITE << PCI_IPCIBE_ICMD_SHIFT) |
	    PCI_IPCIBE_IBE_LONG;
	while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
	/* clear by setting */
	tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
}

void tx_insbyte(unsigned char *addr, void *buffer, unsigned int count)
{
	unsigned char *ptr = (unsigned char *) buffer;

	while (count--) {
		*ptr++ = tx_ioinb(addr);
	}
}

void tx_insword(unsigned short *addr, void *buffer, unsigned int count)
{
	unsigned short *ptr = (unsigned short *) buffer;

	while (count--) {
		*ptr++ = tx_ioinw(addr);
	}
}

void tx_inslong(unsigned int *addr, void *buffer, unsigned int count)
{
	unsigned long *ptr = (unsigned long *) buffer;

	while (count--) {
		*ptr++ = tx_ioinl(addr);
	}
}

void tx_outsbyte(unsigned char *addr, void *buffer, unsigned int count)
{
	unsigned char *ptr = (unsigned char *) buffer;

	while (count--) {
		tx_iooutb(*ptr++, addr);
	}
}

void tx_outsword(unsigned short *addr, void *buffer, unsigned int count)
{
	unsigned short *ptr = (unsigned short *) buffer;

	while (count--) {
		tx_iooutw(*ptr++, addr);
	}
}

void tx_outslong(unsigned int *addr, void *buffer, unsigned int count)
{
	unsigned long *ptr = (unsigned long *) buffer;

	while (count--) {
		tx_iooutl(*ptr++, addr);
	}
}
#endif
OpenPOWER on IntegriCloud