1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
|
/*
* Setup pointers to hardware dependent routines.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1996, 1997, 2004, 05 by Ralf Baechle (ralf@linux-mips.org)
* Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv)
*
*/
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/pm.h>
#include <asm/bootinfo.h>
#include <asm/time.h>
#include <asm/i8253.h>
#include <asm/io.h>
#include <asm/reboot.h>
#include <asm/gt64120.h>
#include <cobalt.h>
#include <irq.h>
extern void cobalt_machine_restart(char *command);
extern void cobalt_machine_halt(void);
const char *get_system_type(void)
{
switch (cobalt_board_id) {
case COBALT_BRD_ID_QUBE1:
return "Cobalt Qube";
case COBALT_BRD_ID_RAQ1:
return "Cobalt RaQ";
case COBALT_BRD_ID_QUBE2:
return "Cobalt Qube2";
case COBALT_BRD_ID_RAQ2:
return "Cobalt RaQ2";
}
return "MIPS Cobalt";
}
void __init plat_timer_setup(struct irqaction *irq)
{
/* Load timer value for HZ (TCLK is 50MHz) */
GT_WRITE(GT_TC0_OFS, 50*1000*1000 / HZ);
/* Enable timer0 */
GT_WRITE(GT_TC_CONTROL_OFS, GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK);
setup_irq(GT641XX_TIMER0_IRQ, irq);
}
/*
* Cobalt doesn't have PS/2 keyboard/mouse interfaces,
* keyboard conntroller is never used.
* Also PCI-ISA bridge DMA contoroller is never used.
*/
static struct resource cobalt_reserved_resources[] = {
{ /* dma1 */
.start = 0x00,
.end = 0x1f,
.name = "reserved",
.flags = IORESOURCE_BUSY | IORESOURCE_IO,
},
{ /* keyboard */
.start = 0x60,
.end = 0x6f,
.name = "reserved",
.flags = IORESOURCE_BUSY | IORESOURCE_IO,
},
{ /* dma page reg */
.start = 0x80,
.end = 0x8f,
.name = "reserved",
.flags = IORESOURCE_BUSY | IORESOURCE_IO,
},
{ /* dma2 */
.start = 0xc0,
.end = 0xdf,
.name = "reserved",
.flags = IORESOURCE_BUSY | IORESOURCE_IO,
},
};
void __init plat_time_init(void)
{
setup_pit_timer();
}
void __init plat_mem_setup(void)
{
int i;
_machine_restart = cobalt_machine_restart;
_machine_halt = cobalt_machine_halt;
pm_power_off = cobalt_machine_halt;
set_io_port_base(CKSEG1ADDR(GT_DEF_PCI0_IO_BASE));
/* I/O port resource must include LCD/buttons */
ioport_resource.end = 0x0fffffff;
/* These resources have been reserved by VIA SuperI/O chip. */
for (i = 0; i < ARRAY_SIZE(cobalt_reserved_resources); i++)
request_resource(&ioport_resource, cobalt_reserved_resources + i);
}
/*
* Prom init. We read our one and only communication with the firmware.
* Grab the amount of installed memory.
* Better boot loaders (CoLo) pass a command line too :-)
*/
void __init prom_init(void)
{
int narg, indx, posn, nchr;
unsigned long memsz;
char **argv;
memsz = fw_arg0 & 0x7fff0000;
narg = fw_arg0 & 0x0000ffff;
if (narg) {
arcs_cmdline[0] = '\0';
argv = (char **) fw_arg1;
posn = 0;
for (indx = 1; indx < narg; ++indx) {
nchr = strlen(argv[indx]);
if (posn + 1 + nchr + 1 > sizeof(arcs_cmdline))
break;
if (posn)
arcs_cmdline[posn++] = ' ';
strcpy(arcs_cmdline + posn, argv[indx]);
posn += nchr;
}
}
add_memory_region(0x0, memsz, BOOT_MEM_RAM);
}
void __init prom_free_prom_memory(void)
{
/* Nothing to do! */
}
|
