summaryrefslogtreecommitdiffstats
path: root/arch/c6x/platforms/plldata.c
blob: 755359eb628622ffd60d2bdd6ebb3a060159620b (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
/*
 *  Port on Texas Instruments TMS320C6x architecture
 *
 *  Copyright (C) 2011 Texas Instruments Incorporated
 *  Author: Mark Salter <msalter@redhat.com>
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License version 2 as
 *  published by the Free Software Foundation.
 */
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/ioport.h>
#include <linux/clkdev.h>
#include <linux/of.h>
#include <linux/of_address.h>

#include <asm/clock.h>
#include <asm/setup.h>
#include <asm/irq.h>

/*
 * Common SoC clock support.
 */

/* Default input for PLL1 */
struct clk clkin1 = {
	.name = "clkin1",
	.node = LIST_HEAD_INIT(clkin1.node),
	.children = LIST_HEAD_INIT(clkin1.children),
	.childnode = LIST_HEAD_INIT(clkin1.childnode),
};

struct pll_data c6x_soc_pll1 = {
	.num	   = 1,
	.sysclks   = {
		{
			.name = "pll1",
			.parent = &clkin1,
			.pll_data = &c6x_soc_pll1,
			.flags = CLK_PLL,
		},
		{
			.name = "pll1_sysclk1",
			.parent = &c6x_soc_pll1.sysclks[0],
			.flags = CLK_PLL,
		},
		{
			.name = "pll1_sysclk2",
			.parent = &c6x_soc_pll1.sysclks[0],
			.flags = CLK_PLL,
		},
		{
			.name = "pll1_sysclk3",
			.parent = &c6x_soc_pll1.sysclks[0],
			.flags = CLK_PLL,
		},
		{
			.name = "pll1_sysclk4",
			.parent = &c6x_soc_pll1.sysclks[0],
			.flags = CLK_PLL,
		},
		{
			.name = "pll1_sysclk5",
			.parent = &c6x_soc_pll1.sysclks[0],
			.flags = CLK_PLL,
		},
		{
			.name = "pll1_sysclk6",
			.parent = &c6x_soc_pll1.sysclks[0],
			.flags = CLK_PLL,
		},
		{
			.name = "pll1_sysclk7",
			.parent = &c6x_soc_pll1.sysclks[0],
			.flags = CLK_PLL,
		},
		{
			.name = "pll1_sysclk8",
			.parent = &c6x_soc_pll1.sysclks[0],
			.flags = CLK_PLL,
		},
		{
			.name = "pll1_sysclk9",
			.parent = &c6x_soc_pll1.sysclks[0],
			.flags = CLK_PLL,
		},
		{
			.name = "pll1_sysclk10",
			.parent = &c6x_soc_pll1.sysclks[0],
			.flags = CLK_PLL,
		},
		{
			.name = "pll1_sysclk11",
			.parent = &c6x_soc_pll1.sysclks[0],
			.flags = CLK_PLL,
		},
		{
			.name = "pll1_sysclk12",
			.parent = &c6x_soc_pll1.sysclks[0],
			.flags = CLK_PLL,
		},
		{
			.name = "pll1_sysclk13",
			.parent = &c6x_soc_pll1.sysclks[0],
			.flags = CLK_PLL,
		},
		{
			.name = "pll1_sysclk14",
			.parent = &c6x_soc_pll1.sysclks[0],
			.flags = CLK_PLL,
		},
		{
			.name = "pll1_sysclk15",
			.parent = &c6x_soc_pll1.sysclks[0],
			.flags = CLK_PLL,
		},
		{
			.name = "pll1_sysclk16",
			.parent = &c6x_soc_pll1.sysclks[0],
			.flags = CLK_PLL,
		},
	},
};

/* CPU core clock */
struct clk c6x_core_clk = {
	.name = "core",
};

/* miscellaneous IO clocks */
struct clk c6x_i2c_clk = {
	.name = "i2c",
};

struct clk c6x_watchdog_clk = {
	.name = "watchdog",
};

struct clk c6x_mcbsp1_clk = {
	.name = "mcbsp1",
};

struct clk c6x_mcbsp2_clk = {
	.name = "mcbsp2",
};

struct clk c6x_mdio_clk = {
	.name = "mdio",
};


#ifdef CONFIG_SOC_TMS320C6455
static struct clk_lookup c6455_clks[] = {
	CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),
	CLK(NULL, "pll1_sysclk2", &c6x_soc_pll1.sysclks[2]),
	CLK(NULL, "pll1_sysclk3", &c6x_soc_pll1.sysclks[3]),
	CLK(NULL, "pll1_sysclk4", &c6x_soc_pll1.sysclks[4]),
	CLK(NULL, "pll1_sysclk5", &c6x_soc_pll1.sysclks[5]),
	CLK(NULL, "core", &c6x_core_clk),
	CLK("i2c_davinci.1", NULL, &c6x_i2c_clk),
	CLK("watchdog", NULL, &c6x_watchdog_clk),
	CLK("2c81800.mdio", NULL, &c6x_mdio_clk),
	CLK("", NULL, NULL)
};


static void __init c6455_setup_clocks(struct device_node *node)
{
	struct pll_data *pll = &c6x_soc_pll1;
	struct clk *sysclks = pll->sysclks;

	pll->flags = PLL_HAS_PRE | PLL_HAS_MUL;

	sysclks[2].flags |= FIXED_DIV_PLL;
	sysclks[2].div = 3;
	sysclks[3].flags |= FIXED_DIV_PLL;
	sysclks[3].div = 6;
	sysclks[4].div = PLLDIV4;
	sysclks[5].div = PLLDIV5;

	c6x_core_clk.parent = &sysclks[0];
	c6x_i2c_clk.parent = &sysclks[3];
	c6x_watchdog_clk.parent = &sysclks[3];
	c6x_mdio_clk.parent = &sysclks[3];

	c6x_clks_init(c6455_clks);
}
#endif /* CONFIG_SOC_TMS320C6455 */

#ifdef CONFIG_SOC_TMS320C6457
static struct clk_lookup c6457_clks[] = {
	CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),
	CLK(NULL, "pll1_sysclk1", &c6x_soc_pll1.sysclks[1]),
	CLK(NULL, "pll1_sysclk2", &c6x_soc_pll1.sysclks[2]),
	CLK(NULL, "pll1_sysclk3", &c6x_soc_pll1.sysclks[3]),
	CLK(NULL, "pll1_sysclk4", &c6x_soc_pll1.sysclks[4]),
	CLK(NULL, "pll1_sysclk5", &c6x_soc_pll1.sysclks[5]),
	CLK(NULL, "core", &c6x_core_clk),
	CLK("i2c_davinci.1", NULL, &c6x_i2c_clk),
	CLK("watchdog", NULL, &c6x_watchdog_clk),
	CLK("2c81800.mdio", NULL, &c6x_mdio_clk),
	CLK("", NULL, NULL)
};

static void __init c6457_setup_clocks(struct device_node *node)
{
	struct pll_data *pll = &c6x_soc_pll1;
	struct clk *sysclks = pll->sysclks;

	pll->flags = PLL_HAS_MUL | PLL_HAS_POST;

	sysclks[1].flags |= FIXED_DIV_PLL;
	sysclks[1].div = 1;
	sysclks[2].flags |= FIXED_DIV_PLL;
	sysclks[2].div = 3;
	sysclks[3].flags |= FIXED_DIV_PLL;
	sysclks[3].div = 6;
	sysclks[4].div = PLLDIV4;
	sysclks[5].div = PLLDIV5;

	c6x_core_clk.parent = &sysclks[1];
	c6x_i2c_clk.parent = &sysclks[3];
	c6x_watchdog_clk.parent = &sysclks[5];
	c6x_mdio_clk.parent = &sysclks[5];

	c6x_clks_init(c6457_clks);
}
#endif /* CONFIG_SOC_TMS320C6455 */

#ifdef CONFIG_SOC_TMS320C6472
static struct clk_lookup c6472_clks[] = {
	CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),
	CLK(NULL, "pll1_sysclk1", &c6x_soc_pll1.sysclks[1]),
	CLK(NULL, "pll1_sysclk2", &c6x_soc_pll1.sysclks[2]),
	CLK(NULL, "pll1_sysclk3", &c6x_soc_pll1.sysclks[3]),
	CLK(NULL, "pll1_sysclk4", &c6x_soc_pll1.sysclks[4]),
	CLK(NULL, "pll1_sysclk5", &c6x_soc_pll1.sysclks[5]),
	CLK(NULL, "pll1_sysclk6", &c6x_soc_pll1.sysclks[6]),
	CLK(NULL, "pll1_sysclk7", &c6x_soc_pll1.sysclks[7]),
	CLK(NULL, "pll1_sysclk8", &c6x_soc_pll1.sysclks[8]),
	CLK(NULL, "pll1_sysclk9", &c6x_soc_pll1.sysclks[9]),
	CLK(NULL, "pll1_sysclk10", &c6x_soc_pll1.sysclks[10]),
	CLK(NULL, "core", &c6x_core_clk),
	CLK("i2c_davinci.1", NULL, &c6x_i2c_clk),
	CLK("watchdog", NULL, &c6x_watchdog_clk),
	CLK("2c81800.mdio", NULL, &c6x_mdio_clk),
	CLK("", NULL, NULL)
};

/* assumptions used for delay loop calculations */
#define MIN_CLKIN1_KHz 15625
#define MAX_CORE_KHz   700000
#define MIN_PLLOUT_KHz MIN_CLKIN1_KHz

static void __init c6472_setup_clocks(struct device_node *node)
{
	struct pll_data *pll = &c6x_soc_pll1;
	struct clk *sysclks = pll->sysclks;
	int i;

	pll->flags = PLL_HAS_MUL;

	for (i = 1; i <= 6; i++) {
		sysclks[i].flags |= FIXED_DIV_PLL;
		sysclks[i].div = 1;
	}

	sysclks[7].flags |= FIXED_DIV_PLL;
	sysclks[7].div = 3;
	sysclks[8].flags |= FIXED_DIV_PLL;
	sysclks[8].div = 6;
	sysclks[9].flags |= FIXED_DIV_PLL;
	sysclks[9].div = 2;
	sysclks[10].div = PLLDIV10;

	c6x_core_clk.parent = &sysclks[get_coreid() + 1];
	c6x_i2c_clk.parent = &sysclks[8];
	c6x_watchdog_clk.parent = &sysclks[8];
	c6x_mdio_clk.parent = &sysclks[5];

	c6x_clks_init(c6472_clks);
}
#endif /* CONFIG_SOC_TMS320C6472 */


#ifdef CONFIG_SOC_TMS320C6474
static struct clk_lookup c6474_clks[] = {
	CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),
	CLK(NULL, "pll1_sysclk7", &c6x_soc_pll1.sysclks[7]),
	CLK(NULL, "pll1_sysclk9", &c6x_soc_pll1.sysclks[9]),
	CLK(NULL, "pll1_sysclk10", &c6x_soc_pll1.sysclks[10]),
	CLK(NULL, "pll1_sysclk11", &c6x_soc_pll1.sysclks[11]),
	CLK(NULL, "pll1_sysclk12", &c6x_soc_pll1.sysclks[12]),
	CLK(NULL, "pll1_sysclk13", &c6x_soc_pll1.sysclks[13]),
	CLK(NULL, "core", &c6x_core_clk),
	CLK("i2c_davinci.1", NULL, &c6x_i2c_clk),
	CLK("mcbsp.1", NULL, &c6x_mcbsp1_clk),
	CLK("mcbsp.2", NULL, &c6x_mcbsp2_clk),
	CLK("watchdog", NULL, &c6x_watchdog_clk),
	CLK("2c81800.mdio", NULL, &c6x_mdio_clk),
	CLK("", NULL, NULL)
};

static void __init c6474_setup_clocks(struct device_node *node)
{
	struct pll_data *pll = &c6x_soc_pll1;
	struct clk *sysclks = pll->sysclks;

	pll->flags = PLL_HAS_MUL;

	sysclks[7].flags |= FIXED_DIV_PLL;
	sysclks[7].div = 1;
	sysclks[9].flags |= FIXED_DIV_PLL;
	sysclks[9].div = 3;
	sysclks[10].flags |= FIXED_DIV_PLL;
	sysclks[10].div = 6;

	sysclks[11].div = PLLDIV11;

	sysclks[12].flags |= FIXED_DIV_PLL;
	sysclks[12].div = 2;

	sysclks[13].div = PLLDIV13;

	c6x_core_clk.parent = &sysclks[7];
	c6x_i2c_clk.parent = &sysclks[10];
	c6x_watchdog_clk.parent = &sysclks[10];
	c6x_mcbsp1_clk.parent = &sysclks[10];
	c6x_mcbsp2_clk.parent = &sysclks[10];

	c6x_clks_init(c6474_clks);
}
#endif /* CONFIG_SOC_TMS320C6474 */

#ifdef CONFIG_SOC_TMS320C6678
static struct clk_lookup c6678_clks[] = {
	CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),
	CLK(NULL, "pll1_refclk", &c6x_soc_pll1.sysclks[1]),
	CLK(NULL, "pll1_sysclk2", &c6x_soc_pll1.sysclks[2]),
	CLK(NULL, "pll1_sysclk3", &c6x_soc_pll1.sysclks[3]),
	CLK(NULL, "pll1_sysclk4", &c6x_soc_pll1.sysclks[4]),
	CLK(NULL, "pll1_sysclk5", &c6x_soc_pll1.sysclks[5]),
	CLK(NULL, "pll1_sysclk6", &c6x_soc_pll1.sysclks[6]),
	CLK(NULL, "pll1_sysclk7", &c6x_soc_pll1.sysclks[7]),
	CLK(NULL, "pll1_sysclk8", &c6x_soc_pll1.sysclks[8]),
	CLK(NULL, "pll1_sysclk9", &c6x_soc_pll1.sysclks[9]),
	CLK(NULL, "pll1_sysclk10", &c6x_soc_pll1.sysclks[10]),
	CLK(NULL, "pll1_sysclk11", &c6x_soc_pll1.sysclks[11]),
	CLK(NULL, "core", &c6x_core_clk),
	CLK("", NULL, NULL)
};

static void __init c6678_setup_clocks(struct device_node *node)
{
	struct pll_data *pll = &c6x_soc_pll1;
	struct clk *sysclks = pll->sysclks;

	pll->flags = PLL_HAS_MUL;

	sysclks[1].flags |= FIXED_DIV_PLL;
	sysclks[1].div = 1;

	sysclks[2].div = PLLDIV2;

	sysclks[3].flags |= FIXED_DIV_PLL;
	sysclks[3].div = 2;

	sysclks[4].flags |= FIXED_DIV_PLL;
	sysclks[4].div = 3;

	sysclks[5].div = PLLDIV5;

	sysclks[6].flags |= FIXED_DIV_PLL;
	sysclks[6].div = 64;

	sysclks[7].flags |= FIXED_DIV_PLL;
	sysclks[7].div = 6;

	sysclks[8].div = PLLDIV8;

	sysclks[9].flags |= FIXED_DIV_PLL;
	sysclks[9].div = 12;

	sysclks[10].flags |= FIXED_DIV_PLL;
	sysclks[10].div = 3;

	sysclks[11].flags |= FIXED_DIV_PLL;
	sysclks[11].div = 6;

	c6x_core_clk.parent = &sysclks[0];
	c6x_i2c_clk.parent = &sysclks[7];

	c6x_clks_init(c6678_clks);
}
#endif /* CONFIG_SOC_TMS320C6678 */

static struct of_device_id c6x_clkc_match[] __initdata = {
#ifdef CONFIG_SOC_TMS320C6455
	{ .compatible = "ti,c6455-pll", .data = c6455_setup_clocks },
#endif
#ifdef CONFIG_SOC_TMS320C6457
	{ .compatible = "ti,c6457-pll", .data = c6457_setup_clocks },
#endif
#ifdef CONFIG_SOC_TMS320C6472
	{ .compatible = "ti,c6472-pll", .data = c6472_setup_clocks },
#endif
#ifdef CONFIG_SOC_TMS320C6474
	{ .compatible = "ti,c6474-pll", .data = c6474_setup_clocks },
#endif
#ifdef CONFIG_SOC_TMS320C6678
	{ .compatible = "ti,c6678-pll", .data = c6678_setup_clocks },
#endif
	{ .compatible = "ti,c64x+pll" },
	{}
};

void __init c64x_setup_clocks(void)
{
	void (*__setup_clocks)(struct device_node *np);
	struct pll_data *pll = &c6x_soc_pll1;
	struct device_node *node;
	const struct of_device_id *id;
	int err;
	u32 val;

	node = of_find_matching_node(NULL, c6x_clkc_match);
	if (!node)
		return;

	pll->base = of_iomap(node, 0);
	if (!pll->base)
		goto out;

	err = of_property_read_u32(node, "clock-frequency", &val);
	if (err || val == 0) {
		pr_err("%s: no clock-frequency found! Using %dMHz\n",
		       node->full_name, (int)val / 1000000);
		val = 25000000;
	}
	clkin1.rate = val;

	err = of_property_read_u32(node, "ti,c64x+pll-bypass-delay", &val);
	if (err)
		val = 5000;
	pll->bypass_delay = val;

	err = of_property_read_u32(node, "ti,c64x+pll-reset-delay", &val);
	if (err)
		val = 30000;
	pll->reset_delay = val;

	err = of_property_read_u32(node, "ti,c64x+pll-lock-delay", &val);
	if (err)
		val = 30000;
	pll->lock_delay = val;

	/* id->data is a pointer to SoC-specific setup */
	id = of_match_node(c6x_clkc_match, node);
	if (id && id->data) {
		__setup_clocks = id->data;
		__setup_clocks(node);
	}

out:
	of_node_put(node);
}
OpenPOWER on IntegriCloud