summaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-mmp/include/mach/irqs.h
blob: 02701196ea0336694d9cd0f14a6d2256b470f5e3 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
#ifndef __ASM_MACH_IRQS_H
#define __ASM_MACH_IRQS_H

/*
 * Interrupt numbers for PXA168
 */
#define IRQ_PXA168_NONE			(-1)
#define IRQ_PXA168_SSP3			0
#define IRQ_PXA168_SSP2			1
#define IRQ_PXA168_SSP1			2
#define IRQ_PXA168_SSP0			3
#define IRQ_PXA168_PMIC_INT		4
#define IRQ_PXA168_RTC_INT		5
#define IRQ_PXA168_RTC_ALARM		6
#define IRQ_PXA168_TWSI0		7
#define IRQ_PXA168_GPU			8
#define IRQ_PXA168_KEYPAD		9
#define IRQ_PXA168_ONEWIRE		12
#define IRQ_PXA168_TIMER1		13
#define IRQ_PXA168_TIMER2		14
#define IRQ_PXA168_TIMER3		15
#define IRQ_PXA168_CMU			16
#define IRQ_PXA168_SSP4			17
#define IRQ_PXA168_MSP_WAKEUP		19
#define IRQ_PXA168_CF_WAKEUP		20
#define IRQ_PXA168_XD_WAKEUP		21
#define IRQ_PXA168_MFU			22
#define IRQ_PXA168_MSP			23
#define IRQ_PXA168_CF			24
#define IRQ_PXA168_XD			25
#define IRQ_PXA168_DDR_INT		26
#define IRQ_PXA168_UART1		27
#define IRQ_PXA168_UART2		28
#define IRQ_PXA168_UART3		29
#define IRQ_PXA168_WDT			35
#define IRQ_PXA168_MAIN_PMU		36
#define IRQ_PXA168_FRQ_CHANGE		38
#define IRQ_PXA168_SDH1			39
#define IRQ_PXA168_SDH2			40
#define IRQ_PXA168_LCD			41
#define IRQ_PXA168_CI			42
#define IRQ_PXA168_USB1			44
#define IRQ_PXA168_NAND			45
#define IRQ_PXA168_HIFI_DMA		46
#define IRQ_PXA168_DMA_INT0		47
#define IRQ_PXA168_DMA_INT1		48
#define IRQ_PXA168_GPIOX		49
#define IRQ_PXA168_USB2			51
#define IRQ_PXA168_AC97			57
#define IRQ_PXA168_TWSI1		58
#define IRQ_PXA168_AP_PMU		60
#define IRQ_PXA168_SM_INT		63

/*
 * Interrupt numbers for PXA910
 */
#define IRQ_PXA910_NONE			(-1)
#define IRQ_PXA910_AIRQ			0
#define IRQ_PXA910_SSP3			1
#define IRQ_PXA910_SSP2			2
#define IRQ_PXA910_SSP1			3
#define IRQ_PXA910_PMIC_INT		4
#define IRQ_PXA910_RTC_INT		5
#define IRQ_PXA910_RTC_ALARM		6
#define IRQ_PXA910_TWSI0		7
#define IRQ_PXA910_GPU			8
#define IRQ_PXA910_KEYPAD		9
#define IRQ_PXA910_ROTARY		10
#define IRQ_PXA910_TRACKBALL		11
#define IRQ_PXA910_ONEWIRE		12
#define IRQ_PXA910_AP1_TIMER1		13
#define IRQ_PXA910_AP1_TIMER2		14
#define IRQ_PXA910_AP1_TIMER3		15
#define IRQ_PXA910_IPC_AP0		16
#define IRQ_PXA910_IPC_AP1		17
#define IRQ_PXA910_IPC_AP2		18
#define IRQ_PXA910_IPC_AP3		19
#define IRQ_PXA910_IPC_AP4		20
#define IRQ_PXA910_IPC_CP0		21
#define IRQ_PXA910_IPC_CP1		22
#define IRQ_PXA910_IPC_CP2		23
#define IRQ_PXA910_IPC_CP3		24
#define IRQ_PXA910_IPC_CP4		25
#define IRQ_PXA910_L2_DDR		26
#define IRQ_PXA910_UART2		27
#define IRQ_PXA910_UART3		28
#define IRQ_PXA910_AP2_TIMER1		29
#define IRQ_PXA910_AP2_TIMER2		30
#define IRQ_PXA910_CP2_TIMER1		31
#define IRQ_PXA910_CP2_TIMER2		32
#define IRQ_PXA910_CP2_TIMER3		33
#define IRQ_PXA910_GSSP			34
#define IRQ_PXA910_CP2_WDT		35
#define IRQ_PXA910_MAIN_PMU		36
#define IRQ_PXA910_CP_FREQ_CHG		37
#define IRQ_PXA910_AP_FREQ_CHG		38
#define IRQ_PXA910_MMC			39
#define IRQ_PXA910_AEU			40
#define IRQ_PXA910_LCD			41
#define IRQ_PXA910_CCIC			42
#define IRQ_PXA910_IRE			43
#define IRQ_PXA910_USB1			44
#define IRQ_PXA910_NAND			45
#define IRQ_PXA910_HIFI_DMA		46
#define IRQ_PXA910_DMA_INT0		47
#define IRQ_PXA910_DMA_INT1		48
#define IRQ_PXA910_AP_GPIO		49
#define IRQ_PXA910_AP2_TIMER3		50
#define IRQ_PXA910_USB2			51
#define IRQ_PXA910_TWSI1		54
#define IRQ_PXA910_CP_GPIO		55
#define IRQ_PXA910_UART1		59	/* Slow UART */
#define IRQ_PXA910_AP_PMU		60
#define IRQ_PXA910_SM_INT		63	/* from PinMux */

/*
 * Interrupt numbers for MMP2
 */
#define IRQ_MMP2_NONE			(-1)
#define IRQ_MMP2_SSP1			0
#define IRQ_MMP2_SSP2			1
#define IRQ_MMP2_SSPA1			2
#define IRQ_MMP2_SSPA2			3
#define IRQ_MMP2_PMIC_MUX		4	/* PMIC & Charger */
#define IRQ_MMP2_RTC_MUX		5
#define IRQ_MMP2_TWSI1			7
#define IRQ_MMP2_GPU			8
#define IRQ_MMP2_KEYPAD			9
#define IRQ_MMP2_ROTARY			10
#define IRQ_MMP2_TRACKBALL		11
#define IRQ_MMP2_ONEWIRE		12
#define IRQ_MMP2_TIMER1			13
#define IRQ_MMP2_TIMER2			14
#define IRQ_MMP2_TIMER3			15
#define IRQ_MMP2_RIPC			16
#define IRQ_MMP2_TWSI_MUX		17	/* TWSI2 ~ TWSI6 */
#define IRQ_MMP2_HDMI			19
#define IRQ_MMP2_SSP3			20
#define IRQ_MMP2_SSP4			21
#define IRQ_MMP2_USB_HS1		22
#define IRQ_MMP2_USB_HS2		23
#define IRQ_MMP2_UART3			24
#define IRQ_MMP2_UART1			27
#define IRQ_MMP2_UART2			28
#define IRQ_MMP2_MIPI_DSI		29
#define IRQ_MMP2_CI2			30
#define IRQ_MMP2_PMU_TIMER1		31
#define IRQ_MMP2_PMU_TIMER2		32
#define IRQ_MMP2_PMU_TIMER3		33
#define IRQ_MMP2_USB_FS			34
#define IRQ_MMP2_MISC_MUX		35
#define IRQ_MMP2_WDT1			36
#define IRQ_MMP2_NAND_DMA		37
#define IRQ_MMP2_USIM			38
#define IRQ_MMP2_MMC			39
#define IRQ_MMP2_WTM			40
#define IRQ_MMP2_LCD			41
#define IRQ_MMP2_CI			42
#define IRQ_MMP2_IRE			43
#define IRQ_MMP2_USB_OTG		44
#define IRQ_MMP2_NAND			45
#define IRQ_MMP2_UART4			46
#define IRQ_MMP2_DMA_FIQ		47
#define IRQ_MMP2_DMA_RIQ		48
#define IRQ_MMP2_GPIO			49
#define IRQ_MMP2_SSP_MUX		51
#define IRQ_MMP2_MMC2			52
#define IRQ_MMP2_MMC3			53
#define IRQ_MMP2_MMC4			54
#define IRQ_MMP2_MIPI_HSI		55
#define IRQ_MMP2_MSP			58
#define IRQ_MMP2_MIPI_SLIM_DMA		59
#define IRQ_MMP2_PJ4_FREQ_CHG		60
#define IRQ_MMP2_MIPI_SLIM		62
#define IRQ_MMP2_SM			63

#define IRQ_MMP2_MUX_BASE		64

/* secondary interrupt of INT #4 */
#define IRQ_MMP2_PMIC_BASE		(IRQ_MMP2_MUX_BASE)
#define IRQ_MMP2_CHARGER		(IRQ_MMP2_PMIC_BASE + 0)
#define IRQ_MMP2_PMIC			(IRQ_MMP2_PMIC_BASE + 1)

/* secondary interrupt of INT #5 */
#define IRQ_MMP2_RTC_BASE		(IRQ_MMP2_PMIC_BASE + 2)
#define IRQ_MMP2_RTC_ALARM		(IRQ_MMP2_RTC_BASE + 0)
#define IRQ_MMP2_RTC			(IRQ_MMP2_RTC_BASE + 1)

/* secondary interrupt of INT #17 */
#define IRQ_MMP2_TWSI_BASE		(IRQ_MMP2_RTC_BASE + 2)
#define IRQ_MMP2_TWSI2			(IRQ_MMP2_TWSI_BASE + 0)
#define IRQ_MMP2_TWSI3			(IRQ_MMP2_TWSI_BASE + 1)
#define IRQ_MMP2_TWSI4			(IRQ_MMP2_TWSI_BASE + 2)
#define IRQ_MMP2_TWSI5			(IRQ_MMP2_TWSI_BASE + 3)
#define IRQ_MMP2_TWSI6			(IRQ_MMP2_TWSI_BASE + 4)

/* secondary interrupt of INT #35 */
#define IRQ_MMP2_MISC_BASE		(IRQ_MMP2_TWSI_BASE + 5)
#define IRQ_MMP2_PERF			(IRQ_MMP2_MISC_BASE + 0)
#define IRQ_MMP2_L2_PA_ECC		(IRQ_MMP2_MISC_BASE + 1)
#define IRQ_MMP2_L2_ECC			(IRQ_MMP2_MISC_BASE + 2)
#define IRQ_MMP2_L2_UECC		(IRQ_MMP2_MISC_BASE + 3)
#define IRQ_MMP2_DDR			(IRQ_MMP2_MISC_BASE + 4)
#define IRQ_MMP2_FAB0_TIMEOUT		(IRQ_MMP2_MISC_BASE + 5)
#define IRQ_MMP2_FAB1_TIMEOUT		(IRQ_MMP2_MISC_BASE + 6)
#define IRQ_MMP2_FAB2_TIMEOUT		(IRQ_MMP2_MISC_BASE + 7)
#define IRQ_MMP2_THERMAL		(IRQ_MMP2_MISC_BASE + 9)
#define IRQ_MMP2_MAIN_PMU		(IRQ_MMP2_MISC_BASE + 10)
#define IRQ_MMP2_WDT2			(IRQ_MMP2_MISC_BASE + 11)
#define IRQ_MMP2_CORESIGHT		(IRQ_MMP2_MISC_BASE + 12)
#define IRQ_MMP2_COMMTX			(IRQ_MMP2_MISC_BASE + 13)
#define IRQ_MMP2_COMMRX			(IRQ_MMP2_MISC_BASE + 14)

/* secondary interrupt of INT #51 */
#define IRQ_MMP2_SSP_BASE		(IRQ_MMP2_MISC_BASE + 15)
#define IRQ_MMP2_SSP1_SRDY		(IRQ_MMP2_SSP_BASE + 0)
#define IRQ_MMP2_SSP3_SRDY		(IRQ_MMP2_SSP_BASE + 1)

#define IRQ_MMP2_MUX_END		(IRQ_MMP2_SSP_BASE + 2)

#define IRQ_GPIO_START			128
#define IRQ_GPIO_NUM			192
#define IRQ_GPIO(x)			(IRQ_GPIO_START + (x))

/* Board IRQ - 64 by default, increase if not enough */
#define IRQ_BOARD_START			(IRQ_GPIO_START + IRQ_GPIO_NUM)
#define IRQ_BOARD_END			(IRQ_BOARD_START + 64)

#define NR_IRQS				(IRQ_BOARD_END)

#endif /* __ASM_MACH_IRQS_H */
OpenPOWER on IntegriCloud