1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
|
/*
* Chip-specific setup code for the AT91SAM9x5 family
*
* Copyright (C) 2010-2012 Atmel Corporation.
*
* Licensed under GPLv2 or later.
*/
#include <linux/module.h>
#include <linux/dma-mapping.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/at91sam9x5.h>
#include <mach/at91_pmc.h>
#include <mach/cpu.h>
#include "board.h"
#include "soc.h"
#include "generic.h"
#include "clock.h"
#include "sam9_smc.h"
/* --------------------------------------------------------------------
* Clocks
* -------------------------------------------------------------------- */
/*
* The peripheral clocks.
*/
static struct clk pioAB_clk = {
.name = "pioAB_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_PIOAB,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk pioCD_clk = {
.name = "pioCD_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_PIOCD,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk smd_clk = {
.name = "smd_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_SMD,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart0_clk = {
.name = "usart0_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_USART0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart1_clk = {
.name = "usart1_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_USART1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart2_clk = {
.name = "usart2_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_USART2,
.type = CLK_TYPE_PERIPHERAL,
};
/* USART3 clock - Only for sam9g25/sam9x25 */
static struct clk usart3_clk = {
.name = "usart3_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_USART3,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk twi0_clk = {
.name = "twi0_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_TWI0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk twi1_clk = {
.name = "twi1_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_TWI1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk twi2_clk = {
.name = "twi2_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_TWI2,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk mmc0_clk = {
.name = "mci0_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_MCI0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk spi0_clk = {
.name = "spi0_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_SPI0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk spi1_clk = {
.name = "spi1_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_SPI1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk uart0_clk = {
.name = "uart0_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_UART0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk uart1_clk = {
.name = "uart1_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_UART1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tcb0_clk = {
.name = "tcb0_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_TCB,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk pwm_clk = {
.name = "pwm_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_PWM,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk adc_clk = {
.name = "adc_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_ADC,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk adc_op_clk = {
.name = "adc_op_clk",
.type = CLK_TYPE_PERIPHERAL,
.rate_hz = 5000000,
};
static struct clk dma0_clk = {
.name = "dma0_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_DMA0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk dma1_clk = {
.name = "dma1_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_DMA1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk uhphs_clk = {
.name = "uhphs",
.pmc_mask = 1 << AT91SAM9X5_ID_UHPHS,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk udphs_clk = {
.name = "udphs_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_UDPHS,
.type = CLK_TYPE_PERIPHERAL,
};
/* emac0 clock - Only for sam9g25/sam9x25/sam9g35/sam9x35 */
static struct clk macb0_clk = {
.name = "pclk",
.pmc_mask = 1 << AT91SAM9X5_ID_EMAC0,
.type = CLK_TYPE_PERIPHERAL,
};
/* lcd clock - Only for sam9g15/sam9g35/sam9x35 */
static struct clk lcdc_clk = {
.name = "lcdc_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_LCDC,
.type = CLK_TYPE_PERIPHERAL,
};
/* isi clock - Only for sam9g25 */
static struct clk isi_clk = {
.name = "isi_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_ISI,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk mmc1_clk = {
.name = "mci1_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_MCI1,
.type = CLK_TYPE_PERIPHERAL,
};
/* emac1 clock - Only for sam9x25 */
static struct clk macb1_clk = {
.name = "pclk",
.pmc_mask = 1 << AT91SAM9X5_ID_EMAC1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk ssc_clk = {
.name = "ssc_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_SSC,
.type = CLK_TYPE_PERIPHERAL,
};
/* can0 clock - Only for sam9x35 */
static struct clk can0_clk = {
.name = "can0_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_CAN0,
.type = CLK_TYPE_PERIPHERAL,
};
/* can1 clock - Only for sam9x35 */
static struct clk can1_clk = {
.name = "can1_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_CAN1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk *periph_clocks[] __initdata = {
&pioAB_clk,
&pioCD_clk,
&smd_clk,
&usart0_clk,
&usart1_clk,
&usart2_clk,
&twi0_clk,
&twi1_clk,
&twi2_clk,
&mmc0_clk,
&spi0_clk,
&spi1_clk,
&uart0_clk,
&uart1_clk,
&tcb0_clk,
&pwm_clk,
&adc_clk,
&adc_op_clk,
&dma0_clk,
&dma1_clk,
&uhphs_clk,
&udphs_clk,
&mmc1_clk,
&ssc_clk,
// irq0
};
static struct clk_lookup periph_clocks_lookups[] = {
/* lookup table for DT entries */
CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
CLKDEV_CON_DEV_ID("usart", "f801c000.serial", &usart0_clk),
CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk),
CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk),
CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk),
CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb0_clk),
CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk),
CLKDEV_CON_DEV_ID("mci_clk", "f0008000.mmc", &mmc0_clk),
CLKDEV_CON_DEV_ID("mci_clk", "f000c000.mmc", &mmc1_clk),
CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma0_clk),
CLKDEV_CON_DEV_ID("dma_clk", "ffffee00.dma-controller", &dma1_clk),
CLKDEV_CON_DEV_ID("pclk", "f0010000.ssc", &ssc_clk),
CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
CLKDEV_CON_DEV_ID(NULL, "f8018000.i2c", &twi2_clk),
CLKDEV_CON_DEV_ID("spi_clk", "f0000000.spi", &spi0_clk),
CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi1_clk),
CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioAB_clk),
CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioAB_clk),
CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCD_clk),
CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCD_clk),
/* additional fake clock for macb_hclk */
CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb0_clk),
CLKDEV_CON_DEV_ID("hclk", "f8030000.ethernet", &macb1_clk),
CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk),
CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk),
CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk),
CLKDEV_CON_DEV_ID("hclk", "500000.gadget", &utmi_clk),
CLKDEV_CON_DEV_ID("pclk", "500000.gadget", &udphs_clk),
};
/*
* The two programmable clocks.
* You must configure pin multiplexing to bring these signals out.
*/
static struct clk pck0 = {
.name = "pck0",
.pmc_mask = AT91_PMC_PCK0,
.type = CLK_TYPE_PROGRAMMABLE,
.id = 0,
};
static struct clk pck1 = {
.name = "pck1",
.pmc_mask = AT91_PMC_PCK1,
.type = CLK_TYPE_PROGRAMMABLE,
.id = 1,
};
static void __init at91sam9x5_register_clocks(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
clk_register(periph_clocks[i]);
clkdev_add_table(periph_clocks_lookups,
ARRAY_SIZE(periph_clocks_lookups));
if (cpu_is_at91sam9g25()
|| cpu_is_at91sam9x25())
clk_register(&usart3_clk);
if (cpu_is_at91sam9g25()
|| cpu_is_at91sam9x25()
|| cpu_is_at91sam9g35()
|| cpu_is_at91sam9x35())
clk_register(&macb0_clk);
if (cpu_is_at91sam9g15()
|| cpu_is_at91sam9g35()
|| cpu_is_at91sam9x35())
clk_register(&lcdc_clk);
if (cpu_is_at91sam9g25())
clk_register(&isi_clk);
if (cpu_is_at91sam9x25())
clk_register(&macb1_clk);
if (cpu_is_at91sam9x25()
|| cpu_is_at91sam9x35()) {
clk_register(&can0_clk);
clk_register(&can1_clk);
}
clk_register(&pck0);
clk_register(&pck1);
}
/* --------------------------------------------------------------------
* AT91SAM9x5 processor initialization
* -------------------------------------------------------------------- */
static void __init at91sam9x5_map_io(void)
{
at91_init_sram(0, AT91SAM9X5_SRAM_BASE, AT91SAM9X5_SRAM_SIZE);
}
/* --------------------------------------------------------------------
* Interrupt initialization
* -------------------------------------------------------------------- */
AT91_SOC_START(at91sam9x5)
.map_io = at91sam9x5_map_io,
.register_clocks = at91sam9x5_register_clocks,
AT91_SOC_END
|
