summaryrefslogtreecommitdiffstats
path: root/arch/arm/boot/dts/mt8127.dtsi
blob: ca3402e8240be1478568f23622c3bed965e06cfa (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
/*
 * Copyright (c) 2014 MediaTek Inc.
 * Author: Joe.C <yingjoe.chen@mediatek.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton64.dtsi"

/ {
	compatible = "mediatek,mt8127";
	interrupt-parent = <&sysirq>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x0>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x1>;
		};
		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x2>;
		};
		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x3>;
		};

	};

	clocks {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "simple-bus";
		ranges;

		system_clk: dummy13m {
			compatible = "fixed-clock";
			clock-frequency = <13000000>;
			#clock-cells = <0>;
		};

		rtc_clk: dummy32k {
			compatible = "fixed-clock";
			clock-frequency = <32000>;
			#clock-cells = <0>;
		};

		uart_clk: dummy26m {
			compatible = "fixed-clock";
			clock-frequency = <26000000>;
			#clock-cells = <0>;
                };
	};

	soc {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "simple-bus";
		ranges;

		timer: timer@10008000 {
			compatible = "mediatek,mt8127-timer",
					"mediatek,mt6577-timer";
			reg = <0 0x10008000 0 0x80>;
			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&system_clk>, <&rtc_clk>;
			clock-names = "system-clk", "rtc-clk";
		};

		sysirq: interrupt-controller@10200100 {
			compatible = "mediatek,mt8127-sysirq",
				     "mediatek,mt6577-sysirq";
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupt-parent = <&gic>;
			reg = <0 0x10200100 0 0x1c>;
		};

		gic: interrupt-controller@10211000 {
			compatible = "arm,cortex-a7-gic";
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupt-parent = <&gic>;
			reg = <0 0x10211000 0 0x1000>,
			      <0 0x10212000 0 0x1000>,
			      <0 0x10214000 0 0x2000>,
			      <0 0x10216000 0 0x2000>;
		};

		uart0: serial@11002000 {
			compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
			reg = <0 0x11002000 0 0x400>;
			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&uart_clk>;
			status = "disabled";
		};

		uart1: serial@11003000 {
			compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
			reg = <0 0x11003000 0 0x400>;
			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&uart_clk>;
			status = "disabled";
		};

		uart2: serial@11004000 {
			compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
			reg = <0 0x11004000 0 0x400>;
			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&uart_clk>;
			status = "disabled";
		};

		uart3: serial@11005000 {
			compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
			reg = <0 0x11005000 0 0x400>;
			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&uart_clk>;
			status = "disabled";
		};
	};
};
OpenPOWER on IntegriCloud