summaryrefslogtreecommitdiffstats
path: root/arch/arm/boot/dts/keystone.dts
blob: a68e34bbecb2628d21fcfb018cb9567f722efc3b (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
/*
 * Copyright 2013 Texas Instruments, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

/dts-v1/;
#include <dt-bindings/interrupt-controller/arm-gic.h>

#include "skeleton.dtsi"

/ {
	model = "Texas Instruments Keystone 2 SoC";
	compatible =  "ti,keystone-evm";
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&gic>;

	aliases {
		serial0	= &uart0;
	};

	memory {
		reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		interrupt-parent = <&gic>;

		cpu@0 {
			compatible = "arm,cortex-a15";
			device_type = "cpu";
			reg = <0>;
		};

		cpu@1 {
			compatible = "arm,cortex-a15";
			device_type = "cpu";
			reg = <1>;
		};

		cpu@2 {
			compatible = "arm,cortex-a15";
			device_type = "cpu";
			reg = <2>;
		};

		cpu@3 {
			compatible = "arm,cortex-a15";
			device_type = "cpu";
			reg = <3>;
		};
	};

	gic: interrupt-controller {
		compatible = "arm,cortex-a15-gic";
		#interrupt-cells = <3>;
		#size-cells = <0>;
		#address-cells = <1>;
		interrupt-controller;
		reg = <0x0 0x02561000 0x0 0x1000>,
		      <0x0 0x02562000 0x0 0x2000>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts =
			<GIC_PPI 13
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 14
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 11
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 10
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};

	pmu {
		compatible = "arm,cortex-a15-pmu";
		interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>,
			     <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
			     <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>,
			     <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>;
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "ti,keystone","simple-bus";
		interrupt-parent = <&gic>;
		ranges = <0x0 0x0 0x0 0xc0000000>;

		rstctrl: reset-controller {
			compatible = "ti,keystone-reset";
			reg = <0x023100e8 4>;	/* pll reset control reg */
		};

		uart0: serial@02530c00 {
			compatible = "ns16550a";
			current-speed = <115200>;
			reg-shift = <2>;
			reg-io-width = <4>;
			reg = <0x02530c00 0x100>;
			clock-frequency = <133120000>;
			interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
		};

		uart1:	serial@02531000 {
			compatible = "ns16550a";
			current-speed = <115200>;
			reg-shift = <2>;
			reg-io-width = <4>;
			reg = <0x02531000 0x100>;
			clock-frequency = <133120000>;
			interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
		};

	};
};
OpenPOWER on IntegriCloud