summaryrefslogtreecommitdiffstats
path: root/arch/arm/boot/dts/bcm7445.dtsi
blob: 3b6b1756068781a4e3a403446a388c9823c7ddaf (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
#include <dt-bindings/interrupt-controller/arm-gic.h>

#include "skeleton.dtsi"

/ {
	#address-cells = <2>;
	#size-cells = <2>;
	model = "Broadcom STB (bcm7445)";
	compatible = "brcm,bcm7445", "brcm,brcmstb";
	interrupt-parent = <&gic>;

	chosen {
		bootargs = "console=ttyS0,115200 earlyprintk";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "brcm,brahma-b15";
			device_type = "cpu";
			enable-method = "brcm,brahma-b15";
			reg = <0>;
		};

		cpu@1 {
			compatible = "brcm,brahma-b15";
			device_type = "cpu";
			enable-method = "brcm,brahma-b15";
			reg = <1>;
		};

		cpu@2 {
			compatible = "brcm,brahma-b15";
			device_type = "cpu";
			enable-method = "brcm,brahma-b15";
			reg = <2>;
		};

		cpu@3 {
			compatible = "brcm,brahma-b15";
			device_type = "cpu";
			enable-method = "brcm,brahma-b15";
			reg = <3>;
		};
	};

	gic: interrupt-controller@ffd00000 {
		compatible = "brcm,brahma-b15-gic", "arm,cortex-a15-gic";
		reg = <0x00 0xffd01000 0x00 0x1000>,
		      <0x00 0xffd02000 0x00 0x2000>,
		      <0x00 0xffd04000 0x00 0x2000>,
		      <0x00 0xffd06000 0x00 0x2000>;
		interrupt-controller;
		#interrupt-cells = <3>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>;
	};

	rdb {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges = <0 0x00 0xf0000000 0x1000000>;

		serial@40ab00 {
			compatible = "ns16550a";
			reg = <0x40ab00 0x20>;
			reg-shift = <2>;
			reg-io-width = <4>;
			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <81000000>;
		};

		sun_top_ctrl: syscon@404000 {
			compatible = "brcm,bcm7445-sun-top-ctrl",
				     "syscon";
			reg = <0x404000 0x51c>;
		};

		hif_cpubiuctrl: syscon@3e2400 {
			compatible = "brcm,bcm7445-hif-cpubiuctrl",
				     "syscon";
			reg = <0x3e2400 0x5b4>;
		};

		hif_continuation: syscon@452000 {
			compatible = "brcm,bcm7445-hif-continuation",
				     "syscon";
			reg = <0x452000 0x100>;
		};

		irq0_intc: interrupt-controller@40a780 {
			compatible = "brcm,bcm7120-l2-intc";
			interrupt-parent = <&gic>;
			#interrupt-cells = <1>;
			reg = <0x40a780 0x8>;
			interrupt-controller;
			interrupts = <GIC_SPI 0x45 0x0>,
				     <GIC_SPI 0x43 0x0>;
			brcm,int-map-mask = <0x25c>, <0x7000000>;
			brcm,int-fwd-mask = <0x70000>;
		};

		irq0_aon_intc: interrupt-controller@417280 {
			compatible = "brcm,bcm7120-l2-intc";
			reg = <0x417280 0x8>;
			interrupt-parent = <&gic>;
			#interrupt-cells = <1>;
			interrupt-controller;
			interrupts = <GIC_SPI 0x46 0x0>,
				     <GIC_SPI 0x44 0x0>,
				     <GIC_SPI 0x49 0x0>;
			brcm,int-map-mask = <0x1e3 0x18000000 0x100000>;
			brcm,int-fwd-mask = <0x0>;
			brcm,irq-can-wake;
		};

		hif_intr2_intc: interrupt-controller@3e1000 {
			compatible = "brcm,l2-intc";
			reg = <0x3e1000 0x30>;
			interrupt-controller;
			#interrupt-cells = <1>;
			interrupts = <GIC_SPI 0x20 0x0>;
			interrupt-parent = <&gic>;
			interrupt-names = "hif";
		};

                aon_pm_l2_intc: interrupt-controller@410640 {
			compatible = "brcm,l2-intc";
			reg = <0x410640 0x30>;
			interrupt-controller;
			#interrupt-cells = <1>;
			interrupts = <GIC_SPI 0x40 0x0>;
			interrupt-parent = <&gic>;
			brcm,irq-can-wake;
		};

		nand: nand@3e2800 {
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "brcm,brcmnand-v7.1", "brcm,brcmnand";
			reg-names = "nand", "flash-dma";
			reg = <0x3e2800 0x600>, <0x3e3000 0x2c>;
			interrupt-parent = <&hif_intr2_intc>;
			interrupts = <24>, <4>;
			interrupt-names = "nand_ctlrdy", "flash_dma_done";
		};

		sata@45a000 {
			compatible = "brcm,bcm7445-ahci", "brcm,sata3-ahci";
			reg-names = "ahci", "top-ctrl";
			reg = <0x45a000 0xa9c>, <0x458040 0x24>;
			interrupts = <GIC_SPI 30 0>;
			#address-cells = <1>;
			#size-cells = <0>;

			sata0: sata-port@0 {
				reg = <0>;
				phys = <&sata_phy0>;
			};

			sata1: sata-port@1 {
				reg = <1>;
				phys = <&sata_phy1>;
			};
		};

		sata_phy: sata-phy@458100 {
			compatible = "brcm,bcm7445-sata-phy", "brcm,phy-sata3";
			reg = <0x458100 0x1f00>;
			reg-names = "phy";
			#address-cells = <0x1>;
			#size-cells = <0x0>;

			sata_phy0: sata-phy@0 {
				reg = <0>;
				#phy-cells = <0>;
			};

			sata_phy1: sata-phy@1 {
				reg = <1>;
				#phy-cells = <0>;
			};
		};

		upg_gio: gpio@40a700 {
			compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
			reg = <0x40a700 0x80>;
			#gpio-cells = <2>;
			#interrupt-cells = <2>;
			gpio-controller;
			interrupt-controller;
			interrupt-parent = <&irq0_intc>;
			interrupts = <6>;
			brcm,gpio-bank-widths = <32 32 32 24>;
		};

		upg_gio_aon: gpio@4172c0 {
			compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
			reg = <0x4172c0 0x40>;
			#gpio-cells = <2>;
			#interrupt-cells = <2>;
			gpio-controller;
			interrupt-controller;
			interrupts-extended = <&irq0_aon_intc 0x6>,
					      <&aon_pm_l2_intc 0x5>;
			wakeup-source;
			brcm,gpio-bank-widths = <18 4>;
		};

	};

	smpboot {
		compatible = "brcm,brcmstb-smpboot";
		syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>;
		syscon-cont = <&hif_continuation>;
	};

	reboot {
		compatible = "brcm,brcmstb-reboot";
		syscon = <&sun_top_ctrl 0x304 0x308>;
	};
};
OpenPOWER on IntegriCloud