summaryrefslogtreecommitdiffstats
path: root/arch/arm/boot/dts/armada-385-turris-omnia.dts
blob: 768b6c5d2129a1449350e674a54e0e0e4db3d4da (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Device Tree file for the Turris Omnia
 *
 * Copyright (C) 2016 Uwe Kleine-König <uwe@kleine-koenig.org>
 * Copyright (C) 2016 Tomas Hlavacek <tmshlvkc@gmail.com>
 *
 * Schematic available at https://www.turris.cz/doc/_media/rtrom01-schema.pdf
 */

/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "armada-385.dtsi"

/ {
	model = "Turris Omnia";
	compatible = "cznic,turris-omnia", "marvell,armada385", "marvell,armada380";

	chosen {
		stdout-path = &uart0;
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x40000000>; /* 1024 MB */
	};

	soc {
		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
			  MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
			  MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;

		internal-regs {

			/* USB part of the PCIe2/USB 2.0 port */
			usb@58000 {
				status = "okay";
			};

			sata@a8000 {
				status = "okay";
			};

			sdhci@d8000 {
				pinctrl-names = "default";
				pinctrl-0 = <&sdhci_pins>;
				status = "okay";

				bus-width = <8>;
				no-1-8-v;
				non-removable;
			};

			usb3@f0000 {
				status = "okay";
			};

			usb3@f8000 {
				status = "okay";
			};
		};

		pcie {
			status = "okay";

			pcie@1,0 {
				/* Port 0, Lane 0 */
				status = "okay";
			};

			pcie@2,0 {
				/* Port 1, Lane 0 */
				status = "okay";
			};

			pcie@3,0 {
				/* Port 2, Lane 0 */
				status = "okay";
			};
		};
	};
};

/* Connected to 88E6176 switch, port 6 */
&eth0 {
	pinctrl-names = "default";
	pinctrl-0 = <&ge0_rgmii_pins>;
	status = "okay";
	phy-mode = "rgmii";

	fixed-link {
		speed = <1000>;
		full-duplex;
	};
};

/* Connected to 88E6176 switch, port 5 */
&eth1 {
	pinctrl-names = "default";
	pinctrl-0 = <&ge1_rgmii_pins>;
	status = "okay";
	phy-mode = "rgmii";

	fixed-link {
		speed = <1000>;
		full-duplex;
	};
};

/* WAN port */
&eth2 {
	status = "okay";
	phy-mode = "sgmii";
	phy = <&phy1>;
};

&i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_pins>;
	status = "okay";

	i2cmux@70 {
		compatible = "nxp,pca9547";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x70>;
		status = "okay";

		i2c@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;

			/* STM32F0 command interface at address 0x2a */
			/* leds device (in STM32F0) at address 0x2b */

			eeprom@54 {
				compatible = "atmel,24c64";
				reg = <0x54>;

				/* The EEPROM contains data for bootloader.
				 * Contents:
				 * 	struct omnia_eeprom {
				 * 		u32 magic; (=0x0341a034 in LE)
				 *		u32 ramsize; (in GiB)
				 * 		char regdomain[4];
				 * 		u32 crc32;
				 * 	};
				 */
			};
		};

		i2c@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;

			/* routed to PCIe0/mSATA connector (CN7A) */
		};

		i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <2>;

			/* routed to PCIe1/USB2 connector (CN61A) */
		};

		i2c@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <3>;

			/* routed to PCIe2 connector (CN62A) */
		};

		i2c@4 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <4>;

			/* routed to SFP+ */
		};

		i2c@5 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <5>;

			/* ATSHA204A at address 0x64 */
		};

		i2c@6 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <6>;

			/* exposed on pin header */
		};

		i2c@7 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <7>;

			pcawan: gpio@71 {
				/*
				 * GPIO expander for SFP+ signals and
				 * and phy irq
				 */
				compatible = "nxp,pca9538";
				reg = <0x71>;

				pinctrl-names = "default";
				pinctrl-0 = <&pcawan_pins>;

				interrupt-parent = <&gpio1>;
				interrupts = <14 IRQ_TYPE_LEVEL_LOW>;

				gpio-controller;
				#gpio-cells = <2>;
			};
		};
	};
};

&mdio {
	pinctrl-names = "default";
	pinctrl-0 = <&mdio_pins>;
	status = "okay";

	phy1: phy@1 {
		status = "okay";
		compatible = "ethernet-phy-id0141.0DD1", "ethernet-phy-ieee802.3-c22";
		reg = <1>;

		/* irq is connected to &pcawan pin 7 */
	};

	/* Switch MV88E6176 at address 0x10 */
	switch@10 {
		compatible = "marvell,mv88e6085";
		#address-cells = <1>;
		#size-cells = <0>;
		dsa,member = <0 0>;

		reg = <0x10>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			ports@0 {
				reg = <0>;
				label = "lan0";
			};

			ports@1 {
				reg = <1>;
				label = "lan1";
			};

			ports@2 {
				reg = <2>;
				label = "lan2";
			};

			ports@3 {
				reg = <3>;
				label = "lan3";
			};

			ports@4 {
				reg = <4>;
				label = "lan4";
			};

			ports@5 {
				reg = <5>;
				label = "cpu";
				ethernet = <&eth1>;
				phy-mode = "rgmii-id";

				fixed-link {
					speed = <1000>;
					full-duplex;
				};
			};

			/* port 6 is connected to eth0 */
		};
	};
};

&pinctrl {
	pcawan_pins: pcawan-pins {
		marvell,pins = "mpp46";
		marvell,function = "gpio";
	};

	spi0cs0_pins: spi0cs0-pins {
		marvell,pins = "mpp25";
		marvell,function = "spi0";
	};

	spi0cs1_pins: spi0cs1-pins {
		marvell,pins = "mpp26";
		marvell,function = "spi0";
	};
};

&spi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi0_pins &spi0cs0_pins>;
	status = "okay";

	spi-nor@0 {
		compatible = "spansion,s25fl164k", "jedec,spi-nor";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0>;
		spi-max-frequency = <40000000>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				reg = <0x0 0x00100000>;
				label = "U-Boot";
			};

			partition@100000 {
				reg = <0x00100000 0x00700000>;
				label = "Rescue system";
			};
		};
	};

	/* MISO, MOSI, SCLK and CS1 are routed to pin header CN11 */
};

&uart0 {
	/* Pin header CN10 */
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_pins>;
	status = "okay";
};

&uart1 {
	/* Pin header CN11 */
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_pins>;
	status = "okay";
};
OpenPOWER on IntegriCloud