/* * BRIEF MODULE DESCRIPTION * Code to handle irqs on GT64120A boards * Derived from mips/orion and Cort * * Copyright (C) 2000 RidgeRun, Inc. * Author: RidgeRun, Inc. * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * You should have received a copy of the GNU General Public License along * with this program; if not, write to the Free Software Foundation, Inc., * 675 Mass Ave, Cambridge, MA 02139, USA. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include asmlinkage void plat_irq_dispatch(struct pt_regs *regs) { unsigned int pending = read_c0_status() & read_c0_cause(); if (pending & STATUSF_IP4) /* int2 hardware line (timer) */ do_IRQ(4, regs); else if (pending & STATUSF_IP2) /* int0 hardware line */ do_IRQ(GT_INTA, regs); else if (pending & STATUSF_IP5) /* int3 hardware line */ do_IRQ(GT_INTD, regs); else if (pending & STATUSF_IP6) /* int4 hardware line */ do_IRQ(6, regs); else if (pending & STATUSF_IP7) /* compare int */ do_IRQ(7, regs); else spurious_interrupt(regs); } static void disable_ev64120_irq(unsigned int irq_nr) { unsigned long flags; local_irq_save(flags); if (irq_nr >= 8) { // All PCI interrupts are on line 5 or 2 clear_c0_status(9 << 10); } else { clear_c0_status(1 << (irq_nr + 8)); } local_irq_restore(flags); } static void enable_ev64120_irq(unsigned int irq_nr) { unsigned long flags; local_irq_save(flags); if (irq_nr >= 8) // All PCI interrupts are on line 5 or 2 set_c0_status(9 << 10); else set_c0_status(1 << (irq_nr + 8)); local_irq_restore(flags); } static unsigned int startup_ev64120_irq(unsigned int irq) { enable_ev64120_irq(irq); return 0; /* Never anything pending */ } #define shutdown_ev64120_irq disable_ev64120_irq #define mask_and_ack_ev64120_irq disable_ev64120_irq static void end_ev64120_irq(unsigned int irq) { if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) enable_ev64120_irq(irq); } static struct hw_interrupt_type ev64120_irq_type = { .typename = "EV64120", .startup = startup_ev64120_irq, .shutdown = shutdown_ev64120_irq, .enable = enable_ev64120_irq, .disable = disable_ev64120_irq, .ack = mask_and_ack_ev64120_irq, .end = end_ev64120_irq, .set_affinity = NULL }; void gt64120_irq_setup(void) { /* * Clear all of the interrupts while we change the able around a bit. */ clear_c0_status(ST0_IM); local_irq_disable(); /* * Enable timer. Other interrupts will be enabled as they are * registered. */ set_c0_status(IE_IRQ2); } void __init arch_init_irq(void) { int i; /* Let's initialize our IRQ descriptors */ for (i = 0; i < NR_IRQS; i++) { irq_desc[i].status = 0; irq_desc[i].handler = &no_irq_type; irq_desc[i].action = NULL; irq_desc[i].depth = 0; spin_lock_init(&irq_desc[i].lock); } gt64120_irq_setup(); }