From 24dd85ff723f142093f44244764b9b5c152235b8 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Wed, 28 Sep 2011 11:57:23 +0200 Subject: io-mapping: ensure io_mapping_map_atomic _is_ atomic For the !HAVE_ATOMIC_IOMAP case the stub functions did not call pagefault_disable/_enable. The i915 driver relies on the map actually being atomic, otherwise it can deadlock with it's own pagefault handler in the gtt pwrite fastpath. This is exercised by gem_mmap_gtt from the intel-gpu-toosl gem testsuite. v2: Chris Wilson noted the lack of an include. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=38115 Cc: stable@kernel.org Signed-off-by: Daniel Vetter Reviewed-by: Chris Wilson Signed-off-by: Keith Packard --- include/linux/io-mapping.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/linux/io-mapping.h b/include/linux/io-mapping.h index 8cdcc2a1..1feeb52 100644 --- a/include/linux/io-mapping.h +++ b/include/linux/io-mapping.h @@ -117,6 +117,8 @@ io_mapping_unmap(void __iomem *vaddr) #else +#include + /* this struct isn't actually defined anywhere */ struct io_mapping; @@ -138,12 +140,14 @@ static inline void __iomem * io_mapping_map_atomic_wc(struct io_mapping *mapping, unsigned long offset) { + pagefault_disable(); return ((char __force __iomem *) mapping) + offset; } static inline void io_mapping_unmap_atomic(void __iomem *vaddr) { + pagefault_enable(); } /* Non-atomic map/unmap */ -- cgit v1.1 From 5c0422878fcdc279ae9a8e8b66972a15b5efb67f Mon Sep 17 00:00:00 2001 From: Ben Widawsky Date: Mon, 17 Oct 2011 15:51:55 -0700 Subject: drm/i915: ILK + VT-d workaround Idle the GPU before doing any unmaps. We know if VT-d is in use through an exported variable from iommu code. This should avoid a known HW issue. Signed-off-by: Ben Widawsky Reviewed-by: Daniel Vetter Signed-off-by: Keith Packard --- include/drm/intel-gtt.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/drm/intel-gtt.h b/include/drm/intel-gtt.h index 9e343c0..b174620 100644 --- a/include/drm/intel-gtt.h +++ b/include/drm/intel-gtt.h @@ -13,6 +13,8 @@ const struct intel_gtt { unsigned int gtt_mappable_entries; /* Whether i915 needs to use the dmar apis or not. */ unsigned int needs_dmar : 1; + /* Whether we idle the gpu before mapping/unmapping */ + unsigned int do_idle_maps : 1; } *intel_gtt_get(void); void intel_gtt_chipset_flush(void); -- cgit v1.1 From b73fe58cafc6954db0170a5d4ef2b4b6316f6709 Mon Sep 17 00:00:00 2001 From: Ben Widawsky Date: Tue, 4 Oct 2011 15:16:48 -0700 Subject: drm: Add Panel Self Refresh DP addresses Add the addresses and definitions I care about for Panel Self Refresh, as documented in the eDP spec. I'm sending these out before some other patches because this should be a fairly simple one to get upstream and not require too much fuss (where the others may have some fuss). This file is a mess with white spacing. I tried to stay consistent with the surrounding code. v2: had some silly mistakes in v1 which Keith caught Cc: Dave Airlie Cc: Keith Packard Signed-off-by: Ben Widawsky Signed-off-by: Keith Packard --- include/drm/drm_dp_helper.h | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) (limited to 'include') diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 91567bb..2b1a358 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -74,6 +74,20 @@ #define DP_TRAINING_AUX_RD_INTERVAL 0x00e +#define DP_PSR_SUPPORT 0x070 +# define DP_PSR_IS_SUPPORTED 1 +#define DP_PSR_CAPS 0x071 +# define DP_PSR_NO_TRAIN_ON_EXIT 1 +# define DP_PSR_SETUP_TIME_330 (0 << 1) +# define DP_PSR_SETUP_TIME_275 (1 << 1) +# define DP_PSR_SETUP_TIME_220 (2 << 1) +# define DP_PSR_SETUP_TIME_165 (3 << 1) +# define DP_PSR_SETUP_TIME_110 (4 << 1) +# define DP_PSR_SETUP_TIME_55 (5 << 1) +# define DP_PSR_SETUP_TIME_0 (6 << 1) +# define DP_PSR_SETUP_TIME_MASK (7 << 1) +# define DP_PSR_SETUP_TIME_SHIFT 1 + /* link configuration */ #define DP_LINK_BW_SET 0x100 # define DP_LINK_BW_1_62 0x06 @@ -133,6 +147,12 @@ #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 # define DP_SET_ANSI_8B10B (1 << 0) +#define DP_PSR_EN_CFG 0x170 +# define DP_PSR_ENABLE (1 << 0) +# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) +# define DP_PSR_CRC_VERIFICATION (1 << 2) +# define DP_PSR_FRAME_CAPTURE (1 << 3) + #define DP_LANE0_1_STATUS 0x202 #define DP_LANE2_3_STATUS 0x203 # define DP_LANE_CR_DONE (1 << 0) @@ -169,6 +189,22 @@ # define DP_SET_POWER_D0 0x1 # define DP_SET_POWER_D3 0x2 +#define DP_PSR_ERROR_STATUS 0x2006 +# define DP_PSR_LINK_CRC_ERROR (1 << 0) +# define DP_PSR_RFB_STORAGE_ERROR (1 << 1) + +#define DP_PSR_ESI 0x2007 +# define DP_PSR_CAPS_CHANGE (1 << 0) + +#define DP_PSR_STATUS 0x2008 +# define DP_PSR_SINK_INACTIVE 0 +# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 +# define DP_PSR_SINK_ACTIVE_RFB 2 +# define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 +# define DP_PSR_SINK_ACTIVE_RESYNC 4 +# define DP_PSR_SINK_INTERNAL_ERROR 7 +# define DP_PSR_SINK_STATE_MASK 0x07 + #define MODE_I2C_START 1 #define MODE_I2C_WRITE 2 #define MODE_I2C_READ 4 -- cgit v1.1 From a60f0e38d72a5e24085d6e7e27a4cadc20ae268a Mon Sep 17 00:00:00 2001 From: Jesse Barnes Date: Thu, 20 Oct 2011 15:09:17 -0700 Subject: drm/i915: add DP test request handling DPCD 1.1+ adds some automated test infrastructure support. Add support for reading the IRQ source and jumping to a test handling routine if needed. Subsequent patches will handle particular tests; this patch just ACKs any requested tests by default. Signed-off-by: Jesse Barnes Signed-off-by: Keith Packard --- include/drm/drm_dp_helper.h | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'include') diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 2b1a358..0d2f727e 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -153,6 +153,12 @@ # define DP_PSR_CRC_VERIFICATION (1 << 2) # define DP_PSR_FRAME_CAPTURE (1 << 3) +#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 +# define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) +# define DP_AUTOMATED_TEST_REQUEST (1 << 1) +# define DP_CP_IRQ (1 << 2) +# define DP_SINK_SPECIFIC_IRQ (1 << 6) + #define DP_LANE0_1_STATUS 0x202 #define DP_LANE2_3_STATUS 0x203 # define DP_LANE_CR_DONE (1 << 0) @@ -185,6 +191,25 @@ # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 +#define DP_TEST_REQUEST 0x218 +# define DP_TEST_LINK_TRAINING (1 << 0) +# define DP_TEST_LINK_PATTERN (1 << 1) +# define DP_TEST_LINK_EDID_READ (1 << 2) +# define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ + +#define DP_TEST_LINK_RATE 0x219 +# define DP_LINK_RATE_162 (0x6) +# define DP_LINK_RATE_27 (0xa) + +#define DP_TEST_LANE_COUNT 0x220 + +#define DP_TEST_PATTERN 0x221 + +#define DP_TEST_RESPONSE 0x260 +# define DP_TEST_ACK (1 << 0) +# define DP_TEST_NAK (1 << 1) +# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) + #define DP_SET_POWER 0x600 # define DP_SET_POWER_D0 0x1 # define DP_SET_POWER_D3 0x2 -- cgit v1.1