From a3ebdb6c423dff420168a3faf25c76e9e5f59258 Mon Sep 17 00:00:00 2001 From: Christoph Lameter Date: Tue, 18 Dec 2007 16:22:46 -0800 Subject: IA64: Slim down __clear_bit_unlock __clear_bit_unlock does not need to perform atomic operations on the variable. Avoid a cmpxchg and simply do a store with release semantics. Add a barrier to be safe that the compiler does not do funky things. Tony: Use intrinsic rather than inline assembler Signed-off-by: Christoph Lameter Acked-by: Nick Piggin Signed-off-by: Andrew Morton Signed-off-by: Tony Luck --- include/asm-ia64/bitops.h | 17 ++++++++++++++--- include/asm-ia64/gcc_intrin.h | 5 +++++ include/asm-ia64/intel_intrin.h | 3 +++ 3 files changed, 22 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/asm-ia64/bitops.h b/include/asm-ia64/bitops.h index a977aff..a1b9719 100644 --- a/include/asm-ia64/bitops.h +++ b/include/asm-ia64/bitops.h @@ -124,10 +124,21 @@ clear_bit_unlock (int nr, volatile void *addr) /** * __clear_bit_unlock - Non-atomically clear a bit with release * - * This is like clear_bit_unlock, but the implementation may use a non-atomic - * store (this one uses an atomic, however). + * This is like clear_bit_unlock, but the implementation uses a store + * with release semantics. See also __raw_spin_unlock(). */ -#define __clear_bit_unlock clear_bit_unlock +static __inline__ void +__clear_bit_unlock(int nr, volatile void *addr) +{ + __u32 mask, new; + volatile __u32 *m; + + m = (volatile __u32 *)addr + (nr >> 5); + mask = ~(1 << (nr & 31)); + new = *m & mask; + barrier(); + ia64_st4_rel_nta(m, new); +} /** * __clear_bit - Clears a bit in memory (non-atomic version) diff --git a/include/asm-ia64/gcc_intrin.h b/include/asm-ia64/gcc_intrin.h index 4fb4e43..e58d329 100644 --- a/include/asm-ia64/gcc_intrin.h +++ b/include/asm-ia64/gcc_intrin.h @@ -191,6 +191,11 @@ register unsigned long ia64_r13 asm ("r13") __attribute_used__; asm volatile ("ldf.fill %0=[%1]" :"=f"(__f__): "r"(x)); \ }) +#define ia64_st4_rel_nta(m, val) \ +({ \ + asm volatile ("st4.rel.nta [%0] = %1\n\t" :: "r"(m), "r"(val)); \ +}) + #define ia64_stfs(x, regnum) \ ({ \ register double __f__ asm ("f"#regnum); \ diff --git a/include/asm-ia64/intel_intrin.h b/include/asm-ia64/intel_intrin.h index d069b6a..a520d10 100644 --- a/include/asm-ia64/intel_intrin.h +++ b/include/asm-ia64/intel_intrin.h @@ -110,6 +110,9 @@ #define ia64_st4_rel __st4_rel #define ia64_st8_rel __st8_rel +/* FIXME: need st4.rel.nta intrinsic */ +#define ia64_st4_rel_nta __st4_rel + #define ia64_ld1_acq __ld1_acq #define ia64_ld2_acq __ld2_acq #define ia64_ld4_acq __ld4_acq -- cgit v1.1 From 313d8e57b074d5f03dfed2755f21ae41a6f0fd5a Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Tue, 18 Dec 2007 17:02:21 -0800 Subject: [IA64] Two trivial spelling fixes s/addres/address/ s/performanc/performance/ Signed-off-by: Joe Perches Signed-off-by: Tony Luck --- include/asm-ia64/hw_irq.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-ia64/hw_irq.h b/include/asm-ia64/hw_irq.h index bba5baa..7e6e377 100644 --- a/include/asm-ia64/hw_irq.h +++ b/include/asm-ia64/hw_irq.h @@ -63,7 +63,7 @@ extern int ia64_last_device_vector; #define IA64_NUM_DEVICE_VECTORS (IA64_LAST_DEVICE_VECTOR - IA64_FIRST_DEVICE_VECTOR + 1) #define IA64_MCA_RENDEZ_VECTOR 0xe8 /* MCA rendez interrupt */ -#define IA64_PERFMON_VECTOR 0xee /* performanc monitor interrupt vector */ +#define IA64_PERFMON_VECTOR 0xee /* performance monitor interrupt vector */ #define IA64_TIMER_VECTOR 0xef /* use highest-prio group 15 interrupt for timer */ #define IA64_MCA_WAKEUP_VECTOR 0xf0 /* MCA wakeup (must be >MCA_RENDEZ_VECTOR) */ #define IA64_IPI_LOCAL_TLB_FLUSH 0xfc /* SMP flush local TLB */ -- cgit v1.1 From 64135fa97ce016058f95345425a9ebd04ee1bd2a Mon Sep 17 00:00:00 2001 From: Russ Anderson Date: Tue, 21 Aug 2007 16:45:12 -0500 Subject: [IA64] Fix Altix BTE error return status The Altix shub2 BTE error detail bits are in a different location than on shub1. The current code does not take this into account resulting in all shub2 BTE failures mapping to "unknown". This patch reads the error detail bits from the proper location, so the correct BTE failure reason is returned for both shub1 and shub2. Signed-off-by: Russ Anderson Signed-off-by: Tony Luck --- include/asm-ia64/sn/bte.h | 31 ++++++++++++++++++++++++++++++- include/asm-ia64/sn/xp.h | 27 +++++++++++++++++++++++++-- include/asm-ia64/sn/xpc.h | 8 +++++++- 3 files changed, 62 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/asm-ia64/sn/bte.h b/include/asm-ia64/sn/bte.h index 5335d87..a0d214f 100644 --- a/include/asm-ia64/sn/bte.h +++ b/include/asm-ia64/sn/bte.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (c) 2000-2006 Silicon Graphics, Inc. All Rights Reserved. + * Copyright (c) 2000-2007 Silicon Graphics, Inc. All Rights Reserved. */ @@ -150,6 +150,35 @@ typedef enum { BTEFAIL_NOTAVAIL, /* BTE not available */ } bte_result_t; +#define BTEFAIL_SH2_RESP_SHORT 0x1 /* bit 000001 */ +#define BTEFAIL_SH2_RESP_LONG 0x2 /* bit 000010 */ +#define BTEFAIL_SH2_RESP_DSP 0x4 /* bit 000100 */ +#define BTEFAIL_SH2_RESP_ACCESS 0x8 /* bit 001000 */ +#define BTEFAIL_SH2_CRB_TO 0x10 /* bit 010000 */ +#define BTEFAIL_SH2_NACK_LIMIT 0x20 /* bit 100000 */ +#define BTEFAIL_SH2_ALL 0x3F /* bit 111111 */ + +#define BTE_ERR_BITS 0x3FUL +#define BTE_ERR_SHIFT 36 +#define BTE_ERR_MASK (BTE_ERR_BITS << BTE_ERR_SHIFT) + +#define BTE_ERROR_RETRY(value) \ + (is_shub2() ? (value != BTEFAIL_SH2_CRB_TO) \ + : (value != BTEFAIL_TOUT)) + +/* + * On shub1 BTE_ERR_MASK will always be false, so no need for is_shub2() + */ +#define BTE_SHUB2_ERROR(_status) \ + ((_status & BTE_ERR_MASK) \ + ? (((_status >> BTE_ERR_SHIFT) & BTE_ERR_BITS) | IBLS_ERROR) \ + : _status) + +#define BTE_GET_ERROR_STATUS(_status) \ + (BTE_SHUB2_ERROR(_status) & ~IBLS_ERROR) + +#define BTE_VALID_SH2_ERROR(value) \ + ((value >= BTEFAIL_SH2_RESP_SHORT) && (value <= BTEFAIL_SH2_ALL)) /* * Structure defining a bte. An instance of this diff --git a/include/asm-ia64/sn/xp.h b/include/asm-ia64/sn/xp.h index 6f807e0..f7711b3 100644 --- a/include/asm-ia64/sn/xp.h +++ b/include/asm-ia64/sn/xp.h @@ -86,7 +86,7 @@ xp_bte_copy(u64 src, u64 vdst, u64 len, u64 mode, void *notification) BUG_ON(REGION_NUMBER(vdst) != RGN_KERNEL); ret = bte_copy(src, pdst, len, mode, notification); - if (ret != BTE_SUCCESS) { + if ((ret != BTE_SUCCESS) && BTE_ERROR_RETRY(ret)) { if (!in_interrupt()) { cond_resched(); } @@ -244,7 +244,30 @@ enum xpc_retval { xpcDisconnected, /* 51: channel disconnected (closed) */ - xpcUnknownReason /* 52: unknown reason -- must be last in list */ + xpcBteSh2Start, /* 52: BTE CRB timeout */ + + /* 53: 0x1 BTE Error Response Short */ + xpcBteSh2RspShort = xpcBteSh2Start + BTEFAIL_SH2_RESP_SHORT, + + /* 54: 0x2 BTE Error Response Long */ + xpcBteSh2RspLong = xpcBteSh2Start + BTEFAIL_SH2_RESP_LONG, + + /* 56: 0x4 BTE Error Response DSB */ + xpcBteSh2RspDSB = xpcBteSh2Start + BTEFAIL_SH2_RESP_DSP, + + /* 60: 0x8 BTE Error Response Access */ + xpcBteSh2RspAccess = xpcBteSh2Start + BTEFAIL_SH2_RESP_ACCESS, + + /* 68: 0x10 BTE Error CRB timeout */ + xpcBteSh2CRBTO = xpcBteSh2Start + BTEFAIL_SH2_CRB_TO, + + /* 84: 0x20 BTE Error NACK limit */ + xpcBteSh2NACKLimit = xpcBteSh2Start + BTEFAIL_SH2_NACK_LIMIT, + + /* 115: BTE end */ + xpcBteSh2End = xpcBteSh2Start + BTEFAIL_SH2_ALL, + + xpcUnknownReason /* 116: unknown reason -- must be last in list */ }; diff --git a/include/asm-ia64/sn/xpc.h b/include/asm-ia64/sn/xpc.h index e52b850..8e5d7de 100644 --- a/include/asm-ia64/sn/xpc.h +++ b/include/asm-ia64/sn/xpc.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (c) 2004-2006 Silicon Graphics, Inc. All Rights Reserved. + * Copyright (c) 2004-2007 Silicon Graphics, Inc. All Rights Reserved. */ @@ -1211,6 +1211,12 @@ xpc_IPI_init(int index) static inline enum xpc_retval xpc_map_bte_errors(bte_result_t error) { + if (is_shub2()) { + if (BTE_VALID_SH2_ERROR(error)) + return xpcBteSh2Start + error; + else + return xpcBteUnmappedError; + } switch (error) { case BTE_SUCCESS: return xpcSuccess; case BTEFAIL_DIR: return xpcBteDirectoryError; -- cgit v1.1 From 285fbd66330cd5899f4e607e3e65ab5921ddabf0 Mon Sep 17 00:00:00 2001 From: Jan Beulich Date: Wed, 19 Dec 2007 12:30:30 -0800 Subject: [IA64] make flush_tlb_kernel_range() an inline function This fixes an unused variable warning in mm/vmalloc.c. Tony: also fix resulting fallout in uncached.c with a typo in args to flush_tlb_kernel_range(). Signed-off-by: Jan Beulich Signed-off-by: Tony Luck --- include/asm-ia64/tlbflush.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-ia64/tlbflush.h b/include/asm-ia64/tlbflush.h index 80bcb0a..7774a1c 100644 --- a/include/asm-ia64/tlbflush.h +++ b/include/asm-ia64/tlbflush.h @@ -92,6 +92,10 @@ void smp_local_flush_tlb(void); #define smp_local_flush_tlb() #endif -#define flush_tlb_kernel_range(start, end) flush_tlb_all() /* XXX fix me */ +static inline void flush_tlb_kernel_range(unsigned long start, + unsigned long end) +{ + flush_tlb_all(); /* XXX fix me */ +} #endif /* _ASM_IA64_TLBFLUSH_H */ -- cgit v1.1