From d909b347591a23c5a2c324fbccd4c9c966f31c67 Mon Sep 17 00:00:00 2001 From: Dan Williams <dan.j.williams@intel.com> Date: Sat, 2 Feb 2008 19:30:14 -0700 Subject: async_tx: kill ASYNC_TX_ASSUME_COHERENT Remove the unused ASYNC_TX_ASSUME_COHERENT flag. Async_tx is meant to hide the difference between asynchronous hardware and synchronous software operations, this flag requires clients to understand cache coherency consequences of the async path. Signed-off-by: Dan Williams <dan.j.williams@intel.com> Reviewed-by: Haavard Skinnemoen <hskinnemoen@atmel.com> --- include/linux/async_tx.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'include') diff --git a/include/linux/async_tx.h b/include/linux/async_tx.h index bdca3f1..3d59d37 100644 --- a/include/linux/async_tx.h +++ b/include/linux/async_tx.h @@ -47,7 +47,6 @@ struct dma_chan_ref { * address is an implied source, whereas the asynchronous case it must be listed * as a source. The destination address must be the first address in the source * array. - * @ASYNC_TX_ASSUME_COHERENT: skip cache maintenance operations * @ASYNC_TX_ACK: immediately ack the descriptor, precludes setting up a * dependency chain * @ASYNC_TX_DEP_ACK: ack the dependency descriptor. Useful for chaining. @@ -55,7 +54,6 @@ struct dma_chan_ref { enum async_tx_flags { ASYNC_TX_XOR_ZERO_DST = (1 << 0), ASYNC_TX_XOR_DROP_DST = (1 << 1), - ASYNC_TX_ASSUME_COHERENT = (1 << 2), ASYNC_TX_ACK = (1 << 3), ASYNC_TX_DEP_ACK = (1 << 4), }; -- cgit v1.1 From 0036731c88fdb5bf4f04a796a30b5e445fc57f54 Mon Sep 17 00:00:00 2001 From: Dan Williams <dan.j.williams@intel.com> Date: Sat, 2 Feb 2008 19:49:57 -0700 Subject: async_tx: kill tx_set_src and tx_set_dest methods The tx_set_src and tx_set_dest methods were originally implemented to allow an array of addresses to be passed down from async_xor to the dmaengine driver while minimizing stack overhead. Removing these methods allows drivers to have all transaction parameters available at 'prep' time, saves two function pointers in struct dma_async_tx_descriptor, and reduces the number of indirect branches.. A consequence of moving this data to the 'prep' routine is that multi-source routines like async_xor need temporary storage to convert an array of linear addresses into an array of dma addresses. In order to keep the same stack footprint of the previous implementation the input array is reused as storage for the dma addresses. This requires that sizeof(dma_addr_t) be less than or equal to sizeof(void *). As a consequence CONFIG_DMADEVICES now depends on !CONFIG_HIGHMEM64G. It also requires that drivers be able to make descriptor resources available when the 'prep' routine is polled. Signed-off-by: Dan Williams <dan.j.williams@intel.com> Acked-by: Shannon Nelson <shannon.nelson@intel.com> --- include/linux/dmaengine.h | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-) (limited to 'include') diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index 5c84bf8..b0864f5 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -209,8 +209,6 @@ typedef void (*dma_async_tx_callback)(void *dma_async_param); * descriptors * @chan: target channel for this operation * @tx_submit: set the prepared descriptor(s) to be executed by the engine - * @tx_set_dest: set a destination address in a hardware descriptor - * @tx_set_src: set a source address in a hardware descriptor * @callback: routine to call after this operation is complete * @callback_param: general parameter to pass to the callback routine * ---async_tx api specific fields--- @@ -227,10 +225,6 @@ struct dma_async_tx_descriptor { struct list_head tx_list; struct dma_chan *chan; dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx); - void (*tx_set_dest)(dma_addr_t addr, - struct dma_async_tx_descriptor *tx, int index); - void (*tx_set_src)(dma_addr_t addr, - struct dma_async_tx_descriptor *tx, int index); dma_async_tx_callback callback; void *callback_param; struct list_head depend_list; @@ -279,15 +273,17 @@ struct dma_device { void (*device_free_chan_resources)(struct dma_chan *chan); struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)( - struct dma_chan *chan, size_t len, int int_en); + struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, + size_t len, int int_en); struct dma_async_tx_descriptor *(*device_prep_dma_xor)( - struct dma_chan *chan, unsigned int src_cnt, size_t len, - int int_en); + struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, + unsigned int src_cnt, size_t len, int int_en); struct dma_async_tx_descriptor *(*device_prep_dma_zero_sum)( - struct dma_chan *chan, unsigned int src_cnt, size_t len, - u32 *result, int int_en); + struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt, + size_t len, u32 *result, int int_en); struct dma_async_tx_descriptor *(*device_prep_dma_memset)( - struct dma_chan *chan, int value, size_t len, int int_en); + struct dma_chan *chan, dma_addr_t dest, int value, size_t len, + int int_en); struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)( struct dma_chan *chan); -- cgit v1.1 From d4c56f97ff21df405d0cebe11f49e3c3c79662b5 Mon Sep 17 00:00:00 2001 From: Dan Williams <dan.j.williams@intel.com> Date: Sat, 2 Feb 2008 19:49:58 -0700 Subject: async_tx: replace 'int_en' with operation preparation flags Pass a full set of flags to drivers' per-operation 'prep' routines. Currently the only flag passed is DMA_PREP_INTERRUPT. The expectation is that arch-specific async_tx_find_channel() implementations can exploit this capability to find the best channel for an operation. Signed-off-by: Dan Williams <dan.j.williams@intel.com> Acked-by: Shannon Nelson <shannon.nelson@intel.com> Reviewed-by: Haavard Skinnemoen <hskinnemoen@atmel.com> --- include/asm-arm/arch-iop13xx/adma.h | 18 ++++++++++-------- include/asm-arm/hardware/iop3xx-adma.h | 30 +++++++++++++++++------------- include/linux/dmaengine.h | 17 +++++++++++++---- 3 files changed, 40 insertions(+), 25 deletions(-) (limited to 'include') diff --git a/include/asm-arm/arch-iop13xx/adma.h b/include/asm-arm/arch-iop13xx/adma.h index 04006c1..efd9a5e 100644 --- a/include/asm-arm/arch-iop13xx/adma.h +++ b/include/asm-arm/arch-iop13xx/adma.h @@ -247,7 +247,7 @@ static inline u32 iop_desc_get_src_count(struct iop_adma_desc_slot *desc, } static inline void -iop_desc_init_memcpy(struct iop_adma_desc_slot *desc, int int_en) +iop_desc_init_memcpy(struct iop_adma_desc_slot *desc, unsigned long flags) { struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; union { @@ -257,13 +257,13 @@ iop_desc_init_memcpy(struct iop_adma_desc_slot *desc, int int_en) u_desc_ctrl.value = 0; u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */ - u_desc_ctrl.field.int_en = int_en; + u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; hw_desc->desc_ctrl = u_desc_ctrl.value; hw_desc->crc_addr = 0; } static inline void -iop_desc_init_memset(struct iop_adma_desc_slot *desc, int int_en) +iop_desc_init_memset(struct iop_adma_desc_slot *desc, unsigned long flags) { struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; union { @@ -274,14 +274,15 @@ iop_desc_init_memset(struct iop_adma_desc_slot *desc, int int_en) u_desc_ctrl.value = 0; u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */ u_desc_ctrl.field.block_fill_en = 1; - u_desc_ctrl.field.int_en = int_en; + u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; hw_desc->desc_ctrl = u_desc_ctrl.value; hw_desc->crc_addr = 0; } /* to do: support buffers larger than ADMA_MAX_BYTE_COUNT */ static inline void -iop_desc_init_xor(struct iop_adma_desc_slot *desc, int src_cnt, int int_en) +iop_desc_init_xor(struct iop_adma_desc_slot *desc, int src_cnt, + unsigned long flags) { struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; union { @@ -292,7 +293,7 @@ iop_desc_init_xor(struct iop_adma_desc_slot *desc, int src_cnt, int int_en) u_desc_ctrl.value = 0; u_desc_ctrl.field.src_select = src_cnt - 1; u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */ - u_desc_ctrl.field.int_en = int_en; + u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; hw_desc->desc_ctrl = u_desc_ctrl.value; hw_desc->crc_addr = 0; @@ -301,7 +302,8 @@ iop_desc_init_xor(struct iop_adma_desc_slot *desc, int src_cnt, int int_en) /* to do: support buffers larger than ADMA_MAX_BYTE_COUNT */ static inline int -iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt, int int_en) +iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt, + unsigned long flags) { struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc; union { @@ -314,7 +316,7 @@ iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt, int int_en) u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */ u_desc_ctrl.field.zero_result = 1; u_desc_ctrl.field.status_write_back_en = 1; - u_desc_ctrl.field.int_en = int_en; + u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; hw_desc->desc_ctrl = u_desc_ctrl.value; hw_desc->crc_addr = 0; diff --git a/include/asm-arm/hardware/iop3xx-adma.h b/include/asm-arm/hardware/iop3xx-adma.h index 10834b5..5c529e6 100644 --- a/include/asm-arm/hardware/iop3xx-adma.h +++ b/include/asm-arm/hardware/iop3xx-adma.h @@ -414,7 +414,7 @@ static inline void iop3xx_aau_desc_set_src_addr(struct iop3xx_desc_aau *hw_desc, } static inline void -iop_desc_init_memcpy(struct iop_adma_desc_slot *desc, int int_en) +iop_desc_init_memcpy(struct iop_adma_desc_slot *desc, unsigned long flags) { struct iop3xx_desc_dma *hw_desc = desc->hw_desc; union { @@ -425,14 +425,14 @@ iop_desc_init_memcpy(struct iop_adma_desc_slot *desc, int int_en) u_desc_ctrl.value = 0; u_desc_ctrl.field.mem_to_mem_en = 1; u_desc_ctrl.field.pci_transaction = 0xe; /* memory read block */ - u_desc_ctrl.field.int_en = int_en; + u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; hw_desc->desc_ctrl = u_desc_ctrl.value; hw_desc->upper_pci_src_addr = 0; hw_desc->crc_addr = 0; } static inline void -iop_desc_init_memset(struct iop_adma_desc_slot *desc, int int_en) +iop_desc_init_memset(struct iop_adma_desc_slot *desc, unsigned long flags) { struct iop3xx_desc_aau *hw_desc = desc->hw_desc; union { @@ -443,12 +443,13 @@ iop_desc_init_memset(struct iop_adma_desc_slot *desc, int int_en) u_desc_ctrl.value = 0; u_desc_ctrl.field.blk1_cmd_ctrl = 0x2; /* memory block fill */ u_desc_ctrl.field.dest_write_en = 1; - u_desc_ctrl.field.int_en = int_en; + u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; hw_desc->desc_ctrl = u_desc_ctrl.value; } static inline u32 -iop3xx_desc_init_xor(struct iop3xx_desc_aau *hw_desc, int src_cnt, int int_en) +iop3xx_desc_init_xor(struct iop3xx_desc_aau *hw_desc, int src_cnt, + unsigned long flags) { int i, shift; u32 edcr; @@ -509,21 +510,23 @@ iop3xx_desc_init_xor(struct iop3xx_desc_aau *hw_desc, int src_cnt, int int_en) u_desc_ctrl.field.dest_write_en = 1; u_desc_ctrl.field.blk1_cmd_ctrl = 0x7; /* direct fill */ - u_desc_ctrl.field.int_en = int_en; + u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; hw_desc->desc_ctrl = u_desc_ctrl.value; return u_desc_ctrl.value; } static inline void -iop_desc_init_xor(struct iop_adma_desc_slot *desc, int src_cnt, int int_en) +iop_desc_init_xor(struct iop_adma_desc_slot *desc, int src_cnt, + unsigned long flags) { - iop3xx_desc_init_xor(desc->hw_desc, src_cnt, int_en); + iop3xx_desc_init_xor(desc->hw_desc, src_cnt, flags); } /* return the number of operations */ static inline int -iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt, int int_en) +iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt, + unsigned long flags) { int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op; struct iop3xx_desc_aau *hw_desc, *prev_hw_desc, *iter; @@ -538,10 +541,10 @@ iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt, int int_en) for (i = 0, j = 0; (slot_cnt -= slots_per_op) >= 0; i += slots_per_op, j++) { iter = iop_hw_desc_slot_idx(hw_desc, i); - u_desc_ctrl.value = iop3xx_desc_init_xor(iter, src_cnt, int_en); + u_desc_ctrl.value = iop3xx_desc_init_xor(iter, src_cnt, flags); u_desc_ctrl.field.dest_write_en = 0; u_desc_ctrl.field.zero_result_en = 1; - u_desc_ctrl.field.int_en = int_en; + u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; iter->desc_ctrl = u_desc_ctrl.value; /* for the subsequent descriptors preserve the store queue @@ -559,7 +562,8 @@ iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt, int int_en) } static inline void -iop_desc_init_null_xor(struct iop_adma_desc_slot *desc, int src_cnt, int int_en) +iop_desc_init_null_xor(struct iop_adma_desc_slot *desc, int src_cnt, + unsigned long flags) { struct iop3xx_desc_aau *hw_desc = desc->hw_desc; union { @@ -591,7 +595,7 @@ iop_desc_init_null_xor(struct iop_adma_desc_slot *desc, int src_cnt, int int_en) } u_desc_ctrl.field.dest_write_en = 0; - u_desc_ctrl.field.int_en = int_en; + u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; hw_desc->desc_ctrl = u_desc_ctrl.value; } diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index b0864f5..acbb364 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -95,6 +95,15 @@ enum dma_transaction_type { #define DMA_TX_TYPE_END (DMA_INTERRUPT + 1) /** + * enum dma_prep_flags - DMA flags to augment operation preparation + * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of + * this transaction + */ +enum dma_prep_flags { + DMA_PREP_INTERRUPT = (1 << 0), +}; + +/** * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t. * See linux/cpumask.h */ @@ -274,16 +283,16 @@ struct dma_device { struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)( struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, - size_t len, int int_en); + size_t len, unsigned long flags); struct dma_async_tx_descriptor *(*device_prep_dma_xor)( struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, - unsigned int src_cnt, size_t len, int int_en); + unsigned int src_cnt, size_t len, unsigned long flags); struct dma_async_tx_descriptor *(*device_prep_dma_zero_sum)( struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt, - size_t len, u32 *result, int int_en); + size_t len, u32 *result, unsigned long flags); struct dma_async_tx_descriptor *(*device_prep_dma_memset)( struct dma_chan *chan, dma_addr_t dest, int value, size_t len, - int int_en); + unsigned long flags); struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)( struct dma_chan *chan); -- cgit v1.1 From 47437b2c9a64315efeb3d84e97ffefd6c3c67ef1 Mon Sep 17 00:00:00 2001 From: Dan Williams <dan.j.williams@intel.com> Date: Sat, 2 Feb 2008 19:49:59 -0700 Subject: async_tx: allow architecture specific async_tx_find_channel implementations The source and destination addresses are included to allow channel selection based on address alignment. Signed-off-by: Dan Williams <dan.j.williams@intel.com> Reviewed-by: Haavard Skinnemoen <hskinnemoen@atmel.com> --- include/linux/async_tx.h | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/linux/async_tx.h b/include/linux/async_tx.h index 3d59d37..eb640f0 100644 --- a/include/linux/async_tx.h +++ b/include/linux/async_tx.h @@ -62,9 +62,15 @@ enum async_tx_flags { void async_tx_issue_pending_all(void); enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx); void async_tx_run_dependencies(struct dma_async_tx_descriptor *tx); +#ifdef CONFIG_ARCH_HAS_ASYNC_TX_FIND_CHANNEL +#include <asm/async_tx.h> +#else +#define async_tx_find_channel(dep, type, dst, dst_count, src, src_count, len) \ + __async_tx_find_channel(dep, type) struct dma_chan * -async_tx_find_channel(struct dma_async_tx_descriptor *depend_tx, +__async_tx_find_channel(struct dma_async_tx_descriptor *depend_tx, enum dma_transaction_type tx_type); +#endif /* CONFIG_ARCH_HAS_ASYNC_TX_FIND_CHANNEL */ #else static inline void async_tx_issue_pending_all(void) { @@ -86,7 +92,8 @@ async_tx_run_dependencies(struct dma_async_tx_descriptor *tx, static inline struct dma_chan * async_tx_find_channel(struct dma_async_tx_descriptor *depend_tx, - enum dma_transaction_type tx_type) + enum dma_transaction_type tx_type, struct page **dst, int dst_count, + struct page **src, int src_count, size_t len) { return NULL; } -- cgit v1.1