From 2b20b6164ec737bec67641564e477aa6e008748b Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Tue, 9 Dec 2014 22:36:50 +0000 Subject: soc/tegra: pmc: restrict compilation of suspend-related support to ARM Tegra SoCs with 64-bit ARM support don't currently support deep CPU low-power states in mainline Linux. When this support is added in the future, it will probably look rather different from the existing 32-bit ARM support, since the ARM64 maintainers' strong preference is to use PSCI to implement it. So, for the time being, prevent the CPU suspend-related code and data in the Tegra PMC driver from compiling on ARM64. Signed-off-by: Paul Walmsley Signed-off-by: Paul Walmsley Cc: Thierry Reding Cc: Allen Martin Cc: Stephen Warren Cc: Alexandre Courbot Signed-off-by: Thierry Reding --- include/soc/tegra/pm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/soc') diff --git a/include/soc/tegra/pm.h b/include/soc/tegra/pm.h index 30fe207..0390910 100644 --- a/include/soc/tegra/pm.h +++ b/include/soc/tegra/pm.h @@ -17,7 +17,7 @@ enum tegra_suspend_mode { TEGRA_MAX_SUSPEND_MODE, }; -#ifdef CONFIG_PM_SLEEP +#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) enum tegra_suspend_mode tegra_pm_validate_suspend_mode(enum tegra_suspend_mode mode); -- cgit v1.1 From 24ef5745dafc2eaf287a0bb9ee9e4ff9a4f64108 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 8 Jan 2015 08:24:45 +0100 Subject: soc/tegra: Add Tegra132 support Add the chip ID for the NVIDIA Tegra132 SoC family. Signed-off-by: Thierry Reding --- include/soc/tegra/fuse.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/soc') diff --git a/include/soc/tegra/fuse.h b/include/soc/tegra/fuse.h index 8e12494..b5f7b5f 100644 --- a/include/soc/tegra/fuse.h +++ b/include/soc/tegra/fuse.h @@ -21,6 +21,7 @@ #define TEGRA30 0x30 #define TEGRA114 0x35 #define TEGRA124 0x40 +#define TEGRA132 0x13 #define TEGRA_FUSE_SKU_CALIB_0 0xf0 #define TEGRA30_FUSE_SATA_CALIB 0x124 -- cgit v1.1 From 02f513a0970d97e4fc5f262f5a6c814014af524e Mon Sep 17 00:00:00 2001 From: Peter Rosin Date: Thu, 5 Feb 2015 14:02:09 +0800 Subject: pm: at91: Workaround DDRSDRC self-refresh bug with LPDDR1 memories. The DDRSDR controller fails miserably to put LPDDR1 memories in self-refresh. Force the controller to think it has DDR2 memories during the self-refresh period, as the DDR2 self-refresh spec is equivalent to LPDDR1, and is correctly implemented in the controller. Assume that the second controller has the same fault, but that is untested. Signed-off-by: Peter Rosin Acked-by: Nicolas Ferre Signed-off-by: Nicolas Ferre --- include/soc/at91/at91sam9_ddrsdr.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/soc') diff --git a/include/soc/at91/at91sam9_ddrsdr.h b/include/soc/at91/at91sam9_ddrsdr.h index 0210797..dc10c52 100644 --- a/include/soc/at91/at91sam9_ddrsdr.h +++ b/include/soc/at91/at91sam9_ddrsdr.h @@ -92,7 +92,7 @@ #define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */ #define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */ -#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */ +#define AT91_DDRSDRC_MD (7 << 0) /* Memory Device Type */ #define AT91_DDRSDRC_MD_SDR 0 #define AT91_DDRSDRC_MD_LOW_POWER_SDR 1 #define AT91_DDRSDRC_MD_LOW_POWER_DDR 3 -- cgit v1.1