From 703860ed4e36ded696bd44af6107243fdedfb746 Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Wed, 17 Apr 2013 16:57:56 -0600 Subject: PCI: Use u8, not int, for PM capability offset The Power Management Capability (PCI_CAP_ID_PM == 0x01) is defined by PCI and must appear in the 256-byte PCI Configuration Space from 0-0xff. It cannot be in the PCIe Extended Configuration space from 0x100-0xfff, so we only need a u8 to hold its offset. Signed-off-by: Bjorn Helgaas Acked-by: Rafael J. Wysocki --- include/linux/pci.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'include/linux/pci.h') diff --git a/include/linux/pci.h b/include/linux/pci.h index 2461033a..9587d4d 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -249,8 +249,7 @@ struct pci_dev { pci_power_t current_state; /* Current operating state. In ACPI-speak, this is D0-D3, D0 being fully functional, and D3 being off. */ - int pm_cap; /* PM capability offset in the - configuration space */ + u8 pm_cap; /* PM capability offset */ unsigned int pme_support:5; /* Bitmask of states from which PME# can be generated */ unsigned int pme_interrupt:1; -- cgit v1.1 From e375b561817d9ae098cc4296a729fc88924a0159 Mon Sep 17 00:00:00 2001 From: Gavin Shan Date: Thu, 4 Apr 2013 16:54:30 +0000 Subject: PCI: Cache MSI/MSI-X capability offsets in struct pci_dev The patch caches the MSI and MSI-X capability offset in PCI device (struct pci_dev) so that we needn't read it from the config space upon enabling or disabling MSI or MSI-X interrupts. [bhelgaas: moved pm_cap size change to separate patch] Signed-off-by: Gavin Shan Signed-off-by: Bjorn Helgaas --- include/linux/pci.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/linux/pci.h') diff --git a/include/linux/pci.h b/include/linux/pci.h index 9587d4d..b73c246 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -232,6 +232,8 @@ struct pci_dev { u8 revision; /* PCI revision, low byte of class word */ u8 hdr_type; /* PCI header type (`multi' flag masked out) */ u8 pcie_cap; /* PCI-E capability offset */ + u8 msi_cap; /* MSI capability offset */ + u8 msix_cap; /* MSI-X capability offset */ u8 pcie_mpss:3; /* PCI-E Max Payload Size Supported */ u8 rom_base_reg; /* which config register controls the ROM */ u8 pin; /* which interrupt pin this device uses */ -- cgit v1.1