From f78eae2e6f5d1eb05f76a45486286445b916bd92 Mon Sep 17 00:00:00 2001 From: "David S. Miller" Date: Mon, 4 Jun 2007 17:01:39 -0700 Subject: [SPARC64]: Proper multi-core scheduling support. The scheduling domain hierarchy is: all cpus --> cpus that share an instruction cache --> cpus that share an integer execution unit Signed-off-by: David S. Miller --- include/asm-sparc64/topology.h | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) (limited to 'include/asm-sparc64/topology.h') diff --git a/include/asm-sparc64/topology.h b/include/asm-sparc64/topology.h index e0d450d..4880f7c 100644 --- a/include/asm-sparc64/topology.h +++ b/include/asm-sparc64/topology.h @@ -1,12 +1,19 @@ #ifndef _ASM_SPARC64_TOPOLOGY_H #define _ASM_SPARC64_TOPOLOGY_H +#ifdef CONFIG_SMP #include -#define smt_capable() (tlb_type == hypervisor) - -#include +#define topology_physical_package_id(cpu) (cpu_data(cpu).proc_id) #define topology_core_id(cpu) (cpu_data(cpu).core_id) +#define topology_core_siblings(cpu) (cpu_core_map[cpu]) #define topology_thread_siblings(cpu) (cpu_sibling_map[cpu]) +#define mc_capable() (tlb_type == hypervisor) +#define smt_capable() (tlb_type == hypervisor) +#endif /* CONFIG_SMP */ + +#include + +#define cpu_coregroup_map(cpu) (cpu_core_map[cpu]) #endif /* _ASM_SPARC64_TOPOLOGY_H */ -- cgit v1.1