From 7f9f4678637f9ee1a999cc0870c4668f32e1a7eb Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Tue, 30 Jan 2007 11:16:16 +0100 Subject: [AVR32] Add PIOE device and reserve SDRAM pins The PIOE device was left out before because it muxes SDRAM pins (and is therefore a bit dangerous to mess with) and because no existing drivers had any use for it. It is needed for CompactFlash, however, and now that we have a way to protect the SDRAM pins, it can be safely added. Signed-off-by: Haavard Skinnemoen --- include/asm-avr32/arch-at32ap/at32ap7000.h | 2 ++ include/asm-avr32/arch-at32ap/irq.h | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) (limited to 'include/asm-avr32/arch-at32ap') diff --git a/include/asm-avr32/arch-at32ap/at32ap7000.h b/include/asm-avr32/arch-at32ap/at32ap7000.h index ba85e04..3914d7b 100644 --- a/include/asm-avr32/arch-at32ap/at32ap7000.h +++ b/include/asm-avr32/arch-at32ap/at32ap7000.h @@ -24,10 +24,12 @@ #define GPIO_PIOB_BASE (GPIO_PIOA_BASE + 32) #define GPIO_PIOC_BASE (GPIO_PIOB_BASE + 32) #define GPIO_PIOD_BASE (GPIO_PIOC_BASE + 32) +#define GPIO_PIOE_BASE (GPIO_PIOD_BASE + 32) #define GPIO_PIN_PA(N) (GPIO_PIOA_BASE + (N)) #define GPIO_PIN_PB(N) (GPIO_PIOB_BASE + (N)) #define GPIO_PIN_PC(N) (GPIO_PIOC_BASE + (N)) #define GPIO_PIN_PD(N) (GPIO_PIOD_BASE + (N)) +#define GPIO_PIN_PE(N) (GPIO_PIOE_BASE + (N)) #endif /* __ASM_ARCH_AT32AP7000_H__ */ diff --git a/include/asm-avr32/arch-at32ap/irq.h b/include/asm-avr32/arch-at32ap/irq.h index f8f7f45..5adffab 100644 --- a/include/asm-avr32/arch-at32ap/irq.h +++ b/include/asm-avr32/arch-at32ap/irq.h @@ -7,7 +7,7 @@ #define AT32_EXTINT(n) (EIM_IRQ_BASE + (n)) #define GPIO_IRQ_BASE (EIM_IRQ_BASE + NR_EIM_IRQS) -#define NR_GPIO_IRQS (4 * 32) +#define NR_GPIO_IRQS (5 * 32) #define NR_IRQS (GPIO_IRQ_BASE + NR_GPIO_IRQS) -- cgit v1.1