From e89c0e4377303a101d1032bf1dde822218372f15 Mon Sep 17 00:00:00 2001 From: David Brown Date: Thu, 12 Apr 2012 11:36:50 -0700 Subject: video: msm: Fix section mismatches in mddi.c The change commit 461cbe77d0a4f887c33a3a95ea68a7daf23b4302 Author: Gregory Bean Date: Wed Jul 28 10:22:13 2010 -0700 video: msm: Fix section mismatch in mddi.c. fixes a section mismatch between the board file and the driver's probe function, however, it misses the additional mismatches between the probe function and some routines it calls. Fix these up as well. Signed-off-by: David Brown --- drivers/video/msm/mddi.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/video') diff --git a/drivers/video/msm/mddi.c b/drivers/video/msm/mddi.c index 4527cbf..b061d70 100644 --- a/drivers/video/msm/mddi.c +++ b/drivers/video/msm/mddi.c @@ -420,7 +420,7 @@ static void mddi_resume(struct msm_mddi_client_data *cdata) mddi_set_auto_hibernate(&mddi->client_data, 1); } -static int __init mddi_get_client_caps(struct mddi_info *mddi) +static int __devinit mddi_get_client_caps(struct mddi_info *mddi) { int i, j; @@ -622,9 +622,9 @@ uint32_t mddi_remote_read(struct msm_mddi_client_data *cdata, uint32_t reg) static struct mddi_info mddi_info[2]; -static int __init mddi_clk_setup(struct platform_device *pdev, - struct mddi_info *mddi, - unsigned long clk_rate) +static int __devinit mddi_clk_setup(struct platform_device *pdev, + struct mddi_info *mddi, + unsigned long clk_rate) { int ret; -- cgit v1.1 From a8081d317978416197295df22fc2ea71e4812f50 Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Thu, 8 Mar 2012 12:52:38 +0200 Subject: OMAPDSS: Ensure OPP100 when DSS is operational Most of the DSS clocks have restrictions on their frequency based on the OPP in use. For example, maximum frequency for a clock may be 180MHz in OPP100, but 90MHz in OPP50. This means that when a high enough pixel clock or function clock is required, we need to use OPP100. However, there's currently no way in the PM framework to make that kind of request. The closest we get is to ask for very high bus throughput from the PM framework, which should effectively force OPP100. This patch is a simple version for handling the problem. Instead of asking for OPP100 only when needed, this patch asks for OPP100 whenever DSS is active. This obviously is not an optimal solution for cases with small displays where OPP50 would work just fine. However, a proper solution is a complex one, and this patch is a short term solution for the problem. Signed-off-by: Tomi Valkeinen Cc: Paul Walmsley Acked-by: Kevin Hilman --- drivers/video/omap2/dss/core.c | 10 ++++++++++ drivers/video/omap2/dss/dss.c | 13 +++++++++++++ drivers/video/omap2/dss/dss.h | 1 + 3 files changed, 24 insertions(+) (limited to 'drivers/video') diff --git a/drivers/video/omap2/dss/core.c b/drivers/video/omap2/dss/core.c index e8a1207..5ad8cc7 100644 --- a/drivers/video/omap2/dss/core.c +++ b/drivers/video/omap2/dss/core.c @@ -87,6 +87,16 @@ struct regulator *dss_get_vdds_sdi(void) return reg; } +int dss_set_min_bus_tput(struct device *dev, unsigned long tput) +{ + struct omap_dss_board_info *pdata = core.pdev->dev.platform_data; + + if (pdata->set_min_bus_tput) + return pdata->set_min_bus_tput(dev, tput); + else + return 0; +} + #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) static int dss_debug_show(struct seq_file *s, void *unused) { diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c index bd2d5e1..e731aa4 100644 --- a/drivers/video/omap2/dss/dss.c +++ b/drivers/video/omap2/dss/dss.c @@ -829,11 +829,24 @@ static int omap_dsshw_remove(struct platform_device *pdev) static int dss_runtime_suspend(struct device *dev) { dss_save_context(); + dss_set_min_bus_tput(dev, 0); return 0; } static int dss_runtime_resume(struct device *dev) { + int r; + /* + * Set an arbitrarily high tput request to ensure OPP100. + * What we should really do is to make a request to stay in OPP100, + * without any tput requirements, but that is not currently possible + * via the PM layer. + */ + + r = dss_set_min_bus_tput(dev, 1000000000); + if (r) + return r; + dss_restore_context(); return 0; } diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h index d4b3dff..42f8f62 100644 --- a/drivers/video/omap2/dss/dss.h +++ b/drivers/video/omap2/dss/dss.h @@ -162,6 +162,7 @@ struct platform_device; struct bus_type *dss_get_bus(void); struct regulator *dss_get_vdds_dsi(void); struct regulator *dss_get_vdds_sdi(void); +int dss_set_min_bus_tput(struct device *dev, unsigned long tput); /* apply */ void dss_apply_init(void); -- cgit v1.1 From b6e695abe710ee1ae248463d325169efac487e17 Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Thu, 15 Mar 2012 15:22:58 +0200 Subject: OMAPDSS: DSI: remove option to use pck for DSI PLL clkin For some OMAP versions the TRM says that the pixel clock from DISPC can be used as an input clock for DSI PLL, instead of the default, which is sysclk. For some OMAP versions the bits affecting this are marked as reserved. This feature has never been tested, so it's unknown if the HW even works, and has never been used. To clean things up, this patch removes the functionality. This should not affect any board. Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dsi.c | 57 +++++++++---------------------------------- drivers/video/omap2/dss/dss.h | 3 --- 2 files changed, 12 insertions(+), 48 deletions(-) (limited to 'drivers/video') diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c index 662d14f..0d2c53f 100644 --- a/drivers/video/omap2/dss/dsi.c +++ b/drivers/video/omap2/dss/dsi.c @@ -1279,10 +1279,9 @@ static int dsi_pll_power(struct platform_device *dsidev, } /* calculate clock rates using dividers in cinfo */ -static int dsi_calc_clock_rates(struct omap_dss_device *dssdev, +static int dsi_calc_clock_rates(struct platform_device *dsidev, struct dsi_clock_info *cinfo) { - struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); if (cinfo->regn == 0 || cinfo->regn > dsi->regn_max) @@ -1297,21 +1296,8 @@ static int dsi_calc_clock_rates(struct omap_dss_device *dssdev, if (cinfo->regm_dsi > dsi->regm_dsi_max) return -EINVAL; - if (cinfo->use_sys_clk) { - cinfo->clkin = clk_get_rate(dsi->sys_clk); - /* XXX it is unclear if highfreq should be used - * with DSS_SYS_CLK source also */ - cinfo->highfreq = 0; - } else { - cinfo->clkin = dispc_mgr_pclk_rate(dssdev->manager->id); - - if (cinfo->clkin < 32000000) - cinfo->highfreq = 0; - else - cinfo->highfreq = 1; - } - - cinfo->fint = cinfo->clkin / (cinfo->regn * (cinfo->highfreq ? 2 : 1)); + cinfo->clkin = clk_get_rate(dsi->sys_clk); + cinfo->fint = cinfo->clkin / cinfo->regn; if (cinfo->fint > dsi->fint_max || cinfo->fint < dsi->fint_min) return -EINVAL; @@ -1378,27 +1364,21 @@ retry: memset(&cur, 0, sizeof(cur)); cur.clkin = dss_sys_clk; - cur.use_sys_clk = 1; - cur.highfreq = 0; - /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */ - /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */ + /* 0.75MHz < Fint = clkin / regn < 2.1MHz */ /* To reduce PLL lock time, keep Fint high (around 2 MHz) */ for (cur.regn = 1; cur.regn < dsi->regn_max; ++cur.regn) { - if (cur.highfreq == 0) - cur.fint = cur.clkin / cur.regn; - else - cur.fint = cur.clkin / (2 * cur.regn); + cur.fint = cur.clkin / cur.regn; if (cur.fint > dsi->fint_max || cur.fint < dsi->fint_min) continue; - /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */ + /* DSIPHY(MHz) = (2 * regm / regn) * clkin */ for (cur.regm = 1; cur.regm < dsi->regm_max; ++cur.regm) { unsigned long a, b; a = 2 * cur.regm * (cur.clkin/1000); - b = cur.regn * (cur.highfreq + 1); + b = cur.regn; cur.clkin4ddr = a / b * 1000; if (cur.clkin4ddr > 1800 * 1000 * 1000) @@ -1486,9 +1466,7 @@ int dsi_pll_set_clock_div(struct platform_device *dsidev, DSSDBGF(); - dsi->current_cinfo.use_sys_clk = cinfo->use_sys_clk; - dsi->current_cinfo.highfreq = cinfo->highfreq; - + dsi->current_cinfo.clkin = cinfo->clkin; dsi->current_cinfo.fint = cinfo->fint; dsi->current_cinfo.clkin4ddr = cinfo->clkin4ddr; dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk = @@ -1503,17 +1481,13 @@ int dsi_pll_set_clock_div(struct platform_device *dsidev, DSSDBG("DSI Fint %ld\n", cinfo->fint); - DSSDBG("clkin (%s) rate %ld, highfreq %d\n", - cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree", - cinfo->clkin, - cinfo->highfreq); + DSSDBG("clkin rate %ld\n", cinfo->clkin); /* DSIPHY == CLKIN4DDR */ - DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu / %d = %lu\n", + DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu = %lu\n", cinfo->regm, cinfo->regn, cinfo->clkin, - cinfo->highfreq + 1, cinfo->clkin4ddr); DSSDBG("Data rate on 1 DSI lane %ld Mbps\n", @@ -1568,10 +1542,6 @@ int dsi_pll_set_clock_div(struct platform_device *dsidev, if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */ - l = FLD_MOD(l, cinfo->use_sys_clk ? 0 : 1, - 11, 11); /* DSI_PLL_CLKSEL */ - l = FLD_MOD(l, cinfo->highfreq, - 12, 12); /* DSI_PLL_HIGHFREQ */ l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */ l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */ l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */ @@ -1726,8 +1696,7 @@ static void dsi_dump_dsidev_clocks(struct platform_device *dsidev, seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1); - seq_printf(s, "dsi pll source = %s\n", - cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree"); + seq_printf(s, "dsi pll clkin\t%lu\n", cinfo->clkin); seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn); @@ -4285,13 +4254,11 @@ static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev) struct dsi_clock_info cinfo; int r; - /* we always use DSS_CLK_SYSCK as input clock */ - cinfo.use_sys_clk = true; cinfo.regn = dssdev->clocks.dsi.regn; cinfo.regm = dssdev->clocks.dsi.regm; cinfo.regm_dispc = dssdev->clocks.dsi.regm_dispc; cinfo.regm_dsi = dssdev->clocks.dsi.regm_dsi; - r = dsi_calc_clock_rates(dssdev, &cinfo); + r = dsi_calc_clock_rates(dsidev, &cinfo); if (r) { DSSERR("Failed to calc dsi clocks\n"); return r; diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h index 42f8f62..7080f5f 100644 --- a/drivers/video/omap2/dss/dss.h +++ b/drivers/video/omap2/dss/dss.h @@ -150,9 +150,6 @@ struct dsi_clock_info { u16 regm_dsi; /* OMAP3: REGM4 * OMAP4: REGM5 */ u16 lp_clk_div; - - u8 highfreq; - bool use_sys_clk; }; struct seq_file; -- cgit v1.1 From 9c3d5eb71b1fdcdef434a46444d931ada6938446 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Mon, 19 Mar 2012 14:50:46 +0000 Subject: OMAP: DSS2: Remove suspicous and unused TAAL regulator API usage The TAAL driver contains some regulator support which is currently unused (the code is there but the one panel supported by the driver doesn't have any regulators provided). This code mostly looks like an open coded version of the regulator core bulk API. The only additional feature is that a voltage range can be set once when the device is opened, though this is never varied at runtime. The general expectation is that if the device is not actively managing the voltage of the device (eg, doing DVFS) then any configuration will be done using the constraints rather than by drivers, saving them code and ensuring that they work well with systems where the voltage is not configurable. If systems are added needing regulator support this can be added back in, though it should be based on core features rather than open coding things. Signed-off-by: Mark Brown Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/displays/panel-taal.c | 80 ------------------------------- 1 file changed, 80 deletions(-) (limited to 'drivers/video') diff --git a/drivers/video/omap2/displays/panel-taal.c b/drivers/video/omap2/displays/panel-taal.c index 0f21fa5..72d6307 100644 --- a/drivers/video/omap2/displays/panel-taal.c +++ b/drivers/video/omap2/displays/panel-taal.c @@ -30,7 +30,6 @@ #include #include #include -#include #include #include