From d0f58bd3bba3877fb1af4664c4e33273d36f00e4 Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Thu, 31 Oct 2013 14:44:23 +0200 Subject: OMAPDSS: remove struct dss_clock_info Remove struct dss_clock_info, as it is not usable in a case where DSS fclk comes from a dedicated PLL. Instead, just use the fclk rate in place of dss_clock_info, as that is all that's needed. Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dss.h | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) (limited to 'drivers/video/omap2/dss/dss.h') diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h index e172531..ead1960 100644 --- a/drivers/video/omap2/dss/dss.h +++ b/drivers/video/omap2/dss/dss.h @@ -100,14 +100,6 @@ enum dss_writeback_channel { DSS_WB_LCD3_MGR = 7, }; -struct dss_clock_info { - /* rates that we get with dividers below */ - unsigned long fck; - - /* dividers */ - u16 fck_div; -}; - struct dispc_clock_info { /* rates that we get with dividers below */ unsigned long lck; @@ -251,10 +243,9 @@ void dss_set_venc_output(enum omap_dss_venc_type type); void dss_set_dac_pwrdn_bgz(bool enable); unsigned long dss_get_dpll4_rate(void); -int dss_calc_clock_rates(struct dss_clock_info *cinfo); -int dss_set_clock_div(struct dss_clock_info *cinfo); +int dss_set_fck_rate(unsigned long rate); -typedef bool (*dss_div_calc_func)(int fckd, unsigned long fck, void *data); +typedef bool (*dss_div_calc_func)(unsigned long fck, void *data); bool dss_div_calc(unsigned long fck_min, dss_div_calc_func func, void *data); /* SDI */ -- cgit v1.1 From ada9443ff407f83a96abc15ea44a106250dd23f2 Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Thu, 31 Oct 2013 16:06:38 +0200 Subject: OMAPDSS: cleanup fck parent handling The dss parent_clk_name currently points to a clock node which we use to change the fclk rate. Now that we have CLK_SET_RATE_PARENT properly set, we can set the rate directly to the fclk node. However, we still need to calculate the possible clock rates. For this, we need the rate of the parent of the current parent_clk. To simplify the code, this patch changes the parent_clk_name to point to the above mentioned parent, so that we can get the rate directly. Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dss.h | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/video/omap2/dss/dss.h') diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h index ead1960..6fc786f 100644 --- a/drivers/video/omap2/dss/dss.h +++ b/drivers/video/omap2/dss/dss.h @@ -242,7 +242,6 @@ enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel); void dss_set_venc_output(enum omap_dss_venc_type type); void dss_set_dac_pwrdn_bgz(bool enable); -unsigned long dss_get_dpll4_rate(void); int dss_set_fck_rate(unsigned long rate); typedef bool (*dss_div_calc_func)(unsigned long fck, void *data); -- cgit v1.1 From 688af02d22c11a077532d6437e4afc7bdc972f82 Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Thu, 31 Oct 2013 16:41:57 +0200 Subject: OMAPDSS: pass pck to dss fck clock calc We need the required pixel clock rate when calculating the dss fclk on SoCs that have a dedicated DSS PLL. This patch changes the code to pass the pck to the calc functions. The pck rate is taken into use in the next patch. Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dss.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/video/omap2/dss/dss.h') diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h index 6fc786f..2acc661 100644 --- a/drivers/video/omap2/dss/dss.h +++ b/drivers/video/omap2/dss/dss.h @@ -245,7 +245,8 @@ void dss_set_dac_pwrdn_bgz(bool enable); int dss_set_fck_rate(unsigned long rate); typedef bool (*dss_div_calc_func)(unsigned long fck, void *data); -bool dss_div_calc(unsigned long fck_min, dss_div_calc_func func, void *data); +bool dss_div_calc(unsigned long pck, unsigned long fck_min, + dss_div_calc_func func, void *data); /* SDI */ int sdi_init_platform_driver(void) __init; -- cgit v1.1