From 33f13120e59cb4eddedc09039d8602d94aa864b4 Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Mon, 15 Sep 2014 15:40:47 +0300 Subject: OMAPDSS: HDMI: rewrite HDMI PLL calculation code The code calculating HDMI PLL parameters has always been very confusing. Now that we are implementing a common PLL library for the DSS, it's important that the PLL code is understandable. This patch rewrites the calculation code, and removes a few hacks that were used there. Signed-off-by: Tomi Valkeinen --- drivers/video/fbdev/omap2/dss/hdmi4.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) (limited to 'drivers/video/fbdev/omap2/dss/hdmi4.c') diff --git a/drivers/video/fbdev/omap2/dss/hdmi4.c b/drivers/video/fbdev/omap2/dss/hdmi4.c index 9a8713c..1f2fbcc 100644 --- a/drivers/video/fbdev/omap2/dss/hdmi4.c +++ b/drivers/video/fbdev/omap2/dss/hdmi4.c @@ -180,7 +180,6 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev) int r; struct omap_video_timings *p; struct omap_overlay_manager *mgr = hdmi.output.manager; - unsigned long phy; struct hdmi_wp_data *wp = &hdmi.wp; r = hdmi_power_on_core(dssdev); @@ -195,10 +194,7 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev) DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res); - /* the functions below use kHz pixel clock. TODO: change to Hz */ - phy = p->pixelclock / 1000; - - hdmi_pll_compute(&hdmi.pll, clk_get_rate(hdmi.sys_clk), phy); + hdmi_pll_compute(&hdmi.pll, clk_get_rate(hdmi.sys_clk), p->pixelclock); /* config the PLL and PHY hdmi_set_pll_pwrfirst */ r = hdmi_pll_enable(&hdmi.pll, &hdmi.wp); @@ -207,7 +203,8 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev) goto err_pll_enable; } - r = hdmi_phy_configure(&hdmi.phy, &hdmi.cfg); + r = hdmi_phy_configure(&hdmi.phy, hdmi.pll.info.clkdco, + hdmi.pll.info.clkout); if (r) { DSSDBG("Failed to configure PHY\n"); goto err_phy_cfg; -- cgit v1.1