From 2f85f97e460a4bcfad678151fcc13dbf0b8181b3 Mon Sep 17 00:00:00 2001 From: Ajay Kumar Date: Mon, 5 Nov 2012 16:47:00 +0900 Subject: video: exynos_dp: Fix incorrect setting for INT_CTL INT_CTL register contains bits INT_POL0 and INT_POL1, and not INT_POL. This patch fixes the wrong register setting for INT_CTL. Signed-off-by: Ajay Kumar Signed-off-by: Jingoo Han --- drivers/video/exynos/exynos_dp_reg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/video/exynos/exynos_dp_reg.c') diff --git a/drivers/video/exynos/exynos_dp_reg.c b/drivers/video/exynos/exynos_dp_reg.c index 9fb901b..93b4b6b 100644 --- a/drivers/video/exynos/exynos_dp_reg.c +++ b/drivers/video/exynos/exynos_dp_reg.c @@ -88,7 +88,7 @@ void exynos_dp_init_analog_param(struct exynos_dp_device *dp) void exynos_dp_init_interrupt(struct exynos_dp_device *dp) { /* Set interrupt pin assertion polarity as high */ - writel(INT_POL, dp->reg_base + EXYNOS_DP_INT_CTL); + writel(INT_POL1 | INT_POL0, dp->reg_base + EXYNOS_DP_INT_CTL); /* Clear pending regisers */ writel(0xff, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1); -- cgit v1.1