From a49d25364dfb9f8a64037488a39ab1f56c5fa419 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Fri, 17 Feb 2017 16:55:17 +0000 Subject: staging/atomisp: Add support for the Intel IPU v2 This patch adds support for the Intel IPU v2 as found on Android and IoT Baytrail-T and Baytrail-CR platforms (those with the IPU PCI mapped). You will also need the firmware files from your device (Android usually puts them into /etc) - or you can find them in the downloadable restore/upgrade kits if you blew them away for some reason. It may be possible to extend the driver to handle the BYT/T windows platforms such as the ASUS T100TA. These platforms don't expose the IPU via the PCI interface but via ACPI buried in the GPU description and with the camera information somewhere unknown so would need a platform driver interface adding to the codebase *IFF* the firmware works on such devices. To get good results you also need a suitable support library such as libxcam. The camera is intended to be driven from Android so it has a lot of features that many desktop apps don't fully spport. In theory all the pieces are there to build it with -DISP2401 and some differing files to get CherryTrail/T support, but unifying the drivers properlly is a work in progress. The IPU driver represents the work of a lot of people within Intel over many years. It's historical goal was portability rather than Linux upstream. Any queries about the upstream aimed driver should be sent to me not to the original authors. Signed-off-by: Alan Cox Signed-off-by: Greg Kroah-Hartman --- .../kernels/sdis/common/ia_css_sdis_common.host.h | 99 +++++++++ .../kernels/sdis/common/ia_css_sdis_common_types.h | 232 +++++++++++++++++++++ .../isp/kernels/sdis/common/ia_css_sdis_param.h | 22 ++ 3 files changed, 353 insertions(+) create mode 100644 drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/common/ia_css_sdis_common.host.h create mode 100644 drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/common/ia_css_sdis_common_types.h create mode 100644 drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/common/ia_css_sdis_param.h (limited to 'drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/common') diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/common/ia_css_sdis_common.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/common/ia_css_sdis_common.host.h new file mode 100644 index 0000000..4eb4910 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/common/ia_css_sdis_common.host.h @@ -0,0 +1,99 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _IA_CSS_SDIS_COMMON_HOST_H +#define _IA_CSS_SDIS_COMMON_HOST_H + +#define ISP_MAX_SDIS_HOR_PROJ_NUM_ISP \ + __ISP_SDIS_HOR_PROJ_NUM_ISP(ISP_MAX_INTERNAL_WIDTH, ISP_MAX_INTERNAL_HEIGHT, \ + SH_CSS_DIS_DECI_FACTOR_LOG2, ISP_PIPE_VERSION) +#define ISP_MAX_SDIS_VER_PROJ_NUM_ISP \ + __ISP_SDIS_VER_PROJ_NUM_ISP(ISP_MAX_INTERNAL_WIDTH, \ + SH_CSS_DIS_DECI_FACTOR_LOG2) + +#define _ISP_SDIS_HOR_COEF_NUM_VECS \ + __ISP_SDIS_HOR_COEF_NUM_VECS(ISP_INTERNAL_WIDTH) +#define ISP_MAX_SDIS_HOR_COEF_NUM_VECS \ + __ISP_SDIS_HOR_COEF_NUM_VECS(ISP_MAX_INTERNAL_WIDTH) +#define ISP_MAX_SDIS_VER_COEF_NUM_VECS \ + __ISP_SDIS_VER_COEF_NUM_VECS(ISP_MAX_INTERNAL_HEIGHT) + +/* SDIS Coefficients: */ +/* The ISP uses vectors to store the coefficients, so we round + the number of coefficients up to vectors. */ +#define __ISP_SDIS_HOR_COEF_NUM_VECS(in_width) _ISP_VECS(_ISP_BQS(in_width)) +#define __ISP_SDIS_VER_COEF_NUM_VECS(in_height) _ISP_VECS(_ISP_BQS(in_height)) + +/* SDIS Projections: + * SDIS1: Horizontal projections are calculated for each line. + * Vertical projections are calculated for each column. + * SDIS2: Projections are calculated for each grid cell. + * Grid cells that do not fall completely within the image are not + * valid. The host needs to use the bigger one for the stride but + * should only return the valid ones to the 3A. */ +#define __ISP_SDIS_HOR_PROJ_NUM_ISP(in_width, in_height, deci_factor_log2, \ + isp_pipe_version) \ + ((isp_pipe_version == 1) ? \ + CEIL_SHIFT(_ISP_BQS(in_height), deci_factor_log2) : \ + CEIL_SHIFT(_ISP_BQS(in_width), deci_factor_log2)) + +#define __ISP_SDIS_VER_PROJ_NUM_ISP(in_width, deci_factor_log2) \ + CEIL_SHIFT(_ISP_BQS(in_width), deci_factor_log2) + +#define SH_CSS_DIS_VER_NUM_COEF_TYPES(b) \ + (((b)->info->sp.pipeline.isp_pipe_version == 2) ? \ + IA_CSS_DVS2_NUM_COEF_TYPES : \ + IA_CSS_DVS_NUM_COEF_TYPES) + +#ifndef PIPE_GENERATION +#if defined(__ISP) || defined (MK_FIRMWARE) + +/* Array cannot be 2-dimensional, since driver ddr allocation does not know stride */ +struct sh_css_isp_sdis_hori_proj_tbl { + int32_t tbl[ISP_DVS_NUM_COEF_TYPES * ISP_MAX_SDIS_HOR_PROJ_NUM_ISP]; +#if DVS2_PROJ_MARGIN > 0 + int32_t margin[DVS2_PROJ_MARGIN]; +#endif +}; + +struct sh_css_isp_sdis_vert_proj_tbl { + int32_t tbl[ISP_DVS_NUM_COEF_TYPES * ISP_MAX_SDIS_VER_PROJ_NUM_ISP]; +#if DVS2_PROJ_MARGIN > 0 + int32_t margin[DVS2_PROJ_MARGIN]; +#endif +}; + +struct sh_css_isp_sdis_hori_coef_tbl { + VMEM_ARRAY(tbl[ISP_DVS_NUM_COEF_TYPES], ISP_MAX_SDIS_HOR_COEF_NUM_VECS*ISP_NWAY); +}; + +struct sh_css_isp_sdis_vert_coef_tbl { + VMEM_ARRAY(tbl[ISP_DVS_NUM_COEF_TYPES], ISP_MAX_SDIS_VER_COEF_NUM_VECS*ISP_NWAY); +}; + +#endif /* defined(__ISP) || defined (MK_FIRMWARE) */ +#endif /* PIPE_GENERATION */ + +#ifndef PIPE_GENERATION +struct s_sdis_config { + unsigned horicoef_vectors; + unsigned vertcoef_vectors; + unsigned horiproj_num; + unsigned vertproj_num; +}; + +extern struct s_sdis_config sdis_config; +#endif + +#endif /* _IA_CSS_SDIS_COMMON_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/common/ia_css_sdis_common_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/common/ia_css_sdis_common_types.h new file mode 100644 index 0000000..295dc60 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/common/ia_css_sdis_common_types.h @@ -0,0 +1,232 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_SDIS_COMMON_TYPES_H +#define __IA_CSS_SDIS_COMMON_TYPES_H + +/** @file +* CSS-API header file for DVS statistics parameters. +*/ + +#include + +/** DVS statistics grid dimensions in number of cells. + */ + +struct ia_css_dvs_grid_dim { + uint32_t width; /**< Width of DVS grid table in cells */ + uint32_t height; /**< Height of DVS grid table in cells */ +}; + +/** DVS statistics dimensions in number of cells for + * grid, coeffieicient and projection. + */ + +struct ia_css_sdis_info { + struct { + struct ia_css_dvs_grid_dim dim; /* Dimensions */ + struct ia_css_dvs_grid_dim pad; /* Padded dimensions */ + } grid, coef, proj; + uint32_t deci_factor_log2; +}; + +#define IA_CSS_DEFAULT_SDIS_INFO \ + { \ + { { 0, 0 }, /* dim */ \ + { 0, 0 }, /* pad */ \ + }, /* grid */ \ + { { 0, 0 }, /* dim */ \ + { 0, 0 }, /* pad */ \ + }, /* coef */ \ + { { 0, 0 }, /* dim */ \ + { 0, 0 }, /* pad */ \ + }, /* proj */ \ + 0, /* dis_deci_factor_log2 */ \ + } + +/** DVS statistics grid + * + * ISP block: SDVS1 (DIS/DVS Support for DIS/DVS ver.1 (2-axes)) + * SDVS2 (DVS Support for DVS ver.2 (6-axes)) + * ISP1: SDVS1 is used. + * ISP2: SDVS2 is used. + */ +struct ia_css_dvs_grid_res { + uint32_t width; /**< Width of DVS grid table. + (= Horizontal number of grid cells + in table, which cells have effective + statistics.) + For DVS1, this is equal to + the number of vertical statistics. */ + uint32_t aligned_width; /**< Stride of each grid line. + (= Horizontal number of grid cells + in table, which means + the allocated width.) */ + uint32_t height; /**< Height of DVS grid table. + (= Vertical number of grid cells + in table, which cells have effective + statistics.) + For DVS1, This is equal to + the number of horizontal statistics. */ + uint32_t aligned_height;/**< Stride of each grid column. + (= Vertical number of grid cells + in table, which means + the allocated height.) */ +}; + +/* TODO: use ia_css_dvs_grid_res in here. + * However, that implies driver I/F changes + */ +struct ia_css_dvs_grid_info { + uint32_t enable; /**< DVS statistics enabled. + 0:disabled, 1:enabled */ + uint32_t width; /**< Width of DVS grid table. + (= Horizontal number of grid cells + in table, which cells have effective + statistics.) + For DVS1, this is equal to + the number of vertical statistics. */ + uint32_t aligned_width; /**< Stride of each grid line. + (= Horizontal number of grid cells + in table, which means + the allocated width.) */ + uint32_t height; /**< Height of DVS grid table. + (= Vertical number of grid cells + in table, which cells have effective + statistics.) + For DVS1, This is equal to + the number of horizontal statistics. */ + uint32_t aligned_height;/**< Stride of each grid column. + (= Vertical number of grid cells + in table, which means + the allocated height.) */ + uint32_t bqs_per_grid_cell; /**< Grid cell size in BQ(Bayer Quad) unit. + (1BQ means {Gr,R,B,Gb}(2x2 pixels).) + For DVS1, valid value is 64. + For DVS2, valid value is only 64, + currently. */ + uint32_t num_hor_coefs; /**< Number of horizontal coefficients. */ + uint32_t num_ver_coefs; /**< Number of vertical coefficients. */ +}; + +/** Number of DVS statistics levels + */ +#define IA_CSS_DVS_STAT_NUM_OF_LEVELS 3 + +/** DVS statistics generated by accelerator global configuration + */ +struct dvs_stat_public_dvs_global_cfg { + unsigned char kappa; + /**< DVS statistics global configuration - kappa */ + unsigned char match_shift; + /**< DVS statistics global configuration - match_shift */ + unsigned char ybin_mode; + /**< DVS statistics global configuration - y binning mode */ +}; + +/** DVS statistics generated by accelerator level grid + * configuration + */ +struct dvs_stat_public_dvs_level_grid_cfg { + unsigned char grid_width; + /**< DVS statistics grid width */ + unsigned char grid_height; + /**< DVS statistics grid height */ + unsigned char block_width; + /**< DVS statistics block width */ + unsigned char block_height; + /**< DVS statistics block height */ +}; + +/** DVS statistics generated by accelerator level grid start + * configuration + */ +struct dvs_stat_public_dvs_level_grid_start { + unsigned short x_start; + /**< DVS statistics level x start */ + unsigned short y_start; + /**< DVS statistics level y start */ + unsigned char enable; + /**< DVS statistics level enable */ +}; + +/** DVS statistics generated by accelerator level grid end + * configuration + */ +struct dvs_stat_public_dvs_level_grid_end { + unsigned short x_end; + /**< DVS statistics level x end */ + unsigned short y_end; + /**< DVS statistics level y end */ +}; + +/** DVS statistics generated by accelerator Feature Extraction + * Region Of Interest (FE-ROI) configuration + */ +struct dvs_stat_public_dvs_level_fe_roi_cfg { + unsigned char x_start; + /**< DVS statistics fe-roi level x start */ + unsigned char y_start; + /**< DVS statistics fe-roi level y start */ + unsigned char x_end; + /**< DVS statistics fe-roi level x end */ + unsigned char y_end; + /**< DVS statistics fe-roi level y end */ +}; + +/** DVS statistics generated by accelerator public configuration + */ +struct dvs_stat_public_dvs_grd_cfg { + struct dvs_stat_public_dvs_level_grid_cfg grd_cfg; + /**< DVS statistics level grid configuration */ + struct dvs_stat_public_dvs_level_grid_start grd_start; + /**< DVS statistics level grid start configuration */ + struct dvs_stat_public_dvs_level_grid_end grd_end; + /**< DVS statistics level grid end configuration */ +}; + +/** DVS statistics grid generated by accelerator + */ +struct ia_css_dvs_stat_grid_info { + struct dvs_stat_public_dvs_global_cfg dvs_gbl_cfg; + /**< DVS statistics global configuration (kappa, match, binning) */ + struct dvs_stat_public_dvs_grd_cfg grd_cfg[IA_CSS_DVS_STAT_NUM_OF_LEVELS]; + /**< DVS statistics grid configuration (blocks and grids) */ + struct dvs_stat_public_dvs_level_fe_roi_cfg fe_roi_cfg[IA_CSS_DVS_STAT_NUM_OF_LEVELS]; + /**< DVS statistics FE ROI (region of interest) configuration */ +}; + +/** DVS statistics generated by accelerator default grid info + */ +#define DEFAULT_DVS_GRID_INFO { \ +{ \ + { 0, 0, 0}, /* GBL CFG reg: kappa, match_shifrt, binning mode*/ \ + {{{0, 0, 0, 0}, {0, 0, 0}, {0, 0} }, \ + {{0, 0, 0, 0}, {0, 0, 0}, {0, 0} }, \ + {{0, 0, 0, 0}, {0, 0, 0}, {0, 0} } }, \ + {{0, 0, 0, 0}, {4, 0, 0, 0}, {0, 0, 0, 0} } } \ +} + + +/** Union that holds all types of DVS statistics grid info in + * CSS format + * */ +union ia_css_dvs_grid_u { + struct ia_css_dvs_stat_grid_info dvs_stat_grid_info; + /**< DVS statistics produced by accelerator grid info */ + struct ia_css_dvs_grid_info dvs_grid_info; + /**< DVS (DVS1/DVS2) grid info */ +}; + +#endif /* __IA_CSS_SDIS_COMMON_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/common/ia_css_sdis_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/common/ia_css_sdis_param.h new file mode 100644 index 0000000..586cc43 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/common/ia_css_sdis_param.h @@ -0,0 +1,22 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_SDIS_PARAM_COMMON_H +#define __IA_CSS_SDIS_PARAM_COMMON_H + + +#include "sdis/common/ia_css_sdis_common.host.h" + +#endif /* __IA_CSS_SDIS_PARAM_COMMON_H */ + -- cgit v1.1