From 5f1377d42bb89988fd9c86a92d1985320ff5053e Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Tue, 6 Oct 2009 15:47:55 +0100 Subject: Staging: et131x: PHY loopback cannot be set (and isn't useful for us anyway) Remove the stuff that falls out from this always being zero. Signed-off-by: Alan Cox Signed-off-by: Greg Kroah-Hartman --- drivers/staging/et131x/et1310_rx.c | 51 +++++++++++++++++--------------------- 1 file changed, 23 insertions(+), 28 deletions(-) (limited to 'drivers/staging/et131x/et1310_rx.c') diff --git a/drivers/staging/et131x/et1310_rx.c b/drivers/staging/et131x/et1310_rx.c index 10e21db..c0695b0 100644 --- a/drivers/staging/et131x/et1310_rx.c +++ b/drivers/staging/et131x/et1310_rx.c @@ -807,40 +807,35 @@ void et131x_rx_dma_disable(struct et131x_adapter *etdev) */ void et131x_rx_dma_enable(struct et131x_adapter *etdev) { - if (etdev->RegistryPhyLoopbk) - /* RxDMA is disabled for loopback operation. */ - writel(0x1, &etdev->regs->rxdma.csr.value); - else { /* Setup the receive dma configuration register for normal operation */ - RXDMA_CSR_t csr = { 0 }; - - csr.bits.fbr1_enable = 1; - if (etdev->RxRing.Fbr1BufferSize == 4096) - csr.bits.fbr1_size = 1; - else if (etdev->RxRing.Fbr1BufferSize == 8192) - csr.bits.fbr1_size = 2; - else if (etdev->RxRing.Fbr1BufferSize == 16384) - csr.bits.fbr1_size = 3; + RXDMA_CSR_t csr = { 0 }; + + csr.bits.fbr1_enable = 1; + if (etdev->RxRing.Fbr1BufferSize == 4096) + csr.bits.fbr1_size = 1; + else if (etdev->RxRing.Fbr1BufferSize == 8192) + csr.bits.fbr1_size = 2; + else if (etdev->RxRing.Fbr1BufferSize == 16384) + csr.bits.fbr1_size = 3; #ifdef USE_FBR0 - csr.bits.fbr0_enable = 1; - if (etdev->RxRing.Fbr0BufferSize == 256) - csr.bits.fbr0_size = 1; - else if (etdev->RxRing.Fbr0BufferSize == 512) - csr.bits.fbr0_size = 2; - else if (etdev->RxRing.Fbr0BufferSize == 1024) - csr.bits.fbr0_size = 3; + csr.bits.fbr0_enable = 1; + if (etdev->RxRing.Fbr0BufferSize == 256) + csr.bits.fbr0_size = 1; + else if (etdev->RxRing.Fbr0BufferSize == 512) + csr.bits.fbr0_size = 2; + else if (etdev->RxRing.Fbr0BufferSize == 1024) + csr.bits.fbr0_size = 3; #endif - writel(csr.value, &etdev->regs->rxdma.csr.value); + writel(csr.value, &etdev->regs->rxdma.csr.value); + csr.value = readl(&etdev->regs->rxdma.csr.value); + if (csr.bits.halt_status != 0) { + udelay(5); csr.value = readl(&etdev->regs->rxdma.csr.value); if (csr.bits.halt_status != 0) { - udelay(5); - csr.value = readl(&etdev->regs->rxdma.csr.value); - if (csr.bits.halt_status != 0) { - dev_err(&etdev->pdev->dev, - "RX Dma failed to exit halt state. CSR 0x%08x\n", - csr.value); - } + dev_err(&etdev->pdev->dev, + "RX Dma failed to exit halt state. CSR 0x%08x\n", + csr.value); } } } -- cgit v1.1