From 3ffad468cf1d9825b425733941bdad0d8d20e795 Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Tue, 16 May 2017 11:43:43 -0700 Subject: regulator: Allow for asymmetric settling times Some regulators have different settling times for voltage increases and decreases. To avoid a time penalty on the faster transition allow for different settings for up- and downward transitions. Signed-off-by: Matthias Kaehlcke Acked-by: Laxman Dewangan Signed-off-by: Mark Brown --- drivers/regulator/core.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers/regulator/core.c') diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c index c0d9ae8..919b7f1 100644 --- a/drivers/regulator/core.c +++ b/drivers/regulator/core.c @@ -2767,6 +2767,12 @@ static int _regulator_set_voltage_time(struct regulator_dev *rdev, ramp_delay = rdev->desc->ramp_delay; else if (rdev->constraints->settling_time) return rdev->constraints->settling_time; + else if (rdev->constraints->settling_time_up && + (new_uV > old_uV)) + return rdev->constraints->settling_time_up; + else if (rdev->constraints->settling_time_down && + (new_uV < old_uV)) + return rdev->constraints->settling_time_down; if (ramp_delay == 0) { rdev_dbg(rdev, "ramp_delay not set\n"); -- cgit v1.1