From 72f71afb86bcdbf9dc2261214bf346fad4e2efb0 Mon Sep 17 00:00:00 2001 From: Minghuan Lian Date: Fri, 16 Oct 2015 15:19:15 +0800 Subject: PCI: layerscape: Remove ls_pcie_establish_link() ls_pcie_establish_link() does not do any real operation, except to wait for the linkup establishment. In fact, this is not necessary. Moreover, each PCIe controller not inserted device will increase the Linux startup time about 200ms. Remove ls_pcie_establish_link(). Signed-off-by: Minghuan Lian Signed-off-by: Bjorn Helgaas --- drivers/pci/host/pci-layerscape.c | 16 ---------------- 1 file changed, 16 deletions(-) (limited to 'drivers/pci') diff --git a/drivers/pci/host/pci-layerscape.c b/drivers/pci/host/pci-layerscape.c index b2328ea1..6dd44a0 100644 --- a/drivers/pci/host/pci-layerscape.c +++ b/drivers/pci/host/pci-layerscape.c @@ -11,7 +11,6 @@ */ #include -#include #include #include #include @@ -62,27 +61,12 @@ static int ls_pcie_link_up(struct pcie_port *pp) return 1; } -static int ls_pcie_establish_link(struct pcie_port *pp) -{ - unsigned int retries; - - for (retries = 0; retries < 200; retries++) { - if (dw_pcie_link_up(pp)) - return 0; - usleep_range(100, 1000); - } - - dev_err(pp->dev, "phy link never came up\n"); - return -EINVAL; -} - static void ls_pcie_host_init(struct pcie_port *pp) { struct ls_pcie *pcie = to_ls_pcie(pp); u32 val; dw_pcie_setup_rc(pp); - ls_pcie_establish_link(pp); /* * LS1021A Workaround for internal TKT228622 -- cgit v1.1 From 7af4ce3571931bdc043c4220402262f817b9b968 Mon Sep 17 00:00:00 2001 From: Minghuan Lian Date: Fri, 16 Oct 2015 15:19:16 +0800 Subject: PCI: layerscape: Ignore PCIe controllers in Endpoint mode Layerscape PCIe controller supports root complex (RC) and endpoint (EP) modes, which can be set by RCW. If not in RC mode, return -ENODEV without claiming the controller. Signed-off-by: Minghuan Lian Signed-off-by: Bjorn Helgaas --- drivers/pci/host/pci-layerscape.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'drivers/pci') diff --git a/drivers/pci/host/pci-layerscape.c b/drivers/pci/host/pci-layerscape.c index 6dd44a0..5eabe92 100644 --- a/drivers/pci/host/pci-layerscape.c +++ b/drivers/pci/host/pci-layerscape.c @@ -47,6 +47,16 @@ struct ls_pcie { #define to_ls_pcie(x) container_of(x, struct ls_pcie, pp) +static bool ls_pcie_is_bridge(struct ls_pcie *pcie) +{ + u32 header_type; + + header_type = ioread8(pcie->dbi + PCI_HEADER_TYPE); + header_type &= 0x7f; + + return header_type == PCI_HEADER_TYPE_BRIDGE; +} + static int ls_pcie_link_up(struct pcie_port *pp) { u32 state; @@ -135,6 +145,9 @@ static int __init ls_pcie_probe(struct platform_device *pdev) return ret; pcie->index = index[1]; + if (!ls_pcie_is_bridge(pcie)) + return -ENODEV; + ret = ls_add_pcie_port(pcie); if (ret < 0) return ret; -- cgit v1.1 From d64633453e3b3e580111ecca566d9e2771dad694 Mon Sep 17 00:00:00 2001 From: Minghuan Lian Date: Fri, 16 Oct 2015 15:19:17 +0800 Subject: PCI: layerscape: Factor out SCFG related function For the LS1021a PCIe controller, some status registers are located in SCFG, unlike other Layerscape devices. Move SCFG-related code to ls1021_pcie_host_init() and rename ls_pcie_link_up() to ls1021_pcie_link_up() because LTSSM status is also in SCFG. Signed-off-by: Minghuan Lian Signed-off-by: Bjorn Helgaas --- drivers/pci/host/pci-layerscape.c | 72 +++++++++++++++++++++++++-------------- 1 file changed, 46 insertions(+), 26 deletions(-) (limited to 'drivers/pci') diff --git a/drivers/pci/host/pci-layerscape.c b/drivers/pci/host/pci-layerscape.c index 5eabe92..89b7eb8 100644 --- a/drivers/pci/host/pci-layerscape.c +++ b/drivers/pci/host/pci-layerscape.c @@ -34,6 +34,10 @@ /* Symbol Timer Register and Filter Mask Register 1 */ #define PCIE_STRFMR1 0x71c +struct ls_pcie_drvdata { + struct pcie_host_ops *ops; +}; + struct ls_pcie { struct list_head node; struct device *dev; @@ -41,6 +45,7 @@ struct ls_pcie { void __iomem *dbi; struct regmap *scfg; struct pcie_port pp; + const struct ls_pcie_drvdata *drvdata; int index; int msi_irq; }; @@ -57,11 +62,14 @@ static bool ls_pcie_is_bridge(struct ls_pcie *pcie) return header_type == PCI_HEADER_TYPE_BRIDGE; } -static int ls_pcie_link_up(struct pcie_port *pp) +static int ls1021_pcie_link_up(struct pcie_port *pp) { u32 state; struct ls_pcie *pcie = to_ls_pcie(pp); + if (!pcie->scfg) + return 0; + regmap_read(pcie->scfg, SCFG_PEXMSCPORTSR(pcie->index), &state); state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK; @@ -71,10 +79,25 @@ static int ls_pcie_link_up(struct pcie_port *pp) return 1; } -static void ls_pcie_host_init(struct pcie_port *pp) +static void ls1021_pcie_host_init(struct pcie_port *pp) { struct ls_pcie *pcie = to_ls_pcie(pp); - u32 val; + u32 val, index[2]; + + pcie->scfg = syscon_regmap_lookup_by_phandle(pp->dev->of_node, + "fsl,pcie-scfg"); + if (IS_ERR(pcie->scfg)) { + dev_err(pp->dev, "No syscfg phandle specified\n"); + pcie->scfg = NULL; + return; + } + + if (of_property_read_u32_array(pp->dev->of_node, + "fsl,pcie-scfg", index, 2)) { + pcie->scfg = NULL; + return; + } + pcie->index = index[1]; dw_pcie_setup_rc(pp); @@ -87,11 +110,21 @@ static void ls_pcie_host_init(struct pcie_port *pp) iowrite32(val, pcie->dbi + PCIE_STRFMR1); } -static struct pcie_host_ops ls_pcie_host_ops = { - .link_up = ls_pcie_link_up, - .host_init = ls_pcie_host_init, +static struct pcie_host_ops ls1021_pcie_host_ops = { + .link_up = ls1021_pcie_link_up, + .host_init = ls1021_pcie_host_init, +}; + +static struct ls_pcie_drvdata ls1021_drvdata = { + .ops = &ls1021_pcie_host_ops, }; +static const struct of_device_id ls_pcie_of_match[] = { + { .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata }, + { }, +}; +MODULE_DEVICE_TABLE(of, ls_pcie_of_match); + static int ls_add_pcie_port(struct ls_pcie *pcie) { struct pcie_port *pp; @@ -101,7 +134,7 @@ static int ls_add_pcie_port(struct ls_pcie *pcie) pp->dev = pcie->dev; pp->dbi_base = pcie->dbi; pp->root_bus_nr = -1; - pp->ops = &ls_pcie_host_ops; + pp->ops = pcie->drvdata->ops; ret = dw_pcie_host_init(pp); if (ret) { @@ -114,11 +147,15 @@ static int ls_add_pcie_port(struct ls_pcie *pcie) static int __init ls_pcie_probe(struct platform_device *pdev) { + const struct of_device_id *match; struct ls_pcie *pcie; struct resource *dbi_base; - u32 index[2]; int ret; + match = of_match_device(ls_pcie_of_match, &pdev->dev); + if (!match) + return -ENODEV; + pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL); if (!pcie) return -ENOMEM; @@ -132,18 +169,7 @@ static int __init ls_pcie_probe(struct platform_device *pdev) return PTR_ERR(pcie->dbi); } - pcie->scfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, - "fsl,pcie-scfg"); - if (IS_ERR(pcie->scfg)) { - dev_err(&pdev->dev, "No syscfg phandle specified\n"); - return PTR_ERR(pcie->scfg); - } - - ret = of_property_read_u32_array(pdev->dev.of_node, - "fsl,pcie-scfg", index, 2); - if (ret) - return ret; - pcie->index = index[1]; + pcie->drvdata = match->data; if (!ls_pcie_is_bridge(pcie)) return -ENODEV; @@ -157,12 +183,6 @@ static int __init ls_pcie_probe(struct platform_device *pdev) return 0; } -static const struct of_device_id ls_pcie_of_match[] = { - { .compatible = "fsl,ls1021a-pcie" }, - { }, -}; -MODULE_DEVICE_TABLE(of, ls_pcie_of_match); - static struct platform_driver ls_pcie_driver = { .driver = { .name = "layerscape-pcie", -- cgit v1.1 From a167fb73be98f43f16116a2c3a0cd9ad11c8ef61 Mon Sep 17 00:00:00 2001 From: Minghuan Lian Date: Fri, 16 Oct 2015 15:19:18 +0800 Subject: PCI: layerscape: Update ls_add_pcie_port() Update the ls_add_pcie_port() signature to keep it consistent with the other DesignWare-based host drivers. Signed-off-by: Minghuan Lian Signed-off-by: Bjorn Helgaas --- drivers/pci/host/pci-layerscape.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) (limited to 'drivers/pci') diff --git a/drivers/pci/host/pci-layerscape.c b/drivers/pci/host/pci-layerscape.c index 89b7eb8..f778f63 100644 --- a/drivers/pci/host/pci-layerscape.c +++ b/drivers/pci/host/pci-layerscape.c @@ -125,15 +125,14 @@ static const struct of_device_id ls_pcie_of_match[] = { }; MODULE_DEVICE_TABLE(of, ls_pcie_of_match); -static int ls_add_pcie_port(struct ls_pcie *pcie) +static int __init ls_add_pcie_port(struct pcie_port *pp, + struct platform_device *pdev) { - struct pcie_port *pp; int ret; + struct ls_pcie *pcie = to_ls_pcie(pp); - pp = &pcie->pp; - pp->dev = pcie->dev; + pp->dev = &pdev->dev; pp->dbi_base = pcie->dbi; - pp->root_bus_nr = -1; pp->ops = pcie->drvdata->ops; ret = dw_pcie_host_init(pp); @@ -160,8 +159,6 @@ static int __init ls_pcie_probe(struct platform_device *pdev) if (!pcie) return -ENOMEM; - pcie->dev = &pdev->dev; - dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); pcie->dbi = devm_ioremap_resource(&pdev->dev, dbi_base); if (IS_ERR(pcie->dbi)) { @@ -174,7 +171,7 @@ static int __init ls_pcie_probe(struct platform_device *pdev) if (!ls_pcie_is_bridge(pcie)) return -ENODEV; - ret = ls_add_pcie_port(pcie); + ret = ls_add_pcie_port(&pcie->pp, pdev); if (ret < 0) return ret; -- cgit v1.1 From 0f3cb324bec688c61578c04c5207898050dcc7ac Mon Sep 17 00:00:00 2001 From: Minghuan Lian Date: Wed, 21 Oct 2015 16:13:37 -0500 Subject: PCI: layerscape: Remove unused fields from struct ls_pcie Removed unused node, dev, and bus fields from struct ls_pcie. [bhelgaas: split into separate patch] Signed-off-by: Minghuan Lian Signed-off-by: Bjorn Helgaas --- drivers/pci/host/pci-layerscape.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'drivers/pci') diff --git a/drivers/pci/host/pci-layerscape.c b/drivers/pci/host/pci-layerscape.c index f778f63..7d61cbb 100644 --- a/drivers/pci/host/pci-layerscape.c +++ b/drivers/pci/host/pci-layerscape.c @@ -39,9 +39,6 @@ struct ls_pcie_drvdata { }; struct ls_pcie { - struct list_head node; - struct device *dev; - struct pci_bus *bus; void __iomem *dbi; struct regmap *scfg; struct pcie_port pp; -- cgit v1.1 From 5192ec7b24dd78bd82fe554995b8889d317da0c1 Mon Sep 17 00:00:00 2001 From: Minghuan Lian Date: Fri, 16 Oct 2015 15:19:19 +0800 Subject: PCI: layerscape: Add support for LS1043a and LS2080a Both LS1043a and LS2080a are based on ARMv8 64-bit architecture and have similar PCIe implementation. LUT is added to controller. Add LS1043a and LS2080a support. [bhelgaas: move unused field removal into separate patch, include DT update] Signed-off-by: Bhupesh Sharma (DT update) Signed-off-by: Minghuan Lian Signed-off-by: Bjorn Helgaas Acked-by: Arnd Bergmann (DT update) --- drivers/pci/host/Kconfig | 2 +- drivers/pci/host/pci-layerscape.c | 71 ++++++++++++++++++++++++++++++++++++--- 2 files changed, 68 insertions(+), 5 deletions(-) (limited to 'drivers/pci') diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig index d5e58ba..fcf08a0 100644 --- a/drivers/pci/host/Kconfig +++ b/drivers/pci/host/Kconfig @@ -105,7 +105,7 @@ config PCI_XGENE_MSI config PCI_LAYERSCAPE bool "Freescale Layerscape PCIe controller" - depends on OF && ARM + depends on OF && (ARM || ARCH_LAYERSCAPE) select PCIE_DW select MFD_SYSCON help diff --git a/drivers/pci/host/pci-layerscape.c b/drivers/pci/host/pci-layerscape.c index 7d61cbb..0f6dd44 100644 --- a/drivers/pci/host/pci-layerscape.c +++ b/drivers/pci/host/pci-layerscape.c @@ -3,7 +3,7 @@ * * Copyright (C) 2014 Freescale Semiconductor. * - * Author: Minghuan Lian + * Author: Minghuan Lian * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -31,20 +31,26 @@ #define LTSSM_STATE_MASK 0x3f #define LTSSM_PCIE_L0 0x11 /* L0 state */ -/* Symbol Timer Register and Filter Mask Register 1 */ -#define PCIE_STRFMR1 0x71c +/* PEX Internal Configuration Registers */ +#define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */ +#define PCIE_DBI_RO_WR_EN 0x8bc /* DBI Read-Only Write Enable Register */ + +/* PEX LUT registers */ +#define PCIE_LUT_DBG 0x7FC /* PEX LUT Debug Register */ struct ls_pcie_drvdata { + u32 lut_offset; + u32 ltssm_shift; struct pcie_host_ops *ops; }; struct ls_pcie { void __iomem *dbi; + void __iomem *lut; struct regmap *scfg; struct pcie_port pp; const struct ls_pcie_drvdata *drvdata; int index; - int msi_irq; }; #define to_ls_pcie(x) container_of(x, struct ls_pcie, pp) @@ -59,6 +65,18 @@ static bool ls_pcie_is_bridge(struct ls_pcie *pcie) return header_type == PCI_HEADER_TYPE_BRIDGE; } +/* Clear multi-function bit */ +static void ls_pcie_clear_multifunction(struct ls_pcie *pcie) +{ + iowrite8(PCI_HEADER_TYPE_BRIDGE, pcie->dbi + PCI_HEADER_TYPE); +} + +/* Fix class value */ +static void ls_pcie_fix_class(struct ls_pcie *pcie) +{ + iowrite16(PCI_CLASS_BRIDGE_PCI, pcie->dbi + PCI_CLASS_DEVICE); +} + static int ls1021_pcie_link_up(struct pcie_port *pp) { u32 state; @@ -107,17 +125,61 @@ static void ls1021_pcie_host_init(struct pcie_port *pp) iowrite32(val, pcie->dbi + PCIE_STRFMR1); } +static int ls_pcie_link_up(struct pcie_port *pp) +{ + struct ls_pcie *pcie = to_ls_pcie(pp); + u32 state; + + state = (ioread32(pcie->lut + PCIE_LUT_DBG) >> + pcie->drvdata->ltssm_shift) & + LTSSM_STATE_MASK; + + if (state < LTSSM_PCIE_L0) + return 0; + + return 1; +} + +static void ls_pcie_host_init(struct pcie_port *pp) +{ + struct ls_pcie *pcie = to_ls_pcie(pp); + + iowrite32(1, pcie->dbi + PCIE_DBI_RO_WR_EN); + ls_pcie_fix_class(pcie); + ls_pcie_clear_multifunction(pcie); + iowrite32(0, pcie->dbi + PCIE_DBI_RO_WR_EN); +} + static struct pcie_host_ops ls1021_pcie_host_ops = { .link_up = ls1021_pcie_link_up, .host_init = ls1021_pcie_host_init, }; +static struct pcie_host_ops ls_pcie_host_ops = { + .link_up = ls_pcie_link_up, + .host_init = ls_pcie_host_init, +}; + static struct ls_pcie_drvdata ls1021_drvdata = { .ops = &ls1021_pcie_host_ops, }; +static struct ls_pcie_drvdata ls1043_drvdata = { + .lut_offset = 0x10000, + .ltssm_shift = 24, + .ops = &ls_pcie_host_ops, +}; + +static struct ls_pcie_drvdata ls2080_drvdata = { + .lut_offset = 0x80000, + .ltssm_shift = 0, + .ops = &ls_pcie_host_ops, +}; + static const struct of_device_id ls_pcie_of_match[] = { { .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata }, + { .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata }, + { .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata }, { }, }; MODULE_DEVICE_TABLE(of, ls_pcie_of_match); @@ -164,6 +226,7 @@ static int __init ls_pcie_probe(struct platform_device *pdev) } pcie->drvdata = match->data; + pcie->lut = pcie->dbi + pcie->drvdata->lut_offset; if (!ls_pcie_is_bridge(pcie)) return -ENODEV; -- cgit v1.1 From bd33b87a9a15f8182e8c6a49f5413e7ef79372bf Mon Sep 17 00:00:00 2001 From: Minghuan Lian Date: Fri, 16 Oct 2015 15:19:20 +0800 Subject: PCI: layerscape: Add ls_pcie_msi_host_init() Layerscape PCIe has its own MSI implementation. Register ls_pcie_msi_host_init() to avoid using DesignWare's MSI. [bhelgaas: add comment] Signed-off-by: Minghuan Lian Signed-off-by: Bjorn Helgaas --- drivers/pci/host/pci-layerscape.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'drivers/pci') diff --git a/drivers/pci/host/pci-layerscape.c b/drivers/pci/host/pci-layerscape.c index 0f6dd44..3923bed 100644 --- a/drivers/pci/host/pci-layerscape.c +++ b/drivers/pci/host/pci-layerscape.c @@ -150,14 +150,37 @@ static void ls_pcie_host_init(struct pcie_port *pp) iowrite32(0, pcie->dbi + PCIE_DBI_RO_WR_EN); } +static int ls_pcie_msi_host_init(struct pcie_port *pp, + struct msi_controller *chip) +{ + struct device_node *msi_node; + struct device_node *np = pp->dev->of_node; + + /* + * The MSI domain is set by the generic of_msi_configure(). This + * .msi_host_init() function keeps us from doing the default MSI + * domain setup in dw_pcie_host_init() and also enforces the + * requirement that "msi-parent" exists. + */ + msi_node = of_parse_phandle(np, "msi-parent", 0); + if (!msi_node) { + dev_err(pp->dev, "failed to find msi-parent\n"); + return -EINVAL; + } + + return 0; +} + static struct pcie_host_ops ls1021_pcie_host_ops = { .link_up = ls1021_pcie_link_up, .host_init = ls1021_pcie_host_init, + .msi_host_init = ls_pcie_msi_host_init, }; static struct pcie_host_ops ls_pcie_host_ops = { .link_up = ls_pcie_link_up, .host_init = ls_pcie_host_init, + .msi_host_init = ls_pcie_msi_host_init, }; static struct ls_pcie_drvdata ls1021_drvdata = { -- cgit v1.1