From 8b2ec318eece89be5e33d5313a25461a55a3177a Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Sun, 12 Jun 2016 16:26:40 -0500 Subject: PCI: Add PTM clock granularity information The PTM Control register (PCIe r3.1, sec 7.32.3) contains an Effective Granularity field: This provides information relating to the expected accuracy of the PTM clock, but does not otherwise affect the PTM mechanism. Set the Effective Granularity based on the PTM Root and any intervening PTM Time Sources. This does not set Effective Granularity for Root Complex Integrated Endpoints because I don't know how to figure out clock granularity for them. The spec says: ... system software must set [Effective Granularity] to the value reported in the Local Clock Granularity field by the associated PTM Time Source. but I don't know how to identify the associated PTM Time Source. Normally it's the upstream bridge, but an integrated endpoint has no upstream bridge. Signed-off-by: Bjorn Helgaas --- drivers/pci/pcie/ptm.c | 31 +++++++++++++++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) (limited to 'drivers/pci/pcie') diff --git a/drivers/pci/pcie/ptm.c b/drivers/pci/pcie/ptm.c index a14ac94..bab8ac6 100644 --- a/drivers/pci/pcie/ptm.c +++ b/drivers/pci/pcie/ptm.c @@ -19,13 +19,29 @@ static void pci_ptm_info(struct pci_dev *dev) { - dev_info(&dev->dev, "PTM enabled%s\n", dev->ptm_root ? " (root)" : ""); + char clock_desc[8]; + + switch (dev->ptm_granularity) { + case 0: + snprintf(clock_desc, sizeof(clock_desc), "unknown"); + break; + case 255: + snprintf(clock_desc, sizeof(clock_desc), ">254ns"); + break; + default: + snprintf(clock_desc, sizeof(clock_desc), "%udns", + dev->ptm_granularity); + break; + } + dev_info(&dev->dev, "PTM enabled%s, %s granularity\n", + dev->ptm_root ? " (root)" : "", clock_desc); } void pci_ptm_init(struct pci_dev *dev) { int pos; u32 cap, ctrl; + u8 local_clock; struct pci_dev *ups; if (!pci_is_pcie(dev)) @@ -45,6 +61,7 @@ void pci_ptm_init(struct pci_dev *dev) return; pci_read_config_dword(dev, pos + PCI_PTM_CAP, &cap); + local_clock = (cap & PCI_PTM_GRANULARITY_MASK) >> 8; /* * There's no point in enabling PTM unless it's enabled in the @@ -55,14 +72,20 @@ void pci_ptm_init(struct pci_dev *dev) ups = pci_upstream_bridge(dev); if (ups && ups->ptm_enabled) { ctrl = PCI_PTM_CTRL_ENABLE; + if (ups->ptm_granularity == 0) + dev->ptm_granularity = 0; + else if (ups->ptm_granularity > local_clock) + dev->ptm_granularity = ups->ptm_granularity; } else { if (cap & PCI_PTM_CAP_ROOT) { ctrl = PCI_PTM_CTRL_ENABLE | PCI_PTM_CTRL_ROOT; dev->ptm_root = 1; + dev->ptm_granularity = local_clock; } else return; } + ctrl |= dev->ptm_granularity << 8; pci_write_config_dword(dev, pos + PCI_PTM_CTRL, ctrl); dev->ptm_enabled = 1; @@ -98,18 +121,22 @@ int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) ups = pci_upstream_bridge(dev); if (!ups || !ups->ptm_enabled) return -EINVAL; + + dev->ptm_granularity = ups->ptm_granularity; } else if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) { + dev->ptm_granularity = 0; } else return -EINVAL; ctrl = PCI_PTM_CTRL_ENABLE; + ctrl |= dev->ptm_granularity << 8; pci_write_config_dword(dev, pos + PCI_PTM_CTRL, ctrl); dev->ptm_enabled = 1; pci_ptm_info(dev); if (granularity) - *granularity = 0; + *granularity = dev->ptm_granularity; return 0; } EXPORT_SYMBOL(pci_enable_ptm); -- cgit v1.1