From 33a31826b4fe9f26d6b383bad19b7ae522fda006 Mon Sep 17 00:00:00 2001
From: Nick Kossifidis <mick@madwifi-project.org>
Date: Mon, 9 Feb 2009 06:00:34 +0200
Subject: ath5k: PHY code cleanup
* Clean up initial rf buffer settings (new file rfbufer.h) and introduce a
new way to access specific rf registers (will use it later)
* Clean up initial rf gain settings by moving them on a new file (rfgain.h)
so we can later work on gain optimization functions
* Update initial rf buffer settings and initial rf gain settings from HALs.
This breaks things for now because our current dumps come from pre-configured
rf buffer (regdumps already had the needed values set from binary HAL).
Signed-off-by: Nick Kossifidis <mickflemm@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
---
drivers/net/wireless/ath5k/phy.c | 1171 ++------------------------------------
1 file changed, 38 insertions(+), 1133 deletions(-)
(limited to 'drivers/net/wireless/ath5k/phy.c')
diff --git a/drivers/net/wireless/ath5k/phy.c b/drivers/net/wireless/ath5k/phy.c
index 7ba18e0..5021749 100644
--- a/drivers/net/wireless/ath5k/phy.c
+++ b/drivers/net/wireless/ath5k/phy.c
@@ -2,7 +2,7 @@
* PHY functions
*
* Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
- * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
+ * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
* Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
*
* Permission to use, copy, modify, and distribute this software for any
@@ -26,1084 +26,8 @@
#include "ath5k.h"
#include "reg.h"
#include "base.h"
-
-/* Struct to hold initial RF register values (RF Banks) */
-struct ath5k_ini_rf {
- u8 rf_bank; /* check out ath5k_reg.h */
- u16 rf_register; /* register address */
- u32 rf_value[5]; /* register value for different modes (above) */
-};
-
-/*
- * Mode-specific RF Gain table (64bytes) for RF5111/5112
- * (RF5110 only comes with AR5210 and only supports a/turbo a mode so initial
- * RF Gain values are included in AR5K_AR5210_INI)
- */
-struct ath5k_ini_rfgain {
- u16 rfg_register; /* RF Gain register address */
- u32 rfg_value[2]; /* [freq (see below)] */
-};
-
-struct ath5k_gain_opt {
- u32 go_default;
- u32 go_steps_count;
- const struct ath5k_gain_opt_step go_step[AR5K_GAIN_STEP_COUNT];
-};
-
-/* RF5111 mode-specific init registers */
-static const struct ath5k_ini_rf rfregs_5111[] = {
- { 0, 0x989c,
- /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
- { 0, 0x989c,
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
- { 0, 0x989c,
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
- { 0, 0x989c,
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
- { 0, 0x989c,
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
- { 0, 0x989c,
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
- { 0, 0x989c,
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
- { 0, 0x989c,
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
- { 0, 0x989c,
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
- { 0, 0x989c,
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
- { 0, 0x989c,
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
- { 0, 0x989c,
- { 0x00380000, 0x00380000, 0x00380000, 0x00380000, 0x00380000 } },
- { 0, 0x989c,
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
- { 0, 0x989c,
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
- { 0, 0x989c,
- { 0x00000000, 0x00000000, 0x000000c0, 0x00000080, 0x00000080 } },
- { 0, 0x989c,
- { 0x000400f9, 0x000400f9, 0x000400ff, 0x000400fd, 0x000400fd } },
- { 0, 0x98d4,
- { 0x00000000, 0x00000000, 0x00000004, 0x00000004, 0x00000004 } },
- { 1, 0x98d4,
- { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
- { 2, 0x98d4,
- { 0x00000010, 0x00000014, 0x00000010, 0x00000010, 0x00000014 } },
- { 3, 0x98d8,
- { 0x00601068, 0x00601068, 0x00601068, 0x00601068, 0x00601068 } },
- { 6, 0x989c,
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
- { 6, 0x989c,
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
- { 6, 0x989c,
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
- { 6, 0x989c,
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
- { 6, 0x989c,
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
- { 6, 0x989c,
- { 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } },
- { 6, 0x989c,
- { 0x04000000, 0x04000000, 0x04000000, 0x04000000, 0x04000000 } },
- { 6, 0x989c,
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
- { 6, 0x989c,
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
- { 6, 0x989c,
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
- { 6, 0x989c,
- { 0x00000000, 0x00000000, 0x0a000000, 0x00000000, 0x00000000 } },
- { 6, 0x989c,
- { 0x003800c0, 0x00380080, 0x023800c0, 0x003800c0, 0x003800c0 } },
- { 6, 0x989c,
- { 0x00020006, 0x00020006, 0x00000006, 0x00020006, 0x00020006 } },
- { 6, 0x989c,
- { 0x00000089, 0x00000089, 0x00000089, 0x00000089, 0x00000089 } },
- { 6, 0x989c,
- { 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0 } },
- { 6, 0x989c,
- { 0x00040007, 0x00040007, 0x00040007, 0x00040007, 0x00040007 } },
- { 6, 0x98d4,
- { 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a } },
- { 7, 0x989c,
- { 0x00000040, 0x00000048, 0x00000040, 0x00000040, 0x00000040 } },
- { 7, 0x989c,
- { 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 } },
- { 7, 0x989c,
- { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } },
- { 7, 0x989c,
- { 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f } },
- { 7, 0x989c,
- { 0x000000f1, 0x000000f1, 0x00000061, 0x000000f1, 0x000000f1 } },
- { 7, 0x989c,
- { 0x0000904f, 0x0000904f, 0x0000904c, 0x0000904f, 0x0000904f } },
- { 7, 0x989c,
- { 0x0000125a, 0x0000125a, 0x0000129a, 0x0000125a, 0x0000125a } },
- { 7, 0x98cc,
- { 0x0000000e, 0x0000000e, 0x0000000f, 0x0000000e, 0x0000000e } },
-};
-
-/* Initial RF Gain settings for RF5111 */
-static const struct ath5k_ini_rfgain rfgain_5111[] = {
- /* 5Ghz 2Ghz */
- { AR5K_RF_GAIN(0), { 0x000001a9, 0x00000000 } },
- { AR5K_RF_GAIN(1), { 0x000001e9, 0x00000040 } },
- { AR5K_RF_GAIN(2), { 0x00000029, 0x00000080 } },
- { AR5K_RF_GAIN(3), { 0x00000069, 0x00000150 } },
- { AR5K_RF_GAIN(4), { 0x00000199, 0x00000190 } },
- { AR5K_RF_GAIN(5), { 0x000001d9, 0x000001d0 } },
- { AR5K_RF_GAIN(6), { 0x00000019, 0x00000010 } },
- { AR5K_RF_GAIN(7), { 0x00000059, 0x00000044 } },
- { AR5K_RF_GAIN(8), { 0x00000099, 0x00000084 } },
- { AR5K_RF_GAIN(9), { 0x000001a5, 0x00000148 } },
- { AR5K_RF_GAIN(10), { 0x000001e5, 0x00000188 } },
- { AR5K_RF_GAIN(11), { 0x00000025, 0x000001c8 } },
- { AR5K_RF_GAIN(12), { 0x000001c8, 0x00000014 } },
- { AR5K_RF_GAIN(13), { 0x00000008, 0x00000042 } },
- { AR5K_RF_GAIN(14), { 0x00000048, 0x00000082 } },
- { AR5K_RF_GAIN(15), { 0x00000088, 0x00000178 } },
- { AR5K_RF_GAIN(16), { 0x00000198, 0x000001b8 } },
- { AR5K_RF_GAIN(17), { 0x000001d8, 0x000001f8 } },
- { AR5K_RF_GAIN(18), { 0x00000018, 0x00000012 } },
- { AR5K_RF_GAIN(19), { 0x00000058, 0x00000052 } },
- { AR5K_RF_GAIN(20), { 0x00000098, 0x00000092 } },
- { AR5K_RF_GAIN(21), { 0x000001a4, 0x0000017c } },
- { AR5K_RF_GAIN(22), { 0x000001e4, 0x000001bc } },
- { AR5K_RF_GAIN(23), { 0x00000024, 0x000001fc } },
- { AR5K_RF_GAIN(24), { 0x00000064, 0x0000000a } },
- { AR5K_RF_GAIN(25), { 0x000000a4, 0x0000004a } },
- { AR5K_RF_GAIN(26), { 0x000000e4, 0x0000008a } },
- { AR5K_RF_GAIN(27), { 0x0000010a, 0x0000015a } },
- { AR5K_RF_GAIN(28), { 0x0000014a, 0x0000019a } },
- { AR5K_RF_GAIN(29), { 0x0000018a, 0x000001da } },
- { AR5K_RF_GAIN(30), { 0x000001ca, 0x0000000e } },
- { AR5K_RF_GAIN(31), { 0x0000000a, 0x0000004e } },
- { AR5K_RF_GAIN(32), { 0x0000004a, 0x0000008e } },
- { AR5K_RF_GAIN(33), { 0x0000008a, 0x0000015e } },
- { AR5K_RF_GAIN(34), { 0x000001ba, 0x0000019e } },
- { AR5K_RF_GAIN(35), { 0x000001fa, 0x000001de } },
- { AR5K_RF_GAIN(36), { 0x0000003a, 0x00000009 } },
- { AR5K_RF_GAIN(37), { 0x0000007a, 0x00000049 } },
- { AR5K_RF_GAIN(38), { 0x00000186, 0x00000089 } },
- { AR5K_RF_GAIN(39), { 0x000001c6, 0x00000179 } },
- { AR5K_RF_GAIN(40), { 0x00000006, 0x000001b9 } },
- { AR5K_RF_GAIN(41), { 0x00000046, 0x000001f9 } },
- { AR5K_RF_GAIN(42), { 0x00000086, 0x00000039 } },
- { AR5K_RF_GAIN(43), { 0x000000c6, 0x00000079 } },
- { AR5K_RF_GAIN(44), { 0x000000c6, 0x000000b9 } },
- { AR5K_RF_GAIN(45), { 0x000000c6, 0x000001bd } },
- { AR5K_RF_GAIN(46), { 0x000000c6, 0x000001fd } },
- { AR5K_RF_GAIN(47), { 0x000000c6, 0x0000003d } },
- { AR5K_RF_GAIN(48), { 0x000000c6, 0x0000007d } },
- { AR5K_RF_GAIN(49), { 0x000000c6, 0x000000bd } },
- { AR5K_RF_GAIN(50), { 0x000000c6, 0x000000fd } },
- { AR5K_RF_GAIN(51), { 0x000000c6, 0x000000fd } },
- { AR5K_RF_GAIN(52), { 0x000000c6, 0x000000fd } },
- { AR5K_RF_GAIN(53), { 0x000000c6, 0x000000fd } },
- { AR5K_RF_GAIN(54), { 0x000000c6, 0x000000fd } },
- { AR5K_RF_GAIN(55), { 0x000000c6, 0x000000fd } },
- { AR5K_RF_GAIN(56), { 0x000000c6, 0x000000fd } },
- { AR5K_RF_GAIN(57), { 0x000000c6, 0x000000fd } },
- { AR5K_RF_GAIN(58), { 0x000000c6, 0x000000fd } },
- { AR5K_RF_GAIN(59), { 0x000000c6, 0x000000fd } },
- { AR5K_RF_GAIN(60), { 0x000000c6, 0x000000fd } },
- { AR5K_RF_GAIN(61), { 0x000000c6, 0x000000fd } },
- { AR5K_RF_GAIN(62), { 0x000000c6, 0x000000fd } },
- { AR5K_RF_GAIN(63), { 0x000000c6, 0x000000fd } },
-};
-
-static const struct ath5k_gain_opt rfgain_opt_5111 = {
- 4,
- 9,
- {
- { { 4, 1, 1, 1 }, 6 },
- { { 4, 0, 1, 1 }, 4 },
- { { 3, 1, 1, 1 }, 3 },
- { { 4, 0, 0, 1 }, 1 },
- { { 4, 1, 1, 0 }, 0 },
- { { 4, 0, 1, 0 }, -2 },
- { { 3, 1, 1, 0 }, -3 },
- { { 4, 0, 0, 0 }, -4 },
- { { 2, 1, 1, 0 }, -6 }
- }
-};
-
-/* RF5112 mode-specific init registers */
-static const struct ath5k_ini_rf rfregs_5112[] = {
- { 1, 0x98d4,
- /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
- { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
- { 2, 0x98d0,
- { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } },
- { 3, 0x98dc,
- { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } },
- { 6, 0x989c,
- { 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000 } },
- { 6, 0x989c,
- { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } },
- { 6, 0x989c,
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
- { 6, 0x989c,
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
- { 6, 0x989c,
- { 0x00660000, 0x00660000, 0x00660000, 0x00660000, 0x00660000 } },
- { 6, 0x989c,
- { 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000 } },
- { 6, 0x989c,
- { 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000 } },
- { 6, 0x989c,
- { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
- { 6, 0x989c,
- { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
- { 6, 0x989c,
- { 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 } },
- { 6, 0x989c,
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
- { 6, 0x989c,
- { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
- { 6, 0x989c,
- { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
- { 6, 0x989c,
- { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
- { 6, 0x989c,
- { 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000 } },
- { 6, 0x989c,
- { 0x00600000, 0x00600000, 0x00600000, 0x00600000, 0x00600000 } },
- { 6, 0x989c,
- { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
- { 6, 0x989c,
- { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } },
- { 6, 0x989c,
- { 0x00640000, 0x00640000, 0x00640000, 0x00640000, 0x00640000 } },
- { 6, 0x989c,
- { 0x00200000, 0x00200000, 0x00200000, 0x00200000, 0x00200000 } },
- { 6, 0x989c,
- { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } },
- { 6, 0x989c,
- { 0x00250000, 0x00250000, 0x00250000, 0x00250000, 0x00250000 } },
- { 6, 0x989c,
- { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
- { 6, 0x989c,
- { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
- { 6, 0x989c,
- { 0x00510000, 0x00510000, 0x00510000, 0x00510000, 0x00510000 } },
- { 6, 0x989c,
- { 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000 } },
- { 6, 0x989c,
- { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } },
- { 6, 0x989c,
- { 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000 } },
- { 6, 0x989c,
- { 0x00400000, 0x00400000, 0x00400000, 0x00400000, 0x00400000 } },
- { 6, 0x989c,
- { 0x03090000, 0x03090000, 0x03090000, 0x03090000, 0x03090000 } },
- { 6, 0x989c,
- { 0x06000000, 0x06000000, 0x06000000, 0x06000000, 0x06000000 } },
- { 6, 0x989c,
- { 0x000000b0, 0x000000b0, 0x000000a8, 0x000000a8, 0x000000a8 } },
- { 6, 0x989c,
- { 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e } },
- { 6, 0x989c,
- { 0x006c4a41, 0x006c4a41, 0x006c4af1, 0x006c4a61, 0x006c4a61 } },
- { 6, 0x989c,
- { 0x0050892a, 0x0050892a, 0x0050892b, 0x0050892b, 0x0050892b } },
- { 6, 0x989c,
- { 0x00842400, 0x00842400, 0x00842400, 0x00842400, 0x00842400 } },
- { 6, 0x989c,
- { 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200 } },
- { 6, 0x98d0,
- { 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c } },
- { 7, 0x989c,
- { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } },
- { 7, 0x989c,
- { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } },
- { 7, 0x989c,
- { 0x0000000a, 0x0000000a, 0x00000012, 0x00000012, 0x00000012 } },
- { 7, 0x989c,
- { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } },
- { 7, 0x989c,
- { 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1 } },
- { 7, 0x989c,
- { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } },
- { 7, 0x989c,
- { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } },
- { 7, 0x989c,
- { 0x00000022, 0x00000022, 0x00000022, 0x00000022, 0x00000022 } },
- { 7, 0x989c,
- { 0x00000092, 0x00000092, 0x00000092, 0x00000092, 0x00000092 } },
- { 7, 0x989c,
- { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } },
- { 7, 0x989c,
- { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } },
- { 7, 0x989c,
- { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } },
- { 7, 0x98c4,
- { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
-};
-
-/* RF5112A mode-specific init registers */
-static const struct ath5k_ini_rf rfregs_5112a[] = {
- { 1, 0x98d4,
- /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
- { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
- { 2, 0x98d0,
- { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } },
- { 3, 0x98dc,
- { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } },
- { 6, 0x989c,
- { 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000 } },
- { 6, 0x989c,
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
- { 6, 0x989c,
- { 0x00800000, 0x00800000, 0x00800000, 0x00800000, 0x00800000 } },
- { 6, 0x989c,
- { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },
- { 6, 0x989c,
- { 0x00010000, 0x00010000, 0x00010000, 0x00010000, 0x00010000 } },
- { 6, 0x989c,
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
- { 6, 0x989c,
- { 0x00180000, 0x00180000, 0x00180000, 0x00180000, 0x00180000 } },
- { 6, 0x989c,
- { 0x00600000, 0x00600000, 0x006e0000, 0x006e0000, 0x006e0000 } },
- { 6, 0x989c,
- { 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000 } },
- { 6, 0x989c,
- { 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000 } },
- { 6, 0x989c,
- { 0x04480000, 0x04480000, 0x04480000, 0x04480000, 0x04480000 } },
- { 6, 0x989c,
- { 0x00220000, 0x00220000, 0x00220000, 0x00220000, 0x00220000 } },
- { 6, 0x989c,
- { 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000 } },
- { 6, 0x989c,
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
- { 6, 0x989c,
- { 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000 } },
- { 6, 0x989c,
- { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
- { 6, 0x989c,
- { 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000 } },
- { 6, 0x989c,
- { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
- { 6, 0x989c,
- { 0x00190000, 0x00190000, 0x00190000, 0x00190000, 0x00190000 } },
- { 6, 0x989c,
- { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } },
- { 6, 0x989c,
- { 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000 } },
- { 6, 0x989c,
- { 0x00990000, 0x00990000, 0x00990000, 0x00990000, 0x00990000 } },
- { 6, 0x989c,
- { 0x00500000, 0x00500000, 0x00500000, 0x00500000, 0x00500000 } },
- { 6, 0x989c,
- { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },
- { 6, 0x989c,
- { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
- { 6, 0x989c,
- { 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000 } },
- { 6, 0x989c,
- { 0x01740000, 0x01740000, 0x01740000, 0x01740000, 0x01740000 } },
- { 6, 0x989c,
- { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
- { 6, 0x989c,
- { 0x86280000, 0x86280000, 0x86280000, 0x86280000, 0x86280000 } },
- { 6, 0x989c,
- { 0x31840000, 0x31840000, 0x31840000, 0x31840000, 0x31840000 } },
- { 6, 0x989c,
- { 0x00020080, 0x00020080, 0x00020080, 0x00020080, 0x00020080 } },
- { 6, 0x989c,
- { 0x00080009, 0x00080009, 0x00080009, 0x00080009, 0x00080009 } },
- { 6, 0x989c,
- { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
- { 6, 0x989c,
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
- { 6, 0x989c,
- { 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2 } },
- { 6, 0x989c,
- { 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084 } },
- { 6, 0x989c,
- { 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4 } },
- { 6, 0x989c,
- { 0x00119220, 0x00119220, 0x00119220, 0x00119220, 0x00119220 } },
- { 6, 0x989c,
- { 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800 } },
- { 6, 0x98d8,
- { 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230 } },
- { 7, 0x989c,
- { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } },
- { 7, 0x989c,
- { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } },
- { 7, 0x989c,
- { 0x00000012, 0x00000012, 0x00000012, 0x00000012, 0x00000012 } },
- { 7, 0x989c,
- { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } },
- { 7, 0x989c,
- { 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9 } },
- { 7, 0x989c,
- { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } },
- { 7, 0x989c,
- { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } },
- { 7, 0x989c,
- { 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2 } },
- { 7, 0x989c,
- { 0x00000052, 0x00000052, 0x00000052, 0x00000052, 0x00000052 } },
- { 7, 0x989c,
- { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } },
- { 7, 0x989c,
- { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } },
- { 7, 0x989c,
- { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } },
- { 7, 0x98c4,
- { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
-};
-
-
-static const struct ath5k_ini_rf rfregs_2112a[] = {
- { 1, AR5K_RF_BUFFER_CONTROL_4,
- /* mode b mode g mode gTurbo */
- { 0x00000020, 0x00000020, 0x00000020 } },
- { 2, AR5K_RF_BUFFER_CONTROL_3,
- { 0x03060408, 0x03060408, 0x03070408 } },
- { 3, AR5K_RF_BUFFER_CONTROL_6,
- { 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
- { 6, AR5K_RF_BUFFER,
- { 0x0a000000, 0x0a000000, 0x0a000000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00000000, 0x00000000, 0x00000000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00800000, 0x00800000, 0x00800000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x002a0000, 0x002a0000, 0x002a0000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00010000, 0x00010000, 0x00010000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00000000, 0x00000000, 0x00000000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00180000, 0x00180000, 0x00180000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x006e0000, 0x006e0000, 0x006e0000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00c70000, 0x00c70000, 0x00c70000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x004b0000, 0x004b0000, 0x004b0000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x04480000, 0x04480000, 0x04480000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x002a0000, 0x002a0000, 0x002a0000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00e40000, 0x00e40000, 0x00e40000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00000000, 0x00000000, 0x00000000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00fc0000, 0x00fc0000, 0x00fc0000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x043f0000, 0x043f0000, 0x043f0000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x0c0c0000, 0x0c0c0000, 0x0c0c0000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x02190000, 0x02190000, 0x02190000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00240000, 0x00240000, 0x00240000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00b40000, 0x00b40000, 0x00b40000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00990000, 0x00990000, 0x00990000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00500000, 0x00500000, 0x00500000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x002a0000, 0x002a0000, 0x002a0000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00120000, 0x00120000, 0x00120000 } },
- { 6, AR5K_RF_BUFFER,
- { 0xc0320000, 0xc0320000, 0xc0320000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x01740000, 0x01740000, 0x01740000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00110000, 0x00110000, 0x00110000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x86280000, 0x86280000, 0x86280000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x31840000, 0x31840000, 0x31840000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00f20080, 0x00f20080, 0x00f20080 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00070019, 0x00070019, 0x00070019 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00000000, 0x00000000, 0x00000000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00000000, 0x00000000, 0x00000000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x000000b2, 0x000000b2, 0x000000b2 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00b02184, 0x00b02184, 0x00b02184 } },
- { 6, AR5K_RF_BUFFER,
- { 0x004125a4, 0x004125a4, 0x004125a4 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00119220, 0x00119220, 0x00119220 } },
- { 6, AR5K_RF_BUFFER,
- { 0x001a4800, 0x001a4800, 0x001a4800 } },
- { 6, AR5K_RF_BUFFER_CONTROL_5,
- { 0x000b0230, 0x000b0230, 0x000b0230 } },
- { 7, AR5K_RF_BUFFER,
- { 0x00000094, 0x00000094, 0x00000094 } },
- { 7, AR5K_RF_BUFFER,
- { 0x00000091, 0x00000091, 0x00000091 } },
- { 7, AR5K_RF_BUFFER,
- { 0x00000012, 0x00000012, 0x00000012 } },
- { 7, AR5K_RF_BUFFER,
- { 0x00000080, 0x00000080, 0x00000080 } },
- { 7, AR5K_RF_BUFFER,
- { 0x000000d9, 0x000000d9, 0x000000d9 } },
- { 7, AR5K_RF_BUFFER,
- { 0x00000060, 0x00000060, 0x00000060 } },
- { 7, AR5K_RF_BUFFER,
- { 0x000000f0, 0x000000f0, 0x000000f0 } },
- { 7, AR5K_RF_BUFFER,
- { 0x000000a2, 0x000000a2, 0x000000a2 } },
- { 7, AR5K_RF_BUFFER,
- { 0x00000052, 0x00000052, 0x00000052 } },
- { 7, AR5K_RF_BUFFER,
- { 0x000000d4, 0x000000d4, 0x000000d4 } },
- { 7, AR5K_RF_BUFFER,
- { 0x000014cc, 0x000014cc, 0x000014cc } },
- { 7, AR5K_RF_BUFFER,
- { 0x0000048c, 0x0000048c, 0x0000048c } },
- { 7, AR5K_RF_BUFFER_CONTROL_1,
- { 0x00000003, 0x00000003, 0x00000003 } },
-};
-
-/* RF5413/5414 mode-specific init registers */
-static const struct ath5k_ini_rf rfregs_5413[] = {
- { 1, 0x98d4,
- /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
- { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
- { 2, 0x98d0,
- { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } },
- { 3, 0x98dc,
- { 0x00a000c0, 0x00a000c0, 0x00e000c0, 0x00e000c0, 0x00e000c0 } },
- { 6, 0x989c,
- { 0x33000000, 0x33000000, 0x33000000, 0x33000000, 0x33000000 } },
- { 6, 0x989c,
- { 0x01000000, 0x01000000, 0x01000000, 0x01000000, 0x01000000 } },
- { 6, 0x989c,
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
- { 6, 0x989c,
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
- { 6, 0x989c,
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
- { 6, 0x989c,
- { 0x1f000000, 0x1f000000, 0x1f000000, 0x1f000000, 0x1f000000 } },
- { 6, 0x989c,
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
- { 6, 0x989c,
- { 0x00b80000, 0x00b80000, 0x00b80000, 0x00b80000, 0x00b80000 } },
- { 6, 0x989c,
- { 0x00b70000, 0x00b70000, 0x00b70000, 0x00b70000, 0x00b70000 } },
- { 6, 0x989c,
- { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } },
- { 6, 0x989c,
- { 0x00980000, 0x00980000, 0x00980000, 0x00980000, 0x00980000 } },
- { 6, 0x989c,
- { 0x00c00000, 0x00c00000, 0x00c00000, 0x00c00000, 0x00c00000 } },
- { 6, 0x989c,
- { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
- { 6, 0x989c,
- { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
- { 6, 0x989c,
- { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
- { 6, 0x989c,
- { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
- { 6, 0x989c,
- { 0x00d70000, 0x00d70000, 0x00d70000, 0x00d70000, 0x00d70000 } },
- { 6, 0x989c,
- { 0x00610000, 0x00610000, 0x00610000, 0x00610000, 0x00610000 } },
- { 6, 0x989c,
- { 0x00fe0000, 0x00fe0000, 0x00fe0000, 0x00fe0000, 0x00fe0000 } },
- { 6, 0x989c,
- { 0x00de0000, 0x00de0000, 0x00de0000, 0x00de0000, 0x00de0000 } },
- { 6, 0x989c,
- { 0x007f0000, 0x007f0000, 0x007f0000, 0x007f0000, 0x007f0000 } },
- { 6, 0x989c,
- { 0x043d0000, 0x043d0000, 0x043d0000, 0x043d0000, 0x043d0000 } },
- { 6, 0x989c,
- { 0x00770000, 0x00770000, 0x00770000, 0x00770000, 0x00770000 } },
- { 6, 0x989c,
- { 0x00440000, 0x00440000, 0x00440000, 0x00440000, 0x00440000 } },
- { 6, 0x989c,
- { 0x00980000, 0x00980000, 0x00980000, 0x00980000, 0x00980000 } },
- { 6, 0x989c,
- { 0x00100080, 0x00100080, 0x00100080, 0x00100080, 0x00100080 } },
- { 6, 0x989c,
- { 0x0005c034, 0x0005c034, 0x0005c034, 0x0005c034, 0x0005c034 } },
- { 6, 0x989c,
- { 0x003100f0, 0x003100f0, 0x003100f0, 0x003100f0, 0x003100f0 } },
- { 6, 0x989c,
- { 0x000c011f, 0x000c011f, 0x000c011f, 0x000c011f, 0x000c011f } },
- { 6, 0x989c,
- { 0x00510040, 0x00510040, 0x005100a0, 0x005100a0, 0x005100a0 } },
- { 6, 0x989c,
- { 0x0050006a, 0x0050006a, 0x005000dd, 0x005000dd, 0x005000dd } },
- { 6, 0x989c,
- { 0x00000001, 0x00000001, 0x00000000, 0x00000000, 0x00000000 } },
- { 6, 0x989c,
- { 0x00004044, 0x00004044, 0x00004044, 0x00004044, 0x00004044 } },
- { 6, 0x989c,
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
- { 6, 0x989c,
- { 0x000060c0, 0x000060c0, 0x000060c0, 0x000060c0, 0x000060c0 } },
- { 6, 0x989c,
- { 0x00002c00, 0x00002c00, 0x00003600, 0x00003600, 0x00003600 } },
- { 6, 0x98c8,
- { 0x00000403, 0x00000403, 0x00040403, 0x00040403, 0x00040403 } },
- { 7, 0x989c,
- { 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 } },
- { 7, 0x989c,
- { 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 } },
- { 7, 0x98cc,
- { 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } },
-};
-
-/* RF2413/2414 mode-specific init registers */
-static const struct ath5k_ini_rf rfregs_2413[] = {
- { 1, AR5K_RF_BUFFER_CONTROL_4,
- /* mode b mode g mode gTurbo */
- { 0x00000020, 0x00000020, 0x00000020 } },
- { 2, AR5K_RF_BUFFER_CONTROL_3,
- { 0x02001408, 0x02001408, 0x02001408 } },
- { 3, AR5K_RF_BUFFER_CONTROL_6,
- { 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
- { 6, AR5K_RF_BUFFER,
- { 0xf0000000, 0xf0000000, 0xf0000000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00000000, 0x00000000, 0x00000000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x03000000, 0x03000000, 0x03000000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00000000, 0x00000000, 0x00000000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00000000, 0x00000000, 0x00000000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00000000, 0x00000000, 0x00000000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00000000, 0x00000000, 0x00000000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00000000, 0x00000000, 0x00000000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x40400000, 0x40400000, 0x40400000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x65050000, 0x65050000, 0x65050000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00000000, 0x00000000, 0x00000000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00000000, 0x00000000, 0x00000000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00420000, 0x00420000, 0x00420000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00b50000, 0x00b50000, 0x00b50000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00030000, 0x00030000, 0x00030000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00f70000, 0x00f70000, 0x00f70000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x009d0000, 0x009d0000, 0x009d0000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00220000, 0x00220000, 0x00220000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x04220000, 0x04220000, 0x04220000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00230018, 0x00230018, 0x00230018 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00280050, 0x00280050, 0x00280050 } },
- { 6, AR5K_RF_BUFFER,
- { 0x005000c3, 0x005000c3, 0x005000c3 } },
- { 6, AR5K_RF_BUFFER,
- { 0x0004007f, 0x0004007f, 0x0004007f } },
- { 6, AR5K_RF_BUFFER,
- { 0x00000458, 0x00000458, 0x00000458 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00000000, 0x00000000, 0x00000000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x0000c000, 0x0000c000, 0x0000c000 } },
- { 6, AR5K_RF_BUFFER_CONTROL_5,
- { 0x00400230, 0x00400230, 0x00400230 } },
- { 7, AR5K_RF_BUFFER,
- { 0x00006400, 0x00006400, 0x00006400 } },
- { 7, AR5K_RF_BUFFER,
- { 0x00000800, 0x00000800, 0x00000800 } },
- { 7, AR5K_RF_BUFFER_CONTROL_2,
- { 0x0000000e, 0x0000000e, 0x0000000e } },
-};
-
-/* RF2425 mode-specific init registers */
-static const struct ath5k_ini_rf rfregs_2425[] = {
- { 1, AR5K_RF_BUFFER_CONTROL_4,
- /* mode g mode gTurbo */
- { 0x00000020, 0x00000020 } },
- { 2, AR5K_RF_BUFFER_CONTROL_3,
- { 0x02001408, 0x02001408 } },
- { 3, AR5K_RF_BUFFER_CONTROL_6,
- { 0x00e020c0, 0x00e020c0 } },
- { 6, AR5K_RF_BUFFER,
- { 0x10000000, 0x10000000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00000000, 0x00000000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00000000, 0x00000000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00000000, 0x00000000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00000000, 0x00000000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00000000, 0x00000000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00000000, 0x00000000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00000000, 0x00000000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00000000, 0x00000000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00000000, 0x00000000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00000000, 0x00000000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x002a0000, 0x002a0000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00000000, 0x00000000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00000000, 0x00000000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00100000, 0x00100000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00020000, 0x00020000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00730000, 0x00730000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00f80000, 0x00f80000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00e70000, 0x00e70000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00140000, 0x00140000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00910040, 0x00910040 } },
- { 6, AR5K_RF_BUFFER,
- { 0x0007001a, 0x0007001a } },
- { 6, AR5K_RF_BUFFER,
- { 0x00410000, 0x00410000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00810060, 0x00810060 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00020803, 0x00020803 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00000000, 0x00000000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00000000, 0x00000000 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00001660, 0x00001660 } },
- { 6, AR5K_RF_BUFFER,
- { 0x00001688, 0x00001688 } },
- { 6, AR5K_RF_BUFFER_CONTROL_1,
- { 0x00000001, 0x00000001 } },
- { 7, AR5K_RF_BUFFER,
- { 0x00006400, 0x00006400 } },
- { 7, AR5K_RF_BUFFER,
- { 0x00000800, 0x00000800 } },
- { 7, AR5K_RF_BUFFER_CONTROL_2,
- { 0x0000000e, 0x0000000e } },
-};
-
-/* Initial RF Gain settings for RF5112 */
-static const struct ath5k_ini_rfgain rfgain_5112[] = {
- /* 5Ghz 2Ghz */
- { AR5K_RF_GAIN(0), { 0x00000007, 0x00000007 } },
- { AR5K_RF_GAIN(1), { 0x00000047, 0x00000047 } },
- { AR5K_RF_GAIN(2), { 0x00000087, 0x00000087 } },
- { AR5K_RF_GAIN(3), { 0x000001a0, 0x000001a0 } },
- { AR5K_RF_GAIN(4), { 0x000001e0, 0x000001e0 } },
- { AR5K_RF_GAIN(5), { 0x00000020, 0x00000020 } },
- { AR5K_RF_GAIN(6), { 0x00000060, 0x00000060 } },
- { AR5K_RF_GAIN(7), { 0x000001a1, 0x000001a1 } },
- { AR5K_RF_GAIN(8), { 0x000001e1, 0x000001e1 } },
- { AR5K_RF_GAIN(9), { 0x00000021, 0x00000021 } },
- { AR5K_RF_GAIN(10), { 0x00000061, 0x00000061 } },
- { AR5K_RF_GAIN(11), { 0x00000162, 0x00000162 } },
- { AR5K_RF_GAIN(12), { 0x000001a2, 0x000001a2 } },
- { AR5K_RF_GAIN(13), { 0x000001e2, 0x000001e2 } },
- { AR5K_RF_GAIN(14), { 0x00000022, 0x00000022 } },
- { AR5K_RF_GAIN(15), { 0x00000062, 0x00000062 } },
- { AR5K_RF_GAIN(16), { 0x00000163, 0x00000163 } },
- { AR5K_RF_GAIN(17), { 0x000001a3, 0x000001a3 } },
- { AR5K_RF_GAIN(18), { 0x000001e3, 0x000001e3 } },
- { AR5K_RF_GAIN(19), { 0x00000023, 0x00000023 } },
- { AR5K_RF_GAIN(20), { 0x00000063, 0x00000063 } },
- { AR5K_RF_GAIN(21), { 0x00000184, 0x00000184 } },
- { AR5K_RF_GAIN(22), { 0x000001c4, 0x000001c4 } },
- { AR5K_RF_GAIN(23), { 0x00000004, 0x00000004 } },
- { AR5K_RF_GAIN(24), { 0x000001ea, 0x0000000b } },
- { AR5K_RF_GAIN(25), { 0x0000002a, 0x0000004b } },
- { AR5K_RF_GAIN(26), { 0x0000006a, 0x0000008b } },
- { AR5K_RF_GAIN(27), { 0x000000aa, 0x000001ac } },
- { AR5K_RF_GAIN(28), { 0x000001ab, 0x000001ec } },
- { AR5K_RF_GAIN(29), { 0x000001eb, 0x0000002c } },
- { AR5K_RF_GAIN(30), { 0x0000002b, 0x00000012 } },
- { AR5K_RF_GAIN(31), { 0x0000006b, 0x00000052 } },
- { AR5K_RF_GAIN(32), { 0x000000ab, 0x00000092 } },
- { AR5K_RF_GAIN(33), { 0x000001ac, 0x00000193 } },
- { AR5K_RF_GAIN(34), { 0x000001ec, 0x000001d3 } },
- { AR5K_RF_GAIN(35), { 0x0000002c, 0x00000013 } },
- { AR5K_RF_GAIN(36), { 0x0000003a, 0x00000053 } },
- { AR5K_RF_GAIN(37), { 0x0000007a, 0x00000093 } },
- { AR5K_RF_GAIN(38), { 0x000000ba, 0x00000194 } },
- { AR5K_RF_GAIN(39), { 0x000001bb, 0x000001d4 } },
- { AR5K_RF_GAIN(40), { 0x000001fb, 0x00000014 } },
- { AR5K_RF_GAIN(41), { 0x0000003b, 0x0000003a } },
- { AR5K_RF_GAIN(42), { 0x0000007b, 0x0000007a } },
- { AR5K_RF_GAIN(43), { 0x000000bb, 0x000000ba } },
- { AR5K_RF_GAIN(44), { 0x000001bc, 0x000001bb } },
- { AR5K_RF_GAIN(45), { 0x000001fc, 0x000001fb } },
- { AR5K_RF_GAIN(46), { 0x0000003c, 0x0000003b } },
- { AR5K_RF_GAIN(47), { 0x0000007c, 0x0000007b } },
- { AR5K_RF_GAIN(48), { 0x000000bc, 0x000000bb } },
- { AR5K_RF_GAIN(49), { 0x000000fc, 0x000001bc } },
- { AR5K_RF_GAIN(50), { 0x000000fc, 0x000001fc } },
- { AR5K_RF_GAIN(51), { 0x000000fc, 0x0000003c } },
- { AR5K_RF_GAIN(52), { 0x000000fc, 0x0000007c } },
- { AR5K_RF_GAIN(53), { 0x000000fc, 0x000000bc } },
- { AR5K_RF_GAIN(54), { 0x000000fc, 0x000000fc } },
- { AR5K_RF_GAIN(55), { 0x000000fc, 0x000000fc } },
- { AR5K_RF_GAIN(56), { 0x000000fc, 0x000000fc } },
- { AR5K_RF_GAIN(57), { 0x000000fc, 0x000000fc } },
- { AR5K_RF_GAIN(58), { 0x000000fc, 0x000000fc } },
- { AR5K_RF_GAIN(59), { 0x000000fc, 0x000000fc } },
- { AR5K_RF_GAIN(60), { 0x000000fc, 0x000000fc } },
- { AR5K_RF_GAIN(61), { 0x000000fc, 0x000000fc } },
- { AR5K_RF_GAIN(62), { 0x000000fc, 0x000000fc } },
- { AR5K_RF_GAIN(63), { 0x000000fc, 0x000000fc } },
-};
-
-/* Initial RF Gain settings for RF5413 */
-static const struct ath5k_ini_rfgain rfgain_5413[] = {
- /* 5Ghz 2Ghz */
- { AR5K_RF_GAIN(0), { 0x00000000, 0x00000000 } },
- { AR5K_RF_GAIN(1), { 0x00000040, 0x00000040 } },
- { AR5K_RF_GAIN(2), { 0x00000080, 0x00000080 } },
- { AR5K_RF_GAIN(3), { 0x000001a1, 0x00000161 } },
- { AR5K_RF_GAIN(4), { 0x000001e1, 0x000001a1 } },
- { AR5K_RF_GAIN(5), { 0x00000021, 0x000001e1 } },
- { AR5K_RF_GAIN(6), { 0x00000061, 0x00000021 } },
- { AR5K_RF_GAIN(7), { 0x00000188, 0x00000061 } },
- { AR5K_RF_GAIN(8), { 0x000001c8, 0x00000188 } },
- { AR5K_RF_GAIN(9), { 0x00000008, 0x000001c8 } },
- { AR5K_RF_GAIN(10), { 0x00000048, 0x00000008 } },
- { AR5K_RF_GAIN(11), { 0x00000088, 0x00000048 } },
- { AR5K_RF_GAIN(12), { 0x000001a9, 0x00000088 } },
- { AR5K_RF_GAIN(13), { 0x000001e9, 0x00000169 } },
- { AR5K_RF_GAIN(14), { 0x00000029, 0x000001a9 } },
- { AR5K_RF_GAIN(15), { 0x00000069, 0x000001e9 } },
- { AR5K_RF_GAIN(16), { 0x000001d0, 0x00000029 } },
- { AR5K_RF_GAIN(17), { 0x00000010, 0x00000069 } },
- { AR5K_RF_GAIN(18), { 0x00000050, 0x00000190 } },
- { AR5K_RF_GAIN(19), { 0x00000090, 0x000001d0 } },
- { AR5K_RF_GAIN(20), { 0x000001b1, 0x00000010 } },
- { AR5K_RF_GAIN(21), { 0x000001f1, 0x00000050 } },
- { AR5K_RF_GAIN(22), { 0x00000031, 0x00000090 } },
- { AR5K_RF_GAIN(23), { 0x00000071, 0x00000171 } },
- { AR5K_RF_GAIN(24), { 0x000001b8, 0x000001b1 } },
- { AR5K_RF_GAIN(25), { 0x000001f8, 0x000001f1 } },
- { AR5K_RF_GAIN(26), { 0x00000038, 0x00000031 } },
- { AR5K_RF_GAIN(27), { 0x00000078, 0x00000071 } },
- { AR5K_RF_GAIN(28), { 0x00000199, 0x00000198 } },
- { AR5K_RF_GAIN(29), { 0x000001d9, 0x000001d8 } },
- { AR5K_RF_GAIN(30), { 0x00000019, 0x00000018 } },
- { AR5K_RF_GAIN(31), { 0x00000059, 0x00000058 } },
- { AR5K_RF_GAIN(32), { 0x00000099, 0x00000098 } },
- { AR5K_RF_GAIN(33), { 0x000000d9, 0x00000179 } },
- { AR5K_RF_GAIN(34), { 0x000000f9, 0x000001b9 } },
- { AR5K_RF_GAIN(35), { 0x000000f9, 0x000001f9 } },
- { AR5K_RF_GAIN(36), { 0x000000f9, 0x00000039 } },
- { AR5K_RF_GAIN(37), { 0x000000f9, 0x00000079 } },
- { AR5K_RF_GAIN(38), { 0x000000f9, 0x000000b9 } },
- { AR5K_RF_GAIN(39), { 0x000000f9, 0x000000f9 } },
- { AR5K_RF_GAIN(40), { 0x000000f9, 0x000000f9 } },
- { AR5K_RF_GAIN(41), { 0x000000f9, 0x000000f9 } },
- { AR5K_RF_GAIN(42), { 0x000000f9, 0x000000f9 } },
- { AR5K_RF_GAIN(43), { 0x000000f9, 0x000000f9 } },
- { AR5K_RF_GAIN(44), { 0x000000f9, 0x000000f9 } },
- { AR5K_RF_GAIN(45), { 0x000000f9, 0x000000f9 } },
- { AR5K_RF_GAIN(46), { 0x000000f9, 0x000000f9 } },
- { AR5K_RF_GAIN(47), { 0x000000f9, 0x000000f9 } },
- { AR5K_RF_GAIN(48), { 0x000000f9, 0x000000f9 } },
- { AR5K_RF_GAIN(49), { 0x000000f9, 0x000000f9 } },
- { AR5K_RF_GAIN(50), { 0x000000f9, 0x000000f9 } },
- { AR5K_RF_GAIN(51), { 0x000000f9, 0x000000f9 } },
- { AR5K_RF_GAIN(52), { 0x000000f9, 0x000000f9 } },
- { AR5K_RF_GAIN(53), { 0x000000f9, 0x000000f9 } },
- { AR5K_RF_GAIN(54), { 0x000000f9, 0x000000f9 } },
- { AR5K_RF_GAIN(55), { 0x000000f9, 0x000000f9 } },
- { AR5K_RF_GAIN(56), { 0x000000f9, 0x000000f9 } },
- { AR5K_RF_GAIN(57), { 0x000000f9, 0x000000f9 } },
- { AR5K_RF_GAIN(58), { 0x000000f9, 0x000000f9 } },
- { AR5K_RF_GAIN(59), { 0x000000f9, 0x000000f9 } },
- { AR5K_RF_GAIN(60), { 0x000000f9, 0x000000f9 } },
- { AR5K_RF_GAIN(61), { 0x000000f9, 0x000000f9 } },
- { AR5K_RF_GAIN(62), { 0x000000f9, 0x000000f9 } },
- { AR5K_RF_GAIN(63), { 0x000000f9, 0x000000f9 } },
-};
-
-/* Initial RF Gain settings for RF2413 */
-static const struct ath5k_ini_rfgain rfgain_2413[] = {
- { AR5K_RF_GAIN(0), { 0x00000000 } },
- { AR5K_RF_GAIN(1), { 0x00000040 } },
- { AR5K_RF_GAIN(2), { 0x00000080 } },
- { AR5K_RF_GAIN(3), { 0x00000181 } },
- { AR5K_RF_GAIN(4), { 0x000001c1 } },
- { AR5K_RF_GAIN(5), { 0x00000001 } },
- { AR5K_RF_GAIN(6), { 0x00000041 } },
- { AR5K_RF_GAIN(7), { 0x00000081 } },
- { AR5K_RF_GAIN(8), { 0x00000168 } },
- { AR5K_RF_GAIN(9), { 0x000001a8 } },
- { AR5K_RF_GAIN(10), { 0x000001e8 } },
- { AR5K_RF_GAIN(11), { 0x00000028 } },
- { AR5K_RF_GAIN(12), { 0x00000068 } },
- { AR5K_RF_GAIN(13), { 0x00000189 } },
- { AR5K_RF_GAIN(14), { 0x000001c9 } },
- { AR5K_RF_GAIN(15), { 0x00000009 } },
- { AR5K_RF_GAIN(16), { 0x00000049 } },
- { AR5K_RF_GAIN(17), { 0x00000089 } },
- { AR5K_RF_GAIN(18), { 0x00000190 } },
- { AR5K_RF_GAIN(19), { 0x000001d0 } },
- { AR5K_RF_GAIN(20), { 0x00000010 } },
- { AR5K_RF_GAIN(21), { 0x00000050 } },
- { AR5K_RF_GAIN(22), { 0x00000090 } },
- { AR5K_RF_GAIN(23), { 0x00000191 } },
- { AR5K_RF_GAIN(24), { 0x000001d1 } },
- { AR5K_RF_GAIN(25), { 0x00000011 } },
- { AR5K_RF_GAIN(26), { 0x00000051 } },
- { AR5K_RF_GAIN(27), { 0x00000091 } },
- { AR5K_RF_GAIN(28), { 0x00000178 } },
- { AR5K_RF_GAIN(29), { 0x000001b8 } },
- { AR5K_RF_GAIN(30), { 0x000001f8 } },
- { AR5K_RF_GAIN(31), { 0x00000038 } },
- { AR5K_RF_GAIN(32), { 0x00000078 } },
- { AR5K_RF_GAIN(33), { 0x00000199 } },
- { AR5K_RF_GAIN(34), { 0x000001d9 } },
- { AR5K_RF_GAIN(35), { 0x00000019 } },
- { AR5K_RF_GAIN(36), { 0x00000059 } },
- { AR5K_RF_GAIN(37), { 0x00000099 } },
- { AR5K_RF_GAIN(38), { 0x000000d9 } },
- { AR5K_RF_GAIN(39), { 0x000000f9 } },
- { AR5K_RF_GAIN(40), { 0x000000f9 } },
- { AR5K_RF_GAIN(41), { 0x000000f9 } },
- { AR5K_RF_GAIN(42), { 0x000000f9 } },
- { AR5K_RF_GAIN(43), { 0x000000f9 } },
- { AR5K_RF_GAIN(44), { 0x000000f9 } },
- { AR5K_RF_GAIN(45), { 0x000000f9 } },
- { AR5K_RF_GAIN(46), { 0x000000f9 } },
- { AR5K_RF_GAIN(47), { 0x000000f9 } },
- { AR5K_RF_GAIN(48), { 0x000000f9 } },
- { AR5K_RF_GAIN(49), { 0x000000f9 } },
- { AR5K_RF_GAIN(50), { 0x000000f9 } },
- { AR5K_RF_GAIN(51), { 0x000000f9 } },
- { AR5K_RF_GAIN(52), { 0x000000f9 } },
- { AR5K_RF_GAIN(53), { 0x000000f9 } },
- { AR5K_RF_GAIN(54), { 0x000000f9 } },
- { AR5K_RF_GAIN(55), { 0x000000f9 } },
- { AR5K_RF_GAIN(56), { 0x000000f9 } },
- { AR5K_RF_GAIN(57), { 0x000000f9 } },
- { AR5K_RF_GAIN(58), { 0x000000f9 } },
- { AR5K_RF_GAIN(59), { 0x000000f9 } },
- { AR5K_RF_GAIN(60), { 0x000000f9 } },
- { AR5K_RF_GAIN(61), { 0x000000f9 } },
- { AR5K_RF_GAIN(62), { 0x000000f9 } },
- { AR5K_RF_GAIN(63), { 0x000000f9 } },
-};
-
-/* Initial RF Gain settings for RF2425 */
-static const struct ath5k_ini_rfgain rfgain_2425[] = {
- { AR5K_RF_GAIN(0), { 0x00000000 } },
- { AR5K_RF_GAIN(1), { 0x00000040 } },
- { AR5K_RF_GAIN(2), { 0x00000080 } },
- { AR5K_RF_GAIN(3), { 0x00000181 } },
- { AR5K_RF_GAIN(4), { 0x000001c1 } },
- { AR5K_RF_GAIN(5), { 0x00000001 } },
- { AR5K_RF_GAIN(6), { 0x00000041 } },
- { AR5K_RF_GAIN(7), { 0x00000081 } },
- { AR5K_RF_GAIN(8), { 0x00000188 } },
- { AR5K_RF_GAIN(9), { 0x000001c8 } },
- { AR5K_RF_GAIN(10), { 0x00000008 } },
- { AR5K_RF_GAIN(11), { 0x00000048 } },
- { AR5K_RF_GAIN(12), { 0x00000088 } },
- { AR5K_RF_GAIN(13), { 0x00000189 } },
- { AR5K_RF_GAIN(14), { 0x000001c9 } },
- { AR5K_RF_GAIN(15), { 0x00000009 } },
- { AR5K_RF_GAIN(16), { 0x00000049 } },
- { AR5K_RF_GAIN(17), { 0x00000089 } },
- { AR5K_RF_GAIN(18), { 0x000001b0 } },
- { AR5K_RF_GAIN(19), { 0x000001f0 } },
- { AR5K_RF_GAIN(20), { 0x00000030 } },
- { AR5K_RF_GAIN(21), { 0x00000070 } },
- { AR5K_RF_GAIN(22), { 0x00000171 } },
- { AR5K_RF_GAIN(23), { 0x000001b1 } },
- { AR5K_RF_GAIN(24), { 0x000001f1 } },
- { AR5K_RF_GAIN(25), { 0x00000031 } },
- { AR5K_RF_GAIN(26), { 0x00000071 } },
- { AR5K_RF_GAIN(27), { 0x000001b8 } },
- { AR5K_RF_GAIN(28), { 0x000001f8 } },
- { AR5K_RF_GAIN(29), { 0x00000038 } },
- { AR5K_RF_GAIN(30), { 0x00000078 } },
- { AR5K_RF_GAIN(31), { 0x000000b8 } },
- { AR5K_RF_GAIN(32), { 0x000001b9 } },
- { AR5K_RF_GAIN(33), { 0x000001f9 } },
- { AR5K_RF_GAIN(34), { 0x00000039 } },
- { AR5K_RF_GAIN(35), { 0x00000079 } },
- { AR5K_RF_GAIN(36), { 0x000000b9 } },
- { AR5K_RF_GAIN(37), { 0x000000f9 } },
- { AR5K_RF_GAIN(38), { 0x000000f9 } },
- { AR5K_RF_GAIN(39), { 0x000000f9 } },
- { AR5K_RF_GAIN(40), { 0x000000f9 } },
- { AR5K_RF_GAIN(41), { 0x000000f9 } },
- { AR5K_RF_GAIN(42), { 0x000000f9 } },
- { AR5K_RF_GAIN(43), { 0x000000f9 } },
- { AR5K_RF_GAIN(44), { 0x000000f9 } },
- { AR5K_RF_GAIN(45), { 0x000000f9 } },
- { AR5K_RF_GAIN(46), { 0x000000f9 } },
- { AR5K_RF_GAIN(47), { 0x000000f9 } },
- { AR5K_RF_GAIN(48), { 0x000000f9 } },
- { AR5K_RF_GAIN(49), { 0x000000f9 } },
- { AR5K_RF_GAIN(50), { 0x000000f9 } },
- { AR5K_RF_GAIN(51), { 0x000000f9 } },
- { AR5K_RF_GAIN(52), { 0x000000f9 } },
- { AR5K_RF_GAIN(53), { 0x000000f9 } },
- { AR5K_RF_GAIN(54), { 0x000000f9 } },
- { AR5K_RF_GAIN(55), { 0x000000f9 } },
- { AR5K_RF_GAIN(56), { 0x000000f9 } },
- { AR5K_RF_GAIN(57), { 0x000000f9 } },
- { AR5K_RF_GAIN(58), { 0x000000f9 } },
- { AR5K_RF_GAIN(59), { 0x000000f9 } },
- { AR5K_RF_GAIN(60), { 0x000000f9 } },
- { AR5K_RF_GAIN(61), { 0x000000f9 } },
- { AR5K_RF_GAIN(62), { 0x000000f9 } },
- { AR5K_RF_GAIN(63), { 0x000000f9 } },
-};
-
-static const struct ath5k_gain_opt rfgain_opt_5112 = {
- 1,
- 8,
- {
- { { 3, 0, 0, 0, 0, 0, 0 }, 6 },
- { { 2, 0, 0, 0, 0, 0, 0 }, 0 },
- { { 1, 0, 0, 0, 0, 0, 0 }, -3 },
- { { 0, 0, 0, 0, 0, 0, 0 }, -6 },
- { { 0, 1, 1, 0, 0, 0, 0 }, -8 },
- { { 0, 1, 1, 0, 1, 1, 0 }, -10 },
- { { 0, 1, 0, 1, 1, 1, 0 }, -13 },
- { { 0, 1, 0, 1, 1, 0, 1 }, -16 },
- }
-};
+#include "rfbuffer.h"
+#include "rfgain.h"
/*
* Used to modify RF Banks before writing them to AR5K_RF_BUFFER
@@ -1297,7 +221,7 @@ static int ath5k_hw_rf5111_rfregs(struct ath5k_hw *ah,
{
struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
u32 *rf;
- const unsigned int rf_size = ARRAY_SIZE(rfregs_5111);
+ const unsigned int rf_size = ARRAY_SIZE(rfb_5111);
unsigned int i;
int obdb = -1, bank = -1;
u32 ee_mode;
@@ -1308,17 +232,17 @@ static int ath5k_hw_rf5111_rfregs(struct ath5k_hw *ah,
/* Copy values to modify them */
for (i = 0; i < rf_size; i++) {
- if (rfregs_5111[i].rf_bank >= AR5K_RF5111_INI_RF_MAX_BANKS) {
+ if (rfb_5111[i].rfb_bank >= AR5K_RF5111_INI_RF_MAX_BANKS) {
ATH5K_ERR(ah->ah_sc, "invalid bank\n");
return -EINVAL;
}
- if (bank != rfregs_5111[i].rf_bank) {
- bank = rfregs_5111[i].rf_bank;
+ if (bank != rfb_5111[i].rfb_bank) {
+ bank = rfb_5111[i].rfb_bank;
ah->ah_offset[bank] = i;
}
- rf[i] = rfregs_5111[i].rf_value[mode];
+ rf[i] = rfb_5111[i].rfb_mode_data[mode];
}
/* Modify bank 0 */
@@ -1384,7 +308,7 @@ static int ath5k_hw_rf5111_rfregs(struct ath5k_hw *ah,
/* Write RF values */
for (i = 0; i < rf_size; i++) {
AR5K_REG_WAIT(i);
- ath5k_hw_reg_write(ah, rf[i], rfregs_5111[i].rf_register);
+ ath5k_hw_reg_write(ah, rf[i], rfb_5111[i].rfb_ctrl_register);
}
return 0;
@@ -1396,7 +320,7 @@ static int ath5k_hw_rf5111_rfregs(struct ath5k_hw *ah,
static int ath5k_hw_rf5112_rfregs(struct ath5k_hw *ah,
struct ieee80211_channel *channel, unsigned int mode)
{
- const struct ath5k_ini_rf *rf_ini;
+ const struct ath5k_ini_rfbuffer *rf_ini;
struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
u32 *rf;
unsigned int rf_size, i;
@@ -1407,37 +331,27 @@ static int ath5k_hw_rf5112_rfregs(struct ath5k_hw *ah,
rf = ah->ah_rf_banks;
- if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_2112A
- && !test_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode)) {
- rf_ini = rfregs_2112a;
- rf_size = ARRAY_SIZE(rfregs_5112a);
- if (mode < 2) {
- ATH5K_ERR(ah->ah_sc, "invalid channel mode: %i\n",
- mode);
- return -EINVAL;
- }
- mode = mode - 2; /*no a/turboa modes for 2112*/
- } else if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
- rf_ini = rfregs_5112a;
- rf_size = ARRAY_SIZE(rfregs_5112a);
+ if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
+ rf_ini = rfb_5112a;
+ rf_size = ARRAY_SIZE(rfb_5112a);
} else {
- rf_ini = rfregs_5112;
- rf_size = ARRAY_SIZE(rfregs_5112);
+ rf_ini = rfb_5112;
+ rf_size = ARRAY_SIZE(rfb_5112);
}
/* Copy values to modify them */
for (i = 0; i < rf_size; i++) {
- if (rf_ini[i].rf_bank >= AR5K_RF5112_INI_RF_MAX_BANKS) {
+ if (rf_ini[i].rfb_bank >= AR5K_RF5112_INI_RF_MAX_BANKS) {
ATH5K_ERR(ah->ah_sc, "invalid bank\n");
return -EINVAL;
}
- if (bank != rf_ini[i].rf_bank) {
- bank = rf_ini[i].rf_bank;
+ if (bank != rf_ini[i].rfb_bank) {
+ bank = rf_ini[i].rfb_bank;
ah->ah_offset[bank] = i;
}
- rf[i] = rf_ini[i].rf_value[mode];
+ rf[i] = rf_ini[i].rfb_mode_data[mode];
}
/* Modify bank 6 */
@@ -1491,7 +405,7 @@ static int ath5k_hw_rf5112_rfregs(struct ath5k_hw *ah,
/* Write RF values */
for (i = 0; i < rf_size; i++)
- ath5k_hw_reg_write(ah, rf[i], rf_ini[i].rf_register);
+ ath5k_hw_reg_write(ah, rf[i], rf_ini[i].rfb_ctrl_register);
return 0;
}
@@ -1503,7 +417,7 @@ static int ath5k_hw_rf5112_rfregs(struct ath5k_hw *ah,
static int ath5k_hw_rf5413_rfregs(struct ath5k_hw *ah,
struct ieee80211_channel *channel, unsigned int mode)
{
- const struct ath5k_ini_rf *rf_ini;
+ const struct ath5k_ini_rfbuffer *rf_ini;
u32 *rf;
unsigned int rf_size, i;
int bank = -1;
@@ -1514,12 +428,12 @@ static int ath5k_hw_rf5413_rfregs(struct ath5k_hw *ah,
switch (ah->ah_radio) {
case AR5K_RF5413:
- rf_ini = rfregs_5413;
- rf_size = ARRAY_SIZE(rfregs_5413);
+ rf_ini = rfb_5413;
+ rf_size = ARRAY_SIZE(rfb_5413);
break;
case AR5K_RF2413:
- rf_ini = rfregs_2413;
- rf_size = ARRAY_SIZE(rfregs_2413);
+ rf_ini = rfb_2413;
+ rf_size = ARRAY_SIZE(rfb_2413);
if (mode < 2) {
ATH5K_ERR(ah->ah_sc,
@@ -1527,11 +441,10 @@ static int ath5k_hw_rf5413_rfregs(struct ath5k_hw *ah,
return -EINVAL;
}
- mode = mode - 2;
break;
case AR5K_RF2425:
- rf_ini = rfregs_2425;
- rf_size = ARRAY_SIZE(rfregs_2425);
+ rf_ini = rfb_2425;
+ rf_size = ARRAY_SIZE(rfb_2425);
if (mode < 2) {
ATH5K_ERR(ah->ah_sc,
@@ -1539,12 +452,6 @@ static int ath5k_hw_rf5413_rfregs(struct ath5k_hw *ah,
return -EINVAL;
}
- /* Map b to g */
- if (mode == 2)
- mode = 0;
- else
- mode = mode - 3;
-
break;
default:
return -EINVAL;
@@ -1552,17 +459,17 @@ static int ath5k_hw_rf5413_rfregs(struct ath5k_hw *ah,
/* Copy values to modify them */
for (i = 0; i < rf_size; i++) {
- if (rf_ini[i].rf_bank >= AR5K_RF5112_INI_RF_MAX_BANKS) {
+ if (rf_ini[i].rfb_bank >= AR5K_RF5112_INI_RF_MAX_BANKS) {
ATH5K_ERR(ah->ah_sc, "invalid bank\n");
return -EINVAL;
}
- if (bank != rf_ini[i].rf_bank) {
- bank = rf_ini[i].rf_bank;
+ if (bank != rf_ini[i].rfb_bank) {
+ bank = rf_ini[i].rfb_bank;
ah->ah_offset[bank] = i;
}
- rf[i] = rf_ini[i].rf_value[mode];
+ rf[i] = rf_ini[i].rfb_mode_data[mode];
}
/*
@@ -1577,7 +484,7 @@ static int ath5k_hw_rf5413_rfregs(struct ath5k_hw *ah,
/* Write RF values */
for (i = 0; i < rf_size; i++)
- ath5k_hw_reg_write(ah, rf[i], rf_ini[i].rf_register);
+ ath5k_hw_reg_write(ah, rf[i], rf_ini[i].rfb_ctrl_register);
return 0;
}
@@ -1593,26 +500,26 @@ int ath5k_hw_rfregs(struct ath5k_hw *ah, struct ieee80211_channel *channel,
switch (ah->ah_radio) {
case AR5K_RF5111:
- ah->ah_rf_banks_size = sizeof(rfregs_5111);
+ ah->ah_rf_banks_size = sizeof(rfb_5111);
func = ath5k_hw_rf5111_rfregs;
break;
case AR5K_RF5112:
if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)
- ah->ah_rf_banks_size = sizeof(rfregs_5112a);
+ ah->ah_rf_banks_size = sizeof(rfb_5112a);
else
- ah->ah_rf_banks_size = sizeof(rfregs_5112);
+ ah->ah_rf_banks_size = sizeof(rfb_5112);
func = ath5k_hw_rf5112_rfregs;
break;
case AR5K_RF5413:
- ah->ah_rf_banks_size = sizeof(rfregs_5413);
+ ah->ah_rf_banks_size = sizeof(rfb_5413);
func = ath5k_hw_rf5413_rfregs;
break;
case AR5K_RF2413:
- ah->ah_rf_banks_size = sizeof(rfregs_2413);
+ ah->ah_rf_banks_size = sizeof(rfb_2413);
func = ath5k_hw_rf5413_rfregs;
break;
case AR5K_RF2425:
- ah->ah_rf_banks_size = sizeof(rfregs_2425);
+ ah->ah_rf_banks_size = sizeof(rfb_2425);
func = ath5k_hw_rf5413_rfregs;
break;
default:
@@ -1656,12 +563,10 @@ int ath5k_hw_rfgain(struct ath5k_hw *ah, unsigned int freq)
case AR5K_RF2413:
ath5k_rfg = rfgain_2413;
size = ARRAY_SIZE(rfgain_2413);
- freq = 0; /* only 2Ghz */
break;
case AR5K_RF2425:
ath5k_rfg = rfgain_2425;
size = ARRAY_SIZE(rfgain_2425);
- freq = 0; /* only 2Ghz */
break;
default:
return -EINVAL;
--
cgit v1.1
From 6f3b414aca060a847e243f676b8601731938eb48 Mon Sep 17 00:00:00 2001
From: Nick Kossifidis <mick@madwifi-project.org>
Date: Mon, 9 Feb 2009 06:03:41 +0200
Subject: ath5k: Update gain_F calibration code and add documentation
* Update and cleanup rf gain optimization code
* Add comments and refferences to docs and use sane function names
* Use only step index on ath5k_gain, no need to have a pointer to
the current step since we can determine te step from it's index,
this also allows us to put all other structs on rfgain.h and cleanup
ath5k.h a little
* No need for ah_rfgain variable, we use ah_gain.g_state for everything
* Tested on RF2112B chip but gain_F calibration is not yet done
(we will finish this on the next patch where we'll rewrite rf-buffer
handling)
* Use initial rf gain settings for 2316 and 2317 SoCs introduced on a previous patch
It seems big but it's mostly cleanup, very few functional changes have been made on phy.c
Signed-off-by: Nick Kossifidis <mickflemm@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
---
drivers/net/wireless/ath5k/phy.c | 403 +++++++++++++++++++++++++--------------
1 file changed, 264 insertions(+), 139 deletions(-)
(limited to 'drivers/net/wireless/ath5k/phy.c')
diff --git a/drivers/net/wireless/ath5k/phy.c b/drivers/net/wireless/ath5k/phy.c
index 5021749..2543a71 100644
--- a/drivers/net/wireless/ath5k/phy.c
+++ b/drivers/net/wireless/ath5k/phy.c
@@ -78,10 +78,104 @@ static unsigned int ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits,
return data;
}
-static u32 ath5k_hw_rfregs_gainf_corr(struct ath5k_hw *ah)
+/**********************\
+* RF Gain optimization *
+\**********************/
+
+/*
+ * This code is used to optimize rf gain on different environments
+ * (temprature mostly) based on feedback from a power detector.
+ *
+ * It's only used on RF5111 and RF5112, later RF chips seem to have
+ * auto adjustment on hw -notice they have a much smaller BANK 7 and
+ * no gain optimization ladder-.
+ *
+ * For more infos check out this patent doc
+ * http://www.freepatentsonline.com/7400691.html
+ *
+ * This paper describes power drops as seen on the receiver due to
+ * probe packets
+ * http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues
+ * %20of%20Power%20Control.pdf
+ *
+ * And this is the MadWiFi bug entry related to the above
+ * http://madwifi-project.org/ticket/1659
+ * with various measurements and diagrams
+ *
+ * TODO: Deal with power drops due to probes by setting an apropriate
+ * tx power on the probe packets ! Make this part of the calibration process.
+ */
+
+/* Initialize ah_gain durring attach */
+int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah)
+{
+ /* Initialize the gain optimization values */
+ switch (ah->ah_radio) {
+ case AR5K_RF5111:
+ ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default;
+ ah->ah_gain.g_low = 20;
+ ah->ah_gain.g_high = 35;
+ ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
+ break;
+ case AR5K_RF5112:
+ ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default;
+ ah->ah_gain.g_low = 20;
+ ah->ah_gain.g_high = 85;
+ ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+/* Schedule a gain probe check on the next transmited packet.
+ * That means our next packet is going to be sent with lower
+ * tx power and a Peak to Average Power Detector (PAPD) will try
+ * to measure the gain.
+ *
+ * TODO: Use propper tx power setting for the probe packet so
+ * that we don't observe a serious power drop on the receiver
+ *
+ * XXX: How about forcing a tx packet (bypassing PCU arbitrator etc)
+ * just after we enable the probe so that we don't mess with
+ * standard traffic ? Maybe it's time to use sw interrupts and
+ * a probe tasklet !!!
+ */
+static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah)
+{
+
+ /* Skip if gain calibration is inactive or
+ * we already handle a probe request */
+ if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE)
+ return;
+
+ ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_max,
+ AR5K_PHY_PAPD_PROBE_TXPOWER) |
+ AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE);
+
+ ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED;
+
+}
+
+/* Calculate gain_F measurement correction
+ * based on the current step for RF5112 rev. 2 */
+static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah)
{
u32 mix, step;
u32 *rf;
+ const struct ath5k_gain_opt *go;
+ const struct ath5k_gain_opt_step *g_step;
+
+ /* Only RF5112 Rev. 2 supports it */
+ if ((ah->ah_radio != AR5K_RF5112) ||
+ (ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A))
+ return 0;
+
+ go = &rfgain_opt_5112;
+
+ g_step = &go->go_step[ah->ah_gain.g_step_idx];
if (ah->ah_rf_banks == NULL)
return 0;
@@ -89,11 +183,15 @@ static u32 ath5k_hw_rfregs_gainf_corr(struct ath5k_hw *ah)
rf = ah->ah_rf_banks;
ah->ah_gain.g_f_corr = 0;
+ /* No VGA (Variable Gain Amplifier) override, skip */
if (ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 1, 36, 0, false) != 1)
return 0;
+ /* Mix gain stepping */
step = ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 4, 32, 0, false);
- mix = ah->ah_gain.g_step->gos_param[0];
+
+ /* Mix gain override */
+ mix = g_step->gos_param[0];
switch (mix) {
case 3:
@@ -113,9 +211,13 @@ static u32 ath5k_hw_rfregs_gainf_corr(struct ath5k_hw *ah)
return ah->ah_gain.g_f_corr;
}
-static bool ath5k_hw_rfregs_gain_readback(struct ath5k_hw *ah)
+/* Check if current gain_F measurement is in the range of our
+ * power detector windows. If we get a measurement outside range
+ * we know it's not accurate (detectors can't measure anything outside
+ * their detection window) so we must ignore it */
+static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah)
{
- u32 step, mix, level[4];
+ u32 step, mix_ovr, level[4];
u32 *rf;
if (ah->ah_rf_banks == NULL)
@@ -127,20 +229,20 @@ static bool ath5k_hw_rfregs_gain_readback(struct ath5k_hw *ah)
step = ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 6, 37, 0,
false);
level[0] = 0;
- level[1] = (step == 0x3f) ? 0x32 : step + 4;
- level[2] = (step != 0x3f) ? 0x40 : level[0];
- level[3] = level[2] + 0x32;
+ level[1] = (step == 63) ? 50 : step + 4;
+ level[2] = (step != 63) ? 64 : level[0];
+ level[3] = level[2] + 50 ;
ah->ah_gain.g_high = level[3] -
- (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5);
+ (step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5);
ah->ah_gain.g_low = level[0] +
- (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0);
+ (step == 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0);
} else {
- mix = ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 1, 36, 0,
+ mix_ovr = ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 1, 36, 0,
false);
level[0] = level[2] = 0;
- if (mix == 1) {
+ if (mix_ovr == 1) {
level[1] = level[3] = 83;
} else {
level[1] = level[3] = 107;
@@ -154,9 +256,12 @@ static bool ath5k_hw_rfregs_gain_readback(struct ath5k_hw *ah)
ah->ah_gain.g_current <= level[3]);
}
-static s32 ath5k_hw_rfregs_gain_adjust(struct ath5k_hw *ah)
+/* Perform gain_F adjustment by choosing the right set
+ * of parameters from rf gain optimization ladder */
+static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah)
{
const struct ath5k_gain_opt *go;
+ const struct ath5k_gain_opt_step *g_step;
int ret = 0;
switch (ah->ah_radio) {
@@ -170,35 +275,39 @@ static s32 ath5k_hw_rfregs_gain_adjust(struct ath5k_hw *ah)
return 0;
}
- ah->ah_gain.g_step = &go->go_step[ah->ah_gain.g_step_idx];
+ g_step = &go->go_step[ah->ah_gain.g_step_idx];
if (ah->ah_gain.g_current >= ah->ah_gain.g_high) {
+
+ /* Reached maximum */
if (ah->ah_gain.g_step_idx == 0)
return -1;
+
for (ah->ah_gain.g_target = ah->ah_gain.g_current;
ah->ah_gain.g_target >= ah->ah_gain.g_high &&
ah->ah_gain.g_step_idx > 0;
- ah->ah_gain.g_step =
- &go->go_step[ah->ah_gain.g_step_idx])
+ g_step = &go->go_step[ah->ah_gain.g_step_idx])
ah->ah_gain.g_target -= 2 *
(go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain -
- ah->ah_gain.g_step->gos_gain);
+ g_step->gos_gain);
ret = 1;
goto done;
}
if (ah->ah_gain.g_current <= ah->ah_gain.g_low) {
+
+ /* Reached minimum */
if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1))
return -2;
+
for (ah->ah_gain.g_target = ah->ah_gain.g_current;
ah->ah_gain.g_target <= ah->ah_gain.g_low &&
ah->ah_gain.g_step_idx < go->go_steps_count-1;
- ah->ah_gain.g_step =
- &go->go_step[ah->ah_gain.g_step_idx])
+ g_step = &go->go_step[ah->ah_gain.g_step_idx])
ah->ah_gain.g_target -= 2 *
(go->go_step[++ah->ah_gain.g_step_idx].gos_gain -
- ah->ah_gain.g_step->gos_gain);
+ g_step->gos_gain);
ret = 2;
goto done;
@@ -213,6 +322,135 @@ done:
return ret;
}
+/* Main callback for thermal rf gain calibration engine
+ * Check for a new gain reading and schedule an adjustment
+ * if needed.
+ *
+ * TODO: Use sw interrupt to schedule reset if gain_F needs
+ * adjustment */
+enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah)
+{
+ u32 data, type;
+ struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
+
+ ATH5K_TRACE(ah->ah_sc);
+
+ if (ah->ah_rf_banks == NULL ||
+ ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE)
+ return AR5K_RFGAIN_INACTIVE;
+
+ /* No check requested, either engine is inactive
+ * or an adjustment is already requested */
+ if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED)
+ goto done;
+
+ /* Read the PAPD (Peak to Average Power Detector)
+ * register */
+ data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE);
+
+ /* No probe is scheduled, read gain_F measurement */
+ if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) {
+ ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S;
+ type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE);
+
+ /* If tx packet is CCK correct the gain_F measurement
+ * by cck ofdm gain delta */
+ if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) {
+ if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)
+ ah->ah_gain.g_current +=
+ ee->ee_cck_ofdm_gain_delta;
+ else
+ ah->ah_gain.g_current +=
+ AR5K_GAIN_CCK_PROBE_CORR;
+ }
+
+ /* Further correct gain_F measurement for
+ * RF5112A radios */
+ if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
+ ath5k_hw_rf_gainf_corr(ah);
+ ah->ah_gain.g_current =
+ ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ?
+ (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) :
+ 0;
+ }
+
+ /* Check if measurement is ok and if we need
+ * to adjust gain, schedule a gain adjustment,
+ * else switch back to the acive state */
+ if (ath5k_hw_rf_check_gainf_readback(ah) &&
+ AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) &&
+ ath5k_hw_rf_gainf_adjust(ah)) {
+ ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE;
+ } else {
+ ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
+ }
+ }
+
+done:
+ return ah->ah_gain.g_state;
+}
+
+/* Write initial rf gain table to set the RF sensitivity
+ * this one works on all RF chips and has nothing to do
+ * with gain_F calibration */
+int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq)
+{
+ const struct ath5k_ini_rfgain *ath5k_rfg;
+ unsigned int i, size;
+
+ switch (ah->ah_radio) {
+ case AR5K_RF5111:
+ ath5k_rfg = rfgain_5111;
+ size = ARRAY_SIZE(rfgain_5111);
+ break;
+ case AR5K_RF5112:
+ ath5k_rfg = rfgain_5112;
+ size = ARRAY_SIZE(rfgain_5112);
+ break;
+ case AR5K_RF2413:
+ ath5k_rfg = rfgain_2413;
+ size = ARRAY_SIZE(rfgain_2413);
+ break;
+ case AR5K_RF2316:
+ ath5k_rfg = rfgain_2316;
+ size = ARRAY_SIZE(rfgain_2316);
+ break;
+ case AR5K_RF5413:
+ ath5k_rfg = rfgain_5413;
+ size = ARRAY_SIZE(rfgain_5413);
+ break;
+ case AR5K_RF2317:
+ case AR5K_RF2425:
+ ath5k_rfg = rfgain_2425;
+ size = ARRAY_SIZE(rfgain_2425);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ switch (freq) {
+ case AR5K_INI_RFGAIN_2GHZ:
+ case AR5K_INI_RFGAIN_5GHZ:
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ for (i = 0; i < size; i++) {
+ AR5K_REG_WAIT(i);
+ ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[freq],
+ (u32)ath5k_rfg[i].rfg_register);
+ }
+
+ return 0;
+}
+
+
+
+/********************\
+* RF Registers setup *
+\********************/
+
/*
* Read EEPROM Calibration data, modify RF Banks and Initialize RF5111
*/
@@ -311,6 +549,8 @@ static int ath5k_hw_rf5111_rfregs(struct ath5k_hw *ah,
ath5k_hw_reg_write(ah, rf[i], rfb_5111[i].rfb_ctrl_register);
}
+ ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
+
return 0;
}
@@ -407,6 +647,9 @@ static int ath5k_hw_rf5112_rfregs(struct ath5k_hw *ah,
for (i = 0; i < rf_size; i++)
ath5k_hw_reg_write(ah, rf[i], rf_ini[i].rfb_ctrl_register);
+
+ ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
+
return 0;
}
@@ -536,125 +779,12 @@ int ath5k_hw_rfregs(struct ath5k_hw *ah, struct ieee80211_channel *channel,
}
ret = func(ah, channel, mode);
- if (!ret)
- ah->ah_rf_gain = AR5K_RFGAIN_INACTIVE;
return ret;
}
-int ath5k_hw_rfgain(struct ath5k_hw *ah, unsigned int freq)
-{
- const struct ath5k_ini_rfgain *ath5k_rfg;
- unsigned int i, size;
- switch (ah->ah_radio) {
- case AR5K_RF5111:
- ath5k_rfg = rfgain_5111;
- size = ARRAY_SIZE(rfgain_5111);
- break;
- case AR5K_RF5112:
- ath5k_rfg = rfgain_5112;
- size = ARRAY_SIZE(rfgain_5112);
- break;
- case AR5K_RF5413:
- ath5k_rfg = rfgain_5413;
- size = ARRAY_SIZE(rfgain_5413);
- break;
- case AR5K_RF2413:
- ath5k_rfg = rfgain_2413;
- size = ARRAY_SIZE(rfgain_2413);
- break;
- case AR5K_RF2425:
- ath5k_rfg = rfgain_2425;
- size = ARRAY_SIZE(rfgain_2425);
- break;
- default:
- return -EINVAL;
- }
- switch (freq) {
- case AR5K_INI_RFGAIN_2GHZ:
- case AR5K_INI_RFGAIN_5GHZ:
- break;
- default:
- return -EINVAL;
- }
-
- for (i = 0; i < size; i++) {
- AR5K_REG_WAIT(i);
- ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[freq],
- (u32)ath5k_rfg[i].rfg_register);
- }
-
- return 0;
-}
-
-enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath5k_hw *ah)
-{
- u32 data, type;
-
- ATH5K_TRACE(ah->ah_sc);
-
- if (ah->ah_rf_banks == NULL || !ah->ah_gain.g_active ||
- ah->ah_version <= AR5K_AR5211)
- return AR5K_RFGAIN_INACTIVE;
-
- if (ah->ah_rf_gain != AR5K_RFGAIN_READ_REQUESTED)
- goto done;
-
- data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE);
-
- if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) {
- ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S;
- type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE);
-
- if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK)
- ah->ah_gain.g_current += AR5K_GAIN_CCK_PROBE_CORR;
-
- if (ah->ah_radio >= AR5K_RF5112) {
- ath5k_hw_rfregs_gainf_corr(ah);
- ah->ah_gain.g_current =
- ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ?
- (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) :
- 0;
- }
-
- if (ath5k_hw_rfregs_gain_readback(ah) &&
- AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) &&
- ath5k_hw_rfregs_gain_adjust(ah))
- ah->ah_rf_gain = AR5K_RFGAIN_NEED_CHANGE;
- }
-
-done:
- return ah->ah_rf_gain;
-}
-
-int ath5k_hw_set_rfgain_opt(struct ath5k_hw *ah)
-{
- /* Initialize the gain optimization values */
- switch (ah->ah_radio) {
- case AR5K_RF5111:
- ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default;
- ah->ah_gain.g_step =
- &rfgain_opt_5111.go_step[ah->ah_gain.g_step_idx];
- ah->ah_gain.g_low = 20;
- ah->ah_gain.g_high = 35;
- ah->ah_gain.g_active = 1;
- break;
- case AR5K_RF5112:
- ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default;
- ah->ah_gain.g_step =
- &rfgain_opt_5112.go_step[ah->ah_gain.g_step_idx];
- ah->ah_gain.g_low = 20;
- ah->ah_gain.g_high = 85;
- ah->ah_gain.g_active = 1;
- break;
- default:
- return -EINVAL;
- }
-
- return 0;
-}
/**************************\
PHY/RF channel functions
@@ -1176,13 +1306,8 @@ done:
* as often as I/Q calibration.*/
ath5k_hw_noise_floor_calibration(ah, channel->center_freq);
- /* Request RF gain */
- if (channel->hw_value & CHANNEL_5GHZ) {
- ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_max,
- AR5K_PHY_PAPD_PROBE_TXPOWER) |
- AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE);
- ah->ah_rf_gain = AR5K_RFGAIN_READ_REQUESTED;
- }
+ /* Initiate a gain_F calibration */
+ ath5k_hw_request_rfgain_probe(ah);
return 0;
}
--
cgit v1.1
From 8892e4ec62f1553d36c88e613890aa4d7c5a372e Mon Sep 17 00:00:00 2001
From: Nick Kossifidis <mick@madwifi-project.org>
Date: Mon, 9 Feb 2009 06:06:34 +0200
Subject: ath5k: Update RF Buffer handling
* Use the new way to modify rf buffer and put some rf buffer
documentation on rfbufer.h
* Merge all rf regs functions to one
* Sync with legacy HAL and Sam's HAL
* Set gain_F settings so that gain_F optimization engine works
on RF5111/RF5112 (note that both HALs only use step 0 for RF5111
and they don't use gain_F optimization for this chip, code is
there but is never used)
Signed-off-by: Nick Kossifidis <mickflemm@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
---
drivers/net/wireless/ath5k/phy.c | 571 ++++++++++++++++++++-------------------
1 file changed, 298 insertions(+), 273 deletions(-)
(limited to 'drivers/net/wireless/ath5k/phy.c')
diff --git a/drivers/net/wireless/ath5k/phy.c b/drivers/net/wireless/ath5k/phy.c
index 2543a71..81f5beb 100644
--- a/drivers/net/wireless/ath5k/phy.c
+++ b/drivers/net/wireless/ath5k/phy.c
@@ -32,48 +32,80 @@
/*
* Used to modify RF Banks before writing them to AR5K_RF_BUFFER
*/
-static unsigned int ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits,
- u32 first, u32 col, bool set)
+static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah,
+ const struct ath5k_rf_reg *rf_regs,
+ u32 val, u8 reg_id, bool set)
{
- u32 mask, entry, last, data, shift, position;
- s32 left;
+ const struct ath5k_rf_reg *rfreg = NULL;
+ u8 offset, bank, num_bits, col, position;
+ u16 entry;
+ u32 mask, data, last_bit, bits_shifted, first_bit;
+ u32 *rfb;
+ s32 bits_left;
int i;
data = 0;
+ rfb = ah->ah_rf_banks;
- if (rf == NULL)
+ for (i = 0; i < ah->ah_rf_regs_count; i++) {
+ if (rf_regs[i].index == reg_id) {
+ rfreg = &rf_regs[i];
+ break;
+ }
+ }
+
+ if (rfb == NULL || rfreg == NULL) {
+ ATH5K_PRINTF("Rf register not found!\n");
/* should not happen */
return 0;
+ }
+
+ bank = rfreg->bank;
+ num_bits = rfreg->field.len;
+ first_bit = rfreg->field.pos;
+ col = rfreg->field.col;
+
+ /* first_bit is an offset from bank's
+ * start. Since we have all banks on
+ * the same array, we use this offset
+ * to mark each bank's start */
+ offset = ah->ah_offset[bank];
- if (!(col <= 3 && bits <= 32 && first + bits <= 319)) {
+ /* Boundary check */
+ if (!(col <= 3 && num_bits <= 32 && first_bit + num_bits <= 319)) {
ATH5K_PRINTF("invalid values at offset %u\n", offset);
return 0;
}
- entry = ((first - 1) / 8) + offset;
- position = (first - 1) % 8;
+ entry = ((first_bit - 1) / 8) + offset;
+ position = (first_bit - 1) % 8;
if (set)
- data = ath5k_hw_bitswap(reg, bits);
+ data = ath5k_hw_bitswap(val, num_bits);
+
+ for (bits_shifted = 0, bits_left = num_bits; bits_left > 0;
+ position = 0, entry++) {
+
+ last_bit = (position + bits_left > 8) ? 8 :
+ position + bits_left;
- for (i = shift = 0, left = bits; left > 0; position = 0, entry++, i++) {
- last = (position + left > 8) ? 8 : position + left;
- mask = (((1 << last) - 1) ^ ((1 << position) - 1)) << (col * 8);
+ mask = (((1 << last_bit) - 1) ^ ((1 << position) - 1)) <<
+ (col * 8);
if (set) {
- rf[entry] &= ~mask;
- rf[entry] |= ((data << position) << (col * 8)) & mask;
+ rfb[entry] &= ~mask;
+ rfb[entry] |= ((data << position) << (col * 8)) & mask;
data >>= (8 - position);
} else {
- data = (((rf[entry] & mask) >> (col * 8)) >> position)
- << shift;
- shift += last - position;
+ data |= (((rfb[entry] & mask) >> (col * 8)) >> position)
+ << bits_shifted;
+ bits_shifted += last_bit - position;
}
- left -= 8 - position;
+ bits_left -= 8 - position;
}
- data = set ? 1 : ath5k_hw_bitswap(data, bits);
+ data = set ? 1 : ath5k_hw_bitswap(data, num_bits);
return data;
}
@@ -167,6 +199,7 @@ static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah)
u32 *rf;
const struct ath5k_gain_opt *go;
const struct ath5k_gain_opt_step *g_step;
+ const struct ath5k_rf_reg *rf_regs;
/* Only RF5112 Rev. 2 supports it */
if ((ah->ah_radio != AR5K_RF5112) ||
@@ -174,6 +207,8 @@ static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah)
return 0;
go = &rfgain_opt_5112;
+ rf_regs = rf_regs_5112a;
+ ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
g_step = &go->go_step[ah->ah_gain.g_step_idx];
@@ -184,11 +219,11 @@ static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah)
ah->ah_gain.g_f_corr = 0;
/* No VGA (Variable Gain Amplifier) override, skip */
- if (ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 1, 36, 0, false) != 1)
+ if (ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, false) != 1)
return 0;
/* Mix gain stepping */
- step = ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 4, 32, 0, false);
+ step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXGAIN_STEP, false);
/* Mix gain override */
mix = g_step->gos_param[0];
@@ -217,6 +252,7 @@ static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah)
* their detection window) so we must ignore it */
static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah)
{
+ const struct ath5k_rf_reg *rf_regs;
u32 step, mix_ovr, level[4];
u32 *rf;
@@ -226,8 +262,13 @@ static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah)
rf = ah->ah_rf_banks;
if (ah->ah_radio == AR5K_RF5111) {
- step = ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 6, 37, 0,
- false);
+
+ rf_regs = rf_regs_5111;
+ ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
+
+ step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_RFGAIN_STEP,
+ false);
+
level[0] = 0;
level[1] = (step == 63) ? 50 : step + 4;
level[2] = (step != 63) ? 64 : level[0];
@@ -238,8 +279,13 @@ static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah)
ah->ah_gain.g_low = level[0] +
(step == 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0);
} else {
- mix_ovr = ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 1, 36, 0,
- false);
+
+ rf_regs = rf_regs_5112;
+ ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
+
+ mix_ovr = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR,
+ false);
+
level[0] = level[2] = 0;
if (mix_ovr == 1) {
@@ -451,341 +497,320 @@ int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq)
* RF Registers setup *
\********************/
+
/*
- * Read EEPROM Calibration data, modify RF Banks and Initialize RF5111
+ * Setup RF registers by writing rf buffer on hw
*/
-static int ath5k_hw_rf5111_rfregs(struct ath5k_hw *ah,
- struct ieee80211_channel *channel, unsigned int mode)
+int ath5k_hw_rfregs_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
+ unsigned int mode)
{
+ const struct ath5k_rf_reg *rf_regs;
+ const struct ath5k_ini_rfbuffer *ini_rfb;
+ const struct ath5k_gain_opt *go = NULL;
+ const struct ath5k_gain_opt_step *g_step;
struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
- u32 *rf;
- const unsigned int rf_size = ARRAY_SIZE(rfb_5111);
- unsigned int i;
- int obdb = -1, bank = -1;
- u32 ee_mode;
+ u8 ee_mode = 0;
+ u32 *rfb;
+ int i, obdb = -1, bank = -1;
- AR5K_ASSERT_ENTRY(mode, AR5K_MODE_MAX);
+ switch (ah->ah_radio) {
+ case AR5K_RF5111:
+ rf_regs = rf_regs_5111;
+ ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
+ ini_rfb = rfb_5111;
+ ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111);
+ go = &rfgain_opt_5111;
+ break;
+ case AR5K_RF5112:
+ if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
+ rf_regs = rf_regs_5112a;
+ ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
+ ini_rfb = rfb_5112a;
+ ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a);
+ } else {
+ rf_regs = rf_regs_5112;
+ ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
+ ini_rfb = rfb_5112;
+ ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112);
+ }
+ go = &rfgain_opt_5112;
+ break;
+ case AR5K_RF2413:
+ rf_regs = rf_regs_2413;
+ ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413);
+ ini_rfb = rfb_2413;
+ ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413);
+ break;
+ case AR5K_RF2316:
+ rf_regs = rf_regs_2316;
+ ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316);
+ ini_rfb = rfb_2316;
+ ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316);
+ break;
+ case AR5K_RF5413:
+ rf_regs = rf_regs_5413;
+ ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413);
+ ini_rfb = rfb_5413;
+ ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413);
+ break;
+ case AR5K_RF2317:
+ rf_regs = rf_regs_2425;
+ ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
+ ini_rfb = rfb_2317;
+ ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317);
+ break;
+ case AR5K_RF2425:
+ rf_regs = rf_regs_2425;
+ ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
+ if (ah->ah_mac_srev < AR5K_SREV_AR2417) {
+ ini_rfb = rfb_2425;
+ ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425);
+ } else {
+ ini_rfb = rfb_2417;
+ ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417);
+ }
+ break;
+ default:
+ return -EINVAL;
+ }
- rf = ah->ah_rf_banks;
+ /* If it's the first time we set rf buffer, allocate
+ * ah->ah_rf_banks based on ah->ah_rf_banks_size
+ * we set above */
+ if (ah->ah_rf_banks == NULL) {
+ ah->ah_rf_banks = kmalloc(sizeof(u32) * ah->ah_rf_banks_size,
+ GFP_KERNEL);
+ if (ah->ah_rf_banks == NULL) {
+ ATH5K_ERR(ah->ah_sc, "out of memory\n");
+ return -ENOMEM;
+ }
+ }
/* Copy values to modify them */
- for (i = 0; i < rf_size; i++) {
- if (rfb_5111[i].rfb_bank >= AR5K_RF5111_INI_RF_MAX_BANKS) {
+ rfb = ah->ah_rf_banks;
+
+ for (i = 0; i < ah->ah_rf_banks_size; i++) {
+ if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) {
ATH5K_ERR(ah->ah_sc, "invalid bank\n");
return -EINVAL;
}
- if (bank != rfb_5111[i].rfb_bank) {
- bank = rfb_5111[i].rfb_bank;
+ /* Bank changed, write down the offset */
+ if (bank != ini_rfb[i].rfb_bank) {
+ bank = ini_rfb[i].rfb_bank;
ah->ah_offset[bank] = i;
}
- rf[i] = rfb_5111[i].rfb_mode_data[mode];
+ rfb[i] = ini_rfb[i].rfb_mode_data[mode];
}
- /* Modify bank 0 */
+ /* Set Output and Driver bias current (OB/DB) */
if (channel->hw_value & CHANNEL_2GHZ) {
+
if (channel->hw_value & CHANNEL_CCK)
ee_mode = AR5K_EEPROM_MODE_11B;
else
ee_mode = AR5K_EEPROM_MODE_11G;
- obdb = 0;
- if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[0],
- ee->ee_ob[ee_mode][obdb], 3, 119, 0, true))
- return -EINVAL;
+ /* For RF511X/RF211X combination we
+ * use b_OB and b_DB parameters stored
+ * in eeprom on ee->ee_ob[ee_mode][0]
+ *
+ * For all other chips we use OB/DB for 2Ghz
+ * stored in the b/g modal section just like
+ * 802.11a on ee->ee_ob[ee_mode][1] */
+ if ((ah->ah_radio == AR5K_RF5111) ||
+ (ah->ah_radio == AR5K_RF5112))
+ obdb = 0;
+ else
+ obdb = 1;
- if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[0],
- ee->ee_ob[ee_mode][obdb], 3, 122, 0, true))
- return -EINVAL;
+ ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
+ AR5K_RF_OB_2GHZ, true);
- obdb = 1;
- /* Modify bank 6 */
- } else {
- /* For 11a, Turbo and XR */
+ ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
+ AR5K_RF_DB_2GHZ, true);
+
+ /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */
+ } else if ((channel->hw_value & CHANNEL_5GHZ) ||
+ (ah->ah_radio == AR5K_RF5111)) {
+
+ /* For 11a, Turbo and XR we need to choose
+ * OB/DB based on frequency range */
ee_mode = AR5K_EEPROM_MODE_11A;
obdb = channel->center_freq >= 5725 ? 3 :
(channel->center_freq >= 5500 ? 2 :
(channel->center_freq >= 5260 ? 1 :
(channel->center_freq > 4000 ? 0 : -1)));
- if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
- ee->ee_pwd_84, 1, 51, 3, true))
+ if (obdb < 0)
return -EINVAL;
- if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
- ee->ee_pwd_90, 1, 45, 3, true))
- return -EINVAL;
- }
+ ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
+ AR5K_RF_OB_5GHZ, true);
- if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
- !ee->ee_xpd[ee_mode], 1, 95, 0, true))
- return -EINVAL;
+ ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
+ AR5K_RF_DB_5GHZ, true);
+ }
- if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
- ee->ee_x_gain[ee_mode], 4, 96, 0, true))
- return -EINVAL;
+ g_step = &go->go_step[ah->ah_gain.g_step_idx];
- if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6], obdb >= 0 ?
- ee->ee_ob[ee_mode][obdb] : 0, 3, 104, 0, true))
- return -EINVAL;
+ /* Bank Modifications (chip-specific) */
+ if (ah->ah_radio == AR5K_RF5111) {
- if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6], obdb >= 0 ?
- ee->ee_db[ee_mode][obdb] : 0, 3, 107, 0, true))
- return -EINVAL;
+ /* Set gain_F settings according to current step */
+ if (channel->hw_value & CHANNEL_OFDM) {
- /* Modify bank 7 */
- if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[7],
- ee->ee_i_gain[ee_mode], 6, 29, 0, true))
- return -EINVAL;
+ AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL,
+ AR5K_PHY_FRAME_CTL_TX_CLIP,
+ g_step->gos_param[0]);
- if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[7],
- ee->ee_xpd[ee_mode], 1, 4, 0, true))
- return -EINVAL;
+ ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
+ AR5K_RF_PWD_90, true);
- /* Write RF values */
- for (i = 0; i < rf_size; i++) {
- AR5K_REG_WAIT(i);
- ath5k_hw_reg_write(ah, rf[i], rfb_5111[i].rfb_ctrl_register);
- }
+ ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
+ AR5K_RF_PWD_84, true);
- ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
+ ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
+ AR5K_RF_RFGAIN_SEL, true);
- return 0;
-}
+ /* We programmed gain_F parameters, switch back
+ * to active state */
+ ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
-/*
- * Read EEPROM Calibration data, modify RF Banks and Initialize RF5112
- */
-static int ath5k_hw_rf5112_rfregs(struct ath5k_hw *ah,
- struct ieee80211_channel *channel, unsigned int mode)
-{
- const struct ath5k_ini_rfbuffer *rf_ini;
- struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
- u32 *rf;
- unsigned int rf_size, i;
- int obdb = -1, bank = -1;
- u32 ee_mode;
+ }
- AR5K_ASSERT_ENTRY(mode, AR5K_MODE_MAX);
+ /* Bank 6/7 setup */
- rf = ah->ah_rf_banks;
+ ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode],
+ AR5K_RF_PWD_XPD, true);
- if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
- rf_ini = rfb_5112a;
- rf_size = ARRAY_SIZE(rfb_5112a);
- } else {
- rf_ini = rfb_5112;
- rf_size = ARRAY_SIZE(rfb_5112);
- }
+ ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode],
+ AR5K_RF_XPD_GAIN, true);
- /* Copy values to modify them */
- for (i = 0; i < rf_size; i++) {
- if (rf_ini[i].rfb_bank >= AR5K_RF5112_INI_RF_MAX_BANKS) {
- ATH5K_ERR(ah->ah_sc, "invalid bank\n");
- return -EINVAL;
- }
+ ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
+ AR5K_RF_GAIN_I, true);
- if (bank != rf_ini[i].rfb_bank) {
- bank = rf_ini[i].rfb_bank;
- ah->ah_offset[bank] = i;
- }
+ ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
+ AR5K_RF_PLO_SEL, true);
- rf[i] = rf_ini[i].rfb_mode_data[mode];
+ /* TODO: Half/quarter channel support */
}
- /* Modify bank 6 */
- if (channel->hw_value & CHANNEL_2GHZ) {
- if (channel->hw_value & CHANNEL_OFDM)
- ee_mode = AR5K_EEPROM_MODE_11G;
- else
- ee_mode = AR5K_EEPROM_MODE_11B;
- obdb = 0;
+ if (ah->ah_radio == AR5K_RF5112) {
- if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
- ee->ee_ob[ee_mode][obdb], 3, 287, 0, true))
- return -EINVAL;
+ /* Set gain_F settings according to current step */
+ if (channel->hw_value & CHANNEL_OFDM) {
- if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
- ee->ee_ob[ee_mode][obdb], 3, 290, 0, true))
- return -EINVAL;
- } else {
- /* For 11a, Turbo and XR */
- ee_mode = AR5K_EEPROM_MODE_11A;
- obdb = channel->center_freq >= 5725 ? 3 :
- (channel->center_freq >= 5500 ? 2 :
- (channel->center_freq >= 5260 ? 1 :
- (channel->center_freq > 4000 ? 0 : -1)));
+ ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0],
+ AR5K_RF_MIXGAIN_OVR, true);
- if (obdb == -1)
- return -EINVAL;
+ ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
+ AR5K_RF_PWD_138, true);
- if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
- ee->ee_ob[ee_mode][obdb], 3, 279, 0, true))
- return -EINVAL;
+ ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
+ AR5K_RF_PWD_137, true);
- if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
- ee->ee_ob[ee_mode][obdb], 3, 282, 0, true))
- return -EINVAL;
- }
+ ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
+ AR5K_RF_PWD_136, true);
- ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
- ee->ee_x_gain[ee_mode], 2, 270, 0, true);
- ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
- ee->ee_x_gain[ee_mode], 2, 257, 0, true);
+ ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4],
+ AR5K_RF_PWD_132, true);
- if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
- ee->ee_xpd[ee_mode], 1, 302, 0, true))
- return -EINVAL;
+ ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5],
+ AR5K_RF_PWD_131, true);
- /* Modify bank 7 */
- if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[7],
- ee->ee_i_gain[ee_mode], 6, 14, 0, true))
- return -EINVAL;
+ ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6],
+ AR5K_RF_PWD_130, true);
- /* Write RF values */
- for (i = 0; i < rf_size; i++)
- ath5k_hw_reg_write(ah, rf[i], rf_ini[i].rfb_ctrl_register);
+ /* We programmed gain_F parameters, switch back
+ * to active state */
+ ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
+ }
+ /* Bank 6/7 setup */
- ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
+ ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
+ AR5K_RF_XPD_SEL, true);
- return 0;
-}
+ if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) {
+ /* Rev. 1 supports only one xpd */
+ ath5k_hw_rfb_op(ah, rf_regs,
+ ee->ee_x_gain[ee_mode],
+ AR5K_RF_XPD_GAIN, true);
-/*
- * Initialize RF5413/5414 and future chips
- * (until we come up with a better solution)
- */
-static int ath5k_hw_rf5413_rfregs(struct ath5k_hw *ah,
- struct ieee80211_channel *channel, unsigned int mode)
-{
- const struct ath5k_ini_rfbuffer *rf_ini;
- u32 *rf;
- unsigned int rf_size, i;
- int bank = -1;
+ } else {
+ /* TODO: Set high and low gain bits */
+ ath5k_hw_rfb_op(ah, rf_regs,
+ ee->ee_x_gain[ee_mode],
+ AR5K_RF_PD_GAIN_LO, true);
+ ath5k_hw_rfb_op(ah, rf_regs,
+ ee->ee_x_gain[ee_mode],
+ AR5K_RF_PD_GAIN_HI, true);
- AR5K_ASSERT_ENTRY(mode, AR5K_MODE_MAX);
+ /* Lower synth voltage on Rev 2 */
+ ath5k_hw_rfb_op(ah, rf_regs, 2,
+ AR5K_RF_HIGH_VC_CP, true);
- rf = ah->ah_rf_banks;
+ ath5k_hw_rfb_op(ah, rf_regs, 2,
+ AR5K_RF_MID_VC_CP, true);
- switch (ah->ah_radio) {
- case AR5K_RF5413:
- rf_ini = rfb_5413;
- rf_size = ARRAY_SIZE(rfb_5413);
- break;
- case AR5K_RF2413:
- rf_ini = rfb_2413;
- rf_size = ARRAY_SIZE(rfb_2413);
+ ath5k_hw_rfb_op(ah, rf_regs, 2,
+ AR5K_RF_LOW_VC_CP, true);
- if (mode < 2) {
- ATH5K_ERR(ah->ah_sc,
- "invalid channel mode: %i\n", mode);
- return -EINVAL;
- }
+ ath5k_hw_rfb_op(ah, rf_regs, 2,
+ AR5K_RF_PUSH_UP, true);
- break;
- case AR5K_RF2425:
- rf_ini = rfb_2425;
- rf_size = ARRAY_SIZE(rfb_2425);
+ /* Decrease power consumption on 5213+ BaseBand */
+ if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
+ ath5k_hw_rfb_op(ah, rf_regs, 1,
+ AR5K_RF_PAD2GND, true);
- if (mode < 2) {
- ATH5K_ERR(ah->ah_sc,
- "invalid channel mode: %i\n", mode);
- return -EINVAL;
- }
+ ath5k_hw_rfb_op(ah, rf_regs, 1,
+ AR5K_RF_XB2_LVL, true);
- break;
- default:
- return -EINVAL;
- }
+ ath5k_hw_rfb_op(ah, rf_regs, 1,
+ AR5K_RF_XB5_LVL, true);
- /* Copy values to modify them */
- for (i = 0; i < rf_size; i++) {
- if (rf_ini[i].rfb_bank >= AR5K_RF5112_INI_RF_MAX_BANKS) {
- ATH5K_ERR(ah->ah_sc, "invalid bank\n");
- return -EINVAL;
- }
+ ath5k_hw_rfb_op(ah, rf_regs, 1,
+ AR5K_RF_PWD_167, true);
- if (bank != rf_ini[i].rfb_bank) {
- bank = rf_ini[i].rfb_bank;
- ah->ah_offset[bank] = i;
+ ath5k_hw_rfb_op(ah, rf_regs, 1,
+ AR5K_RF_PWD_166, true);
+ }
}
- rf[i] = rf_ini[i].rfb_mode_data[mode];
- }
+ ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
+ AR5K_RF_GAIN_I, true);
- /*
- * After compairing dumps from different cards
- * we get the same RF_BUFFER settings (diff returns
- * 0 lines). It seems that RF_BUFFER settings are static
- * and are written unmodified (no EEPROM stuff
- * is used because calibration data would be
- * different between different cards and would result
- * different RF_BUFFER settings)
- */
+ /* TODO: Half/quarter channel support */
- /* Write RF values */
- for (i = 0; i < rf_size; i++)
- ath5k_hw_reg_write(ah, rf[i], rf_ini[i].rfb_ctrl_register);
+ }
- return 0;
-}
+ if (ah->ah_radio == AR5K_RF5413 &&
+ channel->hw_value & CHANNEL_2GHZ) {
-/*
- * Initialize RF
- */
-int ath5k_hw_rfregs(struct ath5k_hw *ah, struct ieee80211_channel *channel,
- unsigned int mode)
-{
- int (*func)(struct ath5k_hw *, struct ieee80211_channel *, unsigned int);
- int ret;
+ ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE,
+ true);
- switch (ah->ah_radio) {
- case AR5K_RF5111:
- ah->ah_rf_banks_size = sizeof(rfb_5111);
- func = ath5k_hw_rf5111_rfregs;
- break;
- case AR5K_RF5112:
- if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)
- ah->ah_rf_banks_size = sizeof(rfb_5112a);
- else
- ah->ah_rf_banks_size = sizeof(rfb_5112);
- func = ath5k_hw_rf5112_rfregs;
- break;
- case AR5K_RF5413:
- ah->ah_rf_banks_size = sizeof(rfb_5413);
- func = ath5k_hw_rf5413_rfregs;
- break;
- case AR5K_RF2413:
- ah->ah_rf_banks_size = sizeof(rfb_2413);
- func = ath5k_hw_rf5413_rfregs;
- break;
- case AR5K_RF2425:
- ah->ah_rf_banks_size = sizeof(rfb_2425);
- func = ath5k_hw_rf5413_rfregs;
- break;
- default:
- return -EINVAL;
- }
+ /* Set optimum value for early revisions (on pci-e chips) */
+ if (ah->ah_mac_srev >= AR5K_SREV_AR5424 &&
+ ah->ah_mac_srev < AR5K_SREV_AR5413)
+ ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3),
+ AR5K_RF_PWD_ICLOBUF_2G, true);
- if (ah->ah_rf_banks == NULL) {
- /* XXX do extra checks? */
- ah->ah_rf_banks = kmalloc(ah->ah_rf_banks_size, GFP_KERNEL);
- if (ah->ah_rf_banks == NULL) {
- ATH5K_ERR(ah->ah_sc, "out of memory\n");
- return -ENOMEM;
- }
}
- ret = func(ah, channel, mode);
+ /* Write RF banks on hw */
+ for (i = 0; i < ah->ah_rf_banks_size; i++) {
+ AR5K_REG_WAIT(i);
+ ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register);
+ }
- return ret;
+ return 0;
}
-
-
/**************************\
PHY/RF channel functions
\**************************/
--
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