From 6dfaa76994e5d49a82afb415bbe1362e901b2b95 Mon Sep 17 00:00:00 2001 From: Bruce Allan Date: Wed, 5 May 2010 22:00:06 +0000 Subject: e1000e: reset MAC-PHY interconnect on 82577/82578 during Sx->S0 During Sx->S0 transitions, the interconnect between the MAC and PHY on 82577/82578 can remain in SMBus mode instead of transitioning to the PCIe-like mode required during normal operation. Toggling the LANPHYPC Value bit essentially resets the interconnect forcing it to the correct mode. Signed-off-by: Bruce Allan Signed-off-by: Jeff Kirsher Signed-off-by: David S. Miller --- drivers/net/e1000e/defines.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/net/e1000e/defines.h') diff --git a/drivers/net/e1000e/defines.h b/drivers/net/e1000e/defines.h index e301e26..7f760aa 100644 --- a/drivers/net/e1000e/defines.h +++ b/drivers/net/e1000e/defines.h @@ -214,6 +214,8 @@ #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ +#define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */ +#define E1000_CTRL_LANPHYPC_VALUE 0x00020000 /* SW value of LANPHYPC */ #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ -- cgit v1.1