From 69f5bf38f93c78faeb93d51dc41adf51e13fe78d Mon Sep 17 00:00:00 2001 From: Aisheng Dong Date: Fri, 9 May 2014 14:53:15 +0800 Subject: mmc: sdhci-esdhc-imx: fix mmc ddr mode regression issue It's caused by the platform driver was still using MMC_TIMING_UHS_DDR50 for MMC DDR mode which needs update too. Reported-by: Fabio Estevam Reported-by: Shawn Guo Signed-off-by: Dong Aisheng Tested-by: Fabio Estevam [Ulf Hansson] Resolved conflict Signed-off-by: Ulf Hansson Signed-off-by: Chris Ball --- drivers/mmc/host/sdhci-esdhc-imx.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/mmc') diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index 4866d80..ccec0e3 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -852,6 +852,7 @@ static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) case MMC_TIMING_MMC_HS200: break; case MMC_TIMING_UHS_DDR50: + case MMC_TIMING_MMC_DDR52: writel(readl(host->ioaddr + ESDHC_MIX_CTRL) | ESDHC_MIX_CTRL_DDREN, host->ioaddr + ESDHC_MIX_CTRL); -- cgit v1.1