From 8ba9580a8045b6d5fed66e13b77599f3d8a77fed Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Wed, 5 Jun 2013 15:13:25 +0200 Subject: mmc: sdhci-esdhc: calculate sdclk divider from controller clock The SDCLK is divided down from the host controller clock. Host controller clock may be different from the maximum SDCLK, so get it from the platform, instead of just using the max SDCLK. Signed-off-by: Lucas Stach Acked-by: Shawn Guo Signed-off-by: Chris Ball --- drivers/mmc/host/sdhci-esdhc.h | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'drivers/mmc/host/sdhci-esdhc.h') diff --git a/drivers/mmc/host/sdhci-esdhc.h b/drivers/mmc/host/sdhci-esdhc.h index d25f9ab..6f16406 100644 --- a/drivers/mmc/host/sdhci-esdhc.h +++ b/drivers/mmc/host/sdhci-esdhc.h @@ -42,7 +42,8 @@ #define ESDHC_HOST_CONTROL_RES 0x05 -static inline void esdhc_set_clock(struct sdhci_host *host, unsigned int clock) +static inline void esdhc_set_clock(struct sdhci_host *host, unsigned int clock, + unsigned int host_clock) { int pre_div = 2; int div = 1; @@ -56,14 +57,14 @@ static inline void esdhc_set_clock(struct sdhci_host *host, unsigned int clock) | ESDHC_CLOCK_MASK); sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); - while (host->max_clk / pre_div / 16 > clock && pre_div < 256) + while (host_clock / pre_div / 16 > clock && pre_div < 256) pre_div *= 2; - while (host->max_clk / pre_div / div > clock && div < 16) + while (host_clock / pre_div / div > clock && div < 16) div++; dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", - clock, host->max_clk / pre_div / div); + clock, host_clock / pre_div / div); pre_div >>= 1; div--; -- cgit v1.1