From a3ef0deb0fa45781ab653d7c9271e02c152076f1 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 7 May 2013 12:01:32 +0100 Subject: mfd: db8500-prcmu: Supply the pdata_size attribute for db8500-thermal The MFD subsystem requires drivers to state the size of any platform data passed, or it will fail to assign it to the device. This will culminate in a NULL platform_data attribute and normally a failure to probe() or a kernel Oops. Acked-by: Linus Walleij Signed-off-by: Lee Jones Signed-off-by: Samuel Ortiz --- drivers/mfd/db8500-prcmu.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/mfd/db8500-prcmu.c') diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c index 319b8ab..5389368 100644 --- a/drivers/mfd/db8500-prcmu.c +++ b/drivers/mfd/db8500-prcmu.c @@ -3095,6 +3095,7 @@ static struct mfd_cell db8500_prcmu_devs[] = { .num_resources = ARRAY_SIZE(db8500_thsens_resources), .resources = db8500_thsens_resources, .platform_data = &db8500_thsens_data, + .pdata_size = sizeof(db8500_thsens_data), }, }; -- cgit v1.1 From e9d7b4b5691cac4dce6c5eed9e217e50e24edef7 Mon Sep 17 00:00:00 2001 From: Ulf Hansson Date: Tue, 14 May 2013 15:14:55 +0200 Subject: mfd: db8500-prcmu: Update stored DSI PLL divider value Previously the DSI PLL divider rate was initialised statically and assumed to be 1. Before the common clock framework was enabled for ux500, a call to clk_set_rate() would always update the HW registers no matter what the current setting was. This patch makes sure the actual hw settings and the sw assumed settings are matched. Signed-off-by: Paer-Olof Haakansson Signed-off-by: Ulf Hansson signed-off-by: Lee Jones Signed-off-by: Samuel Ortiz --- drivers/mfd/db8500-prcmu.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/mfd/db8500-prcmu.c') diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c index 5389368..66f8097 100644 --- a/drivers/mfd/db8500-prcmu.c +++ b/drivers/mfd/db8500-prcmu.c @@ -1613,6 +1613,8 @@ static unsigned long dsiclk_rate(u8 n) if (divsel == PRCM_DSI_PLLOUT_SEL_OFF) divsel = dsiclk[n].divsel; + else + dsiclk[n].divsel = divsel; switch (divsel) { case PRCM_DSI_PLLOUT_SEL_PHI_4: -- cgit v1.1