From dc4aedbf7c152c092c19e980a9fa1e89d6bc215f Mon Sep 17 00:00:00 2001 From: Koji Matsuoka Date: Fri, 11 Nov 2016 18:07:41 +0100 Subject: drm: rcar-du: Add DPLL support The implementation hardcodes a workaround for the H3 ES1.x SoC regardless of the SoC revision, as the workaround can be safely applied on all devices in the Gen3 family without any side effect. Signed-off-by: Koji Matsuoka Signed-off-by: Ulrich Hecht Signed-off-by: Laurent Pinchart --- drivers/gpu/drm/rcar-du/rcar_du_drv.h | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/drm/rcar-du/rcar_du_drv.h') diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.h b/drivers/gpu/drm/rcar-du/rcar_du_drv.h index 90eb209..f8cd794 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.h +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.h @@ -65,6 +65,7 @@ struct rcar_du_device_info { unsigned int num_crtcs; struct rcar_du_output_routing routes[RCAR_DU_OUTPUT_MAX]; unsigned int num_lvds; + unsigned int dpll_ch; }; #define RCAR_DU_MAX_CRTCS 4 -- cgit v1.1