From bdcb2f91069337b3d577d69c15dbd1f5b8f683e8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Fri, 18 Nov 2016 21:52:46 +0200 Subject: drm/nouveau: Fix crtc->primary->fb vs. drm_fb fail MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit So it looks like the code is trying to pick between the passed in fb and crtc->primary->fb based on that funky 'bool atomic'. But later it will mix uses of both drm_fb (which was picked by the aforementioned logic) and crtc->primary->fb. So looks like a bug to me. Let's make it use drm_fb only. Cc: Ben Skeggs Signed-off-by: Ville Syrjälä Link: http://patchwork.freedesktop.org/patch/msgid/1479498793-31021-11-git-send-email-ville.syrjala@linux.intel.com Reviewed-by: Daniel Vetter --- drivers/gpu/drm/nouveau/dispnv04/crtc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/dispnv04/crtc.c b/drivers/gpu/drm/nouveau/dispnv04/crtc.c index 59d1d1c..7c6c66f 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/crtc.c +++ b/drivers/gpu/drm/nouveau/dispnv04/crtc.c @@ -854,9 +854,9 @@ nv04_crtc_do_mode_set_base(struct drm_crtc *crtc, /* Update the framebuffer format. */ regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] &= ~3; - regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (crtc->primary->fb->depth + 1) / 8; + regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (drm_fb->depth + 1) / 8; regp->ramdac_gen_ctrl &= ~NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; - if (crtc->primary->fb->depth == 16) + if (drm_fb->depth == 16) regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_PIXEL_INDEX); NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_GENERAL_CONTROL, -- cgit v1.1 From d92df868a56cac7804967f67a038a90a90591fed Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Fri, 18 Nov 2016 21:52:47 +0200 Subject: drm/nouveau: Add local 'fb' variables MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a local 'fb' variable to a few places to get rid of the 'crtc->primary->fb' stuff. Looks neater and helps me with my poor coccinelle skills later. Cc: Ben Skeggs Signed-off-by: Ville Syrjälä Link: http://patchwork.freedesktop.org/patch/msgid/1479498793-31021-12-git-send-email-ville.syrjala@linux.intel.com Reviewed-by: Daniel Vetter --- drivers/gpu/drm/nouveau/dispnv04/crtc.c | 5 +++-- drivers/gpu/drm/nouveau/dispnv04/dfp.c | 3 ++- 2 files changed, 5 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/dispnv04/crtc.c b/drivers/gpu/drm/nouveau/dispnv04/crtc.c index 7c6c66f..8286b8f 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/crtc.c +++ b/drivers/gpu/drm/nouveau/dispnv04/crtc.c @@ -460,6 +460,7 @@ nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode) struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index]; + const struct drm_framebuffer *fb = crtc->primary->fb; struct drm_encoder *encoder; bool lvds_output = false, tmds_output = false, tv_output = false, off_chip_digital = false; @@ -569,7 +570,7 @@ nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode) regp->CRTC[NV_CIO_CRE_86] = 0x1; } - regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (crtc->primary->fb->depth + 1) / 8; + regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (fb->depth + 1) / 8; /* Enable slaved mode (called MODE_TV in nv4ref.h) */ if (lvds_output || tmds_output || tv_output) regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (1 << 7); @@ -583,7 +584,7 @@ nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode) regp->ramdac_gen_ctrl = NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS | NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL | NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON; - if (crtc->primary->fb->depth == 16) + if (fb->depth == 16) regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; if (drm->device.info.chipset >= 0x11) regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG; diff --git a/drivers/gpu/drm/nouveau/dispnv04/dfp.c b/drivers/gpu/drm/nouveau/dispnv04/dfp.c index c2947ef..945607b 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/dfp.c +++ b/drivers/gpu/drm/nouveau/dispnv04/dfp.c @@ -290,6 +290,7 @@ static void nv04_dfp_mode_set(struct drm_encoder *encoder, struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); struct drm_display_mode *output_mode = &nv_encoder->mode; struct drm_connector *connector = &nv_connector->base; + const struct drm_framebuffer *fb = encoder->crtc->primary->fb; uint32_t mode_ratio, panel_ratio; NV_DEBUG(drm, "Output mode on CRTC %d:\n", nv_crtc->index); @@ -415,7 +416,7 @@ static void nv04_dfp_mode_set(struct drm_encoder *encoder, /* Output property. */ if ((nv_connector->dithering_mode == DITHERING_MODE_ON) || (nv_connector->dithering_mode == DITHERING_MODE_AUTO && - encoder->crtc->primary->fb->depth > connector->display_info.bpc * 3)) { + fb->depth > connector->display_info.bpc * 3)) { if (drm->device.info.chipset == 0x11) regp->dither = savep->dither | 0x00010000; else { -- cgit v1.1 From a3f913ca98925d7e5bae725e9b2b38408215a695 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Wed, 14 Dec 2016 22:48:59 +0200 Subject: drm: Pass 'dev' to drm_helper_mode_fill_fb_struct() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Pass the drm_device to drm_helper_mode_fill_fb_struct() so that we can populate fb->dev early. Will make it easier to use the fb before we register it. @@ identifier fb, mode_cmd; @@ void drm_helper_mode_fill_fb_struct( + struct drm_device *dev, struct drm_framebuffer *fb, const struct drm_mode_fb_cmd2 *mode_cmd ); @@ identifier fb, mode_cmd; @@ void drm_helper_mode_fill_fb_struct( + struct drm_device *dev, struct drm_framebuffer *fb, const struct drm_mode_fb_cmd2 *mode_cmd ) { ... } @@ function func; identifier dev; expression E1, E2; @@ func(struct drm_device *dev, ...) { ... drm_helper_mode_fill_fb_struct( + dev, E1, E2); ... } @@ expression E1, E2; @@ drm_helper_mode_fill_fb_struct( + dev, E1, E2); v2: Rerun spatch due to code changes Signed-off-by: Ville Syrjälä Reviewed-by: Laurent Pinchart Reviewed-by: Alex Deucher Link: http://patchwork.freedesktop.org/patch/msgid/1481748539-18283-1-git-send-email-ville.syrjala@linux.intel.com --- drivers/gpu/drm/nouveau/nouveau_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c index cef08da..e0db5d3 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.c +++ b/drivers/gpu/drm/nouveau/nouveau_display.c @@ -259,7 +259,7 @@ nouveau_framebuffer_new(struct drm_device *dev, if (!(fb = *pfb = kzalloc(sizeof(*fb), GFP_KERNEL))) return -ENOMEM; - drm_helper_mode_fill_fb_struct(&fb->base, mode_cmd); + drm_helper_mode_fill_fb_struct(dev, &fb->base, mode_cmd); fb->nvbo = nvbo; ret = drm_framebuffer_init(dev, &fb->base, &nouveau_framebuffer_funcs); -- cgit v1.1 From 9857ecbe516954fb563f15f5353937796c8cfb53 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Fri, 18 Nov 2016 21:53:03 +0200 Subject: drm/nouveau: Use fb->format rather than drm_format_info() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Let's use the pointer to the format information cached under drm_framebuffer rather than look it up manually. Cc: Ben Skeggs Signed-off-by: Ville Syrjälä Link: http://patchwork.freedesktop.org/patch/msgid/1479498793-31021-28-git-send-email-ville.syrjala@linux.intel.com Reviewed-by: Daniel Vetter --- drivers/gpu/drm/nouveau/nv50_display.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c index 2c2c645..b617e5d 100644 --- a/drivers/gpu/drm/nouveau/nv50_display.c +++ b/drivers/gpu/drm/nouveau/nv50_display.c @@ -1418,12 +1418,10 @@ static int nv50_base_acquire(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw, struct nv50_head_atom *asyh) { - const u32 format = asyw->state.fb->pixel_format; - const struct drm_format_info *info; + const struct drm_framebuffer *fb = asyw->state.fb; int ret; - info = drm_format_info(format); - if (!info || !info->depth) + if (!fb->format->depth) return -EINVAL; ret = drm_plane_helper_check_state(&asyw->state, &asyw->clip, @@ -1433,14 +1431,14 @@ nv50_base_acquire(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw, if (ret) return ret; - asyh->base.depth = info->depth; - asyh->base.cpp = info->cpp[0]; + asyh->base.depth = fb->format->depth; + asyh->base.cpp = fb->format->cpp[0]; asyh->base.x = asyw->state.src.x1 >> 16; asyh->base.y = asyw->state.src.y1 >> 16; asyh->base.w = asyw->state.fb->width; asyh->base.h = asyw->state.fb->height; - switch (format) { + switch (fb->pixel_format) { case DRM_FORMAT_C8 : asyw->image.format = 0x1e; break; case DRM_FORMAT_RGB565 : asyw->image.format = 0xe8; break; case DRM_FORMAT_XRGB1555 : -- cgit v1.1 From b00c600e91531df00aaa551049382416c4db745d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Wed, 14 Dec 2016 23:31:35 +0200 Subject: drm: Nuke fb->depth MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replace uses of fb->depth with fb->format->depth. Less duplicate information is a good thing. @@ struct drm_framebuffer *fb; expression E; @@ drm_helper_mode_fill_fb_struct(...) { ... - fb->depth = E; ... } @@ struct nouveau_framebuffer *fb; @@ - fb->base.depth + fb->base.format->depth @@ struct drm_framebuffer fb; @@ - fb.depth + fb.format->depth @@ struct drm_framebuffer *fb; @@ - fb->depth + fb->format->depth @@ struct drm_framebuffer fb; @@ - (fb.format->depth) + fb.format->depth @@ struct drm_framebuffer *fb; @@ - (fb->format->depth) + fb->format->depth @@ @@ struct drm_framebuffer { ... - unsigned int depth; ... }; v2: Drop the vmw stuff (Daniel) Rerun spatch due to code changes Signed-off-by: Ville Syrjälä Reviewed-by: Laurent Pinchart Reviewed-by: Alex Deucher Reviewed-by: Daniel Vetter Link: http://patchwork.freedesktop.org/patch/msgid/1481751095-18249-1-git-send-email-ville.syrjala@linux.intel.com --- drivers/gpu/drm/nouveau/dispnv04/crtc.c | 12 ++++++------ drivers/gpu/drm/nouveau/dispnv04/dfp.c | 2 +- drivers/gpu/drm/nouveau/nouveau_fbcon.c | 3 ++- 3 files changed, 9 insertions(+), 8 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/dispnv04/crtc.c b/drivers/gpu/drm/nouveau/dispnv04/crtc.c index 8286b8f..480e3ab 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/crtc.c +++ b/drivers/gpu/drm/nouveau/dispnv04/crtc.c @@ -570,7 +570,7 @@ nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode) regp->CRTC[NV_CIO_CRE_86] = 0x1; } - regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (fb->depth + 1) / 8; + regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (fb->format->depth + 1) / 8; /* Enable slaved mode (called MODE_TV in nv4ref.h) */ if (lvds_output || tmds_output || tv_output) regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (1 << 7); @@ -584,7 +584,7 @@ nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode) regp->ramdac_gen_ctrl = NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS | NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL | NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON; - if (fb->depth == 16) + if (fb->format->depth == 16) regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; if (drm->device.info.chipset >= 0x11) regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG; @@ -848,16 +848,16 @@ nv04_crtc_do_mode_set_base(struct drm_crtc *crtc, nv_crtc->fb.offset = fb->nvbo->bo.offset; - if (nv_crtc->lut.depth != drm_fb->depth) { - nv_crtc->lut.depth = drm_fb->depth; + if (nv_crtc->lut.depth != drm_fb->format->depth) { + nv_crtc->lut.depth = drm_fb->format->depth; nv_crtc_gamma_load(crtc); } /* Update the framebuffer format. */ regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] &= ~3; - regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (drm_fb->depth + 1) / 8; + regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (drm_fb->format->depth + 1) / 8; regp->ramdac_gen_ctrl &= ~NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; - if (drm_fb->depth == 16) + if (drm_fb->format->depth == 16) regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_PIXEL_INDEX); NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_GENERAL_CONTROL, diff --git a/drivers/gpu/drm/nouveau/dispnv04/dfp.c b/drivers/gpu/drm/nouveau/dispnv04/dfp.c index 945607b..2e5bb2a 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/dfp.c +++ b/drivers/gpu/drm/nouveau/dispnv04/dfp.c @@ -416,7 +416,7 @@ static void nv04_dfp_mode_set(struct drm_encoder *encoder, /* Output property. */ if ((nv_connector->dithering_mode == DITHERING_MODE_ON) || (nv_connector->dithering_mode == DITHERING_MODE_AUTO && - fb->depth > connector->display_info.bpc * 3)) { + fb->format->depth > connector->display_info.bpc * 3)) { if (drm->device.info.chipset == 0x11) regp->dither = savep->dither | 0x00010000; else { diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c index 2f2a3dc..5600f6c 100644 --- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c +++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c @@ -400,7 +400,8 @@ nouveau_fbcon_create(struct drm_fb_helper *helper, info->screen_base = nvbo_kmap_obj_iovirtual(fb->nvbo); info->screen_size = fb->nvbo->bo.mem.num_pages << PAGE_SHIFT; - drm_fb_helper_fill_fix(info, fb->base.pitches[0], fb->base.depth); + drm_fb_helper_fill_fix(info, fb->base.pitches[0], + fb->base.format->depth); drm_fb_helper_fill_var(info, &fbcon->helper, sizes->fb_width, sizes->fb_height); /* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */ -- cgit v1.1 From 272725c7db4da1fd3229d944fc76d2e98e3a144e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Wed, 14 Dec 2016 23:32:20 +0200 Subject: drm: Nuke fb->bits_per_pixel MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replace uses of fb->bits_per_pixel with fb->format->cpp[0]*8. Less duplicated information is a good thing. Note that I didn't put parens around the cpp*8 in the below cocci script, on account of not wanting spurious parens all over the place. Instead I did the unsafe way, and tried to look over the entire diff to spot if any dangerous expressions were produced. I didn't see any. There are some cases where previously the code did X*bpp/8, so the division happened after the multiplication. Those are now just X*cpp so the division effectively happens before the multiplication, but that is perfectly fine since bpp is always a multiple of 8. @@ struct drm_framebuffer *FB; expression E; @@ drm_helper_mode_fill_fb_struct(...) { ... - FB->bits_per_pixel = E; ... } @@ struct drm_framebuffer *FB; expression E; @@ i9xx_get_initial_plane_config(...) { ... - FB->bits_per_pixel = E; ... } @@ struct drm_framebuffer *FB; expression E; @@ ironlake_get_initial_plane_config(...) { ... - FB->bits_per_pixel = E; ... } @@ struct drm_framebuffer *FB; expression E; @@ skylake_get_initial_plane_config(...) { ... - FB->bits_per_pixel = E; ... } @@ struct drm_framebuffer FB; expression E; @@ ( - E * FB.bits_per_pixel / 8 + E * FB.format->cpp[0] | - FB.bits_per_pixel / 8 + FB.format->cpp[0] | - E * FB.bits_per_pixel >> 3 + E * FB.format->cpp[0] | - FB.bits_per_pixel >> 3 + FB.format->cpp[0] | - (FB.bits_per_pixel + 7) / 8 + FB.format->cpp[0] | - FB.bits_per_pixel + FB.format->cpp[0] * 8 | - FB.format->cpp[0] * 8 != 8 + FB.format->cpp[0] != 1 ) @@ struct drm_framebuffer *FB; expression E; @@ ( - E * FB->bits_per_pixel / 8 + E * FB->format->cpp[0] | - FB->bits_per_pixel / 8 + FB->format->cpp[0] | - E * FB->bits_per_pixel >> 3 + E * FB->format->cpp[0] | - FB->bits_per_pixel >> 3 + FB->format->cpp[0] | - (FB->bits_per_pixel + 7) / 8 + FB->format->cpp[0] | - FB->bits_per_pixel + FB->format->cpp[0] * 8 | - FB->format->cpp[0] * 8 != 8 + FB->format->cpp[0] != 1 ) @@ struct drm_plane_state *state; expression E; @@ ( - E * state->fb->bits_per_pixel / 8 + E * state->fb->format->cpp[0] | - state->fb->bits_per_pixel / 8 + state->fb->format->cpp[0] | - E * state->fb->bits_per_pixel >> 3 + E * state->fb->format->cpp[0] | - state->fb->bits_per_pixel >> 3 + state->fb->format->cpp[0] | - (state->fb->bits_per_pixel + 7) / 8 + state->fb->format->cpp[0] | - state->fb->bits_per_pixel + state->fb->format->cpp[0] * 8 | - state->fb->format->cpp[0] * 8 != 8 + state->fb->format->cpp[0] != 1 ) @@ @@ - (8 * 8) + 8 * 8 @@ struct drm_framebuffer FB; @@ - (FB.format->cpp[0]) + FB.format->cpp[0] @@ struct drm_framebuffer *FB; @@ - (FB->format->cpp[0]) + FB->format->cpp[0] @@ @@ struct drm_framebuffer { ... - int bits_per_pixel; ... }; v2: Clean up the 'cpp*8 != 8' and '(8 * 8)' cases (Laurent) v3: Adjusted the semantic patch a bit and regenerated due to code changes Signed-off-by: Ville Syrjälä Reviewed-by: Laurent Pinchart Reviewed-by: Alex Deucher (v1) Link: http://patchwork.freedesktop.org/patch/msgid/1481751140-18352-1-git-send-email-ville.syrjala@linux.intel.com --- drivers/gpu/drm/nouveau/dispnv04/crtc.c | 4 ++-- drivers/gpu/drm/nouveau/nouveau_display.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/dispnv04/crtc.c b/drivers/gpu/drm/nouveau/dispnv04/crtc.c index 480e3ab..a72754d 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/crtc.c +++ b/drivers/gpu/drm/nouveau/dispnv04/crtc.c @@ -874,11 +874,11 @@ nv04_crtc_do_mode_set_base(struct drm_crtc *crtc, /* Update the framebuffer location. */ regp->fb_start = nv_crtc->fb.offset & ~3; - regp->fb_start += (y * drm_fb->pitches[0]) + (x * drm_fb->bits_per_pixel / 8); + regp->fb_start += (y * drm_fb->pitches[0]) + (x * drm_fb->format->cpp[0]); nv_set_crtc_base(dev, nv_crtc->index, regp->fb_start); /* Update the arbitration parameters. */ - nouveau_calc_arb(dev, crtc->mode.clock, drm_fb->bits_per_pixel, + nouveau_calc_arb(dev, crtc->mode.clock, drm_fb->format->cpp[0] * 8, &arb_burst, &arb_lwm); regp->CRTC[NV_CIO_CRE_FF_INDEX] = arb_burst; diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c index e0db5d3..c5cf888 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.c +++ b/drivers/gpu/drm/nouveau/nouveau_display.c @@ -947,7 +947,7 @@ nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, /* Initialize a page flip struct */ *s = (struct nouveau_page_flip_state) - { { }, event, crtc, fb->bits_per_pixel, fb->pitches[0], + { { }, event, crtc, fb->format->cpp[0] * 8, fb->pitches[0], new_bo->bo.offset }; /* Keep vblanks on during flip, for the target crtc of this flip */ -- cgit v1.1 From 438b74a5497c36d6d59baded434002e30267cabe Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Wed, 14 Dec 2016 23:32:55 +0200 Subject: drm: Nuke fb->pixel_format MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replace uses of fb->pixel_format with fb->format->format. Less duplicated information is a good thing. Note that coccinelle failed to eliminate the "/* fourcc format */" comment from drm_framebuffer.h, so I had to do that part manually. @@ struct drm_framebuffer *FB; expression E; @@ drm_helper_mode_fill_fb_struct(...) { ... - FB->pixel_format = E; ... } @@ struct drm_framebuffer *FB; expression E; @@ i9xx_get_initial_plane_config(...) { ... - FB->pixel_format = E; ... } @@ struct drm_framebuffer *FB; expression E; @@ ironlake_get_initial_plane_config(...) { ... - FB->pixel_format = E; ... } @@ struct drm_framebuffer *FB; expression E; @@ skylake_get_initial_plane_config(...) { ... - FB->pixel_format = E; ... } @@ struct drm_framebuffer *a; struct drm_framebuffer b; @@ ( - a->pixel_format + a->format->format | - b.pixel_format + b.format->format ) @@ struct drm_plane_state *a; struct drm_plane_state b; @@ ( - a->fb->pixel_format + a->fb->format->format | - b.fb->pixel_format + b.fb->format->format ) @@ struct drm_crtc *CRTC; @@ ( - CRTC->primary->fb->pixel_format + CRTC->primary->fb->format->format | - CRTC->primary->state->fb->pixel_format + CRTC->primary->state->fb->format->format ) @@ struct drm_mode_set *set; @@ ( - set->fb->pixel_format + set->fb->format->format | - set->crtc->primary->fb->pixel_format + set->crtc->primary->fb->format->format ) @@ @@ struct drm_framebuffer { ... - uint32_t pixel_format; ... }; v2: Fix commit message (Laurent) Rebase due to earlier removal of many fb->pixel_format uses, including the 'fb->format = drm_format_info(fb->format->format);' snafu v3: Adjusted the semantic patch a bit and regenerated due to code changes Cc: Laurent Pinchart Signed-off-by: Ville Syrjälä Reviewed-by: Alex Deucher (v1) Reviewed-by: Laurent Pinchart Link: http://patchwork.freedesktop.org/patch/msgid/1481751175-18463-1-git-send-email-ville.syrjala@linux.intel.com --- drivers/gpu/drm/nouveau/dispnv04/overlay.c | 8 ++++---- drivers/gpu/drm/nouveau/nv50_display.c | 4 ++-- 2 files changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/dispnv04/overlay.c b/drivers/gpu/drm/nouveau/dispnv04/overlay.c index a79514d..6275c27 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/overlay.c +++ b/drivers/gpu/drm/nouveau/dispnv04/overlay.c @@ -145,16 +145,16 @@ nv10_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, nvif_wr32(dev, NV_PVIDEO_POINT_OUT(flip), crtc_y << 16 | crtc_x); nvif_wr32(dev, NV_PVIDEO_SIZE_OUT(flip), crtc_h << 16 | crtc_w); - if (fb->pixel_format != DRM_FORMAT_UYVY) + if (fb->format->format != DRM_FORMAT_UYVY) format |= NV_PVIDEO_FORMAT_COLOR_LE_CR8YB8CB8YA8; - if (fb->pixel_format == DRM_FORMAT_NV12) + if (fb->format->format == DRM_FORMAT_NV12) format |= NV_PVIDEO_FORMAT_PLANAR; if (nv_plane->iturbt_709) format |= NV_PVIDEO_FORMAT_MATRIX_ITURBT709; if (nv_plane->colorkey & (1 << 24)) format |= NV_PVIDEO_FORMAT_DISPLAY_COLOR_KEY; - if (fb->pixel_format == DRM_FORMAT_NV12) { + if (fb->format->format == DRM_FORMAT_NV12) { nvif_wr32(dev, NV_PVIDEO_UVPLANE_BASE(flip), 0); nvif_wr32(dev, NV_PVIDEO_UVPLANE_OFFSET_BUFF(flip), nv_fb->nvbo->bo.offset + fb->offsets[1]); @@ -411,7 +411,7 @@ nv04_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, if (nv_plane->colorkey & (1 << 24)) overlay |= 0x10; - if (fb->pixel_format == DRM_FORMAT_YUYV) + if (fb->format->format == DRM_FORMAT_YUYV) overlay |= 0x100; nvif_wr32(dev, NV_PVIDEO_OVERLAY, overlay); diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c index b617e5d..cb85cb7 100644 --- a/drivers/gpu/drm/nouveau/nv50_display.c +++ b/drivers/gpu/drm/nouveau/nv50_display.c @@ -1153,7 +1153,7 @@ nv50_curs_acquire(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw, if (asyw->state.fb->width != asyw->state.fb->height) return -EINVAL; - switch (asyw->state.fb->pixel_format) { + switch (asyw->state.fb->format->format) { case DRM_FORMAT_ARGB8888: asyh->curs.format = 1; break; default: WARN_ON(1); @@ -1438,7 +1438,7 @@ nv50_base_acquire(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw, asyh->base.w = asyw->state.fb->width; asyh->base.h = asyw->state.fb->height; - switch (fb->pixel_format) { + switch (fb->format->format) { case DRM_FORMAT_C8 : asyw->image.format = 0x1e; break; case DRM_FORMAT_RGB565 : asyw->image.format = 0xe8; break; case DRM_FORMAT_XRGB1555 : -- cgit v1.1 From 9338203c4f03ffe323b67f0b2fa17b9811fa9bb6 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Mon, 28 Nov 2016 20:51:09 +0200 Subject: drm: Don't include in used to define most of the in-kernel KMS API. It has now been split into separate files for each object type, but still includes most other KMS headers to avoid breaking driver compilation. As a step towards fixing that problem, remove the inclusion of from and include it instead where appropriate. Also remove the forward declarations of the drm_encoder and drm_encoder_helper_funcs structures from as they're not needed in the header. now has to include and contain a forward declaration of struct drm_encoder in order to allow including it as the first header in a compilation unit. Signed-off-by: Laurent Pinchart Reviewed-by: Daniel Vetter Reviewed-by: Sinclair Yeh # For vmwgfx Reviewed-by: Alex Deucher Signed-off-by: Archit Taneja Link: http://patchwork.freedesktop.org/patch/msgid/1481709550-29226-2-git-send-email-laurent.pinchart+renesas@ideasonboard.com --- drivers/gpu/drm/nouveau/nouveau_connector.h | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.h b/drivers/gpu/drm/nouveau/nouveau_connector.h index 096983c..a4d1a05 100644 --- a/drivers/gpu/drm/nouveau/nouveau_connector.h +++ b/drivers/gpu/drm/nouveau/nouveau_connector.h @@ -30,6 +30,7 @@ #include #include +#include #include #include "nouveau_crtc.h" -- cgit v1.1 From 2fa70bb9b5642211c521910d23e8b6c8d425fb89 Mon Sep 17 00:00:00 2001 From: Kees Cook Date: Fri, 16 Dec 2016 17:04:42 -0800 Subject: drm/nouveau: use designated initializers Prepare to mark sensitive kernel structures for randomization by making sure they're using designated initializers. These were identified during allyesconfig builds of x86, arm, and arm64, with most initializer fixes extracted from grsecurity. Signed-off-by: Kees Cook Signed-off-by: Daniel Vetter Link: http://patchwork.freedesktop.org/patch/msgid/20161217010442.GA140619@beast --- drivers/gpu/drm/nouveau/nouveau_ttm.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nouveau_ttm.c b/drivers/gpu/drm/nouveau/nouveau_ttm.c index a6dbe82..ec4668a 100644 --- a/drivers/gpu/drm/nouveau/nouveau_ttm.c +++ b/drivers/gpu/drm/nouveau/nouveau_ttm.c @@ -107,10 +107,10 @@ nouveau_vram_manager_new(struct ttm_mem_type_manager *man, } const struct ttm_mem_type_manager_func nouveau_vram_manager = { - nouveau_vram_manager_init, - nouveau_vram_manager_fini, - nouveau_vram_manager_new, - nouveau_vram_manager_del, + .init = nouveau_vram_manager_init, + .takedown = nouveau_vram_manager_fini, + .get_node = nouveau_vram_manager_new, + .put_node = nouveau_vram_manager_del, }; static int @@ -184,11 +184,11 @@ nouveau_gart_manager_debug(struct ttm_mem_type_manager *man, const char *prefix) } const struct ttm_mem_type_manager_func nouveau_gart_manager = { - nouveau_gart_manager_init, - nouveau_gart_manager_fini, - nouveau_gart_manager_new, - nouveau_gart_manager_del, - nouveau_gart_manager_debug + .init = nouveau_gart_manager_init, + .takedown = nouveau_gart_manager_fini, + .get_node = nouveau_gart_manager_new, + .put_node = nouveau_gart_manager_del, + .debug = nouveau_gart_manager_debug }; /*XXX*/ @@ -257,11 +257,11 @@ nv04_gart_manager_debug(struct ttm_mem_type_manager *man, const char *prefix) } const struct ttm_mem_type_manager_func nv04_gart_manager = { - nv04_gart_manager_init, - nv04_gart_manager_fini, - nv04_gart_manager_new, - nv04_gart_manager_del, - nv04_gart_manager_debug + .init = nv04_gart_manager_init, + .takedown = nv04_gart_manager_fini, + .get_node = nv04_gart_manager_new, + .put_node = nv04_gart_manager_del, + .debug = nv04_gart_manager_debug }; int -- cgit v1.1 From a743d7582db9aba0e7078d6386bdad2756309dba Mon Sep 17 00:00:00 2001 From: Dhinakaran Pandiyan Date: Thu, 22 Dec 2016 00:50:42 -0800 Subject: drm: Wrap the check for atomic_commit implementation This check is useful for drivers that do not have DRIVER_ATOMIC set but have atomic modesetting internally implemented. Wrap the check into a function since this is used in many places and as a bonus, the function name helps to document what the check is for. v2: Change return type to bool (Ville) Move the function drm_atomic.h (Daniel) Fixed comment marker for documentation Suggested-by: Daniel Vetter Cc: Daniel Vetter Cc: Ben Skeggs Signed-off-by: Dhinakaran Pandiyan [danvet: Move back to drmP.h because include hell.] Signed-off-by: Daniel Vetter Link: http://patchwork.freedesktop.org/patch/msgid/1482396643-32456-1-git-send-email-dhinakaran.pandiyan@intel.com --- drivers/gpu/drm/nouveau/nouveau_connector.c | 5 +++-- drivers/gpu/drm/nouveau/nouveau_display.c | 6 +++--- drivers/gpu/drm/nouveau/nouveau_fbcon.c | 3 ++- 3 files changed, 8 insertions(+), 6 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c index 947c200..966d20a 100644 --- a/drivers/gpu/drm/nouveau/nouveau_connector.c +++ b/drivers/gpu/drm/nouveau/nouveau_connector.c @@ -33,6 +33,7 @@ #include #include #include +#include #include "nouveau_reg.h" #include "nouveau_drv.h" @@ -769,7 +770,7 @@ nouveau_connector_set_property(struct drm_connector *connector, struct drm_encoder *encoder = to_drm_encoder(nv_encoder); int ret; - if (connector->dev->mode_config.funcs->atomic_commit) + if (drm_drv_uses_atomic_modeset(connector->dev)) return drm_atomic_helper_connector_set_property(connector, property, value); ret = connector->funcs->atomic_set_property(&nv_connector->base, @@ -1074,7 +1075,7 @@ nouveau_connector_helper_funcs = { static int nouveau_connector_dpms(struct drm_connector *connector, int mode) { - if (connector->dev->mode_config.funcs->atomic_commit) + if (drm_drv_uses_atomic_modeset(connector->dev)) return drm_atomic_helper_connector_dpms(connector, mode); return drm_helper_connector_dpms(connector, mode); } diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c index c5cf888..add353e 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.c +++ b/drivers/gpu/drm/nouveau/nouveau_display.c @@ -162,7 +162,7 @@ nouveau_display_vblstamp(struct drm_device *dev, unsigned int pipe, list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { if (nouveau_crtc(crtc)->index == pipe) { struct drm_display_mode *mode; - if (dev->mode_config.funcs->atomic_commit) + if (drm_drv_uses_atomic_modeset(dev)) mode = &crtc->state->adjusted_mode; else mode = &crtc->hwmode; @@ -738,7 +738,7 @@ nouveau_display_suspend(struct drm_device *dev, bool runtime) struct nouveau_display *disp = nouveau_display(dev); struct drm_crtc *crtc; - if (dev->mode_config.funcs->atomic_commit) { + if (drm_drv_uses_atomic_modeset(dev)) { if (!runtime) { disp->suspend = nouveau_atomic_suspend(dev); if (IS_ERR(disp->suspend)) { @@ -784,7 +784,7 @@ nouveau_display_resume(struct drm_device *dev, bool runtime) struct drm_crtc *crtc; int ret; - if (dev->mode_config.funcs->atomic_commit) { + if (drm_drv_uses_atomic_modeset(dev)) { nouveau_display_init(dev); if (disp->suspend) { drm_atomic_helper_resume(dev, disp->suspend); diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c index 5600f6c..9de6abb 100644 --- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c +++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c @@ -41,6 +41,7 @@ #include #include #include +#include #include "nouveau_drv.h" #include "nouveau_gem.h" @@ -524,7 +525,7 @@ nouveau_fbcon_init(struct drm_device *dev) preferred_bpp = 32; /* disable all the possible outputs/crtcs before entering KMS mode */ - if (!dev->mode_config.funcs->atomic_commit) + if (!drm_drv_uses_atomic_modeset(dev)) drm_helper_disable_unused_functions(dev); ret = drm_fb_helper_initial_config(&fbcon->helper, preferred_bpp); -- cgit v1.1 From a5ad0fd8524e5144512a5c25eda5a5d6fd55fda8 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Sun, 1 Jan 2017 16:20:53 -0800 Subject: drm: nouveau: fix build when LEDS_CLASS=m Fix build errors in nouveau driver when CONFIG_LEDS_CLASS=m and CONFIG_DRM_NOUVEAU=y. If LEDS_CLASS is enabled, DRM_NOUVEAU is restricted to the same kconfig value as LEDS_CLASS. drivers/built-in.o: In function `nouveau_do_suspend': nouveau_drm.c:(.text+0x2030b1): undefined reference to `nouveau_led_suspend' drivers/built-in.o: In function `nouveau_do_resume': nouveau_drm.c:(.text+0x2034ca): undefined reference to `nouveau_led_resume' drivers/built-in.o: In function `nouveau_drm_unload': nouveau_drm.c:(.text+0x203a15): undefined reference to `nouveau_led_fini' drivers/built-in.o: In function `nouveau_drm_load': nouveau_drm.c:(.text+0x204423): undefined reference to `nouveau_led_init' BTW, this line in Kbuild: nouveau-$(CONFIG_LEDS_CLASS) += nouveau_led.o does nothing when CONFIG_LEDS_CLASS=m and CONFIG_DRM_NOUVEAU=y. Signed-off-by: Randy Dunlap Reported-by: kbuild test robot Cc: Martin Peres Cc: Ben Skeggs Signed-off-by: Daniel Vetter Link: http://patchwork.freedesktop.org/patch/msgid/029a1ec5-48ac-a3ce-3106-430e0f2584bb@infradead.org --- drivers/gpu/drm/nouveau/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/Kconfig b/drivers/gpu/drm/nouveau/Kconfig index 2922a82..0c78c30 100644 --- a/drivers/gpu/drm/nouveau/Kconfig +++ b/drivers/gpu/drm/nouveau/Kconfig @@ -1,6 +1,7 @@ config DRM_NOUVEAU tristate "Nouveau (NVIDIA) cards" depends on DRM && PCI + depends on LEDS_CLASS || LEDS_CLASS=n select FW_LOADER select DRM_KMS_HELPER select DRM_TTM -- cgit v1.1 From 00bd61757821e46e78300635450a657e250b6146 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Thu, 5 Jan 2017 08:59:17 +0100 Subject: Revert "drm: nouveau: fix build when LEDS_CLASS=m" This reverts commit a5ad0fd8524e5144512a5c25eda5a5d6fd55fda8. It results in kconfing complaining about recursive depencies: drivers/usb/Kconfig:39:error: recursive dependency detected! For a resolution refer to Documentation/kbuild/kconfig-language.txt subsection "Kconfig recursive dependency limitations" drivers/input/mouse/Kconfig:187: symbol MOUSE_APPLETOUCH depends on INPUT For a resolution refer to Documentation/kbuild/kconfig-language.txt subsection "Kconfig recursive dependency limitations" drivers/input/Kconfig:8: symbol INPUT is selected by VT For a resolution refer to Documentation/kbuild/kconfig-language.txt subsection "Kconfig recursive dependency limitations" drivers/tty/Kconfig:12: symbol VT is selected by FB_STI For a resolution refer to Documentation/kbuild/kconfig-language.txt subsection "Kconfig recursive dependency limitations" drivers/video/fbdev/Kconfig:678: symbol FB_STI depends on FB For a resolution refer to Documentation/kbuild/kconfig-language.txt subsection "Kconfig recursive dependency limitations" drivers/video/fbdev/Kconfig:5: symbol FB is selected by DRM_KMS_FB_HELPER For a resolution refer to Documentation/kbuild/kconfig-language.txt subsection "Kconfig recursive dependency limitations" drivers/gpu/drm/Kconfig:72: symbol DRM_KMS_FB_HELPER is selected by DRM_KMS_CMA_HELPER For a resolution refer to Documentation/kbuild/kconfig-language.txt subsection "Kconfig recursive dependency limitations" drivers/gpu/drm/Kconfig:128: symbol DRM_KMS_CMA_HELPER is selected by DRM_HDLCD For a resolution refer to Documentation/kbuild/kconfig-language.txt subsection "Kconfig recursive dependency limitations" drivers/gpu/drm/arm/Kconfig:6: symbol DRM_HDLCD depends on COMMON_CLK For a resolution refer to Documentation/kbuild/kconfig-language.txt subsection "Kconfig recursive dependency limitations" drivers/clk/Kconfig:9: symbol COMMON_CLK is selected by X86_INTEL_QUARK For a resolution refer to Documentation/kbuild/kconfig-language.txt subsection "Kconfig recursive dependency limitations" arch/x86/Kconfig:554: symbol X86_INTEL_QUARK depends on X86_PLATFORM_DEVICES For a resolution refer to Documentation/kbuild/kconfig-language.txt subsection "Kconfig recursive dependency limitations" drivers/platform/x86/Kconfig:5: symbol X86_PLATFORM_DEVICES is selected by DRM_NOUVEAU For a resolution refer to Documentation/kbuild/kconfig-language.txt subsection "Kconfig recursive dependency limitations" drivers/gpu/drm/nouveau/Kconfig:1: symbol DRM_NOUVEAU depends on LEDS_CLASS For a resolution refer to Documentation/kbuild/kconfig-language.txt subsection "Kconfig recursive dependency limitations" drivers/leds/Kconfig:16: symbol LEDS_CLASS is selected by ATH9K_HTC For a resolution refer to Documentation/kbuild/kconfig-language.txt subsection "Kconfig recursive dependency limitations" drivers/net/wireless/ath/ath9k/Kconfig:158: symbol ATH9K_HTC depends on USB warning: (DRM_NOUVEAU && DRM_I915 && DRM_GMA500) selects ACPI_VIDEO which has unmet direct dependencies (ACPI && X86 && +BACKLIGHT_CLASS_DEVICE && INPUT) And there's apparently a better patch available already. Signed-off-by: Daniel Vetter --- drivers/gpu/drm/nouveau/Kconfig | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/Kconfig b/drivers/gpu/drm/nouveau/Kconfig index 0c78c30..2922a82 100644 --- a/drivers/gpu/drm/nouveau/Kconfig +++ b/drivers/gpu/drm/nouveau/Kconfig @@ -1,7 +1,6 @@ config DRM_NOUVEAU tristate "Nouveau (NVIDIA) cards" depends on DRM && PCI - depends on LEDS_CLASS || LEDS_CLASS=n select FW_LOADER select DRM_KMS_HELPER select DRM_TTM -- cgit v1.1 From 99c48e1e38f0aeaa107ad67c8d91f6c9d9d567a9 Mon Sep 17 00:00:00 2001 From: Benjamin Gaignard Date: Wed, 4 Jan 2017 10:12:56 +0100 Subject: drm: compile drm_vm.c only when needed drm_vm.c functions are only need for DRM_LEGACY and DRM_NOUVEAU. Use a new DRM_VM to define when drm_vm.c in needed. stub drm_legacy_vma_flush() to avoid compilation issues version 4: - a "config DRM_VM" in Kconfig Signed-off-by: Benjamin Gaignard [danvet: Fix conflict.] Signed-off-by: Daniel Vetter --- drivers/gpu/drm/nouveau/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/Kconfig b/drivers/gpu/drm/nouveau/Kconfig index 2922a82..0f2f0af 100644 --- a/drivers/gpu/drm/nouveau/Kconfig +++ b/drivers/gpu/drm/nouveau/Kconfig @@ -16,6 +16,7 @@ config DRM_NOUVEAU select INPUT if ACPI && X86 select THERMAL if ACPI && X86 select ACPI_VIDEO if ACPI && X86 + select DRM_VM help Choose this option for open-source NVIDIA support. -- cgit v1.1 From 11b3c20bdd15d17382068be569740de1dccb173d Mon Sep 17 00:00:00 2001 From: Gabriel Krisman Bertazi Date: Fri, 6 Jan 2017 15:57:31 -0200 Subject: drm: Change the return type of the unload hook to void MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The integer returned by the unload hook is ignored by the drm core, so let's make it void. This patch was created using the following Coccinelle semantic script (except for the declaration and comment in drm_drv.h): Compile-tested only. // @ get_name @ struct drm_driver drv; identifier fn; @@ drv.unload = fn; @ replace_type @ identifier get_name.fn; @@ - int + void fn (...) { ... } @ remove_return_param @ identifier get_name.fn; @@ void fn (...) { <... if (...) return - ... ; ...> } @ drop_final_return @ identifier get_name.fn; @@ void fn (...) { ... - return 0; } // Suggested-by: Daniel Vetter Signed-off-by: Gabriel Krisman Bertazi Acked-by: Christian König . Signed-off-by: Daniel Vetter Link: http://patchwork.freedesktop.org/patch/msgid/20170106175731.29196-1-krisman@collabora.co.uk --- drivers/gpu/drm/nouveau/nouveau_drm.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c index 59348fc..dd7b52a 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c @@ -502,7 +502,7 @@ fail_device: return ret; } -static int +static void nouveau_drm_unload(struct drm_device *dev) { struct nouveau_drm *drm = nouveau_drm(dev); @@ -531,7 +531,6 @@ nouveau_drm_unload(struct drm_device *dev) if (drm->hdmi_device) pci_dev_put(drm->hdmi_device); nouveau_cli_destroy(&drm->client); - return 0; } void -- cgit v1.1 From 011cda589938e56eb93685dee8ead0bb0506f9e2 Mon Sep 17 00:00:00 2001 From: Benjamin Gaignard Date: Sat, 7 Jan 2017 12:39:11 +0100 Subject: drm: fix compilations issues introduced by "drm: allow to use mmuless SoC" Removing MMU configuration flag from DRM make few automatic build failed when they answer yes to all flags. Add asm/vga.h file on Blackfin architecture to not broke compilation. Signed-off-by: Benjamin Gaignard Fixes: 62a0d98a188c ("drm: allow to use mmuless SoC") Signed-off-by: Daniel Vetter Link: http://patchwork.freedesktop.org/patch/msgid/1483789151-6603-1-git-send-email-benjamin.gaignard@linaro.org --- drivers/gpu/drm/nouveau/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/Kconfig b/drivers/gpu/drm/nouveau/Kconfig index 0f2f0af..c02a134 100644 --- a/drivers/gpu/drm/nouveau/Kconfig +++ b/drivers/gpu/drm/nouveau/Kconfig @@ -1,6 +1,6 @@ config DRM_NOUVEAU tristate "Nouveau (NVIDIA) cards" - depends on DRM && PCI + depends on DRM && PCI && MMU select FW_LOADER select DRM_KMS_HELPER select DRM_TTM -- cgit v1.1 From ea441bd33f93aa7f6f404c8877e6d3313a4dbdbe Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Mon, 9 Jan 2017 19:25:43 +0800 Subject: drm: nouveau: use crtc helper drm_crtc_from_index() Use drm_crtc_from_index() to find drm_crtc for given index. Signed-off-by: Shawn Guo Cc: Ben Skeggs Signed-off-by: Sean Paul Link: http://patchwork.freedesktop.org/patch/msgid/1483961145-18453-5-git-send-email-shawnguo@kernel.org --- drivers/gpu/drm/nouveau/nouveau_display.c | 33 +++++++++++++++++-------------- 1 file changed, 18 insertions(+), 15 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c index add353e..6b57007 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.c +++ b/drivers/gpu/drm/nouveau/nouveau_display.c @@ -58,27 +58,30 @@ int nouveau_display_vblank_enable(struct drm_device *dev, unsigned int pipe) { struct drm_crtc *crtc; - list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { - struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); - if (nv_crtc->index == pipe) { - nvif_notify_get(&nv_crtc->vblank); - return 0; - } - } - return -EINVAL; + struct nouveau_crtc *nv_crtc; + + crtc = drm_crtc_from_index(dev, pipe); + if (!crtc) + return -EINVAL; + + nv_crtc = nouveau_crtc(crtc); + nvif_notify_get(&nv_crtc->vblank); + + return 0; } void nouveau_display_vblank_disable(struct drm_device *dev, unsigned int pipe) { struct drm_crtc *crtc; - list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { - struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); - if (nv_crtc->index == pipe) { - nvif_notify_put(&nv_crtc->vblank); - return; - } - } + struct nouveau_crtc *nv_crtc; + + crtc = drm_crtc_from_index(dev, pipe); + if (!crtc) + return; + + nv_crtc = nouveau_crtc(crtc); + nvif_notify_put(&nv_crtc->vblank); } static inline int -- cgit v1.1 From 7b0a89a6db9a5912065e174162ec4a653c9b25d6 Mon Sep 17 00:00:00 2001 From: Dhinakaran Pandiyan Date: Tue, 24 Jan 2017 15:49:29 -0800 Subject: drm/dp: Store drm_device in MST topology manager struct drm_dp_mst_topology_mgr currently stores a pointer to struct dev. Changing this to instead hold a pointer to drm_device is more useful as it gives access to DRM structures. This also makes it consistent with other DRM structures like drm_crtc, drm_connector etc. Signed-off-by: Dhinakaran Pandiyan Reviewed-by: Dave Airlie Signed-off-by: Daniel Vetter Link: http://patchwork.freedesktop.org/patch/msgid/1485301777-3465-2-git-send-email-dhinakaran.pandiyan@intel.com --- drivers/gpu/drm/nouveau/nv50_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c index cb85cb7..452da48 100644 --- a/drivers/gpu/drm/nouveau/nv50_display.c +++ b/drivers/gpu/drm/nouveau/nv50_display.c @@ -3417,7 +3417,7 @@ nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max, mstm->outp = outp; mstm->mgr.cbs = &nv50_mstm; - ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev->dev, aux, aux_max, + ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max, max_payloads, conn_base_id); if (ret) return ret; -- cgit v1.1 From 2ce0264d61548b51d5d406ff9f414af10b9c7348 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Wed, 25 Jan 2017 07:26:52 +0100 Subject: drm: remove device_is_agp callback With that the drm_pci_device_is_agp function becomes trivial, so inline that too. And while at it, move the drm_pci_agp_destroy declaration into drm-internal.h, since it's not used by drivers. Cc: Alex Deucher Cc: Ben Skeggs Reviewed-by: Alex Deucher Signed-off-by: Daniel Vetter Link: http://patchwork.freedesktop.org/patch/msgid/20170125062657.19270-11-daniel.vetter@ffwll.ch --- drivers/gpu/drm/nouveau/nouveau_abi16.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.c b/drivers/gpu/drm/nouveau/nouveau_abi16.c index 7bd4683..4df4f6e 100644 --- a/drivers/gpu/drm/nouveau/nouveau_abi16.c +++ b/drivers/gpu/drm/nouveau/nouveau_abi16.c @@ -199,7 +199,7 @@ nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS) if (!nvxx_device(device)->func->pci) getparam->value = 3; else - if (drm_pci_device_is_agp(dev)) + if (pci_find_capability(dev->pdev, PCI_CAP_ID_AGP)) getparam->value = 0; else if (!pci_is_pcie(dev->pdev)) -- cgit v1.1 From 66257db7a5276d7f1aff8850388a0eb675ffa2e1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Nicolai=20H=C3=A4hnle?= Date: Thu, 15 Dec 2016 17:23:49 +0100 Subject: drm/ttm: add evict parameter to ttm_bo_driver::move_notify MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Ensure that the driver can listen to evictions even when they don't take the path through ttm_bo_driver::move. This is crucial for amdgpu, which relies on an eviction counter to skip re-binding page tables when possible. Signed-off-by: Nicolai Hähnle Reviewed-by: Chunming Zhou Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/nouveau/nouveau_bo.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index dd07ca1..2435183 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -1194,7 +1194,8 @@ out: } static void -nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem) +nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, bool evict, + struct ttm_mem_reg *new_mem) { struct nouveau_bo *nvbo = nouveau_bo(bo); struct nvkm_vma *vma; -- cgit v1.1 From 260498f2cdfcf3a3a266b212a86c9059623ffa32 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Thu, 12 Jan 2017 11:50:13 +0100 Subject: drm/ttm: revert "implement LRU add callbacks v2" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The additional housekeeping had too much CPU overhead, let's use the BO priorities instead. agd: also revert hibmc changes Reviewed-by: Sinclair Yeh Signed-off-by: Christian König Reviewed-and-Tested-by: Roger.He Signed-off-by: Alex Deucher --- drivers/gpu/drm/nouveau/nouveau_bo.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index 2435183..8a528eb 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -1571,8 +1571,6 @@ struct ttm_bo_driver nouveau_bo_driver = { .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify, .io_mem_reserve = &nouveau_ttm_io_mem_reserve, .io_mem_free = &nouveau_ttm_io_mem_free, - .lru_tail = &ttm_bo_default_lru_tail, - .swap_lru_tail = &ttm_bo_default_swap_lru_tail, }; struct nvkm_vma * -- cgit v1.1 From e4563f6ba71792c77aeccb2092cc23149b44e642 Mon Sep 17 00:00:00 2001 From: Gabriel Krisman Bertazi Date: Thu, 2 Feb 2017 14:26:40 -0200 Subject: drm: Rely on mode_config data for fb_helper initialization Instead of receiving the num_crts as a parameter, we can read it directly from the mode_config structure. I audited the drivers that invoke this helper and I believe all of them initialize the mode_config struct accordingly, prior to calling the fb_helper. I used the following coccinelle hack to make this transformation, except for the function headers and comment updates. The first and second rules are split because I couldn't find a way to remove the unused temporary variables at the same time I removed the parameter. // @r@ expression A,B,D,E; identifier C; @@ ( - drm_fb_helper_init(A,B,C,D) + drm_fb_helper_init(A,B,D) | - drm_fbdev_cma_init_with_funcs(A,B,C,D,E) + drm_fbdev_cma_init_with_funcs(A,B,D,E) | - drm_fbdev_cma_init(A,B,C,D) + drm_fbdev_cma_init(A,B,D) ) @@ expression A,B,C,D,E; @@ ( - drm_fb_helper_init(A,B,C,D) + drm_fb_helper_init(A,B,D) | - drm_fbdev_cma_init_with_funcs(A,B,C,D,E) + drm_fbdev_cma_init_with_funcs(A,B,D,E) | - drm_fbdev_cma_init(A,B,C,D) + drm_fbdev_cma_init(A,B,D) ) @@ identifier r.C; type T; expression V; @@ - T C; <... when != C - C = V; ...> // Changes since v1: - Rebased on top of the tip of drm-misc-next. - Remove mention to sti since a proper fix got merged. Suggested-by: Daniel Vetter Signed-off-by: Gabriel Krisman Bertazi Reviewed-by: Eric Anholt Signed-off-by: Daniel Vetter Link: http://patchwork.freedesktop.org/patch/msgid/20170202162640.27261-1-krisman@collabora.co.uk --- drivers/gpu/drm/nouveau/nouveau_fbcon.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c index 9de6abb..971c147 100644 --- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c +++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c @@ -507,8 +507,7 @@ nouveau_fbcon_init(struct drm_device *dev) drm_fb_helper_prepare(dev, &fbcon->helper, &nouveau_fbcon_helper_funcs); - ret = drm_fb_helper_init(dev, &fbcon->helper, - dev->mode_config.num_crtc, 4); + ret = drm_fb_helper_init(dev, &fbcon->helper, 4); if (ret) goto free; -- cgit v1.1 From c1fcb14879e87c837c360c2ec9f32d19f62faf89 Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Tue, 13 Dec 2016 17:11:17 +0900 Subject: drm/nouveau/core: constify nv*_printk macros Constify the local variables declared in these macros so we can pass const pointers to them. Signed-off-by: Alexandre Courbot Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvkm/core/client.h | 4 ++-- drivers/gpu/drm/nouveau/include/nvkm/core/device.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/client.h b/drivers/gpu/drm/nouveau/include/nvkm/core/client.h index eaf5905..9908334 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/client.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/client.h @@ -37,8 +37,8 @@ int nvkm_client_notify_put(struct nvkm_client *, int index); /* logging for client-facing objects */ #define nvif_printk(o,l,p,f,a...) do { \ - struct nvkm_object *_object = (o); \ - struct nvkm_client *_client = _object->client; \ + const struct nvkm_object *_object = (o); \ + const struct nvkm_client *_client = _object->client; \ if (_client->debug >= NV_DBG_##l) \ printk(KERN_##p "nouveau: %s:%08x:%08x: "f, _client->name, \ _object->handle, _object->oclass, ##a); \ diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h index 6bc712f..d426b86 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h @@ -262,7 +262,7 @@ extern const struct nvkm_sclass nvkm_udevice_sclass; /* device logging */ #define nvdev_printk_(d,l,p,f,a...) do { \ - struct nvkm_device *_device = (d); \ + const struct nvkm_device *_device = (d); \ if (_device->debug >= (l)) \ dev_##p(_device->dev, f, ##a); \ } while(0) diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h b/drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h index 57adefa..ca9ed3d 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h @@ -32,7 +32,7 @@ void nvkm_subdev_intr(struct nvkm_subdev *); /* subdev logging */ #define nvkm_printk_(s,l,p,f,a...) do { \ - struct nvkm_subdev *_subdev = (s); \ + const struct nvkm_subdev *_subdev = (s); \ if (_subdev->debug >= (l)) { \ dev_##p(_subdev->device->dev, "%s: "f, \ nvkm_subdev_name[_subdev->index], ##a); \ -- cgit v1.1 From c599dd4b70d3d8a485be6b80d8b190beb3df874b Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Tue, 13 Dec 2016 17:11:18 +0900 Subject: drm/nouveau/mc: add nvkm_mc_enabled() function Add a function that allows us to query whether a given subdev is currently enabled or not. Signed-off-by: Alexandre Courbot Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h | 1 + drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c | 10 ++++++++++ 2 files changed, 11 insertions(+) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h index 27d25b1..e68ba63 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h @@ -9,6 +9,7 @@ struct nvkm_mc { void nvkm_mc_enable(struct nvkm_device *, enum nvkm_devidx); void nvkm_mc_disable(struct nvkm_device *, enum nvkm_devidx); +bool nvkm_mc_enabled(struct nvkm_device *, enum nvkm_devidx); void nvkm_mc_reset(struct nvkm_device *, enum nvkm_devidx); void nvkm_mc_intr(struct nvkm_device *, bool *handled); void nvkm_mc_intr_unarm(struct nvkm_device *); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c index 6b25e25..09f669a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c @@ -161,6 +161,16 @@ nvkm_mc_enable(struct nvkm_device *device, enum nvkm_devidx devidx) } } +bool +nvkm_mc_enabled(struct nvkm_device *device, enum nvkm_devidx devidx) +{ + u64 pmc_enable = nvkm_mc_reset_mask(device, false, devidx); + + return (pmc_enable != 0) && + ((nvkm_rd32(device, 0x000200) & pmc_enable) == pmc_enable); +} + + static int nvkm_mc_fini(struct nvkm_subdev *subdev, bool suspend) { -- cgit v1.1 From 31214108ad08766075bf111df90c1f26520b0159 Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Tue, 13 Dec 2016 17:11:19 +0900 Subject: drm/nouveau/core: add falcon library functions Falcon processors are used in various places of GPU chips. Although there exist different versions of the falcon, and some variants exist, the base set of actions performed on them is the same, which results in lots of duplicated code. This patch consolidates the current nvkm_falcon structure and extends it with the following features: * Ability for an engine to obtain and later release a given falcon, * Abstractions for basic operations (IMEM/DMEM access, start, etc) * Abstractions for secure operations if a falcon is secure Abstractions make it easy to e.g. start a falcon, without having to care about its details. For instance, falcons in secure mode need to be started by writing to a different register. Right now the abstractions variants only cover secure vs. non-secure falcon, but more will come as e.g. SEC2 support is added. This is still a WIP as other functions previously done by engine/falcon.c need to be reimplemented. However this first step allows to keep things simple and to discuss basic design. Signed-off-by: Alexandre Courbot Signed-off-by: Ben Skeggs --- .../gpu/drm/nouveau/include/nvkm/engine/falcon.h | 76 +++++- drivers/gpu/drm/nouveau/nvkm/Kbuild | 1 + drivers/gpu/drm/nouveau/nvkm/falcon/Kbuild | 2 + drivers/gpu/drm/nouveau/nvkm/falcon/base.c | 191 +++++++++++++++ drivers/gpu/drm/nouveau/nvkm/falcon/priv.h | 8 + drivers/gpu/drm/nouveau/nvkm/falcon/v1.c | 263 +++++++++++++++++++++ 6 files changed, 537 insertions(+), 4 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/nvkm/falcon/Kbuild create mode 100644 drivers/gpu/drm/nouveau/nvkm/falcon/base.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/falcon/priv.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/falcon/v1.c (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h index e6baf03..7e498e6 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h @@ -4,13 +4,26 @@ #include struct nvkm_fifo_chan; +enum nvkm_falcon_dmaidx { + FALCON_DMAIDX_UCODE = 0, + FALCON_DMAIDX_VIRT = 1, + FALCON_DMAIDX_PHYS_VID = 2, + FALCON_DMAIDX_PHYS_SYS_COH = 3, + FALCON_DMAIDX_PHYS_SYS_NCOH = 4, +}; + struct nvkm_falcon { const struct nvkm_falcon_func *func; - struct nvkm_engine engine; - + const struct nvkm_subdev *owner; + const char *name; u32 addr; - u8 version; - u8 secret; + + struct mutex mutex; + const struct nvkm_subdev *user; + + u8 version; + u8 secret; + bool debug; struct nvkm_memory *core; bool external; @@ -19,15 +32,25 @@ struct nvkm_falcon { u32 limit; u32 *data; u32 size; + u8 ports; } code; struct { u32 limit; u32 *data; u32 size; + u8 ports; } data; + + struct nvkm_engine engine; }; +int nvkm_falcon_v1_new(struct nvkm_subdev *owner, const char *name, u32 addr, + struct nvkm_falcon **); +void nvkm_falcon_del(struct nvkm_falcon **); +int nvkm_falcon_get(struct nvkm_falcon *, const struct nvkm_subdev *); +void nvkm_falcon_put(struct nvkm_falcon *, const struct nvkm_subdev *); + int nvkm_falcon_new_(const struct nvkm_falcon_func *, struct nvkm_device *, int index, bool enable, u32 addr, struct nvkm_engine **); @@ -42,6 +65,51 @@ struct nvkm_falcon_func { } data; void (*init)(struct nvkm_falcon *); void (*intr)(struct nvkm_falcon *, struct nvkm_fifo_chan *); + void (*load_imem)(struct nvkm_falcon *, void *, u32, u32, u16, u8, bool); + void (*load_dmem)(struct nvkm_falcon *, void *, u32, u32, u8); + void (*read_dmem)(struct nvkm_falcon *, u32, u32, u8, void *); + void (*bind_context)(struct nvkm_falcon *, struct nvkm_gpuobj *); + int (*wait_for_halt)(struct nvkm_falcon *, u32); + int (*clear_interrupt)(struct nvkm_falcon *, u32); + void (*set_start_addr)(struct nvkm_falcon *, u32 start_addr); + void (*start)(struct nvkm_falcon *); + int (*enable)(struct nvkm_falcon *falcon); + void (*disable)(struct nvkm_falcon *falcon); + struct nvkm_sclass sclass[]; }; + +static inline u32 +nvkm_falcon_rd32(struct nvkm_falcon *falcon, u32 addr) +{ + return nvkm_rd32(falcon->owner->device, falcon->addr + addr); +} + +static inline void +nvkm_falcon_wr32(struct nvkm_falcon *falcon, u32 addr, u32 data) +{ + nvkm_wr32(falcon->owner->device, falcon->addr + addr, data); +} + +static inline u32 +nvkm_falcon_mask(struct nvkm_falcon *falcon, u32 addr, u32 mask, u32 val) +{ + struct nvkm_device *device = falcon->owner->device; + + return nvkm_mask(device, falcon->addr + addr, mask, val); +} + +void nvkm_falcon_load_imem(struct nvkm_falcon *, void *, u32, u32, u16, u8, + bool); +void nvkm_falcon_load_dmem(struct nvkm_falcon *, void *, u32, u32, u8); +void nvkm_falcon_read_dmem(struct nvkm_falcon *, u32, u32, u8, void *); +void nvkm_falcon_bind_context(struct nvkm_falcon *, struct nvkm_gpuobj *); +void nvkm_falcon_set_start_addr(struct nvkm_falcon *, u32); +void nvkm_falcon_start(struct nvkm_falcon *); +int nvkm_falcon_wait_for_halt(struct nvkm_falcon *, u32); +int nvkm_falcon_clear_interrupt(struct nvkm_falcon *, u32); +int nvkm_falcon_enable(struct nvkm_falcon *); +void nvkm_falcon_disable(struct nvkm_falcon *); +int nvkm_falcon_reset(struct nvkm_falcon *); + #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/Kbuild b/drivers/gpu/drm/nouveau/nvkm/Kbuild index 2832147..e664378 100644 --- a/drivers/gpu/drm/nouveau/nvkm/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/Kbuild @@ -1,3 +1,4 @@ include $(src)/nvkm/core/Kbuild +include $(src)/nvkm/falcon/Kbuild include $(src)/nvkm/subdev/Kbuild include $(src)/nvkm/engine/Kbuild diff --git a/drivers/gpu/drm/nouveau/nvkm/falcon/Kbuild b/drivers/gpu/drm/nouveau/nvkm/falcon/Kbuild new file mode 100644 index 0000000..584863d --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/falcon/Kbuild @@ -0,0 +1,2 @@ +nvkm-y += nvkm/falcon/base.o +nvkm-y += nvkm/falcon/v1.o diff --git a/drivers/gpu/drm/nouveau/nvkm/falcon/base.c b/drivers/gpu/drm/nouveau/nvkm/falcon/base.c new file mode 100644 index 0000000..4852f31 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/falcon/base.c @@ -0,0 +1,191 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#include "priv.h" + +#include + +void +nvkm_falcon_load_imem(struct nvkm_falcon *falcon, void *data, u32 start, + u32 size, u16 tag, u8 port, bool secure) +{ + if (secure && !falcon->secret) { + nvkm_warn(falcon->user, + "writing with secure tag on a non-secure falcon!\n"); + return; + } + + falcon->func->load_imem(falcon, data, start, size, tag, port, + secure); +} + +void +nvkm_falcon_load_dmem(struct nvkm_falcon *falcon, void *data, u32 start, + u32 size, u8 port) +{ + falcon->func->load_dmem(falcon, data, start, size, port); +} + +void +nvkm_falcon_read_dmem(struct nvkm_falcon *falcon, u32 start, u32 size, u8 port, + void *data) +{ + falcon->func->read_dmem(falcon, start, size, port, data); +} + +void +nvkm_falcon_bind_context(struct nvkm_falcon *falcon, struct nvkm_gpuobj *inst) +{ + if (!falcon->func->bind_context) { + nvkm_error(falcon->user, + "Context binding not supported on this falcon!\n"); + return; + } + + falcon->func->bind_context(falcon, inst); +} + +void +nvkm_falcon_set_start_addr(struct nvkm_falcon *falcon, u32 start_addr) +{ + falcon->func->set_start_addr(falcon, start_addr); +} + +void +nvkm_falcon_start(struct nvkm_falcon *falcon) +{ + falcon->func->start(falcon); +} + +int +nvkm_falcon_enable(struct nvkm_falcon *falcon) +{ + struct nvkm_device *device = falcon->owner->device; + enum nvkm_devidx id = falcon->owner->index; + int ret; + + nvkm_mc_enable(device, id); + ret = falcon->func->enable(falcon); + if (ret) { + nvkm_mc_disable(device, id); + return ret; + } + + return 0; +} + +void +nvkm_falcon_disable(struct nvkm_falcon *falcon) +{ + struct nvkm_device *device = falcon->owner->device; + enum nvkm_devidx id = falcon->owner->index; + + /* already disabled, return or wait_idle will timeout */ + if (!nvkm_mc_enabled(device, id)) + return; + + falcon->func->disable(falcon); + + nvkm_mc_disable(device, id); +} + +int +nvkm_falcon_reset(struct nvkm_falcon *falcon) +{ + nvkm_falcon_disable(falcon); + return nvkm_falcon_enable(falcon); +} + +int +nvkm_falcon_wait_for_halt(struct nvkm_falcon *falcon, u32 ms) +{ + return falcon->func->wait_for_halt(falcon, ms); +} + +int +nvkm_falcon_clear_interrupt(struct nvkm_falcon *falcon, u32 mask) +{ + return falcon->func->clear_interrupt(falcon, mask); +} + +void +nvkm_falcon_put(struct nvkm_falcon *falcon, const struct nvkm_subdev *user) +{ + mutex_lock(&falcon->mutex); + if (falcon->user == user) { + nvkm_debug(falcon->user, "released %s falcon\n", falcon->name); + falcon->user = NULL; + } + mutex_unlock(&falcon->mutex); +} + +int +nvkm_falcon_get(struct nvkm_falcon *falcon, const struct nvkm_subdev *user) +{ + mutex_lock(&falcon->mutex); + if (falcon->user) { + nvkm_error(user, "%s falcon already acquired by %s!\n", + falcon->name, nvkm_subdev_name[falcon->user->index]); + mutex_unlock(&falcon->mutex); + return -EBUSY; + } + + nvkm_debug(user, "acquired %s falcon\n", falcon->name); + falcon->user = user; + mutex_unlock(&falcon->mutex); + return 0; +} + +void +nvkm_falcon_ctor(const struct nvkm_falcon_func *func, + struct nvkm_subdev *subdev, const char *name, u32 addr, + struct nvkm_falcon *falcon) +{ + u32 reg; + + falcon->func = func; + falcon->owner = subdev; + falcon->name = name; + falcon->addr = addr; + mutex_init(&falcon->mutex); + + reg = nvkm_falcon_rd32(falcon, 0x12c); + falcon->version = reg & 0xf; + falcon->secret = (reg >> 4) & 0x3; + falcon->code.ports = (reg >> 8) & 0xf; + falcon->data.ports = (reg >> 12) & 0xf; + + reg = nvkm_falcon_rd32(falcon, 0x108); + falcon->code.limit = (reg & 0x1ff) << 8; + falcon->data.limit = (reg & 0x3fe00) >> 1; + + reg = nvkm_falcon_rd32(falcon, 0xc08); + falcon->debug = (reg >> 20) & 0x1; +} + +void +nvkm_falcon_del(struct nvkm_falcon **pfalcon) +{ + if (*pfalcon) { + kfree(*pfalcon); + *pfalcon = NULL; + } +} diff --git a/drivers/gpu/drm/nouveau/nvkm/falcon/priv.h b/drivers/gpu/drm/nouveau/nvkm/falcon/priv.h new file mode 100644 index 0000000..97b56f7 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/falcon/priv.h @@ -0,0 +1,8 @@ +#ifndef __NVKM_FALCON_PRIV_H__ +#define __NVKM_FALCON_PRIV_H__ +#include + +void +nvkm_falcon_ctor(const struct nvkm_falcon_func *, struct nvkm_subdev *, + const char *, u32, struct nvkm_falcon *); +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/falcon/v1.c b/drivers/gpu/drm/nouveau/nvkm/falcon/v1.c new file mode 100644 index 0000000..24a2958 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/falcon/v1.c @@ -0,0 +1,263 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#include "priv.h" + +#include +#include +#include + +static void +nvkm_falcon_v1_load_imem(struct nvkm_falcon *falcon, void *data, u32 start, + u32 size, u16 tag, u8 port, bool secure) +{ + u8 rem = size % 4; + u32 reg; + int i; + + size -= rem; + + reg = start | BIT(24) | (secure ? BIT(28) : 0); + nvkm_falcon_wr32(falcon, 0x180 + (port * 16), reg); + for (i = 0; i < size / 4; i++) { + /* write new tag every 256B */ + if ((i & 0x3f) == 0) + nvkm_falcon_wr32(falcon, 0x188, tag++); + nvkm_falcon_wr32(falcon, 0x184, ((u32 *)data)[i]); + } + + /* + * If size is not a multiple of 4, mask the last work to ensure garbage + * does not get written + */ + if (rem) { + u32 extra = ((u32 *)data)[i]; + + /* write new tag every 256B */ + if ((i & 0x3f) == 0) + nvkm_falcon_wr32(falcon, 0x188, tag++); + nvkm_falcon_wr32(falcon, 0x184, extra & (BIT(rem * 8) - 1)); + ++i; + } + + /* code must be padded to 0x40 words */ + for (; i & 0x3f; i++) + nvkm_falcon_wr32(falcon, 0x184, 0); +} + +static void +nvkm_falcon_v1_load_dmem(struct nvkm_falcon *falcon, void *data, u32 start, + u32 size, u8 port) +{ + u8 rem = size % 4; + int i; + + size -= rem; + + nvkm_falcon_wr32(falcon, 0x1c0 + (port * 16), start | (0x1 << 24)); + for (i = 0; i < size / 4; i++) + nvkm_falcon_wr32(falcon, 0x1c4, ((u32 *)data)[i]); + + /* + * If size is not a multiple of 4, mask the last work to ensure garbage + * does not get read + */ + if (rem) { + u32 extra = ((u32 *)data)[i]; + + nvkm_falcon_wr32(falcon, 0x1c4, extra & (BIT(rem * 8) - 1)); + } +} + +static void +nvkm_falcon_v1_read_dmem(struct nvkm_falcon *falcon, u32 start, u32 size, + u8 port, void *data) +{ + u8 rem = size % 4; + int i; + + size -= rem; + + nvkm_falcon_wr32(falcon, 0x1c0 + (port * 16), start | (0x1 << 25)); + for (i = 0; i < size / 4; i++) + ((u32 *)data)[i] = nvkm_falcon_rd32(falcon, 0x1c4); + + /* + * If size is not a multiple of 4, mask the last work to ensure garbage + * does not get read + */ + if (rem) { + u32 extra = nvkm_falcon_rd32(falcon, 0x1c4); + + for (i = size; i < size + rem; i++) { + ((u8 *)data)[i] = (u8)(extra & 0xff); + extra >>= 8; + } + } +} + +static void +nvkm_falcon_v1_bind_context(struct nvkm_falcon *falcon, struct nvkm_gpuobj *ctx) +{ + u32 inst_loc; + + /* disable instance block binding */ + if (ctx == NULL) { + nvkm_falcon_wr32(falcon, 0x10c, 0x0); + return; + } + + nvkm_falcon_wr32(falcon, 0x10c, 0x1); + + /* setup apertures - virtual */ + nvkm_falcon_wr32(falcon, 0xe00 + 4 * FALCON_DMAIDX_UCODE, 0x4); + nvkm_falcon_wr32(falcon, 0xe00 + 4 * FALCON_DMAIDX_VIRT, 0x0); + /* setup apertures - physical */ + nvkm_falcon_wr32(falcon, 0xe00 + 4 * FALCON_DMAIDX_PHYS_VID, 0x4); + nvkm_falcon_wr32(falcon, 0xe00 + 4 * FALCON_DMAIDX_PHYS_SYS_COH, 0x5); + nvkm_falcon_wr32(falcon, 0xe00 + 4 * FALCON_DMAIDX_PHYS_SYS_NCOH, 0x6); + + /* Set context */ + if (nvkm_memory_target(ctx->memory) == NVKM_MEM_TARGET_VRAM) + inst_loc = 0x0; /* FB */ + else + inst_loc = 0x3; /* Non-coherent sysmem */ + + /* Enable context */ + nvkm_falcon_mask(falcon, 0x048, 0x1, 0x1); + nvkm_falcon_wr32(falcon, 0x480, + ((ctx->addr >> 12) & 0xfffffff) | + (inst_loc << 28) | (1 << 30)); +} + +static void +nvkm_falcon_v1_set_start_addr(struct nvkm_falcon *falcon, u32 start_addr) +{ + nvkm_falcon_wr32(falcon, 0x104, start_addr); +} + +static void +nvkm_falcon_v1_start(struct nvkm_falcon *falcon) +{ + u32 reg = nvkm_falcon_rd32(falcon, 0x100); + + if (reg & BIT(6)) + nvkm_falcon_wr32(falcon, 0x130, 0x2); + else + nvkm_falcon_wr32(falcon, 0x100, 0x2); +} + +static int +nvkm_falcon_v1_wait_for_halt(struct nvkm_falcon *falcon, u32 ms) +{ + struct nvkm_device *device = falcon->owner->device; + int ret; + + ret = nvkm_wait_msec(device, ms, falcon->addr + 0x100, 0x10, 0x10); + if (ret < 0) + return ret; + + return 0; +} + +static int +nvkm_falcon_v1_clear_interrupt(struct nvkm_falcon *falcon, u32 mask) +{ + struct nvkm_device *device = falcon->owner->device; + int ret; + + /* clear interrupt(s) */ + nvkm_falcon_mask(falcon, 0x004, mask, mask); + /* wait until interrupts are cleared */ + ret = nvkm_wait_msec(device, 10, falcon->addr + 0x008, mask, 0x0); + if (ret < 0) + return ret; + + return 0; +} + +static int +falcon_v1_wait_idle(struct nvkm_falcon *falcon) +{ + struct nvkm_device *device = falcon->owner->device; + int ret; + + ret = nvkm_wait_msec(device, 10, falcon->addr + 0x04c, 0xffff, 0x0); + if (ret < 0) + return ret; + + return 0; +} + +static int +nvkm_falcon_v1_enable(struct nvkm_falcon *falcon) +{ + struct nvkm_device *device = falcon->owner->device; + int ret; + + ret = nvkm_wait_msec(device, 10, falcon->addr + 0x10c, 0x6, 0x0); + if (ret < 0) { + nvkm_error(falcon->user, "Falcon mem scrubbing timeout\n"); + return ret; + } + + ret = falcon_v1_wait_idle(falcon); + if (ret) + return ret; + + /* enable IRQs */ + nvkm_falcon_wr32(falcon, 0x010, 0xff); + + return 0; +} + +static void +nvkm_falcon_v1_disable(struct nvkm_falcon *falcon) +{ + /* disable IRQs and wait for any previous code to complete */ + nvkm_falcon_wr32(falcon, 0x014, 0xff); + falcon_v1_wait_idle(falcon); +} + +static const struct nvkm_falcon_func +nvkm_falcon_v1 = { + .load_imem = nvkm_falcon_v1_load_imem, + .load_dmem = nvkm_falcon_v1_load_dmem, + .read_dmem = nvkm_falcon_v1_read_dmem, + .bind_context = nvkm_falcon_v1_bind_context, + .start = nvkm_falcon_v1_start, + .wait_for_halt = nvkm_falcon_v1_wait_for_halt, + .clear_interrupt = nvkm_falcon_v1_clear_interrupt, + .enable = nvkm_falcon_v1_enable, + .disable = nvkm_falcon_v1_disable, + .set_start_addr = nvkm_falcon_v1_set_start_addr, +}; + +int +nvkm_falcon_v1_new(struct nvkm_subdev *owner, const char *name, u32 addr, + struct nvkm_falcon **pfalcon) +{ + struct nvkm_falcon *falcon; + if (!(falcon = *pfalcon = kzalloc(sizeof(*falcon), GFP_KERNEL))) + return -ENOMEM; + nvkm_falcon_ctor(&nvkm_falcon_v1, owner, name, addr, falcon); + return 0; +} -- cgit v1.1 From e72da6e04f739253b175cd87aab47337c4646a66 Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Tue, 13 Dec 2016 17:11:21 +0900 Subject: drm/nouveau/pmu: add nvkm_pmu_ctor() function Add a PMU constructor so implementations that extend the nvkm_pmu structure can have all base members properly initialized. Signed-off-by: Alexandre Courbot Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c | 17 ++++++++++++----- drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h | 2 ++ 2 files changed, 14 insertions(+), 5 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c index e611ce8..b7edde4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c @@ -129,15 +129,22 @@ nvkm_pmu = { }; int -nvkm_pmu_new_(const struct nvkm_pmu_func *func, struct nvkm_device *device, - int index, struct nvkm_pmu **ppmu) +nvkm_pmu_ctor(const struct nvkm_pmu_func *func, struct nvkm_device *device, + int index, struct nvkm_pmu *pmu) { - struct nvkm_pmu *pmu; - if (!(pmu = *ppmu = kzalloc(sizeof(*pmu), GFP_KERNEL))) - return -ENOMEM; nvkm_subdev_ctor(&nvkm_pmu, device, index, &pmu->subdev); pmu->func = func; INIT_WORK(&pmu->recv.work, nvkm_pmu_recv); init_waitqueue_head(&pmu->recv.wait); return 0; } + +int +nvkm_pmu_new_(const struct nvkm_pmu_func *func, struct nvkm_device *device, + int index, struct nvkm_pmu **ppmu) +{ + struct nvkm_pmu *pmu; + if (!(pmu = *ppmu = kzalloc(sizeof(*pmu), GFP_KERNEL))) + return -ENOMEM; + return nvkm_pmu_ctor(func, device, index, *ppmu); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h index 2e2179a..096cba0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h @@ -4,6 +4,8 @@ #include #include +int nvkm_pmu_ctor(const struct nvkm_pmu_func *, struct nvkm_device *, + int index, struct nvkm_pmu *); int nvkm_pmu_new_(const struct nvkm_pmu_func *, struct nvkm_device *, int index, struct nvkm_pmu **); -- cgit v1.1 From 1e2115d8c0c0da62405400316f5499d909e479bc Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Tue, 13 Dec 2016 17:11:20 +0900 Subject: drm/nouveau/pmu: instanciate the falcon in PMU device Have an instance of nvkm_falcon in the PMU structure, ready to be used by other subdevs (i.e. secboot). Signed-off-by: Alexandre Courbot Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h | 2 ++ drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c | 4 +++- 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h index f37538eb..6514d46 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h @@ -1,10 +1,12 @@ #ifndef __NVKM_PMU_H__ #define __NVKM_PMU_H__ #include +#include struct nvkm_pmu { const struct nvkm_pmu_func *func; struct nvkm_subdev subdev; + struct nvkm_falcon *falcon; struct { u32 base; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c index b7edde4..a73f690 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c @@ -116,6 +116,8 @@ nvkm_pmu_init(struct nvkm_subdev *subdev) static void * nvkm_pmu_dtor(struct nvkm_subdev *subdev) { + struct nvkm_pmu *pmu = nvkm_pmu(subdev); + nvkm_falcon_del(&pmu->falcon); return nvkm_pmu(subdev); } @@ -136,7 +138,7 @@ nvkm_pmu_ctor(const struct nvkm_pmu_func *func, struct nvkm_device *device, pmu->func = func; INIT_WORK(&pmu->recv.work, nvkm_pmu_recv); init_waitqueue_head(&pmu->recv.wait); - return 0; + return nvkm_falcon_v1_new(&pmu->subdev, "PMU", 0x10a000, &pmu->falcon); } int -- cgit v1.1 From d8711c5a9cfd6b06d611a64a30ae3e98ef4e6962 Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Tue, 13 Dec 2016 17:11:22 +0900 Subject: drm/nouveau/pmu/gk20a: use nvkm_pmu_ctor() Use the PMU constructor so that all base members (in particular the falcon instance) are initialized properly. Signed-off-by: Alexandre Courbot Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c | 35 ++++++++++--------------- 1 file changed, 14 insertions(+), 21 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c index f996d90..e897bbd 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c @@ -19,7 +19,7 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ -#define gk20a_pmu(p) container_of((p), struct gk20a_pmu, base.subdev) +#define gk20a_pmu(p) container_of((p), struct gk20a_pmu, base) #include "priv.h" #include @@ -166,32 +166,25 @@ resched: nvkm_timer_alarm(tmr, 100000000, alarm); } -static int -gk20a_pmu_fini(struct nvkm_subdev *subdev, bool suspend) -{ - struct gk20a_pmu *pmu = gk20a_pmu(subdev); - nvkm_timer_alarm_cancel(subdev->device->timer, &pmu->alarm); - return 0; -} - -static void * -gk20a_pmu_dtor(struct nvkm_subdev *subdev) +static void +gk20a_pmu_fini(struct nvkm_pmu *pmu) { - return gk20a_pmu(subdev); + struct gk20a_pmu *gpmu = gk20a_pmu(pmu); + nvkm_timer_alarm_cancel(pmu->subdev.device->timer, &gpmu->alarm); } static int -gk20a_pmu_init(struct nvkm_subdev *subdev) +gk20a_pmu_init(struct nvkm_pmu *pmu) { - struct gk20a_pmu *pmu = gk20a_pmu(subdev); - struct nvkm_device *device = pmu->base.subdev.device; + struct gk20a_pmu *gpmu = gk20a_pmu(pmu); + struct nvkm_device *device = pmu->subdev.device; /* init pwr perf counter */ nvkm_wr32(device, 0x10a504 + (BUSY_SLOT * 0x10), 0x00200001); nvkm_wr32(device, 0x10a50c + (BUSY_SLOT * 0x10), 0x00000002); nvkm_wr32(device, 0x10a50c + (CLK_SLOT * 0x10), 0x00000003); - nvkm_timer_alarm(device->timer, 2000000000, &pmu->alarm); + nvkm_timer_alarm(device->timer, 2000000000, &gpmu->alarm); return 0; } @@ -202,26 +195,26 @@ gk20a_dvfs_data= { .p_smooth = 1, }; -static const struct nvkm_subdev_func +static const struct nvkm_pmu_func gk20a_pmu = { .init = gk20a_pmu_init, .fini = gk20a_pmu_fini, - .dtor = gk20a_pmu_dtor, + .reset = gt215_pmu_reset, }; int gk20a_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu) { - static const struct nvkm_pmu_func func = {}; struct gk20a_pmu *pmu; if (!(pmu = kzalloc(sizeof(*pmu), GFP_KERNEL))) return -ENOMEM; - pmu->base.func = &func; *ppmu = &pmu->base; - nvkm_subdev_ctor(&gk20a_pmu, device, index, &pmu->base.subdev); + nvkm_pmu_ctor(&gk20a_pmu, device, index, &pmu->base); + pmu->data = &gk20a_dvfs_data; nvkm_alarm_init(&pmu->alarm, gk20a_pmu_dvfs_work); + return 0; } -- cgit v1.1 From 68d82161fdab51f44767bcde801fd6a58bef9548 Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Tue, 13 Dec 2016 17:11:23 +0900 Subject: drm/nouveau/pmu/gk20a: simplify code a bit Some functions always succeed - change their return type to void and remove the error-handling code in their caller. Signed-off-by: Alexandre Courbot Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c | 30 +++++++------------------ 1 file changed, 8 insertions(+), 22 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c index e897bbd..4a0f809 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c @@ -43,9 +43,8 @@ struct gk20a_pmu { }; struct gk20a_pmu_dvfs_dev_status { - unsigned long total; - unsigned long busy; - int cur_state; + u32 total; + u32 busy; }; static int @@ -56,13 +55,12 @@ gk20a_pmu_dvfs_target(struct gk20a_pmu *pmu, int *state) return nvkm_clk_astate(clk, *state, 0, false); } -static int +static void gk20a_pmu_dvfs_get_cur_state(struct gk20a_pmu *pmu, int *state) { struct nvkm_clk *clk = pmu->base.subdev.device->clk; *state = clk->pstate; - return 0; } static int @@ -90,20 +88,16 @@ gk20a_pmu_dvfs_get_target_state(struct gk20a_pmu *pmu, *state = level; - if (level == cur_level) - return 0; - else - return 1; + return (level != cur_level); } -static int +static void gk20a_pmu_dvfs_get_dev_status(struct gk20a_pmu *pmu, struct gk20a_pmu_dvfs_dev_status *status) { struct nvkm_device *device = pmu->base.subdev.device; status->busy = nvkm_rd32(device, 0x10a508 + (BUSY_SLOT * 0x10)); status->total= nvkm_rd32(device, 0x10a508 + (CLK_SLOT * 0x10)); - return 0; } static void @@ -127,7 +121,7 @@ gk20a_pmu_dvfs_work(struct nvkm_alarm *alarm) struct nvkm_timer *tmr = device->timer; struct nvkm_volt *volt = device->volt; u32 utilization = 0; - int state, ret; + int state; /* * The PMU is initialized before CLK and VOLT, so we have to make sure the @@ -136,11 +130,7 @@ gk20a_pmu_dvfs_work(struct nvkm_alarm *alarm) if (!clk || !volt) goto resched; - ret = gk20a_pmu_dvfs_get_dev_status(pmu, &status); - if (ret) { - nvkm_warn(subdev, "failed to get device status\n"); - goto resched; - } + gk20a_pmu_dvfs_get_dev_status(pmu, &status); if (status.total) utilization = div_u64((u64)status.busy * 100, status.total); @@ -150,11 +140,7 @@ gk20a_pmu_dvfs_work(struct nvkm_alarm *alarm) nvkm_trace(subdev, "utilization = %d %%, avg_load = %d %%\n", utilization, data->avg_load); - ret = gk20a_pmu_dvfs_get_cur_state(pmu, &state); - if (ret) { - nvkm_warn(subdev, "failed to get current state\n"); - goto resched; - } + gk20a_pmu_dvfs_get_cur_state(pmu, &state); if (gk20a_pmu_dvfs_get_target_state(pmu, &state, data->avg_load)) { nvkm_trace(subdev, "set new state to %d\n", state); -- cgit v1.1 From 9b071c7935f053bf05ab4d0b2f4a8ae4069b4b89 Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Tue, 13 Dec 2016 17:11:24 +0900 Subject: drm/nouveau/pmu/gk20a: use falcon library functions Use the falcon library functions where relevant. Signed-off-by: Alexandre Courbot Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c | 31 ++++++++++++++++++------- 1 file changed, 22 insertions(+), 9 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c index 4a0f809..9ca0db7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c @@ -95,17 +95,19 @@ static void gk20a_pmu_dvfs_get_dev_status(struct gk20a_pmu *pmu, struct gk20a_pmu_dvfs_dev_status *status) { - struct nvkm_device *device = pmu->base.subdev.device; - status->busy = nvkm_rd32(device, 0x10a508 + (BUSY_SLOT * 0x10)); - status->total= nvkm_rd32(device, 0x10a508 + (CLK_SLOT * 0x10)); + struct nvkm_falcon *falcon = pmu->base.falcon; + + status->busy = nvkm_falcon_rd32(falcon, 0x508 + (BUSY_SLOT * 0x10)); + status->total= nvkm_falcon_rd32(falcon, 0x508 + (CLK_SLOT * 0x10)); } static void gk20a_pmu_dvfs_reset_dev_status(struct gk20a_pmu *pmu) { - struct nvkm_device *device = pmu->base.subdev.device; - nvkm_wr32(device, 0x10a508 + (BUSY_SLOT * 0x10), 0x80000000); - nvkm_wr32(device, 0x10a508 + (CLK_SLOT * 0x10), 0x80000000); + struct nvkm_falcon *falcon = pmu->base.falcon; + + nvkm_falcon_wr32(falcon, 0x508 + (BUSY_SLOT * 0x10), 0x80000000); + nvkm_falcon_wr32(falcon, 0x508 + (CLK_SLOT * 0x10), 0x80000000); } static void @@ -157,18 +159,29 @@ gk20a_pmu_fini(struct nvkm_pmu *pmu) { struct gk20a_pmu *gpmu = gk20a_pmu(pmu); nvkm_timer_alarm_cancel(pmu->subdev.device->timer, &gpmu->alarm); + + nvkm_falcon_put(pmu->falcon, &pmu->subdev); } static int gk20a_pmu_init(struct nvkm_pmu *pmu) { struct gk20a_pmu *gpmu = gk20a_pmu(pmu); + struct nvkm_subdev *subdev = &pmu->subdev; struct nvkm_device *device = pmu->subdev.device; + struct nvkm_falcon *falcon = pmu->falcon; + int ret; + + ret = nvkm_falcon_get(falcon, subdev); + if (ret) { + nvkm_error(subdev, "cannot acquire %s falcon!\n", falcon->name); + return ret; + } /* init pwr perf counter */ - nvkm_wr32(device, 0x10a504 + (BUSY_SLOT * 0x10), 0x00200001); - nvkm_wr32(device, 0x10a50c + (BUSY_SLOT * 0x10), 0x00000002); - nvkm_wr32(device, 0x10a50c + (CLK_SLOT * 0x10), 0x00000003); + nvkm_falcon_wr32(falcon, 0x504 + (BUSY_SLOT * 0x10), 0x00200001); + nvkm_falcon_wr32(falcon, 0x50c + (BUSY_SLOT * 0x10), 0x00000002); + nvkm_falcon_wr32(falcon, 0x50c + (CLK_SLOT * 0x10), 0x00000003); nvkm_timer_alarm(device->timer, 2000000000, &gpmu->alarm); return 0; -- cgit v1.1 From b1c39d801ad0f87bb4429f92392bea18c62a23cf Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Tue, 13 Dec 2016 17:11:25 +0900 Subject: drm/nouveau/gm20b: add dummy PMU device Add a dummy PMU device so the PMU falcon is instanciated and can be used by secure boot. We could reuse gk20a's implementation here, but it would fight with secboot over PMU falcon's ownership and secboot will reset the PMU, preventing it from operating afterwards. Proper handout between secboot and pmu is coming along with the actual gm20b PMU implementation, so use this as a temporary solution. Signed-off-by: Alexandre Courbot Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h | 1 + drivers/gpu/drm/nouveau/nvkm/engine/device/base.c | 1 + drivers/gpu/drm/nouveau/nvkm/subdev/pmu/Kbuild | 1 + drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c | 34 +++++++++++++++++++++++ 4 files changed, 37 insertions(+) create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h index 6514d46..179b6ed 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h @@ -37,6 +37,7 @@ int gk110_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); int gk208_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); int gk20a_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); int gm107_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); +int gm20b_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); int gp100_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); int gp102_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index cceda959..7079612 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -2138,6 +2138,7 @@ nv12b_chipset = { .ltc = gm200_ltc_new, .mc = gk20a_mc_new, .mmu = gf100_mmu_new, + .pmu = gm20b_pmu_new, .secboot = gm20b_secboot_new, .timer = gk20a_timer_new, .top = gk104_top_new, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/Kbuild index 51fb4bf..ca57c1e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/Kbuild @@ -8,5 +8,6 @@ nvkm-y += nvkm/subdev/pmu/gk110.o nvkm-y += nvkm/subdev/pmu/gk208.o nvkm-y += nvkm/subdev/pmu/gk20a.o nvkm-y += nvkm/subdev/pmu/gm107.o +nvkm-y += nvkm/subdev/pmu/gm20b.o nvkm-y += nvkm/subdev/pmu/gp100.o nvkm-y += nvkm/subdev/pmu/gp102.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c new file mode 100644 index 0000000..0b8a1cc --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "priv.h" + +static const struct nvkm_pmu_func +gm20b_pmu = { + .reset = gt215_pmu_reset, +}; + +int +gm20b_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu) +{ + return nvkm_pmu_new_(&gm20b_pmu, device, index, ppmu); +} -- cgit v1.1 From 236f4747915bbad4cd276654659870b081e882be Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Tue, 13 Dec 2016 17:11:26 +0900 Subject: drm/nouveau/secboot: fix functions definitions These functions should use the nvkm_secboot_falcon enum. Fix this. Signed-off-by: Alexandre Courbot Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvkm/subdev/secboot.h | 6 +++--- drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c | 4 ++-- drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h | 4 ++-- 3 files changed, 7 insertions(+), 7 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/secboot.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/secboot.h index b04c38c..781586b 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/secboot.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/secboot.h @@ -26,7 +26,7 @@ #include enum nvkm_secboot_falcon { - NVKM_SECBOOT_FALCON_PMU = 0, + NVKM_SECBOOT_FALCON_PMU = 0, NVKM_SECBOOT_FALCON_RESERVED = 1, NVKM_SECBOOT_FALCON_FECS = 2, NVKM_SECBOOT_FALCON_GPCCS = 3, @@ -49,8 +49,8 @@ struct nvkm_secboot { #define nvkm_secboot(p) container_of((p), struct nvkm_secboot, subdev) bool nvkm_secboot_is_managed(struct nvkm_secboot *, enum nvkm_secboot_falcon); -int nvkm_secboot_reset(struct nvkm_secboot *, u32 falcon); -int nvkm_secboot_start(struct nvkm_secboot *, u32 falcon); +int nvkm_secboot_reset(struct nvkm_secboot *, enum nvkm_secboot_falcon); +int nvkm_secboot_start(struct nvkm_secboot *, enum nvkm_secboot_falcon); int gm200_secboot_new(struct nvkm_device *, int, struct nvkm_secboot **); int gm20b_secboot_new(struct nvkm_device *, int, struct nvkm_secboot **); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c index 314be21..6ee140e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c @@ -160,7 +160,7 @@ nvkm_secboot_falcon_run(struct nvkm_secboot *sb) * nvkm_secboot_reset() - reset specified falcon */ int -nvkm_secboot_reset(struct nvkm_secboot *sb, u32 falcon) +nvkm_secboot_reset(struct nvkm_secboot *sb, enum nvkm_secboot_falcon falcon) { /* Unmanaged falcon? */ if (!(BIT(falcon) & sb->func->managed_falcons)) { @@ -175,7 +175,7 @@ nvkm_secboot_reset(struct nvkm_secboot *sb, u32 falcon) * nvkm_secboot_start() - start specified falcon */ int -nvkm_secboot_start(struct nvkm_secboot *sb, u32 falcon) +nvkm_secboot_start(struct nvkm_secboot *sb, enum nvkm_secboot_falcon falcon) { /* Unmanaged falcon? */ if (!(BIT(falcon) & sb->func->managed_falcons)) { diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h index a9a8a0e..2ad6d62 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h @@ -226,8 +226,8 @@ struct gm200_secboot_func { int gm200_secboot_init(struct nvkm_secboot *); void *gm200_secboot_dtor(struct nvkm_secboot *); -int gm200_secboot_reset(struct nvkm_secboot *, u32); -int gm200_secboot_start(struct nvkm_secboot *, u32); +int gm200_secboot_reset(struct nvkm_secboot *, enum nvkm_secboot_falcon); +int gm200_secboot_start(struct nvkm_secboot *, enum nvkm_secboot_falcon); int gm20x_secboot_prepare_blobs(struct gm200_secboot *); -- cgit v1.1 From d72fb36c45698b9f49a1159eb1a3eb46235d3586 Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Tue, 13 Dec 2016 17:11:27 +0900 Subject: drm/nouveau/secboot: use falcon library Use the falcon library functions in secure boot. This removes a lot of code and makes the secure boot flow easier to understand as no register is directly accessed. Signed-off-by: Alexandre Courbot Signed-off-by: Ben Skeggs --- .../gpu/drm/nouveau/include/nvkm/subdev/secboot.h | 4 +- drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c | 146 ++------------------- .../gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c | 125 ++++++------------ drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h | 2 - 4 files changed, 51 insertions(+), 226 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/secboot.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/secboot.h index 781586b..2a2f651 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/secboot.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/secboot.h @@ -42,9 +42,7 @@ enum nvkm_secboot_falcon { struct nvkm_secboot { const struct nvkm_secboot_func *func; struct nvkm_subdev subdev; - - enum nvkm_devidx devidx; - u32 base; + struct nvkm_falcon *boot_falcon; }; #define nvkm_secboot(p) container_of((p), struct nvkm_secboot, subdev) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c index 6ee140e..a6e18ef 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c @@ -23,6 +23,7 @@ #include #include +#include static const char * managed_falcons_names[] = { @@ -32,130 +33,6 @@ managed_falcons_names[] = { [NVKM_SECBOOT_FALCON_GPCCS] = "GPCCS", [NVKM_SECBOOT_FALCON_END] = "", }; - -/* - * Helper falcon functions - */ - -static int -falcon_clear_halt_interrupt(struct nvkm_device *device, u32 base) -{ - int ret; - - /* clear halt interrupt */ - nvkm_mask(device, base + 0x004, 0x10, 0x10); - /* wait until halt interrupt is cleared */ - ret = nvkm_wait_msec(device, 10, base + 0x008, 0x10, 0x0); - if (ret < 0) - return ret; - - return 0; -} - -static int -falcon_wait_idle(struct nvkm_device *device, u32 base) -{ - int ret; - - ret = nvkm_wait_msec(device, 10, base + 0x04c, 0xffff, 0x0); - if (ret < 0) - return ret; - - return 0; -} - -static int -nvkm_secboot_falcon_enable(struct nvkm_secboot *sb) -{ - struct nvkm_device *device = sb->subdev.device; - int ret; - - /* enable engine */ - nvkm_mc_enable(device, sb->devidx); - ret = nvkm_wait_msec(device, 10, sb->base + 0x10c, 0x6, 0x0); - if (ret < 0) { - nvkm_error(&sb->subdev, "Falcon mem scrubbing timeout\n"); - nvkm_mc_disable(device, sb->devidx); - return ret; - } - - ret = falcon_wait_idle(device, sb->base); - if (ret) - return ret; - - /* enable IRQs */ - nvkm_wr32(device, sb->base + 0x010, 0xff); - nvkm_mc_intr_mask(device, sb->devidx, true); - - return 0; -} - -static int -nvkm_secboot_falcon_disable(struct nvkm_secboot *sb) -{ - struct nvkm_device *device = sb->subdev.device; - - /* disable IRQs and wait for any previous code to complete */ - nvkm_mc_intr_mask(device, sb->devidx, false); - nvkm_wr32(device, sb->base + 0x014, 0xff); - - falcon_wait_idle(device, sb->base); - - /* disable engine */ - nvkm_mc_disable(device, sb->devidx); - - return 0; -} - -int -nvkm_secboot_falcon_reset(struct nvkm_secboot *sb) -{ - int ret; - - ret = nvkm_secboot_falcon_disable(sb); - if (ret) - return ret; - - ret = nvkm_secboot_falcon_enable(sb); - if (ret) - return ret; - - return 0; -} - -/** - * nvkm_secboot_falcon_run - run the falcon that will perform secure boot - * - * This function is to be called after all chip-specific preparations have - * been completed. It will start the falcon to perform secure boot, wait for - * it to halt, and report if an error occurred. - */ -int -nvkm_secboot_falcon_run(struct nvkm_secboot *sb) -{ - struct nvkm_device *device = sb->subdev.device; - int ret; - - /* Start falcon */ - nvkm_wr32(device, sb->base + 0x100, 0x2); - - /* Wait for falcon halt */ - ret = nvkm_wait_msec(device, 100, sb->base + 0x100, 0x10, 0x10); - if (ret < 0) - return ret; - - /* If mailbox register contains an error code, then ACR has failed */ - ret = nvkm_rd32(device, sb->base + 0x040); - if (ret) { - nvkm_error(&sb->subdev, "ACR boot failed, ret 0x%08x", ret); - falcon_clear_halt_interrupt(device, sb->base); - return -EINVAL; - } - - return 0; -} - - /** * nvkm_secboot_reset() - reset specified falcon */ @@ -205,6 +82,16 @@ nvkm_secboot_oneinit(struct nvkm_subdev *subdev) struct nvkm_secboot *sb = nvkm_secboot(subdev); int ret = 0; + switch (sb->func->boot_falcon) { + case NVKM_SECBOOT_FALCON_PMU: + sb->boot_falcon = subdev->device->pmu->falcon; + break; + default: + nvkm_error(subdev, "Unmanaged boot falcon %s!\n", + managed_falcons_names[sb->func->boot_falcon]); + return -EINVAL; + } + /* Call chip-specific init function */ if (sb->func->init) ret = sb->func->init(sb); @@ -258,17 +145,6 @@ nvkm_secboot_ctor(const struct nvkm_secboot_func *func, nvkm_subdev_ctor(&nvkm_secboot, device, index, &sb->subdev); sb->func = func; - /* setup the performing falcon's base address and masks */ - switch (func->boot_falcon) { - case NVKM_SECBOOT_FALCON_PMU: - sb->devidx = NVKM_SUBDEV_PMU; - sb->base = 0x10a000; - break; - default: - nvkm_error(&sb->subdev, "invalid secure boot falcon\n"); - return -EINVAL; - }; - nvkm_debug(&sb->subdev, "securely managed falcons:\n"); for_each_set_bit(fid, &sb->func->managed_falcons, NVKM_SECBOOT_FALCON_END) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c index ec48e4a..a2a33f1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c @@ -86,14 +86,7 @@ #include #include #include - -enum { - FALCON_DMAIDX_UCODE = 0, - FALCON_DMAIDX_VIRT = 1, - FALCON_DMAIDX_PHYS_VID = 2, - FALCON_DMAIDX_PHYS_SYS_COH = 3, - FALCON_DMAIDX_PHYS_SYS_NCOH = 4, -}; +#include /** * struct fw_bin_header - header of firmware files @@ -887,7 +880,7 @@ gm200_secboot_hsf_patch_signature(struct gm200_secboot *gsb, void *acr_image) u32 sig_size; /* Falcon in debug or production mode? */ - if ((nvkm_rd32(sb->subdev.device, sb->base + 0xc08) >> 20) & 0x1) { + if (sb->boot_falcon->debug) { sig = acr_image + fw_hdr->sig_dbg_offset; sig_size = fw_hdr->sig_dbg_size; } else { @@ -1101,96 +1094,33 @@ gm200_secboot_blobs_ready(struct gm200_secboot *gsb) * gm200_secboot_load_hs_bl() - load HS bootloader into DMEM and IMEM */ static void -gm200_secboot_load_hs_bl(struct gm200_secboot *gsb, void *data, u32 data_size) +gm200_secboot_load_hs_bl(struct gm200_secboot *gsb, struct nvkm_falcon *falcon, + void *data, u32 data_size) { - struct nvkm_device *device = gsb->base.subdev.device; struct fw_bin_header *hdr = gsb->hsbl_blob; struct fw_bl_desc *hsbl_desc = gsb->hsbl_blob + hdr->header_offset; void *blob_data = gsb->hsbl_blob + hdr->data_offset; void *hsbl_code = blob_data + hsbl_desc->code_off; void *hsbl_data = blob_data + hsbl_desc->data_off; u32 code_size = ALIGN(hsbl_desc->code_size, 256); - const u32 base = gsb->base.base; - u32 blk; u32 tag; - int i; /* * Copy HS bootloader data */ - nvkm_wr32(device, base + 0x1c0, (0x00000000 | (0x1 << 24))); - for (i = 0; i < hsbl_desc->data_size / 4; i++) - nvkm_wr32(device, base + 0x1c4, ((u32 *)hsbl_data)[i]); + nvkm_falcon_load_dmem(falcon, hsbl_data, 0x0, hsbl_desc->data_size, 0); /* * Copy HS bootloader interface structure where the HS descriptor * expects it to be */ - nvkm_wr32(device, base + 0x1c0, - (hsbl_desc->dmem_load_off | (0x1 << 24))); - for (i = 0; i < data_size / 4; i++) - nvkm_wr32(device, base + 0x1c4, ((u32 *)data)[i]); + nvkm_falcon_load_dmem(falcon, data, hsbl_desc->dmem_load_off, data_size, + 0); /* Copy HS bootloader code to end of IMEM */ - blk = (nvkm_rd32(device, base + 0x108) & 0x1ff) - (code_size >> 8); tag = hsbl_desc->start_tag; - nvkm_wr32(device, base + 0x180, ((blk & 0xff) << 8) | (0x1 << 24)); - for (i = 0; i < code_size / 4; i++) { - /* write new tag every 256B */ - if ((i & 0x3f) == 0) { - nvkm_wr32(device, base + 0x188, tag & 0xffff); - tag++; - } - nvkm_wr32(device, base + 0x184, ((u32 *)hsbl_code)[i]); - } - nvkm_wr32(device, base + 0x188, 0); -} - -/** - * gm200_secboot_setup_falcon() - set up the secure falcon for secure boot - */ -static int -gm200_secboot_setup_falcon(struct gm200_secboot *gsb) -{ - struct nvkm_device *device = gsb->base.subdev.device; - struct fw_bin_header *hdr = gsb->hsbl_blob; - struct fw_bl_desc *hsbl_desc = gsb->hsbl_blob + hdr->header_offset; - /* virtual start address for boot vector */ - u32 virt_addr = hsbl_desc->start_tag << 8; - const u32 base = gsb->base.base; - const u32 reg_base = base + 0xe00; - u32 inst_loc; - int ret; - - ret = nvkm_secboot_falcon_reset(&gsb->base); - if (ret) - return ret; - - /* setup apertures - virtual */ - nvkm_wr32(device, reg_base + 4 * (FALCON_DMAIDX_UCODE), 0x4); - nvkm_wr32(device, reg_base + 4 * (FALCON_DMAIDX_VIRT), 0x0); - /* setup apertures - physical */ - nvkm_wr32(device, reg_base + 4 * (FALCON_DMAIDX_PHYS_VID), 0x4); - nvkm_wr32(device, reg_base + 4 * (FALCON_DMAIDX_PHYS_SYS_COH), - 0x4 | 0x1); - nvkm_wr32(device, reg_base + 4 * (FALCON_DMAIDX_PHYS_SYS_NCOH), - 0x4 | 0x2); - - /* Set context */ - if (nvkm_memory_target(gsb->inst->memory) == NVKM_MEM_TARGET_VRAM) - inst_loc = 0x0; /* FB */ - else - inst_loc = 0x3; /* Non-coherent sysmem */ - - nvkm_mask(device, base + 0x048, 0x1, 0x1); - nvkm_wr32(device, base + 0x480, - ((gsb->inst->addr >> 12) & 0xfffffff) | - (inst_loc << 28) | (1 << 30)); - - /* Set boot vector to code's starting virtual address */ - nvkm_wr32(device, base + 0x104, virt_addr); - - return 0; + nvkm_falcon_load_imem(falcon, hsbl_code, falcon->code.limit - code_size, + code_size, tag, 0, false); } /** @@ -1200,16 +1130,27 @@ static int gm200_secboot_run_hs_blob(struct gm200_secboot *gsb, struct nvkm_gpuobj *blob, struct gm200_flcn_bl_desc *desc) { - struct nvkm_vma vma; - u64 vma_addr; + struct nvkm_subdev *subdev = &gsb->base.subdev; + struct fw_bin_header *hdr = gsb->hsbl_blob; + struct fw_bl_desc *hsbl_desc = gsb->hsbl_blob + hdr->header_offset; + struct nvkm_falcon *falcon = gsb->base.boot_falcon; + const u32 virt_addr = hsbl_desc->start_tag << 8; const u32 bl_desc_size = gsb->func->bl_desc_size; u8 bl_desc[bl_desc_size]; + struct nvkm_vma vma; + u64 vma_addr; int ret; + ret = nvkm_falcon_get(falcon, subdev); + if (ret) + return ret; + /* Map the HS firmware so the HS bootloader can see it */ ret = nvkm_gpuobj_map(blob, gsb->vm, NV_MEM_ACCESS_RW, &vma); - if (ret) + if (ret) { + nvkm_falcon_put(falcon, subdev); return ret; + } /* Add the mapping address to the DMA bases */ vma_addr = flcn64_to_u64(desc->code_dma_base) + vma.offset; @@ -1222,19 +1163,30 @@ gm200_secboot_run_hs_blob(struct gm200_secboot *gsb, struct nvkm_gpuobj *blob, /* Fixup the BL header */ gsb->func->fixup_bl_desc(desc, &bl_desc); - /* Reset the falcon and make it ready to run the HS bootloader */ - ret = gm200_secboot_setup_falcon(gsb); + /* Reset and set the falcon up */ + ret = nvkm_falcon_reset(falcon); if (ret) goto done; + nvkm_falcon_bind_context(falcon, gsb->inst); /* Load the HS bootloader into the falcon's IMEM/DMEM */ - gm200_secboot_load_hs_bl(gsb, &bl_desc, bl_desc_size); + gm200_secboot_load_hs_bl(gsb, falcon, &bl_desc, bl_desc_size); /* Start the HS bootloader */ - ret = nvkm_secboot_falcon_run(&gsb->base); + nvkm_falcon_set_start_addr(falcon, virt_addr); + nvkm_falcon_start(falcon); + ret = nvkm_falcon_wait_for_halt(falcon, 100); if (ret) goto done; + /* If mailbox register contains an error code, then ACR has failed */ + ret = nvkm_falcon_rd32(falcon, 0x040); + if (ret) { + nvkm_error(subdev, "ACR boot failed, ret 0x%08x", ret); + ret = -EINVAL; + goto done; + } + done: /* Restore the original DMA addresses */ vma_addr = flcn64_to_u64(desc->code_dma_base) - vma.offset; @@ -1246,6 +1198,7 @@ done: /* We don't need the ACR firmware anymore */ nvkm_gpuobj_unmap(&vma); + nvkm_falcon_put(falcon, subdev); return ret; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h index 2ad6d62..4b090d2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h @@ -41,8 +41,6 @@ struct nvkm_secboot_func { int nvkm_secboot_ctor(const struct nvkm_secboot_func *, struct nvkm_device *, int index, struct nvkm_secboot *); -int nvkm_secboot_falcon_reset(struct nvkm_secboot *); -int nvkm_secboot_falcon_run(struct nvkm_secboot *); struct flcn_u64 { u32 lo; -- cgit v1.1 From d2753f40a947229cf2c8075ed93479159c1af1c1 Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Tue, 13 Dec 2016 17:11:28 +0900 Subject: drm/nouveau/gr: add fini() hook Add a fini() hook to the GR engine. This will be used by gf100+ to properly release the FECS and GPCCS falcons. Signed-off-by: Alexandre Courbot Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c | 10 ++++++++++ drivers/gpu/drm/nouveau/nvkm/engine/gr/priv.h | 1 + 2 files changed, 11 insertions(+) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c index 467065d..a8282ed 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c @@ -106,6 +106,15 @@ nvkm_gr_init(struct nvkm_engine *engine) return gr->func->init(gr); } +static int +nvkm_gr_fini(struct nvkm_engine *engine, bool suspend) +{ + struct nvkm_gr *gr = nvkm_gr(engine); + if (gr->func->fini) + return gr->func->fini(gr, suspend); + return 0; +} + static void * nvkm_gr_dtor(struct nvkm_engine *engine) { @@ -120,6 +129,7 @@ nvkm_gr = { .dtor = nvkm_gr_dtor, .oneinit = nvkm_gr_oneinit, .init = nvkm_gr_init, + .fini = nvkm_gr_fini, .intr = nvkm_gr_intr, .tile = nvkm_gr_tile, .fifo.cclass = nvkm_gr_cclass_new, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/priv.h index d8adcdf..0d6d940 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/priv.h @@ -15,6 +15,7 @@ struct nvkm_gr_func { void *(*dtor)(struct nvkm_gr *); int (*oneinit)(struct nvkm_gr *); int (*init)(struct nvkm_gr *); + int (*fini)(struct nvkm_gr *, bool); void (*intr)(struct nvkm_gr *); void (*tile)(struct nvkm_gr *, int region, struct nvkm_fb_tile *); int (*tlb_flush)(struct nvkm_gr *); -- cgit v1.1 From 0296b5d985a030a99dcf2057b5eac1461637c7ee Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Tue, 13 Dec 2016 17:11:29 +0900 Subject: drm/nouveau/gr/gf100: split gf100_gr_init_ctxctl() gf100_gr_init_ctxctl() is basically two different functions (one for use of internal firmware, the other for use of external firmware), but its current layout makes it look more complex than it is. Split it to better reflect that fact. Signed-off-by: Alexandre Courbot Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c | 212 ++++++++++++++----------- 1 file changed, 115 insertions(+), 97 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c index f65a5b0..7cf1492 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c @@ -1455,134 +1455,139 @@ gf100_gr_init_csdata(struct gf100_gr *gr, nvkm_wr32(device, falcon + 0x01c4, star + 4); } -int -gf100_gr_init_ctxctl(struct gf100_gr *gr) +/* Initialize context from an external (secure or not) firmware */ +static int +gf100_gr_init_ctxctl_ext(struct gf100_gr *gr) { - const struct gf100_grctx_func *grctx = gr->func->grctx; struct nvkm_subdev *subdev = &gr->base.engine.subdev; struct nvkm_device *device = subdev->device; struct nvkm_secboot *sb = device->secboot; - int i; int ret = 0; - if (gr->firmware) { - /* load fuc microcode */ - nvkm_mc_unk260(device, 0); - - /* securely-managed falcons must be reset using secure boot */ - if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_FECS)) - ret = nvkm_secboot_reset(sb, NVKM_SECBOOT_FALCON_FECS); - else - gf100_gr_init_fw(gr, 0x409000, &gr->fuc409c, - &gr->fuc409d); - if (ret) - return ret; + /* load fuc microcode */ + nvkm_mc_unk260(device, 0); - if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_GPCCS)) - ret = nvkm_secboot_reset(sb, NVKM_SECBOOT_FALCON_GPCCS); - else - gf100_gr_init_fw(gr, 0x41a000, &gr->fuc41ac, - &gr->fuc41ad); - if (ret) - return ret; + /* securely-managed falcons must be reset using secure boot */ + if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_FECS)) + ret = nvkm_secboot_reset(sb, NVKM_SECBOOT_FALCON_FECS); + else + gf100_gr_init_fw(gr, 0x409000, &gr->fuc409c, &gr->fuc409d); + if (ret) + return ret; - nvkm_mc_unk260(device, 1); - - /* start both of them running */ - nvkm_wr32(device, 0x409840, 0xffffffff); - nvkm_wr32(device, 0x41a10c, 0x00000000); - nvkm_wr32(device, 0x40910c, 0x00000000); - - if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_GPCCS)) - nvkm_secboot_start(sb, NVKM_SECBOOT_FALCON_GPCCS); - else - nvkm_wr32(device, 0x41a100, 0x00000002); - if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_FECS)) - nvkm_secboot_start(sb, NVKM_SECBOOT_FALCON_FECS); - else - nvkm_wr32(device, 0x409100, 0x00000002); - if (nvkm_msec(device, 2000, - if (nvkm_rd32(device, 0x409800) & 0x00000001) - break; - ) < 0) - return -EBUSY; + if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_GPCCS)) + ret = nvkm_secboot_reset(sb, NVKM_SECBOOT_FALCON_GPCCS); + else + gf100_gr_init_fw(gr, 0x41a000, &gr->fuc41ac, &gr->fuc41ad); + if (ret) + return ret; - nvkm_wr32(device, 0x409840, 0xffffffff); - nvkm_wr32(device, 0x409500, 0x7fffffff); - nvkm_wr32(device, 0x409504, 0x00000021); + nvkm_mc_unk260(device, 1); + + /* start both of them running */ + nvkm_wr32(device, 0x409840, 0xffffffff); + nvkm_wr32(device, 0x41a10c, 0x00000000); + nvkm_wr32(device, 0x40910c, 0x00000000); - nvkm_wr32(device, 0x409840, 0xffffffff); - nvkm_wr32(device, 0x409500, 0x00000000); - nvkm_wr32(device, 0x409504, 0x00000010); + if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_GPCCS)) + nvkm_secboot_start(sb, NVKM_SECBOOT_FALCON_GPCCS); + else + nvkm_wr32(device, 0x41a100, 0x00000002); + if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_FECS)) + nvkm_secboot_start(sb, NVKM_SECBOOT_FALCON_FECS); + else + nvkm_wr32(device, 0x409100, 0x00000002); + if (nvkm_msec(device, 2000, + if (nvkm_rd32(device, 0x409800) & 0x00000001) + break; + ) < 0) + return -EBUSY; + + nvkm_wr32(device, 0x409840, 0xffffffff); + nvkm_wr32(device, 0x409500, 0x7fffffff); + nvkm_wr32(device, 0x409504, 0x00000021); + + nvkm_wr32(device, 0x409840, 0xffffffff); + nvkm_wr32(device, 0x409500, 0x00000000); + nvkm_wr32(device, 0x409504, 0x00000010); + if (nvkm_msec(device, 2000, + if ((gr->size = nvkm_rd32(device, 0x409800))) + break; + ) < 0) + return -EBUSY; + + nvkm_wr32(device, 0x409840, 0xffffffff); + nvkm_wr32(device, 0x409500, 0x00000000); + nvkm_wr32(device, 0x409504, 0x00000016); + if (nvkm_msec(device, 2000, + if (nvkm_rd32(device, 0x409800)) + break; + ) < 0) + return -EBUSY; + + nvkm_wr32(device, 0x409840, 0xffffffff); + nvkm_wr32(device, 0x409500, 0x00000000); + nvkm_wr32(device, 0x409504, 0x00000025); + if (nvkm_msec(device, 2000, + if (nvkm_rd32(device, 0x409800)) + break; + ) < 0) + return -EBUSY; + + if (device->chipset >= 0xe0) { + nvkm_wr32(device, 0x409800, 0x00000000); + nvkm_wr32(device, 0x409500, 0x00000001); + nvkm_wr32(device, 0x409504, 0x00000030); if (nvkm_msec(device, 2000, - if ((gr->size = nvkm_rd32(device, 0x409800))) + if (nvkm_rd32(device, 0x409800)) break; ) < 0) return -EBUSY; - nvkm_wr32(device, 0x409840, 0xffffffff); - nvkm_wr32(device, 0x409500, 0x00000000); - nvkm_wr32(device, 0x409504, 0x00000016); + nvkm_wr32(device, 0x409810, 0xb00095c8); + nvkm_wr32(device, 0x409800, 0x00000000); + nvkm_wr32(device, 0x409500, 0x00000001); + nvkm_wr32(device, 0x409504, 0x00000031); if (nvkm_msec(device, 2000, if (nvkm_rd32(device, 0x409800)) break; ) < 0) return -EBUSY; - nvkm_wr32(device, 0x409840, 0xffffffff); - nvkm_wr32(device, 0x409500, 0x00000000); - nvkm_wr32(device, 0x409504, 0x00000025); + nvkm_wr32(device, 0x409810, 0x00080420); + nvkm_wr32(device, 0x409800, 0x00000000); + nvkm_wr32(device, 0x409500, 0x00000001); + nvkm_wr32(device, 0x409504, 0x00000032); if (nvkm_msec(device, 2000, if (nvkm_rd32(device, 0x409800)) break; ) < 0) return -EBUSY; - if (device->chipset >= 0xe0) { - nvkm_wr32(device, 0x409800, 0x00000000); - nvkm_wr32(device, 0x409500, 0x00000001); - nvkm_wr32(device, 0x409504, 0x00000030); - if (nvkm_msec(device, 2000, - if (nvkm_rd32(device, 0x409800)) - break; - ) < 0) - return -EBUSY; - - nvkm_wr32(device, 0x409810, 0xb00095c8); - nvkm_wr32(device, 0x409800, 0x00000000); - nvkm_wr32(device, 0x409500, 0x00000001); - nvkm_wr32(device, 0x409504, 0x00000031); - if (nvkm_msec(device, 2000, - if (nvkm_rd32(device, 0x409800)) - break; - ) < 0) - return -EBUSY; - - nvkm_wr32(device, 0x409810, 0x00080420); - nvkm_wr32(device, 0x409800, 0x00000000); - nvkm_wr32(device, 0x409500, 0x00000001); - nvkm_wr32(device, 0x409504, 0x00000032); - if (nvkm_msec(device, 2000, - if (nvkm_rd32(device, 0x409800)) - break; - ) < 0) - return -EBUSY; + nvkm_wr32(device, 0x409614, 0x00000070); + nvkm_wr32(device, 0x409614, 0x00000770); + nvkm_wr32(device, 0x40802c, 0x00000001); + } - nvkm_wr32(device, 0x409614, 0x00000070); - nvkm_wr32(device, 0x409614, 0x00000770); - nvkm_wr32(device, 0x40802c, 0x00000001); + if (gr->data == NULL) { + int ret = gf100_grctx_generate(gr); + if (ret) { + nvkm_error(subdev, "failed to construct context\n"); + return ret; } + } - if (gr->data == NULL) { - int ret = gf100_grctx_generate(gr); - if (ret) { - nvkm_error(subdev, "failed to construct context\n"); - return ret; - } - } + return 0; +} + +static int +gf100_gr_init_ctxctl_int(struct gf100_gr *gr) +{ + const struct gf100_grctx_func *grctx = gr->func->grctx; + struct nvkm_subdev *subdev = &gr->base.engine.subdev; + struct nvkm_device *device = subdev->device; + int i; - return 0; - } else if (!gr->func->fecs.ucode) { return -ENOSYS; } @@ -1642,6 +1647,19 @@ gf100_gr_init_ctxctl(struct gf100_gr *gr) return 0; } +int +gf100_gr_init_ctxctl(struct gf100_gr *gr) +{ + int ret; + + if (gr->firmware) + ret = gf100_gr_init_ctxctl_ext(gr); + else + ret = gf100_gr_init_ctxctl_int(gr); + + return ret; +} + static int gf100_gr_oneinit(struct nvkm_gr *base) { -- cgit v1.1 From 89cd6e2071b3d3bc4635fe41461e2bb75b5f2d2d Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Tue, 13 Dec 2016 17:11:30 +0900 Subject: drm/nouveau/gr/gf100: instantiate and reserve GR falcons Create instances for the FECS and GPCCS falcons and use the init() and fini() hooks to reserve them for as long as GR controls them. Signed-off-by: Alexandre Courbot Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c | 98 +++++++++++++------------- drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h | 3 + 2 files changed, 51 insertions(+), 50 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c index 7cf1492..c0c25cf 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c @@ -1391,26 +1391,11 @@ gf100_gr_intr(struct nvkm_gr *base) } static void -gf100_gr_init_fw(struct gf100_gr *gr, u32 fuc_base, +gf100_gr_init_fw(struct nvkm_falcon *falcon, struct gf100_gr_fuc *code, struct gf100_gr_fuc *data) { - struct nvkm_device *device = gr->base.engine.subdev.device; - int i; - - nvkm_wr32(device, fuc_base + 0x01c0, 0x01000000); - for (i = 0; i < data->size / 4; i++) - nvkm_wr32(device, fuc_base + 0x01c4, data->data[i]); - - nvkm_wr32(device, fuc_base + 0x0180, 0x01000000); - for (i = 0; i < code->size / 4; i++) { - if ((i & 0x3f) == 0) - nvkm_wr32(device, fuc_base + 0x0188, i >> 6); - nvkm_wr32(device, fuc_base + 0x0184, code->data[i]); - } - - /* code must be padded to 0x40 words */ - for (; i & 0x3f; i++) - nvkm_wr32(device, fuc_base + 0x0184, 0); + nvkm_falcon_load_dmem(falcon, data->data, 0x0, data->size, 0); + nvkm_falcon_load_imem(falcon, code->data, 0x0, code->size, 0, 0, false); } static void @@ -1471,14 +1456,14 @@ gf100_gr_init_ctxctl_ext(struct gf100_gr *gr) if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_FECS)) ret = nvkm_secboot_reset(sb, NVKM_SECBOOT_FALCON_FECS); else - gf100_gr_init_fw(gr, 0x409000, &gr->fuc409c, &gr->fuc409d); + gf100_gr_init_fw(gr->fecs, &gr->fuc409c, &gr->fuc409d); if (ret) return ret; if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_GPCCS)) ret = nvkm_secboot_reset(sb, NVKM_SECBOOT_FALCON_GPCCS); else - gf100_gr_init_fw(gr, 0x41a000, &gr->fuc41ac, &gr->fuc41ad); + gf100_gr_init_fw(gr->gpccs, &gr->fuc41ac, &gr->fuc41ad); if (ret) return ret; @@ -1489,14 +1474,9 @@ gf100_gr_init_ctxctl_ext(struct gf100_gr *gr) nvkm_wr32(device, 0x41a10c, 0x00000000); nvkm_wr32(device, 0x40910c, 0x00000000); - if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_GPCCS)) - nvkm_secboot_start(sb, NVKM_SECBOOT_FALCON_GPCCS); - else - nvkm_wr32(device, 0x41a100, 0x00000002); - if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_FECS)) - nvkm_secboot_start(sb, NVKM_SECBOOT_FALCON_FECS); - else - nvkm_wr32(device, 0x409100, 0x00000002); + nvkm_falcon_start(gr->gpccs); + nvkm_falcon_start(gr->fecs); + if (nvkm_msec(device, 2000, if (nvkm_rd32(device, 0x409800) & 0x00000001) break; @@ -1586,7 +1566,6 @@ gf100_gr_init_ctxctl_int(struct gf100_gr *gr) const struct gf100_grctx_func *grctx = gr->func->grctx; struct nvkm_subdev *subdev = &gr->base.engine.subdev; struct nvkm_device *device = subdev->device; - int i; if (!gr->func->fecs.ucode) { return -ENOSYS; @@ -1594,28 +1573,16 @@ gf100_gr_init_ctxctl_int(struct gf100_gr *gr) /* load HUB microcode */ nvkm_mc_unk260(device, 0); - nvkm_wr32(device, 0x4091c0, 0x01000000); - for (i = 0; i < gr->func->fecs.ucode->data.size / 4; i++) - nvkm_wr32(device, 0x4091c4, gr->func->fecs.ucode->data.data[i]); - - nvkm_wr32(device, 0x409180, 0x01000000); - for (i = 0; i < gr->func->fecs.ucode->code.size / 4; i++) { - if ((i & 0x3f) == 0) - nvkm_wr32(device, 0x409188, i >> 6); - nvkm_wr32(device, 0x409184, gr->func->fecs.ucode->code.data[i]); - } + nvkm_falcon_load_dmem(gr->fecs, gr->func->fecs.ucode->data.data, 0x0, + gr->func->fecs.ucode->data.size, 0); + nvkm_falcon_load_imem(gr->fecs, gr->func->fecs.ucode->code.data, 0x0, + gr->func->fecs.ucode->code.size, 0, 0, false); /* load GPC microcode */ - nvkm_wr32(device, 0x41a1c0, 0x01000000); - for (i = 0; i < gr->func->gpccs.ucode->data.size / 4; i++) - nvkm_wr32(device, 0x41a1c4, gr->func->gpccs.ucode->data.data[i]); - - nvkm_wr32(device, 0x41a180, 0x01000000); - for (i = 0; i < gr->func->gpccs.ucode->code.size / 4; i++) { - if ((i & 0x3f) == 0) - nvkm_wr32(device, 0x41a188, i >> 6); - nvkm_wr32(device, 0x41a184, gr->func->gpccs.ucode->code.data[i]); - } + nvkm_falcon_load_dmem(gr->gpccs, gr->func->gpccs.ucode->data.data, 0x0, + gr->func->gpccs.ucode->data.size, 0); + nvkm_falcon_load_imem(gr->gpccs, gr->func->gpccs.ucode->code.data, 0x0, + gr->func->gpccs.ucode->code.size, 0, 0, false); nvkm_mc_unk260(device, 1); /* load register lists */ @@ -1729,10 +1696,32 @@ static int gf100_gr_init_(struct nvkm_gr *base) { struct gf100_gr *gr = gf100_gr(base); + struct nvkm_subdev *subdev = &base->engine.subdev; + u32 ret; + nvkm_pmu_pgob(gr->base.engine.subdev.device->pmu, false); + + ret = nvkm_falcon_get(gr->fecs, subdev); + if (ret) + return ret; + + ret = nvkm_falcon_get(gr->gpccs, subdev); + if (ret) + return ret; + return gr->func->init(gr); } +static int +gf100_gr_fini_(struct nvkm_gr *base, bool suspend) +{ + struct gf100_gr *gr = gf100_gr(base); + struct nvkm_subdev *subdev = &gr->base.engine.subdev; + nvkm_falcon_put(gr->gpccs, subdev); + nvkm_falcon_put(gr->fecs, subdev); + return 0; +} + void gf100_gr_dtor_fw(struct gf100_gr_fuc *fuc) { @@ -1755,6 +1744,9 @@ gf100_gr_dtor(struct nvkm_gr *base) gr->func->dtor(gr); kfree(gr->data); + nvkm_falcon_del(&gr->gpccs); + nvkm_falcon_del(&gr->fecs); + gf100_gr_dtor_fw(&gr->fuc409c); gf100_gr_dtor_fw(&gr->fuc409d); gf100_gr_dtor_fw(&gr->fuc41ac); @@ -1773,6 +1765,7 @@ gf100_gr_ = { .dtor = gf100_gr_dtor, .oneinit = gf100_gr_oneinit, .init = gf100_gr_init_, + .fini = gf100_gr_fini_, .intr = gf100_gr_intr, .units = gf100_gr_units, .chan_new = gf100_gr_chan_new, @@ -1846,6 +1839,7 @@ int gf100_gr_ctor(const struct gf100_gr_func *func, struct nvkm_device *device, int index, struct gf100_gr *gr) { + struct nvkm_subdev *subdev = &gr->base.engine.subdev; int ret; gr->func = func; @@ -1858,7 +1852,11 @@ gf100_gr_ctor(const struct gf100_gr_func *func, struct nvkm_device *device, if (ret) return ret; - return 0; + ret = nvkm_falcon_v1_new(subdev, "FECS", 0x409000, &gr->fecs); + if (ret) + return ret; + + return nvkm_falcon_v1_new(subdev, "GPCCS", 0x41a000, &gr->gpccs); } int diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h index 268b8d6..db6ee3b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h @@ -29,6 +29,7 @@ #include #include #include +#include #define GPC_MAX 32 #define TPC_MAX_PER_GPC 8 @@ -75,6 +76,8 @@ struct gf100_gr { const struct gf100_gr_func *func; struct nvkm_gr base; + struct nvkm_falcon *fecs; + struct nvkm_falcon *gpccs; struct gf100_gr_fuc fuc409c; struct gf100_gr_fuc fuc409d; struct gf100_gr_fuc fuc41ac; -- cgit v1.1 From c8225b54fe1b0d64b7da2c0d1d5b64d316b248f5 Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Tue, 13 Dec 2016 17:11:31 +0900 Subject: drm/nouveau/secboot: remove nvkm_secboot_start() Since GR has moved to using the falcon library to start the falcons, this function is not needed anymore. Signed-off-by: Alexandre Courbot Signed-off-by: Ben Skeggs --- .../gpu/drm/nouveau/include/nvkm/subdev/secboot.h | 1 - drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c | 15 ------------ .../gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c | 27 ---------------------- .../gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c | 1 - drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h | 1 - 5 files changed, 45 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/secboot.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/secboot.h index 2a2f651..be04c34 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/secboot.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/secboot.h @@ -48,7 +48,6 @@ struct nvkm_secboot { bool nvkm_secboot_is_managed(struct nvkm_secboot *, enum nvkm_secboot_falcon); int nvkm_secboot_reset(struct nvkm_secboot *, enum nvkm_secboot_falcon); -int nvkm_secboot_start(struct nvkm_secboot *, enum nvkm_secboot_falcon); int gm200_secboot_new(struct nvkm_device *, int, struct nvkm_secboot **); int gm20b_secboot_new(struct nvkm_device *, int, struct nvkm_secboot **); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c index a6e18ef..f423a1c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c @@ -49,21 +49,6 @@ nvkm_secboot_reset(struct nvkm_secboot *sb, enum nvkm_secboot_falcon falcon) } /** - * nvkm_secboot_start() - start specified falcon - */ -int -nvkm_secboot_start(struct nvkm_secboot *sb, enum nvkm_secboot_falcon falcon) -{ - /* Unmanaged falcon? */ - if (!(BIT(falcon) & sb->func->managed_falcons)) { - nvkm_error(&sb->subdev, "cannot start unmanaged falcon!\n"); - return -EINVAL; - } - - return sb->func->start(sb, falcon); -} - -/** * nvkm_secboot_is_managed() - check whether a given falcon is securely-managed */ bool diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c index a2a33f1..6f99cf2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c @@ -1253,32 +1253,6 @@ end: } int -gm200_secboot_start(struct nvkm_secboot *sb, enum nvkm_secboot_falcon falcon) -{ - struct gm200_secboot *gsb = gm200_secboot(sb); - int base; - - switch (falcon) { - case NVKM_SECBOOT_FALCON_FECS: - base = 0x409000; - break; - case NVKM_SECBOOT_FALCON_GPCCS: - base = 0x41a000; - break; - default: - nvkm_error(&sb->subdev, "cannot start unhandled falcon!\n"); - return -EINVAL; - } - - nvkm_wr32(sb->subdev.device, base + 0x130, 0x00000002); - gsb->falcon_state[falcon] = RUNNING; - - return 0; -} - - - -int gm200_secboot_init(struct nvkm_secboot *sb) { struct gm200_secboot *gsb = gm200_secboot(sb); @@ -1361,7 +1335,6 @@ gm200_secboot = { .init = gm200_secboot_init, .fini = gm200_secboot_fini, .reset = gm200_secboot_reset, - .start = gm200_secboot_start, .managed_falcons = BIT(NVKM_SECBOOT_FALCON_FECS) | BIT(NVKM_SECBOOT_FALCON_GPCCS), .boot_falcon = NVKM_SECBOOT_FALCON_PMU, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c index d5395eb..50f503b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c @@ -191,7 +191,6 @@ gm20b_secboot = { .dtor = gm200_secboot_dtor, .init = gm20b_secboot_init, .reset = gm200_secboot_reset, - .start = gm200_secboot_start, .managed_falcons = BIT(NVKM_SECBOOT_FALCON_FECS), .boot_falcon = NVKM_SECBOOT_FALCON_PMU, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h index 4b090d2..d23c94c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h @@ -31,7 +31,6 @@ struct nvkm_secboot_func { int (*fini)(struct nvkm_secboot *, bool suspend); void *(*dtor)(struct nvkm_secboot *); int (*reset)(struct nvkm_secboot *, enum nvkm_secboot_falcon); - int (*start)(struct nvkm_secboot *, enum nvkm_secboot_falcon); /* ID of the falcon that will perform secure boot */ enum nvkm_secboot_falcon boot_falcon; -- cgit v1.1 From 808d6efdeb361bd51c1afa2115db0e5f4fe6609d Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Wed, 14 Dec 2016 17:02:35 +0900 Subject: drm/nouveau/secboot: rename init() hook to oneinit() The init() hook is called by the subdev's oneinit(). Rename it accordingly to avoid confusion about the lifetime of objects allocated in it. Signed-off-by: Alexandre Courbot Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c | 4 ++-- drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c | 4 ++-- drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c | 6 +++--- drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h | 4 ++-- 4 files changed, 9 insertions(+), 9 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c index f423a1c..525740e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c @@ -78,8 +78,8 @@ nvkm_secboot_oneinit(struct nvkm_subdev *subdev) } /* Call chip-specific init function */ - if (sb->func->init) - ret = sb->func->init(sb); + if (sb->func->oneinit) + ret = sb->func->oneinit(sb); if (ret) { nvkm_error(subdev, "Secure Boot initialization failed: %d\n", ret); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c index 6f99cf2..98d18ec 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c @@ -1253,7 +1253,7 @@ end: } int -gm200_secboot_init(struct nvkm_secboot *sb) +gm200_secboot_oneinit(struct nvkm_secboot *sb) { struct gm200_secboot *gsb = gm200_secboot(sb); struct nvkm_device *device = sb->subdev.device; @@ -1332,7 +1332,7 @@ gm200_secboot_dtor(struct nvkm_secboot *sb) static const struct nvkm_secboot_func gm200_secboot = { .dtor = gm200_secboot_dtor, - .init = gm200_secboot_init, + .oneinit = gm200_secboot_oneinit, .fini = gm200_secboot_fini, .reset = gm200_secboot_reset, .managed_falcons = BIT(NVKM_SECBOOT_FALCON_FECS) | diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c index 50f503b..c08eb77 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c @@ -174,7 +174,7 @@ gm20b_tegra_read_wpr(struct gm200_secboot *gsb) #endif static int -gm20b_secboot_init(struct nvkm_secboot *sb) +gm20b_secboot_oneinit(struct nvkm_secboot *sb) { struct gm200_secboot *gsb = gm200_secboot(sb); int ret; @@ -183,13 +183,13 @@ gm20b_secboot_init(struct nvkm_secboot *sb) if (ret) return ret; - return gm200_secboot_init(sb); + return gm200_secboot_oneinit(sb); } static const struct nvkm_secboot_func gm20b_secboot = { .dtor = gm200_secboot_dtor, - .init = gm20b_secboot_init, + .oneinit = gm20b_secboot_oneinit, .reset = gm200_secboot_reset, .managed_falcons = BIT(NVKM_SECBOOT_FALCON_FECS), .boot_falcon = NVKM_SECBOOT_FALCON_PMU, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h index d23c94c..393b945 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h @@ -27,7 +27,7 @@ #include struct nvkm_secboot_func { - int (*init)(struct nvkm_secboot *); + int (*oneinit)(struct nvkm_secboot *); int (*fini)(struct nvkm_secboot *, bool suspend); void *(*dtor)(struct nvkm_secboot *); int (*reset)(struct nvkm_secboot *, enum nvkm_secboot_falcon); @@ -221,7 +221,7 @@ struct gm200_secboot_func { int (*prepare_blobs)(struct gm200_secboot *); }; -int gm200_secboot_init(struct nvkm_secboot *); +int gm200_secboot_oneinit(struct nvkm_secboot *); void *gm200_secboot_dtor(struct nvkm_secboot *); int gm200_secboot_reset(struct nvkm_secboot *, enum nvkm_secboot_falcon); int gm200_secboot_start(struct nvkm_secboot *, enum nvkm_secboot_falcon); -- cgit v1.1 From a9b333a50eee410ed302d25b00a7497e5c76894e Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Wed, 14 Dec 2016 17:02:36 +0900 Subject: drm/nouveau/secboot: remove fixup_hs_desc hook This hook can be removed if the function writing the HS descriptor is aware of WPR settings. Let's do that as it allows us to make the ACR descriptor structure private and save some code. Signed-off-by: Alexandre Courbot Signed-off-by: Ben Skeggs --- .../gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c | 95 ++++++++++++++++------ .../gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c | 11 --- drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h | 60 ++------------ 3 files changed, 79 insertions(+), 87 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c index 98d18ec..2747989 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c @@ -772,7 +772,7 @@ ls_ucode_mgr_write_wpr(struct gm200_secboot *gsb, struct ls_ucode_mgr *mgr, u8 desc[gsb->func->bl_desc_size]; struct gm200_flcn_bl_desc gdesc; - ls_ucode_img_populate_bl_desc(img, gsb->wpr_addr, + ls_ucode_img_populate_bl_desc(img, gsb->acr_wpr_addr, &gdesc); gsb->func->fixup_bl_desc(&gdesc, &desc); nvkm_gpuobj_memcpy_to(wpr_blob, @@ -847,8 +847,11 @@ gm200_secboot_prepare_ls_blob(struct gm200_secboot *gsb) /* If WPR address and size are not fixed, set them to fit the LS blob */ if (!gsb->wpr_size) { - gsb->wpr_addr = gsb->ls_blob->addr; - gsb->wpr_size = gsb->ls_blob->size; + gsb->acr_wpr_addr = gsb->ls_blob->addr; + gsb->acr_wpr_size = gsb->ls_blob->size; + } else { + gsb->acr_wpr_addr = gsb->wpr_addr; + gsb->acr_wpr_size = gsb->wpr_size; } /* Write LS blob */ @@ -926,6 +929,69 @@ gm200_secboot_populate_hsf_bl_desc(void *acr_image, } /** + * struct hsflcn_acr_desc - data section of the HS firmware + * + * This header is to be copied at the beginning of DMEM by the HS bootloader. + * + * @signature: signature of ACR ucode + * @wpr_region_id: region ID holding the WPR header and its details + * @wpr_offset: offset from the WPR region holding the wpr header + * @regions: region descriptors + * @nonwpr_ucode_blob_size: size of LS blob + * @nonwpr_ucode_blob_start: FB location of LS blob is + */ +struct hsflcn_acr_desc { + union { + u8 reserved_dmem[0x200]; + u32 signatures[4]; + } ucode_reserved_space; + u32 wpr_region_id; + u32 wpr_offset; + u32 mmu_mem_range; +#define FLCN_ACR_MAX_REGIONS 2 + struct { + u32 no_regions; + struct { + u32 start_addr; + u32 end_addr; + u32 region_id; + u32 read_mask; + u32 write_mask; + u32 client_mask; + } region_props[FLCN_ACR_MAX_REGIONS]; + } regions; + u32 ucode_blob_size; + u64 ucode_blob_base __aligned(8); + struct { + u32 vpr_enabled; + u32 vpr_start; + u32 vpr_end; + u32 hdcp_policies; + } vpr_desc; +}; + +static void +gm200_secboot_fixup_hs_desc(struct gm200_secboot *gsb, + struct hsflcn_acr_desc *desc) +{ + desc->ucode_blob_base = gsb->ls_blob->addr; + desc->ucode_blob_size = gsb->ls_blob->size; + + desc->wpr_offset = 0; + + /* WPR region information if WPR is not fixed */ + if (gsb->wpr_size == 0) { + desc->wpr_region_id = 1; + desc->regions.no_regions = 1; + desc->regions.region_props[0].region_id = 1; + desc->regions.region_props[0].start_addr = + gsb->acr_wpr_addr >> 8; + desc->regions.region_props[0].end_addr = + (gsb->acr_wpr_addr + gsb->acr_wpr_size) >> 8; + } +} + +/** * gm200_secboot_prepare_hs_blob - load and prepare a HS blob and BL descriptor * * @gsb secure boot instance to prepare for @@ -958,12 +1024,12 @@ gm200_secboot_prepare_hs_blob(struct gm200_secboot *gsb, const char *fw, acr_data = acr_image + hsbin_hdr->data_offset; - /* Patch descriptor? */ + /* Patch descriptor with WPR information? */ if (patch) { fw_hdr = acr_image + hsbin_hdr->header_offset; load_hdr = acr_image + fw_hdr->hdr_offset; desc = acr_data + load_hdr->data_dma_base; - gsb->func->fixup_hs_desc(gsb, desc); + gm200_secboot_fixup_hs_desc(gsb, desc); } /* Generate HS BL descriptor */ @@ -1351,29 +1417,10 @@ gm200_secboot_fixup_bl_desc(const struct gm200_flcn_bl_desc *desc, void *ret) memcpy(ret, desc, sizeof(*desc)); } -static void -gm200_secboot_fixup_hs_desc(struct gm200_secboot *gsb, - struct hsflcn_acr_desc *desc) -{ - desc->ucode_blob_base = gsb->ls_blob->addr; - desc->ucode_blob_size = gsb->ls_blob->size; - - desc->wpr_offset = 0; - - /* WPR region information for the HS binary to set up */ - desc->wpr_region_id = 1; - desc->regions.no_regions = 1; - desc->regions.region_props[0].region_id = 1; - desc->regions.region_props[0].start_addr = gsb->wpr_addr >> 8; - desc->regions.region_props[0].end_addr = - (gsb->wpr_addr + gsb->wpr_size) >> 8; -} - static const struct gm200_secboot_func gm200_secboot_func = { .bl_desc_size = sizeof(struct gm200_flcn_bl_desc), .fixup_bl_desc = gm200_secboot_fixup_bl_desc, - .fixup_hs_desc = gm200_secboot_fixup_hs_desc, .prepare_blobs = gm200_secboot_prepare_blobs, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c index c08eb77..5f38187 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c @@ -99,21 +99,10 @@ gm20b_secboot_fixup_bl_desc(const struct gm200_flcn_bl_desc *desc, void *ret) gdesc->data_size = desc->data_size; } -static void -gm20b_secboot_fixup_hs_desc(struct gm200_secboot *gsb, - struct hsflcn_acr_desc *desc) -{ - desc->ucode_blob_base = gsb->ls_blob->addr; - desc->ucode_blob_size = gsb->ls_blob->size; - - desc->wpr_offset = 0; -} - static const struct gm200_secboot_func gm20b_secboot_func = { .bl_desc_size = sizeof(struct gm20b_flcn_bl_desc), .fixup_bl_desc = gm20b_secboot_fixup_bl_desc, - .fixup_hs_desc = gm20b_secboot_fixup_hs_desc, .prepare_blobs = gm20b_secboot_prepare_blobs, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h index 393b945..e1caa6f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h @@ -88,48 +88,6 @@ struct gm200_flcn_bl_desc { }; /** - * struct hsflcn_acr_desc - data section of the HS firmware - * - * This header is to be copied at the beginning of DMEM by the HS bootloader. - * - * @signature: signature of ACR ucode - * @wpr_region_id: region ID holding the WPR header and its details - * @wpr_offset: offset from the WPR region holding the wpr header - * @regions: region descriptors - * @nonwpr_ucode_blob_size: size of LS blob - * @nonwpr_ucode_blob_start: FB location of LS blob is - */ -struct hsflcn_acr_desc { - union { - u8 reserved_dmem[0x200]; - u32 signatures[4]; - } ucode_reserved_space; - u32 wpr_region_id; - u32 wpr_offset; - u32 mmu_mem_range; -#define FLCN_ACR_MAX_REGIONS 2 - struct { - u32 no_regions; - struct { - u32 start_addr; - u32 end_addr; - u32 region_id; - u32 read_mask; - u32 write_mask; - u32 client_mask; - } region_props[FLCN_ACR_MAX_REGIONS]; - } regions; - u32 ucode_blob_size; - u64 ucode_blob_base __aligned(8); - struct { - u32 vpr_enabled; - u32 vpr_start; - u32 vpr_end; - u32 hdcp_policies; - } vpr_desc; -}; - -/** * Contains the whole secure boot state, allowing it to be performed as needed * @wpr_addr: physical address of the WPR region * @wpr_size: size in bytes of the WPR region @@ -151,14 +109,19 @@ struct gm200_secboot { const struct gm200_secboot_func *func; /* - * Address and size of the WPR region. On dGPU this will be the - * address of the LS blob. On Tegra this is a fixed region set by the - * bootloader + * Address and size of the fixed WPR region, if any. On Tegra this + * region is set by the bootloader */ u64 wpr_addr; u32 wpr_size; /* + * Address and size of the actual WPR region. + */ + u64 acr_wpr_addr; + u32 acr_wpr_size; + + /* * HS FW - lock WPR region (dGPU only) and load LS FWs * on Tegra the HS FW copies the LS blob into the fixed WPR instead */ @@ -200,7 +163,6 @@ struct gm200_secboot { * @fixup_bl_desc: hook that generates the proper BL descriptor format from * the generic GM200 format into a data array of size * bl_desc_size - * @fixup_hs_desc: hook that twiddles the HS descriptor before it is used * @prepare_blobs: prepares the various blobs needed for secure booting */ struct gm200_secboot_func { @@ -212,12 +174,6 @@ struct gm200_secboot_func { u32 bl_desc_size; void (*fixup_bl_desc)(const struct gm200_flcn_bl_desc *, void *); - /* - * Chip-specific modifications of the HS descriptor can be done here. - * On dGPU this is used to fill the information about the WPR region - * we want the HS FW to set up. - */ - void (*fixup_hs_desc)(struct gm200_secboot *, struct hsflcn_acr_desc *); int (*prepare_blobs)(struct gm200_secboot *); }; -- cgit v1.1 From e781ff9118fbbb7f91f55e3076bd0885d7609b59 Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Wed, 14 Dec 2016 17:02:37 +0900 Subject: drm/nouveau/secboot: add low-secure firmware hooks Secure firmwares provided by NVIDIA will follow the same overall principle, but may slightly differ in format, or not use the same bootloader descriptor even on the same chip. In order to handle this as gracefully as possible, turn the LS firmware functions into hooks that can be overloaded as needed. The current hooks cover the external firmware loading as well as the bootloader descriptor generation. Signed-off-by: Alexandre Courbot Signed-off-by: Ben Skeggs --- .../gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c | 239 ++++----------------- .../gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c | 30 +++ drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h | 193 +++++++++++++++++ 3 files changed, 265 insertions(+), 197 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c index 2747989..94cdc97 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c @@ -131,175 +131,6 @@ struct fw_bl_desc { }; -/* - * - * LS blob structures - * - */ - -/** - * struct lsf_ucode_desc - LS falcon signatures - * @prd_keys: signature to use when the GPU is in production mode - * @dgb_keys: signature to use when the GPU is in debug mode - * @b_prd_present: whether the production key is present - * @b_dgb_present: whether the debug key is present - * @falcon_id: ID of the falcon the ucode applies to - * - * Directly loaded from a signature file. - */ -struct lsf_ucode_desc { - u8 prd_keys[2][16]; - u8 dbg_keys[2][16]; - u32 b_prd_present; - u32 b_dbg_present; - u32 falcon_id; -}; - -/** - * struct lsf_lsb_header - LS firmware header - * @signature: signature to verify the firmware against - * @ucode_off: offset of the ucode blob in the WPR region. The ucode - * blob contains the bootloader, code and data of the - * LS falcon - * @ucode_size: size of the ucode blob, including bootloader - * @data_size: size of the ucode blob data - * @bl_code_size: size of the bootloader code - * @bl_imem_off: offset in imem of the bootloader - * @bl_data_off: offset of the bootloader data in WPR region - * @bl_data_size: size of the bootloader data - * @app_code_off: offset of the app code relative to ucode_off - * @app_code_size: size of the app code - * @app_data_off: offset of the app data relative to ucode_off - * @app_data_size: size of the app data - * @flags: flags for the secure bootloader - * - * This structure is written into the WPR region for each managed falcon. Each - * instance is referenced by the lsb_offset member of the corresponding - * lsf_wpr_header. - */ -struct lsf_lsb_header { - struct lsf_ucode_desc signature; - u32 ucode_off; - u32 ucode_size; - u32 data_size; - u32 bl_code_size; - u32 bl_imem_off; - u32 bl_data_off; - u32 bl_data_size; - u32 app_code_off; - u32 app_code_size; - u32 app_data_off; - u32 app_data_size; - u32 flags; -#define LSF_FLAG_LOAD_CODE_AT_0 1 -#define LSF_FLAG_DMACTL_REQ_CTX 4 -#define LSF_FLAG_FORCE_PRIV_LOAD 8 -}; - -/** - * struct lsf_wpr_header - LS blob WPR Header - * @falcon_id: LS falcon ID - * @lsb_offset: offset of the lsb_lsf_header in the WPR region - * @bootstrap_owner: secure falcon reponsible for bootstrapping the LS falcon - * @lazy_bootstrap: skip bootstrapping by ACR - * @status: bootstrapping status - * - * An array of these is written at the beginning of the WPR region, one for - * each managed falcon. The array is terminated by an instance which falcon_id - * is LSF_FALCON_ID_INVALID. - */ -struct lsf_wpr_header { - u32 falcon_id; - u32 lsb_offset; - u32 bootstrap_owner; - u32 lazy_bootstrap; - u32 status; -#define LSF_IMAGE_STATUS_NONE 0 -#define LSF_IMAGE_STATUS_COPY 1 -#define LSF_IMAGE_STATUS_VALIDATION_CODE_FAILED 2 -#define LSF_IMAGE_STATUS_VALIDATION_DATA_FAILED 3 -#define LSF_IMAGE_STATUS_VALIDATION_DONE 4 -#define LSF_IMAGE_STATUS_VALIDATION_SKIPPED 5 -#define LSF_IMAGE_STATUS_BOOTSTRAP_READY 6 -}; - - -/** - * struct ls_ucode_img_desc - descriptor of firmware image - * @descriptor_size: size of this descriptor - * @image_size: size of the whole image - * @bootloader_start_offset: start offset of the bootloader in ucode image - * @bootloader_size: size of the bootloader - * @bootloader_imem_offset: start off set of the bootloader in IMEM - * @bootloader_entry_point: entry point of the bootloader in IMEM - * @app_start_offset: start offset of the LS firmware - * @app_size: size of the LS firmware's code and data - * @app_imem_offset: offset of the app in IMEM - * @app_imem_entry: entry point of the app in IMEM - * @app_dmem_offset: offset of the data in DMEM - * @app_resident_code_offset: offset of app code from app_start_offset - * @app_resident_code_size: size of the code - * @app_resident_data_offset: offset of data from app_start_offset - * @app_resident_data_size: size of data - * - * A firmware image contains the code, data, and bootloader of a given LS - * falcon in a single blob. This structure describes where everything is. - * - * This can be generated from a (bootloader, code, data) set if they have - * been loaded separately, or come directly from a file. - */ -struct ls_ucode_img_desc { - u32 descriptor_size; - u32 image_size; - u32 tools_version; - u32 app_version; - char date[64]; - u32 bootloader_start_offset; - u32 bootloader_size; - u32 bootloader_imem_offset; - u32 bootloader_entry_point; - u32 app_start_offset; - u32 app_size; - u32 app_imem_offset; - u32 app_imem_entry; - u32 app_dmem_offset; - u32 app_resident_code_offset; - u32 app_resident_code_size; - u32 app_resident_data_offset; - u32 app_resident_data_size; - u32 nb_overlays; - struct {u32 start; u32 size; } load_ovl[64]; - u32 compressed; -}; - -/** - * struct ls_ucode_img - temporary storage for loaded LS firmwares - * @node: to link within lsf_ucode_mgr - * @falcon_id: ID of the falcon this LS firmware is for - * @ucode_desc: loaded or generated map of ucode_data - * @ucode_header: header of the firmware - * @ucode_data: firmware payload (code and data) - * @ucode_size: size in bytes of data in ucode_data - * @wpr_header: WPR header to be written to the LS blob - * @lsb_header: LSB header to be written to the LS blob - * - * Preparing the WPR LS blob requires information about all the LS firmwares - * (size, etc) to be known. This structure contains all the data of one LS - * firmware. - */ -struct ls_ucode_img { - struct list_head node; - enum nvkm_secboot_falcon falcon_id; - - struct ls_ucode_img_desc ucode_desc; - u32 *ucode_header; - u8 *ucode_data; - u32 ucode_size; - - struct lsf_wpr_header wpr_header; - struct lsf_lsb_header lsb_header; -}; - /** * struct ls_ucode_mgr - manager for all LS falcon firmwares * @count: number of managed LS falcons @@ -364,7 +195,7 @@ struct hsf_load_header { * it has the required minimum size. */ static void * -gm200_secboot_load_firmware(struct nvkm_subdev *subdev, const char *name, +gm200_secboot_load_firmware(const struct nvkm_subdev *subdev, const char *name, size_t min_size) { const struct firmware *fw; @@ -457,7 +288,7 @@ ls_ucode_img_build(const struct firmware *bl, const struct firmware *code, * blob. Also generate the corresponding ucode descriptor. */ static int -ls_ucode_img_load_generic(struct nvkm_subdev *subdev, +ls_ucode_img_load_generic(const struct nvkm_subdev *subdev, struct ls_ucode_img *img, const char *falcon_name, const u32 falcon_id) { @@ -518,17 +349,17 @@ error: return ret; } -typedef int (*lsf_load_func)(struct nvkm_subdev *, struct ls_ucode_img *); +typedef int (*lsf_load_func)(const struct nvkm_subdev *, struct ls_ucode_img *); -static int -ls_ucode_img_load_fecs(struct nvkm_subdev *subdev, struct ls_ucode_img *img) +int +gm200_ls_load_fecs(const struct nvkm_subdev *subdev, struct ls_ucode_img *img) { return ls_ucode_img_load_generic(subdev, img, "fecs", NVKM_SECBOOT_FALCON_FECS); } -static int -ls_ucode_img_load_gpccs(struct nvkm_subdev *subdev, struct ls_ucode_img *img) +int +gm200_ls_load_gpccs(const struct nvkm_subdev *subdev, struct ls_ucode_img *img) { return ls_ucode_img_load_generic(subdev, img, "gpccs", NVKM_SECBOOT_FALCON_GPCCS); @@ -556,14 +387,8 @@ ls_ucode_img_load(struct nvkm_subdev *subdev, lsf_load_func load_func) return img; } -static const lsf_load_func lsf_load_funcs[] = { - [NVKM_SECBOOT_FALCON_END] = NULL, /* reserve enough space */ - [NVKM_SECBOOT_FALCON_FECS] = ls_ucode_img_load_fecs, - [NVKM_SECBOOT_FALCON_GPCCS] = ls_ucode_img_load_gpccs, -}; - /** - * ls_ucode_img_populate_bl_desc() - populate a DMEM BL descriptor for LS image + * gm200_secboot_ls_bl_desc() - populate a DMEM BL descriptor for LS image * @img: ucode image to generate against * @desc: descriptor to populate * @sb: secure boot state to use for base addresses @@ -573,10 +398,11 @@ static const lsf_load_func lsf_load_funcs[] = { * */ static void -ls_ucode_img_populate_bl_desc(struct ls_ucode_img *img, u64 wpr_addr, - struct gm200_flcn_bl_desc *desc) +gm200_secboot_ls_bl_desc(const struct ls_ucode_img *img, u64 wpr_addr, + void *_desc) { - struct ls_ucode_img_desc *pdesc = &img->ucode_desc; + struct gm200_flcn_bl_desc *desc = _desc; + const struct ls_ucode_img_desc *pdesc = &img->ucode_desc; u64 addr_base; addr_base = wpr_addr + img->lsb_header.ucode_off + @@ -621,6 +447,8 @@ ls_ucode_img_fill_headers(struct gm200_secboot *gsb, struct ls_ucode_img *img, struct lsf_wpr_header *whdr = &img->wpr_header; struct lsf_lsb_header *lhdr = &img->lsb_header; struct ls_ucode_img_desc *desc = &img->ucode_desc; + const struct secboot_ls_single_func *func = + (*gsb->ls_func)[img->falcon_id]; if (img->ucode_header) { nvkm_fatal(&gsb->base.subdev, @@ -681,9 +509,9 @@ ls_ucode_img_fill_headers(struct gm200_secboot *gsb, struct ls_ucode_img *img, if (img->falcon_id == NVKM_SECBOOT_FALCON_GPCCS) lhdr->flags |= LSF_FLAG_FORCE_PRIV_LOAD; - /* Align (size bloat) and save off BL descriptor size */ - lhdr->bl_data_size = ALIGN(sizeof(struct gm200_flcn_bl_desc), - LSF_BL_DATA_SIZE_ALIGN); + /* Align and save off BL descriptor size */ + lhdr->bl_data_size = ALIGN(func->bl_desc_size, LSF_BL_DATA_SIZE_ALIGN); + /* * Align, save off, and include the additional BL data */ @@ -769,15 +597,16 @@ ls_ucode_mgr_write_wpr(struct gm200_secboot *gsb, struct ls_ucode_mgr *mgr, /* Generate and write BL descriptor */ if (!img->ucode_header) { - u8 desc[gsb->func->bl_desc_size]; - struct gm200_flcn_bl_desc gdesc; + const struct secboot_ls_single_func *ls_func = + (*gsb->ls_func)[img->falcon_id]; + u8 gdesc[ls_func->bl_desc_size]; + + ls_func->generate_bl_desc(img, gsb->acr_wpr_addr, + &gdesc); - ls_ucode_img_populate_bl_desc(img, gsb->acr_wpr_addr, - &gdesc); - gsb->func->fixup_bl_desc(&gdesc, &desc); nvkm_gpuobj_memcpy_to(wpr_blob, img->lsb_header.bl_data_off, - &desc, gsb->func->bl_desc_size); + &gdesc, ls_func->bl_desc_size); } /* Copy ucode */ @@ -816,11 +645,12 @@ gm200_secboot_prepare_ls_blob(struct gm200_secboot *gsb) ls_ucode_mgr_init(&mgr); /* Load all LS blobs */ - for_each_set_bit(falcon_id, &gsb->base.func->managed_falcons, + for_each_set_bit(falcon_id, &sb->func->managed_falcons, NVKM_SECBOOT_FALCON_END) { struct ls_ucode_img *img; - img = ls_ucode_img_load(&sb->subdev, lsf_load_funcs[falcon_id]); + img = ls_ucode_img_load(&sb->subdev, + (*gsb->ls_func)[falcon_id]->load); if (IS_ERR(img)) { ret = PTR_ERR(img); @@ -865,6 +695,20 @@ cleanup: return ret; } +static const secboot_ls_func +gm200_ls_func = { + [NVKM_SECBOOT_FALCON_FECS] = &(struct secboot_ls_single_func) { + .load = gm200_ls_load_fecs, + .generate_bl_desc = gm200_secboot_ls_bl_desc, + .bl_desc_size = sizeof(struct gm200_flcn_bl_desc), + }, + [NVKM_SECBOOT_FALCON_GPCCS] = &(struct secboot_ls_single_func) { + .load = gm200_ls_load_gpccs, + .generate_bl_desc = gm200_secboot_ls_bl_desc, + .bl_desc_size = sizeof(struct gm200_flcn_bl_desc), + }, +}; + /* * High-secure blob creation */ @@ -1443,6 +1287,7 @@ gm200_secboot_new(struct nvkm_device *device, int index, return ret; gsb->func = &gm200_secboot_func; + gsb->ls_func = &gm200_ls_func; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c index 5f38187..16b9aa3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c @@ -23,6 +23,7 @@ #include "priv.h" #include +#include /* * The BL header format used by GM20B's firmware is slightly different @@ -42,6 +43,25 @@ struct gm20b_flcn_bl_desc { u32 data_size; }; +static void +gm20b_secboot_ls_bl_desc(const struct ls_ucode_img *img, u64 wpr_addr, + void *_desc) +{ + struct gm20b_flcn_bl_desc *desc = _desc; + const struct ls_ucode_img_desc *pdesc = &img->ucode_desc; + u64 base; + + base = wpr_addr + img->lsb_header.ucode_off + pdesc->app_start_offset; + + memset(desc, 0, sizeof(*desc)); + desc->ctx_dma = FALCON_DMAIDX_UCODE; + desc->code_dma_base = (base + pdesc->app_resident_code_offset) >> 8; + desc->non_sec_code_size = pdesc->app_resident_code_size; + desc->data_dma_base = (base + pdesc->app_resident_data_offset) >> 8; + desc->data_size = pdesc->app_resident_data_size; + desc->code_entry_point = pdesc->app_imem_entry; +} + static int gm20b_secboot_prepare_blobs(struct gm200_secboot *gsb) { @@ -184,6 +204,15 @@ gm20b_secboot = { .boot_falcon = NVKM_SECBOOT_FALCON_PMU, }; +static const secboot_ls_func +gm20b_ls_func = { + [NVKM_SECBOOT_FALCON_FECS] = &(struct secboot_ls_single_func) { + .load = gm200_ls_load_fecs, + .generate_bl_desc = gm20b_secboot_ls_bl_desc, + .bl_desc_size = sizeof(struct gm20b_flcn_bl_desc), + }, +}; + int gm20b_secboot_new(struct nvkm_device *device, int index, struct nvkm_secboot **psb) @@ -203,6 +232,7 @@ gm20b_secboot_new(struct nvkm_device *device, int index, return ret; gsb->func = &gm20b_secboot_func; + gsb->ls_func = &gm20b_ls_func; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h index e1caa6f..a0ecd35 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h @@ -41,6 +41,175 @@ struct nvkm_secboot_func { int nvkm_secboot_ctor(const struct nvkm_secboot_func *, struct nvkm_device *, int index, struct nvkm_secboot *); +/* + * + * LS blob structures + * + */ + +/** + * struct lsf_ucode_desc - LS falcon signatures + * @prd_keys: signature to use when the GPU is in production mode + * @dgb_keys: signature to use when the GPU is in debug mode + * @b_prd_present: whether the production key is present + * @b_dgb_present: whether the debug key is present + * @falcon_id: ID of the falcon the ucode applies to + * + * Directly loaded from a signature file. + */ +struct lsf_ucode_desc { + u8 prd_keys[2][16]; + u8 dbg_keys[2][16]; + u32 b_prd_present; + u32 b_dbg_present; + u32 falcon_id; +}; + +/** + * struct lsf_lsb_header - LS firmware header + * @signature: signature to verify the firmware against + * @ucode_off: offset of the ucode blob in the WPR region. The ucode + * blob contains the bootloader, code and data of the + * LS falcon + * @ucode_size: size of the ucode blob, including bootloader + * @data_size: size of the ucode blob data + * @bl_code_size: size of the bootloader code + * @bl_imem_off: offset in imem of the bootloader + * @bl_data_off: offset of the bootloader data in WPR region + * @bl_data_size: size of the bootloader data + * @app_code_off: offset of the app code relative to ucode_off + * @app_code_size: size of the app code + * @app_data_off: offset of the app data relative to ucode_off + * @app_data_size: size of the app data + * @flags: flags for the secure bootloader + * + * This structure is written into the WPR region for each managed falcon. Each + * instance is referenced by the lsb_offset member of the corresponding + * lsf_wpr_header. + */ +struct lsf_lsb_header { + struct lsf_ucode_desc signature; + u32 ucode_off; + u32 ucode_size; + u32 data_size; + u32 bl_code_size; + u32 bl_imem_off; + u32 bl_data_off; + u32 bl_data_size; + u32 app_code_off; + u32 app_code_size; + u32 app_data_off; + u32 app_data_size; + u32 flags; +#define LSF_FLAG_LOAD_CODE_AT_0 1 +#define LSF_FLAG_DMACTL_REQ_CTX 4 +#define LSF_FLAG_FORCE_PRIV_LOAD 8 +}; + +/** + * struct lsf_wpr_header - LS blob WPR Header + * @falcon_id: LS falcon ID + * @lsb_offset: offset of the lsb_lsf_header in the WPR region + * @bootstrap_owner: secure falcon reponsible for bootstrapping the LS falcon + * @lazy_bootstrap: skip bootstrapping by ACR + * @status: bootstrapping status + * + * An array of these is written at the beginning of the WPR region, one for + * each managed falcon. The array is terminated by an instance which falcon_id + * is LSF_FALCON_ID_INVALID. + */ +struct lsf_wpr_header { + u32 falcon_id; + u32 lsb_offset; + u32 bootstrap_owner; + u32 lazy_bootstrap; + u32 status; +#define LSF_IMAGE_STATUS_NONE 0 +#define LSF_IMAGE_STATUS_COPY 1 +#define LSF_IMAGE_STATUS_VALIDATION_CODE_FAILED 2 +#define LSF_IMAGE_STATUS_VALIDATION_DATA_FAILED 3 +#define LSF_IMAGE_STATUS_VALIDATION_DONE 4 +#define LSF_IMAGE_STATUS_VALIDATION_SKIPPED 5 +#define LSF_IMAGE_STATUS_BOOTSTRAP_READY 6 +}; + + +/** + * struct ls_ucode_img_desc - descriptor of firmware image + * @descriptor_size: size of this descriptor + * @image_size: size of the whole image + * @bootloader_start_offset: start offset of the bootloader in ucode image + * @bootloader_size: size of the bootloader + * @bootloader_imem_offset: start off set of the bootloader in IMEM + * @bootloader_entry_point: entry point of the bootloader in IMEM + * @app_start_offset: start offset of the LS firmware + * @app_size: size of the LS firmware's code and data + * @app_imem_offset: offset of the app in IMEM + * @app_imem_entry: entry point of the app in IMEM + * @app_dmem_offset: offset of the data in DMEM + * @app_resident_code_offset: offset of app code from app_start_offset + * @app_resident_code_size: size of the code + * @app_resident_data_offset: offset of data from app_start_offset + * @app_resident_data_size: size of data + * + * A firmware image contains the code, data, and bootloader of a given LS + * falcon in a single blob. This structure describes where everything is. + * + * This can be generated from a (bootloader, code, data) set if they have + * been loaded separately, or come directly from a file. + */ +struct ls_ucode_img_desc { + u32 descriptor_size; + u32 image_size; + u32 tools_version; + u32 app_version; + char date[64]; + u32 bootloader_start_offset; + u32 bootloader_size; + u32 bootloader_imem_offset; + u32 bootloader_entry_point; + u32 app_start_offset; + u32 app_size; + u32 app_imem_offset; + u32 app_imem_entry; + u32 app_dmem_offset; + u32 app_resident_code_offset; + u32 app_resident_code_size; + u32 app_resident_data_offset; + u32 app_resident_data_size; + u32 nb_overlays; + struct {u32 start; u32 size; } load_ovl[64]; + u32 compressed; +}; + +/** + * struct ls_ucode_img - temporary storage for loaded LS firmwares + * @node: to link within lsf_ucode_mgr + * @falcon_id: ID of the falcon this LS firmware is for + * @ucode_desc: loaded or generated map of ucode_data + * @ucode_header: header of the firmware + * @ucode_data: firmware payload (code and data) + * @ucode_size: size in bytes of data in ucode_data + * @wpr_header: WPR header to be written to the LS blob + * @lsb_header: LSB header to be written to the LS blob + * + * Preparing the WPR LS blob requires information about all the LS firmwares + * (size, etc) to be known. This structure contains all the data of one LS + * firmware. + */ +struct ls_ucode_img { + struct list_head node; + enum nvkm_secboot_falcon falcon_id; + + struct ls_ucode_img_desc ucode_desc; + u32 *ucode_header; + u8 *ucode_data; + u32 ucode_size; + + struct lsf_wpr_header wpr_header; + struct lsf_lsb_header lsb_header; +}; + struct flcn_u64 { u32 lo; u32 hi; @@ -88,6 +257,29 @@ struct gm200_flcn_bl_desc { }; /** + * struct secboot_ls_single_func - manages a single LS firmware + * + * @load: load the external firmware into a ls_ucode_img + * @generate_bl_desc: function called on a block of bl_desc_size to generate the + * proper bootloader descriptor for this LS firmware + * @bl_desc_size: size of the bootloader descriptor + */ +struct secboot_ls_single_func { + int (*load)(const struct nvkm_subdev *, struct ls_ucode_img *); + void (*generate_bl_desc)(const struct ls_ucode_img *, u64, void *); + u32 bl_desc_size; +}; + +/** + * typedef secboot_ls_func - manages all the LS firmwares for this ACR + */ +typedef const struct secboot_ls_single_func * +secboot_ls_func[NVKM_SECBOOT_FALCON_END]; + +int gm200_ls_load_fecs(const struct nvkm_subdev *, struct ls_ucode_img *); +int gm200_ls_load_gpccs(const struct nvkm_subdev *, struct ls_ucode_img *); + +/** * Contains the whole secure boot state, allowing it to be performed as needed * @wpr_addr: physical address of the WPR region * @wpr_size: size in bytes of the WPR region @@ -107,6 +299,7 @@ struct gm200_flcn_bl_desc { struct gm200_secboot { struct nvkm_secboot base; const struct gm200_secboot_func *func; + const secboot_ls_func *ls_func; /* * Address and size of the fixed WPR region, if any. On Tegra this -- cgit v1.1 From 8f491c892eb4acbde080753a51f4d5cb5997168d Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Wed, 14 Dec 2016 17:02:38 +0900 Subject: drm/nouveau/secboot: generate HS BL descriptor in hook Use the HS hook to completely generate the HS BL descriptor, similarly to what is done in the LS hook, instead of (arbitrarily) using the acr_v1 format as an intermediate. This allows us to make the bootloader descriptor structures private to each implementation, resulting in a cleaner an more consistent design. Signed-off-by: Alexandre Courbot Signed-off-by: Ben Skeggs --- .../gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c | 179 ++++++++++----------- .../gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c | 43 ++--- drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h | 71 ++++---- 3 files changed, 138 insertions(+), 155 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c index 94cdc97..fd82203 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c @@ -175,21 +175,45 @@ struct hsf_fw_header { u32 hdr_size; }; + /** - * struct hsf_load_header - HS firmware load header + * struct gm200_flcn_bl_desc - DMEM bootloader descriptor + * @signature: 16B signature for secure code. 0s if no secure code + * @ctx_dma: DMA context to be used by BL while loading code/data + * @code_dma_base: 256B-aligned Physical FB Address where code is located + * (falcon's $xcbase register) + * @non_sec_code_off: offset from code_dma_base where the non-secure code is + * located. The offset must be multiple of 256 to help perf + * @non_sec_code_size: the size of the nonSecure code part. + * @sec_code_off: offset from code_dma_base where the secure code is + * located. The offset must be multiple of 256 to help perf + * @sec_code_size: offset from code_dma_base where the secure code is + * located. The offset must be multiple of 256 to help perf + * @code_entry_point: code entry point which will be invoked by BL after + * code is loaded. + * @data_dma_base: 256B aligned Physical FB Address where data is located. + * (falcon's $xdbase register) + * @data_size: size of data block. Should be multiple of 256B + * + * Structure used by the bootloader to load the rest of the code. This has + * to be filled by host and copied into DMEM at offset provided in the + * hsflcn_bl_desc.bl_desc_dmem_load_off. */ -struct hsf_load_header { +struct gm200_flcn_bl_desc { + u32 reserved[4]; + u32 signature[4]; + u32 ctx_dma; + struct flcn_u64 code_dma_base; u32 non_sec_code_off; u32 non_sec_code_size; - u32 data_dma_base; + u32 sec_code_off; + u32 sec_code_size; + u32 code_entry_point; + struct flcn_u64 data_dma_base; u32 data_size; - u32 num_apps; - struct { - u32 sec_code_off; - u32 sec_code_size; - } app[0]; }; + /** * Convenience function to duplicate a firmware file in memory and check that * it has the required minimum size. @@ -740,39 +764,6 @@ gm200_secboot_hsf_patch_signature(struct gm200_secboot *gsb, void *acr_image) } /** - * gm200_secboot_populate_hsf_bl_desc() - populate BL descriptor for HS image - */ -static void -gm200_secboot_populate_hsf_bl_desc(void *acr_image, - struct gm200_flcn_bl_desc *bl_desc) -{ - struct fw_bin_header *hsbin_hdr = acr_image; - struct hsf_fw_header *fw_hdr = acr_image + hsbin_hdr->header_offset; - struct hsf_load_header *load_hdr = acr_image + fw_hdr->hdr_offset; - - /* - * Descriptor for the bootloader that will load the ACR image into - * IMEM/DMEM memory. - */ - fw_hdr = acr_image + hsbin_hdr->header_offset; - load_hdr = acr_image + fw_hdr->hdr_offset; - memset(bl_desc, 0, sizeof(*bl_desc)); - bl_desc->ctx_dma = FALCON_DMAIDX_VIRT; - bl_desc->non_sec_code_off = load_hdr->non_sec_code_off; - bl_desc->non_sec_code_size = load_hdr->non_sec_code_size; - bl_desc->sec_code_off = load_hdr->app[0].sec_code_off; - bl_desc->sec_code_size = load_hdr->app[0].sec_code_size; - bl_desc->code_entry_point = 0; - /* - * We need to set code_dma_base to the virtual address of the acr_blob, - * and add this address to data_dma_base before writing it into DMEM - */ - bl_desc->code_dma_base.lo = 0; - bl_desc->data_dma_base.lo = load_hdr->data_dma_base; - bl_desc->data_size = load_hdr->data_size; -} - -/** * struct hsflcn_acr_desc - data section of the HS firmware * * This header is to be copied at the beginning of DMEM by the HS bootloader. @@ -847,37 +838,44 @@ gm200_secboot_fixup_hs_desc(struct gm200_secboot *gsb, static int gm200_secboot_prepare_hs_blob(struct gm200_secboot *gsb, const char *fw, struct nvkm_gpuobj **blob, - struct gm200_flcn_bl_desc *bl_desc, bool patch) + struct hsf_load_header *load_header, bool patch) { struct nvkm_subdev *subdev = &gsb->base.subdev; void *acr_image; struct fw_bin_header *hsbin_hdr; struct hsf_fw_header *fw_hdr; - void *acr_data; struct hsf_load_header *load_hdr; - struct hsflcn_acr_desc *desc; + void *acr_data; int ret; acr_image = gm200_secboot_load_firmware(subdev, fw, 0); if (IS_ERR(acr_image)) return PTR_ERR(acr_image); + hsbin_hdr = acr_image; + fw_hdr = acr_image + hsbin_hdr->header_offset; + load_hdr = acr_image + fw_hdr->hdr_offset; + acr_data = acr_image + hsbin_hdr->data_offset; /* Patch signature */ gm200_secboot_hsf_patch_signature(gsb, acr_image); - acr_data = acr_image + hsbin_hdr->data_offset; - /* Patch descriptor with WPR information? */ if (patch) { - fw_hdr = acr_image + hsbin_hdr->header_offset; - load_hdr = acr_image + fw_hdr->hdr_offset; + struct hsflcn_acr_desc *desc; + desc = acr_data + load_hdr->data_dma_base; gm200_secboot_fixup_hs_desc(gsb, desc); } - /* Generate HS BL descriptor */ - gm200_secboot_populate_hsf_bl_desc(acr_image, bl_desc); + if (load_hdr->num_apps > GM200_ACR_MAX_APPS) { + nvkm_error(subdev, "more apps (%d) than supported (%d)!", + load_hdr->num_apps, GM200_ACR_MAX_APPS); + ret = -EINVAL; + goto cleanup; + } + memcpy(load_header, load_hdr, sizeof(*load_header) + + (sizeof(load_hdr->app[0]) * load_hdr->num_apps)); /* Create ACR blob and copy HS data to it */ ret = nvkm_gpuobj_new(subdev->device, ALIGN(hsbin_hdr->data_size, 256), @@ -938,7 +936,7 @@ gm20x_secboot_prepare_blobs(struct gm200_secboot *gsb) if (!gsb->acr_load_blob) { ret = gm200_secboot_prepare_hs_blob(gsb, "acr/ucode_load", &gsb->acr_load_blob, - &gsb->acr_load_bl_desc, true); + &gsb->load_bl_header, true); if (ret) return ret; } @@ -966,7 +964,7 @@ gm200_secboot_prepare_blobs(struct gm200_secboot *gsb) if (!gsb->acr_unload_blob) { ret = gm200_secboot_prepare_hs_blob(gsb, "acr/ucode_unload", &gsb->acr_unload_blob, - &gsb->acr_unload_bl_desc, false); + &gsb->unload_bl_header, false); if (ret) return ret; } @@ -1037,8 +1035,7 @@ gm200_secboot_load_hs_bl(struct gm200_secboot *gsb, struct nvkm_falcon *falcon, * gm200_secboot_run_hs_blob() - run the given high-secure blob */ static int -gm200_secboot_run_hs_blob(struct gm200_secboot *gsb, struct nvkm_gpuobj *blob, - struct gm200_flcn_bl_desc *desc) +gm200_secboot_run_hs_blob(struct gm200_secboot *gsb, struct nvkm_gpuobj *blob) { struct nvkm_subdev *subdev = &gsb->base.subdev; struct fw_bin_header *hdr = gsb->hsbl_blob; @@ -1046,11 +1043,22 @@ gm200_secboot_run_hs_blob(struct gm200_secboot *gsb, struct nvkm_gpuobj *blob, struct nvkm_falcon *falcon = gsb->base.boot_falcon; const u32 virt_addr = hsbl_desc->start_tag << 8; const u32 bl_desc_size = gsb->func->bl_desc_size; + const struct hsf_load_header *load_hdr; u8 bl_desc[bl_desc_size]; struct nvkm_vma vma; - u64 vma_addr; int ret; + /* Find the bootloader descriptor for our blob and copy it */ + if (blob == gsb->acr_load_blob) { + load_hdr = &gsb->load_bl_header; + + } else if (blob == gsb->acr_unload_blob) { + load_hdr = &gsb->unload_bl_header; + } else { + nvkm_error(&gsb->base.subdev, "invalid secure boot blob!\n"); + return -EINVAL; + } + ret = nvkm_falcon_get(falcon, subdev); if (ret) return ret; @@ -1062,21 +1070,13 @@ gm200_secboot_run_hs_blob(struct gm200_secboot *gsb, struct nvkm_gpuobj *blob, return ret; } - /* Add the mapping address to the DMA bases */ - vma_addr = flcn64_to_u64(desc->code_dma_base) + vma.offset; - desc->code_dma_base.lo = lower_32_bits(vma_addr); - desc->code_dma_base.hi = upper_32_bits(vma_addr); - vma_addr = flcn64_to_u64(desc->data_dma_base) + vma.offset; - desc->data_dma_base.lo = lower_32_bits(vma_addr); - desc->data_dma_base.hi = upper_32_bits(vma_addr); - - /* Fixup the BL header */ - gsb->func->fixup_bl_desc(desc, &bl_desc); + /* Generate the BL header */ + gsb->func->generate_bl_desc(load_hdr, bl_desc, vma.offset); /* Reset and set the falcon up */ ret = nvkm_falcon_reset(falcon); if (ret) - goto done; + goto end; nvkm_falcon_bind_context(falcon, gsb->inst); /* Load the HS bootloader into the falcon's IMEM/DMEM */ @@ -1087,25 +1087,17 @@ gm200_secboot_run_hs_blob(struct gm200_secboot *gsb, struct nvkm_gpuobj *blob, nvkm_falcon_start(falcon); ret = nvkm_falcon_wait_for_halt(falcon, 100); if (ret) - goto done; + goto end; /* If mailbox register contains an error code, then ACR has failed */ ret = nvkm_falcon_rd32(falcon, 0x040); if (ret) { nvkm_error(subdev, "ACR boot failed, ret 0x%08x", ret); ret = -EINVAL; - goto done; + goto end; } -done: - /* Restore the original DMA addresses */ - vma_addr = flcn64_to_u64(desc->code_dma_base) - vma.offset; - desc->code_dma_base.lo = lower_32_bits(vma_addr); - desc->code_dma_base.hi = upper_32_bits(vma_addr); - vma_addr = flcn64_to_u64(desc->data_dma_base) - vma.offset; - desc->data_dma_base.lo = lower_32_bits(vma_addr); - desc->data_dma_base.hi = upper_32_bits(vma_addr); - +end: /* We don't need the ACR firmware anymore */ nvkm_gpuobj_unmap(&vma); nvkm_falcon_put(falcon, subdev); @@ -1145,15 +1137,13 @@ gm200_secboot_reset(struct nvkm_secboot *sb, enum nvkm_secboot_falcon falcon) /* If WPR is set and we have an unload blob, run it to unlock WPR */ if (gsb->acr_unload_blob && gsb->falcon_state[NVKM_SECBOOT_FALCON_FECS] != NON_SECURE) { - ret = gm200_secboot_run_hs_blob(gsb, gsb->acr_unload_blob, - &gsb->acr_unload_bl_desc); + ret = gm200_secboot_run_hs_blob(gsb, gsb->acr_unload_blob); if (ret) return ret; } /* Reload all managed falcons */ - ret = gm200_secboot_run_hs_blob(gsb, gsb->acr_load_blob, - &gsb->acr_load_bl_desc); + ret = gm200_secboot_run_hs_blob(gsb, gsb->acr_load_blob); if (ret) return ret; @@ -1211,8 +1201,7 @@ gm200_secboot_fini(struct nvkm_secboot *sb, bool suspend) /* Run the unload blob to unprotect the WPR region */ if (gsb->acr_unload_blob && gsb->falcon_state[NVKM_SECBOOT_FALCON_FECS] != NON_SECURE) - ret = gm200_secboot_run_hs_blob(gsb, gsb->acr_unload_blob, - &gsb->acr_unload_bl_desc); + ret = gm200_secboot_run_hs_blob(gsb, gsb->acr_unload_blob); for (i = 0; i < NVKM_SECBOOT_FALCON_END; i++) gsb->falcon_state[i] = NON_SECURE; @@ -1250,21 +1239,29 @@ gm200_secboot = { .boot_falcon = NVKM_SECBOOT_FALCON_PMU, }; -/** - * gm200_fixup_bl_desc - just copy the BL descriptor - * - * Use the GM200 descriptor format by default. - */ static void -gm200_secboot_fixup_bl_desc(const struct gm200_flcn_bl_desc *desc, void *ret) +gm200_secboot_generate_bl_desc(const struct hsf_load_header *hdr, + void *_bl_desc, u64 offset) { - memcpy(ret, desc, sizeof(*desc)); + struct gm200_flcn_bl_desc *bl_desc = _bl_desc; + + memset(bl_desc, 0, sizeof(*bl_desc)); + bl_desc->ctx_dma = FALCON_DMAIDX_VIRT; + bl_desc->non_sec_code_off = hdr->non_sec_code_off; + bl_desc->non_sec_code_size = hdr->non_sec_code_size; + bl_desc->sec_code_off = hdr->app[0].sec_code_off; + bl_desc->sec_code_size = hdr->app[0].sec_code_size; + bl_desc->code_entry_point = 0; + + bl_desc->code_dma_base = u64_to_flcn64(offset); + bl_desc->data_dma_base = u64_to_flcn64(offset + hdr->data_dma_base); + bl_desc->data_size = hdr->data_size; } static const struct gm200_secboot_func gm200_secboot_func = { .bl_desc_size = sizeof(struct gm200_flcn_bl_desc), - .fixup_bl_desc = gm200_secboot_fixup_bl_desc, + .generate_bl_desc = gm200_secboot_generate_bl_desc, .prepare_blobs = gm200_secboot_prepare_blobs, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c index 16b9aa3..94d6c44 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c @@ -88,41 +88,28 @@ gm20b_secboot_prepare_blobs(struct gm200_secboot *gsb) return 0; } -/** - * gm20b_secboot_fixup_bl_desc - adapt BL descriptor to format used by GM20B FW - * - * There is only a slight format difference (DMA addresses being 32-bits and - * 256B-aligned) to address. - */ static void -gm20b_secboot_fixup_bl_desc(const struct gm200_flcn_bl_desc *desc, void *ret) +gm20b_secboot_generate_bl_desc(const struct hsf_load_header *load_hdr, + void *_bl_desc, u64 offset) { - struct gm20b_flcn_bl_desc *gdesc = ret; - u64 addr; - - memcpy(gdesc->reserved, desc->reserved, sizeof(gdesc->reserved)); - memcpy(gdesc->signature, desc->signature, sizeof(gdesc->signature)); - gdesc->ctx_dma = desc->ctx_dma; - addr = desc->code_dma_base.hi; - addr <<= 32; - addr |= desc->code_dma_base.lo; - gdesc->code_dma_base = lower_32_bits(addr >> 8); - gdesc->non_sec_code_off = desc->non_sec_code_off; - gdesc->non_sec_code_size = desc->non_sec_code_size; - gdesc->sec_code_off = desc->sec_code_off; - gdesc->sec_code_size = desc->sec_code_size; - gdesc->code_entry_point = desc->code_entry_point; - addr = desc->data_dma_base.hi; - addr <<= 32; - addr |= desc->data_dma_base.lo; - gdesc->data_dma_base = lower_32_bits(addr >> 8); - gdesc->data_size = desc->data_size; + struct gm20b_flcn_bl_desc *bl_desc = _bl_desc; + + memset(bl_desc, 0, sizeof(*bl_desc)); + bl_desc->ctx_dma = FALCON_DMAIDX_VIRT; + bl_desc->non_sec_code_off = load_hdr->non_sec_code_off; + bl_desc->non_sec_code_size = load_hdr->non_sec_code_size; + bl_desc->sec_code_off = load_hdr->app[0].sec_code_off; + bl_desc->sec_code_size = load_hdr->app[0].sec_code_size; + bl_desc->code_entry_point = 0; + bl_desc->code_dma_base = offset >> 8; + bl_desc->data_dma_base = (offset + load_hdr->data_dma_base) >> 8; + bl_desc->data_size = load_hdr->data_size; } static const struct gm200_secboot_func gm20b_secboot_func = { .bl_desc_size = sizeof(struct gm20b_flcn_bl_desc), - .fixup_bl_desc = gm20b_secboot_fixup_bl_desc, + .generate_bl_desc = gm20b_secboot_generate_bl_desc, .prepare_blobs = gm20b_secboot_prepare_blobs, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h index a0ecd35..3babed5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h @@ -214,46 +214,39 @@ struct flcn_u64 { u32 lo; u32 hi; }; + static inline u64 flcn64_to_u64(const struct flcn_u64 f) { return ((u64)f.hi) << 32 | f.lo; } +static inline struct flcn_u64 u64_to_flcn64(u64 u) +{ + struct flcn_u64 ret; + + ret.hi = upper_32_bits(u); + ret.lo = lower_32_bits(u); + + return ret; +} + +#define GM200_ACR_MAX_APPS 8 + +struct hsf_load_header_app { + u32 sec_code_off; + u32 sec_code_size; +}; + /** - * struct gm200_flcn_bl_desc - DMEM bootloader descriptor - * @signature: 16B signature for secure code. 0s if no secure code - * @ctx_dma: DMA context to be used by BL while loading code/data - * @code_dma_base: 256B-aligned Physical FB Address where code is located - * (falcon's $xcbase register) - * @non_sec_code_off: offset from code_dma_base where the non-secure code is - * located. The offset must be multiple of 256 to help perf - * @non_sec_code_size: the size of the nonSecure code part. - * @sec_code_off: offset from code_dma_base where the secure code is - * located. The offset must be multiple of 256 to help perf - * @sec_code_size: offset from code_dma_base where the secure code is - * located. The offset must be multiple of 256 to help perf - * @code_entry_point: code entry point which will be invoked by BL after - * code is loaded. - * @data_dma_base: 256B aligned Physical FB Address where data is located. - * (falcon's $xdbase register) - * @data_size: size of data block. Should be multiple of 256B - * - * Structure used by the bootloader to load the rest of the code. This has - * to be filled by host and copied into DMEM at offset provided in the - * hsflcn_bl_desc.bl_desc_dmem_load_off. + * struct hsf_load_header - HS firmware load header */ -struct gm200_flcn_bl_desc { - u32 reserved[4]; - u32 signature[4]; - u32 ctx_dma; - struct flcn_u64 code_dma_base; +struct hsf_load_header { u32 non_sec_code_off; u32 non_sec_code_size; - u32 sec_code_off; - u32 sec_code_size; - u32 code_entry_point; - struct flcn_u64 data_dma_base; + u32 data_dma_base; u32 data_size; + u32 num_apps; + struct hsf_load_header_app app[0]; }; /** @@ -319,11 +312,17 @@ struct gm200_secboot { * on Tegra the HS FW copies the LS blob into the fixed WPR instead */ struct nvkm_gpuobj *acr_load_blob; - struct gm200_flcn_bl_desc acr_load_bl_desc; + struct { + struct hsf_load_header load_bl_header; + struct hsf_load_header_app __load_apps[GM200_ACR_MAX_APPS]; + }; /* HS FW - unlock WPR region (dGPU only) */ struct nvkm_gpuobj *acr_unload_blob; - struct gm200_flcn_bl_desc acr_unload_bl_desc; + struct { + struct hsf_load_header unload_bl_header; + struct hsf_load_header_app __unload_apps[GM200_ACR_MAX_APPS]; + }; /* HS bootloader */ void *hsbl_blob; @@ -353,9 +352,9 @@ struct gm200_secboot { /** * Contains functions we wish to abstract between GM200-like implementations * @bl_desc_size: size of the BL descriptor used by this chip. - * @fixup_bl_desc: hook that generates the proper BL descriptor format from - * the generic GM200 format into a data array of size - * bl_desc_size + * @generate_bl_desc: hook that generates the proper BL descriptor format from + * the hsf_load_header format into a preallocated array of + * size bl_desc_size * @prepare_blobs: prepares the various blobs needed for secure booting */ struct gm200_secboot_func { @@ -365,7 +364,7 @@ struct gm200_secboot_func { * callback is called on it */ u32 bl_desc_size; - void (*fixup_bl_desc)(const struct gm200_flcn_bl_desc *, void *); + void (*generate_bl_desc)(const struct hsf_load_header *, void *, u64); int (*prepare_blobs)(struct gm200_secboot *); }; -- cgit v1.1 From 72e0642fb4c21632a410c1ff971a63886402b9c9 Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Wed, 14 Dec 2016 17:02:39 +0900 Subject: drm/nouveau/secboot: reorganize into more files Split the act of building the ACR blob from firmware files from the rest of the (chip-dependent) secure boot logic. ACR logic is moved into acr_rxxx.c files, where rxxx corresponds to the compatible release of the NVIDIA driver. At the moment r352 and r361 are supported since firmwares have been released for these versions. Some abstractions are added on top of r352 so r361 can easily be implemented on top of it by just overriding a few hooks. This split makes it possible and easy to reuse the same ACR version on different chips. It also hopefully makes the code much more readable as the different secure boot logics are separated. As more chips and firmware versions will be supported, this is a necessity to not get lost in code that is already quite complex. This is a big commit, but it essentially moves things around (and split the nvkm_secboot structure into two, nvkm_secboot and nvkm_acr). Code semantics should not be affected. Signed-off-by: Alexandre Courbot Signed-off-by: Ben Skeggs --- .../gpu/drm/nouveau/include/nvkm/subdev/secboot.h | 9 +- drivers/gpu/drm/nouveau/nvkm/subdev/secboot/Kbuild | 4 + drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr.c | 54 + drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr.h | 69 ++ .../gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c | 910 ++++++++++++++++ .../gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.h | 126 +++ .../gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c | 135 +++ drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c | 84 +- .../gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c | 1152 +------------------- .../gpu/drm/nouveau/nvkm/subdev/secboot/gm200.h | 43 + .../gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c | 125 +-- .../gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode.h | 245 +++++ .../drm/nouveau/nvkm/subdev/secboot/ls_ucode_gr.c | 167 +++ drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h | 328 +----- 14 files changed, 1877 insertions(+), 1574 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_gr.c (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/secboot.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/secboot.h index be04c34..6e9e045 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/secboot.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/secboot.h @@ -34,15 +34,14 @@ enum nvkm_secboot_falcon { NVKM_SECBOOT_FALCON_INVALID = 0xffffffff, }; -/** - * @base: base IO address of the falcon performing secure boot - * @irq_mask: IRQ mask of the falcon performing secure boot - * @enable_mask: enable mask of the falcon performing secure boot -*/ struct nvkm_secboot { const struct nvkm_secboot_func *func; + struct nvkm_acr *acr; struct nvkm_subdev subdev; struct nvkm_falcon *boot_falcon; + + u64 wpr_addr; + u32 wpr_size; }; #define nvkm_secboot(p) container_of((p), struct nvkm_secboot, subdev) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/Kbuild index b02b868..5076d15 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/Kbuild @@ -1,3 +1,7 @@ nvkm-y += nvkm/subdev/secboot/base.o +nvkm-y += nvkm/subdev/secboot/ls_ucode_gr.o +nvkm-y += nvkm/subdev/secboot/acr.o +nvkm-y += nvkm/subdev/secboot/acr_r352.o +nvkm-y += nvkm/subdev/secboot/acr_r361.o nvkm-y += nvkm/subdev/secboot/gm200.o nvkm-y += nvkm/subdev/secboot/gm20b.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr.c new file mode 100644 index 0000000..75dc065 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr.c @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "acr.h" + +#include + +/** + * Convenience function to duplicate a firmware file in memory and check that + * it has the required minimum size. + */ +void * +nvkm_acr_load_firmware(const struct nvkm_subdev *subdev, const char *name, + size_t min_size) +{ + const struct firmware *fw; + void *blob; + int ret; + + ret = nvkm_firmware_get(subdev->device, name, &fw); + if (ret) + return ERR_PTR(ret); + if (fw->size < min_size) { + nvkm_error(subdev, "%s is smaller than expected size %zu\n", + name, min_size); + nvkm_firmware_put(fw); + return ERR_PTR(-EINVAL); + } + blob = kmemdup(fw->data, fw->size, GFP_KERNEL); + nvkm_firmware_put(fw); + if (!blob) + return ERR_PTR(-ENOMEM); + + return blob; +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr.h b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr.h new file mode 100644 index 0000000..97795b3 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __NVKM_SECBOOT_ACR_H__ +#define __NVKM_SECBOOT_ACR_H__ + +#include "priv.h" + +struct nvkm_acr; + +/** + * struct nvkm_acr_func - properties and functions specific to an ACR + * + * @load: make the ACR ready to run on the given secboot device + * @reset: reset the specified falcon + * @start: start the specified falcon (assumed to have been reset) + */ +struct nvkm_acr_func { + void (*dtor)(struct nvkm_acr *); + int (*oneinit)(struct nvkm_acr *, struct nvkm_secboot *); + int (*fini)(struct nvkm_acr *, struct nvkm_secboot *, bool); + int (*load)(struct nvkm_acr *, struct nvkm_secboot *, + struct nvkm_gpuobj *, u64); + int (*reset)(struct nvkm_acr *, struct nvkm_secboot *, + enum nvkm_secboot_falcon); + int (*start)(struct nvkm_acr *, struct nvkm_secboot *, + enum nvkm_secboot_falcon); +}; + +/** + * struct nvkm_acr - instance of an ACR + * + * @boot_falcon: ID of the falcon that will perform secure boot + * @managed_falcons: bitfield of falcons managed by this ACR + * @start_address: virtual start address of the HS bootloader + */ +struct nvkm_acr { + const struct nvkm_acr_func *func; + const struct nvkm_subdev *subdev; + + enum nvkm_secboot_falcon boot_falcon; + unsigned long managed_falcons; + u32 start_address; +}; + +void *nvkm_acr_load_firmware(const struct nvkm_subdev *, const char *, size_t); + +struct nvkm_acr *acr_r352_new(unsigned long); +struct nvkm_acr *acr_r361_new(unsigned long); + +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c new file mode 100644 index 0000000..d8cf06d --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c @@ -0,0 +1,910 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "acr_r352.h" +#include "ls_ucode.h" + +#include +#include +#include + +/** + * struct hsf_fw_header - HS firmware descriptor + * @sig_dbg_offset: offset of the debug signature + * @sig_dbg_size: size of the debug signature + * @sig_prod_offset: offset of the production signature + * @sig_prod_size: size of the production signature + * @patch_loc: offset of the offset (sic) of where the signature is + * @patch_sig: offset of the offset (sic) to add to sig_*_offset + * @hdr_offset: offset of the load header (see struct hs_load_header) + * @hdr_size: size of above header + * + * This structure is embedded in the HS firmware image at + * hs_bin_hdr.header_offset. + */ +struct hsf_fw_header { + u32 sig_dbg_offset; + u32 sig_dbg_size; + u32 sig_prod_offset; + u32 sig_prod_size; + u32 patch_loc; + u32 patch_sig; + u32 hdr_offset; + u32 hdr_size; +}; + +/** + * struct acr_r352_flcn_bl_desc - DMEM bootloader descriptor + * @signature: 16B signature for secure code. 0s if no secure code + * @ctx_dma: DMA context to be used by BL while loading code/data + * @code_dma_base: 256B-aligned Physical FB Address where code is located + * (falcon's $xcbase register) + * @non_sec_code_off: offset from code_dma_base where the non-secure code is + * located. The offset must be multiple of 256 to help perf + * @non_sec_code_size: the size of the nonSecure code part. + * @sec_code_off: offset from code_dma_base where the secure code is + * located. The offset must be multiple of 256 to help perf + * @sec_code_size: offset from code_dma_base where the secure code is + * located. The offset must be multiple of 256 to help perf + * @code_entry_point: code entry point which will be invoked by BL after + * code is loaded. + * @data_dma_base: 256B aligned Physical FB Address where data is located. + * (falcon's $xdbase register) + * @data_size: size of data block. Should be multiple of 256B + * + * Structure used by the bootloader to load the rest of the code. This has + * to be filled by host and copied into DMEM at offset provided in the + * hsflcn_bl_desc.bl_desc_dmem_load_off. + */ +struct acr_r352_flcn_bl_desc { + u32 reserved[4]; + u32 signature[4]; + u32 ctx_dma; + u32 code_dma_base; + u32 non_sec_code_off; + u32 non_sec_code_size; + u32 sec_code_off; + u32 sec_code_size; + u32 code_entry_point; + u32 data_dma_base; + u32 data_size; +}; + +/** + * acr_r352_generate_flcn_bl_desc - generate generic BL descriptor for LS image + */ +static void +acr_r352_generate_flcn_bl_desc(const struct nvkm_acr *acr, + const struct ls_ucode_img *img, u64 wpr_addr, + void *_desc) +{ + struct acr_r352_flcn_bl_desc *desc = _desc; + const struct ls_ucode_img_desc *pdesc = &img->ucode_desc; + u64 base, addr_code, addr_data; + + base = wpr_addr + img->lsb_header.ucode_off + pdesc->app_start_offset; + addr_code = (base + pdesc->app_resident_code_offset) >> 8; + addr_data = (base + pdesc->app_resident_data_offset) >> 8; + + memset(desc, 0, sizeof(*desc)); + desc->ctx_dma = FALCON_DMAIDX_UCODE; + desc->code_dma_base = lower_32_bits(addr_code); + desc->non_sec_code_off = pdesc->app_resident_code_offset; + desc->non_sec_code_size = pdesc->app_resident_code_size; + desc->code_entry_point = pdesc->app_imem_entry; + desc->data_dma_base = lower_32_bits(addr_data); + desc->data_size = pdesc->app_resident_data_size; +} + + +/** + * struct hsflcn_acr_desc - data section of the HS firmware + * + * This header is to be copied at the beginning of DMEM by the HS bootloader. + * + * @signature: signature of ACR ucode + * @wpr_region_id: region ID holding the WPR header and its details + * @wpr_offset: offset from the WPR region holding the wpr header + * @regions: region descriptors + * @nonwpr_ucode_blob_size: size of LS blob + * @nonwpr_ucode_blob_start: FB location of LS blob is + */ +struct hsflcn_acr_desc { + union { + u8 reserved_dmem[0x200]; + u32 signatures[4]; + } ucode_reserved_space; + u32 wpr_region_id; + u32 wpr_offset; + u32 mmu_mem_range; +#define FLCN_ACR_MAX_REGIONS 2 + struct { + u32 no_regions; + struct { + u32 start_addr; + u32 end_addr; + u32 region_id; + u32 read_mask; + u32 write_mask; + u32 client_mask; + } region_props[FLCN_ACR_MAX_REGIONS]; + } regions; + u32 ucode_blob_size; + u64 ucode_blob_base __aligned(8); + struct { + u32 vpr_enabled; + u32 vpr_start; + u32 vpr_end; + u32 hdcp_policies; + } vpr_desc; +}; + + +/* + * Low-secure blob creation + */ + +typedef int (*lsf_load_func)(const struct nvkm_subdev *, struct ls_ucode_img *); + +/** + * ls_ucode_img_load() - create a lsf_ucode_img and load it + */ +static struct ls_ucode_img * +ls_ucode_img_load(const struct nvkm_subdev *subdev, lsf_load_func load_func) +{ + struct ls_ucode_img *img; + int ret; + + img = kzalloc(sizeof(*img), GFP_KERNEL); + if (!img) + return ERR_PTR(-ENOMEM); + + ret = load_func(subdev, img); + + if (ret) { + kfree(img); + return ERR_PTR(ret); + } + + return img; +} + +#define LSF_LSB_HEADER_ALIGN 256 +#define LSF_BL_DATA_ALIGN 256 +#define LSF_BL_DATA_SIZE_ALIGN 256 +#define LSF_BL_CODE_SIZE_ALIGN 256 +#define LSF_UCODE_DATA_ALIGN 4096 + +/** + * ls_ucode_img_fill_headers - fill the WPR and LSB headers of an image + * @acr: ACR to use + * @img: image to generate for + * @offset: offset in the WPR region where this image starts + * + * Allocate space in the WPR area from offset and write the WPR and LSB headers + * accordingly. + * + * Return: offset at the end of this image. + */ +static u32 +ls_ucode_img_fill_headers(struct acr_r352 *acr, struct ls_ucode_img *img, + u32 offset) +{ + struct lsf_wpr_header *whdr = &img->wpr_header; + struct lsf_lsb_header *lhdr = &img->lsb_header; + struct ls_ucode_img_desc *desc = &img->ucode_desc; + const struct acr_r352_ls_func *func = + acr->func->ls_func[img->falcon_id]; + + if (img->ucode_header) { + nvkm_fatal(acr->base.subdev, + "images withough loader are not supported yet!\n"); + return offset; + } + + /* Fill WPR header */ + whdr->falcon_id = img->falcon_id; + whdr->bootstrap_owner = acr->base.boot_falcon; + whdr->status = LSF_IMAGE_STATUS_COPY; + + /* Align, save off, and include an LSB header size */ + offset = ALIGN(offset, LSF_LSB_HEADER_ALIGN); + whdr->lsb_offset = offset; + offset += sizeof(struct lsf_lsb_header); + + /* + * Align, save off, and include the original (static) ucode + * image size + */ + offset = ALIGN(offset, LSF_UCODE_DATA_ALIGN); + lhdr->ucode_off = offset; + offset += img->ucode_size; + + /* + * For falcons that use a boot loader (BL), we append a loader + * desc structure on the end of the ucode image and consider + * this the boot loader data. The host will then copy the loader + * desc args to this space within the WPR region (before locking + * down) and the HS bin will then copy them to DMEM 0 for the + * loader. + */ + lhdr->bl_code_size = ALIGN(desc->bootloader_size, + LSF_BL_CODE_SIZE_ALIGN); + lhdr->ucode_size = ALIGN(desc->app_resident_data_offset, + LSF_BL_CODE_SIZE_ALIGN) + lhdr->bl_code_size; + lhdr->data_size = ALIGN(desc->app_size, LSF_BL_CODE_SIZE_ALIGN) + + lhdr->bl_code_size - lhdr->ucode_size; + /* + * Though the BL is located at 0th offset of the image, the VA + * is different to make sure that it doesn't collide the actual + * OS VA range + */ + lhdr->bl_imem_off = desc->bootloader_imem_offset; + lhdr->app_code_off = desc->app_start_offset + + desc->app_resident_code_offset; + lhdr->app_code_size = desc->app_resident_code_size; + lhdr->app_data_off = desc->app_start_offset + + desc->app_resident_data_offset; + lhdr->app_data_size = desc->app_resident_data_size; + + lhdr->flags = 0; + if (img->falcon_id == acr->base.boot_falcon) + lhdr->flags = LSF_FLAG_DMACTL_REQ_CTX; + + /* GPCCS will be loaded using PRI */ + if (img->falcon_id == NVKM_SECBOOT_FALCON_GPCCS) + lhdr->flags |= LSF_FLAG_FORCE_PRIV_LOAD; + + /* Align and save off BL descriptor size */ + lhdr->bl_data_size = ALIGN(func->bl_desc_size, LSF_BL_DATA_SIZE_ALIGN); + + /* + * Align, save off, and include the additional BL data + */ + offset = ALIGN(offset, LSF_BL_DATA_ALIGN); + lhdr->bl_data_off = offset; + offset += lhdr->bl_data_size; + + return offset; +} + +/** + * struct ls_ucode_mgr - manager for all LS falcon firmwares + * @count: number of managed LS falcons + * @wpr_size: size of the required WPR region in bytes + * @img_list: linked list of lsf_ucode_img + */ +struct ls_ucode_mgr { + u16 count; + u32 wpr_size; + struct list_head img_list; +}; + +static void +ls_ucode_mgr_init(struct ls_ucode_mgr *mgr) +{ + memset(mgr, 0, sizeof(*mgr)); + INIT_LIST_HEAD(&mgr->img_list); +} + +static void +ls_ucode_mgr_cleanup(struct ls_ucode_mgr *mgr) +{ + struct ls_ucode_img *img, *t; + + list_for_each_entry_safe(img, t, &mgr->img_list, node) { + kfree(img->ucode_data); + kfree(img->ucode_header); + kfree(img); + } +} + +static void +ls_ucode_mgr_add_img(struct ls_ucode_mgr *mgr, struct ls_ucode_img *img) +{ + mgr->count++; + list_add_tail(&img->node, &mgr->img_list); +} + +/** + * ls_ucode_mgr_fill_headers - fill WPR and LSB headers of all managed images + */ +static void +ls_ucode_mgr_fill_headers(struct acr_r352 *acr, struct ls_ucode_mgr *mgr) +{ + struct ls_ucode_img *img; + u32 offset; + + /* + * Start with an array of WPR headers at the base of the WPR. + * The expectation here is that the secure falcon will do a single DMA + * read of this array and cache it internally so it's ok to pack these. + * Also, we add 1 to the falcon count to indicate the end of the array. + */ + offset = sizeof(struct lsf_wpr_header) * (mgr->count + 1); + + /* + * Walk the managed falcons, accounting for the LSB structs + * as well as the ucode images. + */ + list_for_each_entry(img, &mgr->img_list, node) { + offset = ls_ucode_img_fill_headers(acr, img, offset); + } + + mgr->wpr_size = offset; +} + +/** + * ls_ucode_mgr_write_wpr - write the WPR blob contents + */ +static int +ls_ucode_mgr_write_wpr(struct acr_r352 *acr, struct ls_ucode_mgr *mgr, + struct nvkm_gpuobj *wpr_blob, u32 wpr_addr) +{ + struct ls_ucode_img *img; + u32 pos = 0; + + nvkm_kmap(wpr_blob); + + list_for_each_entry(img, &mgr->img_list, node) { + nvkm_gpuobj_memcpy_to(wpr_blob, pos, &img->wpr_header, + sizeof(img->wpr_header)); + + nvkm_gpuobj_memcpy_to(wpr_blob, img->wpr_header.lsb_offset, + &img->lsb_header, sizeof(img->lsb_header)); + + /* Generate and write BL descriptor */ + if (!img->ucode_header) { + const struct acr_r352_ls_func *ls_func = + acr->func->ls_func[img->falcon_id]; + u8 gdesc[ls_func->bl_desc_size]; + + ls_func->generate_bl_desc(&acr->base, img, wpr_addr, + gdesc); + + nvkm_gpuobj_memcpy_to(wpr_blob, + img->lsb_header.bl_data_off, + gdesc, ls_func->bl_desc_size); + } + + /* Copy ucode */ + nvkm_gpuobj_memcpy_to(wpr_blob, img->lsb_header.ucode_off, + img->ucode_data, img->ucode_size); + + pos += sizeof(img->wpr_header); + } + + nvkm_wo32(wpr_blob, pos, NVKM_SECBOOT_FALCON_INVALID); + + nvkm_done(wpr_blob); + + return 0; +} + +/* Both size and address of WPR need to be 128K-aligned */ +#define WPR_ALIGNMENT 0x20000 +/** + * acr_r352_prepare_ls_blob() - prepare the LS blob + * + * For each securely managed falcon, load the FW, signatures and bootloaders and + * prepare a ucode blob. Then, compute the offsets in the WPR region for each + * blob, and finally write the headers and ucode blobs into a GPU object that + * will be copied into the WPR region by the HS firmware. + */ +static int +acr_r352_prepare_ls_blob(struct acr_r352 *acr, u64 wpr_addr, u32 wpr_size) +{ + const struct nvkm_subdev *subdev = acr->base.subdev; + struct ls_ucode_mgr mgr; + unsigned long managed_falcons = acr->base.managed_falcons; + int falcon_id; + int ret; + + ls_ucode_mgr_init(&mgr); + + /* Load all LS blobs */ + for_each_set_bit(falcon_id, &managed_falcons, NVKM_SECBOOT_FALCON_END) { + struct ls_ucode_img *img; + + img = ls_ucode_img_load(subdev, + acr->func->ls_func[falcon_id]->load); + + if (IS_ERR(img)) { + ret = PTR_ERR(img); + goto cleanup; + } + ls_ucode_mgr_add_img(&mgr, img); + } + + /* + * Fill the WPR and LSF headers with the right offsets and compute + * required WPR size + */ + ls_ucode_mgr_fill_headers(acr, &mgr); + mgr.wpr_size = ALIGN(mgr.wpr_size, WPR_ALIGNMENT); + + /* Allocate GPU object that will contain the WPR region */ + ret = nvkm_gpuobj_new(subdev->device, mgr.wpr_size, WPR_ALIGNMENT, + false, NULL, &acr->ls_blob); + if (ret) + goto cleanup; + + nvkm_debug(subdev, "%d managed LS falcons, WPR size is %d bytes\n", + mgr.count, mgr.wpr_size); + + /* If WPR address and size are not fixed, set them to fit the LS blob */ + if (wpr_size == 0) { + wpr_addr = acr->ls_blob->addr; + wpr_size = mgr.wpr_size; + /* + * But if the WPR region is set by the bootloader, it is illegal for + * the HS blob to be larger than this region. + */ + } else if (mgr.wpr_size > wpr_size) { + nvkm_error(subdev, "WPR region too small for FW blob!\n"); + nvkm_error(subdev, "required: %dB\n", mgr.wpr_size); + nvkm_error(subdev, "available: %dB\n", wpr_size); + ret = -ENOSPC; + goto cleanup; + } + + /* Write LS blob */ + ret = ls_ucode_mgr_write_wpr(acr, &mgr, acr->ls_blob, wpr_addr); + if (ret) + nvkm_gpuobj_del(&acr->ls_blob); + +cleanup: + ls_ucode_mgr_cleanup(&mgr); + + return ret; +} + + + + +/** + * acr_r352_hsf_patch_signature() - patch HS blob with correct signature + */ +static void +acr_r352_hsf_patch_signature(struct nvkm_secboot *sb, void *acr_image) +{ + struct fw_bin_header *hsbin_hdr = acr_image; + struct hsf_fw_header *fw_hdr = acr_image + hsbin_hdr->header_offset; + void *hs_data = acr_image + hsbin_hdr->data_offset; + void *sig; + u32 sig_size; + + /* Falcon in debug or production mode? */ + if (sb->boot_falcon->debug) { + sig = acr_image + fw_hdr->sig_dbg_offset; + sig_size = fw_hdr->sig_dbg_size; + } else { + sig = acr_image + fw_hdr->sig_prod_offset; + sig_size = fw_hdr->sig_prod_size; + } + + /* Patch signature */ + memcpy(hs_data + fw_hdr->patch_loc, sig + fw_hdr->patch_sig, sig_size); +} + +static void +acr_r352_fixup_hs_desc(struct acr_r352 *acr, struct nvkm_secboot *sb, + struct hsflcn_acr_desc *desc) +{ + struct nvkm_gpuobj *ls_blob = acr->ls_blob; + + desc->ucode_blob_base = ls_blob->addr; + desc->ucode_blob_size = ls_blob->size; + + desc->wpr_offset = 0; + + /* WPR region information if WPR is not fixed */ + if (sb->wpr_size == 0) { + desc->wpr_region_id = 1; + desc->regions.no_regions = 1; + desc->regions.region_props[0].region_id = 1; + desc->regions.region_props[0].start_addr = ls_blob->addr >> 8; + desc->regions.region_props[0].end_addr = + (ls_blob->addr + ls_blob->size) >> 8; + } +} + +static void +acr_r352_generate_hs_bl_desc(const struct hsf_load_header *hdr, void *_bl_desc, + u64 offset) +{ + struct acr_r352_flcn_bl_desc *bl_desc = _bl_desc; + u64 addr_code, addr_data; + + memset(bl_desc, 0, sizeof(*bl_desc)); + addr_code = offset >> 8; + addr_data = (offset + hdr->data_dma_base) >> 8; + + bl_desc->ctx_dma = FALCON_DMAIDX_VIRT; + bl_desc->code_dma_base = lower_32_bits(addr_code); + bl_desc->non_sec_code_off = hdr->non_sec_code_off; + bl_desc->non_sec_code_size = hdr->non_sec_code_size; + bl_desc->sec_code_off = hdr->app[0].sec_code_off; + bl_desc->sec_code_size = hdr->app[0].sec_code_size; + bl_desc->code_entry_point = 0; + bl_desc->data_dma_base = lower_32_bits(addr_data); + bl_desc->data_size = hdr->data_size; +} + +/** + * acr_r352_prepare_hs_blob - load and prepare a HS blob and BL descriptor + * + * @sb secure boot instance to prepare for + * @fw name of the HS firmware to load + * @blob pointer to gpuobj that will be allocated to receive the HS FW payload + * @bl_desc pointer to the BL descriptor to write for this firmware + * @patch whether we should patch the HS descriptor (only for HS loaders) + */ +static int +acr_r352_prepare_hs_blob(struct acr_r352 *acr, struct nvkm_secboot *sb, + const char *fw, struct nvkm_gpuobj **blob, + struct hsf_load_header *load_header, bool patch) +{ + struct nvkm_subdev *subdev = &sb->subdev; + void *acr_image; + struct fw_bin_header *hsbin_hdr; + struct hsf_fw_header *fw_hdr; + struct hsf_load_header *load_hdr; + void *acr_data; + int ret; + + acr_image = nvkm_acr_load_firmware(subdev, fw, 0); + if (IS_ERR(acr_image)) + return PTR_ERR(acr_image); + + hsbin_hdr = acr_image; + fw_hdr = acr_image + hsbin_hdr->header_offset; + load_hdr = acr_image + fw_hdr->hdr_offset; + acr_data = acr_image + hsbin_hdr->data_offset; + + /* Patch signature */ + acr_r352_hsf_patch_signature(sb, acr_image); + + /* Patch descriptor with WPR information? */ + if (patch) { + struct hsflcn_acr_desc *desc; + + desc = acr_data + load_hdr->data_dma_base; + acr_r352_fixup_hs_desc(acr, sb, desc); + } + + if (load_hdr->num_apps > ACR_R352_MAX_APPS) { + nvkm_error(subdev, "more apps (%d) than supported (%d)!", + load_hdr->num_apps, ACR_R352_MAX_APPS); + ret = -EINVAL; + goto cleanup; + } + memcpy(load_header, load_hdr, sizeof(*load_header) + + (sizeof(load_hdr->app[0]) * load_hdr->num_apps)); + + /* Create ACR blob and copy HS data to it */ + ret = nvkm_gpuobj_new(subdev->device, ALIGN(hsbin_hdr->data_size, 256), + 0x1000, false, NULL, blob); + if (ret) + goto cleanup; + + nvkm_kmap(*blob); + nvkm_gpuobj_memcpy_to(*blob, 0, acr_data, hsbin_hdr->data_size); + nvkm_done(*blob); + +cleanup: + kfree(acr_image); + + return ret; +} + +static int +acr_r352_prepare_hsbl_blob(struct acr_r352 *acr) +{ + const struct nvkm_subdev *subdev = acr->base.subdev; + struct fw_bin_header *hdr; + struct fw_bl_desc *hsbl_desc; + + acr->hsbl_blob = nvkm_acr_load_firmware(subdev, "acr/bl", 0); + if (IS_ERR(acr->hsbl_blob)) { + int ret = PTR_ERR(acr->hsbl_blob); + + acr->hsbl_blob = NULL; + return ret; + } + + hdr = acr->hsbl_blob; + hsbl_desc = acr->hsbl_blob + hdr->header_offset; + + /* virtual start address for boot vector */ + acr->base.start_address = hsbl_desc->start_tag << 8; + + return 0; +} + +/** + * acr_r352_load_blobs - load blobs common to all ACR V1 versions. + * + * This includes the LS blob, HS ucode loading blob, and HS bootloader. + * + * The HS ucode unload blob is only used on dGPU if the WPR region is variable. + */ +int +acr_r352_load_blobs(struct acr_r352 *acr, struct nvkm_secboot *sb) +{ + int ret; + + /* Firmware already loaded? */ + if (acr->firmware_ok) + return 0; + + /* Load and prepare the managed falcon's firmwares */ + ret = acr_r352_prepare_ls_blob(acr, sb->wpr_addr, sb->wpr_size); + if (ret) + return ret; + + /* Load the HS firmware that will load the LS firmwares */ + if (!acr->load_blob) { + ret = acr_r352_prepare_hs_blob(acr, sb, "acr/ucode_load", + &acr->load_blob, + &acr->load_bl_header, true); + if (ret) + return ret; + } + + /* If the ACR region is dynamically programmed, we need an unload FW */ + if (sb->wpr_size == 0) { + ret = acr_r352_prepare_hs_blob(acr, sb, "acr/ucode_unload", + &acr->unload_blob, + &acr->unload_bl_header, false); + if (ret) + return ret; + } + + /* Load the HS firmware bootloader */ + if (!acr->hsbl_blob) { + ret = acr_r352_prepare_hsbl_blob(acr); + if (ret) + return ret; + } + + acr->firmware_ok = true; + nvkm_debug(&sb->subdev, "LS blob successfully created\n"); + + return 0; +} + +/** + * acr_r352_load() - prepare HS falcon to run the specified blob, mapped + * at GPU address offset. + */ +static int +acr_r352_load(struct nvkm_acr *_acr, struct nvkm_secboot *sb, + struct nvkm_gpuobj *blob, u64 offset) +{ + struct acr_r352 *acr = acr_r352(_acr); + struct nvkm_falcon *falcon = sb->boot_falcon; + struct fw_bin_header *hdr = acr->hsbl_blob; + struct fw_bl_desc *hsbl_desc = acr->hsbl_blob + hdr->header_offset; + void *blob_data = acr->hsbl_blob + hdr->data_offset; + void *hsbl_code = blob_data + hsbl_desc->code_off; + void *hsbl_data = blob_data + hsbl_desc->data_off; + u32 code_size = ALIGN(hsbl_desc->code_size, 256); + const struct hsf_load_header *load_hdr; + const u32 bl_desc_size = acr->func->hs_bl_desc_size; + u8 bl_desc[bl_desc_size]; + + /* Find the bootloader descriptor for our blob and copy it */ + if (blob == acr->load_blob) { + load_hdr = &acr->load_bl_header; + } else if (blob == acr->unload_blob) { + load_hdr = &acr->unload_bl_header; + } else { + nvkm_error(_acr->subdev, "invalid secure boot blob!\n"); + return -EINVAL; + } + + /* + * Copy HS bootloader data + */ + nvkm_falcon_load_dmem(falcon, hsbl_data, 0x0, hsbl_desc->data_size, 0); + + /* Copy HS bootloader code to end of IMEM */ + nvkm_falcon_load_imem(falcon, hsbl_code, falcon->code.limit - code_size, + code_size, hsbl_desc->start_tag, 0, false); + + /* Generate the BL header */ + acr->func->generate_hs_bl_desc(load_hdr, bl_desc, offset); + + /* + * Copy HS BL header where the HS descriptor expects it to be + */ + nvkm_falcon_load_dmem(falcon, bl_desc, hsbl_desc->dmem_load_off, + bl_desc_size, 0); + + return 0; +} + +/* + * acr_r352_reset() - execute secure boot from the prepared state + * + * Load the HS bootloader and ask the falcon to run it. This will in turn + * load the HS firmware and run it, so once the falcon stops all the managed + * falcons should have their LS firmware loaded and be ready to run. + */ +static int +acr_r352_reset(struct nvkm_acr *_acr, struct nvkm_secboot *sb, + enum nvkm_secboot_falcon falcon) +{ + struct acr_r352 *acr = acr_r352(_acr); + int ret; + + /* Make sure all blobs are ready */ + ret = acr_r352_load_blobs(acr, sb); + if (ret) + return ret; + + /* + * Dummy GM200 implementation: perform secure boot each time we are + * called on FECS. Since only FECS and GPCCS are managed and started + * together, this ought to be safe. + * + * Once we have proper PMU firmware and support, this will be changed + * to a proper call to the PMU method. + */ + if (falcon != NVKM_SECBOOT_FALCON_FECS) + goto end; + + /* If WPR is set and we have an unload blob, run it to unlock WPR */ + if (acr->unload_blob && + acr->falcon_state[NVKM_SECBOOT_FALCON_FECS] != NON_SECURE) { + ret = sb->func->run_blob(sb, acr->unload_blob); + if (ret) + return ret; + } + + /* Reload all managed falcons */ + ret = sb->func->run_blob(sb, acr->load_blob); + if (ret) + return ret; + +end: + acr->falcon_state[falcon] = RESET; + return 0; +} + +static int +acr_r352_start(struct nvkm_acr *_acr, struct nvkm_secboot *sb, + enum nvkm_secboot_falcon falcon) +{ + struct acr_r352 *acr = acr_r352(_acr); + const struct nvkm_subdev *subdev = &sb->subdev; + int base; + + switch (falcon) { + case NVKM_SECBOOT_FALCON_FECS: + base = 0x409000; + break; + case NVKM_SECBOOT_FALCON_GPCCS: + base = 0x41a000; + break; + default: + nvkm_error(subdev, "cannot start unhandled falcon!\n"); + return -EINVAL; + } + + nvkm_wr32(subdev->device, base + 0x130, 0x00000002); + acr->falcon_state[falcon] = RUNNING; + + return 0; +} + +static int +acr_r352_fini(struct nvkm_acr *_acr, struct nvkm_secboot *sb, bool suspend) +{ + struct acr_r352 *acr = acr_r352(_acr); + int ret = 0; + int i; + + /* Run the unload blob to unprotect the WPR region */ + if (acr->unload_blob && + acr->falcon_state[NVKM_SECBOOT_FALCON_FECS] != NON_SECURE) + ret = sb->func->run_blob(sb, acr->unload_blob); + + for (i = 0; i < NVKM_SECBOOT_FALCON_END; i++) + acr->falcon_state[i] = NON_SECURE; + + return ret; +} + +static void +acr_r352_dtor(struct nvkm_acr *_acr) +{ + struct acr_r352 *acr = acr_r352(_acr); + + nvkm_gpuobj_del(&acr->unload_blob); + + kfree(acr->hsbl_blob); + nvkm_gpuobj_del(&acr->load_blob); + nvkm_gpuobj_del(&acr->ls_blob); + + kfree(acr); +} + +const struct acr_r352_ls_func +acr_r352_ls_fecs_func = { + .load = acr_ls_ucode_load_fecs, + .generate_bl_desc = acr_r352_generate_flcn_bl_desc, + .bl_desc_size = sizeof(struct acr_r352_flcn_bl_desc), +}; + +const struct acr_r352_ls_func +acr_r352_ls_gpccs_func = { + .load = acr_ls_ucode_load_gpccs, + .generate_bl_desc = acr_r352_generate_flcn_bl_desc, + .bl_desc_size = sizeof(struct acr_r352_flcn_bl_desc), +}; + +const struct acr_r352_func +acr_r352_func = { + .generate_hs_bl_desc = acr_r352_generate_hs_bl_desc, + .hs_bl_desc_size = sizeof(struct acr_r352_flcn_bl_desc), + .ls_func = { + [NVKM_SECBOOT_FALCON_FECS] = &acr_r352_ls_fecs_func, + [NVKM_SECBOOT_FALCON_GPCCS] = &acr_r352_ls_gpccs_func, + }, +}; + +static const struct nvkm_acr_func +acr_r352_base_func = { + .dtor = acr_r352_dtor, + .fini = acr_r352_fini, + .load = acr_r352_load, + .reset = acr_r352_reset, + .start = acr_r352_start, +}; + +struct nvkm_acr * +acr_r352_new_(const struct acr_r352_func *func, + enum nvkm_secboot_falcon boot_falcon, + unsigned long managed_falcons) +{ + struct acr_r352 *acr; + + acr = kzalloc(sizeof(*acr), GFP_KERNEL); + if (!acr) + return ERR_PTR(-ENOMEM); + + acr->base.boot_falcon = boot_falcon; + acr->base.managed_falcons = managed_falcons; + acr->base.func = &acr_r352_base_func; + acr->func = func; + + return &acr->base; +} + +struct nvkm_acr * +acr_r352_new(unsigned long managed_falcons) +{ + return acr_r352_new_(&acr_r352_func, NVKM_SECBOOT_FALCON_PMU, + managed_falcons); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.h b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.h new file mode 100644 index 0000000..031bd09f --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.h @@ -0,0 +1,126 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __NVKM_SECBOOT_ACR_R352_H__ +#define __NVKM_SECBOOT_ACR_R352_H__ + +#include "acr.h" + +struct ls_ucode_img; + +#define ACR_R352_MAX_APPS 8 + +struct hsf_load_header_app { + u32 sec_code_off; + u32 sec_code_size; +}; + +/** + * struct hsf_load_header - HS firmware load header + */ +struct hsf_load_header { + u32 non_sec_code_off; + u32 non_sec_code_size; + u32 data_dma_base; + u32 data_size; + u32 num_apps; + struct hsf_load_header_app app[0]; +}; + +/** + * struct acr_r352_ls_func - manages a single LS firmware + * + * @load: load the external firmware into a ls_ucode_img + * @generate_bl_desc: function called on a block of bl_desc_size to generate the + * proper bootloader descriptor for this LS firmware + * @bl_desc_size: size of the bootloader descriptor + */ +struct acr_r352_ls_func { + int (*load)(const struct nvkm_subdev *, struct ls_ucode_img *); + void (*generate_bl_desc)(const struct nvkm_acr *, + const struct ls_ucode_img *, u64, void *); + u32 bl_desc_size; +}; + +/** + * struct acr_r352_func - manages nuances between ACR versions + * + * @generate_hs_bl_desc: function called on a block of bl_desc_size to generate + * the proper HS bootloader descriptor + * @hs_bl_desc_size: size of the HS bootloader descriptor + */ +struct acr_r352_func { + void (*generate_hs_bl_desc)(const struct hsf_load_header *, void *, + u64); + u32 hs_bl_desc_size; + + const struct acr_r352_ls_func *ls_func[NVKM_SECBOOT_FALCON_END]; +}; + +/** + * struct acr_r352 - ACR data for driver release 352 (and beyond) + */ +struct acr_r352 { + struct nvkm_acr base; + const struct acr_r352_func *func; + + /* + * HS FW - lock WPR region (dGPU only) and load LS FWs + * on Tegra the HS FW copies the LS blob into the fixed WPR instead + */ + struct nvkm_gpuobj *load_blob; + struct { + struct hsf_load_header load_bl_header; + struct hsf_load_header_app __load_apps[ACR_R352_MAX_APPS]; + }; + + /* HS FW - unlock WPR region (dGPU only) */ + struct nvkm_gpuobj *unload_blob; + struct { + struct hsf_load_header unload_bl_header; + struct hsf_load_header_app __unload_apps[ACR_R352_MAX_APPS]; + }; + + /* HS bootloader */ + void *hsbl_blob; + + /* LS FWs, to be loaded by the HS ACR */ + struct nvkm_gpuobj *ls_blob; + + /* Firmware already loaded? */ + bool firmware_ok; + + /* To keep track of the state of all managed falcons */ + enum { + /* In non-secure state, no firmware loaded, no privileges*/ + NON_SECURE = 0, + /* In low-secure mode and ready to be started */ + RESET, + /* In low-secure mode and running */ + RUNNING, + } falcon_state[NVKM_SECBOOT_FALCON_END]; +}; +#define acr_r352(acr) container_of(acr, struct acr_r352, base) + +struct nvkm_acr *acr_r352_new_(const struct acr_r352_func *, + enum nvkm_secboot_falcon, unsigned long); + +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c new file mode 100644 index 0000000..ec1c558 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "acr_r352.h" +#include "ls_ucode.h" + +#include + +/** + * struct acr_r361_flcn_bl_desc - DMEM bootloader descriptor + * @signature: 16B signature for secure code. 0s if no secure code + * @ctx_dma: DMA context to be used by BL while loading code/data + * @code_dma_base: 256B-aligned Physical FB Address where code is located + * (falcon's $xcbase register) + * @non_sec_code_off: offset from code_dma_base where the non-secure code is + * located. The offset must be multiple of 256 to help perf + * @non_sec_code_size: the size of the nonSecure code part. + * @sec_code_off: offset from code_dma_base where the secure code is + * located. The offset must be multiple of 256 to help perf + * @sec_code_size: offset from code_dma_base where the secure code is + * located. The offset must be multiple of 256 to help perf + * @code_entry_point: code entry point which will be invoked by BL after + * code is loaded. + * @data_dma_base: 256B aligned Physical FB Address where data is located. + * (falcon's $xdbase register) + * @data_size: size of data block. Should be multiple of 256B + * + * Structure used by the bootloader to load the rest of the code. This has + * to be filled by host and copied into DMEM at offset provided in the + * hsflcn_bl_desc.bl_desc_dmem_load_off. + */ +struct acr_r361_flcn_bl_desc { + u32 reserved[4]; + u32 signature[4]; + u32 ctx_dma; + struct flcn_u64 code_dma_base; + u32 non_sec_code_off; + u32 non_sec_code_size; + u32 sec_code_off; + u32 sec_code_size; + u32 code_entry_point; + struct flcn_u64 data_dma_base; + u32 data_size; +}; + +static void +acr_r361_generate_flcn_bl_desc(const struct nvkm_acr *acr, + const struct ls_ucode_img *img, u64 wpr_addr, + void *_desc) +{ + struct acr_r361_flcn_bl_desc *desc = _desc; + const struct ls_ucode_img_desc *pdesc = &img->ucode_desc; + u64 base, addr_code, addr_data; + + base = wpr_addr + img->lsb_header.ucode_off + pdesc->app_start_offset; + addr_code = base + pdesc->app_resident_code_offset; + addr_data = base + pdesc->app_resident_data_offset; + + memset(desc, 0, sizeof(*desc)); + desc->ctx_dma = FALCON_DMAIDX_UCODE; + desc->code_dma_base = u64_to_flcn64(addr_code); + desc->non_sec_code_off = pdesc->app_resident_code_offset; + desc->non_sec_code_size = pdesc->app_resident_code_size; + desc->code_entry_point = pdesc->app_imem_entry; + desc->data_dma_base = u64_to_flcn64(addr_data); + desc->data_size = pdesc->app_resident_data_size; +} + +static void +acr_r361_generate_hs_bl_desc(const struct hsf_load_header *hdr, void *_bl_desc, + u64 offset) +{ + struct acr_r361_flcn_bl_desc *bl_desc = _bl_desc; + + memset(bl_desc, 0, sizeof(*bl_desc)); + bl_desc->ctx_dma = FALCON_DMAIDX_VIRT; + bl_desc->code_dma_base = u64_to_flcn64(offset); + bl_desc->non_sec_code_off = hdr->non_sec_code_off; + bl_desc->non_sec_code_size = hdr->non_sec_code_size; + bl_desc->sec_code_off = hdr->app[0].sec_code_off; + bl_desc->sec_code_size = hdr->app[0].sec_code_size; + bl_desc->code_entry_point = 0; + bl_desc->data_dma_base = u64_to_flcn64(offset + hdr->data_dma_base); + bl_desc->data_size = hdr->data_size; +} + +const struct acr_r352_ls_func +acr_r361_ls_fecs_func = { + .load = acr_ls_ucode_load_fecs, + .generate_bl_desc = acr_r361_generate_flcn_bl_desc, + .bl_desc_size = sizeof(struct acr_r361_flcn_bl_desc), +}; + +const struct acr_r352_ls_func +acr_r361_ls_gpccs_func = { + .load = acr_ls_ucode_load_gpccs, + .generate_bl_desc = acr_r361_generate_flcn_bl_desc, + .bl_desc_size = sizeof(struct acr_r361_flcn_bl_desc), +}; + +const struct acr_r352_func +acr_r361_func = { + .generate_hs_bl_desc = acr_r361_generate_hs_bl_desc, + .hs_bl_desc_size = sizeof(struct acr_r361_flcn_bl_desc), + .ls_func = { + [NVKM_SECBOOT_FALCON_FECS] = &acr_r361_ls_fecs_func, + [NVKM_SECBOOT_FALCON_GPCCS] = &acr_r361_ls_gpccs_func, + }, +}; + +struct nvkm_acr * +acr_r361_new(unsigned long managed_falcons) +{ + return acr_r352_new_(&acr_r361_func, NVKM_SECBOOT_FALCON_PMU, + managed_falcons); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c index 525740e..ad739c6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c @@ -19,7 +19,70 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ + +/* + * Secure boot is the process by which NVIDIA-signed firmware is loaded into + * some of the falcons of a GPU. For production devices this is the only way + * for the firmware to access useful (but sensitive) registers. + * + * A Falcon microprocessor supporting advanced security modes can run in one of + * three modes: + * + * - Non-secure (NS). In this mode, functionality is similar to Falcon + * architectures before security modes were introduced (pre-Maxwell), but + * capability is restricted. In particular, certain registers may be + * inaccessible for reads and/or writes, and physical memory access may be + * disabled (on certain Falcon instances). This is the only possible mode that + * can be used if you don't have microcode cryptographically signed by NVIDIA. + * + * - Heavy Secure (HS). In this mode, the microprocessor is a black box - it's + * not possible to read or write any Falcon internal state or Falcon registers + * from outside the Falcon (for example, from the host system). The only way + * to enable this mode is by loading microcode that has been signed by NVIDIA. + * (The loading process involves tagging the IMEM block as secure, writing the + * signature into a Falcon register, and starting execution. The hardware will + * validate the signature, and if valid, grant HS privileges.) + * + * - Light Secure (LS). In this mode, the microprocessor has more privileges + * than NS but fewer than HS. Some of the microprocessor state is visible to + * host software to ease debugging. The only way to enable this mode is by HS + * microcode enabling LS mode. Some privileges available to HS mode are not + * available here. LS mode is introduced in GM20x. + * + * Secure boot consists in temporarily switching a HS-capable falcon (typically + * PMU) into HS mode in order to validate the LS firmwares of managed falcons, + * load them, and switch managed falcons into LS mode. Once secure boot + * completes, no falcon remains in HS mode. + * + * Secure boot requires a write-protected memory region (WPR) which can only be + * written by the secure falcon. On dGPU, the driver sets up the WPR region in + * video memory. On Tegra, it is set up by the bootloader and its location and + * size written into memory controller registers. + * + * The secure boot process takes place as follows: + * + * 1) A LS blob is constructed that contains all the LS firmwares we want to + * load, along with their signatures and bootloaders. + * + * 2) A HS blob (also called ACR) is created that contains the signed HS + * firmware in charge of loading the LS firmwares into their respective + * falcons. + * + * 3) The HS blob is loaded (via its own bootloader) and executed on the + * HS-capable falcon. It authenticates itself, switches the secure falcon to + * HS mode and setup the WPR region around the LS blob (dGPU) or copies the + * LS blob into the WPR region (Tegra). + * + * 4) The LS blob is now secure from all external tampering. The HS falcon + * checks the signatures of the LS firmwares and, if valid, switches the + * managed falcons to LS mode and makes them ready to run the LS firmware. + * + * 5) The managed falcons remain in LS mode and can be started. + * + */ + #include "priv.h" +#include "acr.h" #include #include @@ -40,25 +103,24 @@ int nvkm_secboot_reset(struct nvkm_secboot *sb, enum nvkm_secboot_falcon falcon) { /* Unmanaged falcon? */ - if (!(BIT(falcon) & sb->func->managed_falcons)) { + if (!(BIT(falcon) & sb->acr->managed_falcons)) { nvkm_error(&sb->subdev, "cannot reset unmanaged falcon!\n"); return -EINVAL; } - return sb->func->reset(sb, falcon); + return sb->acr->func->reset(sb->acr, sb, falcon); } /** * nvkm_secboot_is_managed() - check whether a given falcon is securely-managed */ bool -nvkm_secboot_is_managed(struct nvkm_secboot *secboot, - enum nvkm_secboot_falcon fid) +nvkm_secboot_is_managed(struct nvkm_secboot *sb, enum nvkm_secboot_falcon fid) { - if (!secboot) + if (!sb) return false; - return secboot->func->managed_falcons & BIT(fid); + return sb->acr->managed_falcons & BIT(fid); } static int @@ -67,13 +129,13 @@ nvkm_secboot_oneinit(struct nvkm_subdev *subdev) struct nvkm_secboot *sb = nvkm_secboot(subdev); int ret = 0; - switch (sb->func->boot_falcon) { + switch (sb->acr->boot_falcon) { case NVKM_SECBOOT_FALCON_PMU: sb->boot_falcon = subdev->device->pmu->falcon; break; default: nvkm_error(subdev, "Unmanaged boot falcon %s!\n", - managed_falcons_names[sb->func->boot_falcon]); + managed_falcons_names[sb->acr->boot_falcon]); return -EINVAL; } @@ -121,7 +183,7 @@ nvkm_secboot = { }; int -nvkm_secboot_ctor(const struct nvkm_secboot_func *func, +nvkm_secboot_ctor(const struct nvkm_secboot_func *func, struct nvkm_acr *acr, struct nvkm_device *device, int index, struct nvkm_secboot *sb) { @@ -129,9 +191,11 @@ nvkm_secboot_ctor(const struct nvkm_secboot_func *func, nvkm_subdev_ctor(&nvkm_secboot, device, index, &sb->subdev); sb->func = func; + sb->acr = acr; + acr->subdev = &sb->subdev; nvkm_debug(&sb->subdev, "securely managed falcons:\n"); - for_each_set_bit(fid, &sb->func->managed_falcons, + for_each_set_bit(fid, &sb->acr->managed_falcons, NVKM_SECBOOT_FALCON_END) nvkm_debug(&sb->subdev, "- %s\n", managed_falcons_names[fid]); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c index fd82203..f6a11e2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c @@ -20,1045 +20,27 @@ * DEALINGS IN THE SOFTWARE. */ -/* - * Secure boot is the process by which NVIDIA-signed firmware is loaded into - * some of the falcons of a GPU. For production devices this is the only way - * for the firmware to access useful (but sensitive) registers. - * - * A Falcon microprocessor supporting advanced security modes can run in one of - * three modes: - * - * - Non-secure (NS). In this mode, functionality is similar to Falcon - * architectures before security modes were introduced (pre-Maxwell), but - * capability is restricted. In particular, certain registers may be - * inaccessible for reads and/or writes, and physical memory access may be - * disabled (on certain Falcon instances). This is the only possible mode that - * can be used if you don't have microcode cryptographically signed by NVIDIA. - * - * - Heavy Secure (HS). In this mode, the microprocessor is a black box - it's - * not possible to read or write any Falcon internal state or Falcon registers - * from outside the Falcon (for example, from the host system). The only way - * to enable this mode is by loading microcode that has been signed by NVIDIA. - * (The loading process involves tagging the IMEM block as secure, writing the - * signature into a Falcon register, and starting execution. The hardware will - * validate the signature, and if valid, grant HS privileges.) - * - * - Light Secure (LS). In this mode, the microprocessor has more privileges - * than NS but fewer than HS. Some of the microprocessor state is visible to - * host software to ease debugging. The only way to enable this mode is by HS - * microcode enabling LS mode. Some privileges available to HS mode are not - * available here. LS mode is introduced in GM20x. - * - * Secure boot consists in temporarily switching a HS-capable falcon (typically - * PMU) into HS mode in order to validate the LS firmwares of managed falcons, - * load them, and switch managed falcons into LS mode. Once secure boot - * completes, no falcon remains in HS mode. - * - * Secure boot requires a write-protected memory region (WPR) which can only be - * written by the secure falcon. On dGPU, the driver sets up the WPR region in - * video memory. On Tegra, it is set up by the bootloader and its location and - * size written into memory controller registers. - * - * The secure boot process takes place as follows: - * - * 1) A LS blob is constructed that contains all the LS firmwares we want to - * load, along with their signatures and bootloaders. - * - * 2) A HS blob (also called ACR) is created that contains the signed HS - * firmware in charge of loading the LS firmwares into their respective - * falcons. - * - * 3) The HS blob is loaded (via its own bootloader) and executed on the - * HS-capable falcon. It authenticates itself, switches the secure falcon to - * HS mode and setup the WPR region around the LS blob (dGPU) or copies the - * LS blob into the WPR region (Tegra). - * - * 4) The LS blob is now secure from all external tampering. The HS falcon - * checks the signatures of the LS firmwares and, if valid, switches the - * managed falcons to LS mode and makes them ready to run the LS firmware. - * - * 5) The managed falcons remain in LS mode and can be started. - * - */ -#include "priv.h" +#include "acr.h" +#include "gm200.h" #include -#include #include #include /** - * struct fw_bin_header - header of firmware files - * @bin_magic: always 0x3b1d14f0 - * @bin_ver: version of the bin format - * @bin_size: entire image size including this header - * @header_offset: offset of the firmware/bootloader header in the file - * @data_offset: offset of the firmware/bootloader payload in the file - * @data_size: size of the payload - * - * This header is located at the beginning of the HS firmware and HS bootloader - * files, to describe where the headers and data can be found. - */ -struct fw_bin_header { - u32 bin_magic; - u32 bin_ver; - u32 bin_size; - u32 header_offset; - u32 data_offset; - u32 data_size; -}; - -/** - * struct fw_bl_desc - firmware bootloader descriptor - * @start_tag: starting tag of bootloader - * @desc_dmem_load_off: DMEM offset of flcn_bl_dmem_desc - * @code_off: offset of code section - * @code_size: size of code section - * @data_off: offset of data section - * @data_size: size of data section - * - * This structure is embedded in bootloader firmware files at to describe the - * IMEM and DMEM layout expected by the bootloader. - */ -struct fw_bl_desc { - u32 start_tag; - u32 dmem_load_off; - u32 code_off; - u32 code_size; - u32 data_off; - u32 data_size; -}; - - -/** - * struct ls_ucode_mgr - manager for all LS falcon firmwares - * @count: number of managed LS falcons - * @wpr_size: size of the required WPR region in bytes - * @img_list: linked list of lsf_ucode_img - */ -struct ls_ucode_mgr { - u16 count; - u32 wpr_size; - struct list_head img_list; -}; - - -/* - * - * HS blob structures - * - */ - -/** - * struct hsf_fw_header - HS firmware descriptor - * @sig_dbg_offset: offset of the debug signature - * @sig_dbg_size: size of the debug signature - * @sig_prod_offset: offset of the production signature - * @sig_prod_size: size of the production signature - * @patch_loc: offset of the offset (sic) of where the signature is - * @patch_sig: offset of the offset (sic) to add to sig_*_offset - * @hdr_offset: offset of the load header (see struct hs_load_header) - * @hdr_size: size of above header - * - * This structure is embedded in the HS firmware image at - * hs_bin_hdr.header_offset. - */ -struct hsf_fw_header { - u32 sig_dbg_offset; - u32 sig_dbg_size; - u32 sig_prod_offset; - u32 sig_prod_size; - u32 patch_loc; - u32 patch_sig; - u32 hdr_offset; - u32 hdr_size; -}; - - -/** - * struct gm200_flcn_bl_desc - DMEM bootloader descriptor - * @signature: 16B signature for secure code. 0s if no secure code - * @ctx_dma: DMA context to be used by BL while loading code/data - * @code_dma_base: 256B-aligned Physical FB Address where code is located - * (falcon's $xcbase register) - * @non_sec_code_off: offset from code_dma_base where the non-secure code is - * located. The offset must be multiple of 256 to help perf - * @non_sec_code_size: the size of the nonSecure code part. - * @sec_code_off: offset from code_dma_base where the secure code is - * located. The offset must be multiple of 256 to help perf - * @sec_code_size: offset from code_dma_base where the secure code is - * located. The offset must be multiple of 256 to help perf - * @code_entry_point: code entry point which will be invoked by BL after - * code is loaded. - * @data_dma_base: 256B aligned Physical FB Address where data is located. - * (falcon's $xdbase register) - * @data_size: size of data block. Should be multiple of 256B - * - * Structure used by the bootloader to load the rest of the code. This has - * to be filled by host and copied into DMEM at offset provided in the - * hsflcn_bl_desc.bl_desc_dmem_load_off. - */ -struct gm200_flcn_bl_desc { - u32 reserved[4]; - u32 signature[4]; - u32 ctx_dma; - struct flcn_u64 code_dma_base; - u32 non_sec_code_off; - u32 non_sec_code_size; - u32 sec_code_off; - u32 sec_code_size; - u32 code_entry_point; - struct flcn_u64 data_dma_base; - u32 data_size; -}; - - -/** - * Convenience function to duplicate a firmware file in memory and check that - * it has the required minimum size. - */ -static void * -gm200_secboot_load_firmware(const struct nvkm_subdev *subdev, const char *name, - size_t min_size) -{ - const struct firmware *fw; - void *blob; - int ret; - - ret = nvkm_firmware_get(subdev->device, name, &fw); - if (ret) - return ERR_PTR(ret); - if (fw->size < min_size) { - nvkm_error(subdev, "%s is smaller than expected size %zu\n", - name, min_size); - nvkm_firmware_put(fw); - return ERR_PTR(-EINVAL); - } - blob = kmemdup(fw->data, fw->size, GFP_KERNEL); - nvkm_firmware_put(fw); - if (!blob) - return ERR_PTR(-ENOMEM); - - return blob; -} - - -/* - * Low-secure blob creation - */ - -#define BL_DESC_BLK_SIZE 256 -/** - * Build a ucode image and descriptor from provided bootloader, code and data. - * - * @bl: bootloader image, including 16-bytes descriptor - * @code: LS firmware code segment - * @data: LS firmware data segment - * @desc: ucode descriptor to be written - * - * Return: allocated ucode image with corresponding descriptor information. desc - * is also updated to contain the right offsets within returned image. - */ -static void * -ls_ucode_img_build(const struct firmware *bl, const struct firmware *code, - const struct firmware *data, struct ls_ucode_img_desc *desc) -{ - struct fw_bin_header *bin_hdr = (void *)bl->data; - struct fw_bl_desc *bl_desc = (void *)bl->data + bin_hdr->header_offset; - void *bl_data = (void *)bl->data + bin_hdr->data_offset; - u32 pos = 0; - void *image; - - desc->bootloader_start_offset = pos; - desc->bootloader_size = ALIGN(bl_desc->code_size, sizeof(u32)); - desc->bootloader_imem_offset = bl_desc->start_tag * 256; - desc->bootloader_entry_point = bl_desc->start_tag * 256; - - pos = ALIGN(pos + desc->bootloader_size, BL_DESC_BLK_SIZE); - desc->app_start_offset = pos; - desc->app_size = ALIGN(code->size, BL_DESC_BLK_SIZE) + - ALIGN(data->size, BL_DESC_BLK_SIZE); - desc->app_imem_offset = 0; - desc->app_imem_entry = 0; - desc->app_dmem_offset = 0; - desc->app_resident_code_offset = 0; - desc->app_resident_code_size = ALIGN(code->size, BL_DESC_BLK_SIZE); - - pos = ALIGN(pos + desc->app_resident_code_size, BL_DESC_BLK_SIZE); - desc->app_resident_data_offset = pos - desc->app_start_offset; - desc->app_resident_data_size = ALIGN(data->size, BL_DESC_BLK_SIZE); - - desc->image_size = ALIGN(bl_desc->code_size, BL_DESC_BLK_SIZE) + - desc->app_size; - - image = kzalloc(desc->image_size, GFP_KERNEL); - if (!image) - return ERR_PTR(-ENOMEM); - - memcpy(image + desc->bootloader_start_offset, bl_data, - bl_desc->code_size); - memcpy(image + desc->app_start_offset, code->data, code->size); - memcpy(image + desc->app_start_offset + desc->app_resident_data_offset, - data->data, data->size); - - return image; -} - -/** - * ls_ucode_img_load_generic() - load and prepare a LS ucode image - * - * Load the LS microcode, bootloader and signature and pack them into a single - * blob. Also generate the corresponding ucode descriptor. - */ -static int -ls_ucode_img_load_generic(const struct nvkm_subdev *subdev, - struct ls_ucode_img *img, const char *falcon_name, - const u32 falcon_id) -{ - const struct firmware *bl, *code, *data; - struct lsf_ucode_desc *lsf_desc; - char f[64]; - int ret; - - img->ucode_header = NULL; - - snprintf(f, sizeof(f), "gr/%s_bl", falcon_name); - ret = nvkm_firmware_get(subdev->device, f, &bl); - if (ret) - goto error; - - snprintf(f, sizeof(f), "gr/%s_inst", falcon_name); - ret = nvkm_firmware_get(subdev->device, f, &code); - if (ret) - goto free_bl; - - snprintf(f, sizeof(f), "gr/%s_data", falcon_name); - ret = nvkm_firmware_get(subdev->device, f, &data); - if (ret) - goto free_inst; - - img->ucode_data = ls_ucode_img_build(bl, code, data, - &img->ucode_desc); - if (IS_ERR(img->ucode_data)) { - ret = PTR_ERR(img->ucode_data); - goto free_data; - } - img->ucode_size = img->ucode_desc.image_size; - - snprintf(f, sizeof(f), "gr/%s_sig", falcon_name); - lsf_desc = gm200_secboot_load_firmware(subdev, f, sizeof(*lsf_desc)); - if (IS_ERR(lsf_desc)) { - ret = PTR_ERR(lsf_desc); - goto free_image; - } - /* not needed? the signature should already have the right value */ - lsf_desc->falcon_id = falcon_id; - memcpy(&img->lsb_header.signature, lsf_desc, sizeof(*lsf_desc)); - img->falcon_id = lsf_desc->falcon_id; - kfree(lsf_desc); - - /* success path - only free requested firmware files */ - goto free_data; - -free_image: - kfree(img->ucode_data); -free_data: - nvkm_firmware_put(data); -free_inst: - nvkm_firmware_put(code); -free_bl: - nvkm_firmware_put(bl); -error: - return ret; -} - -typedef int (*lsf_load_func)(const struct nvkm_subdev *, struct ls_ucode_img *); - -int -gm200_ls_load_fecs(const struct nvkm_subdev *subdev, struct ls_ucode_img *img) -{ - return ls_ucode_img_load_generic(subdev, img, "fecs", - NVKM_SECBOOT_FALCON_FECS); -} - -int -gm200_ls_load_gpccs(const struct nvkm_subdev *subdev, struct ls_ucode_img *img) -{ - return ls_ucode_img_load_generic(subdev, img, "gpccs", - NVKM_SECBOOT_FALCON_GPCCS); -} - -/** - * ls_ucode_img_load() - create a lsf_ucode_img and load it - */ -static struct ls_ucode_img * -ls_ucode_img_load(struct nvkm_subdev *subdev, lsf_load_func load_func) -{ - struct ls_ucode_img *img; - int ret; - - img = kzalloc(sizeof(*img), GFP_KERNEL); - if (!img) - return ERR_PTR(-ENOMEM); - - ret = load_func(subdev, img); - if (ret) { - kfree(img); - return ERR_PTR(ret); - } - - return img; -} - -/** - * gm200_secboot_ls_bl_desc() - populate a DMEM BL descriptor for LS image - * @img: ucode image to generate against - * @desc: descriptor to populate - * @sb: secure boot state to use for base addresses - * - * Populate the DMEM BL descriptor with the information contained in a - * ls_ucode_desc. - * - */ -static void -gm200_secboot_ls_bl_desc(const struct ls_ucode_img *img, u64 wpr_addr, - void *_desc) -{ - struct gm200_flcn_bl_desc *desc = _desc; - const struct ls_ucode_img_desc *pdesc = &img->ucode_desc; - u64 addr_base; - - addr_base = wpr_addr + img->lsb_header.ucode_off + - pdesc->app_start_offset; - - memset(desc, 0, sizeof(*desc)); - desc->ctx_dma = FALCON_DMAIDX_UCODE; - desc->code_dma_base.lo = lower_32_bits( - (addr_base + pdesc->app_resident_code_offset)); - desc->code_dma_base.hi = upper_32_bits( - (addr_base + pdesc->app_resident_code_offset)); - desc->non_sec_code_size = pdesc->app_resident_code_size; - desc->data_dma_base.lo = lower_32_bits( - (addr_base + pdesc->app_resident_data_offset)); - desc->data_dma_base.hi = upper_32_bits( - (addr_base + pdesc->app_resident_data_offset)); - desc->data_size = pdesc->app_resident_data_size; - desc->code_entry_point = pdesc->app_imem_entry; -} - -#define LSF_LSB_HEADER_ALIGN 256 -#define LSF_BL_DATA_ALIGN 256 -#define LSF_BL_DATA_SIZE_ALIGN 256 -#define LSF_BL_CODE_SIZE_ALIGN 256 -#define LSF_UCODE_DATA_ALIGN 4096 - -/** - * ls_ucode_img_fill_headers - fill the WPR and LSB headers of an image - * @gsb: secure boot device used - * @img: image to generate for - * @offset: offset in the WPR region where this image starts - * - * Allocate space in the WPR area from offset and write the WPR and LSB headers - * accordingly. - * - * Return: offset at the end of this image. - */ -static u32 -ls_ucode_img_fill_headers(struct gm200_secboot *gsb, struct ls_ucode_img *img, - u32 offset) -{ - struct lsf_wpr_header *whdr = &img->wpr_header; - struct lsf_lsb_header *lhdr = &img->lsb_header; - struct ls_ucode_img_desc *desc = &img->ucode_desc; - const struct secboot_ls_single_func *func = - (*gsb->ls_func)[img->falcon_id]; - - if (img->ucode_header) { - nvkm_fatal(&gsb->base.subdev, - "images withough loader are not supported yet!\n"); - return offset; - } - - /* Fill WPR header */ - whdr->falcon_id = img->falcon_id; - whdr->bootstrap_owner = gsb->base.func->boot_falcon; - whdr->status = LSF_IMAGE_STATUS_COPY; - - /* Align, save off, and include an LSB header size */ - offset = ALIGN(offset, LSF_LSB_HEADER_ALIGN); - whdr->lsb_offset = offset; - offset += sizeof(struct lsf_lsb_header); - - /* - * Align, save off, and include the original (static) ucode - * image size - */ - offset = ALIGN(offset, LSF_UCODE_DATA_ALIGN); - lhdr->ucode_off = offset; - offset += img->ucode_size; - - /* - * For falcons that use a boot loader (BL), we append a loader - * desc structure on the end of the ucode image and consider - * this the boot loader data. The host will then copy the loader - * desc args to this space within the WPR region (before locking - * down) and the HS bin will then copy them to DMEM 0 for the - * loader. - */ - lhdr->bl_code_size = ALIGN(desc->bootloader_size, - LSF_BL_CODE_SIZE_ALIGN); - lhdr->ucode_size = ALIGN(desc->app_resident_data_offset, - LSF_BL_CODE_SIZE_ALIGN) + lhdr->bl_code_size; - lhdr->data_size = ALIGN(desc->app_size, LSF_BL_CODE_SIZE_ALIGN) + - lhdr->bl_code_size - lhdr->ucode_size; - /* - * Though the BL is located at 0th offset of the image, the VA - * is different to make sure that it doesn't collide the actual - * OS VA range - */ - lhdr->bl_imem_off = desc->bootloader_imem_offset; - lhdr->app_code_off = desc->app_start_offset + - desc->app_resident_code_offset; - lhdr->app_code_size = desc->app_resident_code_size; - lhdr->app_data_off = desc->app_start_offset + - desc->app_resident_data_offset; - lhdr->app_data_size = desc->app_resident_data_size; - - lhdr->flags = 0; - if (img->falcon_id == gsb->base.func->boot_falcon) - lhdr->flags = LSF_FLAG_DMACTL_REQ_CTX; - - /* GPCCS will be loaded using PRI */ - if (img->falcon_id == NVKM_SECBOOT_FALCON_GPCCS) - lhdr->flags |= LSF_FLAG_FORCE_PRIV_LOAD; - - /* Align and save off BL descriptor size */ - lhdr->bl_data_size = ALIGN(func->bl_desc_size, LSF_BL_DATA_SIZE_ALIGN); - - /* - * Align, save off, and include the additional BL data - */ - offset = ALIGN(offset, LSF_BL_DATA_ALIGN); - lhdr->bl_data_off = offset; - offset += lhdr->bl_data_size; - - return offset; -} - -static void -ls_ucode_mgr_init(struct ls_ucode_mgr *mgr) -{ - memset(mgr, 0, sizeof(*mgr)); - INIT_LIST_HEAD(&mgr->img_list); -} - -static void -ls_ucode_mgr_cleanup(struct ls_ucode_mgr *mgr) -{ - struct ls_ucode_img *img, *t; - - list_for_each_entry_safe(img, t, &mgr->img_list, node) { - kfree(img->ucode_data); - kfree(img->ucode_header); - kfree(img); - } -} - -static void -ls_ucode_mgr_add_img(struct ls_ucode_mgr *mgr, struct ls_ucode_img *img) -{ - mgr->count++; - list_add_tail(&img->node, &mgr->img_list); -} - -/** - * ls_ucode_mgr_fill_headers - fill WPR and LSB headers of all managed images - */ -static void -ls_ucode_mgr_fill_headers(struct gm200_secboot *gsb, struct ls_ucode_mgr *mgr) -{ - struct ls_ucode_img *img; - u32 offset; - - /* - * Start with an array of WPR headers at the base of the WPR. - * The expectation here is that the secure falcon will do a single DMA - * read of this array and cache it internally so it's ok to pack these. - * Also, we add 1 to the falcon count to indicate the end of the array. - */ - offset = sizeof(struct lsf_wpr_header) * (mgr->count + 1); - - /* - * Walk the managed falcons, accounting for the LSB structs - * as well as the ucode images. - */ - list_for_each_entry(img, &mgr->img_list, node) { - offset = ls_ucode_img_fill_headers(gsb, img, offset); - } - - mgr->wpr_size = offset; -} - -/** - * ls_ucode_mgr_write_wpr - write the WPR blob contents - */ -static int -ls_ucode_mgr_write_wpr(struct gm200_secboot *gsb, struct ls_ucode_mgr *mgr, - struct nvkm_gpuobj *wpr_blob) -{ - struct ls_ucode_img *img; - u32 pos = 0; - - nvkm_kmap(wpr_blob); - - list_for_each_entry(img, &mgr->img_list, node) { - nvkm_gpuobj_memcpy_to(wpr_blob, pos, &img->wpr_header, - sizeof(img->wpr_header)); - - nvkm_gpuobj_memcpy_to(wpr_blob, img->wpr_header.lsb_offset, - &img->lsb_header, sizeof(img->lsb_header)); - - /* Generate and write BL descriptor */ - if (!img->ucode_header) { - const struct secboot_ls_single_func *ls_func = - (*gsb->ls_func)[img->falcon_id]; - u8 gdesc[ls_func->bl_desc_size]; - - ls_func->generate_bl_desc(img, gsb->acr_wpr_addr, - &gdesc); - - nvkm_gpuobj_memcpy_to(wpr_blob, - img->lsb_header.bl_data_off, - &gdesc, ls_func->bl_desc_size); - } - - /* Copy ucode */ - nvkm_gpuobj_memcpy_to(wpr_blob, img->lsb_header.ucode_off, - img->ucode_data, img->ucode_size); - - pos += sizeof(img->wpr_header); - } - - nvkm_wo32(wpr_blob, pos, NVKM_SECBOOT_FALCON_INVALID); - - nvkm_done(wpr_blob); - - return 0; -} - -/* Both size and address of WPR need to be 128K-aligned */ -#define WPR_ALIGNMENT 0x20000 -/** - * gm200_secboot_prepare_ls_blob() - prepare the LS blob - * - * For each securely managed falcon, load the FW, signatures and bootloaders and - * prepare a ucode blob. Then, compute the offsets in the WPR region for each - * blob, and finally write the headers and ucode blobs into a GPU object that - * will be copied into the WPR region by the HS firmware. - */ -static int -gm200_secboot_prepare_ls_blob(struct gm200_secboot *gsb) -{ - struct nvkm_secboot *sb = &gsb->base; - struct nvkm_device *device = sb->subdev.device; - struct ls_ucode_mgr mgr; - int falcon_id; - int ret; - - ls_ucode_mgr_init(&mgr); - - /* Load all LS blobs */ - for_each_set_bit(falcon_id, &sb->func->managed_falcons, - NVKM_SECBOOT_FALCON_END) { - struct ls_ucode_img *img; - - img = ls_ucode_img_load(&sb->subdev, - (*gsb->ls_func)[falcon_id]->load); - - if (IS_ERR(img)) { - ret = PTR_ERR(img); - goto cleanup; - } - ls_ucode_mgr_add_img(&mgr, img); - } - - /* - * Fill the WPR and LSF headers with the right offsets and compute - * required WPR size - */ - ls_ucode_mgr_fill_headers(gsb, &mgr); - mgr.wpr_size = ALIGN(mgr.wpr_size, WPR_ALIGNMENT); - - /* Allocate GPU object that will contain the WPR region */ - ret = nvkm_gpuobj_new(device, mgr.wpr_size, WPR_ALIGNMENT, false, NULL, - &gsb->ls_blob); - if (ret) - goto cleanup; - - nvkm_debug(&sb->subdev, "%d managed LS falcons, WPR size is %d bytes\n", - mgr.count, mgr.wpr_size); - - /* If WPR address and size are not fixed, set them to fit the LS blob */ - if (!gsb->wpr_size) { - gsb->acr_wpr_addr = gsb->ls_blob->addr; - gsb->acr_wpr_size = gsb->ls_blob->size; - } else { - gsb->acr_wpr_addr = gsb->wpr_addr; - gsb->acr_wpr_size = gsb->wpr_size; - } - - /* Write LS blob */ - ret = ls_ucode_mgr_write_wpr(gsb, &mgr, gsb->ls_blob); - if (ret) - nvkm_gpuobj_del(&gsb->ls_blob); - -cleanup: - ls_ucode_mgr_cleanup(&mgr); - - return ret; -} - -static const secboot_ls_func -gm200_ls_func = { - [NVKM_SECBOOT_FALCON_FECS] = &(struct secboot_ls_single_func) { - .load = gm200_ls_load_fecs, - .generate_bl_desc = gm200_secboot_ls_bl_desc, - .bl_desc_size = sizeof(struct gm200_flcn_bl_desc), - }, - [NVKM_SECBOOT_FALCON_GPCCS] = &(struct secboot_ls_single_func) { - .load = gm200_ls_load_gpccs, - .generate_bl_desc = gm200_secboot_ls_bl_desc, - .bl_desc_size = sizeof(struct gm200_flcn_bl_desc), - }, -}; - -/* - * High-secure blob creation - */ - -/** - * gm200_secboot_hsf_patch_signature() - patch HS blob with correct signature - */ -static void -gm200_secboot_hsf_patch_signature(struct gm200_secboot *gsb, void *acr_image) -{ - struct nvkm_secboot *sb = &gsb->base; - struct fw_bin_header *hsbin_hdr = acr_image; - struct hsf_fw_header *fw_hdr = acr_image + hsbin_hdr->header_offset; - void *hs_data = acr_image + hsbin_hdr->data_offset; - void *sig; - u32 sig_size; - - /* Falcon in debug or production mode? */ - if (sb->boot_falcon->debug) { - sig = acr_image + fw_hdr->sig_dbg_offset; - sig_size = fw_hdr->sig_dbg_size; - } else { - sig = acr_image + fw_hdr->sig_prod_offset; - sig_size = fw_hdr->sig_prod_size; - } - - /* Patch signature */ - memcpy(hs_data + fw_hdr->patch_loc, sig + fw_hdr->patch_sig, sig_size); -} - -/** - * struct hsflcn_acr_desc - data section of the HS firmware - * - * This header is to be copied at the beginning of DMEM by the HS bootloader. - * - * @signature: signature of ACR ucode - * @wpr_region_id: region ID holding the WPR header and its details - * @wpr_offset: offset from the WPR region holding the wpr header - * @regions: region descriptors - * @nonwpr_ucode_blob_size: size of LS blob - * @nonwpr_ucode_blob_start: FB location of LS blob is - */ -struct hsflcn_acr_desc { - union { - u8 reserved_dmem[0x200]; - u32 signatures[4]; - } ucode_reserved_space; - u32 wpr_region_id; - u32 wpr_offset; - u32 mmu_mem_range; -#define FLCN_ACR_MAX_REGIONS 2 - struct { - u32 no_regions; - struct { - u32 start_addr; - u32 end_addr; - u32 region_id; - u32 read_mask; - u32 write_mask; - u32 client_mask; - } region_props[FLCN_ACR_MAX_REGIONS]; - } regions; - u32 ucode_blob_size; - u64 ucode_blob_base __aligned(8); - struct { - u32 vpr_enabled; - u32 vpr_start; - u32 vpr_end; - u32 hdcp_policies; - } vpr_desc; -}; - -static void -gm200_secboot_fixup_hs_desc(struct gm200_secboot *gsb, - struct hsflcn_acr_desc *desc) -{ - desc->ucode_blob_base = gsb->ls_blob->addr; - desc->ucode_blob_size = gsb->ls_blob->size; - - desc->wpr_offset = 0; - - /* WPR region information if WPR is not fixed */ - if (gsb->wpr_size == 0) { - desc->wpr_region_id = 1; - desc->regions.no_regions = 1; - desc->regions.region_props[0].region_id = 1; - desc->regions.region_props[0].start_addr = - gsb->acr_wpr_addr >> 8; - desc->regions.region_props[0].end_addr = - (gsb->acr_wpr_addr + gsb->acr_wpr_size) >> 8; - } -} - -/** - * gm200_secboot_prepare_hs_blob - load and prepare a HS blob and BL descriptor - * - * @gsb secure boot instance to prepare for - * @fw name of the HS firmware to load - * @blob pointer to gpuobj that will be allocated to receive the HS FW payload - * @bl_desc pointer to the BL descriptor to write for this firmware - * @patch whether we should patch the HS descriptor (only for HS loaders) - */ -static int -gm200_secboot_prepare_hs_blob(struct gm200_secboot *gsb, const char *fw, - struct nvkm_gpuobj **blob, - struct hsf_load_header *load_header, bool patch) -{ - struct nvkm_subdev *subdev = &gsb->base.subdev; - void *acr_image; - struct fw_bin_header *hsbin_hdr; - struct hsf_fw_header *fw_hdr; - struct hsf_load_header *load_hdr; - void *acr_data; - int ret; - - acr_image = gm200_secboot_load_firmware(subdev, fw, 0); - if (IS_ERR(acr_image)) - return PTR_ERR(acr_image); - - hsbin_hdr = acr_image; - fw_hdr = acr_image + hsbin_hdr->header_offset; - load_hdr = acr_image + fw_hdr->hdr_offset; - acr_data = acr_image + hsbin_hdr->data_offset; - - /* Patch signature */ - gm200_secboot_hsf_patch_signature(gsb, acr_image); - - /* Patch descriptor with WPR information? */ - if (patch) { - struct hsflcn_acr_desc *desc; - - desc = acr_data + load_hdr->data_dma_base; - gm200_secboot_fixup_hs_desc(gsb, desc); - } - - if (load_hdr->num_apps > GM200_ACR_MAX_APPS) { - nvkm_error(subdev, "more apps (%d) than supported (%d)!", - load_hdr->num_apps, GM200_ACR_MAX_APPS); - ret = -EINVAL; - goto cleanup; - } - memcpy(load_header, load_hdr, sizeof(*load_header) + - (sizeof(load_hdr->app[0]) * load_hdr->num_apps)); - - /* Create ACR blob and copy HS data to it */ - ret = nvkm_gpuobj_new(subdev->device, ALIGN(hsbin_hdr->data_size, 256), - 0x1000, false, NULL, blob); - if (ret) - goto cleanup; - - nvkm_kmap(*blob); - nvkm_gpuobj_memcpy_to(*blob, 0, acr_data, hsbin_hdr->data_size); - nvkm_done(*blob); - -cleanup: - kfree(acr_image); - - return ret; -} - -/* - * High-secure bootloader blob creation - */ - -static int -gm200_secboot_prepare_hsbl_blob(struct gm200_secboot *gsb) -{ - struct nvkm_subdev *subdev = &gsb->base.subdev; - - gsb->hsbl_blob = gm200_secboot_load_firmware(subdev, "acr/bl", 0); - if (IS_ERR(gsb->hsbl_blob)) { - int ret = PTR_ERR(gsb->hsbl_blob); - - gsb->hsbl_blob = NULL; - return ret; - } - - return 0; -} - -/** - * gm20x_secboot_prepare_blobs - load blobs common to all GM20X GPUs. + * gm200_secboot_run_blob() - run the given high-secure blob * - * This includes the LS blob, HS ucode loading blob, and HS bootloader. - * - * The HS ucode unload blob is only used on dGPU. */ int -gm20x_secboot_prepare_blobs(struct gm200_secboot *gsb) -{ - int ret; - - /* Load and prepare the managed falcon's firmwares */ - if (!gsb->ls_blob) { - ret = gm200_secboot_prepare_ls_blob(gsb); - if (ret) - return ret; - } - - /* Load the HS firmware that will load the LS firmwares */ - if (!gsb->acr_load_blob) { - ret = gm200_secboot_prepare_hs_blob(gsb, "acr/ucode_load", - &gsb->acr_load_blob, - &gsb->load_bl_header, true); - if (ret) - return ret; - } - - /* Load the HS firmware bootloader */ - if (!gsb->hsbl_blob) { - ret = gm200_secboot_prepare_hsbl_blob(gsb); - if (ret) - return ret; - } - - return 0; -} - -static int -gm200_secboot_prepare_blobs(struct gm200_secboot *gsb) -{ - int ret; - - ret = gm20x_secboot_prepare_blobs(gsb); - if (ret) - return ret; - - /* dGPU only: load the HS firmware that unprotects the WPR region */ - if (!gsb->acr_unload_blob) { - ret = gm200_secboot_prepare_hs_blob(gsb, "acr/ucode_unload", - &gsb->acr_unload_blob, - &gsb->unload_bl_header, false); - if (ret) - return ret; - } - - return 0; -} - -static int -gm200_secboot_blobs_ready(struct gm200_secboot *gsb) -{ - struct nvkm_subdev *subdev = &gsb->base.subdev; - int ret; - - /* firmware already loaded, nothing to do... */ - if (gsb->firmware_ok) - return 0; - - ret = gsb->func->prepare_blobs(gsb); - if (ret) { - nvkm_error(subdev, "failed to load secure firmware\n"); - return ret; - } - - gsb->firmware_ok = true; - - return 0; -} - - -/* - * Secure Boot Execution - */ - -/** - * gm200_secboot_load_hs_bl() - load HS bootloader into DMEM and IMEM - */ -static void -gm200_secboot_load_hs_bl(struct gm200_secboot *gsb, struct nvkm_falcon *falcon, - void *data, u32 data_size) -{ - struct fw_bin_header *hdr = gsb->hsbl_blob; - struct fw_bl_desc *hsbl_desc = gsb->hsbl_blob + hdr->header_offset; - void *blob_data = gsb->hsbl_blob + hdr->data_offset; - void *hsbl_code = blob_data + hsbl_desc->code_off; - void *hsbl_data = blob_data + hsbl_desc->data_off; - u32 code_size = ALIGN(hsbl_desc->code_size, 256); - u32 tag; - - /* - * Copy HS bootloader data - */ - nvkm_falcon_load_dmem(falcon, hsbl_data, 0x0, hsbl_desc->data_size, 0); - - /* - * Copy HS bootloader interface structure where the HS descriptor - * expects it to be - */ - nvkm_falcon_load_dmem(falcon, data, hsbl_desc->dmem_load_off, data_size, - 0); - - /* Copy HS bootloader code to end of IMEM */ - tag = hsbl_desc->start_tag; - nvkm_falcon_load_imem(falcon, hsbl_code, falcon->code.limit - code_size, - code_size, tag, 0, false); -} - -/** - * gm200_secboot_run_hs_blob() - run the given high-secure blob - */ -static int -gm200_secboot_run_hs_blob(struct gm200_secboot *gsb, struct nvkm_gpuobj *blob) +gm200_secboot_run_blob(struct nvkm_secboot *sb, struct nvkm_gpuobj *blob) { + struct gm200_secboot *gsb = gm200_secboot(sb); struct nvkm_subdev *subdev = &gsb->base.subdev; - struct fw_bin_header *hdr = gsb->hsbl_blob; - struct fw_bl_desc *hsbl_desc = gsb->hsbl_blob + hdr->header_offset; struct nvkm_falcon *falcon = gsb->base.boot_falcon; - const u32 virt_addr = hsbl_desc->start_tag << 8; - const u32 bl_desc_size = gsb->func->bl_desc_size; - const struct hsf_load_header *load_hdr; - u8 bl_desc[bl_desc_size]; struct nvkm_vma vma; int ret; - /* Find the bootloader descriptor for our blob and copy it */ - if (blob == gsb->acr_load_blob) { - load_hdr = &gsb->load_bl_header; - - } else if (blob == gsb->acr_unload_blob) { - load_hdr = &gsb->unload_bl_header; - } else { - nvkm_error(&gsb->base.subdev, "invalid secure boot blob!\n"); - return -EINVAL; - } - ret = nvkm_falcon_get(falcon, subdev); if (ret) return ret; @@ -1070,9 +52,6 @@ gm200_secboot_run_hs_blob(struct gm200_secboot *gsb, struct nvkm_gpuobj *blob) return ret; } - /* Generate the BL header */ - gsb->func->generate_bl_desc(load_hdr, bl_desc, vma.offset); - /* Reset and set the falcon up */ ret = nvkm_falcon_reset(falcon); if (ret) @@ -1080,10 +59,12 @@ gm200_secboot_run_hs_blob(struct gm200_secboot *gsb, struct nvkm_gpuobj *blob) nvkm_falcon_bind_context(falcon, gsb->inst); /* Load the HS bootloader into the falcon's IMEM/DMEM */ - gm200_secboot_load_hs_bl(gsb, falcon, &bl_desc, bl_desc_size); + ret = sb->acr->func->load(sb->acr, &gsb->base, blob, vma.offset); + if (ret) + goto end; /* Start the HS bootloader */ - nvkm_falcon_set_start_addr(falcon, virt_addr); + nvkm_falcon_set_start_addr(falcon, sb->acr->start_address); nvkm_falcon_start(falcon); ret = nvkm_falcon_wait_for_halt(falcon, 100); if (ret) @@ -1105,53 +86,6 @@ end: return ret; } -/* - * gm200_secboot_reset() - execute secure boot from the prepared state - * - * Load the HS bootloader and ask the falcon to run it. This will in turn - * load the HS firmware and run it, so once the falcon stops all the managed - * falcons should have their LS firmware loaded and be ready to run. - */ -int -gm200_secboot_reset(struct nvkm_secboot *sb, enum nvkm_secboot_falcon falcon) -{ - struct gm200_secboot *gsb = gm200_secboot(sb); - int ret; - - /* Make sure all blobs are ready */ - ret = gm200_secboot_blobs_ready(gsb); - if (ret) - return ret; - - /* - * Dummy GM200 implementation: perform secure boot each time we are - * called on FECS. Since only FECS and GPCCS are managed and started - * together, this ought to be safe. - * - * Once we have proper PMU firmware and support, this will be changed - * to a proper call to the PMU method. - */ - if (falcon != NVKM_SECBOOT_FALCON_FECS) - goto end; - - /* If WPR is set and we have an unload blob, run it to unlock WPR */ - if (gsb->acr_unload_blob && - gsb->falcon_state[NVKM_SECBOOT_FALCON_FECS] != NON_SECURE) { - ret = gm200_secboot_run_hs_blob(gsb, gsb->acr_unload_blob); - if (ret) - return ret; - } - - /* Reload all managed falcons */ - ret = gm200_secboot_run_hs_blob(gsb, gsb->acr_load_blob); - if (ret) - return ret; - -end: - gsb->falcon_state[falcon] = RESET; - return 0; -} - int gm200_secboot_oneinit(struct nvkm_secboot *sb) { @@ -1188,23 +122,22 @@ gm200_secboot_oneinit(struct nvkm_secboot *sb) nvkm_wo32(gsb->inst, 0x20c, upper_32_bits(vm_area_len - 1)); nvkm_done(gsb->inst); + if (sb->acr->func->oneinit) { + ret = sb->acr->func->oneinit(sb->acr, sb); + if (ret) + return ret; + } + return 0; } -static int +int gm200_secboot_fini(struct nvkm_secboot *sb, bool suspend) { - struct gm200_secboot *gsb = gm200_secboot(sb); int ret = 0; - int i; - - /* Run the unload blob to unprotect the WPR region */ - if (gsb->acr_unload_blob && - gsb->falcon_state[NVKM_SECBOOT_FALCON_FECS] != NON_SECURE) - ret = gm200_secboot_run_hs_blob(gsb, gsb->acr_unload_blob); - for (i = 0; i < NVKM_SECBOOT_FALCON_END; i++) - gsb->falcon_state[i] = NON_SECURE; + if (sb->acr->func->fini) + ret = sb->acr->func->fini(sb->acr, sb, suspend); return ret; } @@ -1214,11 +147,7 @@ gm200_secboot_dtor(struct nvkm_secboot *sb) { struct gm200_secboot *gsb = gm200_secboot(sb); - nvkm_gpuobj_del(&gsb->acr_unload_blob); - - kfree(gsb->hsbl_blob); - nvkm_gpuobj_del(&gsb->acr_load_blob); - nvkm_gpuobj_del(&gsb->ls_blob); + sb->acr->func->dtor(sb->acr); nvkm_vm_ref(NULL, &gsb->vm, gsb->pgd); nvkm_gpuobj_del(&gsb->pgd); @@ -1233,36 +162,7 @@ gm200_secboot = { .dtor = gm200_secboot_dtor, .oneinit = gm200_secboot_oneinit, .fini = gm200_secboot_fini, - .reset = gm200_secboot_reset, - .managed_falcons = BIT(NVKM_SECBOOT_FALCON_FECS) | - BIT(NVKM_SECBOOT_FALCON_GPCCS), - .boot_falcon = NVKM_SECBOOT_FALCON_PMU, -}; - -static void -gm200_secboot_generate_bl_desc(const struct hsf_load_header *hdr, - void *_bl_desc, u64 offset) -{ - struct gm200_flcn_bl_desc *bl_desc = _bl_desc; - - memset(bl_desc, 0, sizeof(*bl_desc)); - bl_desc->ctx_dma = FALCON_DMAIDX_VIRT; - bl_desc->non_sec_code_off = hdr->non_sec_code_off; - bl_desc->non_sec_code_size = hdr->non_sec_code_size; - bl_desc->sec_code_off = hdr->app[0].sec_code_off; - bl_desc->sec_code_size = hdr->app[0].sec_code_size; - bl_desc->code_entry_point = 0; - - bl_desc->code_dma_base = u64_to_flcn64(offset); - bl_desc->data_dma_base = u64_to_flcn64(offset + hdr->data_dma_base); - bl_desc->data_size = hdr->data_size; -} - -static const struct gm200_secboot_func -gm200_secboot_func = { - .bl_desc_size = sizeof(struct gm200_flcn_bl_desc), - .generate_bl_desc = gm200_secboot_generate_bl_desc, - .prepare_blobs = gm200_secboot_prepare_blobs, + .run_blob = gm200_secboot_run_blob, }; int @@ -1271,6 +171,12 @@ gm200_secboot_new(struct nvkm_device *device, int index, { int ret; struct gm200_secboot *gsb; + struct nvkm_acr *acr; + + acr = acr_r361_new(BIT(NVKM_SECBOOT_FALCON_FECS) | + BIT(NVKM_SECBOOT_FALCON_GPCCS)); + if (IS_ERR(acr)) + return PTR_ERR(acr); gsb = kzalloc(sizeof(*gsb), GFP_KERNEL); if (!gsb) { @@ -1279,16 +185,14 @@ gm200_secboot_new(struct nvkm_device *device, int index, } *psb = &gsb->base; - ret = nvkm_secboot_ctor(&gm200_secboot, device, index, &gsb->base); + ret = nvkm_secboot_ctor(&gm200_secboot, acr, device, index, &gsb->base); if (ret) return ret; - gsb->func = &gm200_secboot_func; - gsb->ls_func = &gm200_ls_func; - return 0; } + MODULE_FIRMWARE("nvidia/gm200/acr/bl.bin"); MODULE_FIRMWARE("nvidia/gm200/acr/ucode_load.bin"); MODULE_FIRMWARE("nvidia/gm200/acr/ucode_unload.bin"); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.h b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.h new file mode 100644 index 0000000..45adf1a --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NVKM_SECBOOT_GM200_H__ +#define __NVKM_SECBOOT_GM200_H__ + +#include "priv.h" + +struct gm200_secboot { + struct nvkm_secboot base; + + /* Instance block & address space used for HS FW execution */ + struct nvkm_gpuobj *inst; + struct nvkm_gpuobj *pgd; + struct nvkm_vm *vm; +}; +#define gm200_secboot(sb) container_of(sb, struct gm200_secboot, base) + +int gm200_secboot_oneinit(struct nvkm_secboot *); +int gm200_secboot_fini(struct nvkm_secboot *, bool); +void *gm200_secboot_dtor(struct nvkm_secboot *); +int gm200_secboot_run_blob(struct nvkm_secboot *, struct nvkm_gpuobj *); + +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c index 94d6c44..6707b8e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c @@ -20,99 +20,8 @@ * DEALINGS IN THE SOFTWARE. */ -#include "priv.h" - -#include -#include - -/* - * The BL header format used by GM20B's firmware is slightly different - * from the one of GM200. Fix the differences here. - */ -struct gm20b_flcn_bl_desc { - u32 reserved[4]; - u32 signature[4]; - u32 ctx_dma; - u32 code_dma_base; - u32 non_sec_code_off; - u32 non_sec_code_size; - u32 sec_code_off; - u32 sec_code_size; - u32 code_entry_point; - u32 data_dma_base; - u32 data_size; -}; - -static void -gm20b_secboot_ls_bl_desc(const struct ls_ucode_img *img, u64 wpr_addr, - void *_desc) -{ - struct gm20b_flcn_bl_desc *desc = _desc; - const struct ls_ucode_img_desc *pdesc = &img->ucode_desc; - u64 base; - - base = wpr_addr + img->lsb_header.ucode_off + pdesc->app_start_offset; - - memset(desc, 0, sizeof(*desc)); - desc->ctx_dma = FALCON_DMAIDX_UCODE; - desc->code_dma_base = (base + pdesc->app_resident_code_offset) >> 8; - desc->non_sec_code_size = pdesc->app_resident_code_size; - desc->data_dma_base = (base + pdesc->app_resident_data_offset) >> 8; - desc->data_size = pdesc->app_resident_data_size; - desc->code_entry_point = pdesc->app_imem_entry; -} - -static int -gm20b_secboot_prepare_blobs(struct gm200_secboot *gsb) -{ - struct nvkm_subdev *subdev = &gsb->base.subdev; - int acr_size; - int ret; - - ret = gm20x_secboot_prepare_blobs(gsb); - if (ret) - return ret; - - acr_size = gsb->acr_load_blob->size; - /* - * On Tegra the WPR region is set by the bootloader. It is illegal for - * the HS blob to be larger than this region. - */ - if (acr_size > gsb->wpr_size) { - nvkm_error(subdev, "WPR region too small for FW blob!\n"); - nvkm_error(subdev, "required: %dB\n", acr_size); - nvkm_error(subdev, "WPR size: %dB\n", gsb->wpr_size); - return -ENOSPC; - } - - return 0; -} - -static void -gm20b_secboot_generate_bl_desc(const struct hsf_load_header *load_hdr, - void *_bl_desc, u64 offset) -{ - struct gm20b_flcn_bl_desc *bl_desc = _bl_desc; - - memset(bl_desc, 0, sizeof(*bl_desc)); - bl_desc->ctx_dma = FALCON_DMAIDX_VIRT; - bl_desc->non_sec_code_off = load_hdr->non_sec_code_off; - bl_desc->non_sec_code_size = load_hdr->non_sec_code_size; - bl_desc->sec_code_off = load_hdr->app[0].sec_code_off; - bl_desc->sec_code_size = load_hdr->app[0].sec_code_size; - bl_desc->code_entry_point = 0; - bl_desc->code_dma_base = offset >> 8; - bl_desc->data_dma_base = (offset + load_hdr->data_dma_base) >> 8; - bl_desc->data_size = load_hdr->data_size; -} - -static const struct gm200_secboot_func -gm20b_secboot_func = { - .bl_desc_size = sizeof(struct gm20b_flcn_bl_desc), - .generate_bl_desc = gm20b_secboot_generate_bl_desc, - .prepare_blobs = gm20b_secboot_prepare_blobs, -}; - +#include "acr.h" +#include "gm200.h" #ifdef CONFIG_ARCH_TEGRA #define TEGRA_MC_BASE 0x70019000 @@ -140,15 +49,15 @@ gm20b_tegra_read_wpr(struct gm200_secboot *gsb) nvkm_error(&sb->subdev, "Cannot map Tegra MC registers\n"); return PTR_ERR(mc); } - gsb->wpr_addr = ioread32_native(mc + MC_SECURITY_CARVEOUT2_BOM_0) | + sb->wpr_addr = ioread32_native(mc + MC_SECURITY_CARVEOUT2_BOM_0) | ((u64)ioread32_native(mc + MC_SECURITY_CARVEOUT2_BOM_HI_0) << 32); - gsb->wpr_size = ioread32_native(mc + MC_SECURITY_CARVEOUT2_SIZE_128K) + sb->wpr_size = ioread32_native(mc + MC_SECURITY_CARVEOUT2_SIZE_128K) << 17; cfg = ioread32_native(mc + MC_SECURITY_CARVEOUT2_CFG0); iounmap(mc); /* Check that WPR settings are valid */ - if (gsb->wpr_size == 0) { + if (sb->wpr_size == 0) { nvkm_error(&sb->subdev, "WPR region is empty\n"); return -EINVAL; } @@ -186,18 +95,8 @@ static const struct nvkm_secboot_func gm20b_secboot = { .dtor = gm200_secboot_dtor, .oneinit = gm20b_secboot_oneinit, - .reset = gm200_secboot_reset, - .managed_falcons = BIT(NVKM_SECBOOT_FALCON_FECS), - .boot_falcon = NVKM_SECBOOT_FALCON_PMU, -}; - -static const secboot_ls_func -gm20b_ls_func = { - [NVKM_SECBOOT_FALCON_FECS] = &(struct secboot_ls_single_func) { - .load = gm200_ls_load_fecs, - .generate_bl_desc = gm20b_secboot_ls_bl_desc, - .bl_desc_size = sizeof(struct gm20b_flcn_bl_desc), - }, + .fini = gm200_secboot_fini, + .run_blob = gm200_secboot_run_blob, }; int @@ -206,6 +105,11 @@ gm20b_secboot_new(struct nvkm_device *device, int index, { int ret; struct gm200_secboot *gsb; + struct nvkm_acr *acr; + + acr = acr_r352_new(BIT(NVKM_SECBOOT_FALCON_FECS)); + if (IS_ERR(acr)) + return PTR_ERR(acr); gsb = kzalloc(sizeof(*gsb), GFP_KERNEL); if (!gsb) { @@ -214,13 +118,10 @@ gm20b_secboot_new(struct nvkm_device *device, int index, } *psb = &gsb->base; - ret = nvkm_secboot_ctor(&gm20b_secboot, device, index, &gsb->base); + ret = nvkm_secboot_ctor(&gm20b_secboot, acr, device, index, &gsb->base); if (ret) return ret; - gsb->func = &gm20b_secboot_func; - gsb->ls_func = &gm20b_ls_func; - return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode.h b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode.h new file mode 100644 index 0000000..3598ed5 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode.h @@ -0,0 +1,245 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NVKM_SECBOOT_LS_UCODE_H__ +#define __NVKM_SECBOOT_LS_UCODE_H__ + +#include +#include +#include + +/* + * + * LS blob structures + * + */ + +/** + * struct lsf_ucode_desc - LS falcon signatures + * @prd_keys: signature to use when the GPU is in production mode + * @dgb_keys: signature to use when the GPU is in debug mode + * @b_prd_present: whether the production key is present + * @b_dgb_present: whether the debug key is present + * @falcon_id: ID of the falcon the ucode applies to + * + * Directly loaded from a signature file. + */ +struct lsf_ucode_desc { + u8 prd_keys[2][16]; + u8 dbg_keys[2][16]; + u32 b_prd_present; + u32 b_dbg_present; + u32 falcon_id; +}; + +/** + * struct lsf_lsb_header - LS firmware header + * @signature: signature to verify the firmware against + * @ucode_off: offset of the ucode blob in the WPR region. The ucode + * blob contains the bootloader, code and data of the + * LS falcon + * @ucode_size: size of the ucode blob, including bootloader + * @data_size: size of the ucode blob data + * @bl_code_size: size of the bootloader code + * @bl_imem_off: offset in imem of the bootloader + * @bl_data_off: offset of the bootloader data in WPR region + * @bl_data_size: size of the bootloader data + * @app_code_off: offset of the app code relative to ucode_off + * @app_code_size: size of the app code + * @app_data_off: offset of the app data relative to ucode_off + * @app_data_size: size of the app data + * @flags: flags for the secure bootloader + * + * This structure is written into the WPR region for each managed falcon. Each + * instance is referenced by the lsb_offset member of the corresponding + * lsf_wpr_header. + */ +struct lsf_lsb_header { + struct lsf_ucode_desc signature; + u32 ucode_off; + u32 ucode_size; + u32 data_size; + u32 bl_code_size; + u32 bl_imem_off; + u32 bl_data_off; + u32 bl_data_size; + u32 app_code_off; + u32 app_code_size; + u32 app_data_off; + u32 app_data_size; + u32 flags; +#define LSF_FLAG_LOAD_CODE_AT_0 1 +#define LSF_FLAG_DMACTL_REQ_CTX 4 +#define LSF_FLAG_FORCE_PRIV_LOAD 8 +}; + +/** + * struct lsf_wpr_header - LS blob WPR Header + * @falcon_id: LS falcon ID + * @lsb_offset: offset of the lsb_lsf_header in the WPR region + * @bootstrap_owner: secure falcon reponsible for bootstrapping the LS falcon + * @lazy_bootstrap: skip bootstrapping by ACR + * @status: bootstrapping status + * + * An array of these is written at the beginning of the WPR region, one for + * each managed falcon. The array is terminated by an instance which falcon_id + * is LSF_FALCON_ID_INVALID. + */ +struct lsf_wpr_header { + u32 falcon_id; + u32 lsb_offset; + u32 bootstrap_owner; + u32 lazy_bootstrap; + u32 status; +#define LSF_IMAGE_STATUS_NONE 0 +#define LSF_IMAGE_STATUS_COPY 1 +#define LSF_IMAGE_STATUS_VALIDATION_CODE_FAILED 2 +#define LSF_IMAGE_STATUS_VALIDATION_DATA_FAILED 3 +#define LSF_IMAGE_STATUS_VALIDATION_DONE 4 +#define LSF_IMAGE_STATUS_VALIDATION_SKIPPED 5 +#define LSF_IMAGE_STATUS_BOOTSTRAP_READY 6 +}; + + +/** + * struct ls_ucode_img_desc - descriptor of firmware image + * @descriptor_size: size of this descriptor + * @image_size: size of the whole image + * @bootloader_start_offset: start offset of the bootloader in ucode image + * @bootloader_size: size of the bootloader + * @bootloader_imem_offset: start off set of the bootloader in IMEM + * @bootloader_entry_point: entry point of the bootloader in IMEM + * @app_start_offset: start offset of the LS firmware + * @app_size: size of the LS firmware's code and data + * @app_imem_offset: offset of the app in IMEM + * @app_imem_entry: entry point of the app in IMEM + * @app_dmem_offset: offset of the data in DMEM + * @app_resident_code_offset: offset of app code from app_start_offset + * @app_resident_code_size: size of the code + * @app_resident_data_offset: offset of data from app_start_offset + * @app_resident_data_size: size of data + * + * A firmware image contains the code, data, and bootloader of a given LS + * falcon in a single blob. This structure describes where everything is. + * + * This can be generated from a (bootloader, code, data) set if they have + * been loaded separately, or come directly from a file. + */ +struct ls_ucode_img_desc { + u32 descriptor_size; + u32 image_size; + u32 tools_version; + u32 app_version; + char date[64]; + u32 bootloader_start_offset; + u32 bootloader_size; + u32 bootloader_imem_offset; + u32 bootloader_entry_point; + u32 app_start_offset; + u32 app_size; + u32 app_imem_offset; + u32 app_imem_entry; + u32 app_dmem_offset; + u32 app_resident_code_offset; + u32 app_resident_code_size; + u32 app_resident_data_offset; + u32 app_resident_data_size; + u32 nb_overlays; + struct {u32 start; u32 size; } load_ovl[64]; + u32 compressed; +}; + +/** + * struct ls_ucode_img - temporary storage for loaded LS firmwares + * @node: to link within lsf_ucode_mgr + * @falcon_id: ID of the falcon this LS firmware is for + * @ucode_desc: loaded or generated map of ucode_data + * @ucode_header: header of the firmware + * @ucode_data: firmware payload (code and data) + * @ucode_size: size in bytes of data in ucode_data + * @wpr_header: WPR header to be written to the LS blob + * @lsb_header: LSB header to be written to the LS blob + * + * Preparing the WPR LS blob requires information about all the LS firmwares + * (size, etc) to be known. This structure contains all the data of one LS + * firmware. + */ +struct ls_ucode_img { + struct list_head node; + enum nvkm_secboot_falcon falcon_id; + + struct ls_ucode_img_desc ucode_desc; + u32 *ucode_header; + u8 *ucode_data; + u32 ucode_size; + + struct lsf_wpr_header wpr_header; + struct lsf_lsb_header lsb_header; +}; + +/** + * struct fw_bin_header - header of firmware files + * @bin_magic: always 0x3b1d14f0 + * @bin_ver: version of the bin format + * @bin_size: entire image size including this header + * @header_offset: offset of the firmware/bootloader header in the file + * @data_offset: offset of the firmware/bootloader payload in the file + * @data_size: size of the payload + * + * This header is located at the beginning of the HS firmware and HS bootloader + * files, to describe where the headers and data can be found. + */ +struct fw_bin_header { + u32 bin_magic; + u32 bin_ver; + u32 bin_size; + u32 header_offset; + u32 data_offset; + u32 data_size; +}; + +/** + * struct fw_bl_desc - firmware bootloader descriptor + * @start_tag: starting tag of bootloader + * @desc_dmem_load_off: DMEM offset of flcn_bl_dmem_desc + * @code_off: offset of code section + * @code_size: size of code section + * @data_off: offset of data section + * @data_size: size of data section + * + * This structure is embedded in bootloader firmware files at to describe the + * IMEM and DMEM layout expected by the bootloader. + */ +struct fw_bl_desc { + u32 start_tag; + u32 dmem_load_off; + u32 code_off; + u32 code_size; + u32 data_off; + u32 data_size; +}; + +int acr_ls_ucode_load_fecs(const struct nvkm_subdev *, struct ls_ucode_img *); +int acr_ls_ucode_load_gpccs(const struct nvkm_subdev *, struct ls_ucode_img *); + + +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_gr.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_gr.c new file mode 100644 index 0000000..f9c0c64 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_gr.c @@ -0,0 +1,167 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#include "ls_ucode.h" +#include "acr.h" + +#include + +#define BL_DESC_BLK_SIZE 256 +/** + * Build a ucode image and descriptor from provided bootloader, code and data. + * + * @bl: bootloader image, including 16-bytes descriptor + * @code: LS firmware code segment + * @data: LS firmware data segment + * @desc: ucode descriptor to be written + * + * Return: allocated ucode image with corresponding descriptor information. desc + * is also updated to contain the right offsets within returned image. + */ +static void * +ls_ucode_img_build(const struct firmware *bl, const struct firmware *code, + const struct firmware *data, struct ls_ucode_img_desc *desc) +{ + struct fw_bin_header *bin_hdr = (void *)bl->data; + struct fw_bl_desc *bl_desc = (void *)bl->data + bin_hdr->header_offset; + void *bl_data = (void *)bl->data + bin_hdr->data_offset; + u32 pos = 0; + void *image; + + desc->bootloader_start_offset = pos; + desc->bootloader_size = ALIGN(bl_desc->code_size, sizeof(u32)); + desc->bootloader_imem_offset = bl_desc->start_tag * 256; + desc->bootloader_entry_point = bl_desc->start_tag * 256; + + pos = ALIGN(pos + desc->bootloader_size, BL_DESC_BLK_SIZE); + desc->app_start_offset = pos; + desc->app_size = ALIGN(code->size, BL_DESC_BLK_SIZE) + + ALIGN(data->size, BL_DESC_BLK_SIZE); + desc->app_imem_offset = 0; + desc->app_imem_entry = 0; + desc->app_dmem_offset = 0; + desc->app_resident_code_offset = 0; + desc->app_resident_code_size = ALIGN(code->size, BL_DESC_BLK_SIZE); + + pos = ALIGN(pos + desc->app_resident_code_size, BL_DESC_BLK_SIZE); + desc->app_resident_data_offset = pos - desc->app_start_offset; + desc->app_resident_data_size = ALIGN(data->size, BL_DESC_BLK_SIZE); + + desc->image_size = ALIGN(bl_desc->code_size, BL_DESC_BLK_SIZE) + + desc->app_size; + + image = kzalloc(desc->image_size, GFP_KERNEL); + if (!image) + return ERR_PTR(-ENOMEM); + + memcpy(image + desc->bootloader_start_offset, bl_data, + bl_desc->code_size); + memcpy(image + desc->app_start_offset, code->data, code->size); + memcpy(image + desc->app_start_offset + desc->app_resident_data_offset, + data->data, data->size); + + return image; +} + +/** + * ls_ucode_img_load_gr() - load and prepare a LS GR ucode image + * + * Load the LS microcode, bootloader and signature and pack them into a single + * blob. Also generate the corresponding ucode descriptor. + */ +static int +ls_ucode_img_load_gr(const struct nvkm_subdev *subdev, struct ls_ucode_img *img, + const char *falcon_name, const u32 falcon_id) +{ + const struct firmware *bl, *code, *data; + struct lsf_ucode_desc *lsf_desc; + char f[64]; + int ret; + + img->ucode_header = NULL; + + snprintf(f, sizeof(f), "gr/%s_bl", falcon_name); + ret = nvkm_firmware_get(subdev->device, f, &bl); + if (ret) + goto error; + + snprintf(f, sizeof(f), "gr/%s_inst", falcon_name); + ret = nvkm_firmware_get(subdev->device, f, &code); + if (ret) + goto free_bl; + + snprintf(f, sizeof(f), "gr/%s_data", falcon_name); + ret = nvkm_firmware_get(subdev->device, f, &data); + if (ret) + goto free_inst; + + img->ucode_data = ls_ucode_img_build(bl, code, data, + &img->ucode_desc); + if (IS_ERR(img->ucode_data)) { + ret = PTR_ERR(img->ucode_data); + goto free_data; + } + img->ucode_size = img->ucode_desc.image_size; + + snprintf(f, sizeof(f), "gr/%s_sig", falcon_name); + lsf_desc = nvkm_acr_load_firmware(subdev, f, sizeof(*lsf_desc)); + if (IS_ERR(lsf_desc)) { + ret = PTR_ERR(lsf_desc); + goto free_image; + } + /* not needed? the signature should already have the right value */ + lsf_desc->falcon_id = falcon_id; + memcpy(&img->lsb_header.signature, lsf_desc, sizeof(*lsf_desc)); + img->falcon_id = lsf_desc->falcon_id; + kfree(lsf_desc); + + /* success path - only free requested firmware files */ + goto free_data; + +free_image: + kfree(img->ucode_data); +free_data: + nvkm_firmware_put(data); +free_inst: + nvkm_firmware_put(code); +free_bl: + nvkm_firmware_put(bl); +error: + return ret; +} + +int +acr_ls_ucode_load_fecs(const struct nvkm_subdev *subdev, + struct ls_ucode_img *img) +{ + return ls_ucode_img_load_gr(subdev, img, "fecs", + NVKM_SECBOOT_FALCON_FECS); +} + +int +acr_ls_ucode_load_gpccs(const struct nvkm_subdev *subdev, + struct ls_ucode_img *img) +{ + return ls_ucode_img_load_gr(subdev, img, "gpccs", + NVKM_SECBOOT_FALCON_GPCCS); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h index 3babed5..430b88e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h @@ -30,185 +30,13 @@ struct nvkm_secboot_func { int (*oneinit)(struct nvkm_secboot *); int (*fini)(struct nvkm_secboot *, bool suspend); void *(*dtor)(struct nvkm_secboot *); - int (*reset)(struct nvkm_secboot *, enum nvkm_secboot_falcon); - - /* ID of the falcon that will perform secure boot */ - enum nvkm_secboot_falcon boot_falcon; - /* Bit-mask of IDs of managed falcons */ - unsigned long managed_falcons; -}; - -int nvkm_secboot_ctor(const struct nvkm_secboot_func *, struct nvkm_device *, - int index, struct nvkm_secboot *); - -/* - * - * LS blob structures - * - */ - -/** - * struct lsf_ucode_desc - LS falcon signatures - * @prd_keys: signature to use when the GPU is in production mode - * @dgb_keys: signature to use when the GPU is in debug mode - * @b_prd_present: whether the production key is present - * @b_dgb_present: whether the debug key is present - * @falcon_id: ID of the falcon the ucode applies to - * - * Directly loaded from a signature file. - */ -struct lsf_ucode_desc { - u8 prd_keys[2][16]; - u8 dbg_keys[2][16]; - u32 b_prd_present; - u32 b_dbg_present; - u32 falcon_id; + int (*run_blob)(struct nvkm_secboot *, struct nvkm_gpuobj *); }; -/** - * struct lsf_lsb_header - LS firmware header - * @signature: signature to verify the firmware against - * @ucode_off: offset of the ucode blob in the WPR region. The ucode - * blob contains the bootloader, code and data of the - * LS falcon - * @ucode_size: size of the ucode blob, including bootloader - * @data_size: size of the ucode blob data - * @bl_code_size: size of the bootloader code - * @bl_imem_off: offset in imem of the bootloader - * @bl_data_off: offset of the bootloader data in WPR region - * @bl_data_size: size of the bootloader data - * @app_code_off: offset of the app code relative to ucode_off - * @app_code_size: size of the app code - * @app_data_off: offset of the app data relative to ucode_off - * @app_data_size: size of the app data - * @flags: flags for the secure bootloader - * - * This structure is written into the WPR region for each managed falcon. Each - * instance is referenced by the lsb_offset member of the corresponding - * lsf_wpr_header. - */ -struct lsf_lsb_header { - struct lsf_ucode_desc signature; - u32 ucode_off; - u32 ucode_size; - u32 data_size; - u32 bl_code_size; - u32 bl_imem_off; - u32 bl_data_off; - u32 bl_data_size; - u32 app_code_off; - u32 app_code_size; - u32 app_data_off; - u32 app_data_size; - u32 flags; -#define LSF_FLAG_LOAD_CODE_AT_0 1 -#define LSF_FLAG_DMACTL_REQ_CTX 4 -#define LSF_FLAG_FORCE_PRIV_LOAD 8 -}; - -/** - * struct lsf_wpr_header - LS blob WPR Header - * @falcon_id: LS falcon ID - * @lsb_offset: offset of the lsb_lsf_header in the WPR region - * @bootstrap_owner: secure falcon reponsible for bootstrapping the LS falcon - * @lazy_bootstrap: skip bootstrapping by ACR - * @status: bootstrapping status - * - * An array of these is written at the beginning of the WPR region, one for - * each managed falcon. The array is terminated by an instance which falcon_id - * is LSF_FALCON_ID_INVALID. - */ -struct lsf_wpr_header { - u32 falcon_id; - u32 lsb_offset; - u32 bootstrap_owner; - u32 lazy_bootstrap; - u32 status; -#define LSF_IMAGE_STATUS_NONE 0 -#define LSF_IMAGE_STATUS_COPY 1 -#define LSF_IMAGE_STATUS_VALIDATION_CODE_FAILED 2 -#define LSF_IMAGE_STATUS_VALIDATION_DATA_FAILED 3 -#define LSF_IMAGE_STATUS_VALIDATION_DONE 4 -#define LSF_IMAGE_STATUS_VALIDATION_SKIPPED 5 -#define LSF_IMAGE_STATUS_BOOTSTRAP_READY 6 -}; - - -/** - * struct ls_ucode_img_desc - descriptor of firmware image - * @descriptor_size: size of this descriptor - * @image_size: size of the whole image - * @bootloader_start_offset: start offset of the bootloader in ucode image - * @bootloader_size: size of the bootloader - * @bootloader_imem_offset: start off set of the bootloader in IMEM - * @bootloader_entry_point: entry point of the bootloader in IMEM - * @app_start_offset: start offset of the LS firmware - * @app_size: size of the LS firmware's code and data - * @app_imem_offset: offset of the app in IMEM - * @app_imem_entry: entry point of the app in IMEM - * @app_dmem_offset: offset of the data in DMEM - * @app_resident_code_offset: offset of app code from app_start_offset - * @app_resident_code_size: size of the code - * @app_resident_data_offset: offset of data from app_start_offset - * @app_resident_data_size: size of data - * - * A firmware image contains the code, data, and bootloader of a given LS - * falcon in a single blob. This structure describes where everything is. - * - * This can be generated from a (bootloader, code, data) set if they have - * been loaded separately, or come directly from a file. - */ -struct ls_ucode_img_desc { - u32 descriptor_size; - u32 image_size; - u32 tools_version; - u32 app_version; - char date[64]; - u32 bootloader_start_offset; - u32 bootloader_size; - u32 bootloader_imem_offset; - u32 bootloader_entry_point; - u32 app_start_offset; - u32 app_size; - u32 app_imem_offset; - u32 app_imem_entry; - u32 app_dmem_offset; - u32 app_resident_code_offset; - u32 app_resident_code_size; - u32 app_resident_data_offset; - u32 app_resident_data_size; - u32 nb_overlays; - struct {u32 start; u32 size; } load_ovl[64]; - u32 compressed; -}; - -/** - * struct ls_ucode_img - temporary storage for loaded LS firmwares - * @node: to link within lsf_ucode_mgr - * @falcon_id: ID of the falcon this LS firmware is for - * @ucode_desc: loaded or generated map of ucode_data - * @ucode_header: header of the firmware - * @ucode_data: firmware payload (code and data) - * @ucode_size: size in bytes of data in ucode_data - * @wpr_header: WPR header to be written to the LS blob - * @lsb_header: LSB header to be written to the LS blob - * - * Preparing the WPR LS blob requires information about all the LS firmwares - * (size, etc) to be known. This structure contains all the data of one LS - * firmware. - */ -struct ls_ucode_img { - struct list_head node; - enum nvkm_secboot_falcon falcon_id; - - struct ls_ucode_img_desc ucode_desc; - u32 *ucode_header; - u8 *ucode_data; - u32 ucode_size; - - struct lsf_wpr_header wpr_header; - struct lsf_lsb_header lsb_header; -}; +int nvkm_secboot_ctor(const struct nvkm_secboot_func *, struct nvkm_acr *, + struct nvkm_device *, int, struct nvkm_secboot *); +int nvkm_secboot_falcon_reset(struct nvkm_secboot *); +int nvkm_secboot_falcon_run(struct nvkm_secboot *); struct flcn_u64 { u32 lo; @@ -230,150 +58,4 @@ static inline struct flcn_u64 u64_to_flcn64(u64 u) return ret; } -#define GM200_ACR_MAX_APPS 8 - -struct hsf_load_header_app { - u32 sec_code_off; - u32 sec_code_size; -}; - -/** - * struct hsf_load_header - HS firmware load header - */ -struct hsf_load_header { - u32 non_sec_code_off; - u32 non_sec_code_size; - u32 data_dma_base; - u32 data_size; - u32 num_apps; - struct hsf_load_header_app app[0]; -}; - -/** - * struct secboot_ls_single_func - manages a single LS firmware - * - * @load: load the external firmware into a ls_ucode_img - * @generate_bl_desc: function called on a block of bl_desc_size to generate the - * proper bootloader descriptor for this LS firmware - * @bl_desc_size: size of the bootloader descriptor - */ -struct secboot_ls_single_func { - int (*load)(const struct nvkm_subdev *, struct ls_ucode_img *); - void (*generate_bl_desc)(const struct ls_ucode_img *, u64, void *); - u32 bl_desc_size; -}; - -/** - * typedef secboot_ls_func - manages all the LS firmwares for this ACR - */ -typedef const struct secboot_ls_single_func * -secboot_ls_func[NVKM_SECBOOT_FALCON_END]; - -int gm200_ls_load_fecs(const struct nvkm_subdev *, struct ls_ucode_img *); -int gm200_ls_load_gpccs(const struct nvkm_subdev *, struct ls_ucode_img *); - -/** - * Contains the whole secure boot state, allowing it to be performed as needed - * @wpr_addr: physical address of the WPR region - * @wpr_size: size in bytes of the WPR region - * @ls_blob: LS blob of all the LS firmwares, signatures, bootloaders - * @ls_blob_size: size of the LS blob - * @ls_blob_nb_regions: number of LS firmwares that will be loaded - * @acr_blob: HS blob - * @acr_blob_vma: mapping of the HS blob into the secure falcon's VM - * @acr_bl_desc: bootloader descriptor of the HS blob - * @hsbl_blob: HS blob bootloader - * @inst: instance block for HS falcon - * @pgd: page directory for the HS falcon - * @vm: address space used by the HS falcon - * @falcon_state: current state of the managed falcons - * @firmware_ok: whether the firmware blobs have been created - */ -struct gm200_secboot { - struct nvkm_secboot base; - const struct gm200_secboot_func *func; - const secboot_ls_func *ls_func; - - /* - * Address and size of the fixed WPR region, if any. On Tegra this - * region is set by the bootloader - */ - u64 wpr_addr; - u32 wpr_size; - - /* - * Address and size of the actual WPR region. - */ - u64 acr_wpr_addr; - u32 acr_wpr_size; - - /* - * HS FW - lock WPR region (dGPU only) and load LS FWs - * on Tegra the HS FW copies the LS blob into the fixed WPR instead - */ - struct nvkm_gpuobj *acr_load_blob; - struct { - struct hsf_load_header load_bl_header; - struct hsf_load_header_app __load_apps[GM200_ACR_MAX_APPS]; - }; - - /* HS FW - unlock WPR region (dGPU only) */ - struct nvkm_gpuobj *acr_unload_blob; - struct { - struct hsf_load_header unload_bl_header; - struct hsf_load_header_app __unload_apps[GM200_ACR_MAX_APPS]; - }; - - /* HS bootloader */ - void *hsbl_blob; - - /* LS FWs, to be loaded by the HS ACR */ - struct nvkm_gpuobj *ls_blob; - - /* Instance block & address space used for HS FW execution */ - struct nvkm_gpuobj *inst; - struct nvkm_gpuobj *pgd; - struct nvkm_vm *vm; - - /* To keep track of the state of all managed falcons */ - enum { - /* In non-secure state, no firmware loaded, no privileges*/ - NON_SECURE = 0, - /* In low-secure mode and ready to be started */ - RESET, - /* In low-secure mode and running */ - RUNNING, - } falcon_state[NVKM_SECBOOT_FALCON_END]; - - bool firmware_ok; -}; -#define gm200_secboot(sb) container_of(sb, struct gm200_secboot, base) - -/** - * Contains functions we wish to abstract between GM200-like implementations - * @bl_desc_size: size of the BL descriptor used by this chip. - * @generate_bl_desc: hook that generates the proper BL descriptor format from - * the hsf_load_header format into a preallocated array of - * size bl_desc_size - * @prepare_blobs: prepares the various blobs needed for secure booting - */ -struct gm200_secboot_func { - /* - * Size of the bootloader descriptor for this chip. A block of this - * size is allocated before booting a falcon and the fixup_bl_desc - * callback is called on it - */ - u32 bl_desc_size; - void (*generate_bl_desc)(const struct hsf_load_header *, void *, u64); - - int (*prepare_blobs)(struct gm200_secboot *); -}; - -int gm200_secboot_oneinit(struct nvkm_secboot *); -void *gm200_secboot_dtor(struct nvkm_secboot *); -int gm200_secboot_reset(struct nvkm_secboot *, enum nvkm_secboot_falcon); -int gm200_secboot_start(struct nvkm_secboot *, enum nvkm_secboot_falcon); - -int gm20x_secboot_prepare_blobs(struct gm200_secboot *); - #endif -- cgit v1.1 From 8a50452c89037ccdb844011d1d71146418765fe4 Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Wed, 14 Dec 2016 17:02:40 +0900 Subject: drm/nouveau/secboot: add LS flags to LS func structure Add a flag that can be set when declaring how a LS firmware should be loaded. This allows us to remove falcon-specific code in the loader. Signed-off-by: Alexandre Courbot Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c | 10 ++++------ drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.h | 2 ++ drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c | 2 ++ 3 files changed, 8 insertions(+), 6 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c index d8cf06d..0d44575 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c @@ -266,13 +266,9 @@ ls_ucode_img_fill_headers(struct acr_r352 *acr, struct ls_ucode_img *img, desc->app_resident_data_offset; lhdr->app_data_size = desc->app_resident_data_size; - lhdr->flags = 0; + lhdr->flags = func->lhdr_flags; if (img->falcon_id == acr->base.boot_falcon) - lhdr->flags = LSF_FLAG_DMACTL_REQ_CTX; - - /* GPCCS will be loaded using PRI */ - if (img->falcon_id == NVKM_SECBOOT_FALCON_GPCCS) - lhdr->flags |= LSF_FLAG_FORCE_PRIV_LOAD; + lhdr->flags |= LSF_FLAG_DMACTL_REQ_CTX; /* Align and save off BL descriptor size */ lhdr->bl_data_size = ALIGN(func->bl_desc_size, LSF_BL_DATA_SIZE_ALIGN); @@ -862,6 +858,8 @@ acr_r352_ls_gpccs_func = { .load = acr_ls_ucode_load_gpccs, .generate_bl_desc = acr_r352_generate_flcn_bl_desc, .bl_desc_size = sizeof(struct acr_r352_flcn_bl_desc), + /* GPCCS will be loaded using PRI */ + .lhdr_flags = LSF_FLAG_FORCE_PRIV_LOAD, }; const struct acr_r352_func diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.h b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.h index 031bd09f..9323ed0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.h @@ -52,12 +52,14 @@ struct hsf_load_header { * @generate_bl_desc: function called on a block of bl_desc_size to generate the * proper bootloader descriptor for this LS firmware * @bl_desc_size: size of the bootloader descriptor + * @lhdr_flags: LS flags */ struct acr_r352_ls_func { int (*load)(const struct nvkm_subdev *, struct ls_ucode_img *); void (*generate_bl_desc)(const struct nvkm_acr *, const struct ls_ucode_img *, u64, void *); u32 bl_desc_size; + u32 lhdr_flags; }; /** diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c index ec1c558..097e641 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c @@ -115,6 +115,8 @@ acr_r361_ls_gpccs_func = { .load = acr_ls_ucode_load_gpccs, .generate_bl_desc = acr_r361_generate_flcn_bl_desc, .bl_desc_size = sizeof(struct acr_r361_flcn_bl_desc), + /* GPCCS will be loaded using PRI */ + .lhdr_flags = LSF_FLAG_FORCE_PRIV_LOAD, }; const struct acr_r352_func -- cgit v1.1 From 555cafb40445861c121422b157c74fe2de793e68 Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Wed, 14 Dec 2016 17:02:41 +0900 Subject: drm/nouveau/secboot: split reset function Split the reset function into more meaningful and reusable ones. Signed-off-by: Alexandre Courbot Signed-off-by: Ben Skeggs --- .../gpu/drm/nouveau/include/nvkm/subdev/secboot.h | 5 ++ .../gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c | 78 +++++++++++++++------- 2 files changed, 58 insertions(+), 25 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/secboot.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/secboot.h index 6e9e045..5dbd8aa 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/secboot.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/secboot.h @@ -34,6 +34,9 @@ enum nvkm_secboot_falcon { NVKM_SECBOOT_FALCON_INVALID = 0xffffffff, }; +/** + * @wpr_set: whether the WPR region is currently set +*/ struct nvkm_secboot { const struct nvkm_secboot_func *func; struct nvkm_acr *acr; @@ -42,6 +45,8 @@ struct nvkm_secboot { u64 wpr_addr; u32 wpr_size; + + bool wpr_set; }; #define nvkm_secboot(p) container_of((p), struct nvkm_secboot, subdev) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c index 0d44575..ea2ecd6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c @@ -740,6 +740,54 @@ acr_r352_load(struct nvkm_acr *_acr, struct nvkm_secboot *sb, return 0; } +static int +acr_r352_shutdown(struct acr_r352 *acr, struct nvkm_secboot *sb) +{ + int i; + + /* Run the unload blob to unprotect the WPR region */ + if (acr->unload_blob && sb->wpr_set) { + int ret; + + nvkm_debug(&sb->subdev, "running HS unload blob\n"); + ret = sb->func->run_blob(sb, acr->unload_blob); + if (ret) + return ret; + nvkm_debug(&sb->subdev, "HS unload blob completed\n"); + } + + for (i = 0; i < NVKM_SECBOOT_FALCON_END; i++) + acr->falcon_state[i] = NON_SECURE; + + sb->wpr_set = false; + + return 0; +} + +static int +acr_r352_bootstrap(struct acr_r352 *acr, struct nvkm_secboot *sb) +{ + int ret; + + if (sb->wpr_set) + return 0; + + /* Make sure all blobs are ready */ + ret = acr_r352_load_blobs(acr, sb); + if (ret) + return ret; + + nvkm_debug(&sb->subdev, "running HS load blob\n"); + ret = sb->func->run_blob(sb, acr->load_blob); + if (ret) + return ret; + nvkm_debug(&sb->subdev, "HS load blob completed\n"); + + sb->wpr_set = true; + + return 0; +} + /* * acr_r352_reset() - execute secure boot from the prepared state * @@ -754,11 +802,6 @@ acr_r352_reset(struct nvkm_acr *_acr, struct nvkm_secboot *sb, struct acr_r352 *acr = acr_r352(_acr); int ret; - /* Make sure all blobs are ready */ - ret = acr_r352_load_blobs(acr, sb); - if (ret) - return ret; - /* * Dummy GM200 implementation: perform secure boot each time we are * called on FECS. Since only FECS and GPCCS are managed and started @@ -770,16 +813,11 @@ acr_r352_reset(struct nvkm_acr *_acr, struct nvkm_secboot *sb, if (falcon != NVKM_SECBOOT_FALCON_FECS) goto end; - /* If WPR is set and we have an unload blob, run it to unlock WPR */ - if (acr->unload_blob && - acr->falcon_state[NVKM_SECBOOT_FALCON_FECS] != NON_SECURE) { - ret = sb->func->run_blob(sb, acr->unload_blob); - if (ret) - return ret; - } + ret = acr_r352_shutdown(acr, sb); + if (ret) + return ret; - /* Reload all managed falcons */ - ret = sb->func->run_blob(sb, acr->load_blob); + acr_r352_bootstrap(acr, sb); if (ret) return ret; @@ -818,18 +856,8 @@ static int acr_r352_fini(struct nvkm_acr *_acr, struct nvkm_secboot *sb, bool suspend) { struct acr_r352 *acr = acr_r352(_acr); - int ret = 0; - int i; - /* Run the unload blob to unprotect the WPR region */ - if (acr->unload_blob && - acr->falcon_state[NVKM_SECBOOT_FALCON_FECS] != NON_SECURE) - ret = sb->func->run_blob(sb, acr->unload_blob); - - for (i = 0; i < NVKM_SECBOOT_FALCON_END; i++) - acr->falcon_state[i] = NON_SECURE; - - return ret; + return acr_r352_shutdown(acr, sb); } static void -- cgit v1.1 From 3454a034b715a3b89f8efb92508ccc9fbee17e6f Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Wed, 14 Dec 2016 17:02:42 +0900 Subject: drm/nouveau/secboot: disable falcon interrupts when running blob Make sure we are not disturbed by spurious interrupts, as we poll the halt bit anyway. Signed-off-by: Alexandre Courbot Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c index f6a11e2..2fcb2f7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c @@ -27,6 +27,7 @@ #include #include #include +#include /** * gm200_secboot_run_blob() - run the given high-secure blob @@ -63,6 +64,9 @@ gm200_secboot_run_blob(struct nvkm_secboot *sb, struct nvkm_gpuobj *blob) if (ret) goto end; + /* Disable interrupts as we will poll for the HALT bit */ + nvkm_mc_intr_mask(sb->subdev.device, falcon->owner->index, false); + /* Start the HS bootloader */ nvkm_falcon_set_start_addr(falcon, sb->acr->start_address); nvkm_falcon_start(falcon); @@ -79,6 +83,9 @@ gm200_secboot_run_blob(struct nvkm_secboot *sb, struct nvkm_gpuobj *blob) } end: + /* Reenable interrupts */ + nvkm_mc_intr_mask(sb->subdev.device, falcon->owner->index, true); + /* We don't need the ACR firmware anymore */ nvkm_gpuobj_unmap(&vma); nvkm_falcon_put(falcon, subdev); -- cgit v1.1 From 88490323e46603bc99995a578b399cfc9a5d2ef1 Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Wed, 14 Dec 2016 17:02:43 +0900 Subject: drm/nouveau/secboot: remove unneeded ls_ucode_img member ucode_header is not used anywhere, so just get rid of it. Signed-off-by: Alexandre Courbot Signed-off-by: Ben Skeggs --- .../gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c | 25 ++++++---------------- .../gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode.h | 2 -- .../drm/nouveau/nvkm/subdev/secboot/ls_ucode_gr.c | 2 -- 3 files changed, 7 insertions(+), 22 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c index ea2ecd6..4986483 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c @@ -215,12 +215,6 @@ ls_ucode_img_fill_headers(struct acr_r352 *acr, struct ls_ucode_img *img, const struct acr_r352_ls_func *func = acr->func->ls_func[img->falcon_id]; - if (img->ucode_header) { - nvkm_fatal(acr->base.subdev, - "images withough loader are not supported yet!\n"); - return offset; - } - /* Fill WPR header */ whdr->falcon_id = img->falcon_id; whdr->bootstrap_owner = acr->base.boot_falcon; @@ -309,7 +303,6 @@ ls_ucode_mgr_cleanup(struct ls_ucode_mgr *mgr) list_for_each_entry_safe(img, t, &mgr->img_list, node) { kfree(img->ucode_data); - kfree(img->ucode_header); kfree(img); } } @@ -362,6 +355,10 @@ ls_ucode_mgr_write_wpr(struct acr_r352 *acr, struct ls_ucode_mgr *mgr, nvkm_kmap(wpr_blob); list_for_each_entry(img, &mgr->img_list, node) { + const struct acr_r352_ls_func *ls_func = + acr->func->ls_func[img->falcon_id]; + u8 gdesc[ls_func->bl_desc_size]; + nvkm_gpuobj_memcpy_to(wpr_blob, pos, &img->wpr_header, sizeof(img->wpr_header)); @@ -369,18 +366,10 @@ ls_ucode_mgr_write_wpr(struct acr_r352 *acr, struct ls_ucode_mgr *mgr, &img->lsb_header, sizeof(img->lsb_header)); /* Generate and write BL descriptor */ - if (!img->ucode_header) { - const struct acr_r352_ls_func *ls_func = - acr->func->ls_func[img->falcon_id]; - u8 gdesc[ls_func->bl_desc_size]; - - ls_func->generate_bl_desc(&acr->base, img, wpr_addr, - gdesc); + ls_func->generate_bl_desc(&acr->base, img, wpr_addr, gdesc); - nvkm_gpuobj_memcpy_to(wpr_blob, - img->lsb_header.bl_data_off, - gdesc, ls_func->bl_desc_size); - } + nvkm_gpuobj_memcpy_to(wpr_blob, img->lsb_header.bl_data_off, + gdesc, ls_func->bl_desc_size); /* Copy ucode */ nvkm_gpuobj_memcpy_to(wpr_blob, img->lsb_header.ucode_off, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode.h b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode.h index 3598ed5..be9eac5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode.h @@ -173,7 +173,6 @@ struct ls_ucode_img_desc { * @node: to link within lsf_ucode_mgr * @falcon_id: ID of the falcon this LS firmware is for * @ucode_desc: loaded or generated map of ucode_data - * @ucode_header: header of the firmware * @ucode_data: firmware payload (code and data) * @ucode_size: size in bytes of data in ucode_data * @wpr_header: WPR header to be written to the LS blob @@ -188,7 +187,6 @@ struct ls_ucode_img { enum nvkm_secboot_falcon falcon_id; struct ls_ucode_img_desc ucode_desc; - u32 *ucode_header; u8 *ucode_data; u32 ucode_size; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_gr.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_gr.c index f9c0c64..197ec1b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_gr.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_gr.c @@ -98,8 +98,6 @@ ls_ucode_img_load_gr(const struct nvkm_subdev *subdev, struct ls_ucode_img *img, char f[64]; int ret; - img->ucode_header = NULL; - snprintf(f, sizeof(f), "gr/%s_bl", falcon_name); ret = nvkm_firmware_get(subdev->device, f, &bl); if (ret) -- cgit v1.1 From 9839307cfeedca72d4f2c27d60ada4a1ec5c9489 Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Wed, 14 Dec 2016 17:02:44 +0900 Subject: drm/nouveau/secboot: remove ls_ucode_mgr This was used only locally to one function and can be replaced by ad-hoc variables. Signed-off-by: Alexandre Courbot Signed-off-by: Ben Skeggs --- .../gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c | 90 ++++++++-------------- 1 file changed, 33 insertions(+), 57 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c index 4986483..c193fa90 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c @@ -278,75 +278,44 @@ ls_ucode_img_fill_headers(struct acr_r352 *acr, struct ls_ucode_img *img, } /** - * struct ls_ucode_mgr - manager for all LS falcon firmwares - * @count: number of managed LS falcons - * @wpr_size: size of the required WPR region in bytes - * @img_list: linked list of lsf_ucode_img + * acr_r352_ls_fill_headers - fill WPR and LSB headers of all managed images */ -struct ls_ucode_mgr { - u16 count; - u32 wpr_size; - struct list_head img_list; -}; - -static void -ls_ucode_mgr_init(struct ls_ucode_mgr *mgr) -{ - memset(mgr, 0, sizeof(*mgr)); - INIT_LIST_HEAD(&mgr->img_list); -} - -static void -ls_ucode_mgr_cleanup(struct ls_ucode_mgr *mgr) -{ - struct ls_ucode_img *img, *t; - - list_for_each_entry_safe(img, t, &mgr->img_list, node) { - kfree(img->ucode_data); - kfree(img); - } -} - -static void -ls_ucode_mgr_add_img(struct ls_ucode_mgr *mgr, struct ls_ucode_img *img) -{ - mgr->count++; - list_add_tail(&img->node, &mgr->img_list); -} - -/** - * ls_ucode_mgr_fill_headers - fill WPR and LSB headers of all managed images - */ -static void -ls_ucode_mgr_fill_headers(struct acr_r352 *acr, struct ls_ucode_mgr *mgr) +static int +acr_r352_ls_fill_headers(struct acr_r352 *acr, struct list_head *imgs) { struct ls_ucode_img *img; + struct list_head *l; + u32 count = 0; u32 offset; + /* Count the number of images to manage */ + list_for_each(l, imgs) + count++; + /* * Start with an array of WPR headers at the base of the WPR. * The expectation here is that the secure falcon will do a single DMA * read of this array and cache it internally so it's ok to pack these. * Also, we add 1 to the falcon count to indicate the end of the array. */ - offset = sizeof(struct lsf_wpr_header) * (mgr->count + 1); + offset = sizeof(struct lsf_wpr_header) * (count + 1); /* * Walk the managed falcons, accounting for the LSB structs * as well as the ucode images. */ - list_for_each_entry(img, &mgr->img_list, node) { + list_for_each_entry(img, imgs, node) { offset = ls_ucode_img_fill_headers(acr, img, offset); } - mgr->wpr_size = offset; + return offset; } /** * ls_ucode_mgr_write_wpr - write the WPR blob contents */ static int -ls_ucode_mgr_write_wpr(struct acr_r352 *acr, struct ls_ucode_mgr *mgr, +ls_ucode_mgr_write_wpr(struct acr_r352 *acr, struct list_head *imgs, struct nvkm_gpuobj *wpr_blob, u32 wpr_addr) { struct ls_ucode_img *img; @@ -354,7 +323,7 @@ ls_ucode_mgr_write_wpr(struct acr_r352 *acr, struct ls_ucode_mgr *mgr, nvkm_kmap(wpr_blob); - list_for_each_entry(img, &mgr->img_list, node) { + list_for_each_entry(img, imgs, node) { const struct acr_r352_ls_func *ls_func = acr->func->ls_func[img->falcon_id]; u8 gdesc[ls_func->bl_desc_size]; @@ -399,12 +368,15 @@ static int acr_r352_prepare_ls_blob(struct acr_r352 *acr, u64 wpr_addr, u32 wpr_size) { const struct nvkm_subdev *subdev = acr->base.subdev; - struct ls_ucode_mgr mgr; + struct list_head imgs; + struct ls_ucode_img *img, *t; unsigned long managed_falcons = acr->base.managed_falcons; + int managed_count = 0; + u32 image_wpr_size; int falcon_id; int ret; - ls_ucode_mgr_init(&mgr); + INIT_LIST_HEAD(&imgs); /* Load all LS blobs */ for_each_set_bit(falcon_id, &managed_falcons, NVKM_SECBOOT_FALCON_END) { @@ -417,48 +389,52 @@ acr_r352_prepare_ls_blob(struct acr_r352 *acr, u64 wpr_addr, u32 wpr_size) ret = PTR_ERR(img); goto cleanup; } - ls_ucode_mgr_add_img(&mgr, img); + list_add_tail(&img->node, &imgs); + managed_count++; } /* * Fill the WPR and LSF headers with the right offsets and compute * required WPR size */ - ls_ucode_mgr_fill_headers(acr, &mgr); - mgr.wpr_size = ALIGN(mgr.wpr_size, WPR_ALIGNMENT); + image_wpr_size = acr_r352_ls_fill_headers(acr, &imgs); + image_wpr_size = ALIGN(image_wpr_size, WPR_ALIGNMENT); /* Allocate GPU object that will contain the WPR region */ - ret = nvkm_gpuobj_new(subdev->device, mgr.wpr_size, WPR_ALIGNMENT, + ret = nvkm_gpuobj_new(subdev->device, image_wpr_size, WPR_ALIGNMENT, false, NULL, &acr->ls_blob); if (ret) goto cleanup; nvkm_debug(subdev, "%d managed LS falcons, WPR size is %d bytes\n", - mgr.count, mgr.wpr_size); + managed_count, image_wpr_size); /* If WPR address and size are not fixed, set them to fit the LS blob */ if (wpr_size == 0) { wpr_addr = acr->ls_blob->addr; - wpr_size = mgr.wpr_size; + wpr_size = image_wpr_size; /* * But if the WPR region is set by the bootloader, it is illegal for * the HS blob to be larger than this region. */ - } else if (mgr.wpr_size > wpr_size) { + } else if (image_wpr_size > wpr_size) { nvkm_error(subdev, "WPR region too small for FW blob!\n"); - nvkm_error(subdev, "required: %dB\n", mgr.wpr_size); + nvkm_error(subdev, "required: %dB\n", image_wpr_size); nvkm_error(subdev, "available: %dB\n", wpr_size); ret = -ENOSPC; goto cleanup; } /* Write LS blob */ - ret = ls_ucode_mgr_write_wpr(acr, &mgr, acr->ls_blob, wpr_addr); + ret = ls_ucode_mgr_write_wpr(acr, &imgs, acr->ls_blob, wpr_addr); if (ret) nvkm_gpuobj_del(&acr->ls_blob); cleanup: - ls_ucode_mgr_cleanup(&mgr); + list_for_each_entry_safe(img, t, &imgs, node) { + kfree(img->ucode_data); + kfree(img); + } return ret; } -- cgit v1.1 From 9d896f3e41a6093a843ce668c97159367c1e4573 Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Wed, 14 Dec 2016 17:02:45 +0900 Subject: drm/nouveau/secboot: abstract LS firmware loading functions The WPR and LSB headers, used to generate the LS blob, may have a different layout and sizes depending on the driver version they come from. Abstract them and confine their use to driver-specific code. Signed-off-by: Alexandre Courbot Signed-off-by: Ben Skeggs --- .../gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c | 102 +++++++++++------- .../gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.h | 119 +++++++++++++++++++++ .../gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c | 9 +- drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c | 9 +- .../gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode.h | 100 +---------------- .../drm/nouveau/nvkm/subdev/secboot/ls_ucode_gr.c | 41 +++---- drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h | 2 + 7 files changed, 215 insertions(+), 167 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c index c193fa90..741f3fc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c @@ -21,7 +21,6 @@ */ #include "acr_r352.h" -#include "ls_ucode.h" #include #include @@ -94,11 +93,12 @@ struct acr_r352_flcn_bl_desc { */ static void acr_r352_generate_flcn_bl_desc(const struct nvkm_acr *acr, - const struct ls_ucode_img *img, u64 wpr_addr, + const struct ls_ucode_img *_img, u64 wpr_addr, void *_desc) { + struct ls_ucode_img_r352 *img = ls_ucode_img_r352(_img); struct acr_r352_flcn_bl_desc *desc = _desc; - const struct ls_ucode_img_desc *pdesc = &img->ucode_desc; + const struct ls_ucode_img_desc *pdesc = &_img->ucode_desc; u64 base, addr_code, addr_data; base = wpr_addr + img->lsb_header.ucode_off + pdesc->app_start_offset; @@ -163,29 +163,46 @@ struct hsflcn_acr_desc { * Low-secure blob creation */ -typedef int (*lsf_load_func)(const struct nvkm_subdev *, struct ls_ucode_img *); - /** * ls_ucode_img_load() - create a lsf_ucode_img and load it */ -static struct ls_ucode_img * -ls_ucode_img_load(const struct nvkm_subdev *subdev, lsf_load_func load_func) +struct ls_ucode_img * +acr_r352_ls_ucode_img_load(const struct acr_r352 *acr, + enum nvkm_secboot_falcon falcon_id) { - struct ls_ucode_img *img; + const struct nvkm_subdev *subdev = acr->base.subdev; + struct ls_ucode_img_r352 *img; int ret; img = kzalloc(sizeof(*img), GFP_KERNEL); if (!img) return ERR_PTR(-ENOMEM); - ret = load_func(subdev, img); + img->base.falcon_id = falcon_id; + + ret = acr->func->ls_func[falcon_id]->load(subdev, &img->base); if (ret) { + kfree(img->base.ucode_data); + kfree(img->base.sig); kfree(img); return ERR_PTR(ret); } - return img; + /* Check that the signature size matches our expectations... */ + if (img->base.sig_size != sizeof(img->lsb_header.signature)) { + nvkm_error(subdev, "invalid signature size for %s falcon!\n", + nvkm_secboot_falcon_name[falcon_id]); + return ERR_PTR(-EINVAL); + } + + /* Copy signature to the right place */ + memcpy(&img->lsb_header.signature, img->base.sig, img->base.sig_size); + + /* not needed? the signature should already have the right value */ + img->lsb_header.signature.falcon_id = falcon_id; + + return &img->base; } #define LSF_LSB_HEADER_ALIGN 256 @@ -195,7 +212,7 @@ ls_ucode_img_load(const struct nvkm_subdev *subdev, lsf_load_func load_func) #define LSF_UCODE_DATA_ALIGN 4096 /** - * ls_ucode_img_fill_headers - fill the WPR and LSB headers of an image + * acr_r352_ls_img_fill_headers - fill the WPR and LSB headers of an image * @acr: ACR to use * @img: image to generate for * @offset: offset in the WPR region where this image starts @@ -206,24 +223,25 @@ ls_ucode_img_load(const struct nvkm_subdev *subdev, lsf_load_func load_func) * Return: offset at the end of this image. */ static u32 -ls_ucode_img_fill_headers(struct acr_r352 *acr, struct ls_ucode_img *img, - u32 offset) +acr_r352_ls_img_fill_headers(struct acr_r352 *acr, + struct ls_ucode_img_r352 *img, u32 offset) { - struct lsf_wpr_header *whdr = &img->wpr_header; - struct lsf_lsb_header *lhdr = &img->lsb_header; - struct ls_ucode_img_desc *desc = &img->ucode_desc; + struct ls_ucode_img *_img = &img->base; + struct acr_r352_lsf_wpr_header *whdr = &img->wpr_header; + struct acr_r352_lsf_lsb_header *lhdr = &img->lsb_header; + struct ls_ucode_img_desc *desc = &_img->ucode_desc; const struct acr_r352_ls_func *func = - acr->func->ls_func[img->falcon_id]; + acr->func->ls_func[_img->falcon_id]; /* Fill WPR header */ - whdr->falcon_id = img->falcon_id; + whdr->falcon_id = _img->falcon_id; whdr->bootstrap_owner = acr->base.boot_falcon; whdr->status = LSF_IMAGE_STATUS_COPY; /* Align, save off, and include an LSB header size */ offset = ALIGN(offset, LSF_LSB_HEADER_ALIGN); whdr->lsb_offset = offset; - offset += sizeof(struct lsf_lsb_header); + offset += sizeof(*lhdr); /* * Align, save off, and include the original (static) ucode @@ -231,7 +249,7 @@ ls_ucode_img_fill_headers(struct acr_r352 *acr, struct ls_ucode_img *img, */ offset = ALIGN(offset, LSF_UCODE_DATA_ALIGN); lhdr->ucode_off = offset; - offset += img->ucode_size; + offset += _img->ucode_size; /* * For falcons that use a boot loader (BL), we append a loader @@ -261,7 +279,7 @@ ls_ucode_img_fill_headers(struct acr_r352 *acr, struct ls_ucode_img *img, lhdr->app_data_size = desc->app_resident_data_size; lhdr->flags = func->lhdr_flags; - if (img->falcon_id == acr->base.boot_falcon) + if (_img->falcon_id == acr->base.boot_falcon) lhdr->flags |= LSF_FLAG_DMACTL_REQ_CTX; /* Align and save off BL descriptor size */ @@ -280,10 +298,10 @@ ls_ucode_img_fill_headers(struct acr_r352 *acr, struct ls_ucode_img *img, /** * acr_r352_ls_fill_headers - fill WPR and LSB headers of all managed images */ -static int +int acr_r352_ls_fill_headers(struct acr_r352 *acr, struct list_head *imgs) { - struct ls_ucode_img *img; + struct ls_ucode_img_r352 *img; struct list_head *l; u32 count = 0; u32 offset; @@ -298,34 +316,35 @@ acr_r352_ls_fill_headers(struct acr_r352 *acr, struct list_head *imgs) * read of this array and cache it internally so it's ok to pack these. * Also, we add 1 to the falcon count to indicate the end of the array. */ - offset = sizeof(struct lsf_wpr_header) * (count + 1); + offset = sizeof(img->wpr_header) * (count + 1); /* * Walk the managed falcons, accounting for the LSB structs * as well as the ucode images. */ - list_for_each_entry(img, imgs, node) { - offset = ls_ucode_img_fill_headers(acr, img, offset); + list_for_each_entry(img, imgs, base.node) { + offset = acr_r352_ls_img_fill_headers(acr, img, offset); } return offset; } /** - * ls_ucode_mgr_write_wpr - write the WPR blob contents + * acr_r352_ls_write_wpr - write the WPR blob contents */ -static int -ls_ucode_mgr_write_wpr(struct acr_r352 *acr, struct list_head *imgs, - struct nvkm_gpuobj *wpr_blob, u32 wpr_addr) +int +acr_r352_ls_write_wpr(struct acr_r352 *acr, struct list_head *imgs, + struct nvkm_gpuobj *wpr_blob, u32 wpr_addr) { - struct ls_ucode_img *img; + struct ls_ucode_img *_img; u32 pos = 0; nvkm_kmap(wpr_blob); - list_for_each_entry(img, imgs, node) { + list_for_each_entry(_img, imgs, node) { + struct ls_ucode_img_r352 *img = ls_ucode_img_r352(_img); const struct acr_r352_ls_func *ls_func = - acr->func->ls_func[img->falcon_id]; + acr->func->ls_func[_img->falcon_id]; u8 gdesc[ls_func->bl_desc_size]; nvkm_gpuobj_memcpy_to(wpr_blob, pos, &img->wpr_header, @@ -335,14 +354,14 @@ ls_ucode_mgr_write_wpr(struct acr_r352 *acr, struct list_head *imgs, &img->lsb_header, sizeof(img->lsb_header)); /* Generate and write BL descriptor */ - ls_func->generate_bl_desc(&acr->base, img, wpr_addr, gdesc); + ls_func->generate_bl_desc(&acr->base, _img, wpr_addr, gdesc); nvkm_gpuobj_memcpy_to(wpr_blob, img->lsb_header.bl_data_off, gdesc, ls_func->bl_desc_size); /* Copy ucode */ nvkm_gpuobj_memcpy_to(wpr_blob, img->lsb_header.ucode_off, - img->ucode_data, img->ucode_size); + _img->ucode_data, _img->ucode_size); pos += sizeof(img->wpr_header); } @@ -382,13 +401,12 @@ acr_r352_prepare_ls_blob(struct acr_r352 *acr, u64 wpr_addr, u32 wpr_size) for_each_set_bit(falcon_id, &managed_falcons, NVKM_SECBOOT_FALCON_END) { struct ls_ucode_img *img; - img = ls_ucode_img_load(subdev, - acr->func->ls_func[falcon_id]->load); - + img = acr->func->ls_ucode_img_load(acr, falcon_id); if (IS_ERR(img)) { ret = PTR_ERR(img); goto cleanup; } + list_add_tail(&img->node, &imgs); managed_count++; } @@ -397,7 +415,7 @@ acr_r352_prepare_ls_blob(struct acr_r352 *acr, u64 wpr_addr, u32 wpr_size) * Fill the WPR and LSF headers with the right offsets and compute * required WPR size */ - image_wpr_size = acr_r352_ls_fill_headers(acr, &imgs); + image_wpr_size = acr->func->ls_fill_headers(acr, &imgs); image_wpr_size = ALIGN(image_wpr_size, WPR_ALIGNMENT); /* Allocate GPU object that will contain the WPR region */ @@ -426,13 +444,14 @@ acr_r352_prepare_ls_blob(struct acr_r352 *acr, u64 wpr_addr, u32 wpr_size) } /* Write LS blob */ - ret = ls_ucode_mgr_write_wpr(acr, &imgs, acr->ls_blob, wpr_addr); + ret = acr->func->ls_write_wpr(acr, &imgs, acr->ls_blob, wpr_addr); if (ret) nvkm_gpuobj_del(&acr->ls_blob); cleanup: list_for_each_entry_safe(img, t, &imgs, node) { kfree(img->ucode_data); + kfree(img->sig); kfree(img); } @@ -859,6 +878,9 @@ const struct acr_r352_func acr_r352_func = { .generate_hs_bl_desc = acr_r352_generate_hs_bl_desc, .hs_bl_desc_size = sizeof(struct acr_r352_flcn_bl_desc), + .ls_ucode_img_load = acr_r352_ls_ucode_img_load, + .ls_fill_headers = acr_r352_ls_fill_headers, + .ls_write_wpr = acr_r352_ls_write_wpr, .ls_func = { [NVKM_SECBOOT_FALCON_FECS] = &acr_r352_ls_fecs_func, [NVKM_SECBOOT_FALCON_GPCCS] = &acr_r352_ls_gpccs_func, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.h b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.h index 9323ed0..f335dce 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.h @@ -23,11 +23,116 @@ #define __NVKM_SECBOOT_ACR_R352_H__ #include "acr.h" +#include "ls_ucode.h" struct ls_ucode_img; #define ACR_R352_MAX_APPS 8 +/* + * + * LS blob structures + * + */ + +/** + * struct acr_r352_lsf_lsb_header - LS firmware header + * @signature: signature to verify the firmware against + * @ucode_off: offset of the ucode blob in the WPR region. The ucode + * blob contains the bootloader, code and data of the + * LS falcon + * @ucode_size: size of the ucode blob, including bootloader + * @data_size: size of the ucode blob data + * @bl_code_size: size of the bootloader code + * @bl_imem_off: offset in imem of the bootloader + * @bl_data_off: offset of the bootloader data in WPR region + * @bl_data_size: size of the bootloader data + * @app_code_off: offset of the app code relative to ucode_off + * @app_code_size: size of the app code + * @app_data_off: offset of the app data relative to ucode_off + * @app_data_size: size of the app data + * @flags: flags for the secure bootloader + * + * This structure is written into the WPR region for each managed falcon. Each + * instance is referenced by the lsb_offset member of the corresponding + * lsf_wpr_header. + */ +struct acr_r352_lsf_lsb_header { + /** + * LS falcon signatures + * @prd_keys: signature to use in production mode + * @dgb_keys: signature to use in debug mode + * @b_prd_present: whether the production key is present + * @b_dgb_present: whether the debug key is present + * @falcon_id: ID of the falcon the ucode applies to + */ + struct { + u8 prd_keys[2][16]; + u8 dbg_keys[2][16]; + u32 b_prd_present; + u32 b_dbg_present; + u32 falcon_id; + } signature; + u32 ucode_off; + u32 ucode_size; + u32 data_size; + u32 bl_code_size; + u32 bl_imem_off; + u32 bl_data_off; + u32 bl_data_size; + u32 app_code_off; + u32 app_code_size; + u32 app_data_off; + u32 app_data_size; + u32 flags; +#define LSF_FLAG_LOAD_CODE_AT_0 1 +#define LSF_FLAG_DMACTL_REQ_CTX 4 +#define LSF_FLAG_FORCE_PRIV_LOAD 8 +}; + +/** + * struct acr_r352_lsf_wpr_header - LS blob WPR Header + * @falcon_id: LS falcon ID + * @lsb_offset: offset of the lsb_lsf_header in the WPR region + * @bootstrap_owner: secure falcon reponsible for bootstrapping the LS falcon + * @lazy_bootstrap: skip bootstrapping by ACR + * @status: bootstrapping status + * + * An array of these is written at the beginning of the WPR region, one for + * each managed falcon. The array is terminated by an instance which falcon_id + * is LSF_FALCON_ID_INVALID. + */ +struct acr_r352_lsf_wpr_header { + u32 falcon_id; + u32 lsb_offset; + u32 bootstrap_owner; + u32 lazy_bootstrap; + u32 status; +#define LSF_IMAGE_STATUS_NONE 0 +#define LSF_IMAGE_STATUS_COPY 1 +#define LSF_IMAGE_STATUS_VALIDATION_CODE_FAILED 2 +#define LSF_IMAGE_STATUS_VALIDATION_DATA_FAILED 3 +#define LSF_IMAGE_STATUS_VALIDATION_DONE 4 +#define LSF_IMAGE_STATUS_VALIDATION_SKIPPED 5 +#define LSF_IMAGE_STATUS_BOOTSTRAP_READY 6 +}; + +/** + * struct ls_ucode_img_r352 - ucode image augmented with r352 headers + */ +struct ls_ucode_img_r352 { + struct ls_ucode_img base; + + struct acr_r352_lsf_wpr_header wpr_header; + struct acr_r352_lsf_lsb_header lsb_header; +}; +#define ls_ucode_img_r352(i) container_of(i, struct ls_ucode_img_r352, base) + + +/* + * HS blob structures + */ + struct hsf_load_header_app { u32 sec_code_off; u32 sec_code_size; @@ -62,6 +167,8 @@ struct acr_r352_ls_func { u32 lhdr_flags; }; +struct acr_r352; + /** * struct acr_r352_func - manages nuances between ACR versions * @@ -74,6 +181,12 @@ struct acr_r352_func { u64); u32 hs_bl_desc_size; + struct ls_ucode_img *(*ls_ucode_img_load)(const struct acr_r352 *, + enum nvkm_secboot_falcon); + int (*ls_fill_headers)(struct acr_r352 *, struct list_head *); + int (*ls_write_wpr)(struct acr_r352 *, struct list_head *, + struct nvkm_gpuobj *, u32); + const struct acr_r352_ls_func *ls_func[NVKM_SECBOOT_FALCON_END]; }; @@ -125,4 +238,10 @@ struct acr_r352 { struct nvkm_acr *acr_r352_new_(const struct acr_r352_func *, enum nvkm_secboot_falcon, unsigned long); +struct ls_ucode_img *acr_r352_ls_ucode_img_load(const struct acr_r352 *, + enum nvkm_secboot_falcon); +int acr_r352_ls_fill_headers(struct acr_r352 *, struct list_head *); +int acr_r352_ls_write_wpr(struct acr_r352 *, struct list_head *, + struct nvkm_gpuobj *, u32); + #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c index 097e641..4b9a688 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c @@ -21,7 +21,6 @@ */ #include "acr_r352.h" -#include "ls_ucode.h" #include @@ -64,11 +63,12 @@ struct acr_r361_flcn_bl_desc { static void acr_r361_generate_flcn_bl_desc(const struct nvkm_acr *acr, - const struct ls_ucode_img *img, u64 wpr_addr, + const struct ls_ucode_img *_img, u64 wpr_addr, void *_desc) { + struct ls_ucode_img_r352 *img = ls_ucode_img_r352(_img); struct acr_r361_flcn_bl_desc *desc = _desc; - const struct ls_ucode_img_desc *pdesc = &img->ucode_desc; + const struct ls_ucode_img_desc *pdesc = &img->base.ucode_desc; u64 base, addr_code, addr_data; base = wpr_addr + img->lsb_header.ucode_off + pdesc->app_start_offset; @@ -123,6 +123,9 @@ const struct acr_r352_func acr_r361_func = { .generate_hs_bl_desc = acr_r361_generate_hs_bl_desc, .hs_bl_desc_size = sizeof(struct acr_r361_flcn_bl_desc), + .ls_ucode_img_load = acr_r352_ls_ucode_img_load, + .ls_fill_headers = acr_r352_ls_fill_headers, + .ls_write_wpr = acr_r352_ls_write_wpr, .ls_func = { [NVKM_SECBOOT_FALCON_FECS] = &acr_r361_ls_fecs_func, [NVKM_SECBOOT_FALCON_GPCCS] = &acr_r361_ls_gpccs_func, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c index ad739c6..27c9dff 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c @@ -88,8 +88,8 @@ #include #include -static const char * -managed_falcons_names[] = { +const char * +nvkm_secboot_falcon_name[] = { [NVKM_SECBOOT_FALCON_PMU] = "PMU", [NVKM_SECBOOT_FALCON_RESERVED] = "", [NVKM_SECBOOT_FALCON_FECS] = "FECS", @@ -135,7 +135,7 @@ nvkm_secboot_oneinit(struct nvkm_subdev *subdev) break; default: nvkm_error(subdev, "Unmanaged boot falcon %s!\n", - managed_falcons_names[sb->acr->boot_falcon]); + nvkm_secboot_falcon_name[sb->acr->boot_falcon]); return -EINVAL; } @@ -197,7 +197,8 @@ nvkm_secboot_ctor(const struct nvkm_secboot_func *func, struct nvkm_acr *acr, nvkm_debug(&sb->subdev, "securely managed falcons:\n"); for_each_set_bit(fid, &sb->acr->managed_falcons, NVKM_SECBOOT_FALCON_END) - nvkm_debug(&sb->subdev, "- %s\n", managed_falcons_names[fid]); + nvkm_debug(&sb->subdev, "- %s\n", + nvkm_secboot_falcon_name[fid]); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode.h b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode.h index be9eac5..00886ce 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode.h @@ -27,98 +27,6 @@ #include #include -/* - * - * LS blob structures - * - */ - -/** - * struct lsf_ucode_desc - LS falcon signatures - * @prd_keys: signature to use when the GPU is in production mode - * @dgb_keys: signature to use when the GPU is in debug mode - * @b_prd_present: whether the production key is present - * @b_dgb_present: whether the debug key is present - * @falcon_id: ID of the falcon the ucode applies to - * - * Directly loaded from a signature file. - */ -struct lsf_ucode_desc { - u8 prd_keys[2][16]; - u8 dbg_keys[2][16]; - u32 b_prd_present; - u32 b_dbg_present; - u32 falcon_id; -}; - -/** - * struct lsf_lsb_header - LS firmware header - * @signature: signature to verify the firmware against - * @ucode_off: offset of the ucode blob in the WPR region. The ucode - * blob contains the bootloader, code and data of the - * LS falcon - * @ucode_size: size of the ucode blob, including bootloader - * @data_size: size of the ucode blob data - * @bl_code_size: size of the bootloader code - * @bl_imem_off: offset in imem of the bootloader - * @bl_data_off: offset of the bootloader data in WPR region - * @bl_data_size: size of the bootloader data - * @app_code_off: offset of the app code relative to ucode_off - * @app_code_size: size of the app code - * @app_data_off: offset of the app data relative to ucode_off - * @app_data_size: size of the app data - * @flags: flags for the secure bootloader - * - * This structure is written into the WPR region for each managed falcon. Each - * instance is referenced by the lsb_offset member of the corresponding - * lsf_wpr_header. - */ -struct lsf_lsb_header { - struct lsf_ucode_desc signature; - u32 ucode_off; - u32 ucode_size; - u32 data_size; - u32 bl_code_size; - u32 bl_imem_off; - u32 bl_data_off; - u32 bl_data_size; - u32 app_code_off; - u32 app_code_size; - u32 app_data_off; - u32 app_data_size; - u32 flags; -#define LSF_FLAG_LOAD_CODE_AT_0 1 -#define LSF_FLAG_DMACTL_REQ_CTX 4 -#define LSF_FLAG_FORCE_PRIV_LOAD 8 -}; - -/** - * struct lsf_wpr_header - LS blob WPR Header - * @falcon_id: LS falcon ID - * @lsb_offset: offset of the lsb_lsf_header in the WPR region - * @bootstrap_owner: secure falcon reponsible for bootstrapping the LS falcon - * @lazy_bootstrap: skip bootstrapping by ACR - * @status: bootstrapping status - * - * An array of these is written at the beginning of the WPR region, one for - * each managed falcon. The array is terminated by an instance which falcon_id - * is LSF_FALCON_ID_INVALID. - */ -struct lsf_wpr_header { - u32 falcon_id; - u32 lsb_offset; - u32 bootstrap_owner; - u32 lazy_bootstrap; - u32 status; -#define LSF_IMAGE_STATUS_NONE 0 -#define LSF_IMAGE_STATUS_COPY 1 -#define LSF_IMAGE_STATUS_VALIDATION_CODE_FAILED 2 -#define LSF_IMAGE_STATUS_VALIDATION_DATA_FAILED 3 -#define LSF_IMAGE_STATUS_VALIDATION_DONE 4 -#define LSF_IMAGE_STATUS_VALIDATION_SKIPPED 5 -#define LSF_IMAGE_STATUS_BOOTSTRAP_READY 6 -}; - /** * struct ls_ucode_img_desc - descriptor of firmware image @@ -175,8 +83,8 @@ struct ls_ucode_img_desc { * @ucode_desc: loaded or generated map of ucode_data * @ucode_data: firmware payload (code and data) * @ucode_size: size in bytes of data in ucode_data - * @wpr_header: WPR header to be written to the LS blob - * @lsb_header: LSB header to be written to the LS blob + * @sig: signature for this firmware + * @sig:size: size of the signature in bytes * * Preparing the WPR LS blob requires information about all the LS firmwares * (size, etc) to be known. This structure contains all the data of one LS @@ -190,8 +98,8 @@ struct ls_ucode_img { u8 *ucode_data; u32 ucode_size; - struct lsf_wpr_header wpr_header; - struct lsf_lsb_header lsb_header; + u8 *sig; + u32 sig_size; }; /** diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_gr.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_gr.c index 197ec1b..40a6df7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_gr.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/ls_ucode_gr.c @@ -91,10 +91,9 @@ ls_ucode_img_build(const struct firmware *bl, const struct firmware *code, */ static int ls_ucode_img_load_gr(const struct nvkm_subdev *subdev, struct ls_ucode_img *img, - const char *falcon_name, const u32 falcon_id) + const char *falcon_name) { - const struct firmware *bl, *code, *data; - struct lsf_ucode_desc *lsf_desc; + const struct firmware *bl, *code, *data, *sig; char f[64]; int ret; @@ -113,6 +112,17 @@ ls_ucode_img_load_gr(const struct nvkm_subdev *subdev, struct ls_ucode_img *img, if (ret) goto free_inst; + snprintf(f, sizeof(f), "gr/%s_sig", falcon_name); + ret = nvkm_firmware_get(subdev->device, f, &sig); + if (ret) + goto free_data; + img->sig = kmemdup(sig->data, sig->size, GFP_KERNEL); + if (!img->sig) { + ret = -ENOMEM; + goto free_sig; + } + img->sig_size = sig->size; + img->ucode_data = ls_ucode_img_build(bl, code, data, &img->ucode_desc); if (IS_ERR(img->ucode_data)) { @@ -121,23 +131,8 @@ ls_ucode_img_load_gr(const struct nvkm_subdev *subdev, struct ls_ucode_img *img, } img->ucode_size = img->ucode_desc.image_size; - snprintf(f, sizeof(f), "gr/%s_sig", falcon_name); - lsf_desc = nvkm_acr_load_firmware(subdev, f, sizeof(*lsf_desc)); - if (IS_ERR(lsf_desc)) { - ret = PTR_ERR(lsf_desc); - goto free_image; - } - /* not needed? the signature should already have the right value */ - lsf_desc->falcon_id = falcon_id; - memcpy(&img->lsb_header.signature, lsf_desc, sizeof(*lsf_desc)); - img->falcon_id = lsf_desc->falcon_id; - kfree(lsf_desc); - - /* success path - only free requested firmware files */ - goto free_data; - -free_image: - kfree(img->ucode_data); +free_sig: + nvkm_firmware_put(sig); free_data: nvkm_firmware_put(data); free_inst: @@ -152,14 +147,12 @@ int acr_ls_ucode_load_fecs(const struct nvkm_subdev *subdev, struct ls_ucode_img *img) { - return ls_ucode_img_load_gr(subdev, img, "fecs", - NVKM_SECBOOT_FALCON_FECS); + return ls_ucode_img_load_gr(subdev, img, "fecs"); } int acr_ls_ucode_load_gpccs(const struct nvkm_subdev *subdev, struct ls_ucode_img *img) { - return ls_ucode_img_load_gr(subdev, img, "gpccs", - NVKM_SECBOOT_FALCON_GPCCS); + return ls_ucode_img_load_gr(subdev, img, "gpccs"); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h index 430b88e..936a65f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/priv.h @@ -33,6 +33,8 @@ struct nvkm_secboot_func { int (*run_blob)(struct nvkm_secboot *, struct nvkm_gpuobj *); }; +extern const char *nvkm_secboot_falcon_name[]; + int nvkm_secboot_ctor(const struct nvkm_secboot_func *, struct nvkm_acr *, struct nvkm_device *, int, struct nvkm_secboot *); int nvkm_secboot_falcon_reset(struct nvkm_secboot *); -- cgit v1.1 From b2888c650e61d03bbfc8325662cff660b40b39ba Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Wed, 14 Dec 2016 17:02:46 +0900 Subject: drm/nouveau/secboot: safer zeroing of BL descriptors Perform the zeroing of BL descriptors in the caller function instead of trusting each generator will do it. This could avoid a few pulled hairs. Signed-off-by: Alexandre Courbot Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c | 4 ++-- drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c | 2 -- 2 files changed, 2 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c index 741f3fc..ef8ff7f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c @@ -105,7 +105,6 @@ acr_r352_generate_flcn_bl_desc(const struct nvkm_acr *acr, addr_code = (base + pdesc->app_resident_code_offset) >> 8; addr_data = (base + pdesc->app_resident_data_offset) >> 8; - memset(desc, 0, sizeof(*desc)); desc->ctx_dma = FALCON_DMAIDX_UCODE; desc->code_dma_base = lower_32_bits(addr_code); desc->non_sec_code_off = pdesc->app_resident_code_offset; @@ -354,6 +353,7 @@ acr_r352_ls_write_wpr(struct acr_r352 *acr, struct list_head *imgs, &img->lsb_header, sizeof(img->lsb_header)); /* Generate and write BL descriptor */ + memset(gdesc, 0, ls_func->bl_desc_size); ls_func->generate_bl_desc(&acr->base, _img, wpr_addr, gdesc); nvkm_gpuobj_memcpy_to(wpr_blob, img->lsb_header.bl_data_off, @@ -515,7 +515,6 @@ acr_r352_generate_hs_bl_desc(const struct hsf_load_header *hdr, void *_bl_desc, struct acr_r352_flcn_bl_desc *bl_desc = _bl_desc; u64 addr_code, addr_data; - memset(bl_desc, 0, sizeof(*bl_desc)); addr_code = offset >> 8; addr_data = (offset + hdr->data_dma_base) >> 8; @@ -713,6 +712,7 @@ acr_r352_load(struct nvkm_acr *_acr, struct nvkm_secboot *sb, code_size, hsbl_desc->start_tag, 0, false); /* Generate the BL header */ + memset(bl_desc, 0, bl_desc_size); acr->func->generate_hs_bl_desc(load_hdr, bl_desc, offset); /* diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c index 4b9a688..f0aff1d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c @@ -75,7 +75,6 @@ acr_r361_generate_flcn_bl_desc(const struct nvkm_acr *acr, addr_code = base + pdesc->app_resident_code_offset; addr_data = base + pdesc->app_resident_data_offset; - memset(desc, 0, sizeof(*desc)); desc->ctx_dma = FALCON_DMAIDX_UCODE; desc->code_dma_base = u64_to_flcn64(addr_code); desc->non_sec_code_off = pdesc->app_resident_code_offset; @@ -91,7 +90,6 @@ acr_r361_generate_hs_bl_desc(const struct hsf_load_header *hdr, void *_bl_desc, { struct acr_r361_flcn_bl_desc *bl_desc = _bl_desc; - memset(bl_desc, 0, sizeof(*bl_desc)); bl_desc->ctx_dma = FALCON_DMAIDX_VIRT; bl_desc->code_dma_base = u64_to_flcn64(offset); bl_desc->non_sec_code_off = hdr->non_sec_code_off; -- cgit v1.1 From b606234e2ffe0059055fcf38c087d5f71ca3b4b7 Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Wed, 14 Dec 2016 17:02:47 +0900 Subject: drm/nouveau/secboot: add missing fields to BL structure Since DMEM was initialized to zero, these fields went unnoticed. Add them for safety. Signed-off-by: Alexandre Courbot Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c index ef8ff7f..82e325b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c @@ -86,6 +86,8 @@ struct acr_r352_flcn_bl_desc { u32 code_entry_point; u32 data_dma_base; u32 data_size; + u32 code_dma_base1; + u32 data_dma_base1; }; /** @@ -107,10 +109,12 @@ acr_r352_generate_flcn_bl_desc(const struct nvkm_acr *acr, desc->ctx_dma = FALCON_DMAIDX_UCODE; desc->code_dma_base = lower_32_bits(addr_code); + desc->code_dma_base1 = upper_32_bits(addr_code); desc->non_sec_code_off = pdesc->app_resident_code_offset; desc->non_sec_code_size = pdesc->app_resident_code_size; desc->code_entry_point = pdesc->app_imem_entry; desc->data_dma_base = lower_32_bits(addr_data); + desc->data_dma_base1 = upper_32_bits(addr_data); desc->data_size = pdesc->app_resident_data_size; } -- cgit v1.1 From 45ef8450098fbb243ad65f590b965db1247d2d7e Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Wed, 14 Dec 2016 17:02:48 +0900 Subject: drm/nouveau/secboot: set default error value in error register Set a default error value in the mailbox 0 register so we can catch cases where the secure boot binary fails early without being able to report anything. Signed-off-by: Alexandre Courbot Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c index 2fcb2f7..813c4eb 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm200.c @@ -67,6 +67,9 @@ gm200_secboot_run_blob(struct nvkm_secboot *sb, struct nvkm_gpuobj *blob) /* Disable interrupts as we will poll for the HALT bit */ nvkm_mc_intr_mask(sb->subdev.device, falcon->owner->index, false); + /* Set default error value in mailbox register */ + nvkm_falcon_wr32(falcon, 0x040, 0xdeada5a5); + /* Start the HS bootloader */ nvkm_falcon_set_start_addr(falcon, sb->acr->start_address); nvkm_falcon_start(falcon); -- cgit v1.1 From 64a94ded890a2e4e5701ac34868180c2d895874a Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Wed, 14 Dec 2016 17:02:49 +0900 Subject: drm/nouveau/secboot: fix WPR descriptor generation Generate the WPR descriptor closer to what RM does. In particular, set the expected masks, and only set the ucode members on Tegra. Signed-off-by: Alexandre Courbot Signed-off-by: Ben Skeggs --- .../gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c index 82e325b..d4f0423 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c @@ -496,19 +496,22 @@ acr_r352_fixup_hs_desc(struct acr_r352 *acr, struct nvkm_secboot *sb, { struct nvkm_gpuobj *ls_blob = acr->ls_blob; - desc->ucode_blob_base = ls_blob->addr; - desc->ucode_blob_size = ls_blob->size; - - desc->wpr_offset = 0; - /* WPR region information if WPR is not fixed */ if (sb->wpr_size == 0) { + u32 wpr_start = ls_blob->addr; + u32 wpr_end = wpr_start + ls_blob->size; + desc->wpr_region_id = 1; - desc->regions.no_regions = 1; + desc->regions.no_regions = 2; + desc->regions.region_props[0].start_addr = wpr_start >> 8; + desc->regions.region_props[0].end_addr = wpr_end >> 8; desc->regions.region_props[0].region_id = 1; - desc->regions.region_props[0].start_addr = ls_blob->addr >> 8; - desc->regions.region_props[0].end_addr = - (ls_blob->addr + ls_blob->size) >> 8; + desc->regions.region_props[0].read_mask = 0xf; + desc->regions.region_props[0].write_mask = 0xc; + desc->regions.region_props[0].client_mask = 0x2; + } else { + desc->ucode_blob_base = ls_blob->addr; + desc->ucode_blob_size = ls_blob->size; } } -- cgit v1.1 From 425c816a806230bcaf17ceb41faeb477f285f781 Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Wed, 14 Dec 2016 17:02:50 +0900 Subject: drm/nouveau/secboot: add lazy-bootstrap flag When the PMU firmware is present, the falcons it manages need to have the lazy-bootstrap flag of their WPR header set so the ACR does not boot them. Add support for this. Signed-off-by: Alexandre Courbot Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c | 4 ++++ drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.h | 3 +++ 2 files changed, 7 insertions(+) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c index d4f0423..421cf78 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c @@ -241,6 +241,10 @@ acr_r352_ls_img_fill_headers(struct acr_r352 *acr, whdr->bootstrap_owner = acr->base.boot_falcon; whdr->status = LSF_IMAGE_STATUS_COPY; + /* Skip bootstrapping falcons started by someone else than ACR */ + if (acr->lazy_bootstrap & BIT(_img->falcon_id)) + whdr->lazy_bootstrap = 1; + /* Align, save off, and include an LSB header size */ offset = ALIGN(offset, LSF_LSB_HEADER_ALIGN); whdr->lsb_offset = offset; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.h b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.h index f335dce..ad5923b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.h @@ -223,6 +223,9 @@ struct acr_r352 { /* Firmware already loaded? */ bool firmware_ok; + /* Falcons to lazy-bootstrap */ + u32 lazy_bootstrap; + /* To keep track of the state of all managed falcons */ enum { /* In non-secure state, no firmware loaded, no privileges*/ -- cgit v1.1 From 63f542e4733a3609488c31961036995aa55d2450 Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Wed, 14 Dec 2016 17:02:52 +0900 Subject: drm/nouveau/secboot: clear halt interrupt after ACR is run The halt interrupt must be cleared after ACR is run, otherwise the LS PMU firmware will not be able to run. Signed-off-by: Alexandre Courbot Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c index 421cf78..1aa37ea1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c @@ -774,6 +774,8 @@ acr_r352_bootstrap(struct acr_r352 *acr, struct nvkm_secboot *sb) nvkm_debug(&sb->subdev, "running HS load blob\n"); ret = sb->func->run_blob(sb, acr->load_blob); + /* clear halt interrupt */ + nvkm_falcon_clear_interrupt(sb->boot_falcon, 0x10); if (ret) return ret; nvkm_debug(&sb->subdev, "HS load blob completed\n"); -- cgit v1.1 From 7eb7497e555e84d1cedb847416acbc337c874d15 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 22 Dec 2016 10:06:54 +1000 Subject: drm/nouveau/fb/ram/gk104: remove unused best_clk variable Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c index 7904fa4..fb8a123 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c @@ -989,7 +989,7 @@ gk104_pll_calc_hiclk(int target_khz, int crystal, int *N1, int *fN1, int *M1, int *P1, int *N2, int *M2, int *P2) { - int best_clk = 0, best_err = target_khz, p_ref, n_ref; + int best_err = target_khz, p_ref, n_ref; bool upper = false; *M1 = 1; @@ -1010,7 +1010,6 @@ gk104_pll_calc_hiclk(int target_khz, int crystal, /* we found a better combination */ if (cur_err < best_err) { best_err = cur_err; - best_clk = cur_clk; *N2 = cur_N; *N1 = n_ref; *P1 = p_ref; @@ -1022,7 +1021,6 @@ gk104_pll_calc_hiclk(int target_khz, int crystal, - target_khz; if (cur_err < best_err) { best_err = cur_err; - best_clk = cur_clk; *N2 = cur_N; *N1 = n_ref; *P1 = p_ref; -- cgit v1.1 From fc134253651e906f55fd5ddf29c1699099473c76 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 22 Dec 2016 10:07:27 +1000 Subject: drm/nouveau/disp/g94: remove unused sor implementation Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c | 7 ------- 1 file changed, 7 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c index 4510cb6..627b9ee1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c @@ -39,13 +39,6 @@ g94_sor_loff(struct nvkm_output_dp *outp) } /******************************************************************************* - * TMDS/LVDS - ******************************************************************************/ -static const struct nvkm_output_func -g94_sor_output_func = { -}; - -/******************************************************************************* * DisplayPort ******************************************************************************/ u32 -- cgit v1.1 From 1894054dc1b6e4395048b2c0f28832a3f4320fd3 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 22 Dec 2016 10:07:49 +1000 Subject: drm/nouveau/gr/gf100-: fix ccache error logging Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c index c0c25cf..88aa0b7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c @@ -1136,7 +1136,7 @@ gf100_gr_trap_intr(struct gf100_gr *gr) if (trap & 0x00000008) { u32 stat = nvkm_rd32(device, 0x408030); - nvkm_snprintbf(error, sizeof(error), gf100_m2mf_error, + nvkm_snprintbf(error, sizeof(error), gf100_ccache_error, stat & 0x3fffffff); nvkm_error(subdev, "CCACHE %08x [%s]\n", stat, error); nvkm_wr32(device, 0x408030, 0xc0000000); -- cgit v1.1 From 0233a9f403973c107a2937ed42f3d588e5f1811b Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 21 Dec 2016 12:46:50 +1000 Subject: drm/nouveau/gr/nv50-mcp89: add defines for gr classes Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvif/class.h | 12 ++++++++++++ drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c | 12 +++++++----- drivers/gpu/drm/nouveau/nvkm/engine/gr/gt200.c | 12 +++++++----- drivers/gpu/drm/nouveau/nvkm/engine/gr/gt215.c | 14 ++++++++------ drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp79.c | 12 +++++++----- drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp89.c | 14 ++++++++------ drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c | 12 +++++++----- 7 files changed, 56 insertions(+), 32 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/include/nvif/class.h b/drivers/gpu/drm/nouveau/include/nvif/class.h index 82235f3..9e4df72 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/class.h +++ b/drivers/gpu/drm/nouveau/include/nvif/class.h @@ -11,14 +11,18 @@ #define NVIF_CLASS_SW_GF100 /* if0005.h */ -7 /* the below match nvidia-assigned (either in hw, or sw) class numbers */ +#define NV_NULL_CLASS 0x00000030 + #define NV_DEVICE /* cl0080.h */ 0x00000080 #define NV_DMA_FROM_MEMORY /* cl0002.h */ 0x00000002 #define NV_DMA_TO_MEMORY /* cl0002.h */ 0x00000003 #define NV_DMA_IN_MEMORY /* cl0002.h */ 0x0000003d +#define NV50_TWOD 0x0000502d #define FERMI_TWOD_A 0x0000902d +#define NV50_MEMORY_TO_MEMORY_FORMAT 0x00005039 #define FERMI_MEMORY_TO_MEMORY_FORMAT_A 0x00009039 #define KEPLER_INLINE_TO_MEMORY_A 0x0000a040 @@ -99,6 +103,12 @@ #define GF110_DISP_OVERLAY_CONTROL_DMA /* cl507e.h */ 0x0000907e #define GK104_DISP_OVERLAY_CONTROL_DMA /* cl507e.h */ 0x0000917e +#define NV50_TESLA 0x00005097 +#define G82_TESLA 0x00008297 +#define GT200_TESLA 0x00008397 +#define GT214_TESLA 0x00008597 +#define GT21A_TESLA 0x00008697 + #define FERMI_A /* cl9097.h */ 0x00009097 #define FERMI_B /* cl9097.h */ 0x00009197 #define FERMI_C /* cl9097.h */ 0x00009297 @@ -140,6 +150,8 @@ #define FERMI_DECOMPRESS 0x000090b8 +#define NV50_COMPUTE 0x000050c0 +#define GT214_COMPUTE 0x000085c0 #define FERMI_COMPUTE_A 0x000090c0 #define FERMI_COMPUTE_B 0x000091c0 #define KEPLER_COMPUTE_A 0x0000a0c0 diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c index ce91330..da1ba74 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c @@ -25,6 +25,8 @@ #include +#include + static const struct nvkm_bitfield nv50_gr_status[] = { { 0x00000001, "BUSY" }, /* set when any bit is set */ { 0x00000002, "DISPATCH" }, @@ -180,11 +182,11 @@ g84_gr = { .tlb_flush = g84_gr_tlb_flush, .units = nv50_gr_units, .sclass = { - { -1, -1, 0x0030, &nv50_gr_object }, - { -1, -1, 0x502d, &nv50_gr_object }, - { -1, -1, 0x5039, &nv50_gr_object }, - { -1, -1, 0x50c0, &nv50_gr_object }, - { -1, -1, 0x8297, &nv50_gr_object }, + { -1, -1, NV_NULL_CLASS, &nv50_gr_object }, + { -1, -1, NV50_TWOD, &nv50_gr_object }, + { -1, -1, NV50_MEMORY_TO_MEMORY_FORMAT, &nv50_gr_object }, + { -1, -1, NV50_COMPUTE, &nv50_gr_object }, + { -1, -1, G82_TESLA, &nv50_gr_object }, {} } }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gt200.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gt200.c index 2e68919..c711a55 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gt200.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gt200.c @@ -23,6 +23,8 @@ */ #include "nv50.h" +#include + static const struct nvkm_gr_func gt200_gr = { .init = nv50_gr_init, @@ -31,11 +33,11 @@ gt200_gr = { .tlb_flush = g84_gr_tlb_flush, .units = nv50_gr_units, .sclass = { - { -1, -1, 0x0030, &nv50_gr_object }, - { -1, -1, 0x502d, &nv50_gr_object }, - { -1, -1, 0x5039, &nv50_gr_object }, - { -1, -1, 0x50c0, &nv50_gr_object }, - { -1, -1, 0x8397, &nv50_gr_object }, + { -1, -1, NV_NULL_CLASS, &nv50_gr_object }, + { -1, -1, NV50_TWOD, &nv50_gr_object }, + { -1, -1, NV50_MEMORY_TO_MEMORY_FORMAT, &nv50_gr_object }, + { -1, -1, NV50_COMPUTE, &nv50_gr_object }, + { -1, -1, GT200_TESLA, &nv50_gr_object }, {} } }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gt215.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gt215.c index 2bf7aac..fa103df 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gt215.c @@ -23,6 +23,8 @@ */ #include "nv50.h" +#include + static const struct nvkm_gr_func gt215_gr = { .init = nv50_gr_init, @@ -31,12 +33,12 @@ gt215_gr = { .tlb_flush = g84_gr_tlb_flush, .units = nv50_gr_units, .sclass = { - { -1, -1, 0x0030, &nv50_gr_object }, - { -1, -1, 0x502d, &nv50_gr_object }, - { -1, -1, 0x5039, &nv50_gr_object }, - { -1, -1, 0x50c0, &nv50_gr_object }, - { -1, -1, 0x8597, &nv50_gr_object }, - { -1, -1, 0x85c0, &nv50_gr_object }, + { -1, -1, NV_NULL_CLASS, &nv50_gr_object }, + { -1, -1, NV50_TWOD, &nv50_gr_object }, + { -1, -1, NV50_MEMORY_TO_MEMORY_FORMAT, &nv50_gr_object }, + { -1, -1, NV50_COMPUTE, &nv50_gr_object }, + { -1, -1, GT214_TESLA, &nv50_gr_object }, + { -1, -1, GT214_COMPUTE, &nv50_gr_object }, {} } }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp79.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp79.c index 95d5219..eb1a906 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp79.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp79.c @@ -23,6 +23,8 @@ */ #include "nv50.h" +#include + static const struct nvkm_gr_func mcp79_gr = { .init = nv50_gr_init, @@ -30,11 +32,11 @@ mcp79_gr = { .chan_new = nv50_gr_chan_new, .units = nv50_gr_units, .sclass = { - { -1, -1, 0x0030, &nv50_gr_object }, - { -1, -1, 0x502d, &nv50_gr_object }, - { -1, -1, 0x5039, &nv50_gr_object }, - { -1, -1, 0x50c0, &nv50_gr_object }, - { -1, -1, 0x8397, &nv50_gr_object }, + { -1, -1, NV_NULL_CLASS, &nv50_gr_object }, + { -1, -1, NV50_TWOD, &nv50_gr_object }, + { -1, -1, NV50_MEMORY_TO_MEMORY_FORMAT, &nv50_gr_object }, + { -1, -1, NV50_COMPUTE, &nv50_gr_object }, + { -1, -1, GT200_TESLA, &nv50_gr_object }, {} } }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp89.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp89.c index 027b58e..c91eb56 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp89.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp89.c @@ -23,6 +23,8 @@ */ #include "nv50.h" +#include + static const struct nvkm_gr_func mcp89_gr = { .init = nv50_gr_init, @@ -31,12 +33,12 @@ mcp89_gr = { .tlb_flush = g84_gr_tlb_flush, .units = nv50_gr_units, .sclass = { - { -1, -1, 0x0030, &nv50_gr_object }, - { -1, -1, 0x502d, &nv50_gr_object }, - { -1, -1, 0x5039, &nv50_gr_object }, - { -1, -1, 0x50c0, &nv50_gr_object }, - { -1, -1, 0x85c0, &nv50_gr_object }, - { -1, -1, 0x8697, &nv50_gr_object }, + { -1, -1, NV_NULL_CLASS, &nv50_gr_object }, + { -1, -1, NV50_TWOD, &nv50_gr_object }, + { -1, -1, NV50_MEMORY_TO_MEMORY_FORMAT, &nv50_gr_object }, + { -1, -1, NV50_COMPUTE, &nv50_gr_object }, + { -1, -1, GT214_COMPUTE, &nv50_gr_object }, + { -1, -1, GT21A_TESLA, &nv50_gr_object }, {} } }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c index fca67de..df16ffd 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c @@ -27,6 +27,8 @@ #include #include +#include + u64 nv50_gr_units(struct nvkm_gr *gr) { @@ -778,11 +780,11 @@ nv50_gr = { .chan_new = nv50_gr_chan_new, .units = nv50_gr_units, .sclass = { - { -1, -1, 0x0030, &nv50_gr_object }, - { -1, -1, 0x502d, &nv50_gr_object }, - { -1, -1, 0x5039, &nv50_gr_object }, - { -1, -1, 0x5097, &nv50_gr_object }, - { -1, -1, 0x50c0, &nv50_gr_object }, + { -1, -1, NV_NULL_CLASS, &nv50_gr_object }, + { -1, -1, NV50_TWOD, &nv50_gr_object }, + { -1, -1, NV50_MEMORY_TO_MEMORY_FORMAT, &nv50_gr_object }, + { -1, -1, NV50_TESLA, &nv50_gr_object }, + { -1, -1, NV50_COMPUTE, &nv50_gr_object }, {} } }; -- cgit v1.1 From af7db03e1bd562105dc6460674a05f5463e333e0 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 3 Mar 2016 12:56:33 +1000 Subject: replace BUG_ON(1) with BUG() Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_connector.c | 2 +- drivers/gpu/drm/nouveau/nouveau_usif.c | 2 +- drivers/gpu/drm/nouveau/nv50_display.c | 4 ++-- drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c index 966d20a..dc7dd2e 100644 --- a/drivers/gpu/drm/nouveau/nouveau_connector.c +++ b/drivers/gpu/drm/nouveau/nouveau_connector.c @@ -1041,7 +1041,7 @@ nouveau_connector_mode_valid(struct drm_connector *connector, clock = clock * (connector->display_info.bpc * 3) / 10; break; default: - BUG_ON(1); + BUG(); return MODE_BAD; } diff --git a/drivers/gpu/drm/nouveau/nouveau_usif.c b/drivers/gpu/drm/nouveau/nouveau_usif.c index 08f9c6f..58508b5 100644 --- a/drivers/gpu/drm/nouveau/nouveau_usif.c +++ b/drivers/gpu/drm/nouveau/nouveau_usif.c @@ -103,7 +103,7 @@ usif_notify(const void *header, u32 length, const void *data, u32 size) } break; default: - BUG_ON(1); + BUG(); break; } diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c index 452da48..db35bee 100644 --- a/drivers/gpu/drm/nouveau/nv50_display.c +++ b/drivers/gpu/drm/nouveau/nv50_display.c @@ -3623,7 +3623,7 @@ nv50_sor_enable(struct drm_encoder *encoder) nv50_audio_enable(encoder, mode); break; default: - BUG_ON(1); + BUG(); break; } @@ -3796,7 +3796,7 @@ nv50_pior_enable(struct drm_encoder *encoder) proto = 0x0; break; default: - BUG_ON(1); + BUG(); break; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c index 5841f29..da1770e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c @@ -112,7 +112,7 @@ read_pll_src(struct nv50_clk *clk, u32 base) M = (coef & 0x000000ff) >> 0; break; default: - BUG_ON(1); + BUG(); } if (M) -- cgit v1.1 From 05073caeedd1ea6bfc5b1ebd051f2a6694e4b26b Mon Sep 17 00:00:00 2001 From: Geliang Tang Date: Tue, 20 Dec 2016 22:02:11 +0800 Subject: drm/nouveau/dma: use rb_entry() To make the code clearer, use rb_entry() instead of container_of() to deal with rbtree. Signed-off-by: Geliang Tang Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c index f11ebdd..4655d17 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c @@ -34,7 +34,7 @@ nvkm_dma_search(struct nvkm_dma *dma, struct nvkm_client *client, u64 object) struct rb_node *node = client->dmaroot.rb_node; while (node) { struct nvkm_dmaobj *dmaobj = - container_of(node, typeof(*dmaobj), rb); + rb_entry(node, typeof(*dmaobj), rb); if (object < dmaobj->handle) node = node->rb_left; else @@ -67,7 +67,7 @@ nvkm_dma_oclass_new(struct nvkm_device *device, dmaobj->handle = oclass->object; while (*ptr) { - struct nvkm_dmaobj *obj = container_of(*ptr, typeof(*obj), rb); + struct nvkm_dmaobj *obj = rb_entry(*ptr, typeof(*obj), rb); parent = *ptr; if (dmaobj->handle < obj->handle) ptr = &parent->rb_left; -- cgit v1.1 From 110cccff955313c66dccd2817f62368f106d9bf2 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 22 Dec 2016 15:22:25 +1000 Subject: drm/nouveau/core/object: support lookup of specific object types It turns out we have a nice and convenient way of looking up a specific object type already, by using the func pointer as a key. This will be used to remove the separate object trees for each type we need to be able to search for. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvkm/core/object.h | 5 ++ drivers/gpu/drm/nouveau/nvkm/core/object.c | 61 +++++++++++++++++++++- 2 files changed, 65 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/object.h b/drivers/gpu/drm/nouveau/include/nvkm/core/object.h index dcd048b..96dda35 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/object.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/object.h @@ -62,6 +62,11 @@ int nvkm_object_wr32(struct nvkm_object *, u64 addr, u32 data); int nvkm_object_bind(struct nvkm_object *, struct nvkm_gpuobj *, int align, struct nvkm_gpuobj **); +bool nvkm_object_insert(struct nvkm_object *); +void nvkm_object_remove(struct nvkm_object *); +struct nvkm_object *nvkm_object_search(struct nvkm_client *, u64 object, + const struct nvkm_object_func *); + struct nvkm_sclass { int minver; int maxver; diff --git a/drivers/gpu/drm/nouveau/nvkm/core/object.c b/drivers/gpu/drm/nouveau/nvkm/core/object.c index 67aa722..218f932 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/object.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/object.c @@ -25,6 +25,65 @@ #include #include +struct nvkm_object * +nvkm_object_search(struct nvkm_client *client, u64 handle, + const struct nvkm_object_func *func) +{ + struct nvkm_object *object; + + if (handle) { + struct rb_node *node = client->objroot.rb_node; + while (node) { + object = rb_entry(node, typeof(*object), node); + if (handle < object->object) + node = node->rb_left; + else + if (handle > object->object) + node = node->rb_right; + else + goto done; + } + return ERR_PTR(-ENOENT); + } else { + object = &client->object; + } + +done: + if (unlikely(func && object->func != func)) + return ERR_PTR(-EINVAL); + return object; +} + +void +nvkm_object_remove(struct nvkm_object *object) +{ + if (!RB_EMPTY_NODE(&object->node)) + rb_erase(&object->node, &object->client->objroot); +} + +bool +nvkm_object_insert(struct nvkm_object *object) +{ + struct rb_node **ptr = &object->client->objroot.rb_node; + struct rb_node *parent = NULL; + + while (*ptr) { + struct nvkm_object *this = rb_entry(*ptr, typeof(*this), node); + parent = *ptr; + if (object->object < this->object) + ptr = &parent->rb_left; + else + if (object->object > this->object) + ptr = &parent->rb_right; + else + return false; + } + + rb_link_node(&object->node, parent, ptr); + rb_insert_color(&object->node, &object->client->objroot); + return true; +} + int nvkm_object_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) { @@ -214,7 +273,7 @@ nvkm_object_del(struct nvkm_object **pobject) struct nvkm_object *object = *pobject; if (object && !WARN_ON(!object->func)) { *pobject = nvkm_object_dtor(object); - nvkm_client_remove(object->client, object); + nvkm_object_remove(object); list_del(&object->head); kfree(*pobject); *pobject = NULL; -- cgit v1.1 From daad3dfb05be8b0682c1bb0db6b59e50a4bb95f6 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 22 Dec 2016 15:23:04 +1000 Subject: drm/nouveau/core/client: lookup client objects with nvkm_object_search() Custom code is no longer needed here. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvkm/core/client.h | 4 -- drivers/gpu/drm/nouveau/nvkm/core/client.c | 49 ---------------------- drivers/gpu/drm/nouveau/nvkm/core/ioctl.c | 11 ++--- 3 files changed, 4 insertions(+), 60 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/client.h b/drivers/gpu/drm/nouveau/include/nvkm/core/client.h index 9908334..361ad8c 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/client.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/client.h @@ -19,10 +19,6 @@ struct nvkm_client { struct nvkm_vm *vm; }; -bool nvkm_client_insert(struct nvkm_client *, struct nvkm_object *); -void nvkm_client_remove(struct nvkm_client *, struct nvkm_object *); -struct nvkm_object *nvkm_client_search(struct nvkm_client *, u64 object); - int nvkm_client_new(const char *name, u64 device, const char *cfg, const char *dbg, struct nvkm_client **); void nvkm_client_del(struct nvkm_client **); diff --git a/drivers/gpu/drm/nouveau/nvkm/core/client.c b/drivers/gpu/drm/nouveau/nvkm/core/client.c index e194391..0c2fdf1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/client.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/client.c @@ -206,55 +206,6 @@ nvkm_client_object_func = { .sclass = nvkm_client_child_get, }; -void -nvkm_client_remove(struct nvkm_client *client, struct nvkm_object *object) -{ - if (!RB_EMPTY_NODE(&object->node)) - rb_erase(&object->node, &client->objroot); -} - -bool -nvkm_client_insert(struct nvkm_client *client, struct nvkm_object *object) -{ - struct rb_node **ptr = &client->objroot.rb_node; - struct rb_node *parent = NULL; - - while (*ptr) { - struct nvkm_object *this = - container_of(*ptr, typeof(*this), node); - parent = *ptr; - if (object->object < this->object) - ptr = &parent->rb_left; - else - if (object->object > this->object) - ptr = &parent->rb_right; - else - return false; - } - - rb_link_node(&object->node, parent, ptr); - rb_insert_color(&object->node, &client->objroot); - return true; -} - -struct nvkm_object * -nvkm_client_search(struct nvkm_client *client, u64 handle) -{ - struct rb_node *node = client->objroot.rb_node; - while (node) { - struct nvkm_object *object = - container_of(node, typeof(*object), node); - if (handle < object->object) - node = node->rb_left; - else - if (handle > object->object) - node = node->rb_right; - else - return object; - } - return NULL; -} - int nvkm_client_fini(struct nvkm_client *client, bool suspend) { diff --git a/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c b/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c index b0db518..6e695b7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c @@ -128,7 +128,7 @@ nvkm_ioctl_new(struct nvkm_object *parent, void *data, u32 size) object->route = args->v0.route; object->token = args->v0.token; object->object = args->v0.object; - if (nvkm_client_insert(client, object)) { + if (nvkm_object_insert(object)) { client->data = object; return 0; } @@ -389,13 +389,10 @@ nvkm_ioctl_path(struct nvkm_client *client, u64 handle, u32 type, struct nvkm_object *object; int ret; - if (handle) - object = nvkm_client_search(client, handle); - else - object = &client->object; - if (unlikely(!object)) { + object = nvkm_object_search(client, handle, NULL); + if (IS_ERR(object)) { nvif_ioctl(&client->object, "object not found\n"); - return -ENOENT; + return PTR_ERR(object); } if (owner != NVIF_IOCTL_V0_OWNER_ANY && owner != object->route) { -- cgit v1.1 From 83e85d91b2bc38d4067baf05a7fe9e47436e1d8c Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 17 May 2016 19:40:29 +1000 Subject: drm/nouveau/dma: lookup objects with nvkm_object_search() Custom code is no longer needed here. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvkm/core/client.h | 1 - drivers/gpu/drm/nouveau/include/nvkm/engine/dma.h | 6 +--- drivers/gpu/drm/nouveau/nvkm/core/client.c | 1 - .../gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.c | 7 ++-- drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c | 42 +--------------------- drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c | 19 +++++++--- drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c | 6 ++-- 7 files changed, 22 insertions(+), 60 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/client.h b/drivers/gpu/drm/nouveau/include/nvkm/core/client.h index 361ad8c..f5861ab 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/client.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/client.h @@ -10,7 +10,6 @@ struct nvkm_client { struct nvkm_client_notify *notify[16]; struct rb_root objroot; - struct rb_root dmaroot; bool super; void *data; diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/dma.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/dma.h index 114bfb7..d2a6532 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/dma.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/dma.h @@ -12,9 +12,6 @@ struct nvkm_dmaobj { u32 access; u64 start; u64 limit; - - struct rb_node rb; - u64 handle; /*XXX HANDLE MERGE */ }; struct nvkm_dma { @@ -22,8 +19,7 @@ struct nvkm_dma { struct nvkm_engine engine; }; -struct nvkm_dmaobj * -nvkm_dma_search(struct nvkm_dma *, struct nvkm_client *, u64 object); +struct nvkm_dmaobj *nvkm_dmaobj_search(struct nvkm_client *, u64 object); int nv04_dma_new(struct nvkm_device *, int, struct nvkm_dma **); int nv50_dma_new(struct nvkm_device *, int, struct nvkm_dma **); diff --git a/drivers/gpu/drm/nouveau/nvkm/core/client.c b/drivers/gpu/drm/nouveau/nvkm/core/client.c index 0c2fdf1..8087b25 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/client.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/client.c @@ -255,6 +255,5 @@ nvkm_client_new(const char *name, u64 device, const char *cfg, client->device = device; client->debug = nvkm_dbgopt(dbg, "CLIENT"); client->objroot = RB_ROOT; - client->dmaroot = RB_ROOT; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.c index 0a1381a..070ec5e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.c @@ -137,7 +137,6 @@ nv50_disp_dmac_new_(const struct nv50_disp_dmac_func *func, const struct nvkm_oclass *oclass, struct nvkm_object **pobject) { - struct nvkm_device *device = root->disp->base.engine.subdev.device; struct nvkm_client *client = oclass->client; struct nvkm_dmaobj *dmaobj; struct nv50_disp_dmac *chan; @@ -153,9 +152,9 @@ nv50_disp_dmac_new_(const struct nv50_disp_dmac_func *func, if (ret) return ret; - dmaobj = nvkm_dma_search(device->dma, client, push); - if (!dmaobj) - return -ENOENT; + dmaobj = nvkm_dmaobj_search(client, push); + if (IS_ERR(dmaobj)) + return PTR_ERR(dmaobj); if (dmaobj->limit - dmaobj->start != 0xfff) return -EINVAL; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c index 4655d17..11b7b8f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c @@ -28,24 +28,6 @@ #include -struct nvkm_dmaobj * -nvkm_dma_search(struct nvkm_dma *dma, struct nvkm_client *client, u64 object) -{ - struct rb_node *node = client->dmaroot.rb_node; - while (node) { - struct nvkm_dmaobj *dmaobj = - rb_entry(node, typeof(*dmaobj), rb); - if (object < dmaobj->handle) - node = node->rb_left; - else - if (object > dmaobj->handle) - node = node->rb_right; - else - return dmaobj; - } - return NULL; -} - static int nvkm_dma_oclass_new(struct nvkm_device *device, const struct nvkm_oclass *oclass, void *data, u32 size, @@ -53,34 +35,12 @@ nvkm_dma_oclass_new(struct nvkm_device *device, { struct nvkm_dma *dma = nvkm_dma(oclass->engine); struct nvkm_dmaobj *dmaobj = NULL; - struct nvkm_client *client = oclass->client; - struct rb_node **ptr = &client->dmaroot.rb_node; - struct rb_node *parent = NULL; int ret; ret = dma->func->class_new(dma, oclass, data, size, &dmaobj); if (dmaobj) *pobject = &dmaobj->object; - if (ret) - return ret; - - dmaobj->handle = oclass->object; - - while (*ptr) { - struct nvkm_dmaobj *obj = rb_entry(*ptr, typeof(*obj), rb); - parent = *ptr; - if (dmaobj->handle < obj->handle) - ptr = &parent->rb_left; - else - if (dmaobj->handle > obj->handle) - ptr = &parent->rb_right; - else - return -EEXIST; - } - - rb_link_node(&dmaobj->rb, parent, ptr); - rb_insert_color(&dmaobj->rb, &client->dmaroot); - return 0; + return ret; } static const struct nvkm_device_oclass diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c b/drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c index 13c661b1..d20cc06 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c @@ -31,6 +31,19 @@ #include #include +static const struct nvkm_object_func nvkm_dmaobj_func; +struct nvkm_dmaobj * +nvkm_dmaobj_search(struct nvkm_client *client, u64 handle) +{ + struct nvkm_object *object; + + object = nvkm_object_search(client, handle, &nvkm_dmaobj_func); + if (IS_ERR(object)) + return (void *)object; + + return nvkm_dmaobj(object); +} + static int nvkm_dmaobj_bind(struct nvkm_object *base, struct nvkm_gpuobj *gpuobj, int align, struct nvkm_gpuobj **pgpuobj) @@ -42,10 +55,7 @@ nvkm_dmaobj_bind(struct nvkm_object *base, struct nvkm_gpuobj *gpuobj, static void * nvkm_dmaobj_dtor(struct nvkm_object *base) { - struct nvkm_dmaobj *dmaobj = nvkm_dmaobj(base); - if (!RB_EMPTY_NODE(&dmaobj->rb)) - rb_erase(&dmaobj->rb, &dmaobj->object.client->dmaroot); - return dmaobj; + return nvkm_dmaobj(base); } static const struct nvkm_object_func @@ -74,7 +84,6 @@ nvkm_dmaobj_ctor(const struct nvkm_dmaobj_func *func, struct nvkm_dma *dma, nvkm_object_ctor(&nvkm_dmaobj_func, oclass, &dmaobj->object); dmaobj->func = func; dmaobj->dma = dma; - RB_CLEAR_NODE(&dmaobj->rb); nvif_ioctl(parent, "create dma size %d\n", *psize); if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c index dc6d467..3b87e09 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c @@ -371,9 +371,9 @@ nvkm_fifo_chan_ctor(const struct nvkm_fifo_chan_func *func, /* allocate push buffer ctxdma instance */ if (push) { - dmaobj = nvkm_dma_search(device->dma, oclass->client, push); - if (!dmaobj) - return -ENOENT; + dmaobj = nvkm_dmaobj_search(client, push); + if (IS_ERR(dmaobj)) + return PTR_ERR(dmaobj); ret = nvkm_object_bind(&dmaobj->object, chan->inst, -16, &chan->push); -- cgit v1.1 From a664869ac4c77875ca84a38f614bc1c7b3c79812 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 25 May 2016 17:33:36 +1000 Subject: drm/nouveau/core/object: pass client directly to ioctl handlers nvkm_object::client refers to the client that created the object, which, is currently always the same as the ioctl caller. Upcoming patches introduce the concept of subclients, where a parent is able to access the object trees of its children, making the above no longer true. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/core/ioctl.c | 47 ++++++++++++++++++------------- 1 file changed, 28 insertions(+), 19 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c b/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c index 6e695b7..b43ce4e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c @@ -29,7 +29,8 @@ #include static int -nvkm_ioctl_nop(struct nvkm_object *object, void *data, u32 size) +nvkm_ioctl_nop(struct nvkm_client *client, + struct nvkm_object *object, void *data, u32 size) { union { struct nvif_ioctl_nop_v0 v0; @@ -46,7 +47,8 @@ nvkm_ioctl_nop(struct nvkm_object *object, void *data, u32 size) } static int -nvkm_ioctl_sclass(struct nvkm_object *object, void *data, u32 size) +nvkm_ioctl_sclass(struct nvkm_client *client, + struct nvkm_object *object, void *data, u32 size) { union { struct nvif_ioctl_sclass_v0 v0; @@ -78,12 +80,12 @@ nvkm_ioctl_sclass(struct nvkm_object *object, void *data, u32 size) } static int -nvkm_ioctl_new(struct nvkm_object *parent, void *data, u32 size) +nvkm_ioctl_new(struct nvkm_client *client, + struct nvkm_object *parent, void *data, u32 size) { union { struct nvif_ioctl_new_v0 v0; } *args = data; - struct nvkm_client *client = parent->client; struct nvkm_object *object = NULL; struct nvkm_oclass oclass; int ret = -ENOSYS, i = 0; @@ -142,7 +144,8 @@ nvkm_ioctl_new(struct nvkm_object *parent, void *data, u32 size) } static int -nvkm_ioctl_del(struct nvkm_object *object, void *data, u32 size) +nvkm_ioctl_del(struct nvkm_client *client, + struct nvkm_object *object, void *data, u32 size) { union { struct nvif_ioctl_del none; @@ -160,7 +163,8 @@ nvkm_ioctl_del(struct nvkm_object *object, void *data, u32 size) } static int -nvkm_ioctl_mthd(struct nvkm_object *object, void *data, u32 size) +nvkm_ioctl_mthd(struct nvkm_client *client, + struct nvkm_object *object, void *data, u32 size) { union { struct nvif_ioctl_mthd_v0 v0; @@ -179,7 +183,8 @@ nvkm_ioctl_mthd(struct nvkm_object *object, void *data, u32 size) static int -nvkm_ioctl_rd(struct nvkm_object *object, void *data, u32 size) +nvkm_ioctl_rd(struct nvkm_client *client, + struct nvkm_object *object, void *data, u32 size) { union { struct nvif_ioctl_rd_v0 v0; @@ -218,7 +223,8 @@ nvkm_ioctl_rd(struct nvkm_object *object, void *data, u32 size) } static int -nvkm_ioctl_wr(struct nvkm_object *object, void *data, u32 size) +nvkm_ioctl_wr(struct nvkm_client *client, + struct nvkm_object *object, void *data, u32 size) { union { struct nvif_ioctl_wr_v0 v0; @@ -246,7 +252,8 @@ nvkm_ioctl_wr(struct nvkm_object *object, void *data, u32 size) } static int -nvkm_ioctl_map(struct nvkm_object *object, void *data, u32 size) +nvkm_ioctl_map(struct nvkm_client *client, + struct nvkm_object *object, void *data, u32 size) { union { struct nvif_ioctl_map_v0 v0; @@ -264,7 +271,8 @@ nvkm_ioctl_map(struct nvkm_object *object, void *data, u32 size) } static int -nvkm_ioctl_unmap(struct nvkm_object *object, void *data, u32 size) +nvkm_ioctl_unmap(struct nvkm_client *client, + struct nvkm_object *object, void *data, u32 size) { union { struct nvif_ioctl_unmap none; @@ -280,7 +288,8 @@ nvkm_ioctl_unmap(struct nvkm_object *object, void *data, u32 size) } static int -nvkm_ioctl_ntfy_new(struct nvkm_object *object, void *data, u32 size) +nvkm_ioctl_ntfy_new(struct nvkm_client *client, + struct nvkm_object *object, void *data, u32 size) { union { struct nvif_ioctl_ntfy_new_v0 v0; @@ -306,9 +315,9 @@ nvkm_ioctl_ntfy_new(struct nvkm_object *object, void *data, u32 size) } static int -nvkm_ioctl_ntfy_del(struct nvkm_object *object, void *data, u32 size) +nvkm_ioctl_ntfy_del(struct nvkm_client *client, + struct nvkm_object *object, void *data, u32 size) { - struct nvkm_client *client = object->client; union { struct nvif_ioctl_ntfy_del_v0 v0; } *args = data; @@ -325,9 +334,9 @@ nvkm_ioctl_ntfy_del(struct nvkm_object *object, void *data, u32 size) } static int -nvkm_ioctl_ntfy_get(struct nvkm_object *object, void *data, u32 size) +nvkm_ioctl_ntfy_get(struct nvkm_client *client, + struct nvkm_object *object, void *data, u32 size) { - struct nvkm_client *client = object->client; union { struct nvif_ioctl_ntfy_get_v0 v0; } *args = data; @@ -344,9 +353,9 @@ nvkm_ioctl_ntfy_get(struct nvkm_object *object, void *data, u32 size) } static int -nvkm_ioctl_ntfy_put(struct nvkm_object *object, void *data, u32 size) +nvkm_ioctl_ntfy_put(struct nvkm_client *client, + struct nvkm_object *object, void *data, u32 size) { - struct nvkm_client *client = object->client; union { struct nvif_ioctl_ntfy_put_v0 v0; } *args = data; @@ -364,7 +373,7 @@ nvkm_ioctl_ntfy_put(struct nvkm_object *object, void *data, u32 size) static struct { int version; - int (*func)(struct nvkm_object *, void *, u32); + int (*func)(struct nvkm_client *, struct nvkm_object *, void *, u32); } nvkm_ioctl_v0[] = { { 0x00, nvkm_ioctl_nop }, @@ -404,7 +413,7 @@ nvkm_ioctl_path(struct nvkm_client *client, u64 handle, u32 type, if (ret = -EINVAL, type < ARRAY_SIZE(nvkm_ioctl_v0)) { if (nvkm_ioctl_v0[type].version == 0) - ret = nvkm_ioctl_v0[type].func(object, data, size); + ret = nvkm_ioctl_v0[type].func(client, object, data, size); } return ret; -- cgit v1.1 From 843faa030c3677080e4a108889dccb21798b2a32 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 25 May 2016 17:47:18 +1000 Subject: drm/nouveau/core/object: pass more args in oclass The fields were already in struct nvkm_oclass for some reason (probably as an accidental left-over). Preparation for supporting subclients. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/core/ioctl.c | 7 +++---- drivers/gpu/drm/nouveau/nvkm/core/object.c | 3 +++ 2 files changed, 6 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c b/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c index b43ce4e..25c800b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c @@ -106,9 +106,11 @@ nvkm_ioctl_new(struct nvkm_client *client, do { memset(&oclass, 0x00, sizeof(oclass)); - oclass.client = client; oclass.handle = args->v0.handle; + oclass.route = args->v0.route; + oclass.token = args->v0.token; oclass.object = args->v0.object; + oclass.client = client; oclass.parent = parent; ret = parent->func->sclass(parent, i++, &oclass); if (ret) @@ -127,9 +129,6 @@ nvkm_ioctl_new(struct nvkm_client *client, ret = nvkm_object_init(object); if (ret == 0) { list_add(&object->head, &parent->tree); - object->route = args->v0.route; - object->token = args->v0.token; - object->object = args->v0.object; if (nvkm_object_insert(object)) { client->data = object; return 0; diff --git a/drivers/gpu/drm/nouveau/nvkm/core/object.c b/drivers/gpu/drm/nouveau/nvkm/core/object.c index 218f932..89d2e9d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/object.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/object.c @@ -289,6 +289,9 @@ nvkm_object_ctor(const struct nvkm_object_func *func, object->engine = nvkm_engine_ref(oclass->engine); object->oclass = oclass->base.oclass; object->handle = oclass->handle; + object->route = oclass->route; + object->token = oclass->token; + object->object = oclass->object; INIT_LIST_HEAD(&object->head); INIT_LIST_HEAD(&object->tree); RB_CLEAR_NODE(&object->node); -- cgit v1.1 From 03295eabdb95153be4777ff04cc4f1dec0d62bc4 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 26 May 2016 08:43:00 +1000 Subject: drm/nouveau/core/client: modify prefix on nvif structures, for consistency Preparation for supporting subclients. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvif/class.h | 18 +++++++++++------- drivers/gpu/drm/nouveau/include/nvif/if0000.h | 4 ++-- drivers/gpu/drm/nouveau/include/nvkm/core/client.h | 1 + drivers/gpu/drm/nouveau/nvkm/core/client.c | 20 +++++++++++++------- 4 files changed, 27 insertions(+), 16 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/include/nvif/class.h b/drivers/gpu/drm/nouveau/include/nvif/class.h index 9e4df72..3a2c013 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/class.h +++ b/drivers/gpu/drm/nouveau/include/nvif/class.h @@ -2,13 +2,17 @@ #define __NVIF_CLASS_H__ /* these class numbers are made up by us, and not nvidia-assigned */ -#define NVIF_CLASS_CONTROL /* if0001.h */ -1 -#define NVIF_CLASS_PERFMON /* if0002.h */ -2 -#define NVIF_CLASS_PERFDOM /* if0003.h */ -3 -#define NVIF_CLASS_SW_NV04 /* if0004.h */ -4 -#define NVIF_CLASS_SW_NV10 /* if0005.h */ -5 -#define NVIF_CLASS_SW_NV50 /* if0005.h */ -6 -#define NVIF_CLASS_SW_GF100 /* if0005.h */ -7 +#define NVIF_CLASS_CLIENT /* if0000.h */ -0x00000000 + +#define NVIF_CLASS_CONTROL /* if0001.h */ -0x00000001 + +#define NVIF_CLASS_PERFMON /* if0002.h */ -0x00000002 +#define NVIF_CLASS_PERFDOM /* if0003.h */ -0x00000003 + +#define NVIF_CLASS_SW_NV04 /* if0004.h */ -0x00000004 +#define NVIF_CLASS_SW_NV10 /* if0005.h */ -0x00000005 +#define NVIF_CLASS_SW_NV50 /* if0005.h */ -0x00000006 +#define NVIF_CLASS_SW_GF100 /* if0005.h */ -0x00000007 /* the below match nvidia-assigned (either in hw, or sw) class numbers */ #define NV_NULL_CLASS 0x00000030 diff --git a/drivers/gpu/drm/nouveau/include/nvif/if0000.h b/drivers/gpu/drm/nouveau/include/nvif/if0000.h index 85c44e8..18bbd82 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/if0000.h +++ b/drivers/gpu/drm/nouveau/include/nvif/if0000.h @@ -1,9 +1,9 @@ #ifndef __NVIF_IF0000_H__ #define __NVIF_IF0000_H__ -#define NV_CLIENT_DEVLIST 0x00 +#define NVIF_CLIENT_V0_DEVLIST 0x00 -struct nv_client_devlist_v0 { +struct nvif_client_devlist_v0 { __u8 version; __u8 count; __u8 pad02[6]; diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/client.h b/drivers/gpu/drm/nouveau/include/nvkm/core/client.h index f5861ab..a87d458 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/client.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/client.h @@ -1,5 +1,6 @@ #ifndef __NVKM_CLIENT_H__ #define __NVKM_CLIENT_H__ +#define nvkm_client(p) container_of((p), struct nvkm_client, object) #include struct nvkm_client { diff --git a/drivers/gpu/drm/nouveau/nvkm/core/client.c b/drivers/gpu/drm/nouveau/nvkm/core/client.c index 8087b25..aab4a88 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/client.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/client.c @@ -31,6 +31,11 @@ #include #include +static const struct nvkm_sclass +nvkm_uclient_sclass = { + .oclass = NVIF_CLASS_CLIENT, +}; + struct nvkm_client_notify { struct nvkm_client *client; struct nvkm_notify n; @@ -139,16 +144,16 @@ nvkm_client_notify_new(struct nvkm_object *object, } static int -nvkm_client_mthd_devlist(struct nvkm_object *object, void *data, u32 size) +nvkm_client_mthd_devlist(struct nvkm_client *client, void *data, u32 size) { union { - struct nv_client_devlist_v0 v0; + struct nvif_client_devlist_v0 v0; } *args = data; int ret = -ENOSYS; - nvif_ioctl(object, "client devlist size %d\n", size); + nvif_ioctl(&client->object, "client devlist size %d\n", size); if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) { - nvif_ioctl(object, "client devlist vers %d count %d\n", + nvif_ioctl(&client->object, "client devlist vers %d count %d\n", args->v0.version, args->v0.count); if (size == sizeof(args->v0.device[0]) * args->v0.count) { ret = nvkm_device_list(args->v0.device, args->v0.count); @@ -167,9 +172,10 @@ nvkm_client_mthd_devlist(struct nvkm_object *object, void *data, u32 size) static int nvkm_client_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) { + struct nvkm_client *client = nvkm_client(object); switch (mthd) { - case NV_CLIENT_DEVLIST: - return nvkm_client_mthd_devlist(object, data, size); + case NVIF_CLIENT_V0_DEVLIST: + return nvkm_client_mthd_devlist(client, data, size); default: break; } @@ -243,7 +249,7 @@ int nvkm_client_new(const char *name, u64 device, const char *cfg, const char *dbg, struct nvkm_client **pclient) { - struct nvkm_oclass oclass = {}; + struct nvkm_oclass oclass = { .base = nvkm_uclient_sclass }; struct nvkm_client *client; if (!(client = *pclient = kzalloc(sizeof(*client), GFP_KERNEL))) -- cgit v1.1 From 2c3af924fbee23544a6adc81a2bbe398132b472f Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 23 May 2016 08:42:54 +1000 Subject: drm/nouveau/core/client: use standard object dtor/init/fini paths Preparation for supporting subclients, and also good for consistency. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvkm/core/client.h | 3 -- drivers/gpu/drm/nouveau/nouveau_nvif.c | 10 +++-- drivers/gpu/drm/nouveau/nvkm/core/client.c | 47 +++++++++------------- 3 files changed, 26 insertions(+), 34 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/client.h b/drivers/gpu/drm/nouveau/include/nvkm/core/client.h index a87d458..28f1078 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/client.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/client.h @@ -21,9 +21,6 @@ struct nvkm_client { int nvkm_client_new(const char *name, u64 device, const char *cfg, const char *dbg, struct nvkm_client **); -void nvkm_client_del(struct nvkm_client **); -int nvkm_client_init(struct nvkm_client *); -int nvkm_client_fini(struct nvkm_client *, bool suspend); int nvkm_client_notify_new(struct nvkm_object *, struct nvkm_event *, void *data, u32 size); diff --git a/drivers/gpu/drm/nouveau/nouveau_nvif.c b/drivers/gpu/drm/nouveau/nouveau_nvif.c index 15f0925..5219da4 100644 --- a/drivers/gpu/drm/nouveau/nouveau_nvif.c +++ b/drivers/gpu/drm/nouveau/nouveau_nvif.c @@ -60,20 +60,24 @@ nvkm_client_ioctl(void *priv, bool super, void *data, u32 size, void **hack) static int nvkm_client_resume(void *priv) { - return nvkm_client_init(priv); + struct nvkm_client *client = priv; + return nvkm_object_init(&client->object); } static int nvkm_client_suspend(void *priv) { - return nvkm_client_fini(priv, true); + struct nvkm_client *client = priv; + return nvkm_object_fini(&client->object, true); } static void nvkm_client_driver_fini(void *priv) { struct nvkm_client *client = priv; - nvkm_client_del(&client); + struct nvkm_object *object = &client->object; + nvkm_object_fini(object, false); + nvkm_object_del(&object); } static int diff --git a/drivers/gpu/drm/nouveau/nvkm/core/client.c b/drivers/gpu/drm/nouveau/nvkm/core/client.c index aab4a88..3cde975 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/client.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/client.c @@ -206,45 +206,36 @@ nvkm_client_child_get(struct nvkm_object *object, int index, return 0; } -static const struct nvkm_object_func -nvkm_client_object_func = { - .mthd = nvkm_client_mthd, - .sclass = nvkm_client_child_get, -}; - -int -nvkm_client_fini(struct nvkm_client *client, bool suspend) +static int +nvkm_client_fini(struct nvkm_object *object, bool suspend) { - struct nvkm_object *object = &client->object; + struct nvkm_client *client = nvkm_client(object); const char *name[2] = { "fini", "suspend" }; int i; nvif_debug(object, "%s notify\n", name[suspend]); for (i = 0; i < ARRAY_SIZE(client->notify); i++) nvkm_client_notify_put(client, i); - return nvkm_object_fini(&client->object, suspend); -} - -int -nvkm_client_init(struct nvkm_client *client) -{ - return nvkm_object_init(&client->object); + return 0; } -void -nvkm_client_del(struct nvkm_client **pclient) +static void * +nvkm_client_dtor(struct nvkm_object *object) { - struct nvkm_client *client = *pclient; + struct nvkm_client *client = nvkm_client(object); int i; - if (client) { - nvkm_client_fini(client, false); - for (i = 0; i < ARRAY_SIZE(client->notify); i++) - nvkm_client_notify_del(client, i); - nvkm_object_dtor(&client->object); - kfree(*pclient); - *pclient = NULL; - } + for (i = 0; i < ARRAY_SIZE(client->notify); i++) + nvkm_client_notify_del(client, i); + return client; } +static const struct nvkm_object_func +nvkm_client = { + .dtor = nvkm_client_dtor, + .fini = nvkm_client_fini, + .mthd = nvkm_client_mthd, + .sclass = nvkm_client_child_get, +}; + int nvkm_client_new(const char *name, u64 device, const char *cfg, const char *dbg, struct nvkm_client **pclient) @@ -256,7 +247,7 @@ nvkm_client_new(const char *name, u64 device, const char *cfg, return -ENOMEM; oclass.client = client; - nvkm_object_ctor(&nvkm_client_object_func, &oclass, &client->object); + nvkm_object_ctor(&nvkm_client, &oclass, &client->object); snprintf(client->name, sizeof(client->name), "%s", name); client->device = device; client->debug = nvkm_dbgopt(dbg, "CLIENT"); -- cgit v1.1 From 05da248bbe91fecb29e1f2fb9b978c4d2ee6da8e Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 25 May 2016 17:02:11 +1000 Subject: drm/nouveau/core/client: destroy client objects over nvif Preparation for supporting subclients, and also good for consistency. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_nvif.c | 10 ---------- drivers/gpu/drm/nouveau/nvif/client.c | 6 +++--- drivers/gpu/drm/nouveau/nvkm/core/ioctl.c | 13 +++++++------ 3 files changed, 10 insertions(+), 19 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nouveau_nvif.c b/drivers/gpu/drm/nouveau/nouveau_nvif.c index 5219da4..69341a6 100644 --- a/drivers/gpu/drm/nouveau/nouveau_nvif.c +++ b/drivers/gpu/drm/nouveau/nouveau_nvif.c @@ -71,15 +71,6 @@ nvkm_client_suspend(void *priv) return nvkm_object_fini(&client->object, true); } -static void -nvkm_client_driver_fini(void *priv) -{ - struct nvkm_client *client = priv; - struct nvkm_object *object = &client->object; - nvkm_object_fini(object, false); - nvkm_object_del(&object); -} - static int nvkm_client_ntfy(const void *header, u32 length, const void *data, u32 size) { @@ -128,7 +119,6 @@ const struct nvif_driver nvif_driver_nvkm = { .name = "nvkm", .init = nvkm_client_driver_init, - .fini = nvkm_client_driver_fini, .suspend = nvkm_client_suspend, .resume = nvkm_client_resume, .ioctl = nvkm_client_ioctl, diff --git a/drivers/gpu/drm/nouveau/nvif/client.c b/drivers/gpu/drm/nouveau/nvif/client.c index 29c20df..ad1307b 100644 --- a/drivers/gpu/drm/nouveau/nvif/client.c +++ b/drivers/gpu/drm/nouveau/nvif/client.c @@ -47,11 +47,11 @@ nvif_client_resume(struct nvif_client *client) void nvif_client_fini(struct nvif_client *client) { + nvif_object_fini(&client->object); if (client->driver) { - client->driver->fini(client->object.priv); + if (client->driver->fini) + client->driver->fini(client->object.priv); client->driver = NULL; - client->object.client = NULL; - nvif_object_fini(&client->object); } } diff --git a/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c b/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c index 25c800b..be19bbe 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c @@ -158,7 +158,7 @@ nvkm_ioctl_del(struct nvkm_client *client, nvkm_object_del(&object); } - return ret; + return ret ? ret : 1; } static int @@ -441,12 +441,13 @@ nvkm_ioctl(struct nvkm_client *client, bool supervisor, &args->v0.route, &args->v0.token); } - nvif_ioctl(object, "return %d\n", ret); - if (hack) { - *hack = client->data; - client->data = NULL; + if (ret != 1) { + nvif_ioctl(object, "return %d\n", ret); + if (hack) { + *hack = client->data; + client->data = NULL; + } } - client->super = false; return ret; } -- cgit v1.1 From 7c413feb7f9907c72aad7ea8f43af8ca8893c2bc Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 25 May 2016 17:08:21 +1000 Subject: drm/nouveau/core/client: pass notification callback to nvkm_client_new Preparation for supporting subclients. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvkm/core/client.h | 4 +++- drivers/gpu/drm/nouveau/nouveau_nvif.c | 12 ++---------- drivers/gpu/drm/nouveau/nvkm/core/client.c | 5 ++++- 3 files changed, 9 insertions(+), 12 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/client.h b/drivers/gpu/drm/nouveau/include/nvkm/core/client.h index 28f1078..e3b96e3 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/client.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/client.h @@ -20,7 +20,9 @@ struct nvkm_client { }; int nvkm_client_new(const char *name, u64 device, const char *cfg, - const char *dbg, struct nvkm_client **); + const char *dbg, + int (*)(const void *, u32, const void *, u32), + struct nvkm_client **); int nvkm_client_notify_new(struct nvkm_object *, struct nvkm_event *, void *data, u32 size); diff --git a/drivers/gpu/drm/nouveau/nouveau_nvif.c b/drivers/gpu/drm/nouveau/nouveau_nvif.c index 69341a6..b3f29b1 100644 --- a/drivers/gpu/drm/nouveau/nouveau_nvif.c +++ b/drivers/gpu/drm/nouveau/nouveau_nvif.c @@ -103,16 +103,8 @@ static int nvkm_client_driver_init(const char *name, u64 device, const char *cfg, const char *dbg, void **ppriv) { - struct nvkm_client *client; - int ret; - - ret = nvkm_client_new(name, device, cfg, dbg, &client); - *ppriv = client; - if (ret) - return ret; - - client->ntfy = nvkm_client_ntfy; - return 0; + return nvkm_client_new(name, device, cfg, dbg, nvkm_client_ntfy, + (struct nvkm_client **)ppriv); } const struct nvif_driver diff --git a/drivers/gpu/drm/nouveau/nvkm/core/client.c b/drivers/gpu/drm/nouveau/nvkm/core/client.c index 3cde975..4e2730c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/client.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/client.c @@ -238,7 +238,9 @@ nvkm_client = { int nvkm_client_new(const char *name, u64 device, const char *cfg, - const char *dbg, struct nvkm_client **pclient) + const char *dbg, + int (*ntfy)(const void *, u32, const void *, u32), + struct nvkm_client **pclient) { struct nvkm_oclass oclass = { .base = nvkm_uclient_sclass }; struct nvkm_client *client; @@ -252,5 +254,6 @@ nvkm_client_new(const char *name, u64 device, const char *cfg, client->device = device; client->debug = nvkm_dbgopt(dbg, "CLIENT"); client->objroot = RB_ROOT; + client->ntfy = ntfy; return 0; } -- cgit v1.1 From 04b8867758a4e1fca9d349f4a279fff8855db58c Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 22 May 2016 20:35:16 +1000 Subject: drm/nouveau/core/client: allow creation of subclients We want a supervisor client of NVKM (such as the DRM) to be able to allow sharing of resources (such as memory objects) between clients. To allow this, the supervisor creates all its clients as children of itself, and will use an upcoming ioctl to permit sharing. Currently it's not possible for indirect clients to use subclients. Supporting this will require an additional field in the main ioctl. This isn't important currently, but will need to be fixed for virt. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvif/client.h | 3 +- drivers/gpu/drm/nouveau/include/nvif/driver.h | 6 ++- drivers/gpu/drm/nouveau/include/nvif/if0000.h | 7 +++ drivers/gpu/drm/nouveau/include/nvkm/core/client.h | 1 + drivers/gpu/drm/nouveau/nouveau_drm.c | 6 ++- drivers/gpu/drm/nouveau/nvif/Kbuild | 1 + drivers/gpu/drm/nouveau/nvif/client.c | 43 ++++++---------- drivers/gpu/drm/nouveau/nvif/driver.c | 58 ++++++++++++++++++++++ drivers/gpu/drm/nouveau/nvkm/core/client.c | 50 ++++++++++++++++++- 9 files changed, 140 insertions(+), 35 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/nvif/driver.c (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/include/nvif/client.h b/drivers/gpu/drm/nouveau/include/nvif/client.h index 4a7f6f7..b52a8ea 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/client.h +++ b/drivers/gpu/drm/nouveau/include/nvif/client.h @@ -11,8 +11,7 @@ struct nvif_client { bool super; }; -int nvif_client_init(const char *drv, const char *name, u64 device, - const char *cfg, const char *dbg, +int nvif_client_init(struct nvif_client *parent, const char *name, u64 device, struct nvif_client *); void nvif_client_fini(struct nvif_client *); int nvif_client_ioctl(struct nvif_client *, void *, u32); diff --git a/drivers/gpu/drm/nouveau/include/nvif/driver.h b/drivers/gpu/drm/nouveau/include/nvif/driver.h index 8bd39e6..0c6f48d 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/driver.h +++ b/drivers/gpu/drm/nouveau/include/nvif/driver.h @@ -1,5 +1,7 @@ #ifndef __NVIF_DRIVER_H__ #define __NVIF_DRIVER_H__ +#include +struct nvif_client; struct nvif_driver { const char *name; @@ -14,9 +16,11 @@ struct nvif_driver { bool keep; }; +int nvif_driver_init(const char *drv, const char *cfg, const char *dbg, + const char *name, u64 device, struct nvif_client *); + extern const struct nvif_driver nvif_driver_nvkm; extern const struct nvif_driver nvif_driver_drm; extern const struct nvif_driver nvif_driver_lib; extern const struct nvif_driver nvif_driver_null; - #endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/if0000.h b/drivers/gpu/drm/nouveau/include/nvif/if0000.h index 18bbd82..c2c0fc4 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/if0000.h +++ b/drivers/gpu/drm/nouveau/include/nvif/if0000.h @@ -1,6 +1,13 @@ #ifndef __NVIF_IF0000_H__ #define __NVIF_IF0000_H__ +struct nvif_client_v0 { + __u8 version; + __u8 pad01[7]; + __u64 device; + char name[32]; +}; + #define NVIF_CLIENT_V0_DEVLIST 0x00 struct nvif_client_devlist_v0 { diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/client.h b/drivers/gpu/drm/nouveau/include/nvkm/core/client.h index e3b96e3..e4123192 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/client.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/client.h @@ -23,6 +23,7 @@ int nvkm_client_new(const char *name, u64 device, const char *cfg, const char *dbg, int (*)(const void *, u32, const void *, u32), struct nvkm_client **); +struct nvkm_client *nvkm_client_search(struct nvkm_client *, u64 handle); int nvkm_client_notify_new(struct nvkm_object *, struct nvkm_event *, void *data, u32 size); diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c index dd7b52a..279a96d 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c @@ -37,6 +37,8 @@ #include #include +#include + #include #include #include @@ -119,8 +121,8 @@ nouveau_cli_create(struct drm_device *dev, const char *sname, snprintf(cli->name, sizeof(cli->name), "%s", sname); cli->dev = dev; - ret = nvif_client_init(NULL, cli->name, nouveau_name(dev), - nouveau_config, nouveau_debug, + ret = nvif_driver_init(NULL, nouveau_config, nouveau_debug, + cli->name, nouveau_name(dev), &cli->base); if (ret == 0) { mutex_init(&cli->mutex); diff --git a/drivers/gpu/drm/nouveau/nvif/Kbuild b/drivers/gpu/drm/nouveau/nvif/Kbuild index ff8ed3a..067b5e9 100644 --- a/drivers/gpu/drm/nouveau/nvif/Kbuild +++ b/drivers/gpu/drm/nouveau/nvif/Kbuild @@ -1,4 +1,5 @@ nvif-y := nvif/object.o nvif-y += nvif/client.o nvif-y += nvif/device.o +nvif-y += nvif/driver.o nvif-y += nvif/notify.o diff --git a/drivers/gpu/drm/nouveau/nvif/client.c b/drivers/gpu/drm/nouveau/nvif/client.c index ad1307b..12db549 100644 --- a/drivers/gpu/drm/nouveau/nvif/client.c +++ b/drivers/gpu/drm/nouveau/nvif/client.c @@ -26,6 +26,9 @@ #include #include +#include +#include + int nvif_client_ioctl(struct nvif_client *client, void *data, u32 size) { @@ -55,29 +58,21 @@ nvif_client_fini(struct nvif_client *client) } } -static const struct nvif_driver * -nvif_drivers[] = { -#ifdef __KERNEL__ - &nvif_driver_nvkm, -#else - &nvif_driver_drm, - &nvif_driver_lib, - &nvif_driver_null, -#endif - NULL -}; - int -nvif_client_init(const char *driver, const char *name, u64 device, - const char *cfg, const char *dbg, struct nvif_client *client) +nvif_client_init(struct nvif_client *parent, const char *name, u64 device, + struct nvif_client *client) { + struct nvif_client_v0 args = { .device = device }; struct { struct nvif_ioctl_v0 ioctl; struct nvif_ioctl_nop_v0 nop; - } args = {}; - int ret, i; + } nop = {}; + int ret; - ret = nvif_object_init(NULL, 0, 0, NULL, 0, &client->object); + strncpy(args.name, name, sizeof(args.name)); + ret = nvif_object_init(parent != client ? &parent->object : NULL, + 0, NVIF_CLASS_CLIENT, &args, sizeof(args), + &client->object); if (ret) return ret; @@ -85,19 +80,11 @@ nvif_client_init(const char *driver, const char *name, u64 device, client->object.handle = ~0; client->route = NVIF_IOCTL_V0_ROUTE_NVIF; client->super = true; - - for (i = 0, ret = -EINVAL; (client->driver = nvif_drivers[i]); i++) { - if (!driver || !strcmp(client->driver->name, driver)) { - ret = client->driver->init(name, device, cfg, dbg, - &client->object.priv); - if (!ret || driver) - break; - } - } + client->driver = parent->driver; if (ret == 0) { - ret = nvif_client_ioctl(client, &args, sizeof(args)); - client->version = args.nop.version; + ret = nvif_client_ioctl(client, &nop, sizeof(nop)); + client->version = nop.nop.version; } if (ret) diff --git a/drivers/gpu/drm/nouveau/nvif/driver.c b/drivers/gpu/drm/nouveau/nvif/driver.c new file mode 100644 index 0000000..7013309 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvif/driver.c @@ -0,0 +1,58 @@ +/* + * Copyright 2016 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include +#include + +static const struct nvif_driver * +nvif_driver[] = { +#ifdef __KERNEL__ + &nvif_driver_nvkm, +#else + &nvif_driver_drm, + &nvif_driver_lib, + &nvif_driver_null, +#endif + NULL +}; + +int +nvif_driver_init(const char *drv, const char *cfg, const char *dbg, + const char *name, u64 device, struct nvif_client *client) +{ + int ret = -EINVAL, i; + + for (i = 0; (client->driver = nvif_driver[i]); i++) { + if (!drv || !strcmp(client->driver->name, drv)) { + ret = client->driver->init(name, device, cfg, dbg, + &client->object.priv); + if (ret == 0) + break; + client->driver->fini(client->object.priv); + } + } + + if (ret == 0) + ret = nvif_client_init(client, name, device, client); + return ret; +} diff --git a/drivers/gpu/drm/nouveau/nvkm/core/client.c b/drivers/gpu/drm/nouveau/nvkm/core/client.c index 4e2730c..0d3a896 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/client.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/client.c @@ -31,9 +31,41 @@ #include #include -static const struct nvkm_sclass +static int +nvkm_uclient_new(const struct nvkm_oclass *oclass, void *argv, u32 argc, + struct nvkm_object **pobject) +{ + union { + struct nvif_client_v0 v0; + } *args = argv; + struct nvkm_client *client; + int ret = -ENOSYS; + + if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))){ + args->v0.name[sizeof(args->v0.name) - 1] = 0; + ret = nvkm_client_new(args->v0.name, args->v0.device, NULL, + NULL, oclass->client->ntfy, &client); + if (ret) + return ret; + } else + return ret; + + client->object.client = oclass->client; + client->object.handle = oclass->handle; + client->object.route = oclass->route; + client->object.token = oclass->token; + client->object.object = oclass->object; + client->debug = oclass->client->debug; + *pobject = &client->object; + return 0; +} + +const struct nvkm_sclass nvkm_uclient_sclass = { .oclass = NVIF_CLASS_CLIENT, + .minver = 0, + .maxver = 0, + .ctor = nvkm_uclient_new, }; struct nvkm_client_notify { @@ -143,6 +175,19 @@ nvkm_client_notify_new(struct nvkm_object *object, return ret; } +static const struct nvkm_object_func nvkm_client; +struct nvkm_client * +nvkm_client_search(struct nvkm_client *client, u64 handle) +{ + struct nvkm_object *object; + + object = nvkm_object_search(client, handle, &nvkm_client); + if (IS_ERR(object)) + return (void *)object; + + return nvkm_client(object); +} + static int nvkm_client_mthd_devlist(struct nvkm_client *client, void *data, u32 size) { @@ -196,7 +241,8 @@ nvkm_client_child_get(struct nvkm_object *object, int index, const struct nvkm_sclass *sclass; switch (index) { - case 0: sclass = &nvkm_udevice_sclass; break; + case 0: sclass = &nvkm_uclient_sclass; break; + case 1: sclass = &nvkm_udevice_sclass; break; default: return -EINVAL; } -- cgit v1.1 From 134fdc1a704f0042465ea993c33540aaec7e1d2e Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 3 Oct 2015 17:34:25 +1000 Subject: drm/nouveau/core/mm: replace region list with next pointer We never have any need for a double-linked list here, and as there's generally a large number of these objects, replace it with a single- linked list in order to save some memory. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvkm/core/mm.h | 8 +++++++- drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h | 2 +- drivers/gpu/drm/nouveau/nouveau_bo.c | 2 +- drivers/gpu/drm/nouveau/nvkm/core/mm.c | 2 ++ drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c | 10 +++++----- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c | 23 ++++++++++------------ .../gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c | 17 ++++------------ drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c | 7 ++++--- 8 files changed, 34 insertions(+), 37 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/mm.h b/drivers/gpu/drm/nouveau/include/nvkm/core/mm.h index d92fd41..7bd4897 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/mm.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/mm.h @@ -5,7 +5,7 @@ struct nvkm_mm_node { struct list_head nl_entry; struct list_head fl_entry; - struct list_head rl_entry; + struct nvkm_mm_node *next; #define NVKM_MM_HEAP_ANY 0x00 u8 heap; @@ -38,4 +38,10 @@ int nvkm_mm_tail(struct nvkm_mm *, u8 heap, u8 type, u32 size_max, u32 size_min, u32 align, struct nvkm_mm_node **); void nvkm_mm_free(struct nvkm_mm *, struct nvkm_mm_node **); void nvkm_mm_dump(struct nvkm_mm *, const char *); + +static inline bool +nvkm_mm_contiguous(struct nvkm_mm_node *node) +{ + return !node->next; +} #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h index 794e432..0b26a4c 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h @@ -29,7 +29,7 @@ struct nvkm_mem { u8 page_shift; struct nvkm_mm_node *tag; - struct list_head regions; + struct nvkm_mm_node *mem; dma_addr_t *pages; u32 memtype; u64 offset; diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index 8a528eb..ef8a649 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -321,7 +321,7 @@ nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype, bool contig) if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG) { if (bo->mem.mem_type == TTM_PL_VRAM) { struct nvkm_mem *mem = bo->mem.mm_node; - if (!list_is_singular(&mem->regions)) + if (!nvkm_mm_contiguous(mem->mem)) evict = true; } nvbo->tile_flags &= ~NOUVEAU_GEM_TILE_NONCONTIG; diff --git a/drivers/gpu/drm/nouveau/nvkm/core/mm.c b/drivers/gpu/drm/nouveau/nvkm/core/mm.c index 09a1eee..fd19d65 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/mm.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/mm.c @@ -147,6 +147,7 @@ nvkm_mm_head(struct nvkm_mm *mm, u8 heap, u8 type, u32 size_max, u32 size_min, if (!this) return -ENOMEM; + this->next = NULL; this->type = type; list_del(&this->fl_entry); *pnode = this; @@ -225,6 +226,7 @@ nvkm_mm_tail(struct nvkm_mm *mm, u8 heap, u8 type, u32 size_max, u32 size_min, if (!this) return -ENOMEM; + this->next = NULL; this->type = type; list_del(&this->fl_entry); *pnode = this; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c index 093223d..6758da9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c @@ -445,7 +445,7 @@ gf100_ram_get(struct nvkm_ram *ram, u64 size, u32 align, u32 ncmin, { struct nvkm_ltc *ltc = ram->fb->subdev.device->ltc; struct nvkm_mm *mm = &ram->vram; - struct nvkm_mm_node *r; + struct nvkm_mm_node **node, *r; struct nvkm_mem *mem; int type = (memtype & 0x0ff); int back = (memtype & 0x800); @@ -462,7 +462,6 @@ gf100_ram_get(struct nvkm_ram *ram, u64 size, u32 align, u32 ncmin, if (!mem) return -ENOMEM; - INIT_LIST_HEAD(&mem->regions); mem->size = size; mutex_lock(&ram->fb->subdev.mutex); @@ -478,6 +477,7 @@ gf100_ram_get(struct nvkm_ram *ram, u64 size, u32 align, u32 ncmin, } mem->memtype = type; + node = &mem->mem; do { if (back) ret = nvkm_mm_tail(mm, 0, 1, size, ncmin, align, &r); @@ -489,13 +489,13 @@ gf100_ram_get(struct nvkm_ram *ram, u64 size, u32 align, u32 ncmin, return ret; } - list_add_tail(&r->rl_entry, &mem->regions); + *node = r; + node = &r->next; size -= r->length; } while (size); mutex_unlock(&ram->fb->subdev.mutex); - r = list_first_entry(&mem->regions, struct nvkm_mm_node, rl_entry); - mem->offset = (u64)r->offset << NVKM_RAM_MM_SHIFT; + mem->offset = (u64)mem->mem->offset << NVKM_RAM_MM_SHIFT; *pmem = mem; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c index 87bde8f..6549b05 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c @@ -496,15 +496,12 @@ nv50_ram_tidy(struct nvkm_ram *base) void __nv50_ram_put(struct nvkm_ram *ram, struct nvkm_mem *mem) { - struct nvkm_mm_node *this; - - while (!list_empty(&mem->regions)) { - this = list_first_entry(&mem->regions, typeof(*this), rl_entry); - - list_del(&this->rl_entry); - nvkm_mm_free(&ram->vram, &this); + struct nvkm_mm_node *next = mem->mem; + struct nvkm_mm_node *node; + while ((node = next)) { + next = node->next; + nvkm_mm_free(&ram->vram, &node); } - nvkm_mm_free(&ram->tags, &mem->tag); } @@ -530,7 +527,7 @@ nv50_ram_get(struct nvkm_ram *ram, u64 size, u32 align, u32 ncmin, { struct nvkm_mm *heap = &ram->vram; struct nvkm_mm *tags = &ram->tags; - struct nvkm_mm_node *r; + struct nvkm_mm_node **node, *r; struct nvkm_mem *mem; int comp = (memtype & 0x300) >> 8; int type = (memtype & 0x07f); @@ -559,11 +556,11 @@ nv50_ram_get(struct nvkm_ram *ram, u64 size, u32 align, u32 ncmin, comp = 0; } - INIT_LIST_HEAD(&mem->regions); mem->memtype = (comp << 7) | type; mem->size = max; type = nv50_fb_memtype[type]; + node = &mem->mem; do { if (back) ret = nvkm_mm_tail(heap, 0, type, max, min, align, &r); @@ -575,13 +572,13 @@ nv50_ram_get(struct nvkm_ram *ram, u64 size, u32 align, u32 ncmin, return ret; } - list_add_tail(&r->rl_entry, &mem->regions); + *node = r; + node = &r->next; max -= r->length; } while (max); mutex_unlock(&ram->fb->subdev.mutex); - r = list_first_entry(&mem->regions, struct nvkm_mm_node, rl_entry); - mem->offset = (u64)r->offset << NVKM_RAM_MM_SHIFT; + mem->offset = (u64)mem->mem->offset << NVKM_RAM_MM_SHIFT; *pmem = mem; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c index a6a7fa0..a942383 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c @@ -305,11 +305,11 @@ gk20a_instobj_dtor_iommu(struct nvkm_memory *memory) struct gk20a_instobj_iommu *node = gk20a_instobj_iommu(memory); struct gk20a_instmem *imem = node->base.imem; struct device *dev = imem->base.subdev.device->dev; - struct nvkm_mm_node *r; + struct nvkm_mm_node *r = node->base.mem.mem; unsigned long flags; int i; - if (unlikely(list_empty(&node->base.mem.regions))) + if (unlikely(!r)) goto out; spin_lock_irqsave(&imem->lock, flags); @@ -320,9 +320,6 @@ gk20a_instobj_dtor_iommu(struct nvkm_memory *memory) spin_unlock_irqrestore(&imem->lock, flags); - r = list_first_entry(&node->base.mem.regions, struct nvkm_mm_node, - rl_entry); - /* clear IOMMU bit to unmap pages */ r->offset &= ~BIT(imem->iommu_bit - imem->iommu_pgshift); @@ -404,10 +401,7 @@ gk20a_instobj_ctor_dma(struct gk20a_instmem *imem, u32 npages, u32 align, node->r.length = (npages << PAGE_SHIFT) >> 12; node->base.mem.offset = node->handle; - - INIT_LIST_HEAD(&node->base.mem.regions); - list_add_tail(&node->r.rl_entry, &node->base.mem.regions); - + node->base.mem.mem = &node->r; return 0; } @@ -484,10 +478,7 @@ gk20a_instobj_ctor_iommu(struct gk20a_instmem *imem, u32 npages, u32 align, r->offset |= BIT(imem->iommu_bit - imem->iommu_pgshift); node->base.mem.offset = ((u64)r->offset) << imem->iommu_pgshift; - - INIT_LIST_HEAD(&node->base.mem.regions); - list_add_tail(&r->rl_entry, &node->base.mem.regions); - + node->base.mem.mem = r; return 0; release_area: diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c index 5df9669..d06ad2c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c @@ -31,7 +31,7 @@ nvkm_vm_map_at(struct nvkm_vma *vma, u64 delta, struct nvkm_mem *node) { struct nvkm_vm *vm = vma->vm; struct nvkm_mmu *mmu = vm->mmu; - struct nvkm_mm_node *r; + struct nvkm_mm_node *r = node->mem; int big = vma->node->type != mmu->func->spg_shift; u32 offset = vma->node->offset + (delta >> 12); u32 bits = vma->node->type - 12; @@ -41,7 +41,7 @@ nvkm_vm_map_at(struct nvkm_vma *vma, u64 delta, struct nvkm_mem *node) u32 end, len; delta = 0; - list_for_each_entry(r, &node->regions, rl_entry) { + while (r) { u64 phys = (u64)r->offset << 12; u32 num = r->length >> bits; @@ -65,7 +65,8 @@ nvkm_vm_map_at(struct nvkm_vma *vma, u64 delta, struct nvkm_mem *node) delta += (u64)len << vma->node->type; } - } + r = r->next; + }; mmu->func->flush(vm); } -- cgit v1.1 From d2ee360564dca43cbfb2bd8ceead7671c87962d2 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 10 May 2016 12:42:26 +1000 Subject: drm/nouveau/core/memory: distinguish between coherent/non-coherent targets Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvkm/core/memory.h | 7 ++++--- drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c | 9 ++++++++- drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c | 11 +++++++---- drivers/gpu/drm/nouveau/nvkm/falcon/v1.c | 11 +++++++---- drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c | 2 +- 5 files changed, 27 insertions(+), 13 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/memory.h b/drivers/gpu/drm/nouveau/include/nvkm/core/memory.h index 9363b83..33ca676 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/memory.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/memory.h @@ -6,9 +6,10 @@ struct nvkm_vma; struct nvkm_vm; enum nvkm_memory_target { - NVKM_MEM_TARGET_INST, - NVKM_MEM_TARGET_VRAM, - NVKM_MEM_TARGET_HOST, + NVKM_MEM_TARGET_INST, /* instance memory */ + NVKM_MEM_TARGET_VRAM, /* video memory */ + NVKM_MEM_TARGET_HOST, /* coherent system memory */ + NVKM_MEM_TARGET_NCOH, /* non-coherent system memory */ }; struct nvkm_memory { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c index ec68ea9..8772a99 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c @@ -68,7 +68,14 @@ gf100_fifo_runlist_commit(struct gf100_fifo *fifo) } nvkm_done(cur); - target = (nvkm_memory_target(cur) == NVKM_MEM_TARGET_HOST) ? 0x3 : 0x0; + switch (nvkm_memory_target(cur)) { + case NVKM_MEM_TARGET_VRAM: target = 0; break; + case NVKM_MEM_TARGET_NCOH: target = 3; break; + default: + mutex_unlock(&subdev->mutex); + WARN_ON(1); + return; + } nvkm_wr32(device, 0x002270, (nvkm_memory_addr(cur) >> 12) | (target << 28)); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c index 38c0910..73ae4ec 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c @@ -83,10 +83,13 @@ gk104_fifo_runlist_commit(struct gk104_fifo *fifo, int runl) } nvkm_done(mem); - if (nvkm_memory_target(mem) == NVKM_MEM_TARGET_VRAM) - target = 0; - else - target = 3; + switch (nvkm_memory_target(mem)) { + case NVKM_MEM_TARGET_VRAM: target = 0; break; + case NVKM_MEM_TARGET_NCOH: target = 3; break; + default: + WARN_ON(1); + return; + } nvkm_wr32(device, 0x002270, (nvkm_memory_addr(mem) >> 12) | (target << 28)); diff --git a/drivers/gpu/drm/nouveau/nvkm/falcon/v1.c b/drivers/gpu/drm/nouveau/nvkm/falcon/v1.c index 24a2958..b537f11 100644 --- a/drivers/gpu/drm/nouveau/nvkm/falcon/v1.c +++ b/drivers/gpu/drm/nouveau/nvkm/falcon/v1.c @@ -136,10 +136,13 @@ nvkm_falcon_v1_bind_context(struct nvkm_falcon *falcon, struct nvkm_gpuobj *ctx) nvkm_falcon_wr32(falcon, 0xe00 + 4 * FALCON_DMAIDX_PHYS_SYS_NCOH, 0x6); /* Set context */ - if (nvkm_memory_target(ctx->memory) == NVKM_MEM_TARGET_VRAM) - inst_loc = 0x0; /* FB */ - else - inst_loc = 0x3; /* Non-coherent sysmem */ + switch (nvkm_memory_target(ctx->memory)) { + case NVKM_MEM_TARGET_VRAM: inst_loc = 0; break; + case NVKM_MEM_TARGET_NCOH: inst_loc = 3; break; + default: + WARN_ON(1); + return; + } /* Enable context */ nvkm_falcon_mask(falcon, 0x048, 0x1, 0x1); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c index a942383..9dec58ec 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c @@ -116,7 +116,7 @@ struct gk20a_instmem { static enum nvkm_memory_target gk20a_instobj_target(struct nvkm_memory *memory) { - return NVKM_MEM_TARGET_HOST; + return NVKM_MEM_TARGET_NCOH; } static u64 -- cgit v1.1 From bab7cc18d3ba56c9160f4708dbf353eaa3ce1ec5 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 24 May 2016 17:26:48 +1000 Subject: drm/nouveau: pass nvif_client to nouveau_bo_new() instead of drm_device Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv04/crtc.c | 5 +++-- drivers/gpu/drm/nouveau/nouveau_bo.c | 5 +++-- drivers/gpu/drm/nouveau/nouveau_bo.h | 4 +++- drivers/gpu/drm/nouveau/nouveau_chan.c | 2 +- drivers/gpu/drm/nouveau/nouveau_gem.c | 2 +- drivers/gpu/drm/nouveau/nouveau_prime.c | 3 ++- drivers/gpu/drm/nouveau/nv17_fence.c | 2 +- drivers/gpu/drm/nouveau/nv50_display.c | 4 ++-- drivers/gpu/drm/nouveau/nv50_fence.c | 2 +- drivers/gpu/drm/nouveau/nv84_fence.c | 6 +++--- 10 files changed, 20 insertions(+), 15 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/dispnv04/crtc.c b/drivers/gpu/drm/nouveau/dispnv04/crtc.c index a72754d..eb86f69 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/crtc.c +++ b/drivers/gpu/drm/nouveau/dispnv04/crtc.c @@ -1124,8 +1124,9 @@ nv04_crtc_create(struct drm_device *dev, int crtc_num) drm_crtc_helper_add(&nv_crtc->base, &nv04_crtc_helper_funcs); drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256); - ret = nouveau_bo_new(dev, 64*64*4, 0x100, TTM_PL_FLAG_VRAM, - 0, 0x0000, NULL, NULL, &nv_crtc->cursor.nvbo); + ret = nouveau_bo_new(&nouveau_drm(dev)->client, 64*64*4, 0x100, + TTM_PL_FLAG_VRAM, 0, 0x0000, NULL, NULL, + &nv_crtc->cursor.nvbo); if (!ret) { ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM, false); if (!ret) { diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index ef8a649..66c5085 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -174,12 +174,12 @@ nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags, } int -nouveau_bo_new(struct drm_device *dev, int size, int align, +nouveau_bo_new(struct nouveau_cli *cli, int size, int align, uint32_t flags, uint32_t tile_mode, uint32_t tile_flags, struct sg_table *sg, struct reservation_object *robj, struct nouveau_bo **pnvbo) { - struct nouveau_drm *drm = nouveau_drm(dev); + struct nouveau_drm *drm = nouveau_drm(cli->dev); struct nouveau_bo *nvbo; size_t acc_size; int ret; @@ -208,6 +208,7 @@ nouveau_bo_new(struct drm_device *dev, int size, int align, nvbo->tile_mode = tile_mode; nvbo->tile_flags = tile_flags; nvbo->bo.bdev = &drm->ttm.bdev; + nvbo->cli = cli; if (!nvxx_device(&drm->device)->func->cpu_coherent) nvbo->force_coherent = flags & TTM_PL_FLAG_UNCACHED; diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.h b/drivers/gpu/drm/nouveau/nouveau_bo.h index e423609..abb8a18 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.h +++ b/drivers/gpu/drm/nouveau/nouveau_bo.h @@ -26,6 +26,8 @@ struct nouveau_bo { struct list_head vma_list; unsigned page_shift; + struct nouveau_cli *cli; + u32 tile_mode; u32 tile_flags; struct nouveau_drm_tile *tile; @@ -69,7 +71,7 @@ nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) extern struct ttm_bo_driver nouveau_bo_driver; void nouveau_bo_move_init(struct nouveau_drm *); -int nouveau_bo_new(struct drm_device *, int size, int align, u32 flags, +int nouveau_bo_new(struct nouveau_cli *, int size, int align, u32 flags, u32 tile_mode, u32 tile_flags, struct sg_table *sg, struct reservation_object *robj, struct nouveau_bo **); diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.c b/drivers/gpu/drm/nouveau/nouveau_chan.c index f9b3c81..d50c6e5 100644 --- a/drivers/gpu/drm/nouveau/nouveau_chan.c +++ b/drivers/gpu/drm/nouveau/nouveau_chan.c @@ -113,7 +113,7 @@ nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device, if (nouveau_vram_pushbuf) target = TTM_PL_FLAG_VRAM; - ret = nouveau_bo_new(drm->dev, size, 0, target, 0, 0, NULL, NULL, + ret = nouveau_bo_new(cli, size, 0, target, 0, 0, NULL, NULL, &chan->push.buffer); if (ret == 0) { ret = nouveau_bo_pin(chan->push.buffer, target, false); diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c index 201b52b..5261ad1 100644 --- a/drivers/gpu/drm/nouveau/nouveau_gem.c +++ b/drivers/gpu/drm/nouveau/nouveau_gem.c @@ -194,7 +194,7 @@ nouveau_gem_new(struct drm_device *dev, int size, int align, uint32_t domain, if (domain & NOUVEAU_GEM_DOMAIN_COHERENT) flags |= TTM_PL_FLAG_UNCACHED; - ret = nouveau_bo_new(dev, size, align, flags, tile_mode, + ret = nouveau_bo_new(&drm->client, size, align, flags, tile_mode, tile_flags, NULL, NULL, pnvbo); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nouveau_prime.c b/drivers/gpu/drm/nouveau/nouveau_prime.c index a0a9704..1fefc93 100644 --- a/drivers/gpu/drm/nouveau/nouveau_prime.c +++ b/drivers/gpu/drm/nouveau/nouveau_prime.c @@ -60,6 +60,7 @@ struct drm_gem_object *nouveau_gem_prime_import_sg_table(struct drm_device *dev, struct dma_buf_attachment *attach, struct sg_table *sg) { + struct nouveau_drm *drm = nouveau_drm(dev); struct nouveau_bo *nvbo; struct reservation_object *robj = attach->dmabuf->resv; u32 flags = 0; @@ -68,7 +69,7 @@ struct drm_gem_object *nouveau_gem_prime_import_sg_table(struct drm_device *dev, flags = TTM_PL_FLAG_TT; ww_mutex_lock(&robj->lock, NULL); - ret = nouveau_bo_new(dev, attach->dmabuf->size, 0, flags, 0, 0, + ret = nouveau_bo_new(&drm->client, attach->dmabuf->size, 0, flags, 0, 0, sg, robj, &nvbo); ww_mutex_unlock(&robj->lock); if (ret) diff --git a/drivers/gpu/drm/nouveau/nv17_fence.c b/drivers/gpu/drm/nouveau/nv17_fence.c index 79bc011..5aeda14 100644 --- a/drivers/gpu/drm/nouveau/nv17_fence.c +++ b/drivers/gpu/drm/nouveau/nv17_fence.c @@ -129,7 +129,7 @@ nv17_fence_create(struct nouveau_drm *drm) priv->base.context_base = dma_fence_context_alloc(priv->base.contexts); spin_lock_init(&priv->lock); - ret = nouveau_bo_new(drm->dev, 4096, 0x1000, TTM_PL_FLAG_VRAM, + ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM, 0, 0x0000, NULL, NULL, &priv->bo); if (!ret) { ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM, false); diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c index db35bee..9d22303 100644 --- a/drivers/gpu/drm/nouveau/nv50_display.c +++ b/drivers/gpu/drm/nouveau/nv50_display.c @@ -2428,7 +2428,7 @@ nv50_head_create(struct drm_device *dev, int index) drm_crtc_helper_add(crtc, &nv50_head_help); drm_mode_crtc_set_gamma_size(crtc, 256); - ret = nouveau_bo_new(dev, 8192, 0x100, TTM_PL_FLAG_VRAM, + ret = nouveau_bo_new(&drm->client, 8192, 0x100, TTM_PL_FLAG_VRAM, 0, 0x0000, NULL, NULL, &head->base.lut.nvbo); if (!ret) { ret = nouveau_bo_pin(head->base.lut.nvbo, TTM_PL_FLAG_VRAM, true); @@ -4451,7 +4451,7 @@ nv50_display_create(struct drm_device *dev) dev->driver->driver_features |= DRIVER_ATOMIC; /* small shared memory area we use for notifiers and semaphores */ - ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM, + ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM, 0, 0x0000, NULL, NULL, &disp->sync); if (!ret) { ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true); diff --git a/drivers/gpu/drm/nouveau/nv50_fence.c b/drivers/gpu/drm/nouveau/nv50_fence.c index f68c705..1e3ac3f 100644 --- a/drivers/gpu/drm/nouveau/nv50_fence.c +++ b/drivers/gpu/drm/nouveau/nv50_fence.c @@ -82,7 +82,7 @@ nv50_fence_create(struct nouveau_drm *drm) priv->base.context_base = dma_fence_context_alloc(priv->base.contexts); spin_lock_init(&priv->lock); - ret = nouveau_bo_new(drm->dev, 4096, 0x1000, TTM_PL_FLAG_VRAM, + ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM, 0, 0x0000, NULL, NULL, &priv->bo); if (!ret) { ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM, false); diff --git a/drivers/gpu/drm/nouveau/nv84_fence.c b/drivers/gpu/drm/nouveau/nv84_fence.c index 52b87ae..be30aaf 100644 --- a/drivers/gpu/drm/nouveau/nv84_fence.c +++ b/drivers/gpu/drm/nouveau/nv84_fence.c @@ -219,8 +219,8 @@ nv84_fence_create(struct nouveau_drm *drm) * will lose CPU/GPU coherency! */ TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED; - ret = nouveau_bo_new(drm->dev, 16 * priv->base.contexts, 0, domain, 0, - 0, NULL, NULL, &priv->bo); + ret = nouveau_bo_new(&drm->client, 16 * priv->base.contexts, 0, + domain, 0, 0, NULL, NULL, &priv->bo); if (ret == 0) { ret = nouveau_bo_pin(priv->bo, domain, false); if (ret == 0) { @@ -233,7 +233,7 @@ nv84_fence_create(struct nouveau_drm *drm) } if (ret == 0) - ret = nouveau_bo_new(drm->dev, 16 * priv->base.contexts, 0, + ret = nouveau_bo_new(&drm->client, 16 * priv->base.contexts, 0, TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED, 0, 0, NULL, NULL, &priv->bo_gart); if (ret == 0) { -- cgit v1.1 From fc1b0a02ad4f463e10574afcec797ff620f6813d Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 24 May 2016 17:29:55 +1000 Subject: drm/nouveau: pass nvif_client to nouveau_gem_new() instead of drm_device Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_abi16.c | 2 +- drivers/gpu/drm/nouveau/nouveau_display.c | 3 ++- drivers/gpu/drm/nouveau/nouveau_fbcon.c | 5 +++-- drivers/gpu/drm/nouveau/nouveau_gem.c | 10 +++++----- drivers/gpu/drm/nouveau/nouveau_gem.h | 2 +- 5 files changed, 12 insertions(+), 10 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.c b/drivers/gpu/drm/nouveau/nouveau_abi16.c index 4df4f6e..0232909 100644 --- a/drivers/gpu/drm/nouveau/nouveau_abi16.c +++ b/drivers/gpu/drm/nouveau/nouveau_abi16.c @@ -321,7 +321,7 @@ nouveau_abi16_ioctl_channel_alloc(ABI16_IOCTL_ARGS) } /* Named memory object area */ - ret = nouveau_gem_new(dev, PAGE_SIZE, 0, NOUVEAU_GEM_DOMAIN_GART, + ret = nouveau_gem_new(cli, PAGE_SIZE, 0, NOUVEAU_GEM_DOMAIN_GART, 0, 0, &chan->ntfy); if (ret == 0) ret = nouveau_bo_pin(chan->ntfy, TTM_PL_FLAG_TT, false); diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c index 6b57007..cac940c 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.c +++ b/drivers/gpu/drm/nouveau/nouveau_display.c @@ -1057,6 +1057,7 @@ int nouveau_display_dumb_create(struct drm_file *file_priv, struct drm_device *dev, struct drm_mode_create_dumb *args) { + struct nouveau_cli *cli = nouveau_cli(file_priv); struct nouveau_bo *bo; uint32_t domain; int ret; @@ -1071,7 +1072,7 @@ nouveau_display_dumb_create(struct drm_file *file_priv, struct drm_device *dev, else domain = NOUVEAU_GEM_DOMAIN_GART; - ret = nouveau_gem_new(dev, args->size, 0, domain, 0, 0, &bo); + ret = nouveau_gem_new(cli, args->size, 0, domain, 0, 0, &bo); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c index 971c147..8132372 100644 --- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c +++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c @@ -341,8 +341,9 @@ nouveau_fbcon_create(struct drm_fb_helper *helper, mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp, sizes->surface_depth); - ret = nouveau_gem_new(dev, mode_cmd.pitches[0] * mode_cmd.height, - 0, NOUVEAU_GEM_DOMAIN_VRAM, 0, 0x0000, &nvbo); + ret = nouveau_gem_new(&drm->client, mode_cmd.pitches[0] * + mode_cmd.height, 0, NOUVEAU_GEM_DOMAIN_VRAM, + 0, 0x0000, &nvbo); if (ret) { NV_ERROR(drm, "failed to allocate framebuffer\n"); goto out; diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c index 5261ad1..4ff2d2c 100644 --- a/drivers/gpu/drm/nouveau/nouveau_gem.c +++ b/drivers/gpu/drm/nouveau/nouveau_gem.c @@ -175,11 +175,11 @@ nouveau_gem_object_close(struct drm_gem_object *gem, struct drm_file *file_priv) } int -nouveau_gem_new(struct drm_device *dev, int size, int align, uint32_t domain, +nouveau_gem_new(struct nouveau_cli *cli, int size, int align, uint32_t domain, uint32_t tile_mode, uint32_t tile_flags, struct nouveau_bo **pnvbo) { - struct nouveau_drm *drm = nouveau_drm(dev); + struct nouveau_drm *drm = nouveau_drm(cli->dev); struct nouveau_bo *nvbo; u32 flags = 0; int ret; @@ -194,7 +194,7 @@ nouveau_gem_new(struct drm_device *dev, int size, int align, uint32_t domain, if (domain & NOUVEAU_GEM_DOMAIN_COHERENT) flags |= TTM_PL_FLAG_UNCACHED; - ret = nouveau_bo_new(&drm->client, size, align, flags, tile_mode, + ret = nouveau_bo_new(cli, size, align, flags, tile_mode, tile_flags, NULL, NULL, pnvbo); if (ret) return ret; @@ -211,7 +211,7 @@ nouveau_gem_new(struct drm_device *dev, int size, int align, uint32_t domain, /* Initialize the embedded gem-object. We return a single gem-reference * to the caller, instead of a normal nouveau_bo ttm reference. */ - ret = drm_gem_object_init(dev, &nvbo->gem, nvbo->bo.mem.size); + ret = drm_gem_object_init(drm->dev, &nvbo->gem, nvbo->bo.mem.size); if (ret) { nouveau_bo_ref(NULL, pnvbo); return -ENOMEM; @@ -267,7 +267,7 @@ nouveau_gem_ioctl_new(struct drm_device *dev, void *data, return -EINVAL; } - ret = nouveau_gem_new(dev, req->info.size, req->align, + ret = nouveau_gem_new(cli, req->info.size, req->align, req->info.domain, req->info.tile_mode, req->info.tile_flags, &nvbo); if (ret) diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.h b/drivers/gpu/drm/nouveau/nouveau_gem.h index 7e32da2..5ce9a0e 100644 --- a/drivers/gpu/drm/nouveau/nouveau_gem.h +++ b/drivers/gpu/drm/nouveau/nouveau_gem.h @@ -16,7 +16,7 @@ nouveau_gem_object(struct drm_gem_object *gem) } /* nouveau_gem.c */ -extern int nouveau_gem_new(struct drm_device *, int size, int align, +extern int nouveau_gem_new(struct nouveau_cli *, int size, int align, uint32_t domain, uint32_t tile_mode, uint32_t tile_flags, struct nouveau_bo **); extern void nouveau_gem_object_del(struct drm_gem_object *); -- cgit v1.1 From 20d8a88e557aae5264e793f4626c45cd644c7144 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 18 May 2016 13:36:34 +1000 Subject: drm/nouveau: tidy up the client init/fini interfaces These were a little insane. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_drm.c | 86 ++++++++++++++++++++--------------- drivers/gpu/drm/nouveau/nouveau_drv.h | 5 +- 2 files changed, 52 insertions(+), 39 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c index 279a96d..e7a69d1 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c @@ -111,35 +111,37 @@ nouveau_name(struct drm_device *dev) return nouveau_platform_name(dev->platformdev); } +static void +nouveau_cli_fini(struct nouveau_cli *cli) +{ + nvkm_vm_ref(NULL, &nvxx_client(&cli->base)->vm, NULL); + usif_client_fini(cli); + nvif_client_fini(&cli->base); +} + static int -nouveau_cli_create(struct drm_device *dev, const char *sname, - int size, void **pcli) +nouveau_cli_init(struct nouveau_drm *drm, const char *sname, + struct nouveau_cli *cli) { - struct nouveau_cli *cli = *pcli = kzalloc(size, GFP_KERNEL); + u64 device = nouveau_name(drm->dev); int ret; - if (cli) { - snprintf(cli->name, sizeof(cli->name), "%s", sname); - cli->dev = dev; - ret = nvif_driver_init(NULL, nouveau_config, nouveau_debug, - cli->name, nouveau_name(dev), - &cli->base); - if (ret == 0) { - mutex_init(&cli->mutex); - usif_client_init(cli); - } - return ret; + snprintf(cli->name, sizeof(cli->name), "%s", sname); + cli->dev = drm->dev; + mutex_init(&cli->mutex); + usif_client_init(cli); + + ret = nvif_driver_init(NULL, nouveau_config, nouveau_debug, + cli->name, device, &cli->base); + if (ret) { + NV_ERROR(drm, "Client allocation failed: %d\n", ret); + goto done; } - return -ENOMEM; -} -static void -nouveau_cli_destroy(struct nouveau_cli *cli) -{ - nvkm_vm_ref(NULL, &nvxx_client(&cli->base)->vm, NULL); - nvif_client_fini(&cli->base); - usif_client_fini(cli); - kfree(cli); +done: + if (ret) + nouveau_cli_fini(cli); + return ret; } static void @@ -409,12 +411,15 @@ nouveau_drm_load(struct drm_device *dev, unsigned long flags) struct nouveau_drm *drm; int ret; - ret = nouveau_cli_create(dev, "DRM", sizeof(*drm), (void **)&drm); + if (!(drm = kzalloc(sizeof(*drm), GFP_KERNEL))) + return -ENOMEM; + dev->dev_private = drm; + drm->dev = dev; + + ret = nouveau_cli_init(drm, "DRM", &drm->client); if (ret) return ret; - dev->dev_private = drm; - drm->dev = dev; nvxx_client(&drm->client.base)->debug = nvkm_dbgopt(nouveau_debug, "DRM"); @@ -500,7 +505,8 @@ fail_ttm: nouveau_vga_fini(drm); fail_device: nvif_device_fini(&drm->device); - nouveau_cli_destroy(&drm->client); + nouveau_cli_fini(&drm->client); + kfree(drm); return ret; } @@ -532,7 +538,8 @@ nouveau_drm_unload(struct drm_device *dev) nvif_device_fini(&drm->device); if (drm->hdmi_device) pci_dev_put(drm->hdmi_device); - nouveau_cli_destroy(&drm->client); + nouveau_cli_fini(&drm->client); + kfree(drm); } void @@ -843,20 +850,20 @@ nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv) get_task_comm(tmpname, current); snprintf(name, sizeof(name), "%s[%d]", tmpname, pid_nr(fpriv->pid)); - ret = nouveau_cli_create(dev, name, sizeof(*cli), (void **)&cli); + if (!(cli = kzalloc(sizeof(*cli), GFP_KERNEL))) + return ret; + ret = nouveau_cli_init(drm, name, cli); if (ret) - goto out_suspend; + goto done; cli->base.super = false; if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) { ret = nvkm_vm_new(nvxx_device(&drm->device), 0, (1ULL << 40), 0x1000, NULL, &cli->vm); - if (ret) { - nouveau_cli_destroy(cli); - goto out_suspend; - } + if (ret) + goto done; nvxx_client(&cli->base)->vm = cli->vm; } @@ -867,10 +874,14 @@ nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv) list_add(&cli->head, &drm->clients); mutex_unlock(&drm->client.mutex); -out_suspend: +done: + if (ret && cli) { + nouveau_cli_fini(cli); + kfree(cli); + } + pm_runtime_mark_last_busy(dev->dev); pm_runtime_put_autosuspend(dev->dev); - return ret; } @@ -897,7 +908,8 @@ static void nouveau_drm_postclose(struct drm_device *dev, struct drm_file *fpriv) { struct nouveau_cli *cli = nouveau_cli(fpriv); - nouveau_cli_destroy(cli); + nouveau_cli_fini(cli); + kfree(cli); pm_runtime_mark_last_busy(dev->dev); pm_runtime_put_autosuspend(dev->dev); } diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h index 8d5ed5b..ac36bef 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/drivers/gpu/drm/nouveau/nouveau_drv.h @@ -86,14 +86,15 @@ enum nouveau_drm_handle { struct nouveau_cli { struct nvif_client base; + struct drm_device *dev; + struct mutex mutex; + struct nvkm_vm *vm; /*XXX*/ struct list_head head; - struct mutex mutex; void *abi16; struct list_head objects; struct list_head notifys; char name[32]; - struct drm_device *dev; }; static inline struct nouveau_cli * -- cgit v1.1 From 80e60973b2494a0c51b2c84847f3faeffed595f0 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 23 May 2016 11:25:17 +1000 Subject: drm/nouveau: create userspace clients as subclients This will allow the DRM to share memory objects between clients later down the track. For the moment, the only immediate benefit is less logic required to handle suspend/resume. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_drm.c | 33 +++++++++++---------------------- 1 file changed, 11 insertions(+), 22 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c index e7a69d1..1e30398 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c @@ -131,8 +131,13 @@ nouveau_cli_init(struct nouveau_drm *drm, const char *sname, mutex_init(&cli->mutex); usif_client_init(cli); - ret = nvif_driver_init(NULL, nouveau_config, nouveau_debug, - cli->name, device, &cli->base); + if (cli == &drm->client) { + ret = nvif_driver_init(NULL, nouveau_config, nouveau_debug, + cli->name, device, &cli->base); + } else { + ret = nvif_client_init(&drm->client.base, cli->name, device, + &cli->base); + } if (ret) { NV_ERROR(drm, "Client allocation failed: %d\n", ret); goto done; @@ -569,7 +574,6 @@ static int nouveau_do_suspend(struct drm_device *dev, bool runtime) { struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_cli *cli; int ret; nouveau_led_suspend(dev); @@ -599,7 +603,7 @@ nouveau_do_suspend(struct drm_device *dev, bool runtime) goto fail_display; } - NV_INFO(drm, "suspending client object trees...\n"); + NV_INFO(drm, "suspending fence...\n"); if (drm->fence && nouveau_fence(drm)->suspend) { if (!nouveau_fence(drm)->suspend(drm)) { ret = -ENOMEM; @@ -607,13 +611,7 @@ nouveau_do_suspend(struct drm_device *dev, bool runtime) } } - list_for_each_entry(cli, &drm->clients, head) { - ret = nvif_client_suspend(&cli->base); - if (ret) - goto fail_client; - } - - NV_INFO(drm, "suspending kernel object tree...\n"); + NV_INFO(drm, "suspending object tree...\n"); ret = nvif_client_suspend(&drm->client.base); if (ret) goto fail_client; @@ -621,10 +619,6 @@ nouveau_do_suspend(struct drm_device *dev, bool runtime) return 0; fail_client: - list_for_each_entry_continue_reverse(cli, &drm->clients, head) { - nvif_client_resume(&cli->base); - } - if (drm->fence && nouveau_fence(drm)->resume) nouveau_fence(drm)->resume(drm); @@ -640,19 +634,14 @@ static int nouveau_do_resume(struct drm_device *dev, bool runtime) { struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_cli *cli; - NV_INFO(drm, "resuming kernel object tree...\n"); + NV_INFO(drm, "resuming object tree...\n"); nvif_client_resume(&drm->client.base); - NV_INFO(drm, "resuming client object trees...\n"); + NV_INFO(drm, "resuming fence...\n"); if (drm->fence && nouveau_fence(drm)->resume) nouveau_fence(drm)->resume(drm); - list_for_each_entry(cli, &drm->clients, head) { - nvif_client_resume(&cli->base); - } - nouveau_run_vbios_init(dev); if (dev->mode_config.num_crtc) { -- cgit v1.1 From 1167c6bc51880cb74a3b1a02286fc25392684281 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 18 May 2016 13:57:42 +1000 Subject: drm/nouveau: allocate device object for every client Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv04/arb.c | 6 +-- drivers/gpu/drm/nouveau/dispnv04/crtc.c | 38 +++++++------- drivers/gpu/drm/nouveau/dispnv04/cursor.c | 2 +- drivers/gpu/drm/nouveau/dispnv04/dac.c | 18 +++---- drivers/gpu/drm/nouveau/dispnv04/dfp.c | 12 ++--- drivers/gpu/drm/nouveau/dispnv04/disp.c | 6 +-- drivers/gpu/drm/nouveau/dispnv04/disp.h | 6 +-- drivers/gpu/drm/nouveau/dispnv04/hw.c | 80 ++++++++++++++--------------- drivers/gpu/drm/nouveau/dispnv04/hw.h | 42 +++++++-------- drivers/gpu/drm/nouveau/dispnv04/overlay.c | 16 +++--- drivers/gpu/drm/nouveau/dispnv04/tvnv04.c | 4 +- drivers/gpu/drm/nouveau/dispnv04/tvnv17.c | 16 +++--- drivers/gpu/drm/nouveau/dispnv04/tvnv17.h | 4 +- drivers/gpu/drm/nouveau/nouveau_abi16.c | 4 +- drivers/gpu/drm/nouveau/nouveau_backlight.c | 24 ++++----- drivers/gpu/drm/nouveau/nouveau_bios.c | 18 +++---- drivers/gpu/drm/nouveau/nouveau_bo.c | 52 +++++++++---------- drivers/gpu/drm/nouveau/nouveau_connector.c | 18 +++---- drivers/gpu/drm/nouveau/nouveau_debugfs.c | 5 +- drivers/gpu/drm/nouveau/nouveau_display.c | 14 ++--- drivers/gpu/drm/nouveau/nouveau_drm.c | 59 +++++++++++---------- drivers/gpu/drm/nouveau/nouveau_drv.h | 3 +- drivers/gpu/drm/nouveau/nouveau_fbcon.c | 16 +++--- drivers/gpu/drm/nouveau/nouveau_gem.c | 10 ++-- drivers/gpu/drm/nouveau/nouveau_hwmon.c | 66 ++++++++++++------------ drivers/gpu/drm/nouveau/nouveau_led.c | 6 +-- drivers/gpu/drm/nouveau/nouveau_sgdma.c | 2 +- drivers/gpu/drm/nouveau/nouveau_ttm.c | 28 +++++----- drivers/gpu/drm/nouveau/nouveau_vga.c | 8 +-- drivers/gpu/drm/nouveau/nv04_fbcon.c | 2 +- drivers/gpu/drm/nouveau/nv50_display.c | 26 +++++----- drivers/gpu/drm/nouveau/nv84_fence.c | 4 +- 32 files changed, 310 insertions(+), 305 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/dispnv04/arb.c b/drivers/gpu/drm/nouveau/dispnv04/arb.c index a555681..90075b6 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/arb.c +++ b/drivers/gpu/drm/nouveau/dispnv04/arb.c @@ -198,7 +198,7 @@ nv04_update_arb(struct drm_device *dev, int VClk, int bpp, int *burst, int *lwm) { struct nouveau_drm *drm = nouveau_drm(dev); - struct nvif_object *device = &nouveau_drm(dev)->device.object; + struct nvif_object *device = &nouveau_drm(dev)->client.device.object; struct nv_fifo_info fifo_data; struct nv_sim_state sim_data; int MClk = nouveau_hw_get_clock(dev, PLL_MEMORY); @@ -227,7 +227,7 @@ nv04_update_arb(struct drm_device *dev, int VClk, int bpp, sim_data.mem_page_miss = ((cfg1 >> 4) & 0xf) + ((cfg1 >> 31) & 0x1); } - if (drm->device.info.family == NV_DEVICE_INFO_V0_TNT) + if (drm->client.device.info.family == NV_DEVICE_INFO_V0_TNT) nv04_calc_arb(&fifo_data, &sim_data); else nv10_calc_arb(&fifo_data, &sim_data); @@ -254,7 +254,7 @@ nouveau_calc_arb(struct drm_device *dev, int vclk, int bpp, int *burst, int *lwm { struct nouveau_drm *drm = nouveau_drm(dev); - if (drm->device.info.family < NV_DEVICE_INFO_V0_KELVIN) + if (drm->client.device.info.family < NV_DEVICE_INFO_V0_KELVIN) nv04_update_arb(dev, vclk, bpp, burst, lwm); else if ((dev->pdev->device & 0xfff0) == 0x0240 /*CHIPSET_C51*/ || (dev->pdev->device & 0xfff0) == 0x03d0 /*CHIPSET_C512*/) { diff --git a/drivers/gpu/drm/nouveau/dispnv04/crtc.c b/drivers/gpu/drm/nouveau/dispnv04/crtc.c index eb86f69..ab7b69c 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/crtc.c +++ b/drivers/gpu/drm/nouveau/dispnv04/crtc.c @@ -113,8 +113,8 @@ static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mod { struct drm_device *dev = crtc->dev; struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_bios *bios = nvxx_bios(&drm->device); - struct nvkm_clk *clk = nvxx_clk(&drm->device); + struct nvkm_bios *bios = nvxx_bios(&drm->client.device); + struct nvkm_clk *clk = nvxx_clk(&drm->client.device); struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index]; @@ -138,7 +138,7 @@ static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mod * has yet been observed in allowing the use a single stage pll on all * nv43 however. the behaviour of single stage use is untested on nv40 */ - if (drm->device.info.chipset > 0x40 && dot_clock <= (pll_lim.vco1.max_freq / 2)) + if (drm->client.device.info.chipset > 0x40 && dot_clock <= (pll_lim.vco1.max_freq / 2)) memset(&pll_lim.vco2, 0, sizeof(pll_lim.vco2)); @@ -148,10 +148,10 @@ static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mod state->pllsel &= PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK; /* The blob uses this always, so let's do the same */ - if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) + if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_USE_VPLL2_TRUE; /* again nv40 and some nv43 act more like nv3x as described above */ - if (drm->device.info.chipset < 0x41) + if (drm->client.device.info.chipset < 0x41) state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_MPLL | NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_NVPLL; state->pllsel |= nv_crtc->index ? PLLSEL_VPLL2_MASK : PLLSEL_VPLL1_MASK; @@ -270,7 +270,7 @@ nv_crtc_mode_set_vga(struct drm_crtc *crtc, struct drm_display_mode *mode) horizEnd = horizTotal - 2; horizBlankEnd = horizTotal + 4; #if 0 - if (dev->overlayAdaptor && drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) + if (dev->overlayAdaptor && drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) /* This reportedly works around some video overlay bandwidth problems */ horizTotal += 2; #endif @@ -505,7 +505,7 @@ nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode) regp->cursor_cfg = NV_PCRTC_CURSOR_CONFIG_CUR_LINES_64 | NV_PCRTC_CURSOR_CONFIG_CUR_PIXELS_64 | NV_PCRTC_CURSOR_CONFIG_ADDRESS_SPACE_PNVM; - if (drm->device.info.chipset >= 0x11) + if (drm->client.device.info.chipset >= 0x11) regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_CUR_BPP_32; if (mode->flags & DRM_MODE_FLAG_DBLSCAN) regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_DOUBLE_SCAN_ENABLE; @@ -546,26 +546,26 @@ nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode) * 1 << 30 on 0x60.830), for no apparent reason */ regp->CRTC[NV_CIO_CRE_59] = off_chip_digital; - if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE) + if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) regp->CRTC[0x9f] = off_chip_digital ? 0x11 : 0x1; regp->crtc_830 = mode->crtc_vdisplay - 3; regp->crtc_834 = mode->crtc_vdisplay - 1; - if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) + if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) /* This is what the blob does */ regp->crtc_850 = NVReadCRTC(dev, 0, NV_PCRTC_850); - if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE) + if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) regp->gpio_ext = NVReadCRTC(dev, 0, NV_PCRTC_GPIO_EXT); - if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) + if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) regp->crtc_cfg = NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC; else regp->crtc_cfg = NV04_PCRTC_CONFIG_START_ADDRESS_HSYNC; /* Some misc regs */ - if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) { + if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) { regp->CRTC[NV_CIO_CRE_85] = 0xFF; regp->CRTC[NV_CIO_CRE_86] = 0x1; } @@ -577,7 +577,7 @@ nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode) /* Generic PRAMDAC regs */ - if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) + if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) /* Only bit that bios and blob set. */ regp->nv10_cursync = (1 << 25); @@ -586,7 +586,7 @@ nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode) NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON; if (fb->format->depth == 16) regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; - if (drm->device.info.chipset >= 0x11) + if (drm->client.device.info.chipset >= 0x11) regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG; regp->ramdac_630 = 0; /* turn off green mode (tv test pattern?) */ @@ -649,7 +649,7 @@ nv_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode, nv_crtc_mode_set_vga(crtc, adjusted_mode); /* calculated in nv04_dfp_prepare, nv40 needs it written before calculating PLLs */ - if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) + if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk); nv_crtc_mode_set_regs(crtc, adjusted_mode); nv_crtc_calc_state_ext(crtc, mode, adjusted_mode->clock); @@ -710,7 +710,7 @@ static void nv_crtc_prepare(struct drm_crtc *crtc) /* Some more preparation. */ NVWriteCRTC(dev, nv_crtc->index, NV_PCRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA); - if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) { + if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) { uint32_t reg900 = NVReadRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900); NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900, reg900 & ~0x10000); } @@ -886,7 +886,7 @@ nv04_crtc_do_mode_set_base(struct drm_crtc *crtc, crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FF_INDEX); crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FFLWM__INDEX); - if (drm->device.info.family >= NV_DEVICE_INFO_V0_KELVIN) { + if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_KELVIN) { regp->CRTC[NV_CIO_CRE_47] = arb_lwm >> 8; crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_47); } @@ -967,7 +967,7 @@ static void nv11_cursor_upload(struct drm_device *dev, struct nouveau_bo *src, { struct nouveau_drm *drm = nouveau_drm(dev); - if (drm->device.info.chipset == 0x11) { + if (drm->client.device.info.chipset == 0x11) { pixel = ((pixel & 0x000000ff) << 24) | ((pixel & 0x0000ff00) << 8) | ((pixel & 0x00ff0000) >> 8) | @@ -1008,7 +1008,7 @@ nv04_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv, if (ret) goto out; - if (drm->device.info.chipset >= 0x11) + if (drm->client.device.info.chipset >= 0x11) nv11_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo); else nv04_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo); diff --git a/drivers/gpu/drm/nouveau/dispnv04/cursor.c b/drivers/gpu/drm/nouveau/dispnv04/cursor.c index c83116a..f26e44e 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/cursor.c +++ b/drivers/gpu/drm/nouveau/dispnv04/cursor.c @@ -55,7 +55,7 @@ nv04_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset) crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX); crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); - if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) + if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) nv_fix_nv40_hw_cursor(dev, nv_crtc->index); } diff --git a/drivers/gpu/drm/nouveau/dispnv04/dac.c b/drivers/gpu/drm/nouveau/dispnv04/dac.c index b6cc776..4feab0a 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/dac.c +++ b/drivers/gpu/drm/nouveau/dispnv04/dac.c @@ -66,7 +66,7 @@ int nv04_dac_output_offset(struct drm_encoder *encoder) static int sample_load_twice(struct drm_device *dev, bool sense[2]) { struct nouveau_drm *drm = nouveau_drm(dev); - struct nvif_object *device = &drm->device.object; + struct nvif_object *device = &drm->client.device.object; int i; for (i = 0; i < 2; i++) { @@ -80,19 +80,19 @@ static int sample_load_twice(struct drm_device *dev, bool sense[2]) * use a 10ms timeout (guards against crtc being inactive, in * which case blank state would never change) */ - if (nvif_msec(&drm->device, 10, + if (nvif_msec(&drm->client.device, 10, if (!(nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 1)) break; ) < 0) return -EBUSY; - if (nvif_msec(&drm->device, 10, + if (nvif_msec(&drm->client.device, 10, if ( (nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 1)) break; ) < 0) return -EBUSY; - if (nvif_msec(&drm->device, 10, + if (nvif_msec(&drm->client.device, 10, if (!(nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 1)) break; ) < 0) @@ -133,7 +133,7 @@ static enum drm_connector_status nv04_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) { struct drm_device *dev = encoder->dev; - struct nvif_object *device = &nouveau_drm(dev)->device.object; + struct nvif_object *device = &nouveau_drm(dev)->client.device.object; struct nouveau_drm *drm = nouveau_drm(dev); uint8_t saved_seq1, saved_pi, saved_rpc1, saved_cr_mode; uint8_t saved_palette0[3], saved_palette_mask; @@ -236,8 +236,8 @@ uint32_t nv17_dac_sample_load(struct drm_encoder *encoder) { struct drm_device *dev = encoder->dev; struct nouveau_drm *drm = nouveau_drm(dev); - struct nvif_object *device = &nouveau_drm(dev)->device.object; - struct nvkm_gpio *gpio = nvxx_gpio(&drm->device); + struct nvif_object *device = &nouveau_drm(dev)->client.device.object; + struct nvkm_gpio *gpio = nvxx_gpio(&drm->client.device); struct dcb_output *dcb = nouveau_encoder(encoder)->dcb; uint32_t sample, testval, regoffset = nv04_dac_output_offset(encoder); uint32_t saved_powerctrl_2 = 0, saved_powerctrl_4 = 0, saved_routput, @@ -288,7 +288,7 @@ uint32_t nv17_dac_sample_load(struct drm_encoder *encoder) /* nv driver and nv31 use 0xfffffeee, nv34 and 6600 use 0xfffffece */ routput = (saved_routput & 0xfffffece) | head << 8; - if (drm->device.info.family >= NV_DEVICE_INFO_V0_CURIE) { + if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CURIE) { if (dcb->type == DCB_OUTPUT_TV) routput |= 0x1a << 16; else @@ -403,7 +403,7 @@ static void nv04_dac_mode_set(struct drm_encoder *encoder, } /* This could use refinement for flatpanels, but it should work this way */ - if (drm->device.info.chipset < 0x44) + if (drm->client.device.info.chipset < 0x44) NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0xf0000000); else NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0x00100000); diff --git a/drivers/gpu/drm/nouveau/dispnv04/dfp.c b/drivers/gpu/drm/nouveau/dispnv04/dfp.c index 2e5bb2a..9805d2c 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/dfp.c +++ b/drivers/gpu/drm/nouveau/dispnv04/dfp.c @@ -281,7 +281,7 @@ static void nv04_dfp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *adjusted_mode) { struct drm_device *dev = encoder->dev; - struct nvif_object *device = &nouveau_drm(dev)->device.object; + struct nvif_object *device = &nouveau_drm(dev)->client.device.object; struct nouveau_drm *drm = nouveau_drm(dev); struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; @@ -417,7 +417,7 @@ static void nv04_dfp_mode_set(struct drm_encoder *encoder, if ((nv_connector->dithering_mode == DITHERING_MODE_ON) || (nv_connector->dithering_mode == DITHERING_MODE_AUTO && fb->format->depth > connector->display_info.bpc * 3)) { - if (drm->device.info.chipset == 0x11) + if (drm->client.device.info.chipset == 0x11) regp->dither = savep->dither | 0x00010000; else { int i; @@ -428,7 +428,7 @@ static void nv04_dfp_mode_set(struct drm_encoder *encoder, } } } else { - if (drm->device.info.chipset != 0x11) { + if (drm->client.device.info.chipset != 0x11) { /* reset them */ int i; for (i = 0; i < 3; i++) { @@ -464,7 +464,7 @@ static void nv04_dfp_commit(struct drm_encoder *encoder) NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL); /* This could use refinement for flatpanels, but it should work this way */ - if (drm->device.info.chipset < 0x44) + if (drm->client.device.info.chipset < 0x44) NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0xf0000000); else NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0x00100000); @@ -486,7 +486,7 @@ static void nv04_dfp_update_backlight(struct drm_encoder *encoder, int mode) { #ifdef __powerpc__ struct drm_device *dev = encoder->dev; - struct nvif_object *device = &nouveau_drm(dev)->device.object; + struct nvif_object *device = &nouveau_drm(dev)->client.device.object; /* BIOS scripts usually take care of the backlight, thanks * Apple for your consistency. @@ -624,7 +624,7 @@ static void nv04_tmds_slave_init(struct drm_encoder *encoder) struct drm_device *dev = encoder->dev; struct dcb_output *dcb = nouveau_encoder(encoder)->dcb; struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_i2c *i2c = nvxx_i2c(&drm->device); + struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); struct nvkm_i2c_bus *bus = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_PRI); struct nvkm_i2c_bus_probe info[] = { { diff --git a/drivers/gpu/drm/nouveau/dispnv04/disp.c b/drivers/gpu/drm/nouveau/dispnv04/disp.c index 34c0f2f6..5b9d549 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/disp.c +++ b/drivers/gpu/drm/nouveau/dispnv04/disp.c @@ -35,7 +35,7 @@ int nv04_display_create(struct drm_device *dev) { struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_i2c *i2c = nvxx_i2c(&drm->device); + struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); struct dcb_table *dcb = &drm->vbios.dcb; struct drm_connector *connector, *ct; struct drm_encoder *encoder; @@ -48,7 +48,7 @@ nv04_display_create(struct drm_device *dev) if (!disp) return -ENOMEM; - nvif_object_map(&drm->device.object); + nvif_object_map(&drm->client.device.object); nouveau_display(dev)->priv = disp; nouveau_display(dev)->dtor = nv04_display_destroy; @@ -139,7 +139,7 @@ nv04_display_destroy(struct drm_device *dev) nouveau_display(dev)->priv = NULL; kfree(disp); - nvif_object_unmap(&drm->device.object); + nvif_object_unmap(&drm->client.device.object); } int diff --git a/drivers/gpu/drm/nouveau/dispnv04/disp.h b/drivers/gpu/drm/nouveau/dispnv04/disp.h index 7030307..bea4543 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/disp.h +++ b/drivers/gpu/drm/nouveau/dispnv04/disp.h @@ -129,7 +129,7 @@ nv_two_heads(struct drm_device *dev) struct nouveau_drm *drm = nouveau_drm(dev); const int impl = dev->pdev->device & 0x0ff0; - if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS && impl != 0x0100 && + if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS && impl != 0x0100 && impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) return true; @@ -148,7 +148,7 @@ nv_two_reg_pll(struct drm_device *dev) struct nouveau_drm *drm = nouveau_drm(dev); const int impl = dev->pdev->device & 0x0ff0; - if (impl == 0x0310 || impl == 0x0340 || drm->device.info.family >= NV_DEVICE_INFO_V0_CURIE) + if (impl == 0x0310 || impl == 0x0340 || drm->client.device.info.family >= NV_DEVICE_INFO_V0_CURIE) return true; return false; } @@ -170,7 +170,7 @@ nouveau_bios_run_init_table(struct drm_device *dev, u16 table, struct dcb_output *outp, int crtc) { struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_bios *bios = nvxx_bios(&drm->device); + struct nvkm_bios *bios = nvxx_bios(&drm->client.device); struct nvbios_init init = { .subdev = &bios->subdev, .bios = bios, diff --git a/drivers/gpu/drm/nouveau/dispnv04/hw.c b/drivers/gpu/drm/nouveau/dispnv04/hw.c index 74856a8..48ad4be 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/hw.c +++ b/drivers/gpu/drm/nouveau/dispnv04/hw.c @@ -89,7 +89,7 @@ NVSetOwner(struct drm_device *dev, int owner) if (owner == 1) owner *= 3; - if (drm->device.info.chipset == 0x11) { + if (drm->client.device.info.chipset == 0x11) { /* This might seem stupid, but the blob does it and * omitting it often locks the system up. */ @@ -100,7 +100,7 @@ NVSetOwner(struct drm_device *dev, int owner) /* CR44 is always changed on CRTC0 */ NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_44, owner); - if (drm->device.info.chipset == 0x11) { /* set me harder */ + if (drm->client.device.info.chipset == 0x11) { /* set me harder */ NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner); NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner); } @@ -149,7 +149,7 @@ nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1, pllvals->NM1 = pll1 & 0xffff; if (nv_two_reg_pll(dev) && pll2 & NV31_RAMDAC_ENABLE_VCO2) pllvals->NM2 = pll2 & 0xffff; - else if (drm->device.info.chipset == 0x30 || drm->device.info.chipset == 0x35) { + else if (drm->client.device.info.chipset == 0x30 || drm->client.device.info.chipset == 0x35) { pllvals->M1 &= 0xf; /* only 4 bits */ if (pll1 & NV30_RAMDAC_ENABLE_VCO2) { pllvals->M2 = (pll1 >> 4) & 0x7; @@ -165,8 +165,8 @@ nouveau_hw_get_pllvals(struct drm_device *dev, enum nvbios_pll_type plltype, struct nvkm_pll_vals *pllvals) { struct nouveau_drm *drm = nouveau_drm(dev); - struct nvif_object *device = &drm->device.object; - struct nvkm_bios *bios = nvxx_bios(&drm->device); + struct nvif_object *device = &drm->client.device.object; + struct nvkm_bios *bios = nvxx_bios(&drm->client.device); uint32_t reg1, pll1, pll2 = 0; struct nvbios_pll pll_lim; int ret; @@ -184,7 +184,7 @@ nouveau_hw_get_pllvals(struct drm_device *dev, enum nvbios_pll_type plltype, pll2 = nvif_rd32(device, reg2); } - if (drm->device.info.family == NV_DEVICE_INFO_V0_CELSIUS && reg1 >= NV_PRAMDAC_VPLL_COEFF) { + if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS && reg1 >= NV_PRAMDAC_VPLL_COEFF) { uint32_t ramdac580 = NVReadRAMDAC(dev, 0, NV_PRAMDAC_580); /* check whether vpll has been forced into single stage mode */ @@ -252,7 +252,7 @@ nouveau_hw_fix_bad_vpll(struct drm_device *dev, int head) */ struct nouveau_drm *drm = nouveau_drm(dev); - struct nvif_device *device = &drm->device; + struct nvif_device *device = &drm->client.device; struct nvkm_clk *clk = nvxx_clk(device); struct nvkm_bios *bios = nvxx_bios(device); struct nvbios_pll pll_lim; @@ -391,21 +391,21 @@ nv_save_state_ramdac(struct drm_device *dev, int head, struct nv04_crtc_reg *regp = &state->crtc_reg[head]; int i; - if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) + if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) regp->nv10_cursync = NVReadRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC); nouveau_hw_get_pllvals(dev, head ? PLL_VPLL1 : PLL_VPLL0, ®p->pllvals); state->pllsel = NVReadRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT); if (nv_two_heads(dev)) state->sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK); - if (drm->device.info.chipset == 0x11) + if (drm->client.device.info.chipset == 0x11) regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11); regp->ramdac_gen_ctrl = NVReadRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL); if (nv_gf4_disp_arch(dev)) regp->ramdac_630 = NVReadRAMDAC(dev, head, NV_PRAMDAC_630); - if (drm->device.info.chipset >= 0x30) + if (drm->client.device.info.chipset >= 0x30) regp->ramdac_634 = NVReadRAMDAC(dev, head, NV_PRAMDAC_634); regp->tv_setup = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP); @@ -447,7 +447,7 @@ nv_save_state_ramdac(struct drm_device *dev, int head, if (nv_gf4_disp_arch(dev)) regp->ramdac_8c0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_8C0); - if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) { + if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) { regp->ramdac_a20 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A20); regp->ramdac_a24 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A24); regp->ramdac_a34 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A34); @@ -463,26 +463,26 @@ nv_load_state_ramdac(struct drm_device *dev, int head, struct nv04_mode_state *state) { struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_clk *clk = nvxx_clk(&drm->device); + struct nvkm_clk *clk = nvxx_clk(&drm->client.device); struct nv04_crtc_reg *regp = &state->crtc_reg[head]; uint32_t pllreg = head ? NV_RAMDAC_VPLL2 : NV_PRAMDAC_VPLL_COEFF; int i; - if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) + if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) NVWriteRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync); clk->pll_prog(clk, pllreg, ®p->pllvals); NVWriteRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT, state->pllsel); if (nv_two_heads(dev)) NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, state->sel_clk); - if (drm->device.info.chipset == 0x11) + if (drm->client.device.info.chipset == 0x11) NVWriteRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11, regp->dither); NVWriteRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL, regp->ramdac_gen_ctrl); if (nv_gf4_disp_arch(dev)) NVWriteRAMDAC(dev, head, NV_PRAMDAC_630, regp->ramdac_630); - if (drm->device.info.chipset >= 0x30) + if (drm->client.device.info.chipset >= 0x30) NVWriteRAMDAC(dev, head, NV_PRAMDAC_634, regp->ramdac_634); NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP, regp->tv_setup); @@ -519,7 +519,7 @@ nv_load_state_ramdac(struct drm_device *dev, int head, if (nv_gf4_disp_arch(dev)) NVWriteRAMDAC(dev, head, NV_PRAMDAC_8C0, regp->ramdac_8c0); - if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) { + if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) { NVWriteRAMDAC(dev, head, NV_PRAMDAC_A20, regp->ramdac_a20); NVWriteRAMDAC(dev, head, NV_PRAMDAC_A24, regp->ramdac_a24); NVWriteRAMDAC(dev, head, NV_PRAMDAC_A34, regp->ramdac_a34); @@ -600,10 +600,10 @@ nv_save_state_ext(struct drm_device *dev, int head, rd_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX); rd_cio_state(dev, head, regp, NV_CIO_CRE_21); - if (drm->device.info.family >= NV_DEVICE_INFO_V0_KELVIN) + if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_KELVIN) rd_cio_state(dev, head, regp, NV_CIO_CRE_47); - if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE) + if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) rd_cio_state(dev, head, regp, 0x9f); rd_cio_state(dev, head, regp, NV_CIO_CRE_49); @@ -612,14 +612,14 @@ nv_save_state_ext(struct drm_device *dev, int head, rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); rd_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX); - if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { + if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { regp->crtc_830 = NVReadCRTC(dev, head, NV_PCRTC_830); regp->crtc_834 = NVReadCRTC(dev, head, NV_PCRTC_834); - if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE) + if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) regp->gpio_ext = NVReadCRTC(dev, head, NV_PCRTC_GPIO_EXT); - if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) + if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) regp->crtc_850 = NVReadCRTC(dev, head, NV_PCRTC_850); if (nv_two_heads(dev)) @@ -631,7 +631,7 @@ nv_save_state_ext(struct drm_device *dev, int head, rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX); rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX); - if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { + if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { rd_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX); rd_cio_state(dev, head, regp, NV_CIO_CRE_CSB); rd_cio_state(dev, head, regp, NV_CIO_CRE_4B); @@ -660,12 +660,12 @@ nv_load_state_ext(struct drm_device *dev, int head, struct nv04_mode_state *state) { struct nouveau_drm *drm = nouveau_drm(dev); - struct nvif_object *device = &drm->device.object; + struct nvif_object *device = &drm->client.device.object; struct nv04_crtc_reg *regp = &state->crtc_reg[head]; uint32_t reg900; int i; - if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { + if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { if (nv_two_heads(dev)) /* setting ENGINE_CTRL (EC) *must* come before * CIO_CRE_LCD, as writing CRE_LCD sets bits 16 & 17 in @@ -677,20 +677,20 @@ nv_load_state_ext(struct drm_device *dev, int head, nvif_wr32(device, NV_PVIDEO_INTR_EN, 0); nvif_wr32(device, NV_PVIDEO_OFFSET_BUFF(0), 0); nvif_wr32(device, NV_PVIDEO_OFFSET_BUFF(1), 0); - nvif_wr32(device, NV_PVIDEO_LIMIT(0), drm->device.info.ram_size - 1); - nvif_wr32(device, NV_PVIDEO_LIMIT(1), drm->device.info.ram_size - 1); - nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(0), drm->device.info.ram_size - 1); - nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(1), drm->device.info.ram_size - 1); + nvif_wr32(device, NV_PVIDEO_LIMIT(0), drm->client.device.info.ram_size - 1); + nvif_wr32(device, NV_PVIDEO_LIMIT(1), drm->client.device.info.ram_size - 1); + nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(0), drm->client.device.info.ram_size - 1); + nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(1), drm->client.device.info.ram_size - 1); nvif_wr32(device, NV_PBUS_POWERCTRL_2, 0); NVWriteCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG, regp->cursor_cfg); NVWriteCRTC(dev, head, NV_PCRTC_830, regp->crtc_830); NVWriteCRTC(dev, head, NV_PCRTC_834, regp->crtc_834); - if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE) + if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) NVWriteCRTC(dev, head, NV_PCRTC_GPIO_EXT, regp->gpio_ext); - if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) { + if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) { NVWriteCRTC(dev, head, NV_PCRTC_850, regp->crtc_850); reg900 = NVReadRAMDAC(dev, head, NV_PRAMDAC_900); @@ -713,23 +713,23 @@ nv_load_state_ext(struct drm_device *dev, int head, wr_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX); wr_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX); - if (drm->device.info.family >= NV_DEVICE_INFO_V0_KELVIN) + if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_KELVIN) wr_cio_state(dev, head, regp, NV_CIO_CRE_47); - if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE) + if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) wr_cio_state(dev, head, regp, 0x9f); wr_cio_state(dev, head, regp, NV_CIO_CRE_49); wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX); wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); - if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) + if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) nv_fix_nv40_hw_cursor(dev, head); wr_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX); wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX); wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX); - if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { + if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { wr_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX); wr_cio_state(dev, head, regp, NV_CIO_CRE_CSB); wr_cio_state(dev, head, regp, NV_CIO_CRE_4B); @@ -737,14 +737,14 @@ nv_load_state_ext(struct drm_device *dev, int head, } /* NV11 and NV20 stop at 0x52. */ if (nv_gf4_disp_arch(dev)) { - if (drm->device.info.family < NV_DEVICE_INFO_V0_KELVIN) { + if (drm->client.device.info.family < NV_DEVICE_INFO_V0_KELVIN) { /* Not waiting for vertical retrace before modifying CRE_53/CRE_54 causes lockups. */ - nvif_msec(&drm->device, 650, + nvif_msec(&drm->client.device, 650, if ( (nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 8)) break; ); - nvif_msec(&drm->device, 650, + nvif_msec(&drm->client.device, 650, if (!(nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 8)) break; ); @@ -770,7 +770,7 @@ static void nv_save_state_palette(struct drm_device *dev, int head, struct nv04_mode_state *state) { - struct nvif_object *device = &nouveau_drm(dev)->device.object; + struct nvif_object *device = &nouveau_drm(dev)->client.device.object; int head_offset = head * NV_PRMDIO_SIZE, i; nvif_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset, @@ -789,7 +789,7 @@ void nouveau_hw_load_state_palette(struct drm_device *dev, int head, struct nv04_mode_state *state) { - struct nvif_object *device = &nouveau_drm(dev)->device.object; + struct nvif_object *device = &nouveau_drm(dev)->client.device.object; int head_offset = head * NV_PRMDIO_SIZE, i; nvif_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset, @@ -809,7 +809,7 @@ void nouveau_hw_save_state(struct drm_device *dev, int head, { struct nouveau_drm *drm = nouveau_drm(dev); - if (drm->device.info.chipset == 0x11) + if (drm->client.device.info.chipset == 0x11) /* NB: no attempt is made to restore the bad pll later on */ nouveau_hw_fix_bad_vpll(dev, head); nv_save_state_ramdac(dev, head, state); diff --git a/drivers/gpu/drm/nouveau/dispnv04/hw.h b/drivers/gpu/drm/nouveau/dispnv04/hw.h index 3bded60..3a2be47 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/hw.h +++ b/drivers/gpu/drm/nouveau/dispnv04/hw.h @@ -60,7 +60,7 @@ extern void nouveau_calc_arb(struct drm_device *, int vclk, int bpp, static inline uint32_t NVReadCRTC(struct drm_device *dev, int head, uint32_t reg) { - struct nvif_object *device = &nouveau_drm(dev)->device.object; + struct nvif_object *device = &nouveau_drm(dev)->client.device.object; uint32_t val; if (head) reg += NV_PCRTC0_SIZE; @@ -71,7 +71,7 @@ static inline uint32_t NVReadCRTC(struct drm_device *dev, static inline void NVWriteCRTC(struct drm_device *dev, int head, uint32_t reg, uint32_t val) { - struct nvif_object *device = &nouveau_drm(dev)->device.object; + struct nvif_object *device = &nouveau_drm(dev)->client.device.object; if (head) reg += NV_PCRTC0_SIZE; nvif_wr32(device, reg, val); @@ -80,7 +80,7 @@ static inline void NVWriteCRTC(struct drm_device *dev, static inline uint32_t NVReadRAMDAC(struct drm_device *dev, int head, uint32_t reg) { - struct nvif_object *device = &nouveau_drm(dev)->device.object; + struct nvif_object *device = &nouveau_drm(dev)->client.device.object; uint32_t val; if (head) reg += NV_PRAMDAC0_SIZE; @@ -91,7 +91,7 @@ static inline uint32_t NVReadRAMDAC(struct drm_device *dev, static inline void NVWriteRAMDAC(struct drm_device *dev, int head, uint32_t reg, uint32_t val) { - struct nvif_object *device = &nouveau_drm(dev)->device.object; + struct nvif_object *device = &nouveau_drm(dev)->client.device.object; if (head) reg += NV_PRAMDAC0_SIZE; nvif_wr32(device, reg, val); @@ -120,7 +120,7 @@ static inline void nv_write_tmds(struct drm_device *dev, static inline void NVWriteVgaCrtc(struct drm_device *dev, int head, uint8_t index, uint8_t value) { - struct nvif_object *device = &nouveau_drm(dev)->device.object; + struct nvif_object *device = &nouveau_drm(dev)->client.device.object; nvif_wr08(device, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index); nvif_wr08(device, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE, value); } @@ -128,7 +128,7 @@ static inline void NVWriteVgaCrtc(struct drm_device *dev, static inline uint8_t NVReadVgaCrtc(struct drm_device *dev, int head, uint8_t index) { - struct nvif_object *device = &nouveau_drm(dev)->device.object; + struct nvif_object *device = &nouveau_drm(dev)->client.device.object; uint8_t val; nvif_wr08(device, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index); val = nvif_rd08(device, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE); @@ -165,13 +165,13 @@ static inline uint8_t NVReadVgaCrtc5758(struct drm_device *dev, int head, uint8_ static inline uint8_t NVReadPRMVIO(struct drm_device *dev, int head, uint32_t reg) { - struct nvif_object *device = &nouveau_drm(dev)->device.object; + struct nvif_object *device = &nouveau_drm(dev)->client.device.object; struct nouveau_drm *drm = nouveau_drm(dev); uint8_t val; /* Only NV4x have two pvio ranges; other twoHeads cards MUST call * NVSetOwner for the relevant head to be programmed */ - if (head && drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) + if (head && drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) reg += NV_PRMVIO_SIZE; val = nvif_rd08(device, reg); @@ -181,12 +181,12 @@ static inline uint8_t NVReadPRMVIO(struct drm_device *dev, static inline void NVWritePRMVIO(struct drm_device *dev, int head, uint32_t reg, uint8_t value) { - struct nvif_object *device = &nouveau_drm(dev)->device.object; + struct nvif_object *device = &nouveau_drm(dev)->client.device.object; struct nouveau_drm *drm = nouveau_drm(dev); /* Only NV4x have two pvio ranges; other twoHeads cards MUST call * NVSetOwner for the relevant head to be programmed */ - if (head && drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) + if (head && drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) reg += NV_PRMVIO_SIZE; nvif_wr08(device, reg, value); @@ -194,14 +194,14 @@ static inline void NVWritePRMVIO(struct drm_device *dev, static inline void NVSetEnablePalette(struct drm_device *dev, int head, bool enable) { - struct nvif_object *device = &nouveau_drm(dev)->device.object; + struct nvif_object *device = &nouveau_drm(dev)->client.device.object; nvif_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE); nvif_wr08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, enable ? 0 : 0x20); } static inline bool NVGetEnablePalette(struct drm_device *dev, int head) { - struct nvif_object *device = &nouveau_drm(dev)->device.object; + struct nvif_object *device = &nouveau_drm(dev)->client.device.object; nvif_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE); return !(nvif_rd08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE) & 0x20); } @@ -209,7 +209,7 @@ static inline bool NVGetEnablePalette(struct drm_device *dev, int head) static inline void NVWriteVgaAttr(struct drm_device *dev, int head, uint8_t index, uint8_t value) { - struct nvif_object *device = &nouveau_drm(dev)->device.object; + struct nvif_object *device = &nouveau_drm(dev)->client.device.object; if (NVGetEnablePalette(dev, head)) index &= ~0x20; else @@ -223,7 +223,7 @@ static inline void NVWriteVgaAttr(struct drm_device *dev, static inline uint8_t NVReadVgaAttr(struct drm_device *dev, int head, uint8_t index) { - struct nvif_object *device = &nouveau_drm(dev)->device.object; + struct nvif_object *device = &nouveau_drm(dev)->client.device.object; uint8_t val; if (NVGetEnablePalette(dev, head)) index &= ~0x20; @@ -259,10 +259,10 @@ static inline void NVVgaProtect(struct drm_device *dev, int head, bool protect) static inline bool nv_heads_tied(struct drm_device *dev) { - struct nvif_object *device = &nouveau_drm(dev)->device.object; + struct nvif_object *device = &nouveau_drm(dev)->client.device.object; struct nouveau_drm *drm = nouveau_drm(dev); - if (drm->device.info.chipset == 0x11) + if (drm->client.device.info.chipset == 0x11) return !!(nvif_rd32(device, NV_PBUS_DEBUG_1) & (1 << 28)); return NVReadVgaCrtc(dev, 0, NV_CIO_CRE_44) & 0x4; @@ -318,7 +318,7 @@ NVLockVgaCrtcs(struct drm_device *dev, bool lock) NVWriteVgaCrtc(dev, 0, NV_CIO_SR_LOCK_INDEX, lock ? NV_CIO_SR_LOCK_VALUE : NV_CIO_SR_UNLOCK_RW_VALUE); /* NV11 has independently lockable extended crtcs, except when tied */ - if (drm->device.info.chipset == 0x11 && !nv_heads_tied(dev)) + if (drm->client.device.info.chipset == 0x11 && !nv_heads_tied(dev)) NVWriteVgaCrtc(dev, 1, NV_CIO_SR_LOCK_INDEX, lock ? NV_CIO_SR_LOCK_VALUE : NV_CIO_SR_UNLOCK_RW_VALUE); @@ -335,7 +335,7 @@ static inline int nv_cursor_width(struct drm_device *dev) { struct nouveau_drm *drm = nouveau_drm(dev); - return drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS ? NV10_CURSOR_SIZE : NV04_CURSOR_SIZE; + return drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS ? NV10_CURSOR_SIZE : NV04_CURSOR_SIZE; } static inline void @@ -357,7 +357,7 @@ nv_set_crtc_base(struct drm_device *dev, int head, uint32_t offset) NVWriteCRTC(dev, head, NV_PCRTC_START, offset); - if (drm->device.info.family == NV_DEVICE_INFO_V0_TNT) { + if (drm->client.device.info.family == NV_DEVICE_INFO_V0_TNT) { /* * Hilarious, the 24th bit doesn't want to stick to * PCRTC_START... @@ -382,7 +382,7 @@ nv_show_cursor(struct drm_device *dev, int head, bool show) *curctl1 &= ~MASK(NV_CIO_CRE_HCUR_ADDR1_ENABLE); NVWriteVgaCrtc(dev, head, NV_CIO_CRE_HCUR_ADDR1_INDEX, *curctl1); - if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) + if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) nv_fix_nv40_hw_cursor(dev, head); } @@ -398,7 +398,7 @@ nv_pitch_align(struct drm_device *dev, uint32_t width, int bpp) bpp = 8; /* Alignment requirements taken from the Haiku driver */ - if (drm->device.info.family == NV_DEVICE_INFO_V0_TNT) + if (drm->client.device.info.family == NV_DEVICE_INFO_V0_TNT) mask = 128 / bpp - 1; else mask = 512 / bpp - 1; diff --git a/drivers/gpu/drm/nouveau/dispnv04/overlay.c b/drivers/gpu/drm/nouveau/dispnv04/overlay.c index 6275c27..5319f2a 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/overlay.c +++ b/drivers/gpu/drm/nouveau/dispnv04/overlay.c @@ -97,7 +97,7 @@ nv10_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, uint32_t src_w, uint32_t src_h) { struct nouveau_drm *drm = nouveau_drm(plane->dev); - struct nvif_object *dev = &drm->device.object; + struct nvif_object *dev = &drm->client.device.object; struct nouveau_plane *nv_plane = container_of(plane, struct nouveau_plane, base); struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb); @@ -119,7 +119,7 @@ nv10_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, if (format > 0xffff) return -ERANGE; - if (drm->device.info.chipset >= 0x30) { + if (drm->client.device.info.chipset >= 0x30) { if (crtc_w < (src_w >> 1) || crtc_h < (src_h >> 1)) return -ERANGE; } else { @@ -174,7 +174,7 @@ nv10_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, static int nv10_disable_plane(struct drm_plane *plane) { - struct nvif_object *dev = &nouveau_drm(plane->dev)->device.object; + struct nvif_object *dev = &nouveau_drm(plane->dev)->client.device.object; struct nouveau_plane *nv_plane = container_of(plane, struct nouveau_plane, base); @@ -198,7 +198,7 @@ nv_destroy_plane(struct drm_plane *plane) static void nv10_set_params(struct nouveau_plane *plane) { - struct nvif_object *dev = &nouveau_drm(plane->base.dev)->device.object; + struct nvif_object *dev = &nouveau_drm(plane->base.dev)->client.device.object; u32 luma = (plane->brightness - 512) << 16 | plane->contrast; u32 chroma = ((sin_mul(plane->hue, plane->saturation) & 0xffff) << 16) | (cos_mul(plane->hue, plane->saturation) & 0xffff); @@ -268,7 +268,7 @@ nv10_overlay_init(struct drm_device *device) if (!plane) return; - switch (drm->device.info.chipset) { + switch (drm->client.device.info.chipset) { case 0x10: case 0x11: case 0x15: @@ -347,7 +347,7 @@ nv04_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h) { - struct nvif_object *dev = &nouveau_drm(plane->dev)->device.object; + struct nvif_object *dev = &nouveau_drm(plane->dev)->client.device.object; struct nouveau_plane *nv_plane = container_of(plane, struct nouveau_plane, base); struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb); @@ -427,7 +427,7 @@ nv04_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, static int nv04_disable_plane(struct drm_plane *plane) { - struct nvif_object *dev = &nouveau_drm(plane->dev)->device.object; + struct nvif_object *dev = &nouveau_drm(plane->dev)->client.device.object; struct nouveau_plane *nv_plane = container_of(plane, struct nouveau_plane, base); @@ -495,7 +495,7 @@ err: void nouveau_overlay_init(struct drm_device *device) { - struct nvif_device *dev = &nouveau_drm(device)->device; + struct nvif_device *dev = &nouveau_drm(device)->client.device; if (dev->info.chipset < 0x10) nv04_overlay_init(device); else if (dev->info.chipset <= 0x40) diff --git a/drivers/gpu/drm/nouveau/dispnv04/tvnv04.c b/drivers/gpu/drm/nouveau/dispnv04/tvnv04.c index 477a8d0..0166435 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/tvnv04.c +++ b/drivers/gpu/drm/nouveau/dispnv04/tvnv04.c @@ -54,7 +54,7 @@ static struct nvkm_i2c_bus_probe nv04_tv_encoder_info[] = { int nv04_tv_identify(struct drm_device *dev, int i2c_index) { struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_i2c *i2c = nvxx_i2c(&drm->device); + struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); struct nvkm_i2c_bus *bus = nvkm_i2c_bus_find(i2c, i2c_index); if (bus) { return nvkm_i2c_bus_probe(bus, "TV encoder", @@ -206,7 +206,7 @@ nv04_tv_create(struct drm_connector *connector, struct dcb_output *entry) struct drm_encoder *encoder; struct drm_device *dev = connector->dev; struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_i2c *i2c = nvxx_i2c(&drm->device); + struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); struct nvkm_i2c_bus *bus = nvkm_i2c_bus_find(i2c, entry->i2c_index); int type, ret; diff --git a/drivers/gpu/drm/nouveau/dispnv04/tvnv17.c b/drivers/gpu/drm/nouveau/dispnv04/tvnv17.c index 434d1e2..6d99f11 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/tvnv17.c +++ b/drivers/gpu/drm/nouveau/dispnv04/tvnv17.c @@ -46,7 +46,7 @@ static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder) { struct drm_device *dev = encoder->dev; struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_gpio *gpio = nvxx_gpio(&drm->device); + struct nvkm_gpio *gpio = nvxx_gpio(&drm->client.device); uint32_t testval, regoffset = nv04_dac_output_offset(encoder); uint32_t gpio0, gpio1, fp_htotal, fp_hsync_start, fp_hsync_end, fp_control, test_ctrl, dacclk, ctv_14, ctv_1c, ctv_6c; @@ -130,7 +130,7 @@ static bool get_tv_detect_quirks(struct drm_device *dev, uint32_t *pin_mask) { struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_device *device = nvxx_device(&drm->device); + struct nvkm_device *device = nvxx_device(&drm->client.device); if (device->quirk && device->quirk->tv_pin_mask) { *pin_mask = device->quirk->tv_pin_mask; @@ -154,8 +154,8 @@ nv17_tv_detect(struct drm_encoder *encoder, struct drm_connector *connector) return connector_status_disconnected; if (reliable) { - if (drm->device.info.chipset == 0x42 || - drm->device.info.chipset == 0x43) + if (drm->client.device.info.chipset == 0x42 || + drm->client.device.info.chipset == 0x43) tv_enc->pin_mask = nv42_tv_sample_load(encoder) >> 28 & 0xe; else @@ -362,7 +362,7 @@ static void nv17_tv_dpms(struct drm_encoder *encoder, int mode) { struct drm_device *dev = encoder->dev; struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_gpio *gpio = nvxx_gpio(&drm->device); + struct nvkm_gpio *gpio = nvxx_gpio(&drm->client.device); struct nv17_tv_state *regs = &to_tv_enc(encoder)->state; struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); @@ -435,7 +435,7 @@ static void nv17_tv_prepare(struct drm_encoder *encoder) /* Set the DACCLK register */ dacclk = (NVReadRAMDAC(dev, 0, dacclk_off) & ~0x30) | 0x1; - if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) + if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) dacclk |= 0x1a << 16; if (tv_norm->kind == CTV_ENC_MODE) { @@ -492,7 +492,7 @@ static void nv17_tv_mode_set(struct drm_encoder *encoder, tv_regs->ptv_614 = 0x13; } - if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE) { + if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) { tv_regs->ptv_500 = 0xe8e0; tv_regs->ptv_504 = 0x1710; tv_regs->ptv_604 = 0x0; @@ -587,7 +587,7 @@ static void nv17_tv_commit(struct drm_encoder *encoder) nv17_tv_state_load(dev, &to_tv_enc(encoder)->state); /* This could use refinement for flatpanels, but it should work */ - if (drm->device.info.chipset < 0x44) + if (drm->client.device.info.chipset < 0x44) NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0xf0000000); diff --git a/drivers/gpu/drm/nouveau/dispnv04/tvnv17.h b/drivers/gpu/drm/nouveau/dispnv04/tvnv17.h index 1b07521c..29773b3 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/tvnv17.h +++ b/drivers/gpu/drm/nouveau/dispnv04/tvnv17.h @@ -130,13 +130,13 @@ void nv17_ctv_update_rescaler(struct drm_encoder *encoder); static inline void nv_write_ptv(struct drm_device *dev, uint32_t reg, uint32_t val) { - struct nvif_device *device = &nouveau_drm(dev)->device; + struct nvif_device *device = &nouveau_drm(dev)->client.device; nvif_wr32(&device->object, reg, val); } static inline uint32_t nv_read_ptv(struct drm_device *dev, uint32_t reg) { - struct nvif_device *device = &nouveau_drm(dev)->device; + struct nvif_device *device = &nouveau_drm(dev)->client.device; return nvif_rd32(&device->object, reg); } diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.c b/drivers/gpu/drm/nouveau/nouveau_abi16.c index 0232909..f98f800 100644 --- a/drivers/gpu/drm/nouveau/nouveau_abi16.c +++ b/drivers/gpu/drm/nouveau/nouveau_abi16.c @@ -87,7 +87,7 @@ nouveau_abi16_put(struct nouveau_abi16 *abi16, int ret) s32 nouveau_abi16_swclass(struct nouveau_drm *drm) { - switch (drm->device.info.family) { + switch (drm->client.device.info.family) { case NV_DEVICE_INFO_V0_TNT: return NVIF_CLASS_SW_NV04; case NV_DEVICE_INFO_V0_CELSIUS: @@ -175,7 +175,7 @@ nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS) { struct nouveau_cli *cli = nouveau_cli(file_priv); struct nouveau_drm *drm = nouveau_drm(dev); - struct nvif_device *device = &drm->device; + struct nvif_device *device = &drm->client.device; struct nvkm_gr *gr = nvxx_gr(device); struct drm_nouveau_getparam *getparam = data; diff --git a/drivers/gpu/drm/nouveau/nouveau_backlight.c b/drivers/gpu/drm/nouveau/nouveau_backlight.c index 8b1ca4a..380f340 100644 --- a/drivers/gpu/drm/nouveau/nouveau_backlight.c +++ b/drivers/gpu/drm/nouveau/nouveau_backlight.c @@ -65,7 +65,7 @@ static int nv40_get_intensity(struct backlight_device *bd) { struct nouveau_drm *drm = bl_get_data(bd); - struct nvif_object *device = &drm->device.object; + struct nvif_object *device = &drm->client.device.object; int val = (nvif_rd32(device, NV40_PMC_BACKLIGHT) & NV40_PMC_BACKLIGHT_MASK) >> 16; @@ -76,7 +76,7 @@ static int nv40_set_intensity(struct backlight_device *bd) { struct nouveau_drm *drm = bl_get_data(bd); - struct nvif_object *device = &drm->device.object; + struct nvif_object *device = &drm->client.device.object; int val = bd->props.brightness; int reg = nvif_rd32(device, NV40_PMC_BACKLIGHT); @@ -96,7 +96,7 @@ static int nv40_backlight_init(struct drm_connector *connector) { struct nouveau_drm *drm = nouveau_drm(connector->dev); - struct nvif_object *device = &drm->device.object; + struct nvif_object *device = &drm->client.device.object; struct backlight_properties props; struct backlight_device *bd; struct backlight_connector bl_connector; @@ -133,7 +133,7 @@ nv50_get_intensity(struct backlight_device *bd) { struct nouveau_encoder *nv_encoder = bl_get_data(bd); struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); - struct nvif_object *device = &drm->device.object; + struct nvif_object *device = &drm->client.device.object; int or = nv_encoder->or; u32 div = 1025; u32 val; @@ -148,7 +148,7 @@ nv50_set_intensity(struct backlight_device *bd) { struct nouveau_encoder *nv_encoder = bl_get_data(bd); struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); - struct nvif_object *device = &drm->device.object; + struct nvif_object *device = &drm->client.device.object; int or = nv_encoder->or; u32 div = 1025; u32 val = (bd->props.brightness * div) / 100; @@ -169,7 +169,7 @@ nva3_get_intensity(struct backlight_device *bd) { struct nouveau_encoder *nv_encoder = bl_get_data(bd); struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); - struct nvif_object *device = &drm->device.object; + struct nvif_object *device = &drm->client.device.object; int or = nv_encoder->or; u32 div, val; @@ -187,7 +187,7 @@ nva3_set_intensity(struct backlight_device *bd) { struct nouveau_encoder *nv_encoder = bl_get_data(bd); struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); - struct nvif_object *device = &drm->device.object; + struct nvif_object *device = &drm->client.device.object; int or = nv_encoder->or; u32 div, val; @@ -213,7 +213,7 @@ static int nv50_backlight_init(struct drm_connector *connector) { struct nouveau_drm *drm = nouveau_drm(connector->dev); - struct nvif_object *device = &drm->device.object; + struct nvif_object *device = &drm->client.device.object; struct nouveau_encoder *nv_encoder; struct backlight_properties props; struct backlight_device *bd; @@ -231,9 +231,9 @@ nv50_backlight_init(struct drm_connector *connector) if (!nvif_rd32(device, NV50_PDISP_SOR_PWM_CTL(nv_encoder->or))) return 0; - if (drm->device.info.chipset <= 0xa0 || - drm->device.info.chipset == 0xaa || - drm->device.info.chipset == 0xac) + if (drm->client.device.info.chipset <= 0xa0 || + drm->client.device.info.chipset == 0xaa || + drm->client.device.info.chipset == 0xac) ops = &nv50_bl_ops; else ops = &nva3_bl_ops; @@ -265,7 +265,7 @@ int nouveau_backlight_init(struct drm_device *dev) { struct nouveau_drm *drm = nouveau_drm(dev); - struct nvif_device *device = &drm->device; + struct nvif_device *device = &drm->client.device; struct drm_connector *connector; if (apple_gmux_present()) { diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c index 23ffe85..9a0772a 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bios.c +++ b/drivers/gpu/drm/nouveau/nouveau_bios.c @@ -215,7 +215,7 @@ int call_lvds_script(struct drm_device *dev, struct dcb_output *dcbent, int head */ struct nouveau_drm *drm = nouveau_drm(dev); - struct nvif_object *device = &drm->device.object; + struct nvif_object *device = &drm->client.device.object; struct nvbios *bios = &drm->vbios; uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer]; uint32_t sel_clk_binding, sel_clk; @@ -319,7 +319,7 @@ static int get_fp_strap(struct drm_device *dev, struct nvbios *bios) { struct nouveau_drm *drm = nouveau_drm(dev); - struct nvif_object *device = &drm->device.object; + struct nvif_object *device = &drm->client.device.object; /* * The fp strap is normally dictated by the "User Strap" in @@ -333,10 +333,10 @@ get_fp_strap(struct drm_device *dev, struct nvbios *bios) if (bios->major_version < 5 && bios->data[0x48] & 0x4) return NVReadVgaCrtc5758(dev, 0, 0xf) & 0xf; - if (drm->device.info.family >= NV_DEVICE_INFO_V0_MAXWELL) + if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_MAXWELL) return nvif_rd32(device, 0x001800) & 0x0000000f; else - if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) + if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) return (nvif_rd32(device, NV_PEXTDEV_BOOT_0) >> 24) & 0xf; else return (nvif_rd32(device, NV_PEXTDEV_BOOT_0) >> 16) & 0xf; @@ -638,7 +638,7 @@ int run_tmds_table(struct drm_device *dev, struct dcb_output *dcbent, int head, */ struct nouveau_drm *drm = nouveau_drm(dev); - struct nvif_object *device = &drm->device.object; + struct nvif_object *device = &drm->client.device.object; struct nvbios *bios = &drm->vbios; int cv = bios->chip_version; uint16_t clktable = 0, scriptptr; @@ -1255,7 +1255,7 @@ olddcb_table(struct drm_device *dev) struct nouveau_drm *drm = nouveau_drm(dev); u8 *dcb = NULL; - if (drm->device.info.family > NV_DEVICE_INFO_V0_TNT) + if (drm->client.device.info.family > NV_DEVICE_INFO_V0_TNT) dcb = ROMPTR(dev, drm->vbios.data[0x36]); if (!dcb) { NV_WARN(drm, "No DCB data found in VBIOS\n"); @@ -1918,7 +1918,7 @@ static int load_nv17_hwsq_ucode_entry(struct drm_device *dev, struct nvbios *bio */ struct nouveau_drm *drm = nouveau_drm(dev); - struct nvif_object *device = &drm->device.object; + struct nvif_object *device = &drm->client.device.object; uint8_t bytes_to_write; uint16_t hwsq_entry_offset; int i; @@ -2012,7 +2012,7 @@ uint8_t *nouveau_bios_embedded_edid(struct drm_device *dev) static bool NVInitVBIOS(struct drm_device *dev) { struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_bios *bios = nvxx_bios(&drm->device); + struct nvkm_bios *bios = nvxx_bios(&drm->client.device); struct nvbios *legacy = &drm->vbios; memset(legacy, 0, sizeof(struct nvbios)); @@ -2064,7 +2064,7 @@ nouveau_bios_posted(struct drm_device *dev) struct nouveau_drm *drm = nouveau_drm(dev); unsigned htotal; - if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) + if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) return true; htotal = NVReadVgaCrtc(dev, 0, 0x06); diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index 66c5085..1b8d61b 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -48,7 +48,7 @@ nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg, { struct nouveau_drm *drm = nouveau_drm(dev); int i = reg - drm->tile.reg; - struct nvkm_device *device = nvxx_device(&drm->device); + struct nvkm_device *device = nvxx_device(&drm->client.device); struct nvkm_fb *fb = device->fb; struct nvkm_fb_tile *tile = &fb->tile.region[i]; @@ -100,7 +100,7 @@ nv10_bo_set_tiling(struct drm_device *dev, u32 addr, u32 size, u32 pitch, u32 flags) { struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_fb *fb = nvxx_fb(&drm->device); + struct nvkm_fb *fb = nvxx_fb(&drm->client.device); struct nouveau_drm_tile *tile, *found = NULL; int i; @@ -144,7 +144,7 @@ nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags, int *align, int *size) { struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); - struct nvif_device *device = &drm->device; + struct nvif_device *device = &drm->client.device; if (device->info.family < NV_DEVICE_INFO_V0_TESLA) { if (nvbo->tile_mode) { @@ -210,7 +210,7 @@ nouveau_bo_new(struct nouveau_cli *cli, int size, int align, nvbo->bo.bdev = &drm->ttm.bdev; nvbo->cli = cli; - if (!nvxx_device(&drm->device)->func->cpu_coherent) + if (!nvxx_device(&drm->client.device)->func->cpu_coherent) nvbo->force_coherent = flags & TTM_PL_FLAG_UNCACHED; nvbo->page_shift = 12; @@ -256,10 +256,10 @@ static void set_placement_range(struct nouveau_bo *nvbo, uint32_t type) { struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); - u32 vram_pages = drm->device.info.ram_size >> PAGE_SHIFT; + u32 vram_pages = drm->client.device.info.ram_size >> PAGE_SHIFT; unsigned i, fpfn, lpfn; - if (drm->device.info.family == NV_DEVICE_INFO_V0_CELSIUS && + if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS && nvbo->tile_mode && (type & TTM_PL_FLAG_VRAM) && nvbo->bo.mem.num_pages < vram_pages / 4) { /* @@ -317,7 +317,7 @@ nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype, bool contig) if (ret) return ret; - if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA && + if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA && memtype == TTM_PL_FLAG_VRAM && contig) { if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG) { if (bo->mem.mem_type == TTM_PL_VRAM) { @@ -444,7 +444,7 @@ void nouveau_bo_sync_for_device(struct nouveau_bo *nvbo) { struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); - struct nvkm_device *device = nvxx_device(&drm->device); + struct nvkm_device *device = nvxx_device(&drm->client.device); struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm; int i; @@ -464,7 +464,7 @@ void nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo) { struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); - struct nvkm_device *device = nvxx_device(&drm->device); + struct nvkm_device *device = nvxx_device(&drm->client.device); struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm; int i; @@ -580,9 +580,9 @@ nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, TTM_PL_FLAG_WC; man->default_caching = TTM_PL_FLAG_WC; - if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) { + if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) { /* Some BARs do not support being ioremapped WC */ - if (nvxx_bar(&drm->device)->iomap_uncached) { + if (nvxx_bar(&drm->client.device)->iomap_uncached) { man->available_caching = TTM_PL_FLAG_UNCACHED; man->default_caching = TTM_PL_FLAG_UNCACHED; } @@ -595,7 +595,7 @@ nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, } break; case TTM_PL_TT: - if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) + if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) man->func = &nouveau_gart_manager; else if (!drm->agp.bridge) @@ -1034,7 +1034,7 @@ nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr, * old nvkm_mem node, these will get cleaned up after ttm has * destroyed the ttm_mem_reg */ - if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) { + if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) { ret = nouveau_bo_move_prep(drm, bo, new_mem); if (ret) return ret; @@ -1230,7 +1230,7 @@ nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem, if (new_mem->mem_type != TTM_PL_VRAM) return 0; - if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { + if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { *new_tile = nv10_bo_set_tiling(dev, offset, new_mem->size, nvbo->tile_mode, nvbo->tile_flags); @@ -1269,7 +1269,7 @@ nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr, if (nvbo->pin_refcnt) NV_WARN(drm, "Moving pinned object %p!\n", nvbo); - if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA) { + if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) { ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile); if (ret) return ret; @@ -1304,7 +1304,7 @@ nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr, ret = ttm_bo_move_memcpy(bo, intr, no_wait_gpu, new_mem); out: - if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA) { + if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) { if (ret) nouveau_bo_vm_cleanup(bo, NULL, &new_tile); else @@ -1328,7 +1328,7 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) { struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type]; struct nouveau_drm *drm = nouveau_bdev(bdev); - struct nvkm_device *device = nvxx_device(&drm->device); + struct nvkm_device *device = nvxx_device(&drm->client.device); struct nvkm_mem *node = mem->mm_node; int ret; @@ -1351,7 +1351,7 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) mem->bus.is_iomem = !drm->agp.cma; } #endif - if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA || !node->memtype) + if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA || !node->memtype) /* untiled */ break; /* fallthrough, tiled memory */ @@ -1359,10 +1359,10 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) mem->bus.offset = mem->start << PAGE_SHIFT; mem->bus.base = device->func->resource_addr(device, 1); mem->bus.is_iomem = true; - if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) { - struct nvkm_bar *bar = nvxx_bar(&drm->device); + if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) { + struct nvkm_bar *bar = nvxx_bar(&drm->client.device); int page_shift = 12; - if (drm->device.info.family >= NV_DEVICE_INFO_V0_FERMI) + if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_FERMI) page_shift = node->page_shift; ret = nvkm_bar_umap(bar, node->size << 12, page_shift, @@ -1397,7 +1397,7 @@ nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo) { struct nouveau_drm *drm = nouveau_bdev(bo->bdev); struct nouveau_bo *nvbo = nouveau_bo(bo); - struct nvkm_device *device = nvxx_device(&drm->device); + struct nvkm_device *device = nvxx_device(&drm->client.device); u32 mappable = device->func->resource_size(device, 1) >> PAGE_SHIFT; int i, ret; @@ -1405,7 +1405,7 @@ nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo) * nothing to do here. */ if (bo->mem.mem_type != TTM_PL_VRAM) { - if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA || + if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA || !nouveau_bo_tile_layout(nvbo)) return 0; @@ -1420,7 +1420,7 @@ nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo) } /* make sure bo is in mappable vram */ - if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA || + if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA || bo->mem.start + bo->mem.num_pages < mappable) return 0; @@ -1462,7 +1462,7 @@ nouveau_ttm_tt_populate(struct ttm_tt *ttm) } drm = nouveau_bdev(ttm->bdev); - device = nvxx_device(&drm->device); + device = nvxx_device(&drm->client.device); dev = drm->dev; pdev = device->dev; @@ -1519,7 +1519,7 @@ nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm) return; drm = nouveau_bdev(ttm->bdev); - device = nvxx_device(&drm->device); + device = nvxx_device(&drm->client.device); dev = drm->dev; pdev = device->dev; diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c index dc7dd2e..f5add64 100644 --- a/drivers/gpu/drm/nouveau/nouveau_connector.c +++ b/drivers/gpu/drm/nouveau/nouveau_connector.c @@ -419,7 +419,7 @@ nouveau_connector_ddc_detect(struct drm_connector *connector) struct drm_device *dev = connector->dev; struct nouveau_connector *nv_connector = nouveau_connector(connector); struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_gpio *gpio = nvxx_gpio(&drm->device); + struct nvkm_gpio *gpio = nvxx_gpio(&drm->client.device); struct nouveau_encoder *nv_encoder; struct drm_encoder *encoder; int i, panel = -ENODEV; @@ -521,7 +521,7 @@ nouveau_connector_set_encoder(struct drm_connector *connector, return; nv_connector->detected_encoder = nv_encoder; - if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) { + if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) { connector->interlace_allowed = true; connector->doublescan_allowed = true; } else @@ -531,8 +531,8 @@ nouveau_connector_set_encoder(struct drm_connector *connector, connector->interlace_allowed = false; } else { connector->doublescan_allowed = true; - if (drm->device.info.family == NV_DEVICE_INFO_V0_KELVIN || - (drm->device.info.family == NV_DEVICE_INFO_V0_CELSIUS && + if (drm->client.device.info.family == NV_DEVICE_INFO_V0_KELVIN || + (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS && (dev->pdev->device & 0x0ff0) != 0x0100 && (dev->pdev->device & 0x0ff0) != 0x0150)) /* HW is broken */ @@ -984,17 +984,17 @@ get_tmds_link_bandwidth(struct drm_connector *connector, bool hdmi) /* Note: these limits are conservative, some Fermi's * can do 297 MHz. Unclear how this can be determined. */ - if (drm->device.info.family >= NV_DEVICE_INFO_V0_KEPLER) + if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_KEPLER) return 297000; - if (drm->device.info.family >= NV_DEVICE_INFO_V0_FERMI) + if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_FERMI) return 225000; } if (dcb->location != DCB_LOC_ON_CHIP || - drm->device.info.chipset >= 0x46) + drm->client.device.info.chipset >= 0x46) return 165000; - else if (drm->device.info.chipset >= 0x40) + else if (drm->client.device.info.chipset >= 0x40) return 155000; - else if (drm->device.info.chipset >= 0x18) + else if (drm->client.device.info.chipset >= 0x18) return 135000; else return 112000; diff --git a/drivers/gpu/drm/nouveau/nouveau_debugfs.c b/drivers/gpu/drm/nouveau/nouveau_debugfs.c index 411c12c..fd64dfd 100644 --- a/drivers/gpu/drm/nouveau/nouveau_debugfs.c +++ b/drivers/gpu/drm/nouveau/nouveau_debugfs.c @@ -259,8 +259,9 @@ nouveau_debugfs_init(struct nouveau_drm *drm) if (!drm->debugfs) return -ENOMEM; - ret = nvif_object_init(&drm->device.object, 0, NVIF_CLASS_CONTROL, - NULL, 0, &drm->debugfs->ctrl); + ret = nvif_object_init(&drm->client.device.object, 0, + NVIF_CLASS_CONTROL, NULL, 0, + &drm->debugfs->ctrl); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c index cac940c..d614af8 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.c +++ b/drivers/gpu/drm/nouveau/nouveau_display.c @@ -495,7 +495,7 @@ int nouveau_display_create(struct drm_device *dev) { struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_device *device = nvxx_device(&drm->device); + struct nvkm_device *device = nvxx_device(&drm->client.device); struct nouveau_display *disp; int ret; @@ -512,15 +512,15 @@ nouveau_display_create(struct drm_device *dev) dev->mode_config.min_width = 0; dev->mode_config.min_height = 0; - if (drm->device.info.family < NV_DEVICE_INFO_V0_CELSIUS) { + if (drm->client.device.info.family < NV_DEVICE_INFO_V0_CELSIUS) { dev->mode_config.max_width = 2048; dev->mode_config.max_height = 2048; } else - if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA) { + if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) { dev->mode_config.max_width = 4096; dev->mode_config.max_height = 4096; } else - if (drm->device.info.family < NV_DEVICE_INFO_V0_FERMI) { + if (drm->client.device.info.family < NV_DEVICE_INFO_V0_FERMI) { dev->mode_config.max_width = 8192; dev->mode_config.max_height = 8192; } else { @@ -531,7 +531,7 @@ nouveau_display_create(struct drm_device *dev) dev->mode_config.preferred_depth = 24; dev->mode_config.prefer_shadow = 1; - if (drm->device.info.chipset < 0x11) + if (drm->client.device.info.chipset < 0x11) dev->mode_config.async_page_flip = false; else dev->mode_config.async_page_flip = true; @@ -558,7 +558,7 @@ nouveau_display_create(struct drm_device *dev) int i; for (i = 0, ret = -ENODEV; ret && i < ARRAY_SIZE(oclass); i++) { - ret = nvif_object_init(&drm->device.object, 0, + ret = nvif_object_init(&drm->client.device.object, 0, oclass[i], NULL, 0, &disp->disp); } @@ -1067,7 +1067,7 @@ nouveau_display_dumb_create(struct drm_file *file_priv, struct drm_device *dev, args->size = roundup(args->size, PAGE_SIZE); /* Use VRAM if there is any ; otherwise fallback to system memory */ - if (nouveau_drm(dev)->device.info.ram_size != 0) + if (nouveau_drm(dev)->client.device.info.ram_size != 0) domain = NOUVEAU_GEM_DOMAIN_VRAM; else domain = NOUVEAU_GEM_DOMAIN_GART; diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c index 1e30398..95529d1 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c @@ -116,6 +116,7 @@ nouveau_cli_fini(struct nouveau_cli *cli) { nvkm_vm_ref(NULL, &nvxx_client(&cli->base)->vm, NULL); usif_client_fini(cli); + nvif_device_fini(&cli->device); nvif_client_fini(&cli->base); } @@ -143,6 +144,16 @@ nouveau_cli_init(struct nouveau_drm *drm, const char *sname, goto done; } + ret = nvif_device_init(&cli->base.object, 0, NV_DEVICE, + &(struct nv_device_v0) { + .device = ~0, + }, sizeof(struct nv_device_v0), + &cli->device); + if (ret) { + NV_ERROR(drm, "Device allocation failed: %d\n", ret); + goto done; + } + done: if (ret) nouveau_cli_fini(cli); @@ -170,7 +181,7 @@ nouveau_accel_fini(struct nouveau_drm *drm) static void nouveau_accel_init(struct nouveau_drm *drm) { - struct nvif_device *device = &drm->device; + struct nvif_device *device = &drm->client.device; struct nvif_sclass *sclass; u32 arg0, arg1; int ret, i, n; @@ -224,7 +235,7 @@ nouveau_accel_init(struct nouveau_drm *drm) } if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) { - ret = nouveau_channel_new(drm, &drm->device, + ret = nouveau_channel_new(drm, &drm->client.device, NVA06F_V0_ENGINE_CE0 | NVA06F_V0_ENGINE_CE1, 0, &drm->cechan); @@ -237,7 +248,7 @@ nouveau_accel_init(struct nouveau_drm *drm) if (device->info.chipset >= 0xa3 && device->info.chipset != 0xaa && device->info.chipset != 0xac) { - ret = nouveau_channel_new(drm, &drm->device, + ret = nouveau_channel_new(drm, &drm->client.device, NvDmaFB, NvDmaTT, &drm->cechan); if (ret) NV_ERROR(drm, "failed to create ce channel, %d\n", ret); @@ -249,7 +260,8 @@ nouveau_accel_init(struct nouveau_drm *drm) arg1 = NvDmaTT; } - ret = nouveau_channel_new(drm, &drm->device, arg0, arg1, &drm->channel); + ret = nouveau_channel_new(drm, &drm->client.device, + arg0, arg1, &drm->channel); if (ret) { NV_ERROR(drm, "failed to create kernel channel, %d\n", ret); nouveau_accel_fini(drm); @@ -289,8 +301,8 @@ nouveau_accel_init(struct nouveau_drm *drm) } if (device->info.family < NV_DEVICE_INFO_V0_FERMI) { - ret = nvkm_gpuobj_new(nvxx_device(&drm->device), 32, 0, false, - NULL, &drm->notify); + ret = nvkm_gpuobj_new(nvxx_device(&drm->client.device), 32, 0, + false, NULL, &drm->notify); if (ret) { NV_ERROR(drm, "failed to allocate notifier, %d\n", ret); nouveau_accel_fini(drm); @@ -425,6 +437,8 @@ nouveau_drm_load(struct drm_device *dev, unsigned long flags) if (ret) return ret; + dev->irq_enabled = true; + nvxx_client(&drm->client.base)->debug = nvkm_dbgopt(nouveau_debug, "DRM"); @@ -433,33 +447,24 @@ nouveau_drm_load(struct drm_device *dev, unsigned long flags) nouveau_get_hdmi_dev(drm); - ret = nvif_device_init(&drm->client.base.object, 0, NV_DEVICE, - &(struct nv_device_v0) { - .device = ~0, - }, sizeof(struct nv_device_v0), - &drm->device); - if (ret) - goto fail_device; - - dev->irq_enabled = true; - /* workaround an odd issue on nvc1 by disabling the device's * nosnoop capability. hopefully won't cause issues until a * better fix is found - assuming there is one... */ - if (drm->device.info.chipset == 0xc1) - nvif_mask(&drm->device.object, 0x00088080, 0x00000800, 0x00000000); + if (drm->client.device.info.chipset == 0xc1) + nvif_mask(&drm->client.device.object, 0x00088080, 0x00000800, 0x00000000); nouveau_vga_init(drm); - if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) { - if (!nvxx_device(&drm->device)->mmu) { + if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) { + if (!nvxx_device(&drm->client.device)->mmu) { ret = -ENOSYS; goto fail_device; } - ret = nvkm_vm_new(nvxx_device(&drm->device), 0, (1ULL << 40), - 0x1000, NULL, &drm->client.vm); + ret = nvkm_vm_new(nvxx_device(&drm->client.device), + 0, (1ULL << 40), 0x1000, NULL, + &drm->client.vm); if (ret) goto fail_device; @@ -509,7 +514,6 @@ fail_bios: fail_ttm: nouveau_vga_fini(drm); fail_device: - nvif_device_fini(&drm->device); nouveau_cli_fini(&drm->client); kfree(drm); return ret; @@ -540,7 +544,6 @@ nouveau_drm_unload(struct drm_device *dev) nouveau_ttm_fini(drm); nouveau_vga_fini(drm); - nvif_device_fini(&drm->device); if (drm->hdmi_device) pci_dev_put(drm->hdmi_device); nouveau_cli_fini(&drm->client); @@ -756,7 +759,7 @@ nouveau_pmops_runtime_resume(struct device *dev) { struct pci_dev *pdev = to_pci_dev(dev); struct drm_device *drm_dev = pci_get_drvdata(pdev); - struct nvif_device *device = &nouveau_drm(drm_dev)->device; + struct nvif_device *device = &nouveau_drm(drm_dev)->client.device; int ret; if (nouveau_runtime_pm == 0) @@ -848,9 +851,9 @@ nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv) cli->base.super = false; - if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) { - ret = nvkm_vm_new(nvxx_device(&drm->device), 0, (1ULL << 40), - 0x1000, NULL, &cli->vm); + if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) { + ret = nvkm_vm_new(nvxx_device(&drm->client.device), 0, + (1ULL << 40), 0x1000, NULL, &cli->vm); if (ret) goto done; diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h index ac36bef..92c8b20 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/drivers/gpu/drm/nouveau/nouveau_drv.h @@ -89,6 +89,8 @@ struct nouveau_cli { struct drm_device *dev; struct mutex mutex; + struct nvif_device device; + struct nvkm_vm *vm; /*XXX*/ struct list_head head; void *abi16; @@ -112,7 +114,6 @@ struct nouveau_drm { struct nouveau_cli client; struct drm_device *dev; - struct nvif_device device; struct list_head clients; struct { diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c index 8132372..9131295 100644 --- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c +++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c @@ -60,7 +60,7 @@ nouveau_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect) { struct nouveau_fbdev *fbcon = info->par; struct nouveau_drm *drm = nouveau_drm(fbcon->helper.dev); - struct nvif_device *device = &drm->device; + struct nvif_device *device = &drm->client.device; int ret; if (info->state != FBINFO_STATE_RUNNING) @@ -92,7 +92,7 @@ nouveau_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *image) { struct nouveau_fbdev *fbcon = info->par; struct nouveau_drm *drm = nouveau_drm(fbcon->helper.dev); - struct nvif_device *device = &drm->device; + struct nvif_device *device = &drm->client.device; int ret; if (info->state != FBINFO_STATE_RUNNING) @@ -124,7 +124,7 @@ nouveau_fbcon_imageblit(struct fb_info *info, const struct fb_image *image) { struct nouveau_fbdev *fbcon = info->par; struct nouveau_drm *drm = nouveau_drm(fbcon->helper.dev); - struct nvif_device *device = &drm->device; + struct nvif_device *device = &drm->client.device; int ret; if (info->state != FBINFO_STATE_RUNNING) @@ -266,10 +266,10 @@ nouveau_fbcon_accel_init(struct drm_device *dev) struct fb_info *info = fbcon->helper.fbdev; int ret; - if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA) + if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) ret = nv04_fbcon_accel_init(info); else - if (drm->device.info.family < NV_DEVICE_INFO_V0_FERMI) + if (drm->client.device.info.family < NV_DEVICE_INFO_V0_FERMI) ret = nv50_fbcon_accel_init(info); else ret = nvc0_fbcon_accel_init(info); @@ -324,7 +324,7 @@ nouveau_fbcon_create(struct drm_fb_helper *helper, container_of(helper, struct nouveau_fbdev, helper); struct drm_device *dev = fbcon->helper.dev; struct nouveau_drm *drm = nouveau_drm(dev); - struct nvif_device *device = &drm->device; + struct nvif_device *device = &drm->client.device; struct fb_info *info; struct nouveau_framebuffer *fb; struct nouveau_channel *chan; @@ -516,10 +516,10 @@ nouveau_fbcon_init(struct drm_device *dev) if (ret) goto fini; - if (drm->device.info.ram_size <= 32 * 1024 * 1024) + if (drm->client.device.info.ram_size <= 32 * 1024 * 1024) preferred_bpp = 8; else - if (drm->device.info.ram_size <= 64 * 1024 * 1024) + if (drm->client.device.info.ram_size <= 64 * 1024 * 1024) preferred_bpp = 16; else preferred_bpp = 32; diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c index 4ff2d2c..b334c4a 100644 --- a/drivers/gpu/drm/nouveau/nouveau_gem.c +++ b/drivers/gpu/drm/nouveau/nouveau_gem.c @@ -206,7 +206,7 @@ nouveau_gem_new(struct nouveau_cli *cli, int size, int align, uint32_t domain, */ nvbo->valid_domains = NOUVEAU_GEM_DOMAIN_VRAM | NOUVEAU_GEM_DOMAIN_GART; - if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) + if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) nvbo->valid_domains &= domain; /* Initialize the embedded gem-object. We return a single gem-reference @@ -257,7 +257,7 @@ nouveau_gem_ioctl_new(struct drm_device *dev, void *data, { struct nouveau_drm *drm = nouveau_drm(dev); struct nouveau_cli *cli = nouveau_cli(file_priv); - struct nvkm_fb *fb = nvxx_fb(&drm->device); + struct nvkm_fb *fb = nvxx_fb(&drm->client.device); struct drm_nouveau_gem_new *req = data; struct nouveau_bo *nvbo = NULL; int ret = 0; @@ -496,7 +496,7 @@ validate_list(struct nouveau_channel *chan, struct nouveau_cli *cli, return ret; } - if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA) { + if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) { if (nvbo->bo.offset == b->presumed.offset && ((nvbo->bo.mem.mem_type == TTM_PL_VRAM && b->presumed.domain & NOUVEAU_GEM_DOMAIN_VRAM) || @@ -767,7 +767,7 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data, push[i].length); } } else - if (drm->device.info.chipset >= 0x25) { + if (drm->client.device.info.chipset >= 0x25) { ret = RING_SPACE(chan, req->nr_push * 2); if (ret) { NV_PRINTK(err, cli, "cal_space: %d\n", ret); @@ -840,7 +840,7 @@ out_next: req->suffix0 = 0x00000000; req->suffix1 = 0x00000000; } else - if (drm->device.info.chipset >= 0x25) { + if (drm->client.device.info.chipset >= 0x25) { req->suffix0 = 0x00020000; req->suffix1 = 0x00000000; } else { diff --git a/drivers/gpu/drm/nouveau/nouveau_hwmon.c b/drivers/gpu/drm/nouveau/nouveau_hwmon.c index 71f764b..d762b8a 100644 --- a/drivers/gpu/drm/nouveau/nouveau_hwmon.c +++ b/drivers/gpu/drm/nouveau/nouveau_hwmon.c @@ -43,7 +43,7 @@ nouveau_hwmon_show_temp(struct device *d, struct device_attribute *a, char *buf) { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_therm *therm = nvxx_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->client.device); int temp = nvkm_therm_temp_get(therm); if (temp < 0) @@ -69,7 +69,7 @@ nouveau_hwmon_temp1_auto_point1_temp(struct device *d, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_therm *therm = nvxx_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->client.device); return snprintf(buf, PAGE_SIZE, "%d\n", therm->attr_get(therm, NVKM_THERM_ATTR_THRS_FAN_BOOST) * 1000); @@ -81,7 +81,7 @@ nouveau_hwmon_set_temp1_auto_point1_temp(struct device *d, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_therm *therm = nvxx_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->client.device); long value; if (kstrtol(buf, 10, &value) == -EINVAL) @@ -102,7 +102,7 @@ nouveau_hwmon_temp1_auto_point1_temp_hyst(struct device *d, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_therm *therm = nvxx_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->client.device); return snprintf(buf, PAGE_SIZE, "%d\n", therm->attr_get(therm, NVKM_THERM_ATTR_THRS_FAN_BOOST_HYST) * 1000); @@ -114,7 +114,7 @@ nouveau_hwmon_set_temp1_auto_point1_temp_hyst(struct device *d, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_therm *therm = nvxx_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->client.device); long value; if (kstrtol(buf, 10, &value) == -EINVAL) @@ -134,7 +134,7 @@ nouveau_hwmon_max_temp(struct device *d, struct device_attribute *a, char *buf) { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_therm *therm = nvxx_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->client.device); return snprintf(buf, PAGE_SIZE, "%d\n", therm->attr_get(therm, NVKM_THERM_ATTR_THRS_DOWN_CLK) * 1000); @@ -145,7 +145,7 @@ nouveau_hwmon_set_max_temp(struct device *d, struct device_attribute *a, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_therm *therm = nvxx_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->client.device); long value; if (kstrtol(buf, 10, &value) == -EINVAL) @@ -165,7 +165,7 @@ nouveau_hwmon_max_temp_hyst(struct device *d, struct device_attribute *a, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_therm *therm = nvxx_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->client.device); return snprintf(buf, PAGE_SIZE, "%d\n", therm->attr_get(therm, NVKM_THERM_ATTR_THRS_DOWN_CLK_HYST) * 1000); @@ -176,7 +176,7 @@ nouveau_hwmon_set_max_temp_hyst(struct device *d, struct device_attribute *a, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_therm *therm = nvxx_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->client.device); long value; if (kstrtol(buf, 10, &value) == -EINVAL) @@ -197,7 +197,7 @@ nouveau_hwmon_critical_temp(struct device *d, struct device_attribute *a, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_therm *therm = nvxx_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->client.device); return snprintf(buf, PAGE_SIZE, "%d\n", therm->attr_get(therm, NVKM_THERM_ATTR_THRS_CRITICAL) * 1000); @@ -209,7 +209,7 @@ nouveau_hwmon_set_critical_temp(struct device *d, struct device_attribute *a, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_therm *therm = nvxx_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->client.device); long value; if (kstrtol(buf, 10, &value) == -EINVAL) @@ -230,7 +230,7 @@ nouveau_hwmon_critical_temp_hyst(struct device *d, struct device_attribute *a, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_therm *therm = nvxx_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->client.device); return snprintf(buf, PAGE_SIZE, "%d\n", therm->attr_get(therm, NVKM_THERM_ATTR_THRS_CRITICAL_HYST) * 1000); @@ -243,7 +243,7 @@ nouveau_hwmon_set_critical_temp_hyst(struct device *d, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_therm *therm = nvxx_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->client.device); long value; if (kstrtol(buf, 10, &value) == -EINVAL) @@ -263,7 +263,7 @@ nouveau_hwmon_emergency_temp(struct device *d, struct device_attribute *a, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_therm *therm = nvxx_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->client.device); return snprintf(buf, PAGE_SIZE, "%d\n", therm->attr_get(therm, NVKM_THERM_ATTR_THRS_SHUTDOWN) * 1000); @@ -275,7 +275,7 @@ nouveau_hwmon_set_emergency_temp(struct device *d, struct device_attribute *a, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_therm *therm = nvxx_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->client.device); long value; if (kstrtol(buf, 10, &value) == -EINVAL) @@ -296,7 +296,7 @@ nouveau_hwmon_emergency_temp_hyst(struct device *d, struct device_attribute *a, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_therm *therm = nvxx_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->client.device); return snprintf(buf, PAGE_SIZE, "%d\n", therm->attr_get(therm, NVKM_THERM_ATTR_THRS_SHUTDOWN_HYST) * 1000); @@ -309,7 +309,7 @@ nouveau_hwmon_set_emergency_temp_hyst(struct device *d, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_therm *therm = nvxx_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->client.device); long value; if (kstrtol(buf, 10, &value) == -EINVAL) @@ -349,7 +349,7 @@ nouveau_hwmon_show_fan1_input(struct device *d, struct device_attribute *attr, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_therm *therm = nvxx_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->client.device); return snprintf(buf, PAGE_SIZE, "%d\n", nvkm_therm_fan_sense(therm)); } @@ -362,7 +362,7 @@ nouveau_hwmon_get_pwm1_enable(struct device *d, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_therm *therm = nvxx_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->client.device); int ret; ret = therm->attr_get(therm, NVKM_THERM_ATTR_FAN_MODE); @@ -378,7 +378,7 @@ nouveau_hwmon_set_pwm1_enable(struct device *d, struct device_attribute *a, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_therm *therm = nvxx_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->client.device); long value; int ret; @@ -401,7 +401,7 @@ nouveau_hwmon_get_pwm1(struct device *d, struct device_attribute *a, char *buf) { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_therm *therm = nvxx_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->client.device); int ret; ret = therm->fan_get(therm); @@ -417,7 +417,7 @@ nouveau_hwmon_set_pwm1(struct device *d, struct device_attribute *a, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_therm *therm = nvxx_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->client.device); int ret = -ENODEV; long value; @@ -441,7 +441,7 @@ nouveau_hwmon_get_pwm1_min(struct device *d, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_therm *therm = nvxx_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->client.device); int ret; ret = therm->attr_get(therm, NVKM_THERM_ATTR_FAN_MIN_DUTY); @@ -457,7 +457,7 @@ nouveau_hwmon_set_pwm1_min(struct device *d, struct device_attribute *a, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_therm *therm = nvxx_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->client.device); long value; int ret; @@ -481,7 +481,7 @@ nouveau_hwmon_get_pwm1_max(struct device *d, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_therm *therm = nvxx_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->client.device); int ret; ret = therm->attr_get(therm, NVKM_THERM_ATTR_FAN_MAX_DUTY); @@ -497,7 +497,7 @@ nouveau_hwmon_set_pwm1_max(struct device *d, struct device_attribute *a, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_therm *therm = nvxx_therm(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->client.device); long value; int ret; @@ -521,7 +521,7 @@ nouveau_hwmon_get_in0_input(struct device *d, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_volt *volt = nvxx_volt(&drm->device); + struct nvkm_volt *volt = nvxx_volt(&drm->client.device); int ret; ret = nvkm_volt_get(volt); @@ -540,7 +540,7 @@ nouveau_hwmon_get_in0_min(struct device *d, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_volt *volt = nvxx_volt(&drm->device); + struct nvkm_volt *volt = nvxx_volt(&drm->client.device); if (!volt || !volt->min_uv) return -ENODEV; @@ -557,7 +557,7 @@ nouveau_hwmon_get_in0_max(struct device *d, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_volt *volt = nvxx_volt(&drm->device); + struct nvkm_volt *volt = nvxx_volt(&drm->client.device); if (!volt || !volt->max_uv) return -ENODEV; @@ -584,7 +584,7 @@ nouveau_hwmon_get_power1_input(struct device *d, struct device_attribute *a, { struct drm_device *dev = dev_get_drvdata(d); struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_iccsense *iccsense = nvxx_iccsense(&drm->device); + struct nvkm_iccsense *iccsense = nvxx_iccsense(&drm->client.device); int result = nvkm_iccsense_read_all(iccsense); if (result < 0) @@ -664,9 +664,9 @@ nouveau_hwmon_init(struct drm_device *dev) { #if defined(CONFIG_HWMON) || (defined(MODULE) && defined(CONFIG_HWMON_MODULE)) struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_therm *therm = nvxx_therm(&drm->device); - struct nvkm_volt *volt = nvxx_volt(&drm->device); - struct nvkm_iccsense *iccsense = nvxx_iccsense(&drm->device); + struct nvkm_therm *therm = nvxx_therm(&drm->client.device); + struct nvkm_volt *volt = nvxx_volt(&drm->client.device); + struct nvkm_iccsense *iccsense = nvxx_iccsense(&drm->client.device); struct nouveau_hwmon *hwmon; struct device *hwmon_dev; int ret = 0; diff --git a/drivers/gpu/drm/nouveau/nouveau_led.c b/drivers/gpu/drm/nouveau/nouveau_led.c index 3e2f1b6..72456b1 100644 --- a/drivers/gpu/drm/nouveau/nouveau_led.c +++ b/drivers/gpu/drm/nouveau/nouveau_led.c @@ -38,7 +38,7 @@ nouveau_led_get_brightness(struct led_classdev *led) { struct drm_device *drm_dev = container_of(led, struct nouveau_led, led)->dev; struct nouveau_drm *drm = nouveau_drm(drm_dev); - struct nvif_object *device = &drm->device.object; + struct nvif_object *device = &drm->client.device.object; u32 div, duty; div = nvif_rd32(device, 0x61c880) & 0x00ffffff; @@ -55,7 +55,7 @@ nouveau_led_set_brightness(struct led_classdev *led, enum led_brightness value) { struct drm_device *drm_dev = container_of(led, struct nouveau_led, led)->dev; struct nouveau_drm *drm = nouveau_drm(drm_dev); - struct nvif_object *device = &drm->device.object; + struct nvif_object *device = &drm->client.device.object; u32 input_clk = 27e6; /* PDISPLAY.SOR[1].PWM is connected to the crystal */ u32 freq = 100; /* this is what nvidia uses and it should be good-enough */ @@ -78,7 +78,7 @@ int nouveau_led_init(struct drm_device *dev) { struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_gpio *gpio = nvxx_gpio(&drm->device); + struct nvkm_gpio *gpio = nvxx_gpio(&drm->client.device); struct dcb_gpio_func logo_led; int ret; diff --git a/drivers/gpu/drm/nouveau/nouveau_sgdma.c b/drivers/gpu/drm/nouveau/nouveau_sgdma.c index db35ab5..8da005b 100644 --- a/drivers/gpu/drm/nouveau/nouveau_sgdma.c +++ b/drivers/gpu/drm/nouveau/nouveau_sgdma.c @@ -100,7 +100,7 @@ nouveau_sgdma_create_ttm(struct ttm_bo_device *bdev, if (!nvbe) return NULL; - if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA) + if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) nvbe->ttm.ttm.func = &nv04_sgdma_backend; else nvbe->ttm.ttm.func = &nv50_sgdma_backend; diff --git a/drivers/gpu/drm/nouveau/nouveau_ttm.c b/drivers/gpu/drm/nouveau/nouveau_ttm.c index ec4668a..9b15a15 100644 --- a/drivers/gpu/drm/nouveau/nouveau_ttm.c +++ b/drivers/gpu/drm/nouveau/nouveau_ttm.c @@ -36,7 +36,7 @@ static int nouveau_vram_manager_init(struct ttm_mem_type_manager *man, unsigned long psize) { struct nouveau_drm *drm = nouveau_bdev(man->bdev); - struct nvkm_fb *fb = nvxx_fb(&drm->device); + struct nvkm_fb *fb = nvxx_fb(&drm->client.device); man->priv = fb; return 0; } @@ -67,7 +67,7 @@ nouveau_vram_manager_del(struct ttm_mem_type_manager *man, struct ttm_mem_reg *mem) { struct nouveau_drm *drm = nouveau_bdev(man->bdev); - struct nvkm_ram *ram = nvxx_fb(&drm->device)->ram; + struct nvkm_ram *ram = nvxx_fb(&drm->client.device)->ram; nvkm_mem_node_cleanup(mem->mm_node); ram->func->put(ram, (struct nvkm_mem **)&mem->mm_node); } @@ -79,13 +79,13 @@ nouveau_vram_manager_new(struct ttm_mem_type_manager *man, struct ttm_mem_reg *mem) { struct nouveau_drm *drm = nouveau_bdev(man->bdev); - struct nvkm_ram *ram = nvxx_fb(&drm->device)->ram; + struct nvkm_ram *ram = nvxx_fb(&drm->client.device)->ram; struct nouveau_bo *nvbo = nouveau_bo(bo); struct nvkm_mem *node; u32 size_nc = 0; int ret; - if (drm->device.info.ram_size == 0) + if (drm->client.device.info.ram_size == 0) return -ENOMEM; if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG) @@ -150,7 +150,7 @@ nouveau_gart_manager_new(struct ttm_mem_type_manager *man, node->page_shift = 12; - switch (drm->device.info.family) { + switch (drm->client.device.info.family) { case NV_DEVICE_INFO_V0_TNT: case NV_DEVICE_INFO_V0_CELSIUS: case NV_DEVICE_INFO_V0_KELVIN: @@ -158,7 +158,7 @@ nouveau_gart_manager_new(struct ttm_mem_type_manager *man, case NV_DEVICE_INFO_V0_CURIE: break; case NV_DEVICE_INFO_V0_TESLA: - if (drm->device.info.chipset != 0x50) + if (drm->client.device.info.chipset != 0x50) node->memtype = (nvbo->tile_flags & 0x7f00) >> 8; break; case NV_DEVICE_INFO_V0_FERMI: @@ -169,7 +169,7 @@ nouveau_gart_manager_new(struct ttm_mem_type_manager *man, break; default: NV_WARN(drm, "%s: unhandled family type %x\n", __func__, - drm->device.info.family); + drm->client.device.info.family); break; } @@ -197,7 +197,7 @@ static int nv04_gart_manager_init(struct ttm_mem_type_manager *man, unsigned long psize) { struct nouveau_drm *drm = nouveau_bdev(man->bdev); - struct nvkm_mmu *mmu = nvxx_mmu(&drm->device); + struct nvkm_mmu *mmu = nvxx_mmu(&drm->client.device); struct nv04_mmu *priv = (void *)mmu; struct nvkm_vm *vm = NULL; nvkm_vm_ref(priv->vm, &vm, NULL); @@ -339,7 +339,7 @@ nouveau_ttm_global_release(struct nouveau_drm *drm) int nouveau_ttm_init(struct nouveau_drm *drm) { - struct nvkm_device *device = nvxx_device(&drm->device); + struct nvkm_device *device = nvxx_device(&drm->client.device); struct nvkm_pci *pci = device->pci; struct drm_device *dev = drm->dev; u8 bits; @@ -352,8 +352,8 @@ nouveau_ttm_init(struct nouveau_drm *drm) drm->agp.cma = pci->agp.cma; } - bits = nvxx_mmu(&drm->device)->dma_bits; - if (nvxx_device(&drm->device)->func->pci) { + bits = nvxx_mmu(&drm->client.device)->dma_bits; + if (nvxx_device(&drm->client.device)->func->pci) { if (drm->agp.bridge) bits = 32; } else if (device->func->tegra) { @@ -396,7 +396,7 @@ nouveau_ttm_init(struct nouveau_drm *drm) } /* VRAM init */ - drm->gem.vram_available = drm->device.info.ram_user; + drm->gem.vram_available = drm->client.device.info.ram_user; arch_io_reserve_memtype_wc(device->func->resource_addr(device, 1), device->func->resource_size(device, 1)); @@ -413,7 +413,7 @@ nouveau_ttm_init(struct nouveau_drm *drm) /* GART init */ if (!drm->agp.bridge) { - drm->gem.gart_available = nvxx_mmu(&drm->device)->limit; + drm->gem.gart_available = nvxx_mmu(&drm->client.device)->limit; } else { drm->gem.gart_available = drm->agp.size; } @@ -433,7 +433,7 @@ nouveau_ttm_init(struct nouveau_drm *drm) void nouveau_ttm_fini(struct nouveau_drm *drm) { - struct nvkm_device *device = nvxx_device(&drm->device); + struct nvkm_device *device = nvxx_device(&drm->client.device); ttm_bo_clean_mm(&drm->ttm.bdev, TTM_PL_VRAM); ttm_bo_clean_mm(&drm->ttm.bdev, TTM_PL_TT); diff --git a/drivers/gpu/drm/nouveau/nouveau_vga.c b/drivers/gpu/drm/nouveau/nouveau_vga.c index c6a180a..eef22c6 100644 --- a/drivers/gpu/drm/nouveau/nouveau_vga.c +++ b/drivers/gpu/drm/nouveau/nouveau_vga.c @@ -13,13 +13,13 @@ static unsigned int nouveau_vga_set_decode(void *priv, bool state) { struct nouveau_drm *drm = nouveau_drm(priv); - struct nvif_object *device = &drm->device.object; + struct nvif_object *device = &drm->client.device.object; - if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE && - drm->device.info.chipset >= 0x4c) + if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE && + drm->client.device.info.chipset >= 0x4c) nvif_wr32(device, 0x088060, state); else - if (drm->device.info.chipset >= 0x40) + if (drm->client.device.info.chipset >= 0x40) nvif_wr32(device, 0x088054, state); else nvif_wr32(device, 0x001854, state); diff --git a/drivers/gpu/drm/nouveau/nv04_fbcon.c b/drivers/gpu/drm/nouveau/nv04_fbcon.c index 6a2b187..01731db 100644 --- a/drivers/gpu/drm/nouveau/nv04_fbcon.c +++ b/drivers/gpu/drm/nouveau/nv04_fbcon.c @@ -136,7 +136,7 @@ nv04_fbcon_accel_init(struct fb_info *info) struct drm_device *dev = nfbdev->helper.dev; struct nouveau_drm *drm = nouveau_drm(dev); struct nouveau_channel *chan = drm->channel; - struct nvif_device *device = &drm->device; + struct nvif_device *device = &drm->client.device; int surface_fmt, pattern_fmt, rect_fmt; int ret; diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c index 9d22303..de5e322 100644 --- a/drivers/gpu/drm/nouveau/nv50_display.c +++ b/drivers/gpu/drm/nouveau/nv50_display.c @@ -447,18 +447,18 @@ nv50_dmac_ctxdma_new(struct nv50_dmac *dmac, struct nouveau_framebuffer *fb) args.base.target = NV_DMA_V0_TARGET_VRAM; args.base.access = NV_DMA_V0_ACCESS_RDWR; args.base.start = 0; - args.base.limit = drm->device.info.ram_user - 1; + args.base.limit = drm->client.device.info.ram_user - 1; - if (drm->device.info.chipset < 0x80) { + if (drm->client.device.info.chipset < 0x80) { args.nv50.part = NV50_DMA_V0_PART_256; argc += sizeof(args.nv50); } else - if (drm->device.info.chipset < 0xc0) { + if (drm->client.device.info.chipset < 0xc0) { args.nv50.part = NV50_DMA_V0_PART_256; args.nv50.kind = kind; argc += sizeof(args.nv50); } else - if (drm->device.info.chipset < 0xd0) { + if (drm->client.device.info.chipset < 0xd0) { args.gf100.kind = kind; argc += sizeof(args.gf100); } else { @@ -848,7 +848,7 @@ nv50_wndw_atomic_check_acquire(struct nv50_wndw *wndw, asyw->image.kind = (fb->nvbo->tile_flags & 0x0000ff00) >> 8; if (asyw->image.kind) { asyw->image.layout = 0; - if (drm->device.info.chipset >= 0xc0) + if (drm->client.device.info.chipset >= 0xc0) asyw->image.block = fb->nvbo->tile_mode >> 4; else asyw->image.block = fb->nvbo->tile_mode; @@ -1397,7 +1397,7 @@ nv50_base_ntfy_wait_begun(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev); struct nv50_disp *disp = nv50_disp(wndw->plane.dev); - if (nvif_msec(&drm->device, 2000ULL, + if (nvif_msec(&drm->client.device, 2000ULL, u32 data = nouveau_bo_rd32(disp->sync, asyw->ntfy.offset / 4); if ((data & 0xc0000000) == 0x40000000) break; @@ -1522,7 +1522,7 @@ nv50_base_new(struct nouveau_drm *drm, struct nv50_head *head, return ret; } - ret = nv50_base_create(&drm->device, disp->disp, base->id, + ret = nv50_base_create(&drm->client.device, disp->disp, base->id, disp->sync->bo.offset, &base->chan); if (ret) return ret; @@ -2394,7 +2394,7 @@ static int nv50_head_create(struct drm_device *dev, int index) { struct nouveau_drm *drm = nouveau_drm(dev); - struct nvif_device *device = &drm->device; + struct nvif_device *device = &drm->client.device; struct nv50_disp *disp = nv50_disp(dev); struct nv50_head *head; struct nv50_base *base; @@ -2667,7 +2667,7 @@ static int nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe) { struct nouveau_drm *drm = nouveau_drm(connector->dev); - struct nvkm_i2c *i2c = nvxx_i2c(&drm->device); + struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); struct nvkm_i2c_bus *bus; struct nouveau_encoder *nv_encoder; struct drm_encoder *encoder; @@ -3657,7 +3657,7 @@ nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe) { struct nouveau_connector *nv_connector = nouveau_connector(connector); struct nouveau_drm *drm = nouveau_drm(connector->dev); - struct nvkm_i2c *i2c = nvxx_i2c(&drm->device); + struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); struct nouveau_encoder *nv_encoder; struct drm_encoder *encoder; int type, ret; @@ -3842,7 +3842,7 @@ static int nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe) { struct nouveau_drm *drm = nouveau_drm(connector->dev); - struct nvkm_i2c *i2c = nvxx_i2c(&drm->device); + struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); struct nvkm_i2c_bus *bus = NULL; struct nvkm_i2c_aux *aux = NULL; struct i2c_adapter *ddc; @@ -3915,7 +3915,7 @@ nv50_disp_atomic_commit_core(struct nouveau_drm *drm, u32 interlock) evo_data(push, 0x00000000); nouveau_bo_wr32(disp->sync, 0, 0x00000000); evo_kick(push, core); - if (nvif_msec(&drm->device, 2000ULL, + if (nvif_msec(&drm->client.device, 2000ULL, if (nouveau_bo_rd32(disp->sync, 0)) break; usleep_range(1, 2); @@ -4427,7 +4427,7 @@ module_param_named(atomic, nouveau_atomic, int, 0400); int nv50_display_create(struct drm_device *dev) { - struct nvif_device *device = &nouveau_drm(dev)->device; + struct nvif_device *device = &nouveau_drm(dev)->client.device; struct nouveau_drm *drm = nouveau_drm(dev); struct dcb_table *dcb = &drm->vbios.dcb; struct drm_connector *connector, *tmp; diff --git a/drivers/gpu/drm/nouveau/nv84_fence.c b/drivers/gpu/drm/nouveau/nv84_fence.c index be30aaf..86360fc 100644 --- a/drivers/gpu/drm/nouveau/nv84_fence.c +++ b/drivers/gpu/drm/nouveau/nv84_fence.c @@ -193,7 +193,7 @@ nv84_fence_destroy(struct nouveau_drm *drm) int nv84_fence_create(struct nouveau_drm *drm) { - struct nvkm_fifo *fifo = nvxx_fifo(&drm->device); + struct nvkm_fifo *fifo = nvxx_fifo(&drm->client.device); struct nv84_fence_priv *priv; u32 domain; int ret; @@ -213,7 +213,7 @@ nv84_fence_create(struct nouveau_drm *drm) priv->base.uevent = true; /* Use VRAM if there is any ; otherwise fallback to system memory */ - domain = drm->device.info.ram_size != 0 ? TTM_PL_FLAG_VRAM : + domain = drm->client.device.info.ram_size != 0 ? TTM_PL_FLAG_VRAM : /* * fences created in sysmem must be non-cached or we * will lose CPU/GPU coherency! -- cgit v1.1 From 605f9ccd7d0ad603d8df9301f3f400be5d8081d9 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 17 May 2016 11:13:37 +1000 Subject: drm/nouveau: s/mem/reg/ for struct ttm_mem_reg variables Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_bo.c | 266 ++++++++++++++++---------------- drivers/gpu/drm/nouveau/nouveau_sgdma.c | 12 +- drivers/gpu/drm/nouveau/nouveau_ttm.c | 48 +++--- drivers/gpu/drm/nouveau/nv17_fence.c | 6 +- drivers/gpu/drm/nouveau/nv50_fence.c | 6 +- 5 files changed, 169 insertions(+), 169 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index 1b8d61b..bbcfd27 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -655,20 +655,20 @@ nve0_bo_move_init(struct nouveau_channel *chan, u32 handle) static int nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, - struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) + struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) { - struct nvkm_mem *node = old_mem->mm_node; + struct nvkm_mem *mem = old_reg->mm_node; int ret = RING_SPACE(chan, 10); if (ret == 0) { BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8); - OUT_RING (chan, upper_32_bits(node->vma[0].offset)); - OUT_RING (chan, lower_32_bits(node->vma[0].offset)); - OUT_RING (chan, upper_32_bits(node->vma[1].offset)); - OUT_RING (chan, lower_32_bits(node->vma[1].offset)); + OUT_RING (chan, upper_32_bits(mem->vma[0].offset)); + OUT_RING (chan, lower_32_bits(mem->vma[0].offset)); + OUT_RING (chan, upper_32_bits(mem->vma[1].offset)); + OUT_RING (chan, lower_32_bits(mem->vma[1].offset)); OUT_RING (chan, PAGE_SIZE); OUT_RING (chan, PAGE_SIZE); OUT_RING (chan, PAGE_SIZE); - OUT_RING (chan, new_mem->num_pages); + OUT_RING (chan, new_reg->num_pages); BEGIN_IMC0(chan, NvSubCopy, 0x0300, 0x0386); } return ret; @@ -687,15 +687,15 @@ nvc0_bo_move_init(struct nouveau_channel *chan, u32 handle) static int nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, - struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) + struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) { - struct nvkm_mem *node = old_mem->mm_node; - u64 src_offset = node->vma[0].offset; - u64 dst_offset = node->vma[1].offset; - u32 page_count = new_mem->num_pages; + struct nvkm_mem *mem = old_reg->mm_node; + u64 src_offset = mem->vma[0].offset; + u64 dst_offset = mem->vma[1].offset; + u32 page_count = new_reg->num_pages; int ret; - page_count = new_mem->num_pages; + page_count = new_reg->num_pages; while (page_count) { int line_count = (page_count > 8191) ? 8191 : page_count; @@ -725,15 +725,15 @@ nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, static int nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, - struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) + struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) { - struct nvkm_mem *node = old_mem->mm_node; - u64 src_offset = node->vma[0].offset; - u64 dst_offset = node->vma[1].offset; - u32 page_count = new_mem->num_pages; + struct nvkm_mem *mem = old_reg->mm_node; + u64 src_offset = mem->vma[0].offset; + u64 dst_offset = mem->vma[1].offset; + u32 page_count = new_reg->num_pages; int ret; - page_count = new_mem->num_pages; + page_count = new_reg->num_pages; while (page_count) { int line_count = (page_count > 2047) ? 2047 : page_count; @@ -764,15 +764,15 @@ nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, static int nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, - struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) + struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) { - struct nvkm_mem *node = old_mem->mm_node; - u64 src_offset = node->vma[0].offset; - u64 dst_offset = node->vma[1].offset; - u32 page_count = new_mem->num_pages; + struct nvkm_mem *mem = old_reg->mm_node; + u64 src_offset = mem->vma[0].offset; + u64 dst_offset = mem->vma[1].offset; + u32 page_count = new_reg->num_pages; int ret; - page_count = new_mem->num_pages; + page_count = new_reg->num_pages; while (page_count) { int line_count = (page_count > 8191) ? 8191 : page_count; @@ -802,35 +802,35 @@ nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, static int nv98_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo, - struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) + struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) { - struct nvkm_mem *node = old_mem->mm_node; + struct nvkm_mem *mem = old_reg->mm_node; int ret = RING_SPACE(chan, 7); if (ret == 0) { BEGIN_NV04(chan, NvSubCopy, 0x0320, 6); - OUT_RING (chan, upper_32_bits(node->vma[0].offset)); - OUT_RING (chan, lower_32_bits(node->vma[0].offset)); - OUT_RING (chan, upper_32_bits(node->vma[1].offset)); - OUT_RING (chan, lower_32_bits(node->vma[1].offset)); + OUT_RING (chan, upper_32_bits(mem->vma[0].offset)); + OUT_RING (chan, lower_32_bits(mem->vma[0].offset)); + OUT_RING (chan, upper_32_bits(mem->vma[1].offset)); + OUT_RING (chan, lower_32_bits(mem->vma[1].offset)); OUT_RING (chan, 0x00000000 /* COPY */); - OUT_RING (chan, new_mem->num_pages << PAGE_SHIFT); + OUT_RING (chan, new_reg->num_pages << PAGE_SHIFT); } return ret; } static int nv84_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo, - struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) + struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) { - struct nvkm_mem *node = old_mem->mm_node; + struct nvkm_mem *mem = old_reg->mm_node; int ret = RING_SPACE(chan, 7); if (ret == 0) { BEGIN_NV04(chan, NvSubCopy, 0x0304, 6); - OUT_RING (chan, new_mem->num_pages << PAGE_SHIFT); - OUT_RING (chan, upper_32_bits(node->vma[0].offset)); - OUT_RING (chan, lower_32_bits(node->vma[0].offset)); - OUT_RING (chan, upper_32_bits(node->vma[1].offset)); - OUT_RING (chan, lower_32_bits(node->vma[1].offset)); + OUT_RING (chan, new_reg->num_pages << PAGE_SHIFT); + OUT_RING (chan, upper_32_bits(mem->vma[0].offset)); + OUT_RING (chan, lower_32_bits(mem->vma[0].offset)); + OUT_RING (chan, upper_32_bits(mem->vma[1].offset)); + OUT_RING (chan, lower_32_bits(mem->vma[1].offset)); OUT_RING (chan, 0x00000000 /* MODE_COPY, QUERY_NONE */); } return ret; @@ -854,14 +854,14 @@ nv50_bo_move_init(struct nouveau_channel *chan, u32 handle) static int nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, - struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) + struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) { - struct nvkm_mem *node = old_mem->mm_node; - u64 length = (new_mem->num_pages << PAGE_SHIFT); - u64 src_offset = node->vma[0].offset; - u64 dst_offset = node->vma[1].offset; - int src_tiled = !!node->memtype; - int dst_tiled = !!((struct nvkm_mem *)new_mem->mm_node)->memtype; + struct nvkm_mem *mem = old_reg->mm_node; + u64 length = (new_reg->num_pages << PAGE_SHIFT); + u64 src_offset = mem->vma[0].offset; + u64 dst_offset = mem->vma[1].offset; + int src_tiled = !!mem->memtype; + int dst_tiled = !!((struct nvkm_mem *)new_reg->mm_node)->memtype; int ret; while (length) { @@ -941,20 +941,20 @@ nv04_bo_move_init(struct nouveau_channel *chan, u32 handle) static inline uint32_t nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo, - struct nouveau_channel *chan, struct ttm_mem_reg *mem) + struct nouveau_channel *chan, struct ttm_mem_reg *reg) { - if (mem->mem_type == TTM_PL_TT) + if (reg->mem_type == TTM_PL_TT) return NvDmaTT; return chan->vram.handle; } static int nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, - struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) + struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) { - u32 src_offset = old_mem->start << PAGE_SHIFT; - u32 dst_offset = new_mem->start << PAGE_SHIFT; - u32 page_count = new_mem->num_pages; + u32 src_offset = old_reg->start << PAGE_SHIFT; + u32 dst_offset = new_reg->start << PAGE_SHIFT; + u32 page_count = new_reg->num_pages; int ret; ret = RING_SPACE(chan, 3); @@ -962,10 +962,10 @@ nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, return ret; BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2); - OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem)); - OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem)); + OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_reg)); + OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_reg)); - page_count = new_mem->num_pages; + page_count = new_reg->num_pages; while (page_count) { int line_count = (page_count > 2047) ? 2047 : page_count; @@ -996,33 +996,33 @@ nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, static int nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo, - struct ttm_mem_reg *mem) + struct ttm_mem_reg *reg) { - struct nvkm_mem *old_node = bo->mem.mm_node; - struct nvkm_mem *new_node = mem->mm_node; - u64 size = (u64)mem->num_pages << PAGE_SHIFT; + struct nvkm_mem *old_mem = bo->mem.mm_node; + struct nvkm_mem *new_mem = reg->mm_node; + u64 size = (u64)reg->num_pages << PAGE_SHIFT; int ret; - ret = nvkm_vm_get(drm->client.vm, size, old_node->page_shift, - NV_MEM_ACCESS_RW, &old_node->vma[0]); + ret = nvkm_vm_get(drm->client.vm, size, old_mem->page_shift, + NV_MEM_ACCESS_RW, &old_mem->vma[0]); if (ret) return ret; - ret = nvkm_vm_get(drm->client.vm, size, new_node->page_shift, - NV_MEM_ACCESS_RW, &old_node->vma[1]); + ret = nvkm_vm_get(drm->client.vm, size, new_mem->page_shift, + NV_MEM_ACCESS_RW, &old_mem->vma[1]); if (ret) { - nvkm_vm_put(&old_node->vma[0]); + nvkm_vm_put(&old_mem->vma[0]); return ret; } - nvkm_vm_map(&old_node->vma[0], old_node); - nvkm_vm_map(&old_node->vma[1], new_node); + nvkm_vm_map(&old_mem->vma[0], old_mem); + nvkm_vm_map(&old_mem->vma[1], new_mem); return 0; } static int nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr, - bool no_wait_gpu, struct ttm_mem_reg *new_mem) + bool no_wait_gpu, struct ttm_mem_reg *new_reg) { struct nouveau_drm *drm = nouveau_bdev(bo->bdev); struct nouveau_channel *chan = drm->ttm.chan; @@ -1035,7 +1035,7 @@ nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr, * destroyed the ttm_mem_reg */ if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) { - ret = nouveau_bo_move_prep(drm, bo, new_mem); + ret = nouveau_bo_move_prep(drm, bo, new_reg); if (ret) return ret; } @@ -1043,14 +1043,14 @@ nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr, mutex_lock_nested(&cli->mutex, SINGLE_DEPTH_NESTING); ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, intr); if (ret == 0) { - ret = drm->ttm.move(chan, bo, &bo->mem, new_mem); + ret = drm->ttm.move(chan, bo, &bo->mem, new_reg); if (ret == 0) { ret = nouveau_fence_new(chan, false, &fence); if (ret == 0) { ret = ttm_bo_move_accel_cleanup(bo, &fence->base, evict, - new_mem); + new_reg); nouveau_fence_unref(&fence); } } @@ -1125,7 +1125,7 @@ nouveau_bo_move_init(struct nouveau_drm *drm) static int nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr, - bool no_wait_gpu, struct ttm_mem_reg *new_mem) + bool no_wait_gpu, struct ttm_mem_reg *new_reg) { struct ttm_place placement_memtype = { .fpfn = 0, @@ -1133,35 +1133,35 @@ nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr, .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING }; struct ttm_placement placement; - struct ttm_mem_reg tmp_mem; + struct ttm_mem_reg tmp_reg; int ret; placement.num_placement = placement.num_busy_placement = 1; placement.placement = placement.busy_placement = &placement_memtype; - tmp_mem = *new_mem; - tmp_mem.mm_node = NULL; - ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_gpu); + tmp_reg = *new_reg; + tmp_reg.mm_node = NULL; + ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, intr, no_wait_gpu); if (ret) return ret; - ret = ttm_tt_bind(bo->ttm, &tmp_mem); + ret = ttm_tt_bind(bo->ttm, &tmp_reg); if (ret) goto out; - ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, &tmp_mem); + ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, &tmp_reg); if (ret) goto out; - ret = ttm_bo_move_ttm(bo, intr, no_wait_gpu, new_mem); + ret = ttm_bo_move_ttm(bo, intr, no_wait_gpu, new_reg); out: - ttm_bo_mem_put(bo, &tmp_mem); + ttm_bo_mem_put(bo, &tmp_reg); return ret; } static int nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr, - bool no_wait_gpu, struct ttm_mem_reg *new_mem) + bool no_wait_gpu, struct ttm_mem_reg *new_reg) { struct ttm_place placement_memtype = { .fpfn = 0, @@ -1169,34 +1169,34 @@ nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr, .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING }; struct ttm_placement placement; - struct ttm_mem_reg tmp_mem; + struct ttm_mem_reg tmp_reg; int ret; placement.num_placement = placement.num_busy_placement = 1; placement.placement = placement.busy_placement = &placement_memtype; - tmp_mem = *new_mem; - tmp_mem.mm_node = NULL; - ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_gpu); + tmp_reg = *new_reg; + tmp_reg.mm_node = NULL; + ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, intr, no_wait_gpu); if (ret) return ret; - ret = ttm_bo_move_ttm(bo, intr, no_wait_gpu, &tmp_mem); + ret = ttm_bo_move_ttm(bo, intr, no_wait_gpu, &tmp_reg); if (ret) goto out; - ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, new_mem); + ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, new_reg); if (ret) goto out; out: - ttm_bo_mem_put(bo, &tmp_mem); + ttm_bo_mem_put(bo, &tmp_reg); return ret; } static void nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, bool evict, - struct ttm_mem_reg *new_mem) + struct ttm_mem_reg *new_reg) { struct nouveau_bo *nvbo = nouveau_bo(bo); struct nvkm_vma *vma; @@ -1206,10 +1206,10 @@ nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, bool evict, return; list_for_each_entry(vma, &nvbo->vma_list, head) { - if (new_mem && new_mem->mem_type != TTM_PL_SYSTEM && - (new_mem->mem_type == TTM_PL_VRAM || + if (new_reg && new_reg->mem_type != TTM_PL_SYSTEM && + (new_reg->mem_type == TTM_PL_VRAM || nvbo->page_shift != vma->vm->mmu->lpg_shift)) { - nvkm_vm_map(vma, new_mem->mm_node); + nvkm_vm_map(vma, new_reg->mm_node); } else { WARN_ON(ttm_bo_wait(bo, false, false)); nvkm_vm_unmap(vma); @@ -1218,20 +1218,20 @@ nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, bool evict, } static int -nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem, +nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_reg, struct nouveau_drm_tile **new_tile) { struct nouveau_drm *drm = nouveau_bdev(bo->bdev); struct drm_device *dev = drm->dev; struct nouveau_bo *nvbo = nouveau_bo(bo); - u64 offset = new_mem->start << PAGE_SHIFT; + u64 offset = new_reg->start << PAGE_SHIFT; *new_tile = NULL; - if (new_mem->mem_type != TTM_PL_VRAM) + if (new_reg->mem_type != TTM_PL_VRAM) return 0; if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { - *new_tile = nv10_bo_set_tiling(dev, offset, new_mem->size, + *new_tile = nv10_bo_set_tiling(dev, offset, new_reg->size, nvbo->tile_mode, nvbo->tile_flags); } @@ -1254,11 +1254,11 @@ nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo, static int nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr, - bool no_wait_gpu, struct ttm_mem_reg *new_mem) + bool no_wait_gpu, struct ttm_mem_reg *new_reg) { struct nouveau_drm *drm = nouveau_bdev(bo->bdev); struct nouveau_bo *nvbo = nouveau_bo(bo); - struct ttm_mem_reg *old_mem = &bo->mem; + struct ttm_mem_reg *old_reg = &bo->mem; struct nouveau_drm_tile *new_tile = NULL; int ret = 0; @@ -1270,30 +1270,30 @@ nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr, NV_WARN(drm, "Moving pinned object %p!\n", nvbo); if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) { - ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile); + ret = nouveau_bo_vm_bind(bo, new_reg, &new_tile); if (ret) return ret; } /* Fake bo copy. */ - if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) { + if (old_reg->mem_type == TTM_PL_SYSTEM && !bo->ttm) { BUG_ON(bo->mem.mm_node != NULL); - bo->mem = *new_mem; - new_mem->mm_node = NULL; + bo->mem = *new_reg; + new_reg->mm_node = NULL; goto out; } /* Hardware assisted copy. */ if (drm->ttm.move) { - if (new_mem->mem_type == TTM_PL_SYSTEM) + if (new_reg->mem_type == TTM_PL_SYSTEM) ret = nouveau_bo_move_flipd(bo, evict, intr, - no_wait_gpu, new_mem); - else if (old_mem->mem_type == TTM_PL_SYSTEM) + no_wait_gpu, new_reg); + else if (old_reg->mem_type == TTM_PL_SYSTEM) ret = nouveau_bo_move_flips(bo, evict, intr, - no_wait_gpu, new_mem); + no_wait_gpu, new_reg); else ret = nouveau_bo_move_m2mf(bo, evict, intr, - no_wait_gpu, new_mem); + no_wait_gpu, new_reg); if (!ret) goto out; } @@ -1301,7 +1301,7 @@ nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr, /* Fallback to software copy. */ ret = ttm_bo_wait(bo, intr, no_wait_gpu); if (ret == 0) - ret = ttm_bo_move_memcpy(bo, intr, no_wait_gpu, new_mem); + ret = ttm_bo_move_memcpy(bo, intr, no_wait_gpu, new_reg); out: if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) { @@ -1324,54 +1324,54 @@ nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp) } static int -nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) +nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *reg) { - struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type]; + struct ttm_mem_type_manager *man = &bdev->man[reg->mem_type]; struct nouveau_drm *drm = nouveau_bdev(bdev); struct nvkm_device *device = nvxx_device(&drm->client.device); - struct nvkm_mem *node = mem->mm_node; + struct nvkm_mem *mem = reg->mm_node; int ret; - mem->bus.addr = NULL; - mem->bus.offset = 0; - mem->bus.size = mem->num_pages << PAGE_SHIFT; - mem->bus.base = 0; - mem->bus.is_iomem = false; + reg->bus.addr = NULL; + reg->bus.offset = 0; + reg->bus.size = reg->num_pages << PAGE_SHIFT; + reg->bus.base = 0; + reg->bus.is_iomem = false; if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE)) return -EINVAL; - switch (mem->mem_type) { + switch (reg->mem_type) { case TTM_PL_SYSTEM: /* System memory */ return 0; case TTM_PL_TT: #if IS_ENABLED(CONFIG_AGP) if (drm->agp.bridge) { - mem->bus.offset = mem->start << PAGE_SHIFT; - mem->bus.base = drm->agp.base; - mem->bus.is_iomem = !drm->agp.cma; + reg->bus.offset = reg->start << PAGE_SHIFT; + reg->bus.base = drm->agp.base; + reg->bus.is_iomem = !drm->agp.cma; } #endif - if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA || !node->memtype) + if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA || !mem->memtype) /* untiled */ break; /* fallthrough, tiled memory */ case TTM_PL_VRAM: - mem->bus.offset = mem->start << PAGE_SHIFT; - mem->bus.base = device->func->resource_addr(device, 1); - mem->bus.is_iomem = true; + reg->bus.offset = reg->start << PAGE_SHIFT; + reg->bus.base = device->func->resource_addr(device, 1); + reg->bus.is_iomem = true; if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) { struct nvkm_bar *bar = nvxx_bar(&drm->client.device); int page_shift = 12; if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_FERMI) - page_shift = node->page_shift; + page_shift = mem->page_shift; - ret = nvkm_bar_umap(bar, node->size << 12, page_shift, - &node->bar_vma); + ret = nvkm_bar_umap(bar, mem->size << 12, page_shift, + &mem->bar_vma); if (ret) return ret; - nvkm_vm_map(&node->bar_vma, node); - mem->bus.offset = node->bar_vma.offset; + nvkm_vm_map(&mem->bar_vma, mem); + reg->bus.offset = mem->bar_vma.offset; } break; default: @@ -1381,15 +1381,15 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) } static void -nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) +nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *reg) { - struct nvkm_mem *node = mem->mm_node; + struct nvkm_mem *mem = reg->mm_node; - if (!node->bar_vma.node) + if (!mem->bar_vma.node) return; - nvkm_vm_unmap(&node->bar_vma); - nvkm_vm_put(&node->bar_vma); + nvkm_vm_unmap(&mem->bar_vma); + nvkm_vm_put(&mem->bar_vma); } static int diff --git a/drivers/gpu/drm/nouveau/nouveau_sgdma.c b/drivers/gpu/drm/nouveau/nouveau_sgdma.c index 8da005b..b7ab268 100644 --- a/drivers/gpu/drm/nouveau/nouveau_sgdma.c +++ b/drivers/gpu/drm/nouveau/nouveau_sgdma.c @@ -24,10 +24,10 @@ nouveau_sgdma_destroy(struct ttm_tt *ttm) } static int -nv04_sgdma_bind(struct ttm_tt *ttm, struct ttm_mem_reg *mem) +nv04_sgdma_bind(struct ttm_tt *ttm, struct ttm_mem_reg *reg) { struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)ttm; - struct nvkm_mem *node = mem->mm_node; + struct nvkm_mem *node = reg->mm_node; if (ttm->sg) { node->sg = ttm->sg; @@ -36,7 +36,7 @@ nv04_sgdma_bind(struct ttm_tt *ttm, struct ttm_mem_reg *mem) node->sg = NULL; node->pages = nvbe->ttm.dma_address; } - node->size = (mem->num_pages << PAGE_SHIFT) >> 12; + node->size = (reg->num_pages << PAGE_SHIFT) >> 12; nvkm_vm_map(&node->vma[0], node); nvbe->node = node; @@ -58,10 +58,10 @@ static struct ttm_backend_func nv04_sgdma_backend = { }; static int -nv50_sgdma_bind(struct ttm_tt *ttm, struct ttm_mem_reg *mem) +nv50_sgdma_bind(struct ttm_tt *ttm, struct ttm_mem_reg *reg) { struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)ttm; - struct nvkm_mem *node = mem->mm_node; + struct nvkm_mem *node = reg->mm_node; /* noop: bound in move_notify() */ if (ttm->sg) { @@ -71,7 +71,7 @@ nv50_sgdma_bind(struct ttm_tt *ttm, struct ttm_mem_reg *mem) node->sg = NULL; node->pages = nvbe->ttm.dma_address; } - node->size = (mem->num_pages << PAGE_SHIFT) >> 12; + node->size = (reg->num_pages << PAGE_SHIFT) >> 12; return 0; } diff --git a/drivers/gpu/drm/nouveau/nouveau_ttm.c b/drivers/gpu/drm/nouveau/nouveau_ttm.c index 9b15a15..13e5cc5 100644 --- a/drivers/gpu/drm/nouveau/nouveau_ttm.c +++ b/drivers/gpu/drm/nouveau/nouveau_ttm.c @@ -64,19 +64,19 @@ nvkm_mem_node_cleanup(struct nvkm_mem *node) static void nouveau_vram_manager_del(struct ttm_mem_type_manager *man, - struct ttm_mem_reg *mem) + struct ttm_mem_reg *reg) { struct nouveau_drm *drm = nouveau_bdev(man->bdev); struct nvkm_ram *ram = nvxx_fb(&drm->client.device)->ram; - nvkm_mem_node_cleanup(mem->mm_node); - ram->func->put(ram, (struct nvkm_mem **)&mem->mm_node); + nvkm_mem_node_cleanup(reg->mm_node); + ram->func->put(ram, (struct nvkm_mem **)®->mm_node); } static int nouveau_vram_manager_new(struct ttm_mem_type_manager *man, struct ttm_buffer_object *bo, const struct ttm_place *place, - struct ttm_mem_reg *mem) + struct ttm_mem_reg *reg) { struct nouveau_drm *drm = nouveau_bdev(man->bdev); struct nvkm_ram *ram = nvxx_fb(&drm->client.device)->ram; @@ -91,18 +91,18 @@ nouveau_vram_manager_new(struct ttm_mem_type_manager *man, if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG) size_nc = 1 << nvbo->page_shift; - ret = ram->func->get(ram, mem->num_pages << PAGE_SHIFT, - mem->page_alignment << PAGE_SHIFT, size_nc, + ret = ram->func->get(ram, reg->num_pages << PAGE_SHIFT, + reg->page_alignment << PAGE_SHIFT, size_nc, (nvbo->tile_flags >> 8) & 0x3ff, &node); if (ret) { - mem->mm_node = NULL; + reg->mm_node = NULL; return (ret == -ENOSPC) ? 0 : ret; } node->page_shift = nvbo->page_shift; - mem->mm_node = node; - mem->start = node->offset >> PAGE_SHIFT; + reg->mm_node = node; + reg->start = node->offset >> PAGE_SHIFT; return 0; } @@ -127,18 +127,18 @@ nouveau_gart_manager_fini(struct ttm_mem_type_manager *man) static void nouveau_gart_manager_del(struct ttm_mem_type_manager *man, - struct ttm_mem_reg *mem) + struct ttm_mem_reg *reg) { - nvkm_mem_node_cleanup(mem->mm_node); - kfree(mem->mm_node); - mem->mm_node = NULL; + nvkm_mem_node_cleanup(reg->mm_node); + kfree(reg->mm_node); + reg->mm_node = NULL; } static int nouveau_gart_manager_new(struct ttm_mem_type_manager *man, struct ttm_buffer_object *bo, const struct ttm_place *place, - struct ttm_mem_reg *mem) + struct ttm_mem_reg *reg) { struct nouveau_drm *drm = nouveau_bdev(bo->bdev); struct nouveau_bo *nvbo = nouveau_bo(bo); @@ -173,8 +173,8 @@ nouveau_gart_manager_new(struct ttm_mem_type_manager *man, break; } - mem->mm_node = node; - mem->start = 0; + reg->mm_node = node; + reg->start = 0; return 0; } @@ -215,20 +215,20 @@ nv04_gart_manager_fini(struct ttm_mem_type_manager *man) } static void -nv04_gart_manager_del(struct ttm_mem_type_manager *man, struct ttm_mem_reg *mem) +nv04_gart_manager_del(struct ttm_mem_type_manager *man, struct ttm_mem_reg *reg) { - struct nvkm_mem *node = mem->mm_node; + struct nvkm_mem *node = reg->mm_node; if (node->vma[0].node) nvkm_vm_put(&node->vma[0]); - kfree(mem->mm_node); - mem->mm_node = NULL; + kfree(reg->mm_node); + reg->mm_node = NULL; } static int nv04_gart_manager_new(struct ttm_mem_type_manager *man, struct ttm_buffer_object *bo, const struct ttm_place *place, - struct ttm_mem_reg *mem) + struct ttm_mem_reg *reg) { struct nvkm_mem *node; int ret; @@ -239,15 +239,15 @@ nv04_gart_manager_new(struct ttm_mem_type_manager *man, node->page_shift = 12; - ret = nvkm_vm_get(man->priv, mem->num_pages << 12, node->page_shift, + ret = nvkm_vm_get(man->priv, reg->num_pages << 12, node->page_shift, NV_MEM_ACCESS_RW, &node->vma[0]); if (ret) { kfree(node); return ret; } - mem->mm_node = node; - mem->start = node->vma[0].offset >> PAGE_SHIFT; + reg->mm_node = node; + reg->start = node->vma[0].offset >> PAGE_SHIFT; return 0; } diff --git a/drivers/gpu/drm/nouveau/nv17_fence.c b/drivers/gpu/drm/nouveau/nv17_fence.c index 5aeda14..6477b70 100644 --- a/drivers/gpu/drm/nouveau/nv17_fence.c +++ b/drivers/gpu/drm/nouveau/nv17_fence.c @@ -76,9 +76,9 @@ nv17_fence_context_new(struct nouveau_channel *chan) { struct nv10_fence_priv *priv = chan->drm->fence; struct nv10_fence_chan *fctx; - struct ttm_mem_reg *mem = &priv->bo->bo.mem; - u32 start = mem->start * PAGE_SIZE; - u32 limit = start + mem->size - 1; + struct ttm_mem_reg *reg = &priv->bo->bo.mem; + u32 start = reg->start * PAGE_SIZE; + u32 limit = start + reg->size - 1; int ret = 0; fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL); diff --git a/drivers/gpu/drm/nouveau/nv50_fence.c b/drivers/gpu/drm/nouveau/nv50_fence.c index 1e3ac3f..a369d97 100644 --- a/drivers/gpu/drm/nouveau/nv50_fence.c +++ b/drivers/gpu/drm/nouveau/nv50_fence.c @@ -37,9 +37,9 @@ nv50_fence_context_new(struct nouveau_channel *chan) { struct nv10_fence_priv *priv = chan->drm->fence; struct nv10_fence_chan *fctx; - struct ttm_mem_reg *mem = &priv->bo->bo.mem; - u32 start = mem->start * PAGE_SIZE; - u32 limit = start + mem->size - 1; + struct ttm_mem_reg *reg = &priv->bo->bo.mem; + u32 start = reg->start * PAGE_SIZE; + u32 limit = start + reg->size - 1; int ret; fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL); -- cgit v1.1 From 4d8b3d34c323e4692a69c7ab063c157773c34f0f Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 23 May 2016 12:34:49 +1000 Subject: drm/nouveau: size is u64 everywhere Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_bo.c | 34 ++++++++++++++++++---------------- drivers/gpu/drm/nouveau/nouveau_bo.h | 2 +- drivers/gpu/drm/nouveau/nouveau_gem.c | 2 +- drivers/gpu/drm/nouveau/nouveau_gem.h | 2 +- 4 files changed, 21 insertions(+), 19 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index bbcfd27..548f36d 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -139,9 +139,17 @@ nouveau_bo_del_ttm(struct ttm_buffer_object *bo) kfree(nvbo); } +static inline u64 +roundup_64(u64 x, u32 y) +{ + x += y - 1; + do_div(x, y); + return x * y; +} + static void nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags, - int *align, int *size) + int *align, u64 *size) { struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); struct nvif_device *device = &drm->client.device; @@ -150,31 +158,31 @@ nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags, if (nvbo->tile_mode) { if (device->info.chipset >= 0x40) { *align = 65536; - *size = roundup(*size, 64 * nvbo->tile_mode); + *size = roundup_64(*size, 64 * nvbo->tile_mode); } else if (device->info.chipset >= 0x30) { *align = 32768; - *size = roundup(*size, 64 * nvbo->tile_mode); + *size = roundup_64(*size, 64 * nvbo->tile_mode); } else if (device->info.chipset >= 0x20) { *align = 16384; - *size = roundup(*size, 64 * nvbo->tile_mode); + *size = roundup_64(*size, 64 * nvbo->tile_mode); } else if (device->info.chipset >= 0x10) { *align = 16384; - *size = roundup(*size, 32 * nvbo->tile_mode); + *size = roundup_64(*size, 32 * nvbo->tile_mode); } } } else { - *size = roundup(*size, (1 << nvbo->page_shift)); + *size = roundup_64(*size, (1 << nvbo->page_shift)); *align = max((1 << nvbo->page_shift), *align); } - *size = roundup(*size, PAGE_SIZE); + *size = roundup_64(*size, PAGE_SIZE); } int -nouveau_bo_new(struct nouveau_cli *cli, int size, int align, +nouveau_bo_new(struct nouveau_cli *cli, u64 size, int align, uint32_t flags, uint32_t tile_mode, uint32_t tile_flags, struct sg_table *sg, struct reservation_object *robj, struct nouveau_bo **pnvbo) @@ -184,15 +192,9 @@ nouveau_bo_new(struct nouveau_cli *cli, int size, int align, size_t acc_size; int ret; int type = ttm_bo_type_device; - int lpg_shift = 12; - int max_size; - - if (drm->client.vm) - lpg_shift = drm->client.vm->mmu->lpg_shift; - max_size = INT_MAX & ~((1 << lpg_shift) - 1); - if (size <= 0 || size > max_size) { - NV_WARN(drm, "skipped size %x\n", (u32)size); + if (!size) { + NV_WARN(drm, "skipped size %016llx\n", size); return -EINVAL; } diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.h b/drivers/gpu/drm/nouveau/nouveau_bo.h index abb8a18..b06a538 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.h +++ b/drivers/gpu/drm/nouveau/nouveau_bo.h @@ -71,7 +71,7 @@ nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) extern struct ttm_bo_driver nouveau_bo_driver; void nouveau_bo_move_init(struct nouveau_drm *); -int nouveau_bo_new(struct nouveau_cli *, int size, int align, u32 flags, +int nouveau_bo_new(struct nouveau_cli *, u64 size, int align, u32 flags, u32 tile_mode, u32 tile_flags, struct sg_table *sg, struct reservation_object *robj, struct nouveau_bo **); diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c index b334c4a..ca5397b 100644 --- a/drivers/gpu/drm/nouveau/nouveau_gem.c +++ b/drivers/gpu/drm/nouveau/nouveau_gem.c @@ -175,7 +175,7 @@ nouveau_gem_object_close(struct drm_gem_object *gem, struct drm_file *file_priv) } int -nouveau_gem_new(struct nouveau_cli *cli, int size, int align, uint32_t domain, +nouveau_gem_new(struct nouveau_cli *cli, u64 size, int align, uint32_t domain, uint32_t tile_mode, uint32_t tile_flags, struct nouveau_bo **pnvbo) { diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.h b/drivers/gpu/drm/nouveau/nouveau_gem.h index 5ce9a0e..8fa6ed9 100644 --- a/drivers/gpu/drm/nouveau/nouveau_gem.h +++ b/drivers/gpu/drm/nouveau/nouveau_gem.h @@ -16,7 +16,7 @@ nouveau_gem_object(struct drm_gem_object *gem) } /* nouveau_gem.c */ -extern int nouveau_gem_new(struct nouveau_cli *, int size, int align, +extern int nouveau_gem_new(struct nouveau_cli *, u64 size, int align, uint32_t domain, uint32_t tile_mode, uint32_t tile_flags, struct nouveau_bo **); extern void nouveau_gem_object_del(struct drm_gem_object *); -- cgit v1.1 From 0879683280508ea3d474dcaf91b4658985824513 Mon Sep 17 00:00:00 2001 From: Ilia Mirkin Date: Thu, 5 Jan 2017 01:13:15 -0500 Subject: drm/nouveau: fix bug id typo in comment The issue was recorded in fd.o bug 27501, not 25701. Signed-off-by: Ilia Mirkin Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.c index 0a0e44b..017a91d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.c @@ -39,7 +39,7 @@ mcp77_ram_init(struct nvkm_ram *base) u32 flush = ((ram->base.size - (ram->poller_base + 0x40)) >> 5) - 1; /* Enable NISO poller for various clients and set their associated - * read address, only for MCP77/78 and MCP79/7A. (fd#25701) + * read address, only for MCP77/78 and MCP79/7A. (fd#27501) */ nvkm_wr32(device, 0x100c18, dniso); nvkm_mask(device, 0x100c14, 0x00000000, 0x00000001); -- cgit v1.1 From 9f1c4dbd3def9bc43601b89c94666e660f2f2646 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 16 Jan 2017 13:44:11 +1000 Subject: drm/nouveau/devinit/nv50: return error code if pll calculation fails Reported-by: Dan Carpenter Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c index c714b09..59362f8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c @@ -50,7 +50,7 @@ nv50_devinit_pll_set(struct nvkm_devinit *init, u32 type, u32 freq) ret = nv04_pll_calc(subdev, &info, freq, &N1, &M1, &N2, &M2, &P); if (!ret) { nvkm_error(subdev, "failed pll calculation\n"); - return ret; + return -EINVAL; } switch (info.type) { -- cgit v1.1 From 725af748266727c4aebdfa7e02c2e289435a4d3b Mon Sep 17 00:00:00 2001 From: Karol Herbst Date: Sun, 20 Nov 2016 00:43:14 +0100 Subject: drm/nouveau/pci: Rename g94 to g92 Signed-off-by: Karol Herbst Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/device/base.c | 20 ++++---- drivers/gpu/drm/nouveau/nvkm/subdev/pci/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/pci/g92.c | 57 +++++++++++++++++++++++ drivers/gpu/drm/nouveau/nvkm/subdev/pci/g94.c | 57 ----------------------- drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf100.c | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf106.c | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/pci/priv.h | 2 +- 8 files changed, 72 insertions(+), 72 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/pci/g92.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/pci/g94.c (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h index e6523e2..2592d86 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h @@ -43,7 +43,7 @@ int nv40_pci_new(struct nvkm_device *, int, struct nvkm_pci **); int nv46_pci_new(struct nvkm_device *, int, struct nvkm_pci **); int nv4c_pci_new(struct nvkm_device *, int, struct nvkm_pci **); int g84_pci_new(struct nvkm_device *, int, struct nvkm_pci **); -int g94_pci_new(struct nvkm_device *, int, struct nvkm_pci **); +int g92_pci_new(struct nvkm_device *, int, struct nvkm_pci **); int gf100_pci_new(struct nvkm_device *, int, struct nvkm_pci **); int gf106_pci_new(struct nvkm_device *, int, struct nvkm_pci **); int gk104_pci_new(struct nvkm_device *, int, struct nvkm_pci **); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index 7079612..eb4b016 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -1025,7 +1025,7 @@ nv94_chipset = { .mc = g84_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, - .pci = g94_pci_new, + .pci = g92_pci_new, .therm = g84_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, @@ -1057,7 +1057,7 @@ nv96_chipset = { .mc = g84_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, - .pci = g94_pci_new, + .pci = g92_pci_new, .therm = g84_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, @@ -1089,7 +1089,7 @@ nv98_chipset = { .mc = g98_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, - .pci = g94_pci_new, + .pci = g92_pci_new, .therm = g84_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, @@ -1121,7 +1121,7 @@ nva0_chipset = { .mc = g84_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, - .pci = g94_pci_new, + .pci = g92_pci_new, .therm = g84_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, @@ -1153,7 +1153,7 @@ nva3_chipset = { .mc = gt215_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, - .pci = g94_pci_new, + .pci = g92_pci_new, .pmu = gt215_pmu_new, .therm = gt215_therm_new, .timer = nv41_timer_new, @@ -1187,7 +1187,7 @@ nva5_chipset = { .mc = gt215_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, - .pci = g94_pci_new, + .pci = g92_pci_new, .pmu = gt215_pmu_new, .therm = gt215_therm_new, .timer = nv41_timer_new, @@ -1220,7 +1220,7 @@ nva8_chipset = { .mc = gt215_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, - .pci = g94_pci_new, + .pci = g92_pci_new, .pmu = gt215_pmu_new, .therm = gt215_therm_new, .timer = nv41_timer_new, @@ -1253,7 +1253,7 @@ nvaa_chipset = { .mc = g98_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, - .pci = g94_pci_new, + .pci = g92_pci_new, .therm = g84_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, @@ -1285,7 +1285,7 @@ nvac_chipset = { .mc = g98_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, - .pci = g94_pci_new, + .pci = g92_pci_new, .therm = g84_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, @@ -1317,7 +1317,7 @@ nvaf_chipset = { .mc = gt215_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, - .pci = g94_pci_new, + .pci = g92_pci_new, .pmu = gt215_pmu_new, .therm = gt215_therm_new, .timer = nv41_timer_new, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/Kbuild index 2a31b7d..cdb7ce2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/Kbuild @@ -6,7 +6,7 @@ nvkm-y += nvkm/subdev/pci/nv40.o nvkm-y += nvkm/subdev/pci/nv46.o nvkm-y += nvkm/subdev/pci/nv4c.o nvkm-y += nvkm/subdev/pci/g84.o -nvkm-y += nvkm/subdev/pci/g94.o +nvkm-y += nvkm/subdev/pci/g92.o nvkm-y += nvkm/subdev/pci/gf100.o nvkm-y += nvkm/subdev/pci/gf106.o nvkm-y += nvkm/subdev/pci/gk104.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g92.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g92.c new file mode 100644 index 0000000..654607e --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g92.c @@ -0,0 +1,57 @@ +/* + * Copyright 2015 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "priv.h" + +int +g92_pcie_version_supported(struct nvkm_pci *pci) +{ + if ((nvkm_pci_rd32(pci, 0x460) & 0x200) == 0x200) + return 2; + return 1; +} + +static const struct nvkm_pci_func +g92_pci_func = { + .init = g84_pci_init, + .rd32 = nv40_pci_rd32, + .wr08 = nv40_pci_wr08, + .wr32 = nv40_pci_wr32, + .msi_rearm = nv40_pci_msi_rearm, + + .pcie.init = g84_pcie_init, + .pcie.set_link = g84_pcie_set_link, + + .pcie.max_speed = g84_pcie_max_speed, + .pcie.cur_speed = g84_pcie_cur_speed, + + .pcie.set_version = g84_pcie_set_version, + .pcie.version = g84_pcie_version, + .pcie.version_supported = g92_pcie_version_supported, +}; + +int +g92_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci) +{ + return nvkm_pci_new_(&g92_pci_func, device, index, ppci); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g94.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g94.c deleted file mode 100644 index 4344412..0000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g94.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright 2015 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ -#include "priv.h" - -int -g94_pcie_version_supported(struct nvkm_pci *pci) -{ - if ((nvkm_pci_rd32(pci, 0x460) & 0x200) == 0x200) - return 2; - return 1; -} - -static const struct nvkm_pci_func -g94_pci_func = { - .init = g84_pci_init, - .rd32 = nv40_pci_rd32, - .wr08 = nv40_pci_wr08, - .wr32 = nv40_pci_wr32, - .msi_rearm = nv40_pci_msi_rearm, - - .pcie.init = g84_pcie_init, - .pcie.set_link = g84_pcie_set_link, - - .pcie.max_speed = g84_pcie_max_speed, - .pcie.cur_speed = g84_pcie_cur_speed, - - .pcie.set_version = g84_pcie_set_version, - .pcie.version = g84_pcie_version, - .pcie.version_supported = g94_pcie_version_supported, -}; - -int -g94_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci) -{ - return nvkm_pci_new_(&g94_pci_func, device, index, ppci); -} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf100.c index e30ea67..00a5e7d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf100.c @@ -92,7 +92,7 @@ gf100_pci_func = { .pcie.set_version = gf100_pcie_set_version, .pcie.version = gf100_pcie_version, - .pcie.version_supported = g94_pcie_version_supported, + .pcie.version_supported = g92_pcie_version_supported, }; int diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf106.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf106.c index c3b798c..11bf419 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf106.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf106.c @@ -39,7 +39,7 @@ gf106_pci_func = { .pcie.set_version = gf100_pcie_set_version, .pcie.version = gf100_pcie_version, - .pcie.version_supported = g94_pcie_version_supported, + .pcie.version_supported = g92_pcie_version_supported, }; int diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/priv.h index 23de318..86921ec 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/priv.h @@ -44,7 +44,7 @@ enum nvkm_pcie_speed g84_pcie_max_speed(struct nvkm_pci *); int g84_pcie_init(struct nvkm_pci *); int g84_pcie_set_link(struct nvkm_pci *, enum nvkm_pcie_speed, u8); -int g94_pcie_version_supported(struct nvkm_pci *); +int g92_pcie_version_supported(struct nvkm_pci *); void gf100_pcie_set_version(struct nvkm_pci *, u8); int gf100_pcie_version(struct nvkm_pci *); -- cgit v1.1 From 443828fd9e6097464aa3fd32199bbba3a3bf7e88 Mon Sep 17 00:00:00 2001 From: Karol Herbst Date: Sun, 20 Nov 2016 00:43:15 +0100 Subject: drm/nouveau/pci/g92: Enable changing pcie link speeds Tested on a G92, seems to work. Confirmed by 8 mmiotraces. Signed-off-by: Karol Herbst Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/engine/device/base.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index eb4b016..f40273c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -993,7 +993,7 @@ nv92_chipset = { .mc = g84_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, - .pci = g84_pci_new, + .pci = g92_pci_new, .therm = g84_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, -- cgit v1.1 From ca33fafdc9020720a9773fd416c94fe68aef7220 Mon Sep 17 00:00:00 2001 From: Martin Peres Date: Wed, 18 Jan 2017 23:49:21 +0200 Subject: drm/nouveau/drm/nouveau/led: prevent a possible use-after-free If the led class registration fails, we free drm->led but do not reset it to NULL, which means that the suspend/resume/fini function will act as if everything went well in init() and will likely crash the kernel. This patch adds the missing drm->led = NULL. Reported-by: Emmanuel Pescosta Signed-off-by: Martin Peres Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_led.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nouveau_led.c b/drivers/gpu/drm/nouveau/nouveau_led.c index 72456b1..2c5e062 100644 --- a/drivers/gpu/drm/nouveau/nouveau_led.c +++ b/drivers/gpu/drm/nouveau/nouveau_led.c @@ -102,6 +102,7 @@ nouveau_led_init(struct drm_device *dev) ret = led_classdev_register(dev->dev, &drm->led->led); if (ret) { kfree(drm->led); + drm->led = NULL; return ret; } -- cgit v1.1 From 86d7442baa6ec9f563343fd8515531201312de44 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 5 Nov 2016 14:14:20 +1000 Subject: drm/nouveau/core: increase maximum number of notifies that a client can request Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvkm/core/client.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/client.h b/drivers/gpu/drm/nouveau/include/nvkm/core/client.h index e4123192..e876634 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/client.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/client.h @@ -9,7 +9,7 @@ struct nvkm_client { u64 device; u32 debug; - struct nvkm_client_notify *notify[16]; + struct nvkm_client_notify *notify[32]; struct rb_root objroot; bool super; -- cgit v1.1 From e774055a074b6715193c2984024eecf8fdf8dbd1 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 5 Nov 2016 13:12:57 +1000 Subject: drm/nouveau/fifo: tidy up channel creation event code Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c | 16 +++++++++++----- drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h | 1 + 3 files changed, 13 insertions(+), 6 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c index 1c9682a..4a01afe 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c @@ -91,8 +91,8 @@ nvkm_fifo_chan_chid(struct nvkm_fifo *fifo, int chid, unsigned long *rflags) } static int -nvkm_fifo_event_ctor(struct nvkm_object *object, void *data, u32 size, - struct nvkm_notify *notify) +nvkm_fifo_cevent_ctor(struct nvkm_object *object, void *data, u32 size, + struct nvkm_notify *notify) { if (size == 0) { notify->size = 0; @@ -104,10 +104,16 @@ nvkm_fifo_event_ctor(struct nvkm_object *object, void *data, u32 size, } static const struct nvkm_event_func -nvkm_fifo_event_func = { - .ctor = nvkm_fifo_event_ctor, +nvkm_fifo_cevent_func = { + .ctor = nvkm_fifo_cevent_ctor, }; +void +nvkm_fifo_cevent(struct nvkm_fifo *fifo) +{ + nvkm_event_send(&fifo->cevent, 1, 0, NULL, 0); +} + static void nvkm_fifo_uevent_fini(struct nvkm_event *event, int type, int index) { @@ -283,5 +289,5 @@ nvkm_fifo_ctor(const struct nvkm_fifo_func *func, struct nvkm_device *device, return ret; } - return nvkm_event_init(&nvkm_fifo_event_func, 1, 1, &fifo->cevent); + return nvkm_event_init(&nvkm_fifo_cevent_func, 1, 1, &fifo->cevent); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c index 3b87e09..fab760a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c @@ -410,6 +410,6 @@ nvkm_fifo_chan_ctor(const struct nvkm_fifo_chan_func *func, base + user * chan->chid; chan->size = user; - nvkm_event_send(&fifo->cevent, 1, 0, NULL, 0); + nvkm_fifo_cevent(fifo); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h index f6dfb37..9bf0251 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h @@ -6,6 +6,7 @@ int nvkm_fifo_ctor(const struct nvkm_fifo_func *, struct nvkm_device *, int index, int nr, struct nvkm_fifo *); void nvkm_fifo_uevent(struct nvkm_fifo *); +void nvkm_fifo_cevent(struct nvkm_fifo *); struct nvkm_fifo_chan_oclass; struct nvkm_fifo_func { -- cgit v1.1 From 40cea73984a77acb714e1d4a60a47fdfb07b656f Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 24 Jan 2017 16:08:14 +1000 Subject: drm/nouveau/fifo/g84-: rename non-stall interrupt event Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvif/cl826e.h | 2 +- drivers/gpu/drm/nouveau/include/nvif/cl826f.h | 2 +- drivers/gpu/drm/nouveau/include/nvif/cl906f.h | 2 +- drivers/gpu/drm/nouveau/include/nvif/cla06f.h | 2 +- drivers/gpu/drm/nouveau/nouveau_fence.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl826e.h b/drivers/gpu/drm/nouveau/include/nvif/cl826e.h index 05e6ef7..91e33db 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/cl826e.h +++ b/drivers/gpu/drm/nouveau/include/nvif/cl826e.h @@ -10,5 +10,5 @@ struct g82_channel_dma_v0 { __u64 offset; }; -#define G82_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 +#define NV826E_V0_NTFY_NON_STALL_INTERRUPT 0x00 #endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl826f.h b/drivers/gpu/drm/nouveau/include/nvif/cl826f.h index cecafcb..e34efd4 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/cl826f.h +++ b/drivers/gpu/drm/nouveau/include/nvif/cl826f.h @@ -11,5 +11,5 @@ struct g82_channel_gpfifo_v0 { __u64 vm; }; -#define G82_CHANNEL_GPFIFO_V0_NTFY_UEVENT 0x00 +#define NV826F_V0_NTFY_NON_STALL_INTERRUPT 0x00 #endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl906f.h b/drivers/gpu/drm/nouveau/include/nvif/cl906f.h index 2caf083..e9302ec 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/cl906f.h +++ b/drivers/gpu/drm/nouveau/include/nvif/cl906f.h @@ -10,5 +10,5 @@ struct fermi_channel_gpfifo_v0 { __u64 vm; }; -#define FERMI_CHANNEL_GPFIFO_V0_NTFY_UEVENT 0x00 +#define NV906F_V0_NTFY_NON_STALL_INTERRUPT 0x00 #endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/cla06f.h b/drivers/gpu/drm/nouveau/include/nvif/cla06f.h index 46301ec..567123a 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/cla06f.h +++ b/drivers/gpu/drm/nouveau/include/nvif/cla06f.h @@ -25,5 +25,5 @@ struct kepler_channel_gpfifo_a_v0 { __u64 vm; }; -#define NVA06F_V0_NTFY_UEVENT 0x00 +#define NVA06F_V0_NTFY_NON_STALL_INTERRUPT 0x00 #endif diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.c b/drivers/gpu/drm/nouveau/nouveau_fence.c index a6126c9..f3e551f 100644 --- a/drivers/gpu/drm/nouveau/nouveau_fence.c +++ b/drivers/gpu/drm/nouveau/nouveau_fence.c @@ -190,7 +190,7 @@ nouveau_fence_context_new(struct nouveau_channel *chan, struct nouveau_fence_cha return; ret = nvif_notify_init(&chan->user, nouveau_fence_wait_uevent_handler, - false, G82_CHANNEL_DMA_V0_NTFY_UEVENT, + false, NV826E_V0_NTFY_NON_STALL_INTERRUPT, &(struct nvif_notify_uevent_req) { }, sizeof(struct nvif_notify_uevent_req), sizeof(struct nvif_notify_uevent_rep), diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c index 15a992b..66bd1cd 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c @@ -35,7 +35,7 @@ g84_fifo_chan_ntfy(struct nvkm_fifo_chan *chan, u32 type, struct nvkm_event **pevent) { switch (type) { - case G82_CHANNEL_DMA_V0_NTFY_UEVENT: + case NV826E_V0_NTFY_NON_STALL_INTERRUPT: *pevent = &chan->fifo->uevent; return 0; default: -- cgit v1.1 From ff9f29abf0ef4c43e696bef7621884518e6bdbda Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 5 Nov 2016 13:05:14 +1000 Subject: drm/nouveau/fifo/gf100-: provide notification to user if channel is killed There are instances (such as non-recoverable GPU page faults) where NVKM decides that a channel's context is no longer viable, and will be removed from the runlist. This commit notifies the owner of the channel when this happens, so it has the opportunity to take some kind of recovery action instead of hanging. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvif/cl906f.h | 1 + drivers/gpu/drm/nouveau/include/nvif/cla06f.h | 1 + drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h | 1 + drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c | 32 +++++++++++++++++++++- drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c | 1 + drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c | 1 + .../gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c | 19 ++++++++++++- .../gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h | 1 + 11 files changed, 58 insertions(+), 5 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl906f.h b/drivers/gpu/drm/nouveau/include/nvif/cl906f.h index e9302ec..a2d5410 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/cl906f.h +++ b/drivers/gpu/drm/nouveau/include/nvif/cl906f.h @@ -11,4 +11,5 @@ struct fermi_channel_gpfifo_v0 { }; #define NV906F_V0_NTFY_NON_STALL_INTERRUPT 0x00 +#define NV906F_V0_NTFY_KILLED 0x01 #endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/cla06f.h b/drivers/gpu/drm/nouveau/include/nvif/cla06f.h index 567123a..2efa3d0 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/cla06f.h +++ b/drivers/gpu/drm/nouveau/include/nvif/cla06f.h @@ -26,4 +26,5 @@ struct kepler_channel_gpfifo_a_v0 { }; #define NVA06F_V0_NTFY_NON_STALL_INTERRUPT 0x00 +#define NVA06F_V0_NTFY_KILLED 0x01 #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h index ed92fec..24efa90 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h @@ -40,6 +40,7 @@ struct nvkm_fifo { struct nvkm_event uevent; /* async user trigger */ struct nvkm_event cevent; /* channel creation event */ + struct nvkm_event kevent; /* channel killed */ }; void nvkm_fifo_pause(struct nvkm_fifo *, unsigned long *); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c index 4a01afe..3567c99 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c @@ -90,6 +90,31 @@ nvkm_fifo_chan_chid(struct nvkm_fifo *fifo, int chid, unsigned long *rflags) return NULL; } +void +nvkm_fifo_kevent(struct nvkm_fifo *fifo, int chid) +{ + nvkm_event_send(&fifo->kevent, 1, chid, NULL, 0); +} + +static int +nvkm_fifo_kevent_ctor(struct nvkm_object *object, void *data, u32 size, + struct nvkm_notify *notify) +{ + struct nvkm_fifo_chan *chan = nvkm_fifo_chan(object); + if (size == 0) { + notify->size = 0; + notify->types = 1; + notify->index = chan->chid; + return 0; + } + return -ENOSYS; +} + +static const struct nvkm_event_func +nvkm_fifo_kevent_func = { + .ctor = nvkm_fifo_kevent_ctor, +}; + static int nvkm_fifo_cevent_ctor(struct nvkm_object *object, void *data, u32 size, struct nvkm_notify *notify) @@ -247,6 +272,7 @@ nvkm_fifo_dtor(struct nvkm_engine *engine) void *data = fifo; if (fifo->func->dtor) data = fifo->func->dtor(fifo); + nvkm_event_fini(&fifo->kevent); nvkm_event_fini(&fifo->cevent); nvkm_event_fini(&fifo->uevent); return data; @@ -289,5 +315,9 @@ nvkm_fifo_ctor(const struct nvkm_fifo_func *func, struct nvkm_device *device, return ret; } - return nvkm_event_init(&nvkm_fifo_cevent_func, 1, 1, &fifo->cevent); + ret = nvkm_event_init(&nvkm_fifo_cevent_func, 1, 1, &fifo->cevent); + if (ret) + return ret; + + return nvkm_event_init(&nvkm_fifo_kevent_func, 1, nr, &fifo->kevent); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.h index 55dc415..d8019bd 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.h @@ -29,5 +29,5 @@ struct nvkm_fifo_chan_oclass { struct nvkm_sclass base; }; -int g84_fifo_chan_ntfy(struct nvkm_fifo_chan *, u32, struct nvkm_event **); +int gf100_fifo_chan_ntfy(struct nvkm_fifo_chan *, u32, struct nvkm_event **); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c index 66bd1cd..61797c4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c @@ -30,7 +30,7 @@ #include -int +static int g84_fifo_chan_ntfy(struct nvkm_fifo_chan *chan, u32 type, struct nvkm_event **pevent) { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c index 8772a99..cd468ab 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c @@ -190,6 +190,7 @@ gf100_fifo_recover(struct gf100_fifo *fifo, struct nvkm_engine *engine, if (engine != &fifo->base.engine) fifo->recover.mask |= 1ULL << engine->subdev.index; schedule_work(&fifo->recover.work); + nvkm_fifo_kevent(&fifo->base, chid); } static const struct nvkm_enum diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c index 73ae4ec..67a6a51 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c @@ -178,6 +178,7 @@ gk104_fifo_recover(struct gk104_fifo *fifo, struct nvkm_engine *engine, fifo->recover.runm |= BIT(chan->runl); schedule_work(&fifo->recover.work); + nvkm_fifo_kevent(&fifo->base, chid); } static const struct nvkm_enum diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c index 12d96426..f9e0377 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c @@ -32,6 +32,23 @@ #include #include +int +gf100_fifo_chan_ntfy(struct nvkm_fifo_chan *chan, u32 type, + struct nvkm_event **pevent) +{ + switch (type) { + case NV906F_V0_NTFY_NON_STALL_INTERRUPT: + *pevent = &chan->fifo->uevent; + return 0; + case NV906F_V0_NTFY_KILLED: + *pevent = &chan->fifo->kevent; + return 0; + default: + break; + } + return -EINVAL; +} + static u32 gf100_fifo_gpfifo_engine_addr(struct nvkm_engine *engine) { @@ -184,7 +201,7 @@ gf100_fifo_gpfifo_func = { .dtor = gf100_fifo_gpfifo_dtor, .init = gf100_fifo_gpfifo_init, .fini = gf100_fifo_gpfifo_fini, - .ntfy = g84_fifo_chan_ntfy, + .ntfy = gf100_fifo_chan_ntfy, .engine_ctor = gf100_fifo_gpfifo_engine_ctor, .engine_dtor = gf100_fifo_gpfifo_engine_dtor, .engine_init = gf100_fifo_gpfifo_engine_init, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c index a2df4f3..7f53869 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c @@ -213,7 +213,7 @@ gk104_fifo_gpfifo_func = { .dtor = gk104_fifo_gpfifo_dtor, .init = gk104_fifo_gpfifo_init, .fini = gk104_fifo_gpfifo_fini, - .ntfy = g84_fifo_chan_ntfy, + .ntfy = gf100_fifo_chan_ntfy, .engine_ctor = gk104_fifo_gpfifo_engine_ctor, .engine_dtor = gk104_fifo_gpfifo_engine_dtor, .engine_init = gk104_fifo_gpfifo_engine_init, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h index 9bf0251..1fc9d8b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h @@ -7,6 +7,7 @@ int nvkm_fifo_ctor(const struct nvkm_fifo_func *, struct nvkm_device *, int index, int nr, struct nvkm_fifo *); void nvkm_fifo_uevent(struct nvkm_fifo *); void nvkm_fifo_cevent(struct nvkm_fifo *); +void nvkm_fifo_kevent(struct nvkm_fifo *, int chid); struct nvkm_fifo_chan_oclass; struct nvkm_fifo_func { -- cgit v1.1 From d8cc37d878d695fc2a88b4777cdfea8bca9fdcb5 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 5 Nov 2016 13:31:25 +1000 Subject: drm/nouveau: request notifications for channels that have been killed These will be used to improve error recovery behaviour. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_chan.c | 26 ++++++++++++++++++++++++++ drivers/gpu/drm/nouveau/nouveau_chan.h | 5 ++++- 2 files changed, 30 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.c b/drivers/gpu/drm/nouveau/nouveau_chan.c index d50c6e5..3b3d071 100644 --- a/drivers/gpu/drm/nouveau/nouveau_chan.c +++ b/drivers/gpu/drm/nouveau/nouveau_chan.c @@ -45,6 +45,16 @@ MODULE_PARM_DESC(vram_pushbuf, "Create DMA push buffers in VRAM"); int nouveau_vram_pushbuf; module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400); +static int +nouveau_channel_killed(struct nvif_notify *ntfy) +{ + struct nouveau_channel *chan = container_of(ntfy, typeof(*chan), kill); + struct nouveau_cli *cli = (void *)chan->user.client; + NV_PRINTK(warn, cli, "channel %d killed!\n", chan->chid); + atomic_set(&chan->killed, 1); + return NVIF_NOTIFY_DROP; +} + int nouveau_channel_idle(struct nouveau_channel *chan) { @@ -78,6 +88,7 @@ nouveau_channel_del(struct nouveau_channel **pchan) nvif_object_fini(&chan->nvsw); nvif_object_fini(&chan->gart); nvif_object_fini(&chan->vram); + nvif_notify_fini(&chan->kill); nvif_object_fini(&chan->user); nvif_object_fini(&chan->push.ctxdma); nouveau_bo_vma_del(chan->push.buffer, &chan->push.vma); @@ -107,6 +118,7 @@ nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device, chan->device = device; chan->drm = drm; + atomic_set(&chan->killed, 0); /* allocate memory for dma push buffer */ target = TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED; @@ -301,12 +313,26 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) { struct nvif_device *device = chan->device; struct nouveau_cli *cli = (void *)chan->user.client; + struct nouveau_drm *drm = chan->drm; struct nvkm_mmu *mmu = nvxx_mmu(device); struct nv_dma_v0 args = {}; int ret, i; nvif_object_map(&chan->user); + if (chan->user.oclass >= FERMI_CHANNEL_GPFIFO) { + ret = nvif_notify_init(&chan->user, nouveau_channel_killed, + true, NV906F_V0_NTFY_KILLED, + NULL, 0, 0, &chan->kill); + if (ret == 0) + ret = nvif_notify_get(&chan->kill); + if (ret) { + NV_ERROR(drm, "Failed to request channel kill " + "notification: %d\n", ret); + return ret; + } + } + /* allocate dma objects to cover all allowed vram, and gart */ if (device->info.family < NV_DEVICE_INFO_V0_FERMI) { if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) { diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.h b/drivers/gpu/drm/nouveau/nouveau_chan.h index 48062c9..46b947b 100644 --- a/drivers/gpu/drm/nouveau/nouveau_chan.h +++ b/drivers/gpu/drm/nouveau/nouveau_chan.h @@ -1,7 +1,7 @@ #ifndef __NOUVEAU_CHAN_H__ #define __NOUVEAU_CHAN_H__ - #include +#include struct nvif_device; struct nouveau_channel { @@ -38,6 +38,9 @@ struct nouveau_channel { u32 user_put; struct nvif_object user; + + struct nvif_notify kill; + atomic_t killed; }; -- cgit v1.1 From 84cd0a55659ad7ab5792d5319b315e1e5bba312a Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 24 Jan 2017 16:56:52 +1000 Subject: drm/nouveau: check for dead channel before trying to idle This prevents *very* long waits while attempting to destroy channels after a fault has occurred. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_chan.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.c b/drivers/gpu/drm/nouveau/nouveau_chan.c index 3b3d071..dbc41fa 100644 --- a/drivers/gpu/drm/nouveau/nouveau_chan.c +++ b/drivers/gpu/drm/nouveau/nouveau_chan.c @@ -58,7 +58,7 @@ nouveau_channel_killed(struct nvif_notify *ntfy) int nouveau_channel_idle(struct nouveau_channel *chan) { - if (likely(chan && chan->fence)) { + if (likely(chan && chan->fence && !atomic_read(&chan->killed))) { struct nouveau_cli *cli = (void *)chan->user.client; struct nouveau_fence *fence = NULL; int ret; -- cgit v1.1 From 17041c7eef2efb998b28f770442156401701cd3c Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 16 Jan 2017 10:22:59 +1000 Subject: drm/nouveau/core: add engine method to assist in determining chsw direction FIFO gives us load/save/switch status, and we need to be able to determine which direction a "switch" is failing during channel recovery. In order to do this, we apparently need to query the engine itself. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvkm/core/engine.h | 2 ++ drivers/gpu/drm/nouveau/nvkm/core/engine.c | 8 ++++++++ 2 files changed, 10 insertions(+) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/engine.h b/drivers/gpu/drm/nouveau/include/nvkm/core/engine.h index 9ebfd87..d4cd2fb 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/engine.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/engine.h @@ -20,6 +20,7 @@ struct nvkm_engine_func { int (*fini)(struct nvkm_engine *, bool suspend); void (*intr)(struct nvkm_engine *); void (*tile)(struct nvkm_engine *, int region, struct nvkm_fb_tile *); + bool (*chsw_load)(struct nvkm_engine *); struct { int (*sclass)(struct nvkm_oclass *, int index, @@ -44,4 +45,5 @@ int nvkm_engine_new_(const struct nvkm_engine_func *, struct nvkm_device *, struct nvkm_engine *nvkm_engine_ref(struct nvkm_engine *); void nvkm_engine_unref(struct nvkm_engine **); void nvkm_engine_tile(struct nvkm_engine *, int region); +bool nvkm_engine_chsw_load(struct nvkm_engine *); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/core/engine.c b/drivers/gpu/drm/nouveau/nvkm/core/engine.c index ee8e583..b6c9169 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/engine.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/engine.c @@ -27,6 +27,14 @@ #include +bool +nvkm_engine_chsw_load(struct nvkm_engine *engine) +{ + if (engine->func->chsw_load) + return engine->func->chsw_load(engine); + return false; +} + void nvkm_engine_unref(struct nvkm_engine **pengine) { -- cgit v1.1 From 71ce33a28a06fed624b796189c14d960684cf830 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 16 Jan 2017 10:25:10 +1000 Subject: drm/nouveau/gr: implement chsw_load() method Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c | 10 ++++++++++ drivers/gpu/drm/nouveau/nvkm/engine/gr/priv.h | 1 + 2 files changed, 11 insertions(+) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c index a8282ed..cd8cf6f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c @@ -25,6 +25,15 @@ #include +static bool +nvkm_gr_chsw_load(struct nvkm_engine *engine) +{ + struct nvkm_gr *gr = nvkm_gr(engine); + if (gr->func->chsw_load) + return gr->func->chsw_load(gr); + return false; +} + static void nvkm_gr_tile(struct nvkm_engine *engine, int region, struct nvkm_fb_tile *tile) { @@ -132,6 +141,7 @@ nvkm_gr = { .fini = nvkm_gr_fini, .intr = nvkm_gr_intr, .tile = nvkm_gr_tile, + .chsw_load = nvkm_gr_chsw_load, .fifo.cclass = nvkm_gr_cclass_new, .fifo.sclass = nvkm_gr_oclass_get, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/priv.h index 0d6d940..2a52d9f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/priv.h @@ -25,6 +25,7 @@ struct nvkm_gr_func { /* Returns chipset-specific counts of units packed into an u64. */ u64 (*units)(struct nvkm_gr *); + bool (*chsw_load)(struct nvkm_gr *); struct nvkm_sclass sclass[]; }; -- cgit v1.1 From 6845c313f79fd44c64834b98d4341187e77b2377 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 16 Jan 2017 10:28:54 +1000 Subject: drm/nouveau/gr/gf100-: implement chsw_load() method Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c index 88aa0b7..f9acb8a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c @@ -702,6 +702,22 @@ gf100_gr_pack_mmio[] = { * PGRAPH engine/subdev functions ******************************************************************************/ +static bool +gf100_gr_chsw_load(struct nvkm_gr *base) +{ + struct gf100_gr *gr = gf100_gr(base); + if (!gr->firmware) { + u32 trace = nvkm_rd32(gr->base.engine.subdev.device, 0x40981c); + if (trace & 0x00000040) + return true; + } else { + u32 mthd = nvkm_rd32(gr->base.engine.subdev.device, 0x409808); + if (mthd & 0x00080000) + return true; + } + return false; +} + int gf100_gr_rops(struct gf100_gr *gr) { @@ -1770,6 +1786,7 @@ gf100_gr_ = { .units = gf100_gr_units, .chan_new = gf100_gr_chan_new, .object_get = gf100_gr_object_get, + .chsw_load = gf100_gr_chsw_load, }; int -- cgit v1.1 From 13416077e54354df19d3a4f98e574cce451cec2d Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 18 Jan 2017 14:57:01 +1000 Subject: drm/nouveau/top: add function to translate subdev index to mmu fault id Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvkm/subdev/top.h | 1 + drivers/gpu/drm/nouveau/nvkm/subdev/top/base.c | 14 ++++++++++++++ 2 files changed, 15 insertions(+) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/top.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/top.h index 71ebbfd..d23209b 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/top.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/top.h @@ -11,6 +11,7 @@ struct nvkm_top { u32 nvkm_top_reset(struct nvkm_device *, enum nvkm_devidx); u32 nvkm_top_intr(struct nvkm_device *, u32 intr, u64 *subdevs); u32 nvkm_top_intr_mask(struct nvkm_device *, enum nvkm_devidx); +int nvkm_top_fault_id(struct nvkm_device *, enum nvkm_devidx); enum nvkm_devidx nvkm_top_fault(struct nvkm_device *, int fault); enum nvkm_devidx nvkm_top_engine(struct nvkm_device *, int, int *runl, int *engn); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/top/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/top/base.c index fe063d5..67ada1d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/top/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/top/base.c @@ -95,6 +95,20 @@ nvkm_top_intr(struct nvkm_device *device, u32 intr, u64 *psubdevs) return intr & ~handled; } +int +nvkm_top_fault_id(struct nvkm_device *device, enum nvkm_devidx devidx) +{ + struct nvkm_top *top = device->top; + struct nvkm_top_device *info; + + list_for_each_entry(info, &top->device, head) { + if (info->index == devidx && info->fault >= 0) + return info->fault; + } + + return -ENOENT; +} + enum nvkm_devidx nvkm_top_fault(struct nvkm_device *device, int fault) { -- cgit v1.1 From 21e6de29bb12f82161c2822ebb85dbf9103de4c1 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 26 Jan 2017 12:10:24 +1000 Subject: drm/nouveau/fifo: add an api for initiating channel recovery This will be used by callers outside of fifo interrupt handlers. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c | 11 +++++++++++ drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h | 2 ++ 2 files changed, 13 insertions(+) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c index 3567c99..23f50f1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c @@ -32,6 +32,17 @@ #include void +nvkm_fifo_recover_chan(struct nvkm_fifo *fifo, int chid) +{ + unsigned long flags; + if (WARN_ON(!fifo->func->recover_chan)) + return; + spin_lock_irqsave(&fifo->lock, flags); + fifo->func->recover_chan(fifo, chid); + spin_unlock_irqrestore(&fifo->lock, flags); +} + +void nvkm_fifo_pause(struct nvkm_fifo *fifo, unsigned long *flags) { return fifo->func->pause(fifo, flags); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h index 1fc9d8b..78136d9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h @@ -8,6 +8,7 @@ int nvkm_fifo_ctor(const struct nvkm_fifo_func *, struct nvkm_device *, void nvkm_fifo_uevent(struct nvkm_fifo *); void nvkm_fifo_cevent(struct nvkm_fifo *); void nvkm_fifo_kevent(struct nvkm_fifo *, int chid); +void nvkm_fifo_recover_chan(struct nvkm_fifo *, int chid); struct nvkm_fifo_chan_oclass; struct nvkm_fifo_func { @@ -20,6 +21,7 @@ struct nvkm_fifo_func { void (*start)(struct nvkm_fifo *, unsigned long *); void (*uevent_init)(struct nvkm_fifo *); void (*uevent_fini)(struct nvkm_fifo *); + void (*recover_chan)(struct nvkm_fifo *, int chid); int (*class_get)(struct nvkm_fifo *, int index, const struct nvkm_fifo_chan_oclass **); const struct nvkm_fifo_chan_oclass *chan[]; -- cgit v1.1 From b88917fe0fbb1a8479545ba62496ff71d63b397b Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 16 Jan 2017 10:14:36 +1000 Subject: drm/nouveau/fifo/gk104-: separate out engine status parsing We'll be wanting to reuse this logic in more places. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c | 59 ++++++++++++++++++------ 1 file changed, 46 insertions(+), 13 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c index 67a6a51..6d12a2e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c @@ -32,6 +32,47 @@ #include +struct gk104_fifo_engine_status { + bool busy; + bool faulted; + bool chsw; + bool save; + bool load; + struct { + bool tsg; + u32 id; + } prev, next, *chan; +}; + +static void +gk104_fifo_engine_status(struct gk104_fifo *fifo, int engn, + struct gk104_fifo_engine_status *status) +{ + struct nvkm_subdev *subdev = &fifo->base.engine.subdev; + struct nvkm_device *device = subdev->device; + u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x08)); + + status->busy = !!(stat & 0x80000000); + status->faulted = !!(stat & 0x40000000); + status->next.tsg = !!(stat & 0x10000000); + status->next.id = (stat & 0x0fff0000) >> 16; + status->chsw = !!(stat & 0x00008000); + status->save = !!(stat & 0x00004000); + status->load = !!(stat & 0x00002000); + status->prev.tsg = !!(stat & 0x00001000); + status->prev.id = (stat & 0x00000fff); + status->chan = status->load ? &status->next : &status->prev; + + nvkm_debug(subdev, "engine %02d: busy %d faulted %d chsw %d " + "save %d load %d %sid %d%s-> %sid %d%s\n", + engn, status->busy, status->faulted, + status->chsw, status->save, status->load, + status->prev.tsg ? "tsg" : "ch", status->prev.id, + status->chan == &status->prev ? "*" : " ", + status->next.tsg ? "tsg" : "ch", status->next.id, + status->chan == &status->next ? "*" : " "); +} + static int gk104_fifo_class_get(struct nvkm_fifo *base, int index, const struct nvkm_fifo_chan_oclass **psclass) @@ -214,7 +255,6 @@ gk104_fifo_sched_reason[] = { static void gk104_fifo_intr_sched_ctxsw(struct gk104_fifo *fifo) { - struct nvkm_device *device = fifo->base.engine.subdev.device; struct gk104_fifo_chan *chan; unsigned long flags; u32 engn; @@ -223,21 +263,14 @@ gk104_fifo_intr_sched_ctxsw(struct gk104_fifo *fifo) for (engn = 0; engn < fifo->engine_nr; engn++) { struct nvkm_engine *engine = fifo->engine[engn].engine; int runl = fifo->engine[engn].runl; - u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x08)); - u32 busy = (stat & 0x80000000); - u32 next = (stat & 0x0fff0000) >> 16; - u32 chsw = (stat & 0x00008000); - u32 save = (stat & 0x00004000); - u32 load = (stat & 0x00002000); - u32 prev = (stat & 0x00000fff); - u32 chid = load ? next : prev; - (void)save; - - if (!busy || !chsw) + struct gk104_fifo_engine_status status; + + gk104_fifo_engine_status(fifo, engn, &status); + if (!status.busy || !status.chsw) continue; list_for_each_entry(chan, &fifo->runlist[runl].chan, head) { - if (chan->base.chid == chid && engine) { + if (chan->base.chid == status.chan->id && engine) { gk104_fifo_recover(fifo, engine, chan); break; } -- cgit v1.1 From ec5c6bda19408b78f8bc0e0592c7805e8550470f Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 16 Jan 2017 10:36:00 +1000 Subject: drm/nouveau/fifo/gk104-: better detection of chid when parsing engine status The previous commit simply changes the interface, but should result in the same behaviour as previously. This commit has been split out from it as it can result in a different channel being selected. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c index 6d12a2e..32c3539 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c @@ -48,6 +48,7 @@ static void gk104_fifo_engine_status(struct gk104_fifo *fifo, int engn, struct gk104_fifo_engine_status *status) { + struct nvkm_engine *engine = fifo->engine[engn].engine; struct nvkm_subdev *subdev = &fifo->base.engine.subdev; struct nvkm_device *device = subdev->device; u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x08)); @@ -61,7 +62,24 @@ gk104_fifo_engine_status(struct gk104_fifo *fifo, int engn, status->load = !!(stat & 0x00002000); status->prev.tsg = !!(stat & 0x00001000); status->prev.id = (stat & 0x00000fff); - status->chan = status->load ? &status->next : &status->prev; + status->chan = NULL; + + if (status->busy && status->chsw) { + if (status->load && status->save) { + if (engine && nvkm_engine_chsw_load(engine)) + status->chan = &status->next; + else + status->chan = &status->prev; + } else + if (status->load) { + status->chan = &status->next; + } else { + status->chan = &status->prev; + } + } else + if (status->load) { + status->chan = &status->prev; + } nvkm_debug(subdev, "engine %02d: busy %d faulted %d chsw %d " "save %d load %d %sid %d%s-> %sid %d%s\n", -- cgit v1.1 From 0faaa47d440df5302132c47f8f84b3f61d9fc424 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 18 Jan 2017 15:22:43 +1000 Subject: drm/nouveau/fifo/gk104-: refactor recovery code This will serve as a basis for implementing some improvements to how we recover the GPU from channel errors. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c | 95 ++++++++++++++++++++---- 1 file changed, 81 insertions(+), 14 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c index 32c3539..c45f732 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include @@ -211,33 +212,98 @@ gk104_fifo_recover_work(struct work_struct *w) nvkm_mask(device, 0x002630, runm, 0x00000000); } +static void gk104_fifo_recover_engn(struct gk104_fifo *fifo, int engn); + static void -gk104_fifo_recover(struct gk104_fifo *fifo, struct nvkm_engine *engine, - struct gk104_fifo_chan *chan) +gk104_fifo_recover_runl(struct gk104_fifo *fifo, int runl) { struct nvkm_subdev *subdev = &fifo->base.engine.subdev; struct nvkm_device *device = subdev->device; - u32 chid = chan->base.chid; - int engn; + const u32 runm = BIT(runl); - nvkm_error(subdev, "%s engine fault on channel %d, recovering...\n", - nvkm_subdev_name[engine->subdev.index], chid); assert_spin_locked(&fifo->base.lock); + if (fifo->recover.runm & runm) + return; + fifo->recover.runm |= runm; - nvkm_mask(device, 0x800004 + (chid * 0x08), 0x00000800, 0x00000800); - list_del_init(&chan->head); - chan->killed = true; + /* Block runlist to prevent channel assignment(s) from changing. */ + nvkm_mask(device, 0x002630, runm, runm); - for (engn = 0; engn < fifo->engine_nr; engn++) { - if (fifo->engine[engn].engine == engine) { - fifo->recover.engm |= BIT(engn); + /* Schedule recovery. */ + nvkm_warn(subdev, "runlist %d: scheduled for recovery\n", runl); + schedule_work(&fifo->recover.work); +} + +static void +gk104_fifo_recover_chan(struct nvkm_fifo *base, int chid) +{ + struct gk104_fifo *fifo = gk104_fifo(base); + struct nvkm_subdev *subdev = &fifo->base.engine.subdev; + struct nvkm_device *device = subdev->device; + const u32 stat = nvkm_rd32(device, 0x800004 + (chid * 0x08)); + const u32 runl = (stat & 0x000f0000) >> 16; + const bool used = (stat & 0x00000001); + struct gk104_fifo_chan *chan; + + assert_spin_locked(&fifo->base.lock); + if (!used) + return; + + /* Lookup SW state for channel, and mark it as dead. */ + list_for_each_entry(chan, &fifo->runlist[runl].chan, head) { + if (chan->base.chid == chid) { + list_del_init(&chan->head); + chan->killed = true; + nvkm_fifo_kevent(&fifo->base, chid); break; } } - fifo->recover.runm |= BIT(chan->runl); + /* Disable channel. */ + nvkm_wr32(device, 0x800004 + (chid * 0x08), stat | 0x00000800); + nvkm_warn(subdev, "channel %d: killed\n", chid); +} + +static void +gk104_fifo_recover_engn(struct gk104_fifo *fifo, int engn) +{ + struct nvkm_subdev *subdev = &fifo->base.engine.subdev; + const u32 runl = fifo->engine[engn].runl; + const u32 engm = BIT(engn); + struct gk104_fifo_engine_status status; + + assert_spin_locked(&fifo->base.lock); + if (fifo->recover.engm & engm) + return; + fifo->recover.engm |= engm; + + /* Block channel assignments from changing during recovery. */ + gk104_fifo_recover_runl(fifo, runl); + + /* Determine which channel (if any) is currently on the engine. */ + gk104_fifo_engine_status(fifo, engn, &status); + if (status.chan) { + /* The channel is not longer viable, kill it. */ + gk104_fifo_recover_chan(&fifo->base, status.chan->id); + } + + /* Schedule recovery. */ + nvkm_warn(subdev, "engine %d: scheduled for recovery\n", engn); schedule_work(&fifo->recover.work); - nvkm_fifo_kevent(&fifo->base, chid); +} + +static void +gk104_fifo_recover(struct gk104_fifo *fifo, struct nvkm_engine *engine, + struct gk104_fifo_chan *chan) +{ + int engn; + for (engn = 0; engn < fifo->engine_nr; engn++) { + if (fifo->engine[engn].engine == engine) { + gk104_fifo_recover_engn(fifo, engn); + break; + } + } + gk104_fifo_recover_chan(&fifo->base, chan->base.chid); } static const struct nvkm_enum @@ -771,6 +837,7 @@ gk104_fifo_ = { .intr = gk104_fifo_intr, .uevent_init = gk104_fifo_uevent_init, .uevent_fini = gk104_fifo_uevent_fini, + .recover_chan = gk104_fifo_recover_chan, .class_get = gk104_fifo_class_get, }; -- cgit v1.1 From eaa5ed65eebb3ee9679a5f7b597c34a6207843c2 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 18 Jan 2017 15:35:16 +1000 Subject: drm/nouveau/fifo/gk104-: reset all engines a killed channel is still active on Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c index c45f732..4f17447 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c @@ -243,6 +243,7 @@ gk104_fifo_recover_chan(struct nvkm_fifo *base, int chid) const u32 stat = nvkm_rd32(device, 0x800004 + (chid * 0x08)); const u32 runl = (stat & 0x000f0000) >> 16; const bool used = (stat & 0x00000001); + unsigned long engn, engm = fifo->runlist[runl].engm; struct gk104_fifo_chan *chan; assert_spin_locked(&fifo->base.lock); @@ -262,6 +263,18 @@ gk104_fifo_recover_chan(struct nvkm_fifo *base, int chid) /* Disable channel. */ nvkm_wr32(device, 0x800004 + (chid * 0x08), stat | 0x00000800); nvkm_warn(subdev, "channel %d: killed\n", chid); + + /* Block channel assignments from changing during recovery. */ + gk104_fifo_recover_runl(fifo, runl); + + /* Schedule recovery for any engines the channel is on. */ + for_each_set_bit(engn, &engm, fifo->engine_nr) { + struct gk104_fifo_engine_status status; + gk104_fifo_engine_status(fifo, engn, &status); + if (!status.chan || status.chan->id != chid) + continue; + gk104_fifo_recover_engn(fifo, engn); + } } static void -- cgit v1.1 From 3534821df5e3635e3e7914a4802a74497815817e Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 18 Jan 2017 16:01:11 +1000 Subject: drm/nouveau/fifo/gk104-: directly use new recovery code for mmu faults Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c | 18 ++++++++++++++---- drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c | 24 ++++++++++++++++++++---- drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h | 3 +++ 3 files changed, 37 insertions(+), 8 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c index 23f50f1..660ca7a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c @@ -66,19 +66,29 @@ nvkm_fifo_chan_put(struct nvkm_fifo *fifo, unsigned long flags, } struct nvkm_fifo_chan * -nvkm_fifo_chan_inst(struct nvkm_fifo *fifo, u64 inst, unsigned long *rflags) +nvkm_fifo_chan_inst_locked(struct nvkm_fifo *fifo, u64 inst) { struct nvkm_fifo_chan *chan; - unsigned long flags; - spin_lock_irqsave(&fifo->lock, flags); list_for_each_entry(chan, &fifo->chan, head) { if (chan->inst->addr == inst) { list_del(&chan->head); list_add(&chan->head, &fifo->chan); - *rflags = flags; return chan; } } + return NULL; +} + +struct nvkm_fifo_chan * +nvkm_fifo_chan_inst(struct nvkm_fifo *fifo, u64 inst, unsigned long *rflags) +{ + struct nvkm_fifo_chan *chan; + unsigned long flags; + spin_lock_irqsave(&fifo->lock, flags); + if ((chan = nvkm_fifo_chan_inst_locked(fifo, inst))) { + *rflags = flags; + return chan; + } spin_unlock_irqrestore(&fifo->lock, flags); return NULL; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c index 4f17447..4422891 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c @@ -435,6 +435,7 @@ gk104_fifo_intr_fault(struct gk104_fifo *fifo, int unit) struct nvkm_fifo_chan *chan; unsigned long flags; char gpcid[8] = "", en[16] = ""; + int engn; er = nvkm_enum_find(fifo->func->fault.reason, reason); eu = nvkm_enum_find(fifo->func->fault.engine, unit); @@ -476,7 +477,8 @@ gk104_fifo_intr_fault(struct gk104_fifo *fifo, int unit) snprintf(en, sizeof(en), "%s", eu->name); } - chan = nvkm_fifo_chan_inst(&fifo->base, (u64)inst << 12, &flags); + spin_lock_irqsave(&fifo->base.lock, flags); + chan = nvkm_fifo_chan_inst_locked(&fifo->base, (u64)inst << 12); nvkm_error(subdev, "%s fault at %010llx engine %02x [%s] client %02x [%s%s] " @@ -487,9 +489,23 @@ gk104_fifo_intr_fault(struct gk104_fifo *fifo, int unit) (u64)inst << 12, chan ? chan->object.client->name : "unknown"); - if (engine && chan) - gk104_fifo_recover(fifo, engine, (void *)chan); - nvkm_fifo_chan_put(&fifo->base, flags, &chan); + + /* Kill the channel that caused the fault. */ + if (chan) + gk104_fifo_recover_chan(&fifo->base, chan->chid); + + /* Channel recovery will probably have already done this for the + * correct engine(s), but just in case we can't find the channel + * information... + */ + for (engn = 0; engn < fifo->engine_nr && engine; engn++) { + if (fifo->engine[engn].engine == engine) { + gk104_fifo_recover_engn(fifo, engn); + break; + } + } + + spin_unlock_irqrestore(&fifo->base.lock, flags); } static const struct nvkm_bitfield gk104_fifo_pbdma_intr_0[] = { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h index 78136d9..f889b13 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h @@ -10,6 +10,9 @@ void nvkm_fifo_cevent(struct nvkm_fifo *); void nvkm_fifo_kevent(struct nvkm_fifo *, int chid); void nvkm_fifo_recover_chan(struct nvkm_fifo *, int chid); +struct nvkm_fifo_chan * +nvkm_fifo_chan_inst_locked(struct nvkm_fifo *, u64 inst); + struct nvkm_fifo_chan_oclass; struct nvkm_fifo_func { void *(*dtor)(struct nvkm_fifo *); -- cgit v1.1 From 91b9d659abfd557f79a02c0bc1f92393fdba1e22 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 18 Jan 2017 16:03:44 +1000 Subject: drm/nouveau/fifo/gk104-: directly use new recovery code for ctxsw timeout Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c | 30 +++++------------------- 1 file changed, 6 insertions(+), 24 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c index 4422891..52aedd8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c @@ -305,20 +305,6 @@ gk104_fifo_recover_engn(struct gk104_fifo *fifo, int engn) schedule_work(&fifo->recover.work); } -static void -gk104_fifo_recover(struct gk104_fifo *fifo, struct nvkm_engine *engine, - struct gk104_fifo_chan *chan) -{ - int engn; - for (engn = 0; engn < fifo->engine_nr; engn++) { - if (fifo->engine[engn].engine == engine) { - gk104_fifo_recover_engn(fifo, engn); - break; - } - } - gk104_fifo_recover_chan(&fifo->base, chan->base.chid); -} - static const struct nvkm_enum gk104_fifo_bind_reason[] = { { 0x01, "BIND_NOT_UNBOUND" }, @@ -352,27 +338,23 @@ gk104_fifo_sched_reason[] = { static void gk104_fifo_intr_sched_ctxsw(struct gk104_fifo *fifo) { - struct gk104_fifo_chan *chan; - unsigned long flags; + unsigned long flags, engm = 0; u32 engn; spin_lock_irqsave(&fifo->base.lock, flags); for (engn = 0; engn < fifo->engine_nr; engn++) { - struct nvkm_engine *engine = fifo->engine[engn].engine; - int runl = fifo->engine[engn].runl; struct gk104_fifo_engine_status status; gk104_fifo_engine_status(fifo, engn, &status); if (!status.busy || !status.chsw) continue; - list_for_each_entry(chan, &fifo->runlist[runl].chan, head) { - if (chan->base.chid == status.chan->id && engine) { - gk104_fifo_recover(fifo, engine, chan); - break; - } - } + engm |= BIT(engn); } + + for_each_set_bit(engn, &engm, fifo->engine_nr) + gk104_fifo_recover_engn(fifo, engn); + spin_unlock_irqrestore(&fifo->base.lock, flags); } -- cgit v1.1 From 03f16f5f278af9ef477aa847fda4b09ed87dc382 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 18 Jan 2017 16:05:15 +1000 Subject: drm/nouveau/fifo/gk104-: ACK SCHED_ERROR before attempting CTXSW_TIMEOUT recovery Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c index 52aedd8..e4e68f6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c @@ -338,10 +338,17 @@ gk104_fifo_sched_reason[] = { static void gk104_fifo_intr_sched_ctxsw(struct gk104_fifo *fifo) { + struct nvkm_device *device = fifo->base.engine.subdev.device; unsigned long flags, engm = 0; u32 engn; + /* We need to ACK the SCHED_ERROR here, and prevent it reasserting, + * as MMU_FAULT cannot be triggered while it's pending. + */ spin_lock_irqsave(&fifo->base.lock, flags); + nvkm_mask(device, 0x002140, 0x00000100, 0x00000000); + nvkm_wr32(device, 0x002100, 0x00000100); + for (engn = 0; engn < fifo->engine_nr; engn++) { struct gk104_fifo_engine_status status; @@ -355,6 +362,7 @@ gk104_fifo_intr_sched_ctxsw(struct gk104_fifo *fifo) for_each_set_bit(engn, &engm, fifo->engine_nr) gk104_fifo_recover_engn(fifo, engn); + nvkm_mask(device, 0x002140, 0x00000100, 0x00000100); spin_unlock_irqrestore(&fifo->base.lock, flags); } -- cgit v1.1 From 3ebef76a1d46cd7e45aee6ad3efff9683b3a0f07 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 18 Jan 2017 15:37:24 +1000 Subject: drm/nouveau/fifo/gk104-: trigger mmu fault before attempting engine recovery Greatly improves the chances of recovering the GPU from a CTXSW_TIMEOUT. Tested with piglit's arb_shader_image_load_store-atomicity, which causes GR to hang in such a way that recovery failed (CTXSW_TIMEOUT continually re-triggers). Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c | 41 ++++++++++++++++++++++++ 1 file changed, 41 insertions(+) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c index e4e68f6..3a24788 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c @@ -280,10 +280,13 @@ gk104_fifo_recover_chan(struct nvkm_fifo *base, int chid) static void gk104_fifo_recover_engn(struct gk104_fifo *fifo, int engn) { + struct nvkm_engine *engine = fifo->engine[engn].engine; struct nvkm_subdev *subdev = &fifo->base.engine.subdev; + struct nvkm_device *device = subdev->device; const u32 runl = fifo->engine[engn].runl; const u32 engm = BIT(engn); struct gk104_fifo_engine_status status; + int mmui = -1; assert_spin_locked(&fifo->base.lock); if (fifo->recover.engm & engm) @@ -300,6 +303,44 @@ gk104_fifo_recover_engn(struct gk104_fifo *fifo, int engn) gk104_fifo_recover_chan(&fifo->base, status.chan->id); } + /* Determine MMU fault ID for the engine, if we're not being + * called from the fault handler already. + */ + if (!status.faulted && engine) { + mmui = nvkm_top_fault_id(device, engine->subdev.index); + if (mmui < 0) { + const struct nvkm_enum *en = fifo->func->fault.engine; + for (; en && en->name; en++) { + if (en->data2 == engine->subdev.index) { + mmui = en->value; + break; + } + } + } + WARN_ON(mmui < 0); + } + + /* Trigger a MMU fault for the engine. + * + * No good idea why this is needed, but nvgpu does something similar, + * and it makes recovery from CTXSW_TIMEOUT a lot more reliable. + */ + if (mmui >= 0) { + nvkm_wr32(device, 0x002a30 + (engn * 0x04), 0x00000100 | mmui); + + /* Wait for fault to trigger. */ + nvkm_msec(device, 2000, + gk104_fifo_engine_status(fifo, engn, &status); + if (status.faulted) + break; + ); + + /* Release MMU fault trigger, and ACK the fault. */ + nvkm_wr32(device, 0x002a30 + (engn * 0x04), 0x00000000); + nvkm_wr32(device, 0x00259c, BIT(mmui)); + nvkm_wr32(device, 0x002100, 0x10000000); + } + /* Schedule recovery. */ nvkm_warn(subdev, "engine %d: scheduled for recovery\n", engn); schedule_work(&fifo->recover.work); -- cgit v1.1 From 75d115f2aae145fd7dfed29703ce063e3e7bb716 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 18 Jan 2017 18:40:48 +1000 Subject: drm/nouveau/fifo/gk104-: preempt recovery Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c index 7f53869..8abf6f8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c @@ -50,6 +50,7 @@ gk104_fifo_gpfifo_kick(struct gk104_fifo_chan *chan) ) < 0) { nvkm_error(subdev, "channel %d [%s] kick timeout\n", chan->base.chid, client->name); + nvkm_fifo_recover_chan(&fifo->base, chan->base.chid); ret = -ETIMEDOUT; } mutex_unlock(&subdev->mutex); -- cgit v1.1 From e5f8eabc0077ea3f77b3362e28d3969ae62e70f0 Mon Sep 17 00:00:00 2001 From: Karol Herbst Date: Mon, 23 Jan 2017 23:10:11 +0100 Subject: drm/nouveau/bios/power_budget: Add basic power budget parsing v2: Set entry to 0xff if not found Add cap entry for ver 0x30 tables Rework to fix memory leak v3: More error checks Simplify check for invalid entries v4: disable for ver 0x10 for now move assignments after the second last return Signed-off-by: Karol Herbst Signed-off-by: Ben Skeggs --- .../include/nvkm/subdev/bios/power_budget.h | 26 +++++ drivers/gpu/drm/nouveau/nvkm/subdev/bios/Kbuild | 1 + .../drm/nouveau/nvkm/subdev/bios/power_budget.c | 126 +++++++++++++++++++++ 3 files changed, 153 insertions(+) create mode 100644 drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/power_budget.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/bios/power_budget.c (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/power_budget.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/power_budget.h new file mode 100644 index 0000000..f5f4a14 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/power_budget.h @@ -0,0 +1,26 @@ +#ifndef __NVBIOS_POWER_BUDGET_H__ +#define __NVBIOS_POWER_BUDGET_H__ + +#include + +struct nvbios_power_budget_entry { + u32 min_w; + u32 avg_w; + u32 max_w; +}; + +struct nvbios_power_budget { + u32 offset; + u8 ver; + u8 hlen; + u8 elen; + u8 ecount; + u8 cap_entry; +}; + +int nvbios_power_budget_header(struct nvkm_bios *, + struct nvbios_power_budget *); +int nvbios_power_budget_entry(struct nvkm_bios *, struct nvbios_power_budget *, + u8 idx, struct nvbios_power_budget_entry *); + +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/Kbuild index be57220..6b4f1e0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/Kbuild @@ -19,6 +19,7 @@ nvkm-y += nvkm/subdev/bios/pcir.o nvkm-y += nvkm/subdev/bios/perf.o nvkm-y += nvkm/subdev/bios/pll.o nvkm-y += nvkm/subdev/bios/pmu.o +nvkm-y += nvkm/subdev/bios/power_budget.o nvkm-y += nvkm/subdev/bios/ramcfg.o nvkm-y += nvkm/subdev/bios/rammap.o nvkm-y += nvkm/subdev/bios/shadow.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/power_budget.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/power_budget.c new file mode 100644 index 0000000..617bfff --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/power_budget.c @@ -0,0 +1,126 @@ +/* + * Copyright 2016 Karol Herbst + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Karol Herbst + */ +#include +#include +#include + +static u32 +nvbios_power_budget_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, + u8 *len) +{ + struct bit_entry bit_P; + u32 power_budget; + + if (bit_entry(bios, 'P', &bit_P) || bit_P.version != 2 || + bit_P.length < 0x2c) + return 0; + + power_budget = nvbios_rd32(bios, bit_P.offset + 0x2c); + if (!power_budget) + return 0; + + *ver = nvbios_rd08(bios, power_budget); + switch (*ver) { + case 0x20: + case 0x30: + *hdr = nvbios_rd08(bios, power_budget + 0x1); + *len = nvbios_rd08(bios, power_budget + 0x2); + *cnt = nvbios_rd08(bios, power_budget + 0x3); + return power_budget; + default: + break; + } + + return 0; +} + +int +nvbios_power_budget_header(struct nvkm_bios *bios, + struct nvbios_power_budget *budget) +{ + struct nvkm_subdev *subdev = &bios->subdev; + u8 ver, hdr, cnt, len, cap_entry; + u32 header; + + if (!bios || !budget) + return -EINVAL; + + header = nvbios_power_budget_table(bios, &ver, &hdr, &cnt, &len); + if (!header || !cnt) + return -ENODEV; + + switch (ver) { + case 0x20: + cap_entry = nvbios_rd08(bios, header + 0x9); + break; + case 0x30: + cap_entry = nvbios_rd08(bios, header + 0xa); + break; + default: + cap_entry = 0xff; + } + + if (cap_entry >= cnt && cap_entry != 0xff) { + nvkm_warn(subdev, + "invalid cap_entry in power budget table found\n"); + budget->cap_entry = 0xff; + return -EINVAL; + } + + budget->offset = header; + budget->ver = ver; + budget->hlen = hdr; + budget->elen = len; + budget->ecount = cnt; + + budget->cap_entry = cap_entry; + + return 0; +} + +int +nvbios_power_budget_entry(struct nvkm_bios *bios, + struct nvbios_power_budget *budget, + u8 idx, struct nvbios_power_budget_entry *entry) +{ + u32 entry_offset; + + if (!bios || !budget || !budget->offset || idx >= budget->ecount + || !entry) + return -EINVAL; + + entry_offset = budget->offset + budget->hlen + idx * budget->elen; + + if (budget->ver >= 0x20) { + entry->min_w = nvbios_rd32(bios, entry_offset + 0x2); + entry->avg_w = nvbios_rd32(bios, entry_offset + 0x6); + entry->max_w = nvbios_rd32(bios, entry_offset + 0xa); + } else { + entry->min_w = 0; + entry->max_w = nvbios_rd32(bios, entry_offset + 0x2); + entry->avg_w = entry->max_w; + } + + return 0; +} -- cgit v1.1 From 1efc3c4b9f5410aa8bae10bd4dc28573a0d31ab3 Mon Sep 17 00:00:00 2001 From: Karol Herbst Date: Mon, 23 Jan 2017 23:10:12 +0100 Subject: drm/nouveau/iccsense: Parse max and crit power level Signed-off-by: Karol Herbst Signed-off-by: Ben Skeggs --- .../gpu/drm/nouveau/include/nvkm/subdev/iccsense.h | 3 +++ drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/base.c | 20 ++++++++++++++++++-- 2 files changed, 21 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/iccsense.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/iccsense.h index 3c2ddd9..b7a9b04 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/iccsense.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/iccsense.h @@ -8,6 +8,9 @@ struct nvkm_iccsense { bool data_valid; struct list_head sensors; struct list_head rails; + + u32 power_w_max; + u32 power_w_crit; }; int gf100_iccsense_new(struct nvkm_device *, int index, struct nvkm_iccsense **); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/base.c index f0af2a3..fecfa6a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/base.c @@ -26,6 +26,7 @@ #include #include #include +#include #include static bool @@ -216,10 +217,25 @@ nvkm_iccsense_oneinit(struct nvkm_subdev *subdev) { struct nvkm_iccsense *iccsense = nvkm_iccsense(subdev); struct nvkm_bios *bios = subdev->device->bios; + struct nvbios_power_budget budget; struct nvbios_iccsense stbl; - int i; + int i, ret; - if (!bios || nvbios_iccsense_parse(bios, &stbl) || !stbl.nr_entry) + if (!bios) + return 0; + + ret = nvbios_power_budget_header(bios, &budget); + if (!ret && budget.cap_entry != 0xff) { + struct nvbios_power_budget_entry entry; + ret = nvbios_power_budget_entry(bios, &budget, + budget.cap_entry, &entry); + if (!ret) { + iccsense->power_w_max = entry.avg_w; + iccsense->power_w_crit = entry.max_w; + } + } + + if (nvbios_iccsense_parse(bios, &stbl) || !stbl.nr_entry) return 0; iccsense->data_valid = true; -- cgit v1.1 From 7722e1b0b6accab2ca11da0e9c708459fff65fb4 Mon Sep 17 00:00:00 2001 From: Karol Herbst Date: Mon, 23 Jan 2017 23:10:13 +0100 Subject: drm/nouveau/hwmon: expose power_max and power_crit Signed-off-by: Karol Herbst Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_hwmon.c | 44 +++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nouveau_hwmon.c b/drivers/gpu/drm/nouveau/nouveau_hwmon.c index d762b8a..23b1670 100644 --- a/drivers/gpu/drm/nouveau/nouveau_hwmon.c +++ b/drivers/gpu/drm/nouveau/nouveau_hwmon.c @@ -596,6 +596,32 @@ nouveau_hwmon_get_power1_input(struct device *d, struct device_attribute *a, static SENSOR_DEVICE_ATTR(power1_input, S_IRUGO, nouveau_hwmon_get_power1_input, NULL, 0); +static ssize_t +nouveau_hwmon_get_power1_max(struct device *d, struct device_attribute *a, + char *buf) +{ + struct drm_device *dev = dev_get_drvdata(d); + struct nouveau_drm *drm = nouveau_drm(dev); + struct nvkm_iccsense *iccsense = nvxx_iccsense(&drm->client.device); + return sprintf(buf, "%i\n", iccsense->power_w_max); +} + +static SENSOR_DEVICE_ATTR(power1_max, S_IRUGO, + nouveau_hwmon_get_power1_max, NULL, 0); + +static ssize_t +nouveau_hwmon_get_power1_crit(struct device *d, struct device_attribute *a, + char *buf) +{ + struct drm_device *dev = dev_get_drvdata(d); + struct nouveau_drm *drm = nouveau_drm(dev); + struct nvkm_iccsense *iccsense = nvxx_iccsense(&drm->client.device); + return sprintf(buf, "%i\n", iccsense->power_w_crit); +} + +static SENSOR_DEVICE_ATTR(power1_crit, S_IRUGO, + nouveau_hwmon_get_power1_crit, NULL, 0); + static struct attribute *hwmon_default_attributes[] = { &sensor_dev_attr_name.dev_attr.attr, &sensor_dev_attr_update_rate.dev_attr.attr, @@ -639,6 +665,12 @@ static struct attribute *hwmon_power_attributes[] = { NULL }; +static struct attribute *hwmon_power_caps_attributes[] = { + &sensor_dev_attr_power1_max.dev_attr.attr, + &sensor_dev_attr_power1_crit.dev_attr.attr, + NULL +}; + static const struct attribute_group hwmon_default_attrgroup = { .attrs = hwmon_default_attributes, }; @@ -657,6 +689,9 @@ static const struct attribute_group hwmon_in0_attrgroup = { static const struct attribute_group hwmon_power_attrgroup = { .attrs = hwmon_power_attributes, }; +static const struct attribute_group hwmon_power_caps_attrgroup = { + .attrs = hwmon_power_caps_attributes, +}; #endif int @@ -728,8 +763,16 @@ nouveau_hwmon_init(struct drm_device *dev) if (iccsense && iccsense->data_valid && !list_empty(&iccsense->rails)) { ret = sysfs_create_group(&hwmon_dev->kobj, &hwmon_power_attrgroup); + if (ret) goto error; + + if (iccsense->power_w_max && iccsense->power_w_crit) { + ret = sysfs_create_group(&hwmon_dev->kobj, + &hwmon_power_caps_attrgroup); + if (ret) + goto error; + } } hwmon->hwmon = hwmon_dev; @@ -759,6 +802,7 @@ nouveau_hwmon_fini(struct drm_device *dev) sysfs_remove_group(&hwmon->hwmon->kobj, &hwmon_fan_rpm_attrgroup); sysfs_remove_group(&hwmon->hwmon->kobj, &hwmon_in0_attrgroup); sysfs_remove_group(&hwmon->hwmon->kobj, &hwmon_power_attrgroup); + sysfs_remove_group(&hwmon->hwmon->kobj, &hwmon_power_caps_attrgroup); hwmon_device_unregister(hwmon->hwmon); } -- cgit v1.1 From 800efb4c2857ec543fdc33585bbcb1fd5ef28337 Mon Sep 17 00:00:00 2001 From: Martin Peres Date: Thu, 29 Sep 2016 03:41:35 +0300 Subject: drm/nouveau/drm/therm/fan: add a fallback if no fan control is specified in the vbios This seems to be absolutely necessary for a lot of NV40. Reported-by: gsgf on IRC/freenode Signed-off-by: Martin Peres Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c index 8894fee..df949fa 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c @@ -64,10 +64,9 @@ nvkm_therm_update_trip(struct nvkm_therm *therm) } static int -nvkm_therm_update_linear(struct nvkm_therm *therm) +nvkm_therm_compute_linear_duty(struct nvkm_therm *therm, u8 linear_min_temp, + u8 linear_max_temp) { - u8 linear_min_temp = therm->fan->bios.linear_min_temp; - u8 linear_max_temp = therm->fan->bios.linear_max_temp; u8 temp = therm->func->temp_get(therm); u16 duty; @@ -85,6 +84,21 @@ nvkm_therm_update_linear(struct nvkm_therm *therm) return duty; } +static int +nvkm_therm_update_linear(struct nvkm_therm *therm) +{ + u8 min = therm->fan->bios.linear_min_temp; + u8 max = therm->fan->bios.linear_max_temp; + return nvkm_therm_compute_linear_duty(therm, min, max); +} + +static int +nvkm_therm_update_linear_fallback(struct nvkm_therm *therm) +{ + u8 max = therm->bios_sensor.thrs_fan_boost.temp; + return nvkm_therm_compute_linear_duty(therm, 30, max); +} + static void nvkm_therm_update(struct nvkm_therm *therm, int mode) { @@ -119,6 +133,8 @@ nvkm_therm_update(struct nvkm_therm *therm, int mode) case NVBIOS_THERM_FAN_OTHER: if (therm->cstate) duty = therm->cstate; + else + duty = nvkm_therm_update_linear_fallback(therm); poll = false; break; } -- cgit v1.1 From 5112abc6a43372b2c1934717ed9bf132a427c46c Mon Sep 17 00:00:00 2001 From: Karol Herbst Date: Sat, 11 Feb 2017 12:58:17 +0100 Subject: drm/nouveau/pci/g92: Fix rearm 704a6c008b7942bb7f30bb43d2a6bcad7f543662 broke pci msi rearm for g92 GPUs. g92 needs the nv46_pci_msi_rearm, where g94+ gpus used nv40_pci_msi_rearm. Reported-by: Andrew Randrianasulu Signed-off-by: Karol Herbst Signed-off-by: Ben Skeggs Cc: stable@vger.kernel.org --- drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h | 1 + drivers/gpu/drm/nouveau/nvkm/engine/device/base.c | 20 ++++----- drivers/gpu/drm/nouveau/nvkm/subdev/pci/Kbuild | 1 + drivers/gpu/drm/nouveau/nvkm/subdev/pci/g92.c | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/pci/g94.c | 49 +++++++++++++++++++++++ 5 files changed, 62 insertions(+), 11 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/pci/g94.c (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h index 2592d86..ac2a695 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h @@ -44,6 +44,7 @@ int nv46_pci_new(struct nvkm_device *, int, struct nvkm_pci **); int nv4c_pci_new(struct nvkm_device *, int, struct nvkm_pci **); int g84_pci_new(struct nvkm_device *, int, struct nvkm_pci **); int g92_pci_new(struct nvkm_device *, int, struct nvkm_pci **); +int g94_pci_new(struct nvkm_device *, int, struct nvkm_pci **); int gf100_pci_new(struct nvkm_device *, int, struct nvkm_pci **); int gf106_pci_new(struct nvkm_device *, int, struct nvkm_pci **); int gk104_pci_new(struct nvkm_device *, int, struct nvkm_pci **); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index f40273c..273562d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -1025,7 +1025,7 @@ nv94_chipset = { .mc = g84_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, - .pci = g92_pci_new, + .pci = g94_pci_new, .therm = g84_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, @@ -1057,7 +1057,7 @@ nv96_chipset = { .mc = g84_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, - .pci = g92_pci_new, + .pci = g94_pci_new, .therm = g84_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, @@ -1089,7 +1089,7 @@ nv98_chipset = { .mc = g98_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, - .pci = g92_pci_new, + .pci = g94_pci_new, .therm = g84_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, @@ -1121,7 +1121,7 @@ nva0_chipset = { .mc = g84_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, - .pci = g92_pci_new, + .pci = g94_pci_new, .therm = g84_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, @@ -1153,7 +1153,7 @@ nva3_chipset = { .mc = gt215_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, - .pci = g92_pci_new, + .pci = g94_pci_new, .pmu = gt215_pmu_new, .therm = gt215_therm_new, .timer = nv41_timer_new, @@ -1187,7 +1187,7 @@ nva5_chipset = { .mc = gt215_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, - .pci = g92_pci_new, + .pci = g94_pci_new, .pmu = gt215_pmu_new, .therm = gt215_therm_new, .timer = nv41_timer_new, @@ -1220,7 +1220,7 @@ nva8_chipset = { .mc = gt215_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, - .pci = g92_pci_new, + .pci = g94_pci_new, .pmu = gt215_pmu_new, .therm = gt215_therm_new, .timer = nv41_timer_new, @@ -1253,7 +1253,7 @@ nvaa_chipset = { .mc = g98_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, - .pci = g92_pci_new, + .pci = g94_pci_new, .therm = g84_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, @@ -1285,7 +1285,7 @@ nvac_chipset = { .mc = g98_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, - .pci = g92_pci_new, + .pci = g94_pci_new, .therm = g84_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, @@ -1317,7 +1317,7 @@ nvaf_chipset = { .mc = gt215_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, - .pci = g92_pci_new, + .pci = g94_pci_new, .pmu = gt215_pmu_new, .therm = gt215_therm_new, .timer = nv41_timer_new, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/Kbuild index cdb7ce2..87bf41c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/Kbuild @@ -7,6 +7,7 @@ nvkm-y += nvkm/subdev/pci/nv46.o nvkm-y += nvkm/subdev/pci/nv4c.o nvkm-y += nvkm/subdev/pci/g84.o nvkm-y += nvkm/subdev/pci/g92.o +nvkm-y += nvkm/subdev/pci/g94.o nvkm-y += nvkm/subdev/pci/gf100.o nvkm-y += nvkm/subdev/pci/gf106.o nvkm-y += nvkm/subdev/pci/gk104.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g92.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g92.c index 654607e..4887435 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g92.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g92.c @@ -37,7 +37,7 @@ g92_pci_func = { .rd32 = nv40_pci_rd32, .wr08 = nv40_pci_wr08, .wr32 = nv40_pci_wr32, - .msi_rearm = nv40_pci_msi_rearm, + .msi_rearm = nv46_pci_msi_rearm, .pcie.init = g84_pcie_init, .pcie.set_link = g84_pcie_set_link, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g94.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g94.c new file mode 100644 index 0000000..09adb37 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g94.c @@ -0,0 +1,49 @@ +/* + * Copyright 2015 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "priv.h" + +static const struct nvkm_pci_func +g94_pci_func = { + .init = g84_pci_init, + .rd32 = nv40_pci_rd32, + .wr08 = nv40_pci_wr08, + .wr32 = nv40_pci_wr32, + .msi_rearm = nv40_pci_msi_rearm, + + .pcie.init = g84_pcie_init, + .pcie.set_link = g84_pcie_set_link, + + .pcie.max_speed = g84_pcie_max_speed, + .pcie.cur_speed = g84_pcie_cur_speed, + + .pcie.set_version = g84_pcie_set_version, + .pcie.version = g84_pcie_version, + .pcie.version_supported = g92_pcie_version_supported, +}; + +int +g94_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci) +{ + return nvkm_pci_new_(&g94_pci_func, device, index, ppci); +} -- cgit v1.1 From eb875d87d9ef87cb5565e2e1c4c720e9d4ee591c Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Fri, 17 Feb 2017 15:08:10 +1000 Subject: drm/nouveau/tmr: provide backtrace when a timeout is hit Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/drm/nouveau') diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h index 82d3e28..6a567fe 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h @@ -48,10 +48,8 @@ void nvkm_timer_alarm_cancel(struct nvkm_timer *, struct nvkm_alarm *); } while (_taken = nvkm_timer_read(_tmr) - _time0, _taken < _nsecs); \ \ if (_taken >= _nsecs) { \ - if (_warn) { \ - dev_warn(_device->dev, "timeout at %s:%d/%s()!\n", \ - __FILE__, __LINE__, __func__); \ - } \ + if (_warn) \ + dev_WARN(_device->dev, "timeout\n"); \ _taken = -ETIMEDOUT; \ } \ _taken; \ -- cgit v1.1