From 7c11c99b3c66a8e03494e56ce6e6c5303ee85934 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Fri, 21 Aug 2015 10:52:54 +1000 Subject: drm/nouveau/bios/dcb: accept "maxwell" lane count values for dcb 4.0 We previously assumed that the values "2" and "4" were new in DCB 4.1, however, there's at least one GM107 DCB 4.0 board (Quadro K620) that uses the newer values. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_bios.c | 25 ++++++++++++------------- 1 file changed, 12 insertions(+), 13 deletions(-) (limited to 'drivers/gpu/drm/nouveau/nouveau_bios.c') diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c index 0190b69..e9de6e3 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bios.c +++ b/drivers/gpu/drm/nouveau/nouveau_bios.c @@ -1481,19 +1481,18 @@ parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb, entry->dpconf.link_bw = 540000; break; } - entry->dpconf.link_nr = (conf & 0x0f000000) >> 24; - if (dcb->version < 0x41) { - switch (entry->dpconf.link_nr) { - case 0xf: - entry->dpconf.link_nr = 4; - break; - case 0x3: - entry->dpconf.link_nr = 2; - break; - default: - entry->dpconf.link_nr = 1; - break; - } + switch ((conf & 0x0f000000) >> 24) { + case 0xf: + case 0x4: + entry->dpconf.link_nr = 4; + break; + case 0x3: + case 0x2: + entry->dpconf.link_nr = 2; + break; + default: + entry->dpconf.link_nr = 1; + break; } link = entry->dpconf.sor.link; entry->i2c_index += NV_I2C_AUX(0); -- cgit v1.1