From b5f103ab98c77ca5998b39533c2b46959fbd37d9 Mon Sep 17 00:00:00 2001 From: Jordan Crouse Date: Mon, 28 Nov 2016 12:28:33 -0700 Subject: drm/msm: gpu: Add A5XX target support Add support for the A5XX family of Adreno GPUs. Signed-off-by: Jordan Crouse Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/msm_gpu.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/drm/msm/msm_gpu.c') diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index 3d6e3b7..b28527a 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -96,6 +96,10 @@ static int enable_clk(struct msm_gpu *gpu) if (gpu->grp_clks[0] && gpu->fast_rate) clk_set_rate(gpu->grp_clks[0], gpu->fast_rate); + /* Set the RBBM timer rate to 19.2Mhz */ + if (gpu->grp_clks[2]) + clk_set_rate(gpu->grp_clks[2], 19200000); + for (i = ARRAY_SIZE(gpu->grp_clks) - 1; i >= 0; i--) if (gpu->grp_clks[i]) clk_prepare(gpu->grp_clks[i]); @@ -122,6 +126,9 @@ static int disable_clk(struct msm_gpu *gpu) if (gpu->grp_clks[0] && gpu->slow_rate) clk_set_rate(gpu->grp_clks[0], gpu->slow_rate); + if (gpu->grp_clks[2]) + clk_set_rate(gpu->grp_clks[2], 0); + return 0; } @@ -553,8 +560,8 @@ static irqreturn_t irq_handler(int irq, void *data) } static const char *clk_names[] = { - "core_clk", "iface_clk", "mem_clk", "mem_iface_clk", - "alt_mem_iface_clk", + "core_clk", "iface_clk", "rbbmtimer_clk", "mem_clk", + "mem_iface_clk", "alt_mem_iface_clk", }; int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, @@ -647,7 +654,7 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, iommu = iommu_domain_alloc(&platform_bus_type); if (iommu) { /* TODO 32b vs 64b address space.. */ - iommu->geometry.aperture_start = 0x1000; + iommu->geometry.aperture_start = SZ_16M; iommu->geometry.aperture_end = 0xffffffff; dev_info(drm->dev, "%s: using IOMMU\n", name); -- cgit v1.1