From ba1eb1d825fdef40f69871caf8e5842d00efbbc5 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Tue, 14 Oct 2008 19:55:10 -0700 Subject: i915: Map status page cached for chips with GTT-based HWS location. This should improve performance by avoiding uncached reads by the CPU (the point of having a status page), and may improve stability. This patch only affects G33, GM45 and G45 chips as those are the only ones using GTT-based HWS mappings. Signed-off-by: Keith Packard Signed-off-by: Eric Anholt Signed-off-by: Dave Airlie --- drivers/gpu/drm/i915/i915_drv.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/gpu/drm/i915/i915_drv.h') diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index da7c007..eae4ed3 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -373,6 +373,9 @@ struct drm_i915_gem_object { /** Current tiling mode for the object. */ uint32_t tiling_mode; + /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */ + uint32_t agp_type; + /** * Flagging of which individual pages are valid in GEM_DOMAIN_CPU when * GEM_DOMAIN_CPU is not in the object's read domain. -- cgit v1.1