From 9a9f5786fcccda3cc61eaa8f537690327eff6853 Mon Sep 17 00:00:00 2001 From: Zhao Yakui Date: Wed, 8 Aug 2012 13:57:01 +0000 Subject: gma500: Disable the clock gating of display controller to make DP/eDP work well I don't know why the DP/eDP is affected by the clock gating. But the test shows that it really fixes the DP/eDP clock issue during enabling DP/eDP. Signed-off-by: Zhao Yakui [Updated to only apply the workaround if the device has DP. We don't want to do this on netbooks] Signed-off-by: Alan Cox Signed-off-by: Dave Airlie --- drivers/gpu/drm/gma500/psb_intel_reg.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/gpu/drm/gma500/psb_intel_reg.h') diff --git a/drivers/gpu/drm/gma500/psb_intel_reg.h b/drivers/gpu/drm/gma500/psb_intel_reg.h index 389e969..d914719 100644 --- a/drivers/gpu/drm/gma500/psb_intel_reg.h +++ b/drivers/gpu/drm/gma500/psb_intel_reg.h @@ -1313,6 +1313,10 @@ No status bits are changed. # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* Fixed value on CDV */ # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) +# define DPUNIT_PIPEB_GATE_DISABLE (1 << 30) +# define DPUNIT_PIPEA_GATE_DISABLE (1 << 25) +# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) +# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) #define RAMCLK_GATE_D 0x6210 -- cgit v1.1