From 35dbb74aa752cff90e8dac1a24ed2a452aed0251 Mon Sep 17 00:00:00 2001 From: Rick Chen Date: Mon, 11 Dec 2017 15:53:15 +0800 Subject: clocksource/drivers/atcpit100: Add andestech atcpit100 timer ATCPIT100 is often used on the Andes architecture, This timer provide 4 PIT channels. Each PIT channel is a multi-function timer, can be configured as 32,16,8 bit timers or PWM as well. For system timer it will set channel 1 32-bit timer0 as clock source and count downwards until underflow and restart again. It also set channel 0 32-bit timer0 as clock event and count downwards until condition match. It will generate an interrupt for handling periodically. Signed-off-by: Rick Chen Signed-off-by: Greentime Hu Reviewed-by: Linus Walleij Add andestech atcpit100 timer --- drivers/clocksource/Kconfig | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'drivers/clocksource/Kconfig') diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index b3b4ed9..19d65fe 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -591,4 +591,13 @@ config CLKSRC_ST_LPC Enable this option to use the Low Power controller timer as clocksource. +config ATCPIT100_TIMER + bool "ATCPIT100 timer driver" + depends on NDS32 || COMPILE_TEST + depends on HAS_IOMEM + select TIMER_OF + default NDS32 + help + This option enables support for the Andestech ATCPIT100 timers. + endmenu -- cgit v1.1