From 70b1fce2ec3a89e68a35d99e5e9c6c90338b3dd1 Mon Sep 17 00:00:00 2001 From: Ulf Hansson Date: Fri, 31 Aug 2012 14:21:29 +0200 Subject: clk: ux500: Support for prmcu_rate clock The prmcu_rate clock is not gateable and has a rate which only can be fetched. Signed-off-by: Ulf Hansson Acked-by: Linus Walleij Signed-off-by: Mike Turquette --- drivers/clk/ux500/clk-prcmu.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'drivers/clk/ux500/clk-prcmu.c') diff --git a/drivers/clk/ux500/clk-prcmu.c b/drivers/clk/ux500/clk-prcmu.c index 1d779ad..930cdfe 100644 --- a/drivers/clk/ux500/clk-prcmu.c +++ b/drivers/clk/ux500/clk-prcmu.c @@ -153,6 +153,11 @@ static struct clk_ops clk_prcmu_gate_ops = { .recalc_rate = clk_prcmu_recalc_rate, }; +static struct clk_ops clk_prcmu_rate_ops = { + .is_enabled = clk_prcmu_is_enabled, + .recalc_rate = clk_prcmu_recalc_rate, +}; + static struct clk_ops clk_prcmu_opp_gate_ops = { .prepare = clk_prcmu_opp_prepare, .unprepare = clk_prcmu_opp_unprepare, @@ -228,6 +233,15 @@ struct clk *clk_reg_prcmu_gate(const char *name, &clk_prcmu_gate_ops); } +struct clk *clk_reg_prcmu_rate(const char *name, + const char *parent_name, + u8 cg_sel, + unsigned long flags) +{ + return clk_reg_prcmu(name, parent_name, cg_sel, 0, flags, + &clk_prcmu_rate_ops); +} + struct clk *clk_reg_prcmu_opp_gate(const char *name, const char *parent_name, u8 cg_sel, -- cgit v1.1