From c9c3c6eecc5533d14bb9bc82319257eb8bc52768 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 15 Mar 2016 16:55:41 +0100 Subject: clk: rockchip: simplify GRF handling in pll clocks With the previous commit, the clock drivers now know at init time if the GRF regmap is available. That means if it isn't available then, it also won't become available later and we can therefore switch PLLs, that need the GRF for the lock-status, to read-only mode - similar behaviour as the aborting of rate changes we did before. This saves some conditionals on every rate change and we can also drop the rockchip_clk_get_grf function completely. Signed-off-by: Heiko Stuebner --- drivers/clk/rockchip/clk-pll.c | 30 +++--------------------------- 1 file changed, 3 insertions(+), 27 deletions(-) (limited to 'drivers/clk/rockchip/clk-pll.c') diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index 8ac73bc..76e278d 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -92,15 +92,10 @@ static long rockchip_pll_round_rate(struct clk_hw *hw, */ static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll) { - struct regmap *grf = rockchip_clk_get_grf(pll->ctx); + struct regmap *grf = pll->ctx->grf; unsigned int val; int delay = 24000000, ret; - if (IS_ERR(grf)) { - pr_err("%s: grf regmap not available\n", __func__); - return PTR_ERR(grf); - } - while (delay > 0) { ret = regmap_read(grf, pll->lock_offset, &val); if (ret) { @@ -253,13 +248,6 @@ static int rockchip_rk3036_pll_set_rate(struct clk_hw *hw, unsigned long drate, struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); const struct rockchip_pll_rate_table *rate; unsigned long old_rate = rockchip_rk3036_pll_recalc_rate(hw, prate); - struct regmap *grf = rockchip_clk_get_grf(pll->ctx); - - if (IS_ERR(grf)) { - pr_debug("%s: grf regmap not available, aborting rate change\n", - __func__); - return PTR_ERR(grf); - } pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n", __func__, __clk_get_name(hw->clk), old_rate, drate, prate); @@ -492,13 +480,6 @@ static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate, struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); const struct rockchip_pll_rate_table *rate; unsigned long old_rate = rockchip_rk3066_pll_recalc_rate(hw, prate); - struct regmap *grf = rockchip_clk_get_grf(pll->ctx); - - if (IS_ERR(grf)) { - pr_debug("%s: grf regmap not available, aborting rate change\n", - __func__); - return PTR_ERR(grf); - } pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n", __func__, clk_hw_get_name(hw), old_rate, drate, prate); @@ -565,11 +546,6 @@ static void rockchip_rk3066_pll_init(struct clk_hw *hw) rate->no, cur.no, rate->nf, cur.nf, rate->nb, cur.nb); if (rate->nr != cur.nr || rate->no != cur.no || rate->nf != cur.nf || rate->nb != cur.nb) { - struct regmap *grf = rockchip_clk_get_grf(pll->ctx); - - if (IS_ERR(grf)) - return; - pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", __func__, clk_hw_get_name(hw)); rockchip_rk3066_pll_set_params(pll, rate); @@ -943,13 +919,13 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, switch (pll_type) { case pll_rk3036: - if (!pll->rate_table) + if (!pll->rate_table || IS_ERR(ctx->grf)) init.ops = &rockchip_rk3036_pll_clk_norate_ops; else init.ops = &rockchip_rk3036_pll_clk_ops; break; case pll_rk3066: - if (!pll->rate_table) + if (!pll->rate_table || IS_ERR(ctx->grf)) init.ops = &rockchip_rk3066_pll_clk_norate_ops; else init.ops = &rockchip_rk3066_pll_clk_ops; -- cgit v1.1