From 923587aafc2c41ed516d39651d5750ea402cfc06 Mon Sep 17 00:00:00 2001
From: Jose Abreu <Jose.Abreu@synopsys.com>
Date: Mon, 2 May 2016 10:39:05 +0100
Subject: clk/axs10x: Add I2S PLL clock driver

The ARC SDP I2S clock can be programmed using a
specific PLL.

This patch has the goal of adding a clock driver
that programs this PLL.

At this moment the rate values are hardcoded in
a table but in the future it would be ideal to
use a function which determines the PLL values
given the desired rate.

Signed-off-by: Jose Abreu <joabreu@synopsys.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
 drivers/clk/Makefile | 1 +
 1 file changed, 1 insertion(+)

(limited to 'drivers/clk/Makefile')

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 4ef71a1..6d1e3be 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -86,3 +86,4 @@ obj-$(CONFIG_X86)			+= x86/
 obj-$(CONFIG_ARCH_ZX)			+= zte/
 obj-$(CONFIG_ARCH_ZYNQ)			+= zynq/
 obj-$(CONFIG_H8300)		+= h8300/
+obj-$(CONFIG_ARC_PLAT_AXS10X)		+= axs10x/
-- 
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