From 9cc4581528233e2a4eb8720621c1e2f613d7c38a Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Thu, 11 Sep 2008 00:44:04 +0900 Subject: MIPS: TXx9: Fix RBTX4939 ethernet address initialization Fix location of ethernet adddress when booted from external ROM. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/txx9/rbtx4939/setup.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/mips/txx9/rbtx4939/setup.c b/arch/mips/txx9/rbtx4939/setup.c index 6daee9b..98fbd93 100644 --- a/arch/mips/txx9/rbtx4939/setup.c +++ b/arch/mips/txx9/rbtx4939/setup.c @@ -308,16 +308,22 @@ static void __init rbtx4939_device_init(void) #if defined(CONFIG_TC35815) || defined(CONFIG_TC35815_MODULE) int i, j; unsigned char ethaddr[2][6]; + u8 bdipsw = readb(rbtx4939_bdipsw_addr) & 0x0f; + for (i = 0; i < 2; i++) { unsigned long area = CKSEG1 + 0x1fff0000 + (i * 0x10); - if (readb(rbtx4939_bdipsw_addr) & 8) { + if (bdipsw == 0) + memcpy(ethaddr[i], (void *)area, 6); + else { u16 buf[3]; - area -= 0x03000000; + if (bdipsw & 8) + area -= 0x03000000; + else + area -= 0x01000000; for (j = 0; j < 3; j++) buf[j] = le16_to_cpup((u16 *)(area + j * 2)); memcpy(ethaddr[i], buf, 6); - } else - memcpy(ethaddr[i], (void *)area, 6); + } } tx4939_ethaddr_init(ethaddr[0], ethaddr[1]); #endif -- cgit v1.1 From 864cbf804ddfb3d63d3ba3cca7afdeb98be23434 Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Tue, 2 Sep 2008 22:44:38 +0900 Subject: MIPS: RBTX4927: Add GPIO-LED support Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/txx9/rbtx4927/setup.c | 25 +++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/mips/txx9/rbtx4927/setup.c b/arch/mips/txx9/rbtx4927/setup.c index 4a74423..01129a9 100644 --- a/arch/mips/txx9/rbtx4927/setup.c +++ b/arch/mips/txx9/rbtx4927/setup.c @@ -49,6 +49,7 @@ #include #include #include +#include #include #include #include @@ -210,10 +211,6 @@ static void __init rbtx4927_mem_setup(void) /* TX4927-SIO DTR on (PIO[15]) */ gpio_request(15, "sio-dtr"); gpio_direction_output(15, 1); - gpio_request(0, "led"); - gpio_direction_output(0, 1); - gpio_request(1, "led"); - gpio_direction_output(1, 1); tx4927_sio_init(0, 0); #ifdef CONFIG_SERIAL_TXX9_CONSOLE @@ -315,6 +312,25 @@ static void __init rbtx4927_mtd_init(void) tx4927_mtd_init(i); } +static void __init rbtx4927_gpioled_init(void) +{ + static struct gpio_led leds[] = { + { .name = "gpioled:green:0", .gpio = 0, .active_low = 1, }, + { .name = "gpioled:green:1", .gpio = 1, .active_low = 1, }, + }; + static struct gpio_led_platform_data pdata = { + .num_leds = ARRAY_SIZE(leds), + .leds = leds, + }; + struct platform_device *pdev = platform_device_alloc("leds-gpio", 0); + + if (!pdev) + return; + pdev->dev.platform_data = &pdata; + if (platform_device_add(pdev)) + platform_device_put(pdev); +} + static void __init rbtx4927_device_init(void) { toshiba_rbtx4927_rtc_init(); @@ -322,6 +338,7 @@ static void __init rbtx4927_device_init(void) tx4927_wdt_init(); rbtx4927_mtd_init(); txx9_iocled_init(RBTX4927_LED_ADDR - IO_BASE, -1, 3, 1, "green", NULL); + rbtx4927_gpioled_init(); } struct txx9_board_vec rbtx4927_vec __initdata = { -- cgit v1.1 From c46b302b948e2070cb713171207c42e9586f131a Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 28 Oct 2008 09:37:47 +0000 Subject: MIPS: New feature test macro cpu_has_mips_r cpu_has_mips_r is true if a processor is MIPS32 or MIPS64, any architecture revision. Signed-off-by: Ralf Baechle --- arch/mips/include/asm/cpu-features.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index 5ea701f..12d12df 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -141,6 +141,8 @@ #define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2) #define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1) #define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2) +#define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \ + cpu_has_mips64r1 | cpu_has_mips64r2) #ifndef cpu_has_dsp #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) -- cgit v1.1 From 4816227b54d2366cba785e6f3b9f81495b83a5f1 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 28 Oct 2008 09:40:35 +0000 Subject: MIPS: Clean up MIPSxx-optimized bitop functions Signed-off-by: Ralf Baechle --- arch/mips/include/asm/bitops.h | 114 +++++++++++++++++++++++++++-------------- 1 file changed, 76 insertions(+), 38 deletions(-) (limited to 'arch') diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h index 49df8c4..bac4a96 100644 --- a/arch/mips/include/asm/bitops.h +++ b/arch/mips/include/asm/bitops.h @@ -558,39 +558,67 @@ static inline void __clear_bit_unlock(unsigned long nr, volatile unsigned long * __clear_bit(nr, addr); } -#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) - /* * Return the bit position (0..63) of the most significant 1 bit in a word * Returns -1 if no 1 bit exists */ -static inline unsigned long __fls(unsigned long x) +static inline unsigned long __fls(unsigned long word) { - int lz; + int num; - if (sizeof(x) == 4) { + if (BITS_PER_LONG == 32 && + __builtin_constant_p(cpu_has_mips_r) && cpu_has_mips_r) { __asm__( " .set push \n" " .set mips32 \n" " clz %0, %1 \n" " .set pop \n" - : "=r" (lz) - : "r" (x)); + : "=r" (num) + : "r" (word)); - return 31 - lz; + return 31 - num; } - BUG_ON(sizeof(x) != 8); + if (BITS_PER_LONG == 64 && + __builtin_constant_p(cpu_has_mips64) && cpu_has_mips64) { + __asm__( + " .set push \n" + " .set mips64 \n" + " dclz %0, %1 \n" + " .set pop \n" + : "=r" (num) + : "r" (word)); - __asm__( - " .set push \n" - " .set mips64 \n" - " dclz %0, %1 \n" - " .set pop \n" - : "=r" (lz) - : "r" (x)); + return 63 - num; + } + + num = BITS_PER_LONG - 1; - return 63 - lz; +#if BITS_PER_LONG == 64 + if (!(word & (~0ul << 32))) { + num -= 32; + word <<= 32; + } +#endif + if (!(word & (~0ul << (BITS_PER_LONG-16)))) { + num -= 16; + word <<= 16; + } + if (!(word & (~0ul << (BITS_PER_LONG-8)))) { + num -= 8; + word <<= 8; + } + if (!(word & (~0ul << (BITS_PER_LONG-4)))) { + num -= 4; + word <<= 4; + } + if (!(word & (~0ul << (BITS_PER_LONG-2)))) { + num -= 2; + word <<= 2; + } + if (!(word & (~0ul << (BITS_PER_LONG-1)))) + num -= 1; + return num; } /* @@ -612,23 +640,43 @@ static inline unsigned long __ffs(unsigned long word) * This is defined the same way as ffs. * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32. */ -static inline int fls(int word) +static inline int fls(int x) { - __asm__("clz %0, %1" : "=r" (word) : "r" (word)); + int r; - return 32 - word; -} + if (__builtin_constant_p(cpu_has_mips_r) && cpu_has_mips_r) { + __asm__("clz %0, %1" : "=r" (x) : "r" (x)); -#if defined(CONFIG_64BIT) && defined(CONFIG_CPU_MIPS64) -static inline int fls64(__u64 word) -{ - __asm__("dclz %0, %1" : "=r" (word) : "r" (word)); + return 32 - x; + } - return 64 - word; + r = 32; + if (!x) + return 0; + if (!(x & 0xffff0000u)) { + x <<= 16; + r -= 16; + } + if (!(x & 0xff000000u)) { + x <<= 8; + r -= 8; + } + if (!(x & 0xf0000000u)) { + x <<= 4; + r -= 4; + } + if (!(x & 0xc0000000u)) { + x <<= 2; + r -= 2; + } + if (!(x & 0x80000000u)) { + x <<= 1; + r -= 1; + } + return r; } -#else + #include -#endif /* * ffs - find first bit set. @@ -646,16 +694,6 @@ static inline int ffs(int word) return fls(word & -word); } -#else - -#include -#include -#include -#include -#include - -#endif /*defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) */ - #include #include -- cgit v1.1 From 566f74f6b2f8b85d5b8d6caaf97e5672cecd3e3e Mon Sep 17 00:00:00 2001 From: David Daney Date: Thu, 23 Oct 2008 17:56:35 -0700 Subject: MIPS: Consider value of c0_ebase when computing value of exception base. It just so happens to be zero on all currently supported systems so this hasn't bitten yet ... [Ralf: Original patch from Cavium; handling of set_uncached_handler() and de-ifdef'ed trap_init() implementation by me.] Signed-off-by: Tomaso Paoletti Signed-off-by: David Daney Signed-off-by: Ralf Baechle --- arch/mips/kernel/traps.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 80b9e07..3f6de76 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1555,6 +1555,8 @@ void __cpuinit set_uncached_handler(unsigned long offset, void *addr, #ifdef CONFIG_64BIT unsigned long uncached_ebase = TO_UNCAC(ebase); #endif + if (cpu_has_mips_r2) + ebase += (read_c0_ebase() & 0x3ffff000); if (!addr) panic(panic_null_cerr); @@ -1588,8 +1590,11 @@ void __init trap_init(void) if (cpu_has_veic || cpu_has_vint) ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64); - else + else { ebase = CAC_BASE; + if (cpu_has_mips_r2) + ebase += (read_c0_ebase() & 0x3ffff000); + } per_cpu_trap_init(); @@ -1697,11 +1702,11 @@ void __init trap_init(void) if (cpu_has_vce) /* Special exception: R4[04]00 uses also the divec space. */ - memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100); + memcpy((void *)(ebase + 0x180), &except_vec3_r4000, 0x100); else if (cpu_has_4kex) - memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80); + memcpy((void *)(ebase + 0x180), &except_vec3_generic, 0x80); else - memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80); + memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80); signal_init(); #ifdef CONFIG_MIPS32_COMPAT -- cgit v1.1 From 076c6e4f4d81113615f50e5bc2c569f628bcd54a Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 28 Oct 2008 10:03:57 +0000 Subject: MIPS: SMP: Do not initialize __cpu_number_map/__cpu_logical_map for CPU 0. A system isn't necessarily booted on physical processor 0 as this code assumes. Also the array happens to be allocated in .bss so it's zero initialized anyway. Systems which need to override this can do so in their mp_ops->smp_setup() method. Signed-off-by: Ralf Baechle --- arch/mips/kernel/smp.c | 6 ------ 1 file changed, 6 deletions(-) (limited to 'arch') diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index b79ea70..8bf88faf 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -195,12 +195,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus) /* preload SMP state for boot cpu */ void __devinit smp_prepare_boot_cpu(void) { - /* - * This assumes that bootup is always handled by the processor - * with the logic and physical number 0. - */ - __cpu_number_map[0] = 0; - __cpu_logical_map[0] = 0; cpu_set(0, phys_cpu_present_map); cpu_set(0, cpu_online_map); cpu_set(0, cpu_callin_map); -- cgit v1.1 From ba3049ed4086737dab200b6087138a4b8e06915d Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 28 Oct 2008 17:38:42 +0000 Subject: MIPS: Switch FPU emulator trap to BREAK instruction. Arguably using the address error handler has always been ugly. But with processors that handle unaligned loads and stores in hardware the current mechanism ceases to work so switch it to a BREAK instruction and allocate break code 514 to the FPU emulator. Yoichi Yuasa provided a build fix for CONFIG_BUG=n. Signed-off-by: Ralf Baechle Signed-off-by: Yoichi Yuasa --- arch/mips/include/asm/break.h | 1 + arch/mips/include/asm/fpu_emulator.h | 17 +++++++++++++++++ arch/mips/kernel/traps.c | 16 ++++++++++++++++ arch/mips/kernel/unaligned.c | 12 ------------ arch/mips/math-emu/cp1emu.c | 4 ---- arch/mips/math-emu/dsemul.c | 7 +++---- arch/mips/math-emu/dsemul.h | 17 ----------------- 7 files changed, 37 insertions(+), 37 deletions(-) delete mode 100644 arch/mips/math-emu/dsemul.h (limited to 'arch') diff --git a/arch/mips/include/asm/break.h b/arch/mips/include/asm/break.h index 25b980c..44437ed 100644 --- a/arch/mips/include/asm/break.h +++ b/arch/mips/include/asm/break.h @@ -29,6 +29,7 @@ #define _BRK_THREADBP 11 /* For threads, user bp (used by debuggers) */ #define BRK_BUG 512 /* Used by BUG() */ #define BRK_KDB 513 /* Used in KDB_ENTER() */ +#define BRK_MEMU 514 /* Used by FPU emulator */ #define BRK_MULOVF 1023 /* Multiply overflow */ #endif /* __ASM_BREAK_H */ diff --git a/arch/mips/include/asm/fpu_emulator.h b/arch/mips/include/asm/fpu_emulator.h index 2731c38..e518957 100644 --- a/arch/mips/include/asm/fpu_emulator.h +++ b/arch/mips/include/asm/fpu_emulator.h @@ -23,6 +23,9 @@ #ifndef _ASM_FPU_EMULATOR_H #define _ASM_FPU_EMULATOR_H +#include +#include + struct mips_fpu_emulator_stats { unsigned int emulated; unsigned int loads; @@ -34,4 +37,18 @@ struct mips_fpu_emulator_stats { extern struct mips_fpu_emulator_stats fpuemustats; +extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir, + unsigned long cpc); +extern int do_dsemulret(struct pt_regs *xcp); + +/* + * Instruction inserted following the badinst to further tag the sequence + */ +#define BD_COOKIE 0x0000bd36 /* tne $0, $0 with baggage */ + +/* + * Break instruction with special math emu break code set + */ +#define BREAK_MATH (0x0000000d | (BRK_MEMU << 16)) + #endif /* _ASM_FPU_EMULATOR_H */ diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 3f6de76..3530561 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #include @@ -722,6 +723,21 @@ static void do_trap_or_bp(struct pt_regs *regs, unsigned int code, die_if_kernel("Kernel bug detected", regs); force_sig(SIGTRAP, current); break; + case BRK_MEMU: + /* + * Address errors may be deliberately induced by the FPU + * emulator to retake control of the CPU after executing the + * instruction in the delay slot of an emulated branch. + * + * Terminate if exception was recognized as a delay slot return + * otherwise handle as normal. + */ + if (do_dsemulret(regs)) + return; + + die_if_kernel("Math emu break/trap", regs); + force_sig(SIGTRAP, current); + break; default: scnprintf(b, sizeof(b), "%s instruction in kernel code", str); die_if_kernel(b, regs); diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c index 20709669..bf4c4a9 100644 --- a/arch/mips/kernel/unaligned.c +++ b/arch/mips/kernel/unaligned.c @@ -499,22 +499,10 @@ sigill: asmlinkage void do_ade(struct pt_regs *regs) { - extern int do_dsemulret(struct pt_regs *); unsigned int __user *pc; mm_segment_t seg; /* - * Address errors may be deliberately induced by the FPU emulator to - * retake control of the CPU after executing the instruction in the - * delay slot of an emulated branch. - */ - /* Terminate if exception was recognized as a delay slot return */ - if (do_dsemulret(regs)) - return; - - /* Otherwise handle as normal */ - - /* * Did we catch a fault trying to load an instruction? * Or are we running in MIPS16 mode? */ diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c index 7ec0b21..890f7792 100644 --- a/arch/mips/math-emu/cp1emu.c +++ b/arch/mips/math-emu/cp1emu.c @@ -48,7 +48,6 @@ #include #include "ieee754.h" -#include "dsemul.h" /* Strap kernel emulator for full MIPS IV emulation */ @@ -346,9 +345,6 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx) /* cop control register rd -> gpr[rt] */ u32 value; - if (ir == CP1UNDEF) { - return do_dsemulret(xcp); - } if (MIPSInst_RD(ir) == FPCREG_CSR) { value = ctx->fcr31; value = (value & ~0x3) | mips_rm[value & 0x3]; diff --git a/arch/mips/math-emu/dsemul.c b/arch/mips/math-emu/dsemul.c index 653e325..df7b9d9 100644 --- a/arch/mips/math-emu/dsemul.c +++ b/arch/mips/math-emu/dsemul.c @@ -18,7 +18,6 @@ #include #include "ieee754.h" -#include "dsemul.h" /* Strap kernel emulator for full MIPS IV emulation */ @@ -94,7 +93,7 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc) return SIGBUS; err = __put_user(ir, &fr->emul); - err |= __put_user((mips_instruction)BADINST, &fr->badinst); + err |= __put_user((mips_instruction)BREAK_MATH, &fr->badinst); err |= __put_user((mips_instruction)BD_COOKIE, &fr->cookie); err |= __put_user(cpc, &fr->epc); @@ -130,13 +129,13 @@ int do_dsemulret(struct pt_regs *xcp) /* * Do some sanity checking on the stackframe: * - * - Is the instruction pointed to by the EPC an BADINST? + * - Is the instruction pointed to by the EPC an BREAK_MATH? * - Is the following memory word the BD_COOKIE? */ err = __get_user(insn, &fr->badinst); err |= __get_user(cookie, &fr->cookie); - if (unlikely(err || (insn != BADINST) || (cookie != BD_COOKIE))) { + if (unlikely(err || (insn != BREAK_MATH) || (cookie != BD_COOKIE))) { fpuemustats.errors++; return 0; } diff --git a/arch/mips/math-emu/dsemul.h b/arch/mips/math-emu/dsemul.h deleted file mode 100644 index 091f0e7..0000000 --- a/arch/mips/math-emu/dsemul.h +++ /dev/null @@ -1,17 +0,0 @@ -extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc); -extern int do_dsemulret(struct pt_regs *xcp); - -/* Instruction which will always cause an address error */ -#define AdELOAD 0x8c000001 /* lw $0,1($0) */ -/* Instruction which will plainly cause a CP1 exception when FPU is disabled */ -#define CP1UNDEF 0x44400001 /* cfc1 $0,$0 undef */ - -/* Instruction inserted following the badinst to further tag the sequence */ -#define BD_COOKIE 0x0000bd36 /* tne $0,$0 with baggage */ - -/* Setup which instruction to use for trampoline */ -#ifdef STANDALONE_EMULATOR -#define BADINST CP1UNDEF -#else -#define BADINST AdELOAD -#endif -- cgit v1.1 From 558ce12494e9e0321b77b9f1ef62c16d0b893cf5 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 29 Oct 2008 12:33:34 +0000 Subject: MIPS: Probe for watch registers on cores of all vendors, not just MTI. Signed-off-by: Ralf Baechle Acked-by: David Daney --- arch/mips/kernel/cpu-probe.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) (limited to 'arch') diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 0cf1545..41a1d07 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -652,21 +652,24 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c) static void __cpuinit decode_configs(struct cpuinfo_mips *c) { + int ok; + /* MIPS32 or MIPS64 compliant CPU. */ c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; c->scache.flags = MIPS_CACHE_NOT_PRESENT; - /* Read Config registers. */ - if (!decode_config0(c)) - return; /* actually worth a panic() */ - if (!decode_config1(c)) - return; - if (!decode_config2(c)) - return; - if (!decode_config3(c)) - return; + ok = decode_config0(c); /* Read Config registers. */ + BUG_ON(!ok); /* Arch spec violation! */ + if (ok) + ok = decode_config1(c); + if (ok) + ok = decode_config2(c); + if (ok) + ok = decode_config3(c); + + mips_probe_watch_registers(c); } #ifdef CONFIG_CPU_MIPSR2 @@ -678,7 +681,6 @@ static inline void spram_config(void) {} static inline void cpu_probe_mips(struct cpuinfo_mips *c) { decode_configs(c); - mips_probe_watch_registers(c); switch (c->processor_id & 0xff00) { case PRID_IMP_4KC: c->cputype = CPU_4KC; -- cgit v1.1 From 255a12fbf994664125983e389c975b4403aea167 Mon Sep 17 00:00:00 2001 From: Harvey Harrison Date: Wed, 29 Oct 2008 14:21:32 -0700 Subject: MIPS: Use the new byteorder headers Signed-off-by: Harvey Harrison Signed-off-by: Andrew Morton Signed-off-by: Ralf Baechle --- arch/mips/include/asm/byteorder.h | 40 ++++++++++++++++----------------------- 1 file changed, 16 insertions(+), 24 deletions(-) (limited to 'arch') diff --git a/arch/mips/include/asm/byteorder.h b/arch/mips/include/asm/byteorder.h index fe7dc2d..2988d29 100644 --- a/arch/mips/include/asm/byteorder.h +++ b/arch/mips/include/asm/byteorder.h @@ -11,11 +11,19 @@ #include #include -#ifdef __GNUC__ +#if defined(__MIPSEB__) +# define __BIG_ENDIAN +#elif defined(__MIPSEL__) +# define __LITTLE_ENDIAN +#else +# error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???" +#endif + +#define __SWAB_64_THRU_32__ #ifdef CONFIG_CPU_MIPSR2 -static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x) +static inline __attribute_const__ __u16 __arch_swab16(__u16 x) { __asm__( " wsbh %0, %1 \n" @@ -24,9 +32,9 @@ static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x) return x; } -#define __arch__swab16(x) ___arch__swab16(x) +#define __arch_swab16 __arch_swab16 -static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x) +static inline __attribute_const__ __u32 __arch_swab32(__u32 x) { __asm__( " wsbh %0, %1 \n" @@ -36,11 +44,10 @@ static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x) return x; } -#define __arch__swab32(x) ___arch__swab32(x) +#define __arch_swab32 __arch_swab32 #ifdef CONFIG_CPU_MIPS64_R2 - -static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x) +static inline __attribute_const__ __u64 __arch_swab64(__u64 x) { __asm__( " dsbh %0, %1 \n" @@ -51,26 +58,11 @@ static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x) return x; } - -#define __arch__swab64(x) ___arch__swab64(x) - +#define __arch_swab64 __arch_swab64 #endif /* CONFIG_CPU_MIPS64_R2 */ #endif /* CONFIG_CPU_MIPSR2 */ -#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) -# define __BYTEORDER_HAS_U64__ -# define __SWAB_64_THRU_32__ -#endif - -#endif /* __GNUC__ */ - -#if defined(__MIPSEB__) -# include -#elif defined(__MIPSEL__) -# include -#else -# error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???" -#endif +#include #endif /* _ASM_BYTEORDER_H */ -- cgit v1.1 From cea7e2dfdef53fe55f359d00da562a268be06fd2 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 30 Oct 2008 13:38:45 +0000 Subject: MIPS: Sort out CPU type to name translation. As noticed by David Daney , the old long switch statement did not comply with the Linux C coding style. It was also yet another place of code to be changed when adding a new processor type leading to annoying bugs for example in /proc/cpuinfo. Fixed by moving the setting of the CPU type string into the core of the probing code and a few BUG_ON() test to ensure the CPU probing code indeed did its job and removing multiple now redundant tests. Signed-off-by: Ralf Baechle --- arch/mips/kernel/cpu-probe.c | 225 +++++++++++++++++++------------------------ 1 file changed, 98 insertions(+), 127 deletions(-) (limited to 'arch') diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 41a1d07..c9207b5 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -286,11 +286,12 @@ static inline int __cpu_has_fpu(void) #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ | MIPS_CPU_COUNTER) -static inline void cpu_probe_legacy(struct cpuinfo_mips *c) +static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) { switch (c->processor_id & 0xff00) { case PRID_IMP_R2000: c->cputype = CPU_R2000; + __cpu_name[cpu] = "R2000"; c->isa_level = MIPS_CPU_ISA_I; c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | MIPS_CPU_NOFPUEX; @@ -299,13 +300,19 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) c->tlbsize = 64; break; case PRID_IMP_R3000: - if ((c->processor_id & 0xff) == PRID_REV_R3000A) - if (cpu_has_confreg()) + if ((c->processor_id & 0xff) == PRID_REV_R3000A) { + if (cpu_has_confreg()) { c->cputype = CPU_R3081E; - else + __cpu_name[cpu] = "R3081"; + } else { c->cputype = CPU_R3000A; - else + __cpu_name[cpu] = "R3000A"; + } + break; + } else { c->cputype = CPU_R3000; + __cpu_name[cpu] = "R3000"; + } c->isa_level = MIPS_CPU_ISA_I; c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | MIPS_CPU_NOFPUEX; @@ -315,15 +322,21 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_R4000: if (read_c0_config() & CONF_SC) { - if ((c->processor_id & 0xff) >= PRID_REV_R4400) + if ((c->processor_id & 0xff) >= PRID_REV_R4400) { c->cputype = CPU_R4400PC; - else + __cpu_name[cpu] = "R4400PC"; + } else { c->cputype = CPU_R4000PC; + __cpu_name[cpu] = "R4000PC"; + } } else { - if ((c->processor_id & 0xff) >= PRID_REV_R4400) + if ((c->processor_id & 0xff) >= PRID_REV_R4400) { c->cputype = CPU_R4400SC; - else + __cpu_name[cpu] = "R4400SC"; + } else { c->cputype = CPU_R4000SC; + __cpu_name[cpu] = "R4000SC"; + } } c->isa_level = MIPS_CPU_ISA_III; @@ -336,25 +349,34 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) switch (c->processor_id & 0xf0) { case PRID_REV_VR4111: c->cputype = CPU_VR4111; + __cpu_name[cpu] = "NEC VR4111"; break; case PRID_REV_VR4121: c->cputype = CPU_VR4121; + __cpu_name[cpu] = "NEC VR4121"; break; case PRID_REV_VR4122: - if ((c->processor_id & 0xf) < 0x3) + if ((c->processor_id & 0xf) < 0x3) { c->cputype = CPU_VR4122; - else + __cpu_name[cpu] = "NEC VR4122"; + } else { c->cputype = CPU_VR4181A; + __cpu_name[cpu] = "NEC VR4181A"; + } break; case PRID_REV_VR4130: - if ((c->processor_id & 0xf) < 0x4) + if ((c->processor_id & 0xf) < 0x4) { c->cputype = CPU_VR4131; - else + __cpu_name[cpu] = "NEC VR4131"; + } else { c->cputype = CPU_VR4133; + __cpu_name[cpu] = "NEC VR4133"; + } break; default: printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); c->cputype = CPU_VR41XX; + __cpu_name[cpu] = "NEC Vr41xx"; break; } c->isa_level = MIPS_CPU_ISA_III; @@ -363,6 +385,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_R4300: c->cputype = CPU_R4300; + __cpu_name[cpu] = "R4300"; c->isa_level = MIPS_CPU_ISA_III; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_LLSC; @@ -370,6 +393,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_R4600: c->cputype = CPU_R4600; + __cpu_name[cpu] = "R4600"; c->isa_level = MIPS_CPU_ISA_III; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_LLSC; @@ -384,6 +408,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) * it's c0_prid id number with the TX3900. */ c->cputype = CPU_R4650; + __cpu_name[cpu] = "R4650"; c->isa_level = MIPS_CPU_ISA_III; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; c->tlbsize = 48; @@ -395,25 +420,26 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { c->cputype = CPU_TX3927; + __cpu_name[cpu] = "TX3927"; c->tlbsize = 64; } else { switch (c->processor_id & 0xff) { case PRID_REV_TX3912: c->cputype = CPU_TX3912; + __cpu_name[cpu] = "TX3912"; c->tlbsize = 32; break; case PRID_REV_TX3922: c->cputype = CPU_TX3922; + __cpu_name[cpu] = "TX3922"; c->tlbsize = 64; break; - default: - c->cputype = CPU_UNKNOWN; - break; } } break; case PRID_IMP_R4700: c->cputype = CPU_R4700; + __cpu_name[cpu] = "R4700"; c->isa_level = MIPS_CPU_ISA_III; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_LLSC; @@ -421,6 +447,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_TX49: c->cputype = CPU_TX49XX; + __cpu_name[cpu] = "R49XX"; c->isa_level = MIPS_CPU_ISA_III; c->options = R4K_OPTS | MIPS_CPU_LLSC; if (!(c->processor_id & 0x08)) @@ -429,6 +456,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_R5000: c->cputype = CPU_R5000; + __cpu_name[cpu] = "R5000"; c->isa_level = MIPS_CPU_ISA_IV; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_LLSC; @@ -436,6 +464,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_R5432: c->cputype = CPU_R5432; + __cpu_name[cpu] = "R5432"; c->isa_level = MIPS_CPU_ISA_IV; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_WATCH | MIPS_CPU_LLSC; @@ -443,6 +472,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_R5500: c->cputype = CPU_R5500; + __cpu_name[cpu] = "R5500"; c->isa_level = MIPS_CPU_ISA_IV; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_WATCH | MIPS_CPU_LLSC; @@ -450,6 +480,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_NEVADA: c->cputype = CPU_NEVADA; + __cpu_name[cpu] = "Nevada"; c->isa_level = MIPS_CPU_ISA_IV; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_DIVEC | MIPS_CPU_LLSC; @@ -457,6 +488,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_R6000: c->cputype = CPU_R6000; + __cpu_name[cpu] = "R6000"; c->isa_level = MIPS_CPU_ISA_II; c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | MIPS_CPU_LLSC; @@ -464,6 +496,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_R6000A: c->cputype = CPU_R6000A; + __cpu_name[cpu] = "R6000A"; c->isa_level = MIPS_CPU_ISA_II; c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | MIPS_CPU_LLSC; @@ -471,6 +504,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_RM7000: c->cputype = CPU_RM7000; + __cpu_name[cpu] = "RM7000"; c->isa_level = MIPS_CPU_ISA_IV; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_LLSC; @@ -486,6 +520,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_RM9000: c->cputype = CPU_RM9000; + __cpu_name[cpu] = "RM9000"; c->isa_level = MIPS_CPU_ISA_IV; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_LLSC; @@ -500,6 +535,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_R8000: c->cputype = CPU_R8000; + __cpu_name[cpu] = "RM8000"; c->isa_level = MIPS_CPU_ISA_IV; c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_FPU | MIPS_CPU_32FPR | @@ -508,6 +544,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_R10000: c->cputype = CPU_R10000; + __cpu_name[cpu] = "R10000"; c->isa_level = MIPS_CPU_ISA_IV; c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | MIPS_CPU_FPU | MIPS_CPU_32FPR | @@ -517,6 +554,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_R12000: c->cputype = CPU_R12000; + __cpu_name[cpu] = "R12000"; c->isa_level = MIPS_CPU_ISA_IV; c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | MIPS_CPU_FPU | MIPS_CPU_32FPR | @@ -526,6 +564,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_R14000: c->cputype = CPU_R14000; + __cpu_name[cpu] = "R14000"; c->isa_level = MIPS_CPU_ISA_IV; c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | MIPS_CPU_FPU | MIPS_CPU_32FPR | @@ -535,6 +574,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) break; case PRID_IMP_LOONGSON2: c->cputype = CPU_LOONGSON2; + __cpu_name[cpu] = "ICT Loongson-2"; c->isa_level = MIPS_CPU_ISA_III; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC | @@ -678,51 +718,62 @@ extern void spram_config(void); static inline void spram_config(void) {} #endif -static inline void cpu_probe_mips(struct cpuinfo_mips *c) +static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); switch (c->processor_id & 0xff00) { case PRID_IMP_4KC: c->cputype = CPU_4KC; + __cpu_name[cpu] = "MIPS 4Kc"; break; case PRID_IMP_4KEC: c->cputype = CPU_4KEC; + __cpu_name[cpu] = "MIPS 4KEc"; break; case PRID_IMP_4KECR2: c->cputype = CPU_4KEC; + __cpu_name[cpu] = "MIPS 4KEc"; break; case PRID_IMP_4KSC: case PRID_IMP_4KSD: c->cputype = CPU_4KSC; + __cpu_name[cpu] = "MIPS 4KSc"; break; case PRID_IMP_5KC: c->cputype = CPU_5KC; + __cpu_name[cpu] = "MIPS 5Kc"; break; case PRID_IMP_20KC: c->cputype = CPU_20KC; + __cpu_name[cpu] = "MIPS 20Kc"; break; case PRID_IMP_24K: case PRID_IMP_24KE: c->cputype = CPU_24K; + __cpu_name[cpu] = "MIPS 24Kc"; break; case PRID_IMP_25KF: c->cputype = CPU_25KF; + __cpu_name[cpu] = "MIPS 25Kc"; break; case PRID_IMP_34K: c->cputype = CPU_34K; + __cpu_name[cpu] = "MIPS 34Kc"; break; case PRID_IMP_74K: c->cputype = CPU_74K; + __cpu_name[cpu] = "MIPS 74Kc"; break; case PRID_IMP_1004K: c->cputype = CPU_1004K; + __cpu_name[cpu] = "MIPS 1004Kc"; break; } spram_config(); } -static inline void cpu_probe_alchemy(struct cpuinfo_mips *c) +static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); switch (c->processor_id & 0xff00) { @@ -731,23 +782,31 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c) switch ((c->processor_id >> 24) & 0xff) { case 0: c->cputype = CPU_AU1000; + __cpu_name[cpu] = "Au1000"; break; case 1: c->cputype = CPU_AU1500; + __cpu_name[cpu] = "Au1500"; break; case 2: c->cputype = CPU_AU1100; + __cpu_name[cpu] = "Au1100"; break; case 3: c->cputype = CPU_AU1550; + __cpu_name[cpu] = "Au1550"; break; case 4: c->cputype = CPU_AU1200; - if (2 == (c->processor_id & 0xff)) + __cpu_name[cpu] = "Au1200"; + if ((c->processor_id & 0xff) == 2) { c->cputype = CPU_AU1250; + __cpu_name[cpu] = "Au1250"; + } break; case 5: c->cputype = CPU_AU1210; + __cpu_name[cpu] = "Au1210"; break; default: panic("Unknown Au Core!"); @@ -757,154 +816,67 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c) } } -static inline void cpu_probe_sibyte(struct cpuinfo_mips *c) +static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); switch (c->processor_id & 0xff00) { case PRID_IMP_SB1: c->cputype = CPU_SB1; + __cpu_name[cpu] = "SiByte SB1"; /* FPU in pass1 is known to have issues. */ if ((c->processor_id & 0xff) < 0x02) c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); break; case PRID_IMP_SB1A: c->cputype = CPU_SB1A; + __cpu_name[cpu] = "SiByte SB1A"; break; } } -static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c) +static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); switch (c->processor_id & 0xff00) { case PRID_IMP_SR71000: c->cputype = CPU_SR71000; + __cpu_name[cpu] = "Sandcraft SR71000"; c->scache.ways = 8; c->tlbsize = 64; break; } } -static inline void cpu_probe_nxp(struct cpuinfo_mips *c) +static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); switch (c->processor_id & 0xff00) { case PRID_IMP_PR4450: c->cputype = CPU_PR4450; + __cpu_name[cpu] = "Philips PR4450"; c->isa_level = MIPS_CPU_ISA_M32R1; break; - default: - panic("Unknown NXP Core!"); /* REVISIT: die? */ - break; } } - -static inline void cpu_probe_broadcom(struct cpuinfo_mips *c) +static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); switch (c->processor_id & 0xff00) { case PRID_IMP_BCM3302: c->cputype = CPU_BCM3302; + __cpu_name[cpu] = "Broadcom BCM3302"; break; case PRID_IMP_BCM4710: c->cputype = CPU_BCM4710; - break; - default: - c->cputype = CPU_UNKNOWN; + __cpu_name[cpu] = "Broadcom BCM4710"; break; } } const char *__cpu_name[NR_CPUS]; -/* - * Name a CPU - */ -static __cpuinit const char *cpu_to_name(struct cpuinfo_mips *c) -{ - const char *name = NULL; - - switch (c->cputype) { - case CPU_UNKNOWN: name = "unknown"; break; - case CPU_R2000: name = "R2000"; break; - case CPU_R3000: name = "R3000"; break; - case CPU_R3000A: name = "R3000A"; break; - case CPU_R3041: name = "R3041"; break; - case CPU_R3051: name = "R3051"; break; - case CPU_R3052: name = "R3052"; break; - case CPU_R3081: name = "R3081"; break; - case CPU_R3081E: name = "R3081E"; break; - case CPU_R4000PC: name = "R4000PC"; break; - case CPU_R4000SC: name = "R4000SC"; break; - case CPU_R4000MC: name = "R4000MC"; break; - case CPU_R4200: name = "R4200"; break; - case CPU_R4400PC: name = "R4400PC"; break; - case CPU_R4400SC: name = "R4400SC"; break; - case CPU_R4400MC: name = "R4400MC"; break; - case CPU_R4600: name = "R4600"; break; - case CPU_R6000: name = "R6000"; break; - case CPU_R6000A: name = "R6000A"; break; - case CPU_R8000: name = "R8000"; break; - case CPU_R10000: name = "R10000"; break; - case CPU_R12000: name = "R12000"; break; - case CPU_R14000: name = "R14000"; break; - case CPU_R4300: name = "R4300"; break; - case CPU_R4650: name = "R4650"; break; - case CPU_R4700: name = "R4700"; break; - case CPU_R5000: name = "R5000"; break; - case CPU_R5000A: name = "R5000A"; break; - case CPU_R4640: name = "R4640"; break; - case CPU_NEVADA: name = "Nevada"; break; - case CPU_RM7000: name = "RM7000"; break; - case CPU_RM9000: name = "RM9000"; break; - case CPU_R5432: name = "R5432"; break; - case CPU_4KC: name = "MIPS 4Kc"; break; - case CPU_5KC: name = "MIPS 5Kc"; break; - case CPU_R4310: name = "R4310"; break; - case CPU_SB1: name = "SiByte SB1"; break; - case CPU_SB1A: name = "SiByte SB1A"; break; - case CPU_TX3912: name = "TX3912"; break; - case CPU_TX3922: name = "TX3922"; break; - case CPU_TX3927: name = "TX3927"; break; - case CPU_AU1000: name = "Au1000"; break; - case CPU_AU1500: name = "Au1500"; break; - case CPU_AU1100: name = "Au1100"; break; - case CPU_AU1550: name = "Au1550"; break; - case CPU_AU1200: name = "Au1200"; break; - case CPU_AU1210: name = "Au1210"; break; - case CPU_AU1250: name = "Au1250"; break; - case CPU_4KEC: name = "MIPS 4KEc"; break; - case CPU_4KSC: name = "MIPS 4KSc"; break; - case CPU_VR41XX: name = "NEC Vr41xx"; break; - case CPU_R5500: name = "R5500"; break; - case CPU_TX49XX: name = "TX49xx"; break; - case CPU_20KC: name = "MIPS 20Kc"; break; - case CPU_24K: name = "MIPS 24K"; break; - case CPU_25KF: name = "MIPS 25Kf"; break; - case CPU_34K: name = "MIPS 34K"; break; - case CPU_1004K: name = "MIPS 1004K"; break; - case CPU_74K: name = "MIPS 74K"; break; - case CPU_VR4111: name = "NEC VR4111"; break; - case CPU_VR4121: name = "NEC VR4121"; break; - case CPU_VR4122: name = "NEC VR4122"; break; - case CPU_VR4131: name = "NEC VR4131"; break; - case CPU_VR4133: name = "NEC VR4133"; break; - case CPU_VR4181: name = "NEC VR4181"; break; - case CPU_VR4181A: name = "NEC VR4181A"; break; - case CPU_SR71000: name = "Sandcraft SR71000"; break; - case CPU_BCM3302: name = "Broadcom BCM3302"; break; - case CPU_BCM4710: name = "Broadcom BCM4710"; break; - case CPU_PR4450: name = "Philips PR4450"; break; - case CPU_LOONGSON2: name = "ICT Loongson-2"; break; - default: - BUG(); - } - - return name; -} - __cpuinit void cpu_probe(void) { struct cpuinfo_mips *c = ¤t_cpu_data; @@ -917,30 +889,31 @@ __cpuinit void cpu_probe(void) c->processor_id = read_c0_prid(); switch (c->processor_id & 0xff0000) { case PRID_COMP_LEGACY: - cpu_probe_legacy(c); + cpu_probe_legacy(c, cpu); break; case PRID_COMP_MIPS: - cpu_probe_mips(c); + cpu_probe_mips(c, cpu); break; case PRID_COMP_ALCHEMY: - cpu_probe_alchemy(c); + cpu_probe_alchemy(c, cpu); break; case PRID_COMP_SIBYTE: - cpu_probe_sibyte(c); + cpu_probe_sibyte(c, cpu); break; case PRID_COMP_BROADCOM: - cpu_probe_broadcom(c); + cpu_probe_broadcom(c, cpu); break; case PRID_COMP_SANDCRAFT: - cpu_probe_sandcraft(c); + cpu_probe_sandcraft(c, cpu); break; case PRID_COMP_NXP: - cpu_probe_nxp(c); + cpu_probe_nxp(c, cpu); break; - default: - c->cputype = CPU_UNKNOWN; } + BUG_ON(!__cpu_name[cpu]); + BUG_ON(c->cputype == CPU_UNKNOWN); + /* * Platform code can force the cpu type to optimize code * generation. In that case be sure the cpu type is correctly @@ -960,8 +933,6 @@ __cpuinit void cpu_probe(void) } } - __cpu_name[cpu] = cpu_to_name(c); - if (cpu_has_mips_r2) c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; else -- cgit v1.1 From 4bdebe5b4a7216bd6bfca9e9b368abad8e9f9bd9 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Sun, 26 Oct 2008 16:12:13 +0000 Subject: CHAR: Delete old and now unused DS1286 driver. It was only used by two SGI platforms which recently were converted to RTC_LIB and with RTC_LIB enabled the legacy drivers are no more selectable. Signed-off-by: Ralf Baechle Signed-off-by: Yoichi Yuasa --- arch/mips/Kconfig | 5 ----- arch/mips/configs/ip22_defconfig | 1 - arch/mips/configs/ip28_defconfig | 2 -- arch/mips/include/asm/ds1286.h | 15 --------------- 4 files changed, 23 deletions(-) delete mode 100644 arch/mips/include/asm/ds1286.h (limited to 'arch') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 653574b..f4af967 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -327,7 +327,6 @@ config SGI_IP22 select IP22_CPU_SCACHE select IRQ_CPU select GENERIC_ISA_DMA_SUPPORT_BROKEN - select SGI_HAS_DS1286 select SGI_HAS_I8042 select SGI_HAS_INDYDOG select SGI_HAS_HAL2 @@ -382,7 +381,6 @@ config SGI_IP28 select HW_HAS_EISA select I8253 select I8259 - select SGI_HAS_DS1286 select SGI_HAS_I8042 select SGI_HAS_INDYDOG select SGI_HAS_HAL2 @@ -893,9 +891,6 @@ config EMMA2RH config SERIAL_RM9000 bool -config SGI_HAS_DS1286 - bool - config SGI_HAS_INDYDOG bool diff --git a/arch/mips/configs/ip22_defconfig b/arch/mips/configs/ip22_defconfig index cc8e6bf..f719bf5 100644 --- a/arch/mips/configs/ip22_defconfig +++ b/arch/mips/configs/ip22_defconfig @@ -771,7 +771,6 @@ CONFIG_WATCHDOG=y CONFIG_INDYDOG=m # CONFIG_HW_RANDOM is not set # CONFIG_RTC is not set -CONFIG_SGI_DS1286=m # CONFIG_R3964 is not set CONFIG_RAW_DRIVER=m CONFIG_MAX_RAW_DEVS=256 diff --git a/arch/mips/configs/ip28_defconfig b/arch/mips/configs/ip28_defconfig index 822b01f..70a744e 100644 --- a/arch/mips/configs/ip28_defconfig +++ b/arch/mips/configs/ip28_defconfig @@ -70,7 +70,6 @@ CONFIG_CPU_BIG_ENDIAN=y CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_SWAP_IO_SPACE=y -CONFIG_SGI_HAS_DS1286=y CONFIG_SGI_HAS_INDYDOG=y CONFIG_SGI_HAS_SEEQ=y CONFIG_SGI_HAS_WD93=y @@ -585,7 +584,6 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_IPMI_HANDLER is not set # CONFIG_HW_RANDOM is not set # CONFIG_RTC is not set -CONFIG_SGI_DS1286=y # CONFIG_DTLK is not set # CONFIG_R3964 is not set # CONFIG_RAW_DRIVER is not set diff --git a/arch/mips/include/asm/ds1286.h b/arch/mips/include/asm/ds1286.h deleted file mode 100644 index 6983b6f..0000000 --- a/arch/mips/include/asm/ds1286.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Machine dependent access functions for RTC registers. - * - * Copyright (C) 2003 Ralf Baechle (ralf@linux-mips.org) - */ -#ifndef _ASM_DS1286_H -#define _ASM_DS1286_H - -#include - -#endif /* _ASM_DS1286_H */ -- cgit v1.1 From 09d9327b3420002c9952a81db37effec9dc1135e Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Mon, 27 Oct 2008 13:10:29 +0000 Subject: CHAR: Delete old and now unused M48T35 RTC driver for SGI IP27. It was only used by this one SGI platform which recently was converted to RTC_LIB and with RTC_LIB enabled the legacy drivers are no more selectable. Signed-off-by: Ralf Baechle --- arch/mips/configs/ip27_defconfig | 1 - arch/mips/include/asm/m48t35.h | 27 --------------------------- 2 files changed, 28 deletions(-) delete mode 100644 arch/mips/include/asm/m48t35.h (limited to 'arch') diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig index 831d3e5..34ea319 100644 --- a/arch/mips/configs/ip27_defconfig +++ b/arch/mips/configs/ip27_defconfig @@ -701,7 +701,6 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_WATCHDOG is not set CONFIG_HW_RANDOM=m # CONFIG_RTC is not set -CONFIG_SGI_IP27_RTC=y # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set # CONFIG_DRM is not set diff --git a/arch/mips/include/asm/m48t35.h b/arch/mips/include/asm/m48t35.h deleted file mode 100644 index f44852e..0000000 --- a/arch/mips/include/asm/m48t35.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Registers for the SGS-Thomson M48T35 Timekeeper RAM chip - */ -#ifndef _ASM_M48T35_H -#define _ASM_M48T35_H - -#include - -extern spinlock_t rtc_lock; - -struct m48t35_rtc { - volatile u8 pad[0x7ff8]; /* starts at 0x7ff8 */ - volatile u8 control; - volatile u8 sec; - volatile u8 min; - volatile u8 hour; - volatile u8 day; - volatile u8 date; - volatile u8 month; - volatile u8 year; -}; - -#define M48T35_RTC_SET 0x80 -#define M48T35_RTC_STOPPED 0x80 -#define M48T35_RTC_READ 0x40 - -#endif /* _ASM_M48T35_H */ -- cgit v1.1