From eaaaeef392cb245e415c31d480ed2d5a466fd88f Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Mon, 14 Jun 2010 15:16:53 +0900 Subject: sh: Add kprobe-based event tracer. This follows the x86/ppc changes for kprobe-based event tracing on sh. While kprobes is only supported on 32-bit sh, we provide the API for HAVE_REGS_AND_STACK_ACCESS_API for both 32 and 64-bit. Signed-off-by: Paul Mundt --- arch/sh/Kconfig | 1 + arch/sh/include/asm/kprobes.h | 1 - arch/sh/include/asm/processor_32.h | 3 -- arch/sh/include/asm/processor_64.h | 3 -- arch/sh/include/asm/ptrace.h | 89 ++++++++++++++++++++++++++++++++++++-- arch/sh/kernel/Makefile | 2 +- arch/sh/kernel/ptrace.c | 33 ++++++++++++++ arch/sh/kernel/ptrace_32.c | 27 ++++++++++++ arch/sh/kernel/ptrace_64.c | 79 +++++++++++++++++++++++++++++++++ 9 files changed, 227 insertions(+), 11 deletions(-) create mode 100644 arch/sh/kernel/ptrace.c (limited to 'arch') diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 573fca1..e6b1f20 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -23,6 +23,7 @@ config SUPERH select HAVE_KERNEL_LZMA select HAVE_KERNEL_LZO select HAVE_SYSCALL_TRACEPOINTS + select HAVE_REGS_AND_STACK_ACCESS_API select RTC_LIB select GENERIC_ATOMIC64 help diff --git a/arch/sh/include/asm/kprobes.h b/arch/sh/include/asm/kprobes.h index 036c331..134f398 100644 --- a/arch/sh/include/asm/kprobes.h +++ b/arch/sh/include/asm/kprobes.h @@ -16,7 +16,6 @@ typedef insn_size_t kprobe_opcode_t; ? (MAX_STACK_SIZE) \ : (((unsigned long)current_thread_info()) + THREAD_SIZE - (ADDR))) -#define regs_return_value(_regs) ((_regs)->regs[0]) #define flush_insn_slot(p) do { } while (0) #define kretprobe_blacklist_size 0 diff --git a/arch/sh/include/asm/processor_32.h b/arch/sh/include/asm/processor_32.h index 61a445d..46d5179 100644 --- a/arch/sh/include/asm/processor_32.h +++ b/arch/sh/include/asm/processor_32.h @@ -13,7 +13,6 @@ #include #include #include -#include #include /* @@ -194,8 +193,6 @@ extern unsigned long get_wchan(struct task_struct *p); #define KSTK_EIP(tsk) (task_pt_regs(tsk)->pc) #define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[15]) -#define user_stack_pointer(_regs) ((_regs)->regs[15]) - #if defined(CONFIG_CPU_SH2A) || defined(CONFIG_CPU_SH4) #define PREFETCH_STRIDE L1_CACHE_BYTES #define ARCH_HAS_PREFETCH diff --git a/arch/sh/include/asm/processor_64.h b/arch/sh/include/asm/processor_64.h index 621bc46..2a541dd 100644 --- a/arch/sh/include/asm/processor_64.h +++ b/arch/sh/include/asm/processor_64.h @@ -17,7 +17,6 @@ #include #include #include -#include #include /* @@ -231,7 +230,5 @@ extern unsigned long get_wchan(struct task_struct *p); #define KSTK_EIP(tsk) ((tsk)->thread.pc) #define KSTK_ESP(tsk) ((tsk)->thread.sp) -#define user_stack_pointer(_regs) ((_regs)->regs[15]) - #endif /* __ASSEMBLY__ */ #endif /* __ASM_SH_PROCESSOR_64_H */ diff --git a/arch/sh/include/asm/ptrace.h b/arch/sh/include/asm/ptrace.h index 2168fde..33b3f37 100644 --- a/arch/sh/include/asm/ptrace.h +++ b/arch/sh/include/asm/ptrace.h @@ -1,6 +1,8 @@ #ifndef __ASM_SH_PTRACE_H #define __ASM_SH_PTRACE_H +#include + /* * Copyright (C) 1999, 2000 Niibe Yutaka * @@ -14,6 +16,13 @@ struct pt_regs { unsigned long long tregs[8]; unsigned long long pad[2]; }; + +#define MAX_REG_OFFSET offsetof(struct pt_regs, tregs[7]) +#define regs_return_value(regs) ((regs)->regs[3]) + +#define TREGS_OFFSET_NAME(num) \ + {.name = __stringify(tr##num), .offset = offsetof(struct pt_regs, tregs[num])} + #else /* * GCC defines register number like this: @@ -66,6 +75,9 @@ struct pt_regs { long tra; }; +#define MAX_REG_OFFSET offsetof(struct pt_regs, tra) +#define regs_return_value(regs) ((regs)->regs[0]) + /* * This struct defines the way the DSP registers are stored on the * kernel stack during a system call or other kernel entry. @@ -113,16 +125,87 @@ struct pt_dspregs { #include #define user_mode(regs) (((regs)->sr & 0x40000000)==0) +#define user_stack_pointer(regs) ((unsigned long)(regs)->regs[15]) +#define kernel_stack_pointer(regs) ((unsigned long)(regs)->regs[15]) #define instruction_pointer(regs) ((unsigned long)(regs)->pc) extern void show_regs(struct pt_regs *); +#define arch_has_single_step() (1) + /* - * These are defined as per linux/ptrace.h. + * kprobe-based event tracer support */ -struct task_struct; +#include +#include -#define arch_has_single_step() (1) +struct pt_regs_offset { + const char *name; + int offset; +}; + +#define REG_OFFSET_NAME(r) {.name = #r, .offset = offsetof(struct pt_regs, r)} +#define REGS_OFFSET_NAME(num) \ + {.name = __stringify(r##num), .offset = offsetof(struct pt_regs, regs[num])} +#define REG_OFFSET_END {.name = NULL, .offset = 0} + +/* Query offset/name of register from its name/offset */ +extern int regs_query_register_offset(const char *name); +extern const char *regs_query_register_name(unsigned int offset); + +extern const struct pt_regs_offset regoffset_table[]; + +/** + * regs_get_register() - get register value from its offset + * @regs: pt_regs from which register value is gotten. + * @offset: offset number of the register. + * + * regs_get_register returns the value of a register. The @offset is the + * offset of the register in struct pt_regs address which specified by @regs. + * If @offset is bigger than MAX_REG_OFFSET, this returns 0. + */ +static inline unsigned long regs_get_register(struct pt_regs *regs, + unsigned int offset) +{ + if (unlikely(offset > MAX_REG_OFFSET)) + return 0; + return *(unsigned long *)((unsigned long)regs + offset); +} + +/** + * regs_within_kernel_stack() - check the address in the stack + * @regs: pt_regs which contains kernel stack pointer. + * @addr: address which is checked. + * + * regs_within_kernel_stack() checks @addr is within the kernel stack page(s). + * If @addr is within the kernel stack, it returns true. If not, returns false. + */ +static inline int regs_within_kernel_stack(struct pt_regs *regs, + unsigned long addr) +{ + return ((addr & ~(THREAD_SIZE - 1)) == + (kernel_stack_pointer(regs) & ~(THREAD_SIZE - 1))); +} + +/** + * regs_get_kernel_stack_nth() - get Nth entry of the stack + * @regs: pt_regs which contains kernel stack pointer. + * @n: stack entry number. + * + * regs_get_kernel_stack_nth() returns @n th entry of the kernel stack which + * is specified by @regs. If the @n th entry is NOT in the kernel stack, + * this returns 0. + */ +static inline unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, + unsigned int n) +{ + unsigned long *addr = (unsigned long *)kernel_stack_pointer(regs); + addr += n; + if (regs_within_kernel_stack(regs, (unsigned long)addr)) + return *addr; + else + return 0; +} struct perf_event; struct perf_sample_data; diff --git a/arch/sh/kernel/Makefile b/arch/sh/kernel/Makefile index e25f3c6..1086ba1 100644 --- a/arch/sh/kernel/Makefile +++ b/arch/sh/kernel/Makefile @@ -14,7 +14,7 @@ CFLAGS_REMOVE_return_address.o = -pg obj-y := clkdev.o debugtraps.o dma-nommu.o dumpstack.o \ idle.o io.o irq.o \ irq_$(BITS).o machvec.o nmi_debug.o process.o \ - process_$(BITS).o ptrace_$(BITS).o \ + process_$(BITS).o ptrace.o ptrace_$(BITS).o \ reboot.o return_address.o \ setup.o signal_$(BITS).o sys_sh.o sys_sh$(BITS).o \ syscalls_$(BITS).o time.o topology.o traps.o \ diff --git a/arch/sh/kernel/ptrace.c b/arch/sh/kernel/ptrace.c new file mode 100644 index 0000000..0a05983 --- /dev/null +++ b/arch/sh/kernel/ptrace.c @@ -0,0 +1,33 @@ +#include + +/** + * regs_query_register_offset() - query register offset from its name + * @name: the name of a register + * + * regs_query_register_offset() returns the offset of a register in struct + * pt_regs from its name. If the name is invalid, this returns -EINVAL; + */ +int regs_query_register_offset(const char *name) +{ + const struct pt_regs_offset *roff; + for (roff = regoffset_table; roff->name != NULL; roff++) + if (!strcmp(roff->name, name)) + return roff->offset; + return -EINVAL; +} + +/** + * regs_query_register_name() - query register name from its offset + * @offset: the offset of a register in struct pt_regs. + * + * regs_query_register_name() returns the name of a register from its + * offset in struct pt_regs. If the @offset is invalid, this returns NULL; + */ +const char *regs_query_register_name(unsigned int offset) +{ + const struct pt_regs_offset *roff; + for (roff = regoffset_table; roff->name != NULL; roff++) + if (roff->offset == offset) + return roff->name; + return NULL; +} diff --git a/arch/sh/kernel/ptrace_32.c b/arch/sh/kernel/ptrace_32.c index 6c4bbba..2cd42b5 100644 --- a/arch/sh/kernel/ptrace_32.c +++ b/arch/sh/kernel/ptrace_32.c @@ -274,6 +274,33 @@ static int dspregs_active(struct task_struct *target, } #endif +const struct pt_regs_offset regoffset_table[] = { + REGS_OFFSET_NAME(0), + REGS_OFFSET_NAME(1), + REGS_OFFSET_NAME(2), + REGS_OFFSET_NAME(3), + REGS_OFFSET_NAME(4), + REGS_OFFSET_NAME(5), + REGS_OFFSET_NAME(6), + REGS_OFFSET_NAME(7), + REGS_OFFSET_NAME(8), + REGS_OFFSET_NAME(9), + REGS_OFFSET_NAME(10), + REGS_OFFSET_NAME(11), + REGS_OFFSET_NAME(12), + REGS_OFFSET_NAME(13), + REGS_OFFSET_NAME(14), + REGS_OFFSET_NAME(15), + REG_OFFSET_NAME(pc), + REG_OFFSET_NAME(pr), + REG_OFFSET_NAME(sr), + REG_OFFSET_NAME(gbr), + REG_OFFSET_NAME(mach), + REG_OFFSET_NAME(macl), + REG_OFFSET_NAME(tra), + REG_OFFSET_END, +}; + /* * These are our native regset flavours. */ diff --git a/arch/sh/kernel/ptrace_64.c b/arch/sh/kernel/ptrace_64.c index 5fd644d..b978170 100644 --- a/arch/sh/kernel/ptrace_64.c +++ b/arch/sh/kernel/ptrace_64.c @@ -252,6 +252,85 @@ static int fpregs_active(struct task_struct *target, } #endif +const struct pt_regs_offset regoffset_table[] = { + REG_OFFSET_NAME(pc), + REG_OFFSET_NAME(sr), + REG_OFFSET_NAME(syscall_nr), + REGS_OFFSET_NAME(0), + REGS_OFFSET_NAME(1), + REGS_OFFSET_NAME(2), + REGS_OFFSET_NAME(3), + REGS_OFFSET_NAME(4), + REGS_OFFSET_NAME(5), + REGS_OFFSET_NAME(6), + REGS_OFFSET_NAME(7), + REGS_OFFSET_NAME(8), + REGS_OFFSET_NAME(9), + REGS_OFFSET_NAME(10), + REGS_OFFSET_NAME(11), + REGS_OFFSET_NAME(12), + REGS_OFFSET_NAME(13), + REGS_OFFSET_NAME(14), + REGS_OFFSET_NAME(15), + REGS_OFFSET_NAME(16), + REGS_OFFSET_NAME(17), + REGS_OFFSET_NAME(18), + REGS_OFFSET_NAME(19), + REGS_OFFSET_NAME(20), + REGS_OFFSET_NAME(21), + REGS_OFFSET_NAME(22), + REGS_OFFSET_NAME(23), + REGS_OFFSET_NAME(24), + REGS_OFFSET_NAME(25), + REGS_OFFSET_NAME(26), + REGS_OFFSET_NAME(27), + REGS_OFFSET_NAME(28), + REGS_OFFSET_NAME(29), + REGS_OFFSET_NAME(30), + REGS_OFFSET_NAME(31), + REGS_OFFSET_NAME(32), + REGS_OFFSET_NAME(33), + REGS_OFFSET_NAME(34), + REGS_OFFSET_NAME(35), + REGS_OFFSET_NAME(36), + REGS_OFFSET_NAME(37), + REGS_OFFSET_NAME(38), + REGS_OFFSET_NAME(39), + REGS_OFFSET_NAME(40), + REGS_OFFSET_NAME(41), + REGS_OFFSET_NAME(42), + REGS_OFFSET_NAME(43), + REGS_OFFSET_NAME(44), + REGS_OFFSET_NAME(45), + REGS_OFFSET_NAME(46), + REGS_OFFSET_NAME(47), + REGS_OFFSET_NAME(48), + REGS_OFFSET_NAME(49), + REGS_OFFSET_NAME(50), + REGS_OFFSET_NAME(51), + REGS_OFFSET_NAME(52), + REGS_OFFSET_NAME(53), + REGS_OFFSET_NAME(54), + REGS_OFFSET_NAME(55), + REGS_OFFSET_NAME(56), + REGS_OFFSET_NAME(57), + REGS_OFFSET_NAME(58), + REGS_OFFSET_NAME(59), + REGS_OFFSET_NAME(60), + REGS_OFFSET_NAME(61), + REGS_OFFSET_NAME(62), + REGS_OFFSET_NAME(63), + TREGS_OFFSET_NAME(0), + TREGS_OFFSET_NAME(1), + TREGS_OFFSET_NAME(2), + TREGS_OFFSET_NAME(3), + TREGS_OFFSET_NAME(4), + TREGS_OFFSET_NAME(5), + TREGS_OFFSET_NAME(6), + TREGS_OFFSET_NAME(7), + REG_OFFSET_END, +}; + /* * These are our native regset flavours. */ -- cgit v1.1 From da28c597996a964a195529595c37f7aacd6dad09 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Mon, 14 Jun 2010 16:02:47 +0900 Subject: sh: split out ptrace header for _32/_64 variants. asm/ptrace.h is getting a bit messy, with the _32/_64-specific changes being fairly insular. This splits out the header accordingly. Signed-off-by: Paul Mundt --- arch/sh/include/asm/Kbuild | 2 + arch/sh/include/asm/ptrace.h | 110 +++++----------------------------------- arch/sh/include/asm/ptrace_32.h | 83 ++++++++++++++++++++++++++++++ arch/sh/include/asm/ptrace_64.h | 20 ++++++++ 4 files changed, 117 insertions(+), 98 deletions(-) create mode 100644 arch/sh/include/asm/ptrace_32.h create mode 100644 arch/sh/include/asm/ptrace_64.h (limited to 'arch') diff --git a/arch/sh/include/asm/Kbuild b/arch/sh/include/asm/Kbuild index 46cb934..b4d3462 100644 --- a/arch/sh/include/asm/Kbuild +++ b/arch/sh/include/asm/Kbuild @@ -8,3 +8,5 @@ unifdef-y += unistd_32.h unifdef-y += unistd_64.h unifdef-y += posix_types_32.h unifdef-y += posix_types_64.h +unifdef-y += ptrace_32.h +unifdef-y += ptrace_64.h diff --git a/arch/sh/include/asm/ptrace.h b/arch/sh/include/asm/ptrace.h index 33b3f37..f6edc10 100644 --- a/arch/sh/include/asm/ptrace.h +++ b/arch/sh/include/asm/ptrace.h @@ -1,104 +1,9 @@ #ifndef __ASM_SH_PTRACE_H #define __ASM_SH_PTRACE_H -#include - /* * Copyright (C) 1999, 2000 Niibe Yutaka - * - */ -#if defined(__SH5__) -struct pt_regs { - unsigned long long pc; - unsigned long long sr; - long long syscall_nr; - unsigned long long regs[63]; - unsigned long long tregs[8]; - unsigned long long pad[2]; -}; - -#define MAX_REG_OFFSET offsetof(struct pt_regs, tregs[7]) -#define regs_return_value(regs) ((regs)->regs[3]) - -#define TREGS_OFFSET_NAME(num) \ - {.name = __stringify(tr##num), .offset = offsetof(struct pt_regs, tregs[num])} - -#else -/* - * GCC defines register number like this: - * ----------------------------- - * 0 - 15 are integer registers - * 17 - 22 are control/special registers - * 24 - 39 fp registers - * 40 - 47 xd registers - * 48 - fpscr register - * ----------------------------- - * - * We follows above, except: - * 16 --- program counter (PC) - * 22 --- syscall # - * 23 --- floating point communication register - */ -#define REG_REG0 0 -#define REG_REG15 15 - -#define REG_PC 16 - -#define REG_PR 17 -#define REG_SR 18 -#define REG_GBR 19 -#define REG_MACH 20 -#define REG_MACL 21 - -#define REG_SYSCALL 22 - -#define REG_FPREG0 23 -#define REG_FPREG15 38 -#define REG_XFREG0 39 -#define REG_XFREG15 54 - -#define REG_FPSCR 55 -#define REG_FPUL 56 - -/* - * This struct defines the way the registers are stored on the - * kernel stack during a system call or other kernel entry. - */ -struct pt_regs { - unsigned long regs[16]; - unsigned long pc; - unsigned long pr; - unsigned long sr; - unsigned long gbr; - unsigned long mach; - unsigned long macl; - long tra; -}; - -#define MAX_REG_OFFSET offsetof(struct pt_regs, tra) -#define regs_return_value(regs) ((regs)->regs[0]) - -/* - * This struct defines the way the DSP registers are stored on the - * kernel stack during a system call or other kernel entry. */ -struct pt_dspregs { - unsigned long a1; - unsigned long a0g; - unsigned long a1g; - unsigned long m0; - unsigned long m1; - unsigned long a0; - unsigned long x0; - unsigned long x1; - unsigned long y0; - unsigned long y1; - unsigned long dsr; - unsigned long rs; - unsigned long re; - unsigned long mod; -}; -#endif #define PTRACE_GETREGS 12 /* General registers */ #define PTRACE_SETREGS 13 @@ -119,7 +24,17 @@ struct pt_dspregs { #define PT_DATA_ADDR 248 /* &(struct user)->start_data */ #define PT_TEXT_LEN 252 +#if defined(__SH5__) || defined(CONFIG_CPU_SH5) +#include "ptrace_64.h" +#else +#include "ptrace_32.h" +#endif + #ifdef __KERNEL__ + +#include +#include +#include #include #include #include @@ -136,9 +51,6 @@ extern void show_regs(struct pt_regs *); /* * kprobe-based event tracer support */ -#include -#include - struct pt_regs_offset { const char *name; int offset; @@ -147,6 +59,8 @@ struct pt_regs_offset { #define REG_OFFSET_NAME(r) {.name = #r, .offset = offsetof(struct pt_regs, r)} #define REGS_OFFSET_NAME(num) \ {.name = __stringify(r##num), .offset = offsetof(struct pt_regs, regs[num])} +#define TREGS_OFFSET_NAME(num) \ + {.name = __stringify(tr##num), .offset = offsetof(struct pt_regs, tregs[num])} #define REG_OFFSET_END {.name = NULL, .offset = 0} /* Query offset/name of register from its name/offset */ diff --git a/arch/sh/include/asm/ptrace_32.h b/arch/sh/include/asm/ptrace_32.h new file mode 100644 index 0000000..35d9e25 --- /dev/null +++ b/arch/sh/include/asm/ptrace_32.h @@ -0,0 +1,83 @@ +#ifndef __ASM_SH_PTRACE_32_H +#define __ASM_SH_PTRACE_32_H + +/* + * GCC defines register number like this: + * ----------------------------- + * 0 - 15 are integer registers + * 17 - 22 are control/special registers + * 24 - 39 fp registers + * 40 - 47 xd registers + * 48 - fpscr register + * ----------------------------- + * + * We follows above, except: + * 16 --- program counter (PC) + * 22 --- syscall # + * 23 --- floating point communication register + */ +#define REG_REG0 0 +#define REG_REG15 15 + +#define REG_PC 16 + +#define REG_PR 17 +#define REG_SR 18 +#define REG_GBR 19 +#define REG_MACH 20 +#define REG_MACL 21 + +#define REG_SYSCALL 22 + +#define REG_FPREG0 23 +#define REG_FPREG15 38 +#define REG_XFREG0 39 +#define REG_XFREG15 54 + +#define REG_FPSCR 55 +#define REG_FPUL 56 + +/* + * This struct defines the way the registers are stored on the + * kernel stack during a system call or other kernel entry. + */ +struct pt_regs { + unsigned long regs[16]; + unsigned long pc; + unsigned long pr; + unsigned long sr; + unsigned long gbr; + unsigned long mach; + unsigned long macl; + long tra; +}; + +/* + * This struct defines the way the DSP registers are stored on the + * kernel stack during a system call or other kernel entry. + */ +struct pt_dspregs { + unsigned long a1; + unsigned long a0g; + unsigned long a1g; + unsigned long m0; + unsigned long m1; + unsigned long a0; + unsigned long x0; + unsigned long x1; + unsigned long y0; + unsigned long y1; + unsigned long dsr; + unsigned long rs; + unsigned long re; + unsigned long mod; +}; + +#ifdef __KERNEL__ + +#define MAX_REG_OFFSET offsetof(struct pt_regs, tra) +#define regs_return_value(regs) ((regs)->regs[0]) + +#endif /* __KERNEL__ */ + +#endif /* __ASM_SH_PTRACE_32_H */ diff --git a/arch/sh/include/asm/ptrace_64.h b/arch/sh/include/asm/ptrace_64.h new file mode 100644 index 0000000..d43c1cb --- /dev/null +++ b/arch/sh/include/asm/ptrace_64.h @@ -0,0 +1,20 @@ +#ifndef __ASM_SH_PTRACE_64_H +#define __ASM_SH_PTRACE_64_H + +struct pt_regs { + unsigned long long pc; + unsigned long long sr; + long long syscall_nr; + unsigned long long regs[63]; + unsigned long long tregs[8]; + unsigned long long pad[2]; +}; + +#ifdef __KERNEL__ + +#define MAX_REG_OFFSET offsetof(struct pt_regs, tregs[7]) +#define regs_return_value(regs) ((regs)->regs[3]) + +#endif /* __KERNEL__ */ + +#endif /* __ASM_SH_PTRACE_64_H */ -- cgit v1.1 From 57fcfdf9b2bbe8ea47771ffc16c418a20e4173c6 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Mon, 14 Jun 2010 17:06:10 +0900 Subject: sh: kprobes SMP support. Presently kprobes support relies on several saved opcode variables for saving and restoring state, without any specific locking. This is inherently racy on SMP, and given that we already use per-CPU variables for everything else, convert these over too. Signed-off-by: Paul Mundt --- arch/sh/kernel/kprobes.c | 100 +++++++++++++++++++++++------------------------ 1 file changed, 50 insertions(+), 50 deletions(-) (limited to 'arch') diff --git a/arch/sh/kernel/kprobes.c b/arch/sh/kernel/kprobes.c index 4049d99..1208b09 100644 --- a/arch/sh/kernel/kprobes.c +++ b/arch/sh/kernel/kprobes.c @@ -20,9 +20,9 @@ DEFINE_PER_CPU(struct kprobe *, current_kprobe) = NULL; DEFINE_PER_CPU(struct kprobe_ctlblk, kprobe_ctlblk); -static struct kprobe saved_current_opcode; -static struct kprobe saved_next_opcode; -static struct kprobe saved_next_opcode2; +static DEFINE_PER_CPU(struct kprobe, saved_current_opcode); +static DEFINE_PER_CPU(struct kprobe, saved_next_opcode); +static DEFINE_PER_CPU(struct kprobe, saved_next_opcode2); #define OPCODE_JMP(x) (((x) & 0xF0FF) == 0x402b) #define OPCODE_JSR(x) (((x) & 0xF0FF) == 0x400b) @@ -102,16 +102,21 @@ int __kprobes kprobe_handle_illslot(unsigned long pc) void __kprobes arch_remove_kprobe(struct kprobe *p) { - if (saved_next_opcode.addr != 0x0) { + struct kprobe *saved = &__get_cpu_var(saved_next_opcode); + + if (saved->addr) { arch_disarm_kprobe(p); - arch_disarm_kprobe(&saved_next_opcode); - saved_next_opcode.addr = 0x0; - saved_next_opcode.opcode = 0x0; - - if (saved_next_opcode2.addr != 0x0) { - arch_disarm_kprobe(&saved_next_opcode2); - saved_next_opcode2.addr = 0x0; - saved_next_opcode2.opcode = 0x0; + arch_disarm_kprobe(saved); + + saved->addr = NULL; + saved->opcode = 0; + + saved = &__get_cpu_var(saved_next_opcode2); + if (saved->addr) { + arch_disarm_kprobe(saved); + + saved->addr = NULL; + saved->opcode = 0; } } } @@ -141,57 +146,59 @@ static void __kprobes set_current_kprobe(struct kprobe *p, struct pt_regs *regs, */ static void __kprobes prepare_singlestep(struct kprobe *p, struct pt_regs *regs) { - kprobe_opcode_t *addr = NULL; - saved_current_opcode.addr = (kprobe_opcode_t *) (regs->pc); - addr = saved_current_opcode.addr; + __get_cpu_var(saved_current_opcode).addr = (kprobe_opcode_t *)regs->pc; if (p != NULL) { + struct kprobe *op1, *op2; + arch_disarm_kprobe(p); + op1 = &__get_cpu_var(saved_next_opcode); + op2 = &__get_cpu_var(saved_next_opcode2); + if (OPCODE_JSR(p->opcode) || OPCODE_JMP(p->opcode)) { unsigned int reg_nr = ((p->opcode >> 8) & 0x000F); - saved_next_opcode.addr = - (kprobe_opcode_t *) regs->regs[reg_nr]; + op1->addr = (kprobe_opcode_t *) regs->regs[reg_nr]; } else if (OPCODE_BRA(p->opcode) || OPCODE_BSR(p->opcode)) { unsigned long disp = (p->opcode & 0x0FFF); - saved_next_opcode.addr = + op1->addr = (kprobe_opcode_t *) (regs->pc + 4 + disp * 2); } else if (OPCODE_BRAF(p->opcode) || OPCODE_BSRF(p->opcode)) { unsigned int reg_nr = ((p->opcode >> 8) & 0x000F); - saved_next_opcode.addr = + op1->addr = (kprobe_opcode_t *) (regs->pc + 4 + regs->regs[reg_nr]); } else if (OPCODE_RTS(p->opcode)) { - saved_next_opcode.addr = (kprobe_opcode_t *) regs->pr; + op1->addr = (kprobe_opcode_t *) regs->pr; } else if (OPCODE_BF(p->opcode) || OPCODE_BT(p->opcode)) { unsigned long disp = (p->opcode & 0x00FF); /* case 1 */ - saved_next_opcode.addr = p->addr + 1; + op1->addr = p->addr + 1; /* case 2 */ - saved_next_opcode2.addr = + op2->addr = (kprobe_opcode_t *) (regs->pc + 4 + disp * 2); - saved_next_opcode2.opcode = *(saved_next_opcode2.addr); - arch_arm_kprobe(&saved_next_opcode2); + op2->opcode = *(op2->addr); + arch_arm_kprobe(op2); } else if (OPCODE_BF_S(p->opcode) || OPCODE_BT_S(p->opcode)) { unsigned long disp = (p->opcode & 0x00FF); /* case 1 */ - saved_next_opcode.addr = p->addr + 2; + op1->addr = p->addr + 2; /* case 2 */ - saved_next_opcode2.addr = + op2->addr = (kprobe_opcode_t *) (regs->pc + 4 + disp * 2); - saved_next_opcode2.opcode = *(saved_next_opcode2.addr); - arch_arm_kprobe(&saved_next_opcode2); + op2->opcode = *(op2->addr); + arch_arm_kprobe(op2); } else { - saved_next_opcode.addr = p->addr + 1; + op1->addr = p->addr + 1; } - saved_next_opcode.opcode = *(saved_next_opcode.addr); - arch_arm_kprobe(&saved_next_opcode); + op1->opcode = *(op1->addr); + arch_arm_kprobe(op1); } } @@ -376,21 +383,23 @@ static int __kprobes post_kprobe_handler(struct pt_regs *regs) cur->post_handler(cur, regs, 0); } - if (saved_next_opcode.addr != 0x0) { - arch_disarm_kprobe(&saved_next_opcode); - saved_next_opcode.addr = 0x0; - saved_next_opcode.opcode = 0x0; + p = &__get_cpu_var(saved_next_opcode); + if (p->addr) { + arch_disarm_kprobe(p); + p->addr = NULL; + p->opcode = 0; - addr = saved_current_opcode.addr; - saved_current_opcode.addr = 0x0; + addr = __get_cpu_var(saved_current_opcode).addr; + __get_cpu_var(saved_current_opcode).addr = NULL; p = get_kprobe(addr); arch_arm_kprobe(p); - if (saved_next_opcode2.addr != 0x0) { - arch_disarm_kprobe(&saved_next_opcode2); - saved_next_opcode2.addr = 0x0; - saved_next_opcode2.opcode = 0x0; + p = &__get_cpu_var(saved_next_opcode2); + if (p->addr) { + arch_disarm_kprobe(p); + p->addr = NULL; + p->opcode = 0; } } @@ -572,14 +581,5 @@ static struct kprobe trampoline_p = { int __init arch_init_kprobes(void) { - saved_next_opcode.addr = 0x0; - saved_next_opcode.opcode = 0x0; - - saved_current_opcode.addr = 0x0; - saved_current_opcode.opcode = 0x0; - - saved_next_opcode2.addr = 0x0; - saved_next_opcode2.opcode = 0x0; - return register_kprobe(&trampoline_p); } -- cgit v1.1 From 9a9fcfa04e86d26dd6129eb08165b696d602a118 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Mon, 14 Jun 2010 18:02:13 +0900 Subject: sh: update the FDPIC relocations. Now that the FDPIC relocations have been given fixed numbers upstream, switch to using those. The previous values only applied to experimental toolchains that never made it in to the wild, so the impact remains minimal. Signed-off-by: Paul Mundt --- arch/sh/include/asm/elf.h | 27 ++++++++------------------- 1 file changed, 8 insertions(+), 19 deletions(-) (limited to 'arch') diff --git a/arch/sh/include/asm/elf.h b/arch/sh/include/asm/elf.h index ce830fa..f38112b 100644 --- a/arch/sh/include/asm/elf.h +++ b/arch/sh/include/asm/elf.h @@ -50,25 +50,14 @@ #define R_SH_GOTPC 167 /* FDPIC relocs */ -#define R_SH_GOT20 70 -#define R_SH_GOTOFF20 71 -#define R_SH_GOTFUNCDESC 72 -#define R_SH_GOTFUNCDESC20 73 -#define R_SH_GOTOFFFUNCDESC 74 -#define R_SH_GOTOFFFUNCDESC20 75 -#define R_SH_FUNCDESC 76 -#define R_SH_FUNCDESC_VALUE 77 - -#if 0 /* XXX - later .. */ -#define R_SH_GOT20 198 -#define R_SH_GOTOFF20 199 -#define R_SH_GOTFUNCDESC 200 -#define R_SH_GOTFUNCDESC20 201 -#define R_SH_GOTOFFFUNCDESC 202 -#define R_SH_GOTOFFFUNCDESC20 203 -#define R_SH_FUNCDESC 204 -#define R_SH_FUNCDESC_VALUE 205 -#endif +#define R_SH_GOT20 201 +#define R_SH_GOTOFF20 202 +#define R_SH_GOTFUNCDESC 203 +#define R_SH_GOTFUNCDESC20 204 +#define R_SH_GOTOFFFUNCDESC 205 +#define R_SH_GOTOFFFUNCDESC20 206 +#define R_SH_FUNCDESC 207 +#define R_SH_FUNCDESC_VALUE 208 /* SHmedia relocs */ #define R_SH_IMM_LOW16 246 -- cgit v1.1 From 3a598264436e94c410c413088a7873fcad33616c Mon Sep 17 00:00:00 2001 From: Hitoshi Mitake Date: Mon, 21 Jun 2010 15:10:51 +0900 Subject: sh: SH-2007 board support. This patch series adds support for ITO Co., Ltd.'s SH-2007 reference platform (A PC-104 based SH7780 platform). This is a direct port of the out-of-tree board support from the vendor's kernel, originally located at: http://ms-n.org/sh-linux/kernel/ More information on the board and the vendor can be obtained from the vendor's site at: http://www.itonet.co.jp/ Presently supported peripherals are CF and ethernet, with support for the on-board IDE still pending further testing. Reviewed-by: Nobuhiro Iwamatsu Reviewed-by: Magnus Damm Signed-off-by: Hitoshi Mitake Signed-off-by: Paul Mundt --- arch/sh/boards/Kconfig | 11 + arch/sh/boards/Makefile | 1 + arch/sh/boards/board-sh2007.c | 133 +++ arch/sh/configs/sh2007_defconfig | 1357 +++++++++++++++++++++++++++++ arch/sh/include/mach-common/mach/sh2007.h | 117 +++ arch/sh/tools/mach-types | 1 + 6 files changed, 1620 insertions(+) create mode 100644 arch/sh/boards/board-sh2007.c create mode 100644 arch/sh/configs/sh2007_defconfig create mode 100644 arch/sh/include/mach-common/mach/sh2007.h (limited to 'arch') diff --git a/arch/sh/boards/Kconfig b/arch/sh/boards/Kconfig index 07b35ca..65abfd4 100644 --- a/arch/sh/boards/Kconfig +++ b/arch/sh/boards/Kconfig @@ -309,6 +309,17 @@ config SH_POLARIS help Select if configuring for an SMSC Polaris development board +config SH_SH2007 + bool "SH-2007 board" + select NO_IOPORT + depends on CPU_SUBTYPE_SH7780 + help + SH-2007 is a single-board computer based around SH7780 chip + intended for embedded applications. + It has an Ethernet interface (SMC9118), direct connected + Compact Flash socket, two serial ports and PC-104 bus. + More information at . + endmenu source "arch/sh/boards/mach-r2d/Kconfig" diff --git a/arch/sh/boards/Makefile b/arch/sh/boards/Makefile index 4f90f9b..2049d95 100644 --- a/arch/sh/boards/Makefile +++ b/arch/sh/boards/Makefile @@ -2,6 +2,7 @@ # Specific board support, not covered by a mach group. # obj-$(CONFIG_SH_MAGIC_PANEL_R2) += board-magicpanelr2.o +obj-$(CONFIG_SH_SH2007) += board-sh2007.o obj-$(CONFIG_SH_SH7785LCR) += board-sh7785lcr.o obj-$(CONFIG_SH_URQUELL) += board-urquell.o obj-$(CONFIG_SH_SHMIN) += board-shmin.o diff --git a/arch/sh/boards/board-sh2007.c b/arch/sh/boards/board-sh2007.c new file mode 100644 index 0000000..b90b78f --- /dev/null +++ b/arch/sh/boards/board-sh2007.c @@ -0,0 +1,133 @@ +/* + * SH-2007 board support. + * + * Copyright (C) 2003, 2004 SUGIOKA Toshinobu + * Copyright (C) 2010 Hitoshi Mitake + */ +#include +#include +#include +#include +#include +#include +#include +#include + +struct smsc911x_platform_config smc911x_info = { + .flags = SMSC911X_USE_32BIT, + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, +}; + +static struct resource smsc9118_0_resources[] = { + [0] = { + .start = SMC0_BASE, + .end = SMC0_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x240), + .end = evt2irq(0x240), + .flags = IORESOURCE_IRQ, + } +}; + +static struct resource smsc9118_1_resources[] = { + [0] = { + .start = SMC1_BASE, + .end = SMC1_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x280), + .end = evt2irq(0x280), + .flags = IORESOURCE_IRQ, + } +}; + +static struct platform_device smsc9118_0_device = { + .name = "smsc911x", + .id = 0, + .num_resources = ARRAY_SIZE(smsc9118_0_resources), + .resource = smsc9118_0_resources, + .dev = { + .platform_data = &smc911x_info, + }, +}; + +static struct platform_device smsc9118_1_device = { + .name = "smsc911x", + .id = 1, + .num_resources = ARRAY_SIZE(smsc9118_1_resources), + .resource = smsc9118_1_resources, + .dev = { + .platform_data = &smc911x_info, + }, +}; + +static struct resource cf_resources[] = { + [0] = { + .start = CF_BASE + CF_OFFSET, + .end = CF_BASE + CF_OFFSET + 0x0f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = CF_BASE + CF_OFFSET + 0x206, + .end = CF_BASE + CF_OFFSET + 0x20f, + .flags = IORESOURCE_MEM, + }, + [2] = { + .start = evt2irq(0x2c0), + .end = evt2irq(0x2c0), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device cf_device = { + .name = "pata_platform", + .id = 0, + .num_resources = ARRAY_SIZE(cf_resources), + .resource = cf_resources, +}; + +static struct platform_device *sh2007_devices[] __initdata = { + &smsc9118_0_device, + &smsc9118_1_device, + &cf_device, +}; + +static int __init sh2007_io_init(void) +{ + platform_add_devices(sh2007_devices, ARRAY_SIZE(sh2007_devices)); + return 0; +} +subsys_initcall(sh2007_io_init); + +static void __init sh2007_init_irq(void) +{ + plat_irq_setup_pins(IRQ_MODE_IRQ); +} + +/* + * Initialize the board + */ +static void __init sh2007_setup(char **cmdline_p) +{ + printk(KERN_INFO "SH-2007 Setup..."); + + /* setup wait control registers for area 5 */ + __raw_writel(CS5BCR_D, CS5BCR); + __raw_writel(CS5WCR_D, CS5WCR); + __raw_writel(CS5PCR_D, CS5PCR); + + printk(KERN_INFO " done.\n"); +} + +/* + * The Machine Vector + */ +struct sh_machine_vector mv_sh2007 __initmv = { + .mv_setup = sh2007_setup, + .mv_name = "sh2007", + .mv_init_irq = sh2007_init_irq, +}; diff --git a/arch/sh/configs/sh2007_defconfig b/arch/sh/configs/sh2007_defconfig new file mode 100644 index 0000000..adf7a6b --- /dev/null +++ b/arch/sh/configs/sh2007_defconfig @@ -0,0 +1,1357 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.35-rc2 +# Fri Jun 18 19:46:14 2010 +# +CONFIG_SUPERH=y +CONFIG_SUPERH32=y +# CONFIG_SUPERH64 is not set +CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_IRQ_PER_CPU=y +CONFIG_SPARSE_IRQ=y +# CONFIG_GENERIC_GPIO is not set +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +# CONFIG_ARCH_SUSPEND_POSSIBLE is not set +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_SYS_SUPPORTS_HUGETLBFS=y +CONFIG_SYS_SUPPORTS_TMU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_NO_VIRT_TO_BUS=y +CONFIG_ARCH_HAS_DEFAULT_IDLE=y +CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y +CONFIG_NO_IOPORT=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_BZIP2=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_BSD_PROCESS_ACCT=y +# CONFIG_BSD_PROCESS_ACCT_V3 is not set +# CONFIG_TASKSTATS is not set +CONFIG_AUDIT=y +CONFIG_AUDITSYSCALL=y +CONFIG_AUDIT_TREE=y + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +CONFIG_IKCONFIG=y +# CONFIG_IKCONFIG_PROC is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +# CONFIG_BLK_DEV_INITRD is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_PERF_COUNTERS is not set +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_HW_BREAKPOINT=y +CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +# CONFIG_MODULES is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +# CONFIG_FREEZER is not set + +# +# System type +# +CONFIG_CPU_SH4=y +CONFIG_CPU_SH4A=y +# CONFIG_CPU_SUBTYPE_SH7619 is not set +# CONFIG_CPU_SUBTYPE_SH7201 is not set +# CONFIG_CPU_SUBTYPE_SH7203 is not set +# CONFIG_CPU_SUBTYPE_SH7206 is not set +# CONFIG_CPU_SUBTYPE_SH7263 is not set +# CONFIG_CPU_SUBTYPE_MXG is not set +# CONFIG_CPU_SUBTYPE_SH7705 is not set +# CONFIG_CPU_SUBTYPE_SH7706 is not set +# CONFIG_CPU_SUBTYPE_SH7707 is not set +# CONFIG_CPU_SUBTYPE_SH7708 is not set +# CONFIG_CPU_SUBTYPE_SH7709 is not set +# CONFIG_CPU_SUBTYPE_SH7710 is not set +# CONFIG_CPU_SUBTYPE_SH7712 is not set +# CONFIG_CPU_SUBTYPE_SH7720 is not set +# CONFIG_CPU_SUBTYPE_SH7721 is not set +# CONFIG_CPU_SUBTYPE_SH7750 is not set +# CONFIG_CPU_SUBTYPE_SH7091 is not set +# CONFIG_CPU_SUBTYPE_SH7750R is not set +# CONFIG_CPU_SUBTYPE_SH7750S is not set +# CONFIG_CPU_SUBTYPE_SH7751 is not set +# CONFIG_CPU_SUBTYPE_SH7751R is not set +# CONFIG_CPU_SUBTYPE_SH7760 is not set +# CONFIG_CPU_SUBTYPE_SH4_202 is not set +# CONFIG_CPU_SUBTYPE_SH7723 is not set +# CONFIG_CPU_SUBTYPE_SH7724 is not set +# CONFIG_CPU_SUBTYPE_SH7757 is not set +# CONFIG_CPU_SUBTYPE_SH7763 is not set +# CONFIG_CPU_SUBTYPE_SH7770 is not set +CONFIG_CPU_SUBTYPE_SH7780=y +# CONFIG_CPU_SUBTYPE_SH7785 is not set +# CONFIG_CPU_SUBTYPE_SH7786 is not set +# CONFIG_CPU_SUBTYPE_SHX3 is not set +# CONFIG_CPU_SUBTYPE_SH7343 is not set +# CONFIG_CPU_SUBTYPE_SH7722 is not set +# CONFIG_CPU_SUBTYPE_SH7366 is not set + +# +# Memory management options +# +CONFIG_QUICKLIST=y +CONFIG_MMU=y +CONFIG_PAGE_OFFSET=0x80000000 +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_MEMORY_START=0x08000000 +CONFIG_MEMORY_SIZE=0x08000000 +CONFIG_29BIT=y +# CONFIG_PMB is not set +# CONFIG_VSYSCALL is not set +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SPARSEMEM_DEFAULT=y +CONFIG_MAX_ACTIVE_REGIONS=1 +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_UNCACHED_MAPPING=y +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_SPARSEMEM_STATIC=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_NR_QUICK=1 +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 + +# +# Cache configuration +# +CONFIG_CACHE_WRITEBACK=y +# CONFIG_CACHE_WRITETHROUGH is not set +# CONFIG_CACHE_OFF is not set + +# +# Processor features +# +CONFIG_CPU_LITTLE_ENDIAN=y +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_SH_FPU=y +# CONFIG_SH_STORE_QUEUES is not set +# CONFIG_SPECULATIVE_EXECUTION is not set +CONFIG_CPU_HAS_INTEVT=y +CONFIG_CPU_HAS_SR_RB=y +CONFIG_CPU_HAS_FPU=y + +# +# Board support +# +# CONFIG_SH_7780_SOLUTION_ENGINE is not set +# CONFIG_SH_SDK7780 is not set +# CONFIG_SH_HIGHLANDER is not set +CONFIG_SH_SH2007=y + +# +# Timer and clock configuration +# +CONFIG_SH_TIMER_TMU=y +CONFIG_SH_PCLK_FREQ=50000000 +CONFIG_SH_CLK_CPG=y +CONFIG_SH_CLK_CPG_LEGACY=y +CONFIG_TICK_ONESHOT=y +# CONFIG_NO_HZ is not set +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y + +# +# CPU Frequency scaling +# +# CONFIG_CPU_FREQ is not set + +# +# DMA support +# +CONFIG_SH_DMA=y +CONFIG_SH_DMA_IRQ_MULTI=y +CONFIG_SH_DMA_API=y +CONFIG_NR_ONCHIP_DMA_CHANNELS=12 +CONFIG_NR_DMA_CHANNELS_BOOL=y +CONFIG_NR_DMA_CHANNELS=12 + +# +# Companion Chips +# + +# +# Additional SuperH Device Drivers +# +# CONFIG_HEARTBEAT is not set +# CONFIG_PUSH_SWITCH is not set + +# +# Kernel features +# +CONFIG_HZ_100=y +# CONFIG_HZ_250 is not set +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=100 +CONFIG_SCHED_HRTICK=y +# CONFIG_KEXEC is not set +# CONFIG_CRASH_DUMP is not set +# CONFIG_SECCOMP is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_GUSA=y +# CONFIG_INTC_USERIMASK is not set + +# +# Boot options +# +CONFIG_ZERO_PAGE_OFFSET=0x00001000 +CONFIG_BOOT_LINK_OFFSET=0x00800000 +CONFIG_ENTRY_OFFSET=0x00001000 +CONFIG_CMDLINE_OVERWRITE=y +# CONFIG_CMDLINE_EXTEND is not set +CONFIG_CMDLINE="console=ttySC1,115200 ip=dhcp root=/dev/nfs rw nfsroot=/nfs/rootfs,rsize=1024,wsize=1024 earlyprintk=sh-sci.1" + +# +# Bus options +# +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_PCCARD=y +CONFIG_PCMCIA=y +CONFIG_PCMCIA_LOAD_CIS=y + +# +# PC-card bridges +# + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set +CONFIG_BINFMT_MISC=y + +# +# Power management options (EXPERIMENTAL) +# +# CONFIG_PM is not set +# CONFIG_CPU_IDLE is not set +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=y +# CONFIG_XFRM_SUB_POLICY is not set +CONFIG_XFRM_MIGRATE=y +# CONFIG_XFRM_STATISTICS is not set +CONFIG_NET_KEY=y +CONFIG_NET_KEY_MIGRATE=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_ASK_IP_FIB_HASH=y +# CONFIG_IP_FIB_TRIE is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +CONFIG_NET_IPIP=y +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +CONFIG_NETWORK_SECMARK=y +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +CONFIG_NET_PKTGEN=y +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_FIB_RULES=y +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +# CONFIG_LIB80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# + +# +# Some wireless drivers require a rate control algorithm +# +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_BLK_DEV_XIP is not set +CONFIG_CDROM_PKTCDVD=y +CONFIG_CDROM_PKTCDVD_BUFFERS=8 +# CONFIG_CDROM_PKTCDVD_WCACHE is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MISC_DEVICES is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +CONFIG_RAID_ATTRS=y +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +CONFIG_SCSI_TGT=y +CONFIG_SCSI_NETLINK=y +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=y +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set +CONFIG_SCSI_MULTI_LUN=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y + +# +# SCSI Transports +# +CONFIG_SCSI_SPI_ATTRS=y +CONFIG_SCSI_FC_ATTRS=y +# CONFIG_SCSI_FC_TGT_ATTRS is not set +CONFIG_SCSI_ISCSI_ATTRS=y +# CONFIG_SCSI_SAS_LIBSAS is not set +CONFIG_SCSI_SRP_ATTRS=y +# CONFIG_SCSI_SRP_TGT_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +CONFIG_DUMMY=y +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +CONFIG_EQUALIZER=y +CONFIG_TUN=y +CONFIG_VETH=y +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_STNIC is not set +# CONFIG_SMC91X is not set +# CONFIG_ETHOC is not set +# CONFIG_SMC911X is not set +CONFIG_SMSC911X=y +# CONFIG_DNET is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851_MLL is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_WLAN is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_IPHETH is not set +# CONFIG_NET_PCMCIA is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_FF_MEMLESS=y +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_DEVKMEM is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_SH_SCI=y +CONFIG_SERIAL_SH_SCI_NR_UARTS=2 +CONFIG_SERIAL_SH_SCI_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set + +# +# PCMCIA character devices +# +# CONFIG_SYNCLINK_CS is not set +# CONFIG_CARDMAN_4000 is not set +# CONFIG_CARDMAN_4040 is not set +# CONFIG_IPWIRELESS is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_RAMOOPS is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +CONFIG_SH_WDT=y +# CONFIG_SH_WDT_MMAP is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +CONFIG_SSB=y +CONFIG_SSB_PCMCIAHOST_POSSIBLE=y +# CONFIG_SSB_PCMCIAHOST is not set +# CONFIG_SSB_SILENT is not set +# CONFIG_SSB_DEBUG is not set +CONFIG_MFD_SUPPORT=y +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SH_MOBILE_SDHI is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +# CONFIG_FB_CFB_FILLRECT is not set +# CONFIG_FB_CFB_COPYAREA is not set +# CONFIG_FB_CFB_IMAGEBLIT is not set +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_SH_MOBILE_LCDC is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_GENERIC=y + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y +CONFIG_LOGO_SUPERH_MONO=y +CONFIG_LOGO_SUPERH_VGA16=y +CONFIG_LOGO_SUPERH_CLUT224=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +# CONFIG_USB_ARCH_HAS_EHCI is not set +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_DEVICE_CLASS is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +# CONFIG_USB_STORAGE is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_GADGET is not set + +# +# OTG and related infrastructure +# +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +CONFIG_LEDS_TRIGGERS=y + +# +# LED Triggers +# +# CONFIG_LEDS_TRIGGER_TIMER is not set +# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set + +# +# iptables trigger is under Netfilter config (LED target) +# +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +# CONFIG_RTC_DRV_TEST is not set + +# +# SPI RTC drivers +# + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_SH is not set +# CONFIG_RTC_DRV_GENERIC is not set +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +CONFIG_TIMB_DMA=y +CONFIG_DMA_ENGINE=y + +# +# DMA Clients +# +# CONFIG_NET_DMA is not set +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_DMATEST is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# File systems +# +# CONFIG_EXT2_FS is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set +CONFIG_GENERIC_ACL=y + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=y +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=932 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_HUGETLBFS is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=y +# CONFIG_MISC_FILESYSTEMS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +# CONFIG_NFS_V4_1 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +CONFIG_RPCSEC_GSS_KRB5=y +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=y +CONFIG_NLS_CODEPAGE_775=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_CODEPAGE_852=y +CONFIG_NLS_CODEPAGE_855=y +CONFIG_NLS_CODEPAGE_857=y +CONFIG_NLS_CODEPAGE_860=y +CONFIG_NLS_CODEPAGE_861=y +CONFIG_NLS_CODEPAGE_862=y +CONFIG_NLS_CODEPAGE_863=y +CONFIG_NLS_CODEPAGE_864=y +CONFIG_NLS_CODEPAGE_865=y +CONFIG_NLS_CODEPAGE_866=y +CONFIG_NLS_CODEPAGE_869=y +CONFIG_NLS_CODEPAGE_936=y +CONFIG_NLS_CODEPAGE_950=y +CONFIG_NLS_CODEPAGE_932=y +CONFIG_NLS_CODEPAGE_949=y +CONFIG_NLS_CODEPAGE_874=y +CONFIG_NLS_ISO8859_8=y +CONFIG_NLS_CODEPAGE_1250=y +CONFIG_NLS_CODEPAGE_1251=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +CONFIG_NLS_ISO8859_3=y +CONFIG_NLS_ISO8859_4=y +CONFIG_NLS_ISO8859_5=y +CONFIG_NLS_ISO8859_6=y +CONFIG_NLS_ISO8859_7=y +CONFIG_NLS_ISO8859_9=y +CONFIG_NLS_ISO8859_13=y +CONFIG_NLS_ISO8859_14=y +CONFIG_NLS_ISO8859_15=y +CONFIG_NLS_KOI8_R=y +CONFIG_NLS_KOI8_U=y +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +# CONFIG_PRINTK_TIME is not set +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_DETECT_SOFTLOCKUP is not set +# CONFIG_DETECT_HUNG_TASK is not set +# CONFIG_SCHED_DEBUG is not set +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +CONFIG_FRAME_POINTER=y +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_LKDTM is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_FTRACE_SYSCALLS is not set +# CONFIG_BOOT_TRACER is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_KSYM_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_SH_STANDARD_BIOS=y +# CONFIG_STACK_DEBUG is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_4KSTACKS is not set +CONFIG_DUMP_CODE=y +# CONFIG_DWARF_UNWINDER is not set +# CONFIG_SH_NO_BSS_INIT is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=y + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_LRW=y +CONFIG_CRYPTO_PCBC=y +CONFIG_CRYPTO_XTS=y + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_XCBC=y +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_GHASH is not set +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=y +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_TGR192=y +CONFIG_CRYPTO_WP512=y + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_ANUBIS=y +CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_CAMELLIA=y +CONFIG_CRYPTO_CAST5=y +CONFIG_CRYPTO_CAST6=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_FCRYPT=y +CONFIG_CRYPTO_KHAZAD=y +# CONFIG_CRYPTO_SALSA20 is not set +CONFIG_CRYPTO_SEED=y +CONFIG_CRYPTO_SERPENT=y +CONFIG_CRYPTO_TEA=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_TWOFISH_COMMON=y + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_ZLIB is not set +CONFIG_CRYPTO_LZO=y + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set +# CONFIG_VIRTUALIZATION is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=y +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=y +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=y +CONFIG_AUDIT_GENERIC=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_DMA=y +CONFIG_HAVE_LMB=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y diff --git a/arch/sh/include/mach-common/mach/sh2007.h b/arch/sh/include/mach-common/mach/sh2007.h new file mode 100644 index 0000000..48180b9 --- /dev/null +++ b/arch/sh/include/mach-common/mach/sh2007.h @@ -0,0 +1,117 @@ +#ifndef __MACH_SH2007_H +#define __MACH_SH2007_H + +#define CS5BCR 0xff802050 +#define CS5WCR 0xff802058 +#define CS5PCR 0xff802070 + +#define BUS_SZ8 1 +#define BUS_SZ16 2 +#define BUS_SZ32 3 + +#define PCMCIA_IODYN 1 +#define PCMCIA_ATA 0 +#define PCMCIA_IO8 2 +#define PCMCIA_IO16 3 +#define PCMCIA_COMM8 4 +#define PCMCIA_COMM16 5 +#define PCMCIA_ATTR8 6 +#define PCMCIA_ATTR16 7 + +#define TYPE_SRAM 0 +#define TYPE_PCMCIA 4 + +/* write-read/write-write delay (0-7:0,1,2,3,4,5,6,7) */ +#define IWW5 0 +#define IWW6 3 +/* different area, read-write delay (0-7:0,1,2,3,4,5,6,7) */ +#define IWRWD5 2 +#define IWRWD6 2 +/* same area, read-write delay (0-7:0,1,2,3,4,5,6,7) */ +#define IWRWS5 2 +#define IWRWS6 2 +/* different area, read-read delay (0-7:0,1,2,3,4,5,6,7) */ +#define IWRRD5 2 +#define IWRRD6 2 +/* same area, read-read delay (0-7:0,1,2,3,4,5,6,7) */ +#define IWRRS5 0 +#define IWRRS6 2 +/* burst count (0-3:4,8,16,32) */ +#define BST5 0 +#define BST6 0 +/* bus size */ +#define SZ5 BUS_SZ16 +#define SZ6 BUS_SZ16 +/* RD hold for SRAM (0-1:0,1) */ +#define RDSPL5 0 +#define RDSPL6 0 +/* Burst pitch (0-7:0,1,2,3,4,5,6,7) */ +#define BW5 0 +#define BW6 0 +/* Multiplex (0-1:0,1) */ +#define MPX5 0 +#define MPX6 0 +/* device type */ +#define TYPE5 TYPE_PCMCIA +#define TYPE6 TYPE_PCMCIA +/* address setup before assert CSn for SRAM (0-7:0,1,2,3,4,5,6,7) */ +#define ADS5 0 +#define ADS6 0 +/* address hold after negate CSn for SRAM (0-7:0,1,2,3,4,5,6,7) */ +#define ADH5 0 +#define ADH6 0 +/* CSn assert to RD assert delay for SRAM (0-7:0,1,2,3,4,5,6,7) */ +#define RDS5 0 +#define RDS6 0 +/* RD negate to CSn negate delay for SRAM (0-7:0,1,2,3,4,5,6,7) */ +#define RDH5 0 +#define RDH6 0 +/* CSn assert to WE assert delay for SRAM (0-7:0,1,2,3,4,5,6,7) */ +#define WTS5 0 +#define WTS6 0 +/* WE negate to CSn negate delay for SRAM (0-7:0,1,2,3,4,5,6,7) */ +#define WTH5 0 +#define WTH6 0 +/* BS hold (0-1:1,2) */ +#define BSH5 0 +#define BSH6 0 +/* wait cycle (0-15:0,1,2,3,4,5,6,7,8,9,11,13,15,17,21,25) */ +#define IW5 6 /* 60ns PIO mode 4 */ +#define IW6 15 /* 250ns */ + +#define SAA5 PCMCIA_IODYN /* IDE area b4000000-b5ffffff */ +#define SAB5 PCMCIA_IODYN /* CF area b6000000-b7ffffff */ +#define PCWA5 0 /* additional wait A (0-3:0,15,30,50) */ +#define PCWB5 0 /* additional wait B (0-3:0,15,30,50) */ +/* wait B (0-15:0,1,2,3,4,5,6,7,8,9,11,13,15,17,21,25) */ +#define PCIW5 12 +/* Address->OE/WE assert delay A (0-7:0,1,2,3,6,9,12,15) */ +#define TEDA5 2 +/* Address->OE/WE assert delay B (0-7:0,1,2,3,6,9,12,15) */ +#define TEDB5 4 +/* OE/WE negate->Address delay A (0-7:0,1,2,3,6,9,12,15) */ +#define TEHA5 2 +/* OE/WE negate->Address delay B (0-7:0,1,2,3,6,9,12,15) */ +#define TEHB5 3 + +#define CS5BCR_D ((IWW5<<28)|(IWRWD5<<24)|(IWRWS5<<20)| \ + (IWRRD5<<16)|(IWRRS5<<12)|(BST5<<10)| \ + (SZ5<<8)|(RDSPL5<<7)|(BW5<<4)|(MPX5<<3)|TYPE5) +#define CS5WCR_D ((ADS5<<28)|(ADH5<<24)|(RDS5<<20)| \ + (RDH5<<16)|(WTS5<<12)|(WTH5<<8)|(BSH5<<4)|IW5) +#define CS5PCR_D ((SAA5<<28)|(SAB5<<24)|(PCWA5<<22)| \ + (PCWB5<<20)|(PCIW5<<16)|(TEDA5<<12)| \ + (TEDB5<<8)|(TEHA5<<4)|TEHB5) + +#define SMC0_BASE 0xb0800000 /* eth0 */ +#define SMC1_BASE 0xb0900000 /* eth1 */ +#define CF_BASE 0xb6100000 /* Compact Flash (I/O area) */ +#define IDE_BASE 0xb4000000 /* IDE */ +#define PC104_IO_BASE 0xb8000000 +#define PC104_MEM_BASE 0xba000000 +#define SMC_IO_SIZE 0x100 + +#define CF_OFFSET 0x1f0 +#define IDE_OFFSET 0x170 + +#endif /* __MACH_SH2007_H */ diff --git a/arch/sh/tools/mach-types b/arch/sh/tools/mach-types index b25aa55..120a211 100644 --- a/arch/sh/tools/mach-types +++ b/arch/sh/tools/mach-types @@ -52,6 +52,7 @@ MIGOR SH_MIGOR RSK7201 SH_RSK7201 RSK7203 SH_RSK7203 AP325RXA SH_AP325RXA +SH2007 SH_SH2007 SH7763RDP SH_SH7763RDP SH7785LCR SH_SH7785LCR SH7785LCR_PT SH_SH7785LCR_PT -- cgit v1.1 From 7210ed74a1ab9ce148a66798fbeec88d27f42070 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Mon, 21 Jun 2010 16:23:03 +0900 Subject: sh: fix up an off-by-1 in the number of early ioremap fixmaps. There was an off-by-1 in the begin/end of the ioremap fixmaps, leaving us with a spurious entry. In practice this wasn't a problem since we aligned on a PMD boundary anyways, but this makes it consistent with the intention and the other fixmaps. Signed-off-by: Paul Mundt --- arch/sh/include/asm/fixmap.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/sh/include/asm/fixmap.h b/arch/sh/include/asm/fixmap.h index 6e7cea4..bd7e79a 100644 --- a/arch/sh/include/asm/fixmap.h +++ b/arch/sh/include/asm/fixmap.h @@ -58,7 +58,7 @@ enum fixed_addresses { #ifdef CONFIG_HIGHMEM FIX_KMAP_BEGIN, /* reserved pte's for temporary kernel mappings */ - FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1, + FIX_KMAP_END = FIX_KMAP_BEGIN + (KM_TYPE_NR * NR_CPUS) - 1, #endif #ifdef CONFIG_IOREMAP_FIXED @@ -69,7 +69,7 @@ enum fixed_addresses { */ #define FIX_N_IOREMAPS 32 FIX_IOREMAP_BEGIN, - FIX_IOREMAP_END = FIX_IOREMAP_BEGIN + FIX_N_IOREMAPS, + FIX_IOREMAP_END = FIX_IOREMAP_BEGIN + FIX_N_IOREMAPS - 1, #endif __end_of_fixed_addresses -- cgit v1.1 From 598ee698d9db7beb06e12f4ea9d9a5fbc03a3a77 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Mon, 21 Jun 2010 16:26:27 +0900 Subject: sh: Fix up PUD trampling in ranged page table init for X2TLB. page_table_range_init() presently allocates a PUD page for the 3-level page table case on X2 TLB configurations on each successive call. This results in the previous PUD page being trampled when PMDs with an overlapping PUD are initialized. This case was triggered by putting persistent kmaps immediately below the fixmap range for highmem. Signed-off-by: Paul Mundt --- arch/sh/mm/init.c | 52 ++++++++++++++++++++++++++++++++++++++-------------- 1 file changed, 38 insertions(+), 14 deletions(-) (limited to 'arch') diff --git a/arch/sh/mm/init.c b/arch/sh/mm/init.c index 46f84de..82d4609 100644 --- a/arch/sh/mm/init.c +++ b/arch/sh/mm/init.c @@ -47,7 +47,6 @@ static pte_t *__get_pte_phys(unsigned long addr) pgd_t *pgd; pud_t *pud; pmd_t *pmd; - pte_t *pte; pgd = pgd_offset_k(addr); if (pgd_none(*pgd)) { @@ -67,8 +66,7 @@ static pte_t *__get_pte_phys(unsigned long addr) return NULL; } - pte = pte_offset_kernel(pmd, addr); - return pte; + return pte_offset_kernel(pmd, addr); } static void set_pte_phys(unsigned long addr, unsigned long phys, pgprot_t prot) @@ -125,13 +123,45 @@ void __clear_fixmap(enum fixed_addresses idx, pgprot_t prot) clear_pte_phys(address, prot); } +static pmd_t * __init one_md_table_init(pud_t *pud) +{ + if (pud_none(*pud)) { + pmd_t *pmd; + + pmd = alloc_bootmem_pages(PAGE_SIZE); + pud_populate(&init_mm, pud, pmd); + BUG_ON(pmd != pmd_offset(pud, 0)); + } + + return pmd_offset(pud, 0); +} + +static pte_t * __init one_page_table_init(pmd_t *pmd) +{ + if (pmd_none(*pmd)) { + pte_t *pte; + + pte = alloc_bootmem_pages(PAGE_SIZE); + pmd_populate_kernel(&init_mm, pmd, pte); + BUG_ON(pte != pte_offset_kernel(pmd, 0)); + } + + return pte_offset_kernel(pmd, 0); +} + +static pte_t * __init page_table_kmap_check(pte_t *pte, pmd_t *pmd, + unsigned long vaddr, pte_t *lastpte) +{ + return pte; +} + void __init page_table_range_init(unsigned long start, unsigned long end, pgd_t *pgd_base) { pgd_t *pgd; pud_t *pud; pmd_t *pmd; - pte_t *pte; + pte_t *pte = NULL; int i, j, k; unsigned long vaddr; @@ -144,19 +174,13 @@ void __init page_table_range_init(unsigned long start, unsigned long end, for ( ; (i < PTRS_PER_PGD) && (vaddr != end); pgd++, i++) { pud = (pud_t *)pgd; for ( ; (j < PTRS_PER_PUD) && (vaddr != end); pud++, j++) { -#ifdef __PAGETABLE_PMD_FOLDED - pmd = (pmd_t *)pud; -#else - pmd = (pmd_t *)alloc_bootmem_low_pages(PAGE_SIZE); - pud_populate(&init_mm, pud, pmd); + pmd = one_md_table_init(pud); +#ifndef __PAGETABLE_PMD_FOLDED pmd += k; #endif for (; (k < PTRS_PER_PMD) && (vaddr != end); pmd++, k++) { - if (pmd_none(*pmd)) { - pte = (pte_t *) alloc_bootmem_low_pages(PAGE_SIZE); - pmd_populate_kernel(&init_mm, pmd, pte); - BUG_ON(pte != pte_offset_kernel(pmd, 0)); - } + pte = page_table_kmap_check(one_page_table_init(pmd), + pmd, vaddr, pte); vaddr += PMD_SIZE; } k = 0; -- cgit v1.1 From 3b554c33dcde9d67efcb8d0a5acca201afd44730 Mon Sep 17 00:00:00 2001 From: Matt Fleming Date: Sat, 19 Jun 2010 00:01:03 +0100 Subject: sh: Fix typos in PCI initialization message This typo seems to have been copy and pasted in the PCI initialization code. Replace 'intialization' with 'initialization'. Signed-off-by: Matt Fleming --- arch/sh/drivers/pci/pci-sh7751.c | 2 +- arch/sh/drivers/pci/pci-sh7780.c | 2 +- arch/sh/drivers/pci/pcie-sh7786.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/sh/drivers/pci/pci-sh7751.c b/arch/sh/drivers/pci/pci-sh7751.c index f98141b..86adb1e 100644 --- a/arch/sh/drivers/pci/pci-sh7751.c +++ b/arch/sh/drivers/pci/pci-sh7751.c @@ -81,7 +81,7 @@ static int __init sh7751_pci_init(void) unsigned int id; u32 word, reg; - printk(KERN_NOTICE "PCI: Starting intialization.\n"); + printk(KERN_NOTICE "PCI: Starting initialization.\n"); chan->reg_base = 0xfe200000; diff --git a/arch/sh/drivers/pci/pci-sh7780.c b/arch/sh/drivers/pci/pci-sh7780.c index ffdcbf1..edb7cca 100644 --- a/arch/sh/drivers/pci/pci-sh7780.c +++ b/arch/sh/drivers/pci/pci-sh7780.c @@ -246,7 +246,7 @@ static int __init sh7780_pci_init(void) const char *type; int ret, i; - printk(KERN_NOTICE "PCI: Starting intialization.\n"); + printk(KERN_NOTICE "PCI: Starting initialization.\n"); chan->reg_base = 0xfe040000; diff --git a/arch/sh/drivers/pci/pcie-sh7786.c b/arch/sh/drivers/pci/pcie-sh7786.c index 68cb9b0..78f3787 100644 --- a/arch/sh/drivers/pci/pcie-sh7786.c +++ b/arch/sh/drivers/pci/pcie-sh7786.c @@ -392,7 +392,7 @@ static int __init sh7786_pcie_init(void) { int ret = 0, i; - printk(KERN_NOTICE "PCI: Starting intialization.\n"); + printk(KERN_NOTICE "PCI: Starting initialization.\n"); sh7786_pcie_hwops = &sh7786_65nm_pcie_hwops; -- cgit v1.1 From 7974891db234467eaf1fec613ec0129cb4ac2332 Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Mon, 28 Jun 2010 14:15:54 +0200 Subject: x86: Always use irq stacks IRQ stacks provide much better safety against unexpected stack use from interrupts, at the minimal downside of slightly higher memory usage. Enable irq stacks also for the default 8k stack on 32-bit kernels to minimize the problem of stack overflows through interrupt activity. This is what the 64-bit kernel and various other architectures already do. Signed-off-by: Christoph Hellwig LKML-Reference: <20100628121554.GA6605@lst.de> Signed-off-by: Thomas Gleixner --- arch/x86/Kconfig.debug | 3 +-- arch/x86/include/asm/irq.h | 12 +++++------- arch/x86/kernel/irq_32.c | 6 ------ 3 files changed, 6 insertions(+), 15 deletions(-) (limited to 'arch') diff --git a/arch/x86/Kconfig.debug b/arch/x86/Kconfig.debug index 7508508..badda8e 100644 --- a/arch/x86/Kconfig.debug +++ b/arch/x86/Kconfig.debug @@ -128,8 +128,7 @@ config 4KSTACKS If you say Y here the kernel will use a 4Kb stacksize for the kernel stack attached to each process/thread. This facilitates running more threads on a system and also reduces the pressure - on the VM subsystem for higher order allocations. This option - will also use IRQ stacks to compensate for the reduced stackspace. + on the VM subsystem for higher order allocations. config DOUBLEFAULT default y diff --git a/arch/x86/include/asm/irq.h b/arch/x86/include/asm/irq.h index 5458380..0bf5b00 100644 --- a/arch/x86/include/asm/irq.h +++ b/arch/x86/include/asm/irq.h @@ -19,18 +19,16 @@ static inline int irq_canonicalize(int irq) # define ARCH_HAS_NMI_WATCHDOG #endif -#ifdef CONFIG_4KSTACKS - extern void irq_ctx_init(int cpu); - extern void irq_ctx_exit(int cpu); -# define __ARCH_HAS_DO_SOFTIRQ +#ifdef CONFIG_X86_32 +extern void irq_ctx_init(int cpu); +extern void irq_ctx_exit(int cpu); #else # define irq_ctx_init(cpu) do { } while (0) # define irq_ctx_exit(cpu) do { } while (0) -# ifdef CONFIG_X86_64 -# define __ARCH_HAS_DO_SOFTIRQ -# endif #endif +#define __ARCH_HAS_DO_SOFTIRQ + #ifdef CONFIG_HOTPLUG_CPU #include extern void fixup_irqs(void); diff --git a/arch/x86/kernel/irq_32.c b/arch/x86/kernel/irq_32.c index 10709f2..67f5f9f 100644 --- a/arch/x86/kernel/irq_32.c +++ b/arch/x86/kernel/irq_32.c @@ -49,7 +49,6 @@ static inline int check_stack_overflow(void) { return 0; } static inline void print_stack_overflow(void) { } #endif -#ifdef CONFIG_4KSTACKS /* * per-CPU IRQ handling contexts (thread information and stack) */ @@ -187,11 +186,6 @@ asmlinkage void do_softirq(void) local_irq_restore(flags); } -#else -static inline int -execute_on_irq_stack(int overflow, struct irq_desc *desc, int irq) { return 0; } -#endif - bool handle_irq(unsigned irq, struct pt_regs *regs) { struct irq_desc *desc; -- cgit v1.1 From dcfa726280116dd31adad37da940f542663567d0 Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Mon, 28 Jun 2010 14:16:14 +0200 Subject: x86: Remove CONFIG_4KSTACKS These days 4 kilobytes of stack just aren't enough for reliably operation, and people using lots of threads have long switched to 64-bit kernels, so remove the CONFIG_4KSTACKS option. Signed-off-by: Christoph Hellwig LKML-Reference: <20100628121614.GB6605@lst.de> Signed-off-by: Thomas Gleixner --- arch/x86/Kconfig.debug | 9 --------- arch/x86/include/asm/module.h | 7 +------ arch/x86/include/asm/page_32_types.h | 4 ---- 3 files changed, 1 insertion(+), 19 deletions(-) (limited to 'arch') diff --git a/arch/x86/Kconfig.debug b/arch/x86/Kconfig.debug index badda8e..7f15308 100644 --- a/arch/x86/Kconfig.debug +++ b/arch/x86/Kconfig.debug @@ -121,15 +121,6 @@ config DEBUG_NX_TEST and the software setup of this feature. If in doubt, say "N" -config 4KSTACKS - bool "Use 4Kb for kernel stacks instead of 8Kb" - depends on X86_32 - ---help--- - If you say Y here the kernel will use a 4Kb stacksize for the - kernel stack attached to each process/thread. This facilitates - running more threads on a system and also reduces the pressure - on the VM subsystem for higher order allocations. - config DOUBLEFAULT default y bool "Enable doublefault exception handler" if EMBEDDED diff --git a/arch/x86/include/asm/module.h b/arch/x86/include/asm/module.h index 3e2ce58..67763c5 100644 --- a/arch/x86/include/asm/module.h +++ b/arch/x86/include/asm/module.h @@ -60,12 +60,7 @@ #endif #ifdef CONFIG_X86_32 -# ifdef CONFIG_4KSTACKS -# define MODULE_STACKSIZE "4KSTACKS " -# else -# define MODULE_STACKSIZE "" -# endif -# define MODULE_ARCH_VERMAGIC MODULE_PROC_FAMILY MODULE_STACKSIZE +# define MODULE_ARCH_VERMAGIC MODULE_PROC_FAMILY #endif #endif /* _ASM_X86_MODULE_H */ diff --git a/arch/x86/include/asm/page_32_types.h b/arch/x86/include/asm/page_32_types.h index 6f1b733..ade619f 100644 --- a/arch/x86/include/asm/page_32_types.h +++ b/arch/x86/include/asm/page_32_types.h @@ -15,11 +15,7 @@ */ #define __PAGE_OFFSET _AC(CONFIG_PAGE_OFFSET, UL) -#ifdef CONFIG_4KSTACKS -#define THREAD_ORDER 0 -#else #define THREAD_ORDER 1 -#endif #define THREAD_SIZE (PAGE_SIZE << THREAD_ORDER) #define STACKFAULT_STACK 0 -- cgit v1.1 From 59615ecdb516cf218c3699b02d87d9827dc3e0c7 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 2 Jul 2010 15:44:09 +0900 Subject: sh: Provide a global TLB flush for U/I-TLB clear. This provides a sledgehammer approach for clearing the TLBs, only to be used in cases where we know we will never want to use the mappings again and have no interest in preserving state. This also destroys wired entries. The primary use for this is when we are either entering or exiting the kernel completely, in the latter case as a precursor for CPU reset by MMU. Signed-off-by: Paul Mundt --- arch/sh/include/asm/tlbflush.h | 2 ++ arch/sh/kernel/reboot.c | 4 ++++ arch/sh/mm/tlbflush_32.c | 16 ++++++++++++++++ arch/sh/mm/tlbflush_64.c | 5 +++++ 4 files changed, 27 insertions(+) (limited to 'arch') diff --git a/arch/sh/include/asm/tlbflush.h b/arch/sh/include/asm/tlbflush.h index e0ac972..0df66f0 100644 --- a/arch/sh/include/asm/tlbflush.h +++ b/arch/sh/include/asm/tlbflush.h @@ -21,6 +21,8 @@ extern void local_flush_tlb_kernel_range(unsigned long start, unsigned long end); extern void local_flush_tlb_one(unsigned long asid, unsigned long page); +extern void __flush_tlb_global(void); + #ifdef CONFIG_SMP extern void flush_tlb_all(void); diff --git a/arch/sh/kernel/reboot.c b/arch/sh/kernel/reboot.c index b1fca66..ca6a5ca 100644 --- a/arch/sh/kernel/reboot.c +++ b/arch/sh/kernel/reboot.c @@ -9,6 +9,7 @@ #include #include #include +#include void (*pm_power_off)(void); EXPORT_SYMBOL(pm_power_off); @@ -25,6 +26,9 @@ static void native_machine_restart(char * __unused) { local_irq_disable(); + /* Destroy all of the TLBs in preparation for reset by MMU */ + __flush_tlb_global(); + /* Address error with SR.BL=1 first. */ trigger_address_error(); diff --git a/arch/sh/mm/tlbflush_32.c b/arch/sh/mm/tlbflush_32.c index 3fbe03c..a6a20d6 100644 --- a/arch/sh/mm/tlbflush_32.c +++ b/arch/sh/mm/tlbflush_32.c @@ -119,3 +119,19 @@ void local_flush_tlb_mm(struct mm_struct *mm) local_irq_restore(flags); } } + +void __flush_tlb_global(void) +{ + unsigned long flags; + + local_irq_save(flags); + + /* + * This is the most destructive of the TLB flushing options, + * and will tear down all of the UTLB/ITLB mappings, including + * wired entries. + */ + __raw_writel(__raw_readl(MMUCR) | MMUCR_TI, MMUCR); + + local_irq_restore(flags); +} diff --git a/arch/sh/mm/tlbflush_64.c b/arch/sh/mm/tlbflush_64.c index 03db41c..7f5810f 100644 --- a/arch/sh/mm/tlbflush_64.c +++ b/arch/sh/mm/tlbflush_64.c @@ -455,6 +455,11 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) flush_tlb_all(); } +void __flush_tlb_global(void) +{ + flush_tlb_all(); +} + void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte) { } -- cgit v1.1 From 358aa7031d90fc3c7c1dbf1fd248a7e3af3c4b11 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Tue, 8 Jun 2010 02:00:13 +0000 Subject: sh: Drop dependence for 29bit mode of trigger_address_error() When CONFIG_PMB enable, ITLB is not cleared by reset of watchdog timer. This should use trigger_address_error(). Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Paul Mundt --- arch/sh/include/asm/system_32.h | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/sh/include/asm/system_32.h b/arch/sh/include/asm/system_32.h index 51296b3..9bd2684 100644 --- a/arch/sh/include/asm/system_32.h +++ b/arch/sh/include/asm/system_32.h @@ -216,13 +216,12 @@ int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs, static inline void trigger_address_error(void) { - if (__in_29bit_mode()) - __asm__ __volatile__ ( - "ldc %0, sr\n\t" - "mov.l @%1, %0" - : - : "r" (0x10000000), "r" (0x80000001) - ); + __asm__ __volatile__ ( + "ldc %0, sr\n\t" + "mov.l @%1, %0" + : + : "r" (0x10000000), "r" (0x80000001) + ); } asmlinkage void do_address_error(struct pt_regs *regs, -- cgit v1.1 From b32f1fef4fd7bdfb4f1c466393e7f3e3f359c5e0 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Tue, 6 Jul 2010 04:32:40 +0000 Subject: sh: modify NR_IRQS from 256 to 512 Newer parts need NR_IRQS > 256, so simply bump this up to 512 across the board. At this point sparseirq is used unconditionally across all CPUs, so this introduces minimal overhead. Signed-off-by: Yoshihiro Shimoda Signed-off-by: Paul Mundt --- arch/sh/include/asm/irq.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/sh/include/asm/irq.h b/arch/sh/include/asm/irq.h index 02c2f01..45d08b6 100644 --- a/arch/sh/include/asm/irq.h +++ b/arch/sh/include/asm/irq.h @@ -9,7 +9,7 @@ * advised to cap this at the hard limit that they're interested in * through the machvec. */ -#define NR_IRQS 256 +#define NR_IRQS 512 #define NR_IRQS_LEGACY 8 /* Legacy external IRQ0-7 */ /* -- cgit v1.1 From e81e5ce23f8950bd9f5b9f1846be49ac078f2d11 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Tue, 6 Jul 2010 04:31:29 +0000 Subject: sh: change PVR of SH7757 for 2nd cut All 1st cut silicon in the wild has been replaced by the 2nd cut, so it's safe to replace all of the 1st cut references and support. Signed-off-by: Yoshihiro Shimoda Signed-off-by: Paul Mundt --- arch/sh/kernel/cpu/sh4/probe.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c index d180f16..b93458f 100644 --- a/arch/sh/kernel/cpu/sh4/probe.c +++ b/arch/sh/kernel/cpu/sh4/probe.c @@ -150,7 +150,7 @@ void __cpuinit cpu_probe(void) boot_cpu_data.type = CPU_SH7724; boot_cpu_data.flags |= CPU_HAS_L2_CACHE; break; - case 0x50: + case 0x10: boot_cpu_data.type = CPU_SH7757; break; } -- cgit v1.1 From a7f5551cae9a9f667ed80174ac1a20f780310977 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Tue, 6 Jul 2010 04:31:40 +0000 Subject: sh: fix the id of scif in setup-sh7757 Because the value of CONFIG_SERIAL_SH_SCI_NR_UARTS is 3. Signed-off-by: Yoshihiro Shimoda Signed-off-by: Paul Mundt --- arch/sh/kernel/cpu/sh4a/setup-sh7757.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c index 444aca9..93b7aa4 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c @@ -26,7 +26,7 @@ static struct plat_sci_port scif2_platform_data = { static struct platform_device scif2_device = { .name = "sh-sci", - .id = 2, + .id = 0, .dev = { .platform_data = &scif2_platform_data, }, @@ -41,7 +41,7 @@ static struct plat_sci_port scif3_platform_data = { static struct platform_device scif3_device = { .name = "sh-sci", - .id = 3, + .id = 1, .dev = { .platform_data = &scif3_platform_data, }, @@ -56,7 +56,7 @@ static struct plat_sci_port scif4_platform_data = { static struct platform_device scif4_device = { .name = "sh-sci", - .id = 4, + .id = 2, .dev = { .platform_data = &scif4_platform_data, }, -- cgit v1.1 From c3721d5bbecad670d35589756ad2a15eaf592bd4 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Tue, 6 Jul 2010 04:31:47 +0000 Subject: sh: add some INTC_VECT for setup-sh7757 Signed-off-by: Yoshihiro Shimoda Signed-off-by: Paul Mundt --- arch/sh/kernel/cpu/sh4a/setup-sh7757.c | 216 ++++++++++++++++++++++----------- 1 file changed, 147 insertions(+), 69 deletions(-) (limited to 'arch') diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c index 93b7aa4..749c638 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c @@ -163,39 +163,23 @@ enum { IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, - SDHI, - DVC, - IRQ8, IRQ9, IRQ10, - WDT0, - TMU0, TMU1, TMU2, TMU2_TICPI, + SDHI, DVC, + IRQ8, IRQ9, IRQ11, IRQ10, IRQ12, IRQ13, IRQ14, IRQ15, + TMU0, TMU1, TMU2, TMU2_TICPI, TMU3, TMU4, TMU5, HUDI, - ARC4, - DMAC0, - IRQ11, - SCIF2, - DMAC1_6, - USB0, - IRQ12, + DMAC0_5, DMAC6_7, DMAC8_11, + SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, + USB0, USB1, JMC, - SPI1, - IRQ13, IRQ14, - USB1, + SPI0, SPI1, TMR01, TMR23, TMR45, - WDT1, FRT, - LPC, - SCIF0, SCIF1, SCIF3, - PECI0I, PECI1I, PECI2I, - IRQ15, + LPC, LPC5, LPC6, LPC7, LPC8, + PECI0, PECI1, PECI2, PECI3, PECI4, PECI5, ETHERC, - SPI0, - ADC1, - DMAC1_8, + ADC0, ADC1, SIM, - TMU3, TMU4, TMU5, - ADC0, - SCIF4, IIC0_0, IIC0_1, IIC0_2, IIC0_3, IIC1_0, IIC1_1, IIC1_2, IIC1_3, IIC2_0, IIC2_1, IIC2_2, IIC2_3, @@ -206,9 +190,23 @@ enum { IIC7_0, IIC7_1, IIC7_2, IIC7_3, IIC8_0, IIC8_1, IIC8_2, IIC8_3, IIC9_0, IIC9_1, IIC9_2, IIC9_3, - PCIINTA, - PCIE, + ONFICTL, + MMC1, MMC2, + ECCU, + PCIC, + G200, + RSPI, SGPIO, + DMINT12, DMINT13, DMINT14, DMINT15, DMINT16, DMINT17, DMINT18, DMINT19, + DMINT20, DMINT21, DMINT22, DMINT23, + DDRECC, + TSIP, + PCIE_BRIDGE, + WDT0B, WDT1B, WDT2B, WDT3B, WDT4B, WDT5B, WDT6B, WDT7B, WDT8B, + GETHER0, GETHER1, GETHER2, + PBIA, PBIB, PBIC, + DMAE2, DMAE3, + SERMUX2, SERMUX3, /* interrupt groups */ @@ -221,19 +219,18 @@ static struct intc_vect vectors[] __initdata = { INTC_VECT(DVC, 0x4e0), INTC_VECT(IRQ8, 0x500), INTC_VECT(IRQ9, 0x520), INTC_VECT(IRQ10, 0x540), - INTC_VECT(WDT0, 0x560), INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0), INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0), INTC_VECT(HUDI, 0x600), INTC_VECT(ARC4, 0x620), - INTC_VECT(DMAC0, 0x640), INTC_VECT(DMAC0, 0x660), - INTC_VECT(DMAC0, 0x680), INTC_VECT(DMAC0, 0x6a0), - INTC_VECT(DMAC0, 0x6c0), + INTC_VECT(DMAC0_5, 0x640), INTC_VECT(DMAC0_5, 0x660), + INTC_VECT(DMAC0_5, 0x680), INTC_VECT(DMAC0_5, 0x6a0), + INTC_VECT(DMAC0_5, 0x6c0), INTC_VECT(IRQ11, 0x6e0), INTC_VECT(SCIF2, 0x700), INTC_VECT(SCIF2, 0x720), INTC_VECT(SCIF2, 0x740), INTC_VECT(SCIF2, 0x760), - INTC_VECT(DMAC0, 0x780), INTC_VECT(DMAC0, 0x7a0), - INTC_VECT(DMAC1_6, 0x7c0), INTC_VECT(DMAC1_6, 0x7e0), + INTC_VECT(DMAC0_5, 0x780), INTC_VECT(DMAC0_5, 0x7a0), + INTC_VECT(DMAC6_7, 0x7c0), INTC_VECT(DMAC6_7, 0x7e0), INTC_VECT(USB0, 0x840), INTC_VECT(IRQ12, 0x880), INTC_VECT(JMC, 0x8a0), @@ -242,7 +239,6 @@ static struct intc_vect vectors[] __initdata = { INTC_VECT(USB1, 0x920), INTC_VECT(TMR01, 0xa00), INTC_VECT(TMR23, 0xa20), INTC_VECT(TMR45, 0xa40), - INTC_VECT(WDT1, 0xa60), INTC_VECT(FRT, 0xa80), INTC_VECT(LPC, 0xaa0), INTC_VECT(LPC, 0xac0), INTC_VECT(LPC, 0xae0), INTC_VECT(LPC, 0xb00), @@ -250,14 +246,14 @@ static struct intc_vect vectors[] __initdata = { INTC_VECT(SCIF0, 0xb40), INTC_VECT(SCIF1, 0xb60), INTC_VECT(SCIF3, 0xb80), INTC_VECT(SCIF3, 0xba0), INTC_VECT(SCIF3, 0xbc0), INTC_VECT(SCIF3, 0xbe0), - INTC_VECT(PECI0I, 0xc00), INTC_VECT(PECI1I, 0xc20), - INTC_VECT(PECI2I, 0xc40), + INTC_VECT(PECI0, 0xc00), INTC_VECT(PECI1, 0xc20), + INTC_VECT(PECI2, 0xc40), INTC_VECT(IRQ15, 0xc60), INTC_VECT(ETHERC, 0xc80), INTC_VECT(ETHERC, 0xca0), INTC_VECT(SPI0, 0xcc0), INTC_VECT(ADC1, 0xce0), - INTC_VECT(DMAC1_8, 0xd00), INTC_VECT(DMAC1_8, 0xd20), - INTC_VECT(DMAC1_8, 0xd40), INTC_VECT(DMAC1_8, 0xd60), + INTC_VECT(DMAC8_11, 0xd00), INTC_VECT(DMAC8_11, 0xd20), + INTC_VECT(DMAC8_11, 0xd40), INTC_VECT(DMAC8_11, 0xd60), INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0), INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0), INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20), @@ -278,17 +274,47 @@ static struct intc_vect vectors[] __initdata = { INTC_VECT(IIC5_0, 0x1860), INTC_VECT(IIC5_1, 0x1880), INTC_VECT(IIC5_2, 0x18a0), INTC_VECT(IIC5_3, 0x18c0), INTC_VECT(IIC6_0, 0x18e0), INTC_VECT(IIC6_1, 0x1900), - INTC_VECT(IIC6_2, 0x1920), INTC_VECT(IIC6_3, 0x1980), + INTC_VECT(IIC6_2, 0x1920), + INTC_VECT(ONFICTL, 0x1960), + INTC_VECT(IIC6_3, 0x1980), INTC_VECT(IIC7_0, 0x19a0), INTC_VECT(IIC7_1, 0x1a00), INTC_VECT(IIC7_2, 0x1a20), INTC_VECT(IIC7_3, 0x1a40), INTC_VECT(IIC8_0, 0x1a60), INTC_VECT(IIC8_1, 0x1a80), INTC_VECT(IIC8_2, 0x1aa0), INTC_VECT(IIC8_3, 0x1b40), INTC_VECT(IIC9_0, 0x1b60), INTC_VECT(IIC9_1, 0x1b80), INTC_VECT(IIC9_2, 0x1c00), INTC_VECT(IIC9_3, 0x1c20), - INTC_VECT(PCIINTA, 0x1ce0), - INTC_VECT(PCIE, 0x1e00), - INTC_VECT(SGPIO, 0x1f80), - INTC_VECT(SGPIO, 0x1fa0), + INTC_VECT(MMC1, 0x1c60), INTC_VECT(MMC2, 0x1c80), + INTC_VECT(ECCU, 0x1cc0), + INTC_VECT(PCIC, 0x1ce0), + INTC_VECT(G200, 0x1d00), + INTC_VECT(RSPI, 0x1d80), INTC_VECT(RSPI, 0x1da0), + INTC_VECT(RSPI, 0x1dc0), INTC_VECT(RSPI, 0x1de0), + INTC_VECT(PECI3, 0x1ec0), INTC_VECT(PECI4, 0x1ee0), + INTC_VECT(PECI5, 0x1f00), + INTC_VECT(SGPIO, 0x1f80), INTC_VECT(SGPIO, 0x1fa0), + INTC_VECT(SGPIO, 0x1fc0), + INTC_VECT(DMINT12, 0x2400), INTC_VECT(DMINT13, 0x2420), + INTC_VECT(DMINT14, 0x2440), INTC_VECT(DMINT15, 0x2460), + INTC_VECT(DMINT16, 0x2480), INTC_VECT(DMINT17, 0x24e0), + INTC_VECT(DMINT18, 0x2500), INTC_VECT(DMINT19, 0x2520), + INTC_VECT(DMINT20, 0x2540), INTC_VECT(DMINT21, 0x2560), + INTC_VECT(DMINT22, 0x2580), INTC_VECT(DMINT23, 0x2600), + INTC_VECT(DDRECC, 0x2620), + INTC_VECT(TSIP, 0x2640), + INTC_VECT(PCIE_BRIDGE, 0x27c0), + INTC_VECT(WDT0B, 0x2800), INTC_VECT(WDT1B, 0x2820), + INTC_VECT(WDT2B, 0x2840), INTC_VECT(WDT3B, 0x2860), + INTC_VECT(WDT4B, 0x2880), INTC_VECT(WDT5B, 0x28a0), + INTC_VECT(WDT6B, 0x28c0), INTC_VECT(WDT7B, 0x28e0), + INTC_VECT(WDT8B, 0x2900), + INTC_VECT(GETHER0, 0x2960), INTC_VECT(GETHER1, 0x2980), + INTC_VECT(GETHER2, 0x29a0), + INTC_VECT(PBIA, 0x2a00), INTC_VECT(PBIB, 0x2a20), + INTC_VECT(PBIC, 0x2a40), + INTC_VECT(DMAE2, 0x2a60), INTC_VECT(DMAE3, 0x2a80), + INTC_VECT(SERMUX2, 0x2aa0), INTC_VECT(SERMUX3, 0x2b40), + INTC_VECT(LPC5, 0x2b60), INTC_VECT(LPC6, 0x2b80), + INTC_VECT(LPC7, 0x2c00), INTC_VECT(LPC8, 0x2c20), }; static struct intc_group groups[] __initdata = { @@ -312,31 +338,45 @@ static struct intc_mask_reg mask_registers[] __initdata = { { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */ { 0, 0, 0, 0, 0, 0, 0, 0, - 0, DMAC1_8, 0, PECI0I, LPC, FRT, WDT1, TMR45, - TMR23, TMR01, 0, 0, 0, 0, 0, DMAC0, - HUDI, 0, WDT0, SCIF3, SCIF2, SDHI, TMU345, TMU012 + 0, DMAC8_11, 0, PECI0, LPC, FRT, 0, TMR45, + TMR23, TMR01, 0, 0, 0, 0, 0, DMAC0_5, + HUDI, 0, 0, SCIF3, SCIF2, SDHI, TMU345, TMU012 } }, { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */ { IRQ15, IRQ14, IRQ13, IRQ12, IRQ11, IRQ10, SCIF4, ETHERC, IRQ9, IRQ8, SCIF1, SCIF0, USB0, 0, 0, USB1, - ADC1, 0, DMAC1_6, ADC0, SPI0, SIM, PECI2I, PECI1I, + ADC1, 0, DMAC6_7, ADC0, SPI0, SIM, PECI2, PECI1, ARC4, 0, SPI1, JMC, 0, 0, 0, DVC } }, { 0xffd10038, 0xffd1003c, 32, /* INT2MSKR2 / INT2MSKCR2 */ - { IIC4_1, IIC4_2, IIC5_0, 0, 0, 0, SGPIO, 0, - 0, 0, 0, IIC9_2, IIC8_2, IIC8_1, IIC8_0, IIC7_3, + { IIC4_1, IIC4_2, IIC5_0, ONFICTL, 0, 0, SGPIO, 0, + 0, G200, 0, IIC9_2, IIC8_2, IIC8_1, IIC8_0, IIC7_3, IIC7_2, IIC7_1, IIC6_3, IIC0_0, IIC0_1, IIC0_2, IIC0_3, IIC3_1, - IIC2_3, 0, IIC2_1, IIC9_1, IIC3_3, IIC1_0, PCIE, IIC2_2 + IIC2_3, 0, IIC2_1, IIC9_1, IIC3_3, IIC1_0, 0, IIC2_2 } }, - { 0xffd100d0, 0xff1400d4, 32, /* INT2MSKR3 / INT2MSKCR4 */ - { 0, IIC6_1, IIC6_0, IIC5_1, IIC3_2, IIC2_0, 0, 0, + { 0xffd100d0, 0xffd100d4, 32, /* INT2MSKR3 / INT2MSKCR3 */ + { MMC1, IIC6_1, IIC6_0, IIC5_1, IIC3_2, IIC2_0, PECI5, MMC2, IIC1_3, IIC1_2, IIC9_0, IIC8_3, IIC4_3, IIC7_0, 0, IIC6_2, - PCIINTA, 0, IIC4_0, 0, 0, 0, 0, IIC9_3, + PCIC, 0, IIC4_0, 0, ECCU, RSPI, 0, IIC9_3, IIC3_0, 0, IIC5_3, IIC5_2, 0, 0, 0, IIC1_1 } }, + + { 0xffd20038, 0xffd2003c, 32, /* INT2MSKR4 / INT2MSKCR4 */ + { WDT0B, WDT1B, WDT3B, GETHER0, 0, 0, 0, 0, + 0, 0, 0, LPC7, SERMUX2, DMAE3, DMAE2, PBIC, + PBIB, PBIA, GETHER1, DMINT12, DMINT13, DMINT14, DMINT15, TSIP, + DMINT23, 0, DMINT21, LPC6, 0, DMINT16, 0, DMINT22 + } }, + + { 0xffd200d0, 0xffd200d4, 32, /* INT2MSKR5 / INT2MSKCR5 */ + { 0, WDT8B, WDT7B, WDT4B, 0, DMINT20, 0, 0, + DMINT19, DMINT18, LPC5, SERMUX3, WDT2B, GETHER2, 0, 0, + 0, 0, PCIE_BRIDGE, 0, 0, 0, 0, LPC8, + DDRECC, 0, WDT6B, WDT5B, 0, 0, 0, DMINT17 + } }, }; #define INTPRI 0xffd00010 @@ -372,6 +412,22 @@ static struct intc_mask_reg mask_registers[] __initdata = { #define INT2PRI29 0xffd100b4 #define INT2PRI30 0xffd100b8 #define INT2PRI31 0xffd100bc +#define INT2PRI32 0xffd20000 +#define INT2PRI33 0xffd20004 +#define INT2PRI34 0xffd20008 +#define INT2PRI35 0xffd2000c +#define INT2PRI36 0xffd20010 +#define INT2PRI37 0xffd20014 +#define INT2PRI38 0xffd20018 +#define INT2PRI39 0xffd2001c +#define INT2PRI40 0xffd200a0 +#define INT2PRI41 0xffd200a4 +#define INT2PRI42 0xffd200a8 +#define INT2PRI43 0xffd200ac +#define INT2PRI44 0xffd200b0 +#define INT2PRI45 0xffd200b4 +#define INT2PRI46 0xffd200b8 +#define INT2PRI47 0xffd200bc static struct intc_prio_reg prio_registers[] __initdata = { { INTPRI, 0, 32, 4, { IRQ0, IRQ1, IRQ2, IRQ3, @@ -379,39 +435,61 @@ static struct intc_prio_reg prio_registers[] __initdata = { { INT2PRI0, 0, 32, 8, { TMU0, TMU1, TMU2, TMU2_TICPI } }, { INT2PRI1, 0, 32, 8, { TMU3, TMU4, TMU5, SDHI } }, - { INT2PRI2, 0, 32, 8, { SCIF2, SCIF3, WDT0, IRQ8 } }, - { INT2PRI3, 0, 32, 8, { HUDI, DMAC0, ADC0, IRQ9 } }, + { INT2PRI2, 0, 32, 8, { SCIF2, SCIF3, 0, IRQ8 } }, + { INT2PRI3, 0, 32, 8, { HUDI, DMAC0_5, ADC0, IRQ9 } }, { INT2PRI4, 0, 32, 8, { IRQ10, 0, TMR01, TMR23 } }, - { INT2PRI5, 0, 32, 8, { TMR45, WDT1, FRT, LPC } }, - { INT2PRI6, 0, 32, 8, { PECI0I, ETHERC, DMAC1_8, 0 } }, + { INT2PRI5, 0, 32, 8, { TMR45, 0, FRT, LPC } }, + { INT2PRI6, 0, 32, 8, { PECI0, ETHERC, DMAC8_11, 0 } }, { INT2PRI7, 0, 32, 8, { SCIF4, 0, IRQ11, IRQ12 } }, { INT2PRI8, 0, 32, 8, { 0, 0, 0, DVC } }, { INT2PRI9, 0, 32, 8, { ARC4, 0, SPI1, JMC } }, - { INT2PRI10, 0, 32, 8, { SPI0, SIM, PECI2I, PECI1I } }, - { INT2PRI11, 0, 32, 8, { ADC1, IRQ13, DMAC1_6, IRQ14 } }, + { INT2PRI10, 0, 32, 8, { SPI0, SIM, PECI2, PECI1 } }, + { INT2PRI11, 0, 32, 8, { ADC1, IRQ13, DMAC6_7, IRQ14 } }, { INT2PRI12, 0, 32, 8, { USB0, 0, IRQ15, USB1 } }, { INT2PRI13, 0, 32, 8, { 0, 0, SCIF1, SCIF0 } }, { INT2PRI16, 0, 32, 8, { IIC2_2, 0, 0, 0 } }, - { INT2PRI17, 0, 32, 8, { PCIE, 0, 0, IIC1_0 } }, + { INT2PRI17, 0, 32, 8, { 0, 0, 0, IIC1_0 } }, { INT2PRI18, 0, 32, 8, { IIC3_3, IIC9_1, IIC2_1, IIC1_2 } }, { INT2PRI19, 0, 32, 8, { IIC2_3, IIC3_1, 0, IIC1_3 } }, { INT2PRI20, 0, 32, 8, { IIC2_0, IIC6_3, IIC7_1, IIC7_2 } }, { INT2PRI21, 0, 32, 8, { IIC7_3, IIC8_0, IIC8_1, IIC8_2 } }, - { INT2PRI22, 0, 32, 8, { IIC9_2, 0, 0, 0 } }, - { INT2PRI23, 0, 32, 8, { 0, SGPIO, IIC3_2, IIC5_1 } }, - { INT2PRI24, 0, 32, 8, { 0, 0, 0, IIC1_1 } }, + { INT2PRI22, 0, 32, 8, { IIC9_2, MMC2, G200, 0 } }, + { INT2PRI23, 0, 32, 8, { PECI5, SGPIO, IIC3_2, IIC5_1 } }, + { INT2PRI24, 0, 32, 8, { PECI4, PECI3, 0, IIC1_1 } }, { INT2PRI25, 0, 32, 8, { IIC3_0, 0, IIC5_3, IIC5_2 } }, - { INT2PRI26, 0, 32, 8, { 0, 0, 0, IIC9_3 } }, - { INT2PRI27, 0, 32, 8, { PCIINTA, IIC6_0, IIC4_0, IIC6_1 } }, - { INT2PRI28, 0, 32, 8, { IIC4_3, IIC7_0, 0, IIC6_2 } }, + { INT2PRI26, 0, 32, 8, { ECCU, RSPI, 0, IIC9_3 } }, + { INT2PRI27, 0, 32, 8, { PCIC, IIC6_0, IIC4_0, IIC6_1 } }, + { INT2PRI28, 0, 32, 8, { IIC4_3, IIC7_0, MMC1, IIC6_2 } }, { INT2PRI29, 0, 32, 8, { 0, 0, IIC9_0, IIC8_3 } }, - { INT2PRI30, 0, 32, 8, { IIC4_1, IIC4_2, IIC5_0, 0 } }, + { INT2PRI30, 0, 32, 8, { IIC4_1, IIC4_2, IIC5_0, ONFICTL } }, { INT2PRI31, 0, 32, 8, { IIC0_0, IIC0_1, IIC0_2, IIC0_3 } }, + { INT2PRI32, 0, 32, 8, { DMINT22, 0, 0, 0 } }, + { INT2PRI33, 0, 32, 8, { 0, 0, 0, DMINT16 } }, + { INT2PRI34, 0, 32, 8, { 0, LPC6, DMINT21, DMINT18 } }, + { INT2PRI35, 0, 32, 8, { DMINT23, TSIP, 0, DMINT19 } }, + { INT2PRI36, 0, 32, 8, { DMINT20, GETHER1, PBIA, PBIB } }, + { INT2PRI37, 0, 32, 8, { PBIC, DMAE2, DMAE3, SERMUX2 } }, + { INT2PRI38, 0, 32, 8, { LPC7, 0, 0, 0 } }, + { INT2PRI39, 0, 32, 8, { 0, 0, 0, WDT4B } }, + { INT2PRI40, 0, 32, 8, { 0, 0, 0, DMINT17 } }, + { INT2PRI41, 0, 32, 8, { DDRECC, 0, WDT6B, WDT5B } }, + { INT2PRI42, 0, 32, 8, { 0, 0, 0, LPC8 } }, + { INT2PRI43, 0, 32, 8, { 0, WDT7B, PCIE_BRIDGE, WDT8B } }, + { INT2PRI44, 0, 32, 8, { WDT2B, GETHER2, 0, 0 } }, + { INT2PRI45, 0, 32, 8, { 0, 0, LPC5, SERMUX3 } }, + { INT2PRI46, 0, 32, 8, { WDT0B, WDT1B, WDT3B, GETHER0 } }, + { INT2PRI47, 0, 32, 8, { DMINT12, DMINT13, DMINT14, DMINT15 } }, +}; + +static struct intc_sense_reg sense_registers_irq8to15[] __initdata = { + { 0xffd100f8, 32, 2, /* ICR2 */ { IRQ15, IRQ14, IRQ13, IRQ12, + IRQ11, IRQ10, IRQ9, IRQ8 } }, }; static DECLARE_INTC_DESC(intc_desc, "sh7757", vectors, groups, - mask_registers, prio_registers, NULL); + mask_registers, prio_registers, + sense_registers_irq8to15); /* Support for external interrupt pins in IRQ mode */ static struct intc_vect vectors_irq0123[] __initdata = { -- cgit v1.1 From 3810e96056ffddf68305f6d11d2d5103ec1f605d Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Tue, 6 Jul 2010 04:31:57 +0000 Subject: sh: modify pinmux for SH7757 2nd cut Signed-off-by: Yoshihiro Shimoda Signed-off-by: Paul Mundt --- arch/sh/include/cpu-sh4/cpu/sh7757.h | 301 +++--- arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c | 1582 ++++++++++++++++++------------- 2 files changed, 1081 insertions(+), 802 deletions(-) (limited to 'arch') diff --git a/arch/sh/include/cpu-sh4/cpu/sh7757.h b/arch/sh/include/cpu-sh4/cpu/sh7757.h index f4d267e..15f3de1 100644 --- a/arch/sh/include/cpu-sh4/cpu/sh7757.h +++ b/arch/sh/include/cpu-sh4/cpu/sh7757.h @@ -3,241 +3,252 @@ enum { /* PTA */ - GPIO_PTA7, GPIO_PTA6, GPIO_PTA5, GPIO_PTA4, - GPIO_PTA3, GPIO_PTA2, GPIO_PTA1, GPIO_PTA0, + GPIO_PTA0, GPIO_PTA1, GPIO_PTA2, GPIO_PTA3, + GPIO_PTA4, GPIO_PTA5, GPIO_PTA6, GPIO_PTA7, /* PTB */ - GPIO_PTB7, GPIO_PTB6, GPIO_PTB5, GPIO_PTB4, - GPIO_PTB3, GPIO_PTB2, GPIO_PTB1, GPIO_PTB0, + GPIO_PTB0, GPIO_PTB1, GPIO_PTB2, GPIO_PTB3, + GPIO_PTB4, GPIO_PTB5, GPIO_PTB6, GPIO_PTB7, /* PTC */ - GPIO_PTC7, GPIO_PTC6, GPIO_PTC5, GPIO_PTC4, - GPIO_PTC3, GPIO_PTC2, GPIO_PTC1, GPIO_PTC0, + GPIO_PTC0, GPIO_PTC1, GPIO_PTC2, GPIO_PTC3, + GPIO_PTC4, GPIO_PTC5, GPIO_PTC6, GPIO_PTC7, /* PTD */ - GPIO_PTD7, GPIO_PTD6, GPIO_PTD5, GPIO_PTD4, - GPIO_PTD3, GPIO_PTD2, GPIO_PTD1, GPIO_PTD0, + GPIO_PTD0, GPIO_PTD1, GPIO_PTD2, GPIO_PTD3, + GPIO_PTD4, GPIO_PTD5, GPIO_PTD6, GPIO_PTD7, /* PTE */ - GPIO_PTE7, GPIO_PTE6, GPIO_PTE5, GPIO_PTE4, - GPIO_PTE3, GPIO_PTE2, GPIO_PTE1, GPIO_PTE0, + GPIO_PTE0, GPIO_PTE1, GPIO_PTE2, GPIO_PTE3, + GPIO_PTE4, GPIO_PTE5, GPIO_PTE6, GPIO_PTE7, /* PTF */ - GPIO_PTF7, GPIO_PTF6, GPIO_PTF5, GPIO_PTF4, - GPIO_PTF3, GPIO_PTF2, GPIO_PTF1, GPIO_PTF0, + GPIO_PTF0, GPIO_PTF1, GPIO_PTF2, GPIO_PTF3, + GPIO_PTF4, GPIO_PTF5, GPIO_PTF6, GPIO_PTF7, /* PTG */ - GPIO_PTG7, GPIO_PTG6, GPIO_PTG5, GPIO_PTG4, - GPIO_PTG3, GPIO_PTG2, GPIO_PTG1, GPIO_PTG0, + GPIO_PTG0, GPIO_PTG1, GPIO_PTG2, GPIO_PTG3, + GPIO_PTG4, GPIO_PTG5, GPIO_PTG6, GPIO_PTG7, /* PTH */ - GPIO_PTH7, GPIO_PTH6, GPIO_PTH5, GPIO_PTH4, - GPIO_PTH3, GPIO_PTH2, GPIO_PTH1, GPIO_PTH0, + GPIO_PTH0, GPIO_PTH1, GPIO_PTH2, GPIO_PTH3, + GPIO_PTH4, GPIO_PTH5, GPIO_PTH6, GPIO_PTH7, /* PTI */ - GPIO_PTI7, GPIO_PTI6, GPIO_PTI5, GPIO_PTI4, - GPIO_PTI3, GPIO_PTI2, GPIO_PTI1, GPIO_PTI0, + GPIO_PTI0, GPIO_PTI1, GPIO_PTI2, GPIO_PTI3, + GPIO_PTI4, GPIO_PTI5, GPIO_PTI6, GPIO_PTI7, /* PTJ */ - GPIO_PTJ7, GPIO_PTJ6, GPIO_PTJ5, GPIO_PTJ4, - GPIO_PTJ3, GPIO_PTJ2, GPIO_PTJ1, GPIO_PTJ0, + GPIO_PTJ0, GPIO_PTJ1, GPIO_PTJ2, GPIO_PTJ3, + GPIO_PTJ4, GPIO_PTJ5, GPIO_PTJ6, GPIO_PTJ7_RESV, /* PTK */ - GPIO_PTK7, GPIO_PTK6, GPIO_PTK5, GPIO_PTK4, - GPIO_PTK3, GPIO_PTK2, GPIO_PTK1, GPIO_PTK0, + GPIO_PTK0, GPIO_PTK1, GPIO_PTK2, GPIO_PTK3, + GPIO_PTK4, GPIO_PTK5, GPIO_PTK6, GPIO_PTK7, /* PTL */ - GPIO_PTL7, GPIO_PTL6, GPIO_PTL5, GPIO_PTL4, - GPIO_PTL3, GPIO_PTL2, GPIO_PTL1, GPIO_PTL0, + GPIO_PTL0, GPIO_PTL1, GPIO_PTL2, GPIO_PTL3, + GPIO_PTL4, GPIO_PTL5, GPIO_PTL6, GPIO_PTL7_RESV, /* PTM */ - GPIO_PTM6, GPIO_PTM5, GPIO_PTM4, - GPIO_PTM3, GPIO_PTM2, GPIO_PTM1, GPIO_PTM0, + GPIO_PTM0, GPIO_PTM1, GPIO_PTM2, GPIO_PTM3, + GPIO_PTM4, GPIO_PTM5, GPIO_PTM6, GPIO_PTM7, /* PTN */ - GPIO_PTN7, GPIO_PTN6, GPIO_PTN5, GPIO_PTN4, - GPIO_PTN3, GPIO_PTN2, GPIO_PTN1, GPIO_PTN0, + GPIO_PTN0, GPIO_PTN1, GPIO_PTN2, GPIO_PTN3, + GPIO_PTN4, GPIO_PTN5, GPIO_PTN6, GPIO_PTN7_RESV, /* PTO */ - GPIO_PTO7, GPIO_PTO6, GPIO_PTO5, GPIO_PTO4, - GPIO_PTO3, GPIO_PTO2, GPIO_PTO1, GPIO_PTO0, + GPIO_PTO0, GPIO_PTO1, GPIO_PTO2, GPIO_PTO3, + GPIO_PTO4, GPIO_PTO5, GPIO_PTO6, GPIO_PTO7, /* PTP */ - GPIO_PTP6, GPIO_PTP5, GPIO_PTP4, - GPIO_PTP3, GPIO_PTP2, GPIO_PTP1, GPIO_PTP0, + GPIO_PTP0, GPIO_PTP1, GPIO_PTP2, GPIO_PTP3, + GPIO_PTP4, GPIO_PTP5, GPIO_PTP6, GPIO_PTP7, /* PTQ */ - GPIO_PTQ6, GPIO_PTQ5, GPIO_PTQ4, - GPIO_PTQ3, GPIO_PTQ2, GPIO_PTQ1, GPIO_PTQ0, + GPIO_PTQ0, GPIO_PTQ1, GPIO_PTQ2, GPIO_PTQ3, + GPIO_PTQ4, GPIO_PTQ5, GPIO_PTQ6, GPIO_PTQ7_RESV, /* PTR */ - GPIO_PTR7, GPIO_PTR6, GPIO_PTR5, GPIO_PTR4, - GPIO_PTR3, GPIO_PTR2, GPIO_PTR1, GPIO_PTR0, + GPIO_PTR0, GPIO_PTR1, GPIO_PTR2, GPIO_PTR3, + GPIO_PTR4, GPIO_PTR5, GPIO_PTR6, GPIO_PTR7, /* PTS */ - GPIO_PTS7, GPIO_PTS6, GPIO_PTS5, GPIO_PTS4, - GPIO_PTS3, GPIO_PTS2, GPIO_PTS1, GPIO_PTS0, + GPIO_PTS0, GPIO_PTS1, GPIO_PTS2, GPIO_PTS3, + GPIO_PTS4, GPIO_PTS5, GPIO_PTS6, GPIO_PTS7, /* PTT */ - GPIO_PTT5, GPIO_PTT4, - GPIO_PTT3, GPIO_PTT2, GPIO_PTT1, GPIO_PTT0, + GPIO_PTT0, GPIO_PTT1, GPIO_PTT2, GPIO_PTT3, + GPIO_PTT4, GPIO_PTT5, GPIO_PTT6, GPIO_PTT7, /* PTU */ - GPIO_PTU7, GPIO_PTU6, GPIO_PTU5, GPIO_PTU4, - GPIO_PTU3, GPIO_PTU2, GPIO_PTU1, GPIO_PTU0, + GPIO_PTU0, GPIO_PTU1, GPIO_PTU2, GPIO_PTU3, + GPIO_PTU4, GPIO_PTU5, GPIO_PTU6, GPIO_PTU7, /* PTV */ - GPIO_PTV7, GPIO_PTV6, GPIO_PTV5, GPIO_PTV4, - GPIO_PTV3, GPIO_PTV2, GPIO_PTV1, GPIO_PTV0, + GPIO_PTV0, GPIO_PTV1, GPIO_PTV2, GPIO_PTV3, + GPIO_PTV4, GPIO_PTV5, GPIO_PTV6, GPIO_PTV7, /* PTW */ - GPIO_PTW7, GPIO_PTW6, GPIO_PTW5, GPIO_PTW4, - GPIO_PTW3, GPIO_PTW2, GPIO_PTW1, GPIO_PTW0, + GPIO_PTW0, GPIO_PTW1, GPIO_PTW2, GPIO_PTW3, + GPIO_PTW4, GPIO_PTW5, GPIO_PTW6, GPIO_PTW7, /* PTX */ - GPIO_PTX7, GPIO_PTX6, GPIO_PTX5, GPIO_PTX4, - GPIO_PTX3, GPIO_PTX2, GPIO_PTX1, GPIO_PTX0, + GPIO_PTX0, GPIO_PTX1, GPIO_PTX2, GPIO_PTX3, + GPIO_PTX4, GPIO_PTX5, GPIO_PTX6, GPIO_PTX7, /* PTY */ - GPIO_PTY7, GPIO_PTY6, GPIO_PTY5, GPIO_PTY4, - GPIO_PTY3, GPIO_PTY2, GPIO_PTY1, GPIO_PTY0, + GPIO_PTY0, GPIO_PTY1, GPIO_PTY2, GPIO_PTY3, + GPIO_PTY4, GPIO_PTY5, GPIO_PTY6, GPIO_PTY7, /* PTZ */ - GPIO_PTZ7, GPIO_PTZ6, GPIO_PTZ5, GPIO_PTZ4, - GPIO_PTZ3, GPIO_PTZ2, GPIO_PTZ1, GPIO_PTZ0, + GPIO_PTZ0, GPIO_PTZ1, GPIO_PTZ2, GPIO_PTZ3, + GPIO_PTZ4, GPIO_PTZ5, GPIO_PTZ6, GPIO_PTZ7, - /* PTA (mobule: LBSC, CPG, LPC) */ + /* PTA (mobule: LBSC, RGMII) */ GPIO_FN_BS, GPIO_FN_RDWR, GPIO_FN_WE1, GPIO_FN_RDY, - GPIO_FN_MD10, GPIO_FN_MD9, GPIO_FN_MD8, - GPIO_FN_LGPIO7, GPIO_FN_LGPIO6, GPIO_FN_LGPIO5, GPIO_FN_LGPIO4, - GPIO_FN_LGPIO3, GPIO_FN_LGPIO2, GPIO_FN_LGPIO1, GPIO_FN_LGPIO0, - - /* PTB (mobule: LBSC, EtherC, SIM, LPC) */ - GPIO_FN_D15, GPIO_FN_D14, GPIO_FN_D13, GPIO_FN_D12, - GPIO_FN_D11, GPIO_FN_D10, GPIO_FN_D9, GPIO_FN_D8, - GPIO_FN_ET0_MDC, GPIO_FN_ET0_MDIO, - GPIO_FN_ET1_MDC, GPIO_FN_ET1_MDIO, - GPIO_FN_SIM_D, GPIO_FN_SIM_CLK, GPIO_FN_SIM_RST, - GPIO_FN_WPSZ1, GPIO_FN_WPSZ0, GPIO_FN_FWID, GPIO_FN_FLSHSZ, - GPIO_FN_LPC_SPIEN, GPIO_FN_BASEL, + GPIO_FN_ET0_MDC, GPIO_FN_ET0_MDIO, + GPIO_FN_ET1_MDC, GPIO_FN_ET1_MDIO, - /* PTC (mobule: SD) */ - GPIO_FN_SD_WP, GPIO_FN_SD_CD, GPIO_FN_SD_CLK, GPIO_FN_SD_CMD, - GPIO_FN_SD_D3, GPIO_FN_SD_D2, GPIO_FN_SD_D1, GPIO_FN_SD_D0, + /* PTB (mobule: INTC, ONFI, TMU) */ + GPIO_FN_IRQ15, GPIO_FN_IRQ14, GPIO_FN_IRQ13, GPIO_FN_IRQ12, + GPIO_FN_IRQ11, GPIO_FN_IRQ10, GPIO_FN_IRQ9, GPIO_FN_IRQ8, + GPIO_FN_ON_NRE, GPIO_FN_ON_NWE, GPIO_FN_ON_NWP, GPIO_FN_ON_NCE0, + GPIO_FN_ON_R_B0, GPIO_FN_ON_ALE, GPIO_FN_ON_CLE, + GPIO_FN_TCLK, - /* PTD (mobule: INTC, SPI0, LBSC, CPG, ADC) */ + /* PTC (mobule: IRQ, PWMU) */ GPIO_FN_IRQ7, GPIO_FN_IRQ6, GPIO_FN_IRQ5, GPIO_FN_IRQ4, GPIO_FN_IRQ3, GPIO_FN_IRQ2, GPIO_FN_IRQ1, GPIO_FN_IRQ0, - GPIO_FN_MD6, GPIO_FN_MD5, GPIO_FN_MD3, GPIO_FN_MD2, - GPIO_FN_MD1, GPIO_FN_MD0, GPIO_FN_ADTRG1, GPIO_FN_ADTRG0, - - /* PTE (mobule: EtherC) */ - GPIO_FN_ET0_CRS_DV, GPIO_FN_ET0_TXD1, - GPIO_FN_ET0_TXD0, GPIO_FN_ET0_TX_EN, - GPIO_FN_ET0_REF_CLK, GPIO_FN_ET0_RXD1, - GPIO_FN_ET0_RXD0, GPIO_FN_ET0_RX_ER, - - /* PTF (mobule: EtherC) */ - GPIO_FN_ET1_CRS_DV, GPIO_FN_ET1_TXD1, - GPIO_FN_ET1_TXD0, GPIO_FN_ET1_TX_EN, - GPIO_FN_ET1_REF_CLK, GPIO_FN_ET1_RXD1, - GPIO_FN_ET1_RXD0, GPIO_FN_ET1_RX_ER, - - /* PTG (mobule: SYSTEM, PWMX, LPC) */ - GPIO_FN_STATUS0, GPIO_FN_STATUS1, - GPIO_FN_PWX0, GPIO_FN_PWX1, GPIO_FN_PWX2, GPIO_FN_PWX3, - GPIO_FN_SERIRQ, GPIO_FN_CLKRUN, GPIO_FN_LPCPD, GPIO_FN_LDRQ, - - /* PTH (mobule: TMU, SCIF234, SPI1, SPI0) */ - GPIO_FN_TCLK, GPIO_FN_RXD4, GPIO_FN_TXD4, + GPIO_FN_PWMU0, GPIO_FN_PWMU1, GPIO_FN_PWMU2, GPIO_FN_PWMU3, + GPIO_FN_PWMU4, GPIO_FN_PWMU5, + + /* PTD (mobule: SPI0, DMAC) */ + GPIO_FN_SP0_MOSI, GPIO_FN_SP0_MISO, GPIO_FN_SP0_SCK, + GPIO_FN_SP0_SCK_FB, GPIO_FN_SP0_SS0, GPIO_FN_SP0_SS1, + GPIO_FN_SP0_SS2, GPIO_FN_SP0_SS3, GPIO_FN_DREQ0, + GPIO_FN_DACK0, GPIO_FN_TEND0, + + /* PTE (mobule: RMII) */ + GPIO_FN_RMII0_CRS_DV, GPIO_FN_RMII0_TXD1, GPIO_FN_RMII0_TXD0, + GPIO_FN_RMII0_TXEN, GPIO_FN_RMII0_REFCLK, GPIO_FN_RMII0_RXD1, + GPIO_FN_RMII0_RXD0, GPIO_FN_RMII0_RX_ER, + + /* PTF (mobule: RMII, SerMux) */ + GPIO_FN_RMII1_CRS_DV, GPIO_FN_RMII1_TXD1, GPIO_FN_RMII1_TXD0, + GPIO_FN_RMII1_TXEN, GPIO_FN_RMII1_REFCLK, GPIO_FN_RMII1_RXD1, + GPIO_FN_RMII1_RXD0, GPIO_FN_RMII1_RX_ER, GPIO_FN_RAC_RI, + + /* PTG (mobule: system, LBSC, LPC, WDT, LPC, eMMC) */ + GPIO_FN_BOOTFMS, GPIO_FN_BOOTWP, + GPIO_FN_A25, GPIO_FN_A24, GPIO_FN_SERIRQ, GPIO_FN_WDTOVF, + GPIO_FN_LPCPD, GPIO_FN_LDRQ, GPIO_FN_MMCCLK, GPIO_FN_MMCCMD, + + /* PTH (mobule: SPI1, LPC, DMAC, ADC) */ GPIO_FN_SP1_MOSI, GPIO_FN_SP1_MISO, GPIO_FN_SP1_SCK, GPIO_FN_SP1_SCK_FB, GPIO_FN_SP1_SS0, GPIO_FN_SP1_SS1, - GPIO_FN_SP0_SS1, - - /* PTI (mobule: INTC) */ - GPIO_FN_IRQ15, GPIO_FN_IRQ14, GPIO_FN_IRQ13, GPIO_FN_IRQ12, - GPIO_FN_IRQ11, GPIO_FN_IRQ10, GPIO_FN_IRQ9, GPIO_FN_IRQ8, - - /* PTJ (mobule: SCIF234, SERMUX) */ - GPIO_FN_RXD3, GPIO_FN_TXD3, GPIO_FN_RXD2, GPIO_FN_TXD2, - GPIO_FN_COM1_TXD, GPIO_FN_COM1_RXD, - GPIO_FN_COM1_RTS, GPIO_FN_COM1_CTS, - - /* PTK (mobule: SERMUX) */ - GPIO_FN_COM2_TXD, GPIO_FN_COM2_RXD, - GPIO_FN_COM2_RTS, GPIO_FN_COM2_CTS, - GPIO_FN_COM2_DTR, GPIO_FN_COM2_DSR, - GPIO_FN_COM2_DCD, GPIO_FN_COM2_RI, + GPIO_FN_WP, GPIO_FN_FMS0, GPIO_FN_TEND1, GPIO_FN_DREQ1, + GPIO_FN_DACK1, GPIO_FN_ADTRG1, GPIO_FN_ADTRG0, - /* PTL (mobule: SERMUX) */ - GPIO_FN_RAC_TXD, GPIO_FN_RAC_RXD, - GPIO_FN_RAC_RTS, GPIO_FN_RAC_CTS, - GPIO_FN_RAC_DTR, GPIO_FN_RAC_DSR, - GPIO_FN_RAC_DCD, GPIO_FN_RAC_RI, + /* PTI (mobule: LBSC, SDHI) */ + GPIO_FN_D15, GPIO_FN_D14, GPIO_FN_D13, GPIO_FN_D12, + GPIO_FN_D11, GPIO_FN_D10, GPIO_FN_D9, GPIO_FN_D8, + GPIO_FN_SD_WP, GPIO_FN_SD_CD, GPIO_FN_SD_CLK, GPIO_FN_SD_CMD, + GPIO_FN_SD_D3, GPIO_FN_SD_D2, GPIO_FN_SD_D1, GPIO_FN_SD_D0, - /* PTM (mobule: IIC, LPC) */ + /* PTJ (mobule: SCIF234) */ + GPIO_FN_RTS3, GPIO_FN_CTS3, GPIO_FN_TXD3, GPIO_FN_RXD3, + GPIO_FN_RTS4, GPIO_FN_RXD4, GPIO_FN_TXD4, + + /* PTK (mobule: SERMUX, LBSC, SCIF) */ + GPIO_FN_COM2_TXD, GPIO_FN_COM2_RXD, GPIO_FN_COM2_RTS, + GPIO_FN_COM2_CTS, GPIO_FN_COM2_DTR, GPIO_FN_COM2_DSR, + GPIO_FN_COM2_DCD, GPIO_FN_CLKOUT, + GPIO_FN_SCK2, GPIO_FN_SCK4, GPIO_FN_SCK3, + + /* PTL (mobule: SERMUX, SCIF, LBSC, AUD) */ + GPIO_FN_RAC_RXD, GPIO_FN_RAC_RTS, GPIO_FN_RAC_CTS, + GPIO_FN_RAC_DTR, GPIO_FN_RAC_DSR, GPIO_FN_RAC_DCD, + GPIO_FN_RAC_TXD, GPIO_FN_RXD2, GPIO_FN_CS5, + GPIO_FN_CS6, GPIO_FN_AUDSYNC, GPIO_FN_AUDCK, + GPIO_FN_TXD2, + + /* PTM (mobule: LBSC, IIC) */ + GPIO_FN_CS4, GPIO_FN_RD, GPIO_FN_WE0, GPIO_FN_CS0, GPIO_FN_SDA6, GPIO_FN_SCL6, GPIO_FN_SDA7, GPIO_FN_SCL7, - GPIO_FN_WP, GPIO_FN_FMS0, GPIO_FN_FMS1, - - /* PTN (mobule: SCIF234, EVC) */ - GPIO_FN_SCK2, GPIO_FN_RTS4, GPIO_FN_RTS3, GPIO_FN_RTS2, - GPIO_FN_CTS4, GPIO_FN_CTS3, GPIO_FN_CTS2, - GPIO_FN_EVENT7, GPIO_FN_EVENT6, GPIO_FN_EVENT5, GPIO_FN_EVENT4, - GPIO_FN_EVENT3, GPIO_FN_EVENT2, GPIO_FN_EVENT1, GPIO_FN_EVENT0, - /* PTO (mobule: SGPIO) */ - GPIO_FN_SGPIO0_CLK, GPIO_FN_SGPIO0_LOAD, - GPIO_FN_SGPIO0_DI, GPIO_FN_SGPIO0_DO, - GPIO_FN_SGPIO1_CLK, GPIO_FN_SGPIO1_LOAD, - GPIO_FN_SGPIO1_DI, GPIO_FN_SGPIO1_DO, + /* PTN (mobule: USB, JMC, SGPIO, WDT) */ + GPIO_FN_VBUS_EN, GPIO_FN_VBUS_OC, GPIO_FN_JMCTCK, + GPIO_FN_JMCTMS, GPIO_FN_JMCTDO, GPIO_FN_JMCTDI, + GPIO_FN_JMCTRST, + GPIO_FN_SGPIO1_CLK, GPIO_FN_SGPIO1_LOAD, GPIO_FN_SGPIO1_DI, + GPIO_FN_SGPIO1_DO, GPIO_FN_SUB_CLKIN, - /* PTP (mobule: JMC, SCIF234) */ - GPIO_FN_JMCTCK, GPIO_FN_JMCTMS, GPIO_FN_JMCTDO, GPIO_FN_JMCTDI, - GPIO_FN_JMCRST, GPIO_FN_SCK4, GPIO_FN_SCK3, + /* PTO (mobule: SGPIO, SerMux) */ + GPIO_FN_SGPIO0_CLK, GPIO_FN_SGPIO0_LOAD, GPIO_FN_SGPIO0_DI, + GPIO_FN_SGPIO0_DO, GPIO_FN_SGPIO2_CLK, GPIO_FN_SGPIO2_LOAD, + GPIO_FN_SGPIO2_DI, GPIO_FN_SGPIO2_DO, GPIO_FN_COM1_TXD, + GPIO_FN_COM1_RXD, GPIO_FN_COM1_RTS, GPIO_FN_COM1_CTS, /* PTQ (mobule: LPC) */ GPIO_FN_LAD3, GPIO_FN_LAD2, GPIO_FN_LAD1, GPIO_FN_LAD0, GPIO_FN_LFRAME, GPIO_FN_LRESET, GPIO_FN_LCLK, /* PTR (mobule: GRA, IIC) */ - GPIO_FN_DDC3, GPIO_FN_DDC2, - GPIO_FN_SDA8, GPIO_FN_SCL8, GPIO_FN_SDA2, GPIO_FN_SCL2, + GPIO_FN_DDC3, GPIO_FN_DDC2, GPIO_FN_SDA2, GPIO_FN_SCL2, GPIO_FN_SDA1, GPIO_FN_SCL1, GPIO_FN_SDA0, GPIO_FN_SCL0, + GPIO_FN_SDA8, GPIO_FN_SCL8, /* PTS (mobule: GRA, IIC) */ - GPIO_FN_DDC1, GPIO_FN_DDC0, - GPIO_FN_SDA9, GPIO_FN_SCL9, GPIO_FN_SDA5, GPIO_FN_SCL5, + GPIO_FN_DDC1, GPIO_FN_DDC0, GPIO_FN_SDA5, GPIO_FN_SCL5, GPIO_FN_SDA4, GPIO_FN_SCL4, GPIO_FN_SDA3, GPIO_FN_SCL3, + GPIO_FN_SDA9, GPIO_FN_SCL9, - /* PTT (mobule: SYSTEM, PWMX) */ - GPIO_FN_AUDSYNC, GPIO_FN_AUDCK, - GPIO_FN_AUDATA3, GPIO_FN_AUDATA2, - GPIO_FN_AUDATA1, GPIO_FN_AUDATA0, - GPIO_FN_PWX7, GPIO_FN_PWX6, GPIO_FN_PWX5, GPIO_FN_PWX4, + /* PTT (mobule: PWMX, AUD) */ + GPIO_FN_PWMX7, GPIO_FN_PWMX6, GPIO_FN_PWMX5, GPIO_FN_PWMX4, + GPIO_FN_PWMX3, GPIO_FN_PWMX2, GPIO_FN_PWMX1, GPIO_FN_PWMX0, + GPIO_FN_AUDATA3, GPIO_FN_AUDATA2, GPIO_FN_AUDATA1, + GPIO_FN_AUDATA0, GPIO_FN_STATUS1, GPIO_FN_STATUS0, - /* PTU (mobule: LBSC, DMAC) */ - GPIO_FN_CS6, GPIO_FN_CS5, GPIO_FN_CS4, GPIO_FN_CS0, - GPIO_FN_RD, GPIO_FN_WE0, GPIO_FN_A25, GPIO_FN_A24, - GPIO_FN_DREQ0, GPIO_FN_DACK0, + /* PTU (mobule: LPC, APM) */ + GPIO_FN_LGPIO7, GPIO_FN_LGPIO6, GPIO_FN_LGPIO5, GPIO_FN_LGPIO4, + GPIO_FN_LGPIO3, GPIO_FN_LGPIO2, GPIO_FN_LGPIO1, GPIO_FN_LGPIO0, + GPIO_FN_APMONCTL_O, GPIO_FN_APMPWBTOUT_O, GPIO_FN_APMSCI_O, + GPIO_FN_APMVDDON, GPIO_FN_APMSLPBTN, GPIO_FN_APMPWRBTN, + GPIO_FN_APMS5N, GPIO_FN_APMS3N, - /* PTV (mobule: LBSC, DMAC) */ + /* PTV (mobule: LBSC, SerMux, R-SPI, EVC, GRA) */ GPIO_FN_A23, GPIO_FN_A22, GPIO_FN_A21, GPIO_FN_A20, GPIO_FN_A19, GPIO_FN_A18, GPIO_FN_A17, GPIO_FN_A16, - GPIO_FN_TEND0, GPIO_FN_DREQ1, GPIO_FN_DACK1, GPIO_FN_TEND1, + GPIO_FN_COM2_RI, GPIO_FN_R_SPI_MOSI, GPIO_FN_R_SPI_MISO, + GPIO_FN_R_SPI_RSPCK, GPIO_FN_R_SPI_SSL0, GPIO_FN_R_SPI_SSL1, + GPIO_FN_EVENT7, GPIO_FN_EVENT6, GPIO_FN_VBIOS_DI, + GPIO_FN_VBIOS_DO, GPIO_FN_VBIOS_CLK, GPIO_FN_VBIOS_CS, - /* PTW (mobule: LBSC) */ + /* PTW (mobule: LBSC, EVC, SCIF) */ GPIO_FN_A15, GPIO_FN_A14, GPIO_FN_A13, GPIO_FN_A12, GPIO_FN_A11, GPIO_FN_A10, GPIO_FN_A9, GPIO_FN_A8, + GPIO_FN_EVENT5, GPIO_FN_EVENT4, GPIO_FN_EVENT3, GPIO_FN_EVENT2, + GPIO_FN_EVENT1, GPIO_FN_EVENT0, GPIO_FN_CTS4, GPIO_FN_CTS2, - /* PTX (mobule: LBSC) */ + /* PTX (mobule: LBSC, SCIF, SIM) */ GPIO_FN_A7, GPIO_FN_A6, GPIO_FN_A5, GPIO_FN_A4, GPIO_FN_A3, GPIO_FN_A2, GPIO_FN_A1, GPIO_FN_A0, + GPIO_FN_RTS2, GPIO_FN_SIM_D, GPIO_FN_SIM_CLK, GPIO_FN_SIM_RST, /* PTY (mobule: LBSC) */ GPIO_FN_D7, GPIO_FN_D6, GPIO_FN_D5, GPIO_FN_D4, GPIO_FN_D3, GPIO_FN_D2, GPIO_FN_D1, GPIO_FN_D0, + + /* PTZ (mobule: eMMC, ONFI) */ + GPIO_FN_MMCDAT7, GPIO_FN_MMCDAT6, GPIO_FN_MMCDAT5, + GPIO_FN_MMCDAT4, GPIO_FN_MMCDAT3, GPIO_FN_MMCDAT2, + GPIO_FN_MMCDAT1, GPIO_FN_MMCDAT0, + GPIO_FN_ON_DQ7, GPIO_FN_ON_DQ6, GPIO_FN_ON_DQ5, GPIO_FN_ON_DQ4, + GPIO_FN_ON_DQ3, GPIO_FN_ON_DQ2, GPIO_FN_ON_DQ1, GPIO_FN_ON_DQ0, }; #endif /* __ASM_SH7757_H__ */ diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c index ed23b15..4c74bd0 100644 --- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c +++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c @@ -1,11 +1,11 @@ /* - * SH7757 (A0 step) Pinmux + * SH7757 (B0 step) Pinmux * - * Copyright (C) 2009 Renesas Solutions Corp. + * Copyright (C) 2009-2010 Renesas Solutions Corp. * * Author : Yoshihiro Shimoda * - * Based on SH7757 Pinmux + * Based on SH7723 Pinmux * Copyright (C) 2008 Magnus Damm * * This file is subject to the terms and conditions of the GNU General Public @@ -40,27 +40,27 @@ enum { PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA, PTI7_DATA, PTI6_DATA, PTI5_DATA, PTI4_DATA, PTI3_DATA, PTI2_DATA, PTI1_DATA, PTI0_DATA, - PTJ7_DATA, PTJ6_DATA, PTJ5_DATA, PTJ4_DATA, + PTJ6_DATA, PTJ5_DATA, PTJ4_DATA, PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA, PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA, PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA, - PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA, + PTL6_DATA, PTL5_DATA, PTL4_DATA, PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA, - PTM6_DATA, PTM5_DATA, PTM4_DATA, + PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA, PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA, - PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA, + PTN6_DATA, PTN5_DATA, PTN4_DATA, PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA, PTO7_DATA, PTO6_DATA, PTO5_DATA, PTO4_DATA, PTO3_DATA, PTO2_DATA, PTO1_DATA, PTO0_DATA, - PTP6_DATA, PTP5_DATA, PTP4_DATA, + PTP7_DATA, PTP6_DATA, PTP5_DATA, PTP4_DATA, PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA, - PTQ6_DATA, PTQ5_DATA, PTQ4_DATA, + PTQ6_DATA, PTQ5_DATA, PTQ4_DATA, PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA, PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA, PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA, PTS7_DATA, PTS6_DATA, PTS5_DATA, PTS4_DATA, PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA, - PTT5_DATA, PTT4_DATA, + PTT7_DATA, PTT6_DATA, PTT5_DATA, PTT4_DATA, PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA, PTU7_DATA, PTU6_DATA, PTU5_DATA, PTU4_DATA, PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA, @@ -95,27 +95,27 @@ enum { PTH3_IN, PTH2_IN, PTH1_IN, PTH0_IN, PTI7_IN, PTI6_IN, PTI5_IN, PTI4_IN, PTI3_IN, PTI2_IN, PTI1_IN, PTI0_IN, - PTJ7_IN, PTJ6_IN, PTJ5_IN, PTJ4_IN, + PTJ6_IN, PTJ5_IN, PTJ4_IN, PTJ3_IN, PTJ2_IN, PTJ1_IN, PTJ0_IN, PTK7_IN, PTK6_IN, PTK5_IN, PTK4_IN, PTK3_IN, PTK2_IN, PTK1_IN, PTK0_IN, - PTL7_IN, PTL6_IN, PTL5_IN, PTL4_IN, + PTL6_IN, PTL5_IN, PTL4_IN, PTL3_IN, PTL2_IN, PTL1_IN, PTL0_IN, - PTM6_IN, PTM5_IN, PTM4_IN, + PTM7_IN, PTM6_IN, PTM5_IN, PTM4_IN, PTM3_IN, PTM2_IN, PTM1_IN, PTM0_IN, - PTN7_IN, PTN6_IN, PTN5_IN, PTN4_IN, + PTN6_IN, PTN5_IN, PTN4_IN, PTN3_IN, PTN2_IN, PTN1_IN, PTN0_IN, PTO7_IN, PTO6_IN, PTO5_IN, PTO4_IN, PTO3_IN, PTO2_IN, PTO1_IN, PTO0_IN, - PTP6_IN, PTP5_IN, PTP4_IN, + PTP7_IN, PTP6_IN, PTP5_IN, PTP4_IN, PTP3_IN, PTP2_IN, PTP1_IN, PTP0_IN, - PTQ6_IN, PTQ5_IN, PTQ4_IN, + PTQ6_IN, PTQ5_IN, PTQ4_IN, PTQ3_IN, PTQ2_IN, PTQ1_IN, PTQ0_IN, PTR7_IN, PTR6_IN, PTR5_IN, PTR4_IN, PTR3_IN, PTR2_IN, PTR1_IN, PTR0_IN, PTS7_IN, PTS6_IN, PTS5_IN, PTS4_IN, PTS3_IN, PTS2_IN, PTS1_IN, PTS0_IN, - PTT5_IN, PTT4_IN, + PTT7_IN, PTT6_IN, PTT5_IN, PTT4_IN, PTT3_IN, PTT2_IN, PTT1_IN, PTT0_IN, PTU7_IN, PTU6_IN, PTU5_IN, PTU4_IN, PTU3_IN, PTU2_IN, PTU1_IN, PTU0_IN, @@ -132,16 +132,43 @@ enum { PINMUX_INPUT_END, PINMUX_INPUT_PULLUP_BEGIN, + PTA7_IN_PU, PTA6_IN_PU, PTA5_IN_PU, PTA4_IN_PU, + PTA3_IN_PU, PTA2_IN_PU, PTA1_IN_PU, PTA0_IN_PU, + PTD7_IN_PU, PTD6_IN_PU, PTD5_IN_PU, PTD4_IN_PU, + PTD3_IN_PU, PTD2_IN_PU, PTD1_IN_PU, PTD0_IN_PU, + PTE7_IN_PU, PTE6_IN_PU, PTE5_IN_PU, PTE4_IN_PU, + PTE3_IN_PU, PTE2_IN_PU, PTE1_IN_PU, PTE0_IN_PU, + PTF7_IN_PU, PTF6_IN_PU, PTF5_IN_PU, PTF4_IN_PU, + PTF3_IN_PU, PTF2_IN_PU, PTF1_IN_PU, PTF0_IN_PU, + PTG7_IN_PU, PTG6_IN_PU, PTG4_IN_PU, + PTH7_IN_PU, PTH6_IN_PU, PTH5_IN_PU, PTH4_IN_PU, + PTH3_IN_PU, PTH2_IN_PU, PTH1_IN_PU, PTH0_IN_PU, + PTI7_IN_PU, PTI6_IN_PU, PTI4_IN_PU, + PTI3_IN_PU, PTI2_IN_PU, PTI1_IN_PU, PTI0_IN_PU, + PTJ6_IN_PU, PTJ5_IN_PU, PTJ4_IN_PU, + PTJ3_IN_PU, PTJ2_IN_PU, PTJ1_IN_PU, PTJ0_IN_PU, + PTK7_IN_PU, PTK6_IN_PU, PTK5_IN_PU, PTK4_IN_PU, + PTK3_IN_PU, PTK2_IN_PU, PTK1_IN_PU, PTK0_IN_PU, + PTL6_IN_PU, PTL5_IN_PU, PTL4_IN_PU, + PTL3_IN_PU, PTL2_IN_PU, PTL1_IN_PU, PTL0_IN_PU, + PTM7_IN_PU, PTM6_IN_PU, PTM5_IN_PU, PTM4_IN_PU, + PTN4_IN_PU, + PTN3_IN_PU, PTN2_IN_PU, PTN1_IN_PU, PTN0_IN_PU, + PTO7_IN_PU, PTO6_IN_PU, PTO5_IN_PU, PTO4_IN_PU, + PTO3_IN_PU, PTO2_IN_PU, PTO1_IN_PU, PTO0_IN_PU, + PTT7_IN_PU, PTT6_IN_PU, PTT5_IN_PU, PTT4_IN_PU, + PTT3_IN_PU, PTT2_IN_PU, PTT1_IN_PU, PTT0_IN_PU, PTU7_IN_PU, PTU6_IN_PU, PTU5_IN_PU, PTU4_IN_PU, PTU3_IN_PU, PTU2_IN_PU, PTU1_IN_PU, PTU0_IN_PU, PTV7_IN_PU, PTV6_IN_PU, PTV5_IN_PU, PTV4_IN_PU, - PTV3_IN_PU, PTV2_IN_PU, PTV1_IN_PU, PTV0_IN_PU, - PTW7_IN_PU, PTW6_IN_PU, PTW5_IN_PU, PTW4_IN_PU, - PTW3_IN_PU, PTW2_IN_PU, PTW1_IN_PU, PTW0_IN_PU, + PTV3_IN_PU, PTV2_IN_PU, + PTW1_IN_PU, PTW0_IN_PU, PTX7_IN_PU, PTX6_IN_PU, PTX5_IN_PU, PTX4_IN_PU, PTX3_IN_PU, PTX2_IN_PU, PTX1_IN_PU, PTX0_IN_PU, PTY7_IN_PU, PTY6_IN_PU, PTY5_IN_PU, PTY4_IN_PU, PTY3_IN_PU, PTY2_IN_PU, PTY1_IN_PU, PTY0_IN_PU, + PTZ7_IN_PU, PTZ6_IN_PU, PTZ5_IN_PU, PTZ4_IN_PU, + PTZ3_IN_PU, PTZ2_IN_PU, PTZ1_IN_PU, PTZ0_IN_PU, PINMUX_INPUT_PULLUP_END, PINMUX_OUTPUT_BEGIN, @@ -163,27 +190,27 @@ enum { PTH3_OUT, PTH2_OUT, PTH1_OUT, PTH0_OUT, PTI7_OUT, PTI6_OUT, PTI5_OUT, PTI4_OUT, PTI3_OUT, PTI2_OUT, PTI1_OUT, PTI0_OUT, - PTJ7_OUT, PTJ6_OUT, PTJ5_OUT, PTJ4_OUT, + PTJ6_OUT, PTJ5_OUT, PTJ4_OUT, PTJ3_OUT, PTJ2_OUT, PTJ1_OUT, PTJ0_OUT, PTK7_OUT, PTK6_OUT, PTK5_OUT, PTK4_OUT, PTK3_OUT, PTK2_OUT, PTK1_OUT, PTK0_OUT, - PTL7_OUT, PTL6_OUT, PTL5_OUT, PTL4_OUT, + PTL6_OUT, PTL5_OUT, PTL4_OUT, PTL3_OUT, PTL2_OUT, PTL1_OUT, PTL0_OUT, - PTM6_OUT, PTM5_OUT, PTM4_OUT, + PTM7_OUT, PTM6_OUT, PTM5_OUT, PTM4_OUT, PTM3_OUT, PTM2_OUT, PTM1_OUT, PTM0_OUT, - PTN7_OUT, PTN6_OUT, PTN5_OUT, PTN4_OUT, + PTN6_OUT, PTN5_OUT, PTN4_OUT, PTN3_OUT, PTN2_OUT, PTN1_OUT, PTN0_OUT, PTO7_OUT, PTO6_OUT, PTO5_OUT, PTO4_OUT, PTO3_OUT, PTO2_OUT, PTO1_OUT, PTO0_OUT, - PTP6_OUT, PTP5_OUT, PTP4_OUT, + PTP7_OUT, PTP6_OUT, PTP5_OUT, PTP4_OUT, PTP3_OUT, PTP2_OUT, PTP1_OUT, PTP0_OUT, - PTQ6_OUT, PTQ5_OUT, PTQ4_OUT, + PTQ6_OUT, PTQ5_OUT, PTQ4_OUT, PTQ3_OUT, PTQ2_OUT, PTQ1_OUT, PTQ0_OUT, PTR7_OUT, PTR6_OUT, PTR5_OUT, PTR4_OUT, PTR3_OUT, PTR2_OUT, PTR1_OUT, PTR0_OUT, PTS7_OUT, PTS6_OUT, PTS5_OUT, PTS4_OUT, PTS3_OUT, PTS2_OUT, PTS1_OUT, PTS0_OUT, - PTT5_OUT, PTT4_OUT, + PTT7_OUT, PTT6_OUT, PTT5_OUT, PTT4_OUT, PTT3_OUT, PTT2_OUT, PTT1_OUT, PTT0_OUT, PTU7_OUT, PTU6_OUT, PTU5_OUT, PTU4_OUT, PTU3_OUT, PTU2_OUT, PTU1_OUT, PTU0_OUT, @@ -218,27 +245,27 @@ enum { PTH3_FN, PTH2_FN, PTH1_FN, PTH0_FN, PTI7_FN, PTI6_FN, PTI5_FN, PTI4_FN, PTI3_FN, PTI2_FN, PTI1_FN, PTI0_FN, - PTJ7_FN, PTJ6_FN, PTJ5_FN, PTJ4_FN, + PTJ6_FN, PTJ5_FN, PTJ4_FN, PTJ3_FN, PTJ2_FN, PTJ1_FN, PTJ0_FN, PTK7_FN, PTK6_FN, PTK5_FN, PTK4_FN, PTK3_FN, PTK2_FN, PTK1_FN, PTK0_FN, - PTL7_FN, PTL6_FN, PTL5_FN, PTL4_FN, + PTL6_FN, PTL5_FN, PTL4_FN, PTL3_FN, PTL2_FN, PTL1_FN, PTL0_FN, - PTM6_FN, PTM5_FN, PTM4_FN, + PTM7_FN, PTM6_FN, PTM5_FN, PTM4_FN, PTM3_FN, PTM2_FN, PTM1_FN, PTM0_FN, - PTN7_FN, PTN6_FN, PTN5_FN, PTN4_FN, + PTN6_FN, PTN5_FN, PTN4_FN, PTN3_FN, PTN2_FN, PTN1_FN, PTN0_FN, PTO7_FN, PTO6_FN, PTO5_FN, PTO4_FN, PTO3_FN, PTO2_FN, PTO1_FN, PTO0_FN, - PTP6_FN, PTP5_FN, PTP4_FN, + PTP7_FN, PTP6_FN, PTP5_FN, PTP4_FN, PTP3_FN, PTP2_FN, PTP1_FN, PTP0_FN, - PTQ6_FN, PTQ5_FN, PTQ4_FN, + PTQ6_FN, PTQ5_FN, PTQ4_FN, PTQ3_FN, PTQ2_FN, PTQ1_FN, PTQ0_FN, PTR7_FN, PTR6_FN, PTR5_FN, PTR4_FN, PTR3_FN, PTR2_FN, PTR1_FN, PTR0_FN, PTS7_FN, PTS6_FN, PTS5_FN, PTS4_FN, PTS3_FN, PTS2_FN, PTS1_FN, PTS0_FN, - PTT5_FN, PTT4_FN, + PTT7_FN, PTT6_FN, PTT5_FN, PTT4_FN, PTT3_FN, PTT2_FN, PTT1_FN, PTT0_FN, PTU7_FN, PTU6_FN, PTU5_FN, PTU4_FN, PTU3_FN, PTU2_FN, PTU1_FN, PTU0_FN, @@ -253,181 +280,248 @@ enum { PTZ7_FN, PTZ6_FN, PTZ5_FN, PTZ4_FN, PTZ3_FN, PTZ2_FN, PTZ1_FN, PTZ0_FN, - PS0_15_FN1, PS0_15_FN3, - PS0_14_FN1, PS0_14_FN3, - PS0_13_FN1, PS0_13_FN3, - PS0_12_FN1, PS0_12_FN3, + PS0_15_FN1, PS0_15_FN2, + PS0_14_FN1, PS0_14_FN2, + PS0_13_FN1, PS0_13_FN2, + PS0_12_FN1, PS0_12_FN2, + PS0_11_FN1, PS0_11_FN2, + PS0_10_FN1, PS0_10_FN2, + PS0_9_FN1, PS0_9_FN2, + PS0_8_FN1, PS0_8_FN2, PS0_7_FN1, PS0_7_FN2, PS0_6_FN1, PS0_6_FN2, PS0_5_FN1, PS0_5_FN2, PS0_4_FN1, PS0_4_FN2, PS0_3_FN1, PS0_3_FN2, PS0_2_FN1, PS0_2_FN2, - PS0_1_FN1, PS0_1_FN2, - PS1_7_FN1, PS1_7_FN3, - PS1_6_FN1, PS1_6_FN3, + PS1_10_FN1, PS1_10_FN2, + PS1_9_FN1, PS1_9_FN2, + PS1_8_FN1, PS1_8_FN2, + PS1_2_FN1, PS1_2_FN2, + + PS2_13_FN1, PS2_13_FN2, + PS2_12_FN1, PS2_12_FN2, + PS2_7_FN1, PS2_7_FN2, + PS2_6_FN1, PS2_6_FN2, + PS2_5_FN1, PS2_5_FN2, + PS2_4_FN1, PS2_4_FN2, + PS2_2_FN1, PS2_2_FN2, + + PS3_15_FN1, PS3_15_FN2, + PS3_14_FN1, PS3_14_FN2, + PS3_13_FN1, PS3_13_FN2, + PS3_12_FN1, PS3_12_FN2, + PS3_11_FN1, PS3_11_FN2, + PS3_10_FN1, PS3_10_FN2, + PS3_9_FN1, PS3_9_FN2, + PS3_8_FN1, PS3_8_FN2, + PS3_7_FN1, PS3_7_FN2, + PS3_2_FN1, PS3_2_FN2, + PS3_1_FN1, PS3_1_FN2, - PS2_13_FN1, PS2_13_FN3, - PS2_12_FN1, PS2_12_FN3, - PS2_1_FN1, PS2_1_FN2, - PS2_0_FN1, PS2_0_FN2, - - PS4_15_FN1, PS4_15_FN2, PS4_14_FN1, PS4_14_FN2, PS4_13_FN1, PS4_13_FN2, PS4_12_FN1, PS4_12_FN2, - PS4_11_FN1, PS4_11_FN2, PS4_10_FN1, PS4_10_FN2, PS4_9_FN1, PS4_9_FN2, + PS4_8_FN1, PS4_8_FN2, + PS4_4_FN1, PS4_4_FN2, PS4_3_FN1, PS4_3_FN2, PS4_2_FN1, PS4_2_FN2, PS4_1_FN1, PS4_1_FN2, PS4_0_FN1, PS4_0_FN2, + PS5_11_FN1, PS5_11_FN2, + PS5_10_FN1, PS5_10_FN2, PS5_9_FN1, PS5_9_FN2, PS5_8_FN1, PS5_8_FN2, PS5_7_FN1, PS5_7_FN2, PS5_6_FN1, PS5_6_FN2, PS5_5_FN1, PS5_5_FN2, PS5_4_FN1, PS5_4_FN2, - - /* AN15 to 8 : EVENT15 to 8 */ - PS6_7_FN_AN, PS6_7_FN_EV, - PS6_6_FN_AN, PS6_6_FN_EV, - PS6_5_FN_AN, PS6_5_FN_EV, - PS6_4_FN_AN, PS6_4_FN_EV, - PS6_3_FN_AN, PS6_3_FN_EV, - PS6_2_FN_AN, PS6_2_FN_EV, - PS6_1_FN_AN, PS6_1_FN_EV, - PS6_0_FN_AN, PS6_0_FN_EV, - + PS5_3_FN1, PS5_3_FN2, + PS5_2_FN1, PS5_2_FN2, + + PS6_15_FN1, PS6_15_FN2, + PS6_14_FN1, PS6_14_FN2, + PS6_13_FN1, PS6_13_FN2, + PS6_12_FN1, PS6_12_FN2, + PS6_11_FN1, PS6_11_FN2, + PS6_10_FN1, PS6_10_FN2, + PS6_9_FN1, PS6_9_FN2, + PS6_8_FN1, PS6_8_FN2, + PS6_7_FN1, PS6_7_FN2, + PS6_6_FN1, PS6_6_FN2, + PS6_5_FN1, PS6_5_FN2, + PS6_4_FN1, PS6_4_FN2, + PS6_3_FN1, PS6_3_FN2, + PS6_2_FN1, PS6_2_FN2, + PS6_1_FN1, PS6_1_FN2, + PS6_0_FN1, PS6_0_FN2, + + PS7_15_FN1, PS7_15_FN2, + PS7_14_FN1, PS7_14_FN2, + PS7_13_FN1, PS7_13_FN2, + PS7_12_FN1, PS7_12_FN2, + PS7_11_FN1, PS7_11_FN2, + PS7_10_FN1, PS7_10_FN2, + PS7_9_FN1, PS7_9_FN2, + PS7_8_FN1, PS7_8_FN2, + PS7_7_FN1, PS7_7_FN2, + PS7_6_FN1, PS7_6_FN2, + PS7_5_FN1, PS7_5_FN2, + PS7_4_FN1, PS7_4_FN2, + + PS8_15_FN1, PS8_15_FN2, + PS8_14_FN1, PS8_14_FN2, + PS8_13_FN1, PS8_13_FN2, + PS8_12_FN1, PS8_12_FN2, + PS8_11_FN1, PS8_11_FN2, + PS8_10_FN1, PS8_10_FN2, + PS8_9_FN1, PS8_9_FN2, + PS8_8_FN1, PS8_8_FN2, PINMUX_FUNCTION_END, PINMUX_MARK_BEGIN, - /* PTA (mobule: LBSC, CPG, LPC) */ + /* PTA (mobule: LBSC, RGMII) */ BS_MARK, RDWR_MARK, WE1_MARK, RDY_MARK, - MD10_MARK, MD9_MARK, MD8_MARK, - LGPIO7_MARK, LGPIO6_MARK, LGPIO5_MARK, LGPIO4_MARK, - LGPIO3_MARK, LGPIO2_MARK, LGPIO1_MARK, LGPIO0_MARK, - - /* PTB (mobule: LBSC, EtherC, SIM, LPC) */ - D15_MARK, D14_MARK, D13_MARK, D12_MARK, - D11_MARK, D10_MARK, D9_MARK, D8_MARK, ET0_MDC_MARK, ET0_MDIO_MARK, ET1_MDC_MARK, ET1_MDIO_MARK, - SIM_D_MARK, SIM_CLK_MARK, SIM_RST_MARK, - WPSZ1_MARK, WPSZ0_MARK, FWID_MARK, FLSHSZ_MARK, - LPC_SPIEN_MARK, BASEL_MARK, - /* PTC (mobule: SD) */ - SD_WP_MARK, SD_CD_MARK, SD_CLK_MARK, SD_CMD_MARK, - SD_D3_MARK, SD_D2_MARK, SD_D1_MARK, SD_D0_MARK, + /* PTB (mobule: INTC, ONFI, TMU) */ + IRQ15_MARK, IRQ14_MARK, IRQ13_MARK, IRQ12_MARK, + IRQ11_MARK, IRQ10_MARK, IRQ9_MARK, IRQ8_MARK, + ON_NRE_MARK, ON_NWE_MARK, ON_NWP_MARK, ON_NCE0_MARK, + ON_R_B0_MARK, ON_ALE_MARK, ON_CLE_MARK, TCLK_MARK, - /* PTD (mobule: INTC, SPI0, LBSC, CPG, ADC) */ + /* PTC (mobule: IRQ, PWMU) */ IRQ7_MARK, IRQ6_MARK, IRQ5_MARK, IRQ4_MARK, IRQ3_MARK, IRQ2_MARK, IRQ1_MARK, IRQ0_MARK, - MD6_MARK, MD5_MARK, MD3_MARK, MD2_MARK, - MD1_MARK, MD0_MARK, ADTRG1_MARK, ADTRG0_MARK, - - /* PTE (mobule: EtherC) */ - ET0_CRS_DV_MARK, ET0_TXD1_MARK, - ET0_TXD0_MARK, ET0_TX_EN_MARK, - ET0_REF_CLK_MARK, ET0_RXD1_MARK, - ET0_RXD0_MARK, ET0_RX_ER_MARK, - - /* PTF (mobule: EtherC) */ - ET1_CRS_DV_MARK, ET1_TXD1_MARK, - ET1_TXD0_MARK, ET1_TX_EN_MARK, - ET1_REF_CLK_MARK, ET1_RXD1_MARK, - ET1_RXD0_MARK, ET1_RX_ER_MARK, - - /* PTG (mobule: SYSTEM, PWMX, LPC) */ - STATUS0_MARK, STATUS1_MARK, - PWX0_MARK, PWX1_MARK, PWX2_MARK, PWX3_MARK, - SERIRQ_MARK, CLKRUN_MARK, LPCPD_MARK, LDRQ_MARK, - - /* PTH (mobule: TMU, SCIF234, SPI1, SPI0) */ - TCLK_MARK, RXD4_MARK, TXD4_MARK, + PWMU0_MARK, PWMU1_MARK, PWMU2_MARK, PWMU3_MARK, + PWMU4_MARK, PWMU5_MARK, + + /* PTD (mobule: SPI0, DMAC) */ + SP0_MOSI_MARK, SP0_MISO_MARK, SP0_SCK_MARK, SP0_SCK_FB_MARK, + SP0_SS0_MARK, SP0_SS1_MARK, SP0_SS2_MARK, SP0_SS3_MARK, + DREQ0_MARK, DACK0_MARK, TEND0_MARK, + + /* PTE (mobule: RMII) */ + RMII0_CRS_DV_MARK, RMII0_TXD1_MARK, + RMII0_TXD0_MARK, RMII0_TXEN_MARK, + RMII0_REFCLK_MARK, RMII0_RXD1_MARK, + RMII0_RXD0_MARK, RMII0_RX_ER_MARK, + + /* PTF (mobule: RMII, SerMux) */ + RMII1_CRS_DV_MARK, RMII1_TXD1_MARK, + RMII1_TXD0_MARK, RMII1_TXEN_MARK, + RMII1_REFCLK_MARK, RMII1_RXD1_MARK, + RMII1_RXD0_MARK, RMII1_RX_ER_MARK, + RAC_RI_MARK, + + /* PTG (mobule: system, LBSC, LPC, WDT, LPC, eMMC) */ + BOOTFMS_MARK, BOOTWP_MARK, A25_MARK, A24_MARK, + SERIRQ_MARK, WDTOVF_MARK, LPCPD_MARK, LDRQ_MARK, + MMCCLK_MARK, MMCCMD_MARK, + + /* PTH (mobule: SPI1, LPC, DMAC, ADC) */ SP1_MOSI_MARK, SP1_MISO_MARK, SP1_SCK_MARK, SP1_SCK_FB_MARK, - SP1_SS0_MARK, SP1_SS1_MARK, SP0_SS1_MARK, + SP1_SS0_MARK, SP1_SS1_MARK, WP_MARK, FMS0_MARK, + TEND1_MARK, DREQ1_MARK, DACK1_MARK, ADTRG1_MARK, + ADTRG0_MARK, - /* PTI (mobule: INTC) */ - IRQ15_MARK, IRQ14_MARK, IRQ13_MARK, IRQ12_MARK, - IRQ11_MARK, IRQ10_MARK, IRQ9_MARK, IRQ8_MARK, + /* PTI (mobule: LBSC, SDHI) */ + D15_MARK, D14_MARK, D13_MARK, D12_MARK, + D11_MARK, D10_MARK, D9_MARK, D8_MARK, + SD_WP_MARK, SD_CD_MARK, SD_CLK_MARK, SD_CMD_MARK, + SD_D3_MARK, SD_D2_MARK, SD_D1_MARK, SD_D0_MARK, - /* PTJ (mobule: SCIF234, SERMUX) */ - RXD3_MARK, TXD3_MARK, RXD2_MARK, TXD2_MARK, - COM1_TXD_MARK, COM1_RXD_MARK, COM1_RTS_MARK, COM1_CTS_MARK, + /* PTJ (mobule: SCIF234) */ + RTS3_MARK, CTS3_MARK, TXD3_MARK, RXD3_MARK, + RTS4_MARK, RXD4_MARK, TXD4_MARK, - /* PTK (mobule: SERMUX) */ + /* PTK (mobule: SERMUX, LBSC, SCIF) */ COM2_TXD_MARK, COM2_RXD_MARK, COM2_RTS_MARK, COM2_CTS_MARK, - COM2_DTR_MARK, COM2_DSR_MARK, COM2_DCD_MARK, COM2_RI_MARK, + COM2_DTR_MARK, COM2_DSR_MARK, COM2_DCD_MARK, CLKOUT_MARK, + SCK2_MARK, SCK4_MARK, SCK3_MARK, - /* PTL (mobule: SERMUX) */ - RAC_TXD_MARK, RAC_RXD_MARK, RAC_RTS_MARK, RAC_CTS_MARK, - RAC_DTR_MARK, RAC_DSR_MARK, RAC_DCD_MARK, RAC_RI_MARK, + /* PTL (mobule: SERMUX, SCIF, LBSC, AUD) */ + RAC_RXD_MARK, RAC_RTS_MARK, RAC_CTS_MARK, RAC_DTR_MARK, + RAC_DSR_MARK, RAC_DCD_MARK, RAC_TXD_MARK, RXD2_MARK, + CS5_MARK, CS6_MARK, AUDSYNC_MARK, AUDCK_MARK, + TXD2_MARK, - /* PTM (mobule: IIC, LPC) */ + /* PTM (mobule: LBSC, IIC) */ + CS4_MARK, RD_MARK, WE0_MARK, CS0_MARK, SDA6_MARK, SCL6_MARK, SDA7_MARK, SCL7_MARK, - WP_MARK, FMS0_MARK, FMS1_MARK, - /* PTN (mobule: SCIF234, EVC) */ - SCK2_MARK, RTS4_MARK, RTS3_MARK, RTS2_MARK, - CTS4_MARK, CTS3_MARK, CTS2_MARK, - EVENT7_MARK, EVENT6_MARK, EVENT5_MARK, EVENT4_MARK, - EVENT3_MARK, EVENT2_MARK, EVENT1_MARK, EVENT0_MARK, + /* PTN (mobule: USB, JMC, SGPIO, WDT) */ + VBUS_EN_MARK, VBUS_OC_MARK, JMCTCK_MARK, JMCTMS_MARK, + JMCTDO_MARK, JMCTDI_MARK, JMCTRST_MARK, + SGPIO1_CLK_MARK, SGPIO1_LOAD_MARK, SGPIO1_DI_MARK, + SGPIO1_DO_MARK, SUB_CLKIN_MARK, - /* PTO (mobule: SGPIO) */ - SGPIO0_CLK_MARK, SGPIO0_LOAD_MARK, - SGPIO0_DI_MARK, SGPIO0_DO_MARK, - SGPIO1_CLK_MARK, SGPIO1_LOAD_MARK, - SGPIO1_DI_MARK, SGPIO1_DO_MARK, - - /* PTP (mobule: JMC, SCIF234) */ - JMCTCK_MARK, JMCTMS_MARK, JMCTDO_MARK, JMCTDI_MARK, - JMCRST_MARK, SCK4_MARK, SCK3_MARK, + /* PTO (mobule: SGPIO, SerMux) */ + SGPIO0_CLK_MARK, SGPIO0_LOAD_MARK, SGPIO0_DI_MARK, + SGPIO0_DO_MARK, SGPIO2_CLK_MARK, SGPIO2_LOAD_MARK, + SGPIO2_DI_MARK, SGPIO2_DO_MARK, + COM1_TXD_MARK, COM1_RXD_MARK, COM1_RTS_MARK, COM1_CTS_MARK, /* PTQ (mobule: LPC) */ LAD3_MARK, LAD2_MARK, LAD1_MARK, LAD0_MARK, LFRAME_MARK, LRESET_MARK, LCLK_MARK, /* PTR (mobule: GRA, IIC) */ - DDC3_MARK, DDC2_MARK, - SDA8_MARK, SCL8_MARK, SDA2_MARK, SCL2_MARK, + DDC3_MARK, DDC2_MARK, SDA2_MARK, SCL2_MARK, SDA1_MARK, SCL1_MARK, SDA0_MARK, SCL0_MARK, + SDA8_MARK, SCL8_MARK, /* PTS (mobule: GRA, IIC) */ - DDC1_MARK, DDC0_MARK, - SDA9_MARK, SCL9_MARK, SDA5_MARK, SCL5_MARK, + DDC1_MARK, DDC0_MARK, SDA5_MARK, SCL5_MARK, SDA4_MARK, SCL4_MARK, SDA3_MARK, SCL3_MARK, + SDA9_MARK, SCL9_MARK, - /* PTT (mobule: SYSTEM, PWMX) */ - AUDSYNC_MARK, AUDCK_MARK, - AUDATA3_MARK, AUDATA2_MARK, - AUDATA1_MARK, AUDATA0_MARK, - PWX7_MARK, PWX6_MARK, PWX5_MARK, PWX4_MARK, + /* PTT (mobule: PWMX, AUD) */ + PWMX7_MARK, PWMX6_MARK, PWMX5_MARK, PWMX4_MARK, + PWMX3_MARK, PWMX2_MARK, PWMX1_MARK, PWMX0_MARK, + AUDATA3_MARK, AUDATA2_MARK, AUDATA1_MARK, AUDATA0_MARK, + STATUS1_MARK, STATUS0_MARK, - /* PTU (mobule: LBSC, DMAC) */ - CS6_MARK, CS5_MARK, CS4_MARK, CS0_MARK, - RD_MARK, WE0_MARK, A25_MARK, A24_MARK, - DREQ0_MARK, DACK0_MARK, + /* PTU (mobule: LPC, APM) */ + LGPIO7_MARK, LGPIO6_MARK, LGPIO5_MARK, LGPIO4_MARK, + LGPIO3_MARK, LGPIO2_MARK, LGPIO1_MARK, LGPIO0_MARK, + APMONCTL_O_MARK, APMPWBTOUT_O_MARK, APMSCI_O_MARK, + APMVDDON_MARK, APMSLPBTN_MARK, APMPWRBTN_MARK, APMS5N_MARK, + APMS3N_MARK, - /* PTV (mobule: LBSC, DMAC) */ + /* PTV (mobule: LBSC, SerMux, R-SPI, EVC, GRA) */ A23_MARK, A22_MARK, A21_MARK, A20_MARK, A19_MARK, A18_MARK, A17_MARK, A16_MARK, - TEND0_MARK, DREQ1_MARK, DACK1_MARK, TEND1_MARK, + COM2_RI_MARK, R_SPI_MOSI_MARK, R_SPI_MISO_MARK, + R_SPI_RSPCK_MARK, R_SPI_SSL0_MARK, R_SPI_SSL1_MARK, + EVENT7_MARK, EVENT6_MARK, VBIOS_DI_MARK, VBIOS_DO_MARK, + VBIOS_CLK_MARK, VBIOS_CS_MARK, - /* PTW (mobule: LBSC) */ + /* PTW (mobule: LBSC, EVC, SCIF) */ A15_MARK, A14_MARK, A13_MARK, A12_MARK, A11_MARK, A10_MARK, A9_MARK, A8_MARK, + EVENT5_MARK, EVENT4_MARK, EVENT3_MARK, EVENT2_MARK, + EVENT1_MARK, EVENT0_MARK, CTS4_MARK, CTS2_MARK, - /* PTX (mobule: LBSC) */ + /* PTX (mobule: LBSC, SCIF, SIM) */ A7_MARK, A6_MARK, A5_MARK, A4_MARK, A3_MARK, A2_MARK, A1_MARK, A0_MARK, + RTS2_MARK, SIM_D_MARK, SIM_CLK_MARK, SIM_RST_MARK, /* PTY (mobule: LBSC) */ D7_MARK, D6_MARK, D5_MARK, D4_MARK, D3_MARK, D2_MARK, D1_MARK, D0_MARK, + + /* PTZ (mobule: eMMC, ONFI) */ + MMCDAT7_MARK, MMCDAT6_MARK, MMCDAT5_MARK, MMCDAT4_MARK, + MMCDAT3_MARK, MMCDAT2_MARK, MMCDAT1_MARK, MMCDAT0_MARK, + ON_DQ7_MARK, ON_DQ6_MARK, ON_DQ5_MARK, ON_DQ4_MARK, + ON_DQ3_MARK, ON_DQ2_MARK, ON_DQ1_MARK, ON_DQ0_MARK, + PINMUX_MARK_END, }; @@ -473,6 +567,8 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(PTD0_DATA, PTD0_IN, PTD0_OUT), /* PTE GPIO */ + PINMUX_DATA(PTE7_DATA, PTE7_IN, PTE7_OUT), + PINMUX_DATA(PTE6_DATA, PTE6_IN, PTE6_OUT), PINMUX_DATA(PTE5_DATA, PTE5_IN, PTE5_OUT), PINMUX_DATA(PTE4_DATA, PTE4_IN, PTE4_OUT), PINMUX_DATA(PTE3_DATA, PTE3_IN, PTE3_OUT), @@ -521,7 +617,6 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(PTI0_DATA, PTI0_IN, PTI0_OUT), /* PTJ GPIO */ - PINMUX_DATA(PTJ7_DATA, PTJ7_IN, PTJ7_OUT), PINMUX_DATA(PTJ6_DATA, PTJ6_IN, PTJ6_OUT), PINMUX_DATA(PTJ5_DATA, PTJ5_IN, PTJ5_OUT), PINMUX_DATA(PTJ4_DATA, PTJ4_IN, PTJ4_OUT), @@ -541,7 +636,6 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(PTK0_DATA, PTK0_IN, PTK0_OUT), /* PTL GPIO */ - PINMUX_DATA(PTL7_DATA, PTL7_IN, PTL7_OUT), PINMUX_DATA(PTL6_DATA, PTL6_IN, PTL6_OUT), PINMUX_DATA(PTL5_DATA, PTL5_IN, PTL5_OUT), PINMUX_DATA(PTL4_DATA, PTL4_IN, PTL4_OUT), @@ -560,7 +654,6 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(PTM0_DATA, PTM0_IN, PTM0_OUT), /* PTN GPIO */ - PINMUX_DATA(PTN7_DATA, PTN7_IN, PTN7_OUT), PINMUX_DATA(PTN6_DATA, PTN6_IN, PTN6_OUT), PINMUX_DATA(PTN5_DATA, PTN5_IN, PTN5_OUT), PINMUX_DATA(PTN4_DATA, PTN4_IN, PTN4_OUT), @@ -609,6 +702,8 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(PTS0_DATA, PTS0_IN, PTS0_OUT), /* PTT GPIO */ + PINMUX_DATA(PTT7_DATA, PTT7_IN, PTT7_OUT), + PINMUX_DATA(PTT6_DATA, PTT6_IN, PTT6_OUT), PINMUX_DATA(PTT5_DATA, PTT5_IN, PTT5_OUT), PINMUX_DATA(PTT4_DATA, PTT4_IN, PTT4_OUT), PINMUX_DATA(PTT3_DATA, PTT3_IN, PTT3_OUT), @@ -677,186 +772,204 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(PTZ0_DATA, PTZ0_IN, PTZ0_OUT), /* PTA FN */ - PINMUX_DATA(BS_MARK, PS0_15_FN1, PTA7_FN), - PINMUX_DATA(LGPIO7_MARK, PS0_15_FN3, PTA7_FN), - PINMUX_DATA(RDWR_MARK, PS0_14_FN1, PTA6_FN), - PINMUX_DATA(LGPIO6_MARK, PS0_14_FN3, PTA6_FN), - PINMUX_DATA(WE1_MARK, PS0_13_FN1, PTA5_FN), - PINMUX_DATA(LGPIO5_MARK, PS0_13_FN3, PTA5_FN), - PINMUX_DATA(RDY_MARK, PS0_12_FN1, PTA4_FN), - PINMUX_DATA(LGPIO4_MARK, PS0_12_FN3, PTA4_FN), - PINMUX_DATA(LGPIO3_MARK, PTA3_FN), - PINMUX_DATA(LGPIO2_MARK, PTA2_FN), - PINMUX_DATA(LGPIO1_MARK, PTA1_FN), - PINMUX_DATA(LGPIO0_MARK, PTA0_FN), + PINMUX_DATA(BS_MARK, PTA7_FN), + PINMUX_DATA(RDWR_MARK, PTA6_FN), + PINMUX_DATA(WE1_MARK, PTA5_FN), + PINMUX_DATA(RDY_MARK, PTA4_FN), + PINMUX_DATA(ET0_MDC_MARK, PTA3_FN), + PINMUX_DATA(ET0_MDIO_MARK, PTA2_FN), + PINMUX_DATA(ET1_MDC_MARK, PTA1_FN), + PINMUX_DATA(ET1_MDIO_MARK, PTA0_FN), /* PTB FN */ - PINMUX_DATA(D15_MARK, PS0_7_FN1, PTB7_FN), - PINMUX_DATA(ET0_MDC_MARK, PS0_7_FN2, PTB7_FN), - PINMUX_DATA(D14_MARK, PS0_6_FN1, PTB6_FN), - PINMUX_DATA(ET0_MDIO_MARK, PS0_6_FN2, PTB6_FN), - PINMUX_DATA(D13_MARK, PS0_5_FN1, PTB5_FN), - PINMUX_DATA(ET1_MDC_MARK, PS0_5_FN2, PTB5_FN), - PINMUX_DATA(D12_MARK, PS0_4_FN1, PTB4_FN), - PINMUX_DATA(ET1_MDIO_MARK, PS0_4_FN2, PTB4_FN), - PINMUX_DATA(D11_MARK, PS0_3_FN1, PTB3_FN), - PINMUX_DATA(SIM_D_MARK, PS0_3_FN2, PTB3_FN), - PINMUX_DATA(D10_MARK, PS0_2_FN1, PTB2_FN), - PINMUX_DATA(SIM_CLK_MARK, PS0_2_FN2, PTB2_FN), - PINMUX_DATA(D9_MARK, PS0_1_FN1, PTB1_FN), - PINMUX_DATA(SIM_RST_MARK, PS0_1_FN2, PTB1_FN), - PINMUX_DATA(D8_MARK, PTB0_FN), + PINMUX_DATA(IRQ15_MARK, PS0_15_FN1, PTB7_FN), + PINMUX_DATA(ON_NRE_MARK, PS0_15_FN2, PTB7_FN), + PINMUX_DATA(IRQ14_MARK, PS0_14_FN1, PTB6_FN), + PINMUX_DATA(ON_NWE_MARK, PS0_14_FN2, PTB6_FN), + PINMUX_DATA(IRQ13_MARK, PS0_13_FN1, PTB5_FN), + PINMUX_DATA(ON_NWP_MARK, PS0_13_FN2, PTB5_FN), + PINMUX_DATA(IRQ12_MARK, PS0_12_FN1, PTB4_FN), + PINMUX_DATA(ON_NCE0_MARK, PS0_12_FN2, PTB4_FN), + PINMUX_DATA(IRQ11_MARK, PS0_11_FN1, PTB3_FN), + PINMUX_DATA(ON_R_B0_MARK, PS0_11_FN2, PTB3_FN), + PINMUX_DATA(IRQ10_MARK, PS0_10_FN1, PTB2_FN), + PINMUX_DATA(ON_ALE_MARK, PS0_10_FN2, PTB2_FN), + PINMUX_DATA(IRQ9_MARK, PS0_9_FN1, PTB1_FN), + PINMUX_DATA(ON_CLE_MARK, PS0_9_FN2, PTB1_FN), + PINMUX_DATA(IRQ8_MARK, PS0_8_FN1, PTB0_FN), + PINMUX_DATA(TCLK_MARK, PS0_8_FN2, PTB0_FN), /* PTC FN */ - PINMUX_DATA(SD_WP_MARK, PTC7_FN), - PINMUX_DATA(SD_CD_MARK, PTC6_FN), - PINMUX_DATA(SD_CLK_MARK, PTC5_FN), - PINMUX_DATA(SD_CMD_MARK, PTC4_FN), - PINMUX_DATA(SD_D3_MARK, PTC3_FN), - PINMUX_DATA(SD_D2_MARK, PTC2_FN), - PINMUX_DATA(SD_D1_MARK, PTC1_FN), - PINMUX_DATA(SD_D0_MARK, PTC0_FN), + PINMUX_DATA(IRQ7_MARK, PS0_7_FN1, PTC7_FN), + PINMUX_DATA(PWMU0_MARK, PS0_7_FN2, PTC7_FN), + PINMUX_DATA(IRQ6_MARK, PS0_6_FN1, PTC6_FN), + PINMUX_DATA(PWMU1_MARK, PS0_6_FN2, PTC6_FN), + PINMUX_DATA(IRQ5_MARK, PS0_5_FN1, PTC5_FN), + PINMUX_DATA(PWMU2_MARK, PS0_5_FN2, PTC5_FN), + PINMUX_DATA(IRQ4_MARK, PS0_4_FN1, PTC5_FN), + PINMUX_DATA(PWMU3_MARK, PS0_4_FN2, PTC4_FN), + PINMUX_DATA(IRQ3_MARK, PS0_3_FN1, PTC3_FN), + PINMUX_DATA(PWMU4_MARK, PS0_3_FN2, PTC3_FN), + PINMUX_DATA(IRQ2_MARK, PS0_2_FN1, PTC2_FN), + PINMUX_DATA(PWMU5_MARK, PS0_2_FN2, PTC2_FN), + PINMUX_DATA(IRQ1_MARK, PTC1_FN), + PINMUX_DATA(IRQ0_MARK, PTC0_FN), /* PTD FN */ - PINMUX_DATA(IRQ7_MARK, PS1_7_FN1, PTD7_FN), - PINMUX_DATA(ADTRG1_MARK, PS1_7_FN3, PTD7_FN), - PINMUX_DATA(IRQ6_MARK, PS1_6_FN1, PTD6_FN), - PINMUX_DATA(ADTRG0_MARK, PS1_6_FN3, PTD6_FN), - PINMUX_DATA(IRQ5_MARK, PTD5_FN), - PINMUX_DATA(IRQ4_MARK, PTD4_FN), - PINMUX_DATA(IRQ3_MARK, PTD3_FN), - PINMUX_DATA(IRQ2_MARK, PTD2_FN), - PINMUX_DATA(IRQ1_MARK, PTD1_FN), - PINMUX_DATA(IRQ0_MARK, PTD0_FN), + PINMUX_DATA(SP0_MOSI_MARK, PTD7_FN), + PINMUX_DATA(SP0_MISO_MARK, PTD6_FN), + PINMUX_DATA(SP0_SCK_MARK, PTD5_FN), + PINMUX_DATA(SP0_SCK_FB_MARK, PTD4_FN), + PINMUX_DATA(SP0_SS0_MARK, PTD3_FN), + PINMUX_DATA(SP0_SS1_MARK, PS1_10_FN1, PTD2_FN), + PINMUX_DATA(DREQ0_MARK, PS1_10_FN2, PTD2_FN), + PINMUX_DATA(SP0_SS2_MARK, PS1_9_FN1, PTD1_FN), + PINMUX_DATA(DACK0_MARK, PS1_9_FN2, PTD1_FN), + PINMUX_DATA(SP0_SS3_MARK, PS1_8_FN1, PTD0_FN), + PINMUX_DATA(TEND0_MARK, PS1_8_FN2, PTD0_FN), /* PTE FN */ - PINMUX_DATA(ET0_CRS_DV_MARK, PTE7_FN), - PINMUX_DATA(ET0_TXD1_MARK, PTE6_FN), - PINMUX_DATA(ET0_TXD0_MARK, PTE5_FN), - PINMUX_DATA(ET0_TX_EN_MARK, PTE4_FN), - PINMUX_DATA(ET0_REF_CLK_MARK, PTE3_FN), - PINMUX_DATA(ET0_RXD1_MARK, PTE2_FN), - PINMUX_DATA(ET0_RXD0_MARK, PTE1_FN), - PINMUX_DATA(ET0_RX_ER_MARK, PTE0_FN), + PINMUX_DATA(RMII0_CRS_DV_MARK, PTE7_FN), + PINMUX_DATA(RMII0_TXD1_MARK, PTE6_FN), + PINMUX_DATA(RMII0_TXD0_MARK, PTE5_FN), + PINMUX_DATA(RMII0_TXEN_MARK, PTE4_FN), + PINMUX_DATA(RMII0_REFCLK_MARK, PTE3_FN), + PINMUX_DATA(RMII0_RXD1_MARK, PTE2_FN), + PINMUX_DATA(RMII0_RXD0_MARK, PTE1_FN), + PINMUX_DATA(RMII0_RX_ER_MARK, PTE0_FN), /* PTF FN */ - PINMUX_DATA(ET1_CRS_DV_MARK, PTF7_FN), - PINMUX_DATA(ET1_TXD1_MARK, PTF6_FN), - PINMUX_DATA(ET1_TXD0_MARK, PTF5_FN), - PINMUX_DATA(ET1_TX_EN_MARK, PTF4_FN), - PINMUX_DATA(ET1_REF_CLK_MARK, PTF3_FN), - PINMUX_DATA(ET1_RXD1_MARK, PTF2_FN), - PINMUX_DATA(ET1_RXD0_MARK, PTF1_FN), - PINMUX_DATA(ET1_RX_ER_MARK, PTF0_FN), + PINMUX_DATA(RMII1_CRS_DV_MARK, PTF7_FN), + PINMUX_DATA(RMII1_TXD1_MARK, PTF6_FN), + PINMUX_DATA(RMII1_TXD0_MARK, PTF5_FN), + PINMUX_DATA(RMII1_TXEN_MARK, PTF4_FN), + PINMUX_DATA(RMII1_REFCLK_MARK, PTF3_FN), + PINMUX_DATA(RMII1_RXD1_MARK, PS1_2_FN1, PTF2_FN), + PINMUX_DATA(RAC_RI_MARK, PS1_2_FN2, PTF2_FN), + PINMUX_DATA(RMII1_RXD0_MARK, PTF1_FN), + PINMUX_DATA(RMII1_RX_ER_MARK, PTF0_FN), /* PTG FN */ - PINMUX_DATA(PWX0_MARK, PTG7_FN), - PINMUX_DATA(PWX1_MARK, PTG6_FN), - PINMUX_DATA(STATUS0_MARK, PS2_13_FN1, PTG5_FN), - PINMUX_DATA(PWX2_MARK, PS2_13_FN3, PTG5_FN), - PINMUX_DATA(STATUS1_MARK, PS2_12_FN1, PTG4_FN), - PINMUX_DATA(PWX3_MARK, PS2_12_FN3, PTG4_FN), + PINMUX_DATA(BOOTFMS_MARK, PTG7_FN), + PINMUX_DATA(BOOTWP_MARK, PTG6_FN), + PINMUX_DATA(A25_MARK, PS2_13_FN1, PTG5_FN), + PINMUX_DATA(MMCCLK_MARK, PS2_13_FN2, PTG5_FN), + PINMUX_DATA(A24_MARK, PS2_12_FN1, PTG4_FN), + PINMUX_DATA(MMCCMD_MARK, PS2_12_FN2, PTG4_FN), PINMUX_DATA(SERIRQ_MARK, PTG3_FN), - PINMUX_DATA(CLKRUN_MARK, PTG2_FN), + PINMUX_DATA(WDTOVF_MARK, PTG2_FN), PINMUX_DATA(LPCPD_MARK, PTG1_FN), PINMUX_DATA(LDRQ_MARK, PTG0_FN), /* PTH FN */ - PINMUX_DATA(SP1_MOSI_MARK, PTH7_FN), - PINMUX_DATA(SP1_MISO_MARK, PTH6_FN), - PINMUX_DATA(SP1_SCK_MARK, PTH5_FN), - PINMUX_DATA(SP1_SCK_FB_MARK, PTH4_FN), + PINMUX_DATA(SP1_MOSI_MARK, PS2_7_FN1, PTH7_FN), + PINMUX_DATA(TEND1_MARK, PS2_7_FN2, PTH7_FN), + PINMUX_DATA(SP1_MISO_MARK, PS2_6_FN1, PTH6_FN), + PINMUX_DATA(DREQ1_MARK, PS2_6_FN2, PTH6_FN), + PINMUX_DATA(SP1_SCK_MARK, PS2_5_FN1, PTH5_FN), + PINMUX_DATA(DACK1_MARK, PS2_5_FN2, PTH5_FN), + PINMUX_DATA(SP1_SCK_FB_MARK, PS2_4_FN1, PTH4_FN), + PINMUX_DATA(ADTRG1_MARK, PS2_4_FN2, PTH4_FN), PINMUX_DATA(SP1_SS0_MARK, PTH3_FN), - PINMUX_DATA(TCLK_MARK, PTH2_FN), - PINMUX_DATA(RXD4_MARK, PS2_1_FN1, PTH1_FN), - PINMUX_DATA(SP1_SS1_MARK, PS2_1_FN2, PTH1_FN), - PINMUX_DATA(TXD4_MARK, PS2_0_FN1, PTH0_FN), - PINMUX_DATA(SP0_SS1_MARK, PS2_0_FN2, PTH0_FN), + PINMUX_DATA(SP1_SS1_MARK, PS2_2_FN1, PTH2_FN), + PINMUX_DATA(ADTRG0_MARK, PS2_2_FN2, PTH2_FN), + PINMUX_DATA(WP_MARK, PTH1_FN), + PINMUX_DATA(FMS0_MARK, PTH0_FN), /* PTI FN */ - PINMUX_DATA(IRQ15_MARK, PTI7_FN), - PINMUX_DATA(IRQ14_MARK, PTI6_FN), - PINMUX_DATA(IRQ13_MARK, PTI5_FN), - PINMUX_DATA(IRQ12_MARK, PTI4_FN), - PINMUX_DATA(IRQ11_MARK, PTI3_FN), - PINMUX_DATA(IRQ10_MARK, PTI2_FN), - PINMUX_DATA(IRQ9_MARK, PTI1_FN), - PINMUX_DATA(IRQ8_MARK, PTI0_FN), + PINMUX_DATA(D15_MARK, PS3_15_FN1, PTI7_FN), + PINMUX_DATA(SD_WP_MARK, PS3_15_FN2, PTI7_FN), + PINMUX_DATA(D14_MARK, PS3_14_FN1, PTI6_FN), + PINMUX_DATA(SD_CD_MARK, PS3_14_FN2, PTI6_FN), + PINMUX_DATA(D13_MARK, PS3_13_FN1, PTI5_FN), + PINMUX_DATA(SD_CLK_MARK, PS3_13_FN2, PTI5_FN), + PINMUX_DATA(D12_MARK, PS3_12_FN1, PTI4_FN), + PINMUX_DATA(SD_CMD_MARK, PS3_12_FN2, PTI4_FN), + PINMUX_DATA(D11_MARK, PS3_11_FN1, PTI3_FN), + PINMUX_DATA(SD_D3_MARK, PS3_11_FN2, PTI3_FN), + PINMUX_DATA(D10_MARK, PS3_10_FN1, PTI2_FN), + PINMUX_DATA(SD_D2_MARK, PS3_10_FN2, PTI2_FN), + PINMUX_DATA(D9_MARK, PS3_9_FN1, PTI1_FN), + PINMUX_DATA(SD_D1_MARK, PS3_9_FN2, PTI1_FN), + PINMUX_DATA(D8_MARK, PS3_8_FN1, PTI0_FN), + PINMUX_DATA(SD_D0_MARK, PS3_8_FN2, PTI0_FN), /* PTJ FN */ - PINMUX_DATA(RXD3_MARK, PTJ7_FN), - PINMUX_DATA(TXD3_MARK, PTJ6_FN), - PINMUX_DATA(RXD2_MARK, PTJ5_FN), - PINMUX_DATA(TXD2_MARK, PTJ4_FN), - PINMUX_DATA(COM1_TXD_MARK, PTJ3_FN), - PINMUX_DATA(COM1_RXD_MARK, PTJ2_FN), - PINMUX_DATA(COM1_RTS_MARK, PTJ1_FN), - PINMUX_DATA(COM1_CTS_MARK, PTJ0_FN), + PINMUX_DATA(RTS3_MARK, PTJ6_FN), + PINMUX_DATA(CTS3_MARK, PTJ5_FN), + PINMUX_DATA(TXD3_MARK, PTJ4_FN), + PINMUX_DATA(RXD3_MARK, PTJ3_FN), + PINMUX_DATA(RTS4_MARK, PTJ2_FN), + PINMUX_DATA(RXD4_MARK, PTJ1_FN), + PINMUX_DATA(TXD4_MARK, PTJ0_FN), /* PTK FN */ - PINMUX_DATA(COM2_TXD_MARK, PTK7_FN), + PINMUX_DATA(COM2_TXD_MARK, PS3_7_FN1, PTK7_FN), + PINMUX_DATA(SCK2_MARK, PS3_7_FN2, PTK7_FN), PINMUX_DATA(COM2_RXD_MARK, PTK6_FN), PINMUX_DATA(COM2_RTS_MARK, PTK5_FN), PINMUX_DATA(COM2_CTS_MARK, PTK4_FN), PINMUX_DATA(COM2_DTR_MARK, PTK3_FN), - PINMUX_DATA(COM2_DSR_MARK, PTK2_FN), - PINMUX_DATA(COM2_DCD_MARK, PTK1_FN), - PINMUX_DATA(COM2_RI_MARK, PTK0_FN), + PINMUX_DATA(COM2_DSR_MARK, PS3_2_FN1, PTK2_FN), + PINMUX_DATA(SCK4_MARK, PS3_2_FN2, PTK2_FN), + PINMUX_DATA(COM2_DCD_MARK, PS3_1_FN1, PTK1_FN), + PINMUX_DATA(SCK3_MARK, PS3_1_FN2, PTK1_FN), + PINMUX_DATA(CLKOUT_MARK, PTK0_FN), /* PTL FN */ - PINMUX_DATA(RAC_TXD_MARK, PTL7_FN), - PINMUX_DATA(RAC_RXD_MARK, PTL6_FN), - PINMUX_DATA(RAC_RTS_MARK, PTL5_FN), - PINMUX_DATA(RAC_CTS_MARK, PTL4_FN), + PINMUX_DATA(RAC_RXD_MARK, PS4_14_FN1, PTL6_FN), + PINMUX_DATA(RXD2_MARK, PS4_14_FN2, PTL6_FN), + PINMUX_DATA(RAC_RTS_MARK, PS4_13_FN1, PTL5_FN), + PINMUX_DATA(CS5_MARK, PS4_13_FN2, PTL5_FN), + PINMUX_DATA(RAC_CTS_MARK, PS4_12_FN1, PTL4_FN), + PINMUX_DATA(CS6_MARK, PS4_12_FN2, PTL4_FN), PINMUX_DATA(RAC_DTR_MARK, PTL3_FN), - PINMUX_DATA(RAC_DSR_MARK, PTL2_FN), - PINMUX_DATA(RAC_DCD_MARK, PTL1_FN), - PINMUX_DATA(RAC_RI_MARK, PTL0_FN), + PINMUX_DATA(RAC_DSR_MARK, PS4_10_FN1, PTL2_FN), + PINMUX_DATA(AUDSYNC_MARK, PS4_10_FN2, PTL2_FN), + PINMUX_DATA(RAC_DCD_MARK, PS4_9_FN1, PTL1_FN), + PINMUX_DATA(AUDCK_MARK, PS4_9_FN2, PTL1_FN), + PINMUX_DATA(RAC_TXD_MARK, PS4_8_FN1, PTL0_FN), + PINMUX_DATA(TXD2_MARK, PS4_8_FN1, PTL0_FN), /* PTM FN */ - PINMUX_DATA(WP_MARK, PTM6_FN), - PINMUX_DATA(FMS0_MARK, PTM5_FN), - PINMUX_DATA(FMS1_MARK, PTM4_FN), + PINMUX_DATA(CS4_MARK, PTM7_FN), + PINMUX_DATA(RD_MARK, PTM6_FN), + PINMUX_DATA(WE0_MARK, PTM7_FN), + PINMUX_DATA(CS0_MARK, PTM4_FN), PINMUX_DATA(SDA6_MARK, PTM3_FN), PINMUX_DATA(SCL6_MARK, PTM2_FN), PINMUX_DATA(SDA7_MARK, PTM1_FN), PINMUX_DATA(SCL7_MARK, PTM0_FN), /* PTN FN */ - PINMUX_DATA(SCK2_MARK, PS4_15_FN1, PTN7_FN), - PINMUX_DATA(EVENT7_MARK, PS4_15_FN2, PTN7_FN), - PINMUX_DATA(RTS4_MARK, PS4_14_FN1, PTN6_FN), - PINMUX_DATA(EVENT6_MARK, PS4_14_FN2, PTN6_FN), - PINMUX_DATA(RTS3_MARK, PS4_13_FN1, PTN5_FN), - PINMUX_DATA(EVENT5_MARK, PS4_13_FN2, PTN5_FN), - PINMUX_DATA(RTS2_MARK, PS4_12_FN1, PTN4_FN), - PINMUX_DATA(EVENT4_MARK, PS4_12_FN2, PTN4_FN), - PINMUX_DATA(CTS4_MARK, PS4_11_FN1, PTN3_FN), - PINMUX_DATA(EVENT3_MARK, PS4_11_FN2, PTN3_FN), - PINMUX_DATA(CTS3_MARK, PS4_10_FN1, PTN2_FN), - PINMUX_DATA(EVENT2_MARK, PS4_10_FN2, PTN2_FN), - PINMUX_DATA(CTS2_MARK, PS4_9_FN1, PTN1_FN), - PINMUX_DATA(EVENT1_MARK, PS4_9_FN2, PTN1_FN), - PINMUX_DATA(EVENT0_MARK, PTN0_FN), + PINMUX_DATA(VBUS_EN_MARK, PTN6_FN), + PINMUX_DATA(VBUS_OC_MARK, PTN5_FN), + PINMUX_DATA(JMCTCK_MARK, PS4_4_FN1, PTN4_FN), + PINMUX_DATA(SGPIO1_CLK_MARK, PS4_4_FN2, PTN4_FN), + PINMUX_DATA(JMCTMS_MARK, PS4_3_FN1, PTN5_FN), + PINMUX_DATA(SGPIO1_LOAD_MARK, PS4_3_FN2, PTN5_FN), + PINMUX_DATA(JMCTDO_MARK, PS4_2_FN1, PTN2_FN), + PINMUX_DATA(SGPIO1_DO_MARK, PS4_2_FN2, PTN2_FN), + PINMUX_DATA(JMCTDI_MARK, PS4_1_FN1, PTN1_FN), + PINMUX_DATA(SGPIO1_DI_MARK, PS4_1_FN2, PTN1_FN), + PINMUX_DATA(JMCTRST_MARK, PS4_0_FN1, PTN0_FN), + PINMUX_DATA(SUB_CLKIN_MARK, PS4_0_FN2, PTN0_FN), /* PTO FN */ PINMUX_DATA(SGPIO0_CLK_MARK, PTO7_FN), PINMUX_DATA(SGPIO0_LOAD_MARK, PTO6_FN), PINMUX_DATA(SGPIO0_DI_MARK, PTO5_FN), PINMUX_DATA(SGPIO0_DO_MARK, PTO4_FN), - PINMUX_DATA(SGPIO1_CLK_MARK, PTO3_FN), - PINMUX_DATA(SGPIO1_LOAD_MARK, PTO2_FN), - PINMUX_DATA(SGPIO1_DI_MARK, PTO1_FN), - PINMUX_DATA(SGPIO1_DO_MARK, PTO0_FN), + PINMUX_DATA(SGPIO2_CLK_MARK, PS5_11_FN1, PTO3_FN), + PINMUX_DATA(COM1_TXD_MARK, PS5_11_FN2, PTO3_FN), + PINMUX_DATA(SGPIO2_LOAD_MARK, PS5_10_FN1, PTO2_FN), + PINMUX_DATA(COM1_RXD_MARK, PS5_10_FN2, PTO2_FN), + PINMUX_DATA(SGPIO2_DI_MARK, PS5_9_FN1, PTO1_FN), + PINMUX_DATA(COM1_RTS_MARK, PS5_9_FN2, PTO1_FN), + PINMUX_DATA(SGPIO2_DO_MARK, PS5_8_FN1, PTO0_FN), + PINMUX_DATA(COM1_CTS_MARK, PS5_8_FN2, PTO0_FN), /* PTP FN */ - PINMUX_DATA(JMCTCK_MARK, PTP6_FN), - PINMUX_DATA(JMCTMS_MARK, PTP5_FN), - PINMUX_DATA(JMCTDO_MARK, PTP4_FN), - PINMUX_DATA(JMCTDI_MARK, PTP3_FN), - PINMUX_DATA(JMCRST_MARK, PTP2_FN), - PINMUX_DATA(SCK4_MARK, PTP1_FN), - PINMUX_DATA(SCK3_MARK, PTP0_FN), /* PTQ FN */ PINMUX_DATA(LAD3_MARK, PTQ6_FN), @@ -864,8 +977,8 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(LAD1_MARK, PTQ4_FN), PINMUX_DATA(LAD0_MARK, PTQ3_FN), PINMUX_DATA(LFRAME_MARK, PTQ2_FN), - PINMUX_DATA(SCK4_MARK, PTQ1_FN), - PINMUX_DATA(SCK3_MARK, PTQ0_FN), + PINMUX_DATA(LRESET_MARK, PTQ1_FN), + PINMUX_DATA(LCLK_MARK, PTQ0_FN), /* PTR FN */ PINMUX_DATA(SDA8_MARK, PTR7_FN), /* DDC3? */ @@ -888,58 +1001,84 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(SCL3_MARK, PTS0_FN), /* PTT FN */ - PINMUX_DATA(AUDSYNC_MARK, PTS5_FN), - PINMUX_DATA(AUDCK_MARK, PTS4_FN), - PINMUX_DATA(AUDATA3_MARK, PS4_3_FN1, PTS3_FN), - PINMUX_DATA(PWX7_MARK, PS4_3_FN2, PTS3_FN), - PINMUX_DATA(AUDATA2_MARK, PS4_2_FN1, PTS2_FN), - PINMUX_DATA(PWX6_MARK, PS4_2_FN2, PTS2_FN), - PINMUX_DATA(AUDATA1_MARK, PS4_1_FN1, PTS1_FN), - PINMUX_DATA(PWX5_MARK, PS4_1_FN2, PTS1_FN), - PINMUX_DATA(AUDATA0_MARK, PS4_0_FN1, PTS0_FN), - PINMUX_DATA(PWX4_MARK, PS4_0_FN2, PTS0_FN), + PINMUX_DATA(PWMX7_MARK, PS5_7_FN1, PTT7_FN), + PINMUX_DATA(AUDATA3_MARK, PS5_7_FN2, PTT7_FN), + PINMUX_DATA(PWMX6_MARK, PS5_6_FN1, PTT6_FN), + PINMUX_DATA(AUDATA2_MARK, PS5_6_FN2, PTT6_FN), + PINMUX_DATA(PWMX5_MARK, PS5_5_FN1, PTT5_FN), + PINMUX_DATA(AUDATA1_MARK, PS5_5_FN2, PTT5_FN), + PINMUX_DATA(PWMX4_MARK, PS5_4_FN1, PTT4_FN), + PINMUX_DATA(AUDATA0_MARK, PS5_4_FN2, PTT4_FN), + PINMUX_DATA(PWMX3_MARK, PS5_3_FN1, PTT3_FN), + PINMUX_DATA(STATUS1_MARK, PS5_3_FN2, PTT3_FN), + PINMUX_DATA(PWMX2_MARK, PS5_2_FN1, PTT2_FN), + PINMUX_DATA(STATUS0_MARK, PS5_2_FN2, PTT2_FN), + PINMUX_DATA(PWMX1_MARK, PTT1_FN), + PINMUX_DATA(PWMX0_MARK, PTT0_FN), /* PTU FN */ - PINMUX_DATA(CS6_MARK, PTU7_FN), - PINMUX_DATA(CS5_MARK, PTU6_FN), - PINMUX_DATA(CS4_MARK, PTU5_FN), - PINMUX_DATA(CS0_MARK, PTU4_FN), - PINMUX_DATA(RD_MARK, PTU3_FN), - PINMUX_DATA(WE0_MARK, PTU2_FN), - PINMUX_DATA(A25_MARK, PS5_9_FN1, PTU1_FN), - PINMUX_DATA(DREQ0_MARK, PS5_9_FN2, PTU1_FN), - PINMUX_DATA(A24_MARK, PS5_8_FN1, PTU0_FN), - PINMUX_DATA(DACK0_MARK, PS5_8_FN2, PTU0_FN), + PINMUX_DATA(LGPIO7_MARK, PS6_15_FN1, PTU7_FN), + PINMUX_DATA(APMONCTL_O_MARK, PS6_15_FN2, PTU7_FN), + PINMUX_DATA(LGPIO6_MARK, PS6_14_FN1, PTU6_FN), + PINMUX_DATA(APMPWBTOUT_O_MARK, PS6_14_FN2, PTU6_FN), + PINMUX_DATA(LGPIO5_MARK, PS6_13_FN1, PTU5_FN), + PINMUX_DATA(APMSCI_O_MARK, PS6_13_FN2, PTU5_FN), + PINMUX_DATA(LGPIO4_MARK, PS6_12_FN1, PTU4_FN), + PINMUX_DATA(APMVDDON_MARK, PS6_12_FN2, PTU4_FN), + PINMUX_DATA(LGPIO3_MARK, PS6_11_FN1, PTU3_FN), + PINMUX_DATA(APMSLPBTN_MARK, PS6_11_FN2, PTU3_FN), + PINMUX_DATA(LGPIO2_MARK, PS6_10_FN1, PTU2_FN), + PINMUX_DATA(APMPWRBTN_MARK, PS6_10_FN2, PTU2_FN), + PINMUX_DATA(LGPIO1_MARK, PS6_9_FN1, PTU1_FN), + PINMUX_DATA(APMS5N_MARK, PS6_9_FN2, PTU1_FN), + PINMUX_DATA(LGPIO0_MARK, PS6_8_FN1, PTU0_FN), + PINMUX_DATA(APMS3N_MARK, PS6_8_FN2, PTU0_FN), /* PTV FN */ - PINMUX_DATA(A23_MARK, PS5_7_FN1, PTV7_FN), - PINMUX_DATA(TEND0_MARK, PS5_7_FN2, PTV7_FN), - PINMUX_DATA(A22_MARK, PS5_6_FN1, PTV6_FN), - PINMUX_DATA(DREQ1_MARK, PS5_6_FN2, PTV6_FN), - PINMUX_DATA(A21_MARK, PS5_5_FN1, PTV5_FN), - PINMUX_DATA(DACK1_MARK, PS5_5_FN2, PTV5_FN), - PINMUX_DATA(A20_MARK, PS5_4_FN1, PTV4_FN), - PINMUX_DATA(TEND1_MARK, PS5_4_FN2, PTV4_FN), - PINMUX_DATA(A19_MARK, PTV3_FN), - PINMUX_DATA(A18_MARK, PTV2_FN), - PINMUX_DATA(A17_MARK, PTV1_FN), - PINMUX_DATA(A16_MARK, PTV0_FN), + PINMUX_DATA(A23_MARK, PS6_7_FN1, PTV7_FN), + PINMUX_DATA(COM2_RI_MARK, PS6_7_FN2, PTV7_FN), + PINMUX_DATA(A22_MARK, PS6_6_FN1, PTV6_FN), + PINMUX_DATA(R_SPI_MOSI_MARK, PS6_6_FN2, PTV6_FN), + PINMUX_DATA(A21_MARK, PS6_5_FN1, PTV5_FN), + PINMUX_DATA(R_SPI_MISO_MARK, PS6_5_FN2, PTV5_FN), + PINMUX_DATA(A20_MARK, PS6_4_FN1, PTV4_FN), + PINMUX_DATA(R_SPI_RSPCK_MARK, PS6_4_FN2, PTV4_FN), + PINMUX_DATA(A19_MARK, PS6_3_FN1, PTV3_FN), + PINMUX_DATA(R_SPI_SSL0_MARK, PS6_3_FN2, PTV3_FN), + PINMUX_DATA(A18_MARK, PS6_2_FN1, PTV2_FN), + PINMUX_DATA(R_SPI_SSL1_MARK, PS6_2_FN2, PTV2_FN), + PINMUX_DATA(A17_MARK, PS6_1_FN1, PTV1_FN), + PINMUX_DATA(EVENT7_MARK, PS6_1_FN2, PTV1_FN), + PINMUX_DATA(A16_MARK, PS6_0_FN1, PTV0_FN), + PINMUX_DATA(EVENT6_MARK, PS6_0_FN1, PTV0_FN), /* PTW FN */ - PINMUX_DATA(A15_MARK, PTW7_FN), - PINMUX_DATA(A14_MARK, PTW6_FN), - PINMUX_DATA(A13_MARK, PTW5_FN), - PINMUX_DATA(A12_MARK, PTW4_FN), - PINMUX_DATA(A11_MARK, PTW3_FN), - PINMUX_DATA(A10_MARK, PTW2_FN), - PINMUX_DATA(A9_MARK, PTW1_FN), - PINMUX_DATA(A8_MARK, PTW0_FN), + PINMUX_DATA(A15_MARK, PS7_15_FN1, PTW7_FN), + PINMUX_DATA(EVENT5_MARK, PS7_15_FN2, PTW7_FN), + PINMUX_DATA(A14_MARK, PS7_14_FN1, PTW6_FN), + PINMUX_DATA(EVENT4_MARK, PS7_14_FN2, PTW6_FN), + PINMUX_DATA(A13_MARK, PS7_13_FN1, PTW5_FN), + PINMUX_DATA(EVENT3_MARK, PS7_13_FN2, PTW5_FN), + PINMUX_DATA(A12_MARK, PS7_12_FN1, PTW4_FN), + PINMUX_DATA(EVENT2_MARK, PS7_12_FN2, PTW4_FN), + PINMUX_DATA(A11_MARK, PS7_11_FN1, PTW3_FN), + PINMUX_DATA(EVENT1_MARK, PS7_11_FN2, PTW3_FN), + PINMUX_DATA(A10_MARK, PS7_10_FN1, PTW2_FN), + PINMUX_DATA(EVENT0_MARK, PS7_10_FN2, PTW2_FN), + PINMUX_DATA(A9_MARK, PS7_9_FN1, PTW1_FN), + PINMUX_DATA(CTS4_MARK, PS7_9_FN2, PTW1_FN), + PINMUX_DATA(A8_MARK, PS7_8_FN1, PTW0_FN), + PINMUX_DATA(CTS2_MARK, PS7_8_FN2, PTW0_FN), /* PTX FN */ - PINMUX_DATA(A7_MARK, PTX7_FN), - PINMUX_DATA(A6_MARK, PTX6_FN), - PINMUX_DATA(A5_MARK, PTX5_FN), - PINMUX_DATA(A4_MARK, PTX4_FN), + PINMUX_DATA(A7_MARK, PS7_7_FN1, PTX7_FN), + PINMUX_DATA(RTS2_MARK, PS7_7_FN2, PTX7_FN), + PINMUX_DATA(A6_MARK, PS7_6_FN1, PTX6_FN), + PINMUX_DATA(SIM_D_MARK, PS7_6_FN2, PTX6_FN), + PINMUX_DATA(A5_MARK, PS7_5_FN1, PTX5_FN), + PINMUX_DATA(SIM_CLK_MARK, PS7_5_FN2, PTX5_FN), + PINMUX_DATA(A4_MARK, PS7_4_FN1, PTX4_FN), + PINMUX_DATA(SIM_RST_MARK, PS7_4_FN2, PTX4_FN), PINMUX_DATA(A3_MARK, PTX3_FN), PINMUX_DATA(A2_MARK, PTX2_FN), PINMUX_DATA(A1_MARK, PTX1_FN), @@ -954,6 +1093,24 @@ static pinmux_enum_t pinmux_data[] = { PINMUX_DATA(D2_MARK, PTY2_FN), PINMUX_DATA(D1_MARK, PTY1_FN), PINMUX_DATA(D0_MARK, PTY0_FN), + + /* PTZ FN */ + PINMUX_DATA(MMCDAT7_MARK, PS8_15_FN1, PTZ7_FN), + PINMUX_DATA(ON_DQ7_MARK, PS8_15_FN2, PTZ7_FN), + PINMUX_DATA(MMCDAT6_MARK, PS8_14_FN1, PTZ6_FN), + PINMUX_DATA(ON_DQ6_MARK, PS8_14_FN2, PTZ6_FN), + PINMUX_DATA(MMCDAT5_MARK, PS8_13_FN1, PTZ5_FN), + PINMUX_DATA(ON_DQ5_MARK, PS8_13_FN2, PTZ5_FN), + PINMUX_DATA(MMCDAT4_MARK, PS8_12_FN1, PTZ4_FN), + PINMUX_DATA(ON_DQ4_MARK, PS8_12_FN2, PTZ4_FN), + PINMUX_DATA(MMCDAT3_MARK, PS8_11_FN1, PTZ3_FN), + PINMUX_DATA(ON_DQ3_MARK, PS8_11_FN2, PTZ3_FN), + PINMUX_DATA(MMCDAT2_MARK, PS8_10_FN1, PTZ2_FN), + PINMUX_DATA(ON_DQ2_MARK, PS8_10_FN2, PTZ2_FN), + PINMUX_DATA(MMCDAT1_MARK, PS8_9_FN1, PTZ1_FN), + PINMUX_DATA(ON_DQ1_MARK, PS8_9_FN2, PTZ1_FN), + PINMUX_DATA(MMCDAT0_MARK, PS8_8_FN1, PTZ0_FN), + PINMUX_DATA(ON_DQ0_MARK, PS8_8_FN2, PTZ0_FN), }; static struct pinmux_gpio pinmux_gpios[] = { @@ -1048,7 +1205,6 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_PTI0, PTI0_DATA), /* PTJ */ - PINMUX_GPIO(GPIO_PTJ7, PTJ7_DATA), PINMUX_GPIO(GPIO_PTJ6, PTJ6_DATA), PINMUX_GPIO(GPIO_PTJ5, PTJ5_DATA), PINMUX_GPIO(GPIO_PTJ4, PTJ4_DATA), @@ -1068,7 +1224,6 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_PTK0, PTK0_DATA), /* PTL */ - PINMUX_GPIO(GPIO_PTL7, PTL7_DATA), PINMUX_GPIO(GPIO_PTL6, PTL6_DATA), PINMUX_GPIO(GPIO_PTL5, PTL5_DATA), PINMUX_GPIO(GPIO_PTL4, PTL4_DATA), @@ -1078,6 +1233,7 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_PTL0, PTL0_DATA), /* PTM */ + PINMUX_GPIO(GPIO_PTM7, PTM7_DATA), PINMUX_GPIO(GPIO_PTM6, PTM6_DATA), PINMUX_GPIO(GPIO_PTM5, PTM5_DATA), PINMUX_GPIO(GPIO_PTM4, PTM4_DATA), @@ -1087,7 +1243,6 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_PTM0, PTM0_DATA), /* PTN */ - PINMUX_GPIO(GPIO_PTN7, PTN7_DATA), PINMUX_GPIO(GPIO_PTN6, PTN6_DATA), PINMUX_GPIO(GPIO_PTN5, PTN5_DATA), PINMUX_GPIO(GPIO_PTN4, PTN4_DATA), @@ -1107,6 +1262,7 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_PTO0, PTO0_DATA), /* PTP */ + PINMUX_GPIO(GPIO_PTP7, PTP7_DATA), PINMUX_GPIO(GPIO_PTP6, PTP6_DATA), PINMUX_GPIO(GPIO_PTP5, PTP5_DATA), PINMUX_GPIO(GPIO_PTP4, PTP4_DATA), @@ -1145,6 +1301,8 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_PTS0, PTS0_DATA), /* PTT */ + PINMUX_GPIO(GPIO_PTT7, PTT7_DATA), + PINMUX_GPIO(GPIO_PTT6, PTT6_DATA), PINMUX_GPIO(GPIO_PTT5, PTT5_DATA), PINMUX_GPIO(GPIO_PTT4, PTT4_DATA), PINMUX_GPIO(GPIO_PTT3, PTT3_DATA), @@ -1212,54 +1370,35 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA), PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA), - /* PTA (mobule: LBSC, CPG, LPC) */ + /* PTA (mobule: LBSC, RGMII) */ PINMUX_GPIO(GPIO_FN_BS, BS_MARK), PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK), PINMUX_GPIO(GPIO_FN_WE1, WE1_MARK), PINMUX_GPIO(GPIO_FN_RDY, RDY_MARK), - PINMUX_GPIO(GPIO_FN_MD10, MD10_MARK), - PINMUX_GPIO(GPIO_FN_MD9, MD9_MARK), - PINMUX_GPIO(GPIO_FN_MD8, MD8_MARK), - PINMUX_GPIO(GPIO_FN_LGPIO7, LGPIO7_MARK), - PINMUX_GPIO(GPIO_FN_LGPIO6, LGPIO6_MARK), - PINMUX_GPIO(GPIO_FN_LGPIO5, LGPIO5_MARK), - PINMUX_GPIO(GPIO_FN_LGPIO4, LGPIO4_MARK), - PINMUX_GPIO(GPIO_FN_LGPIO3, LGPIO3_MARK), - PINMUX_GPIO(GPIO_FN_LGPIO2, LGPIO2_MARK), - PINMUX_GPIO(GPIO_FN_LGPIO1, LGPIO1_MARK), - PINMUX_GPIO(GPIO_FN_LGPIO0, LGPIO0_MARK), - - /* PTB (mobule: LBSC, EtherC, SIM, LPC) */ - PINMUX_GPIO(GPIO_FN_D15, D15_MARK), - PINMUX_GPIO(GPIO_FN_D14, D14_MARK), - PINMUX_GPIO(GPIO_FN_D13, D13_MARK), - PINMUX_GPIO(GPIO_FN_D12, D12_MARK), - PINMUX_GPIO(GPIO_FN_D11, D11_MARK), - PINMUX_GPIO(GPIO_FN_D10, D10_MARK), - PINMUX_GPIO(GPIO_FN_D9, D9_MARK), - PINMUX_GPIO(GPIO_FN_D8, D8_MARK), PINMUX_GPIO(GPIO_FN_ET0_MDC, ET0_MDC_MARK), - PINMUX_GPIO(GPIO_FN_ET0_MDIO, ET0_MDIO_MARK), + PINMUX_GPIO(GPIO_FN_ET0_MDIO, ET0_MDC_MARK), PINMUX_GPIO(GPIO_FN_ET1_MDC, ET1_MDC_MARK), - PINMUX_GPIO(GPIO_FN_ET1_MDIO, ET1_MDIO_MARK), - PINMUX_GPIO(GPIO_FN_WPSZ1, WPSZ1_MARK), - PINMUX_GPIO(GPIO_FN_WPSZ0, WPSZ0_MARK), - PINMUX_GPIO(GPIO_FN_FWID, FWID_MARK), - PINMUX_GPIO(GPIO_FN_FLSHSZ, FLSHSZ_MARK), - PINMUX_GPIO(GPIO_FN_LPC_SPIEN, LPC_SPIEN_MARK), - PINMUX_GPIO(GPIO_FN_BASEL, BASEL_MARK), - - /* PTC (mobule: SD) */ - PINMUX_GPIO(GPIO_FN_SD_WP, SD_WP_MARK), - PINMUX_GPIO(GPIO_FN_SD_CD, SD_CD_MARK), - PINMUX_GPIO(GPIO_FN_SD_CLK, SD_CLK_MARK), - PINMUX_GPIO(GPIO_FN_SD_CMD, SD_CMD_MARK), - PINMUX_GPIO(GPIO_FN_SD_D3, SD_D3_MARK), - PINMUX_GPIO(GPIO_FN_SD_D2, SD_D2_MARK), - PINMUX_GPIO(GPIO_FN_SD_D1, SD_D1_MARK), - PINMUX_GPIO(GPIO_FN_SD_D0, SD_D0_MARK), + PINMUX_GPIO(GPIO_FN_ET1_MDIO, ET1_MDC_MARK), - /* PTD (mobule: INTC, SPI0, LBSC, CPG, ADC) */ + /* PTB (mobule: INTC, ONFI, TMU) */ + PINMUX_GPIO(GPIO_FN_IRQ15, IRQ15_MARK), + PINMUX_GPIO(GPIO_FN_IRQ14, IRQ14_MARK), + PINMUX_GPIO(GPIO_FN_IRQ13, IRQ13_MARK), + PINMUX_GPIO(GPIO_FN_IRQ12, IRQ12_MARK), + PINMUX_GPIO(GPIO_FN_IRQ11, IRQ11_MARK), + PINMUX_GPIO(GPIO_FN_IRQ10, IRQ10_MARK), + PINMUX_GPIO(GPIO_FN_IRQ9, IRQ9_MARK), + PINMUX_GPIO(GPIO_FN_IRQ8, IRQ8_MARK), + PINMUX_GPIO(GPIO_FN_ON_NRE, ON_NRE_MARK), + PINMUX_GPIO(GPIO_FN_ON_NWE, ON_NWE_MARK), + PINMUX_GPIO(GPIO_FN_ON_NWP, ON_NWP_MARK), + PINMUX_GPIO(GPIO_FN_ON_NCE0, ON_NCE0_MARK), + PINMUX_GPIO(GPIO_FN_ON_R_B0, ON_R_B0_MARK), + PINMUX_GPIO(GPIO_FN_ON_ALE, ON_ALE_MARK), + PINMUX_GPIO(GPIO_FN_ON_CLE, ON_CLE_MARK), + PINMUX_GPIO(GPIO_FN_TCLK, TCLK_MARK), + + /* PTC (mobule: IRQ, PWMU) */ PINMUX_GPIO(GPIO_FN_IRQ7, IRQ7_MARK), PINMUX_GPIO(GPIO_FN_IRQ6, IRQ6_MARK), PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK), @@ -1268,80 +1407,102 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK), PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK), PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK), - PINMUX_GPIO(GPIO_FN_MD6, MD6_MARK), - PINMUX_GPIO(GPIO_FN_MD5, MD5_MARK), - PINMUX_GPIO(GPIO_FN_MD3, MD3_MARK), - PINMUX_GPIO(GPIO_FN_MD2, MD2_MARK), - PINMUX_GPIO(GPIO_FN_MD1, MD1_MARK), - PINMUX_GPIO(GPIO_FN_MD0, MD0_MARK), - PINMUX_GPIO(GPIO_FN_ADTRG1, ADTRG1_MARK), - PINMUX_GPIO(GPIO_FN_ADTRG0, ADTRG0_MARK), + PINMUX_GPIO(GPIO_FN_PWMU0, PWMU0_MARK), + PINMUX_GPIO(GPIO_FN_PWMU1, PWMU1_MARK), + PINMUX_GPIO(GPIO_FN_PWMU2, PWMU2_MARK), + PINMUX_GPIO(GPIO_FN_PWMU3, PWMU3_MARK), + PINMUX_GPIO(GPIO_FN_PWMU4, PWMU4_MARK), + PINMUX_GPIO(GPIO_FN_PWMU5, PWMU5_MARK), + + /* PTD (mobule: SPI0, DMAC) */ + PINMUX_GPIO(GPIO_FN_SP0_MOSI, SP0_MOSI_MARK), + PINMUX_GPIO(GPIO_FN_SP0_MISO, SP0_MISO_MARK), + PINMUX_GPIO(GPIO_FN_SP0_SCK, SP0_SCK_MARK), + PINMUX_GPIO(GPIO_FN_SP0_SCK_FB, SP0_SCK_FB_MARK), + PINMUX_GPIO(GPIO_FN_SP0_SS0, SP0_SS0_MARK), + PINMUX_GPIO(GPIO_FN_SP0_SS1, SP0_SS1_MARK), + PINMUX_GPIO(GPIO_FN_SP0_SS2, SP0_SS2_MARK), + PINMUX_GPIO(GPIO_FN_SP0_SS3, SP0_SS3_MARK), + PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), + PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), + PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK), - /* PTE (mobule: EtherC) */ - PINMUX_GPIO(GPIO_FN_ET0_CRS_DV, ET0_CRS_DV_MARK), - PINMUX_GPIO(GPIO_FN_ET0_TXD1, ET0_TXD1_MARK), - PINMUX_GPIO(GPIO_FN_ET0_TXD0, ET0_TXD0_MARK), - PINMUX_GPIO(GPIO_FN_ET0_TX_EN, ET0_TX_EN_MARK), - PINMUX_GPIO(GPIO_FN_ET0_REF_CLK, ET0_REF_CLK_MARK), - PINMUX_GPIO(GPIO_FN_ET0_RXD1, ET0_RXD1_MARK), - PINMUX_GPIO(GPIO_FN_ET0_RXD0, ET0_RXD0_MARK), - PINMUX_GPIO(GPIO_FN_ET0_RX_ER, ET0_RX_ER_MARK), - - /* PTF (mobule: EtherC) */ - PINMUX_GPIO(GPIO_FN_ET1_CRS_DV, ET1_CRS_DV_MARK), - PINMUX_GPIO(GPIO_FN_ET1_TXD1, ET1_TXD1_MARK), - PINMUX_GPIO(GPIO_FN_ET1_TXD0, ET1_TXD0_MARK), - PINMUX_GPIO(GPIO_FN_ET1_TX_EN, ET1_TX_EN_MARK), - PINMUX_GPIO(GPIO_FN_ET1_REF_CLK, ET1_REF_CLK_MARK), - PINMUX_GPIO(GPIO_FN_ET1_RXD1, ET1_RXD1_MARK), - PINMUX_GPIO(GPIO_FN_ET1_RXD0, ET1_RXD0_MARK), - PINMUX_GPIO(GPIO_FN_ET1_RX_ER, ET1_RX_ER_MARK), - - /* PTG (mobule: SYSTEM, PWMX, LPC) */ - PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), - PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK), - PINMUX_GPIO(GPIO_FN_PWX0, PWX0_MARK), - PINMUX_GPIO(GPIO_FN_PWX1, PWX1_MARK), - PINMUX_GPIO(GPIO_FN_PWX2, PWX2_MARK), - PINMUX_GPIO(GPIO_FN_PWX3, PWX3_MARK), + /* PTE (mobule: RMII) */ + PINMUX_GPIO(GPIO_FN_RMII0_CRS_DV, RMII0_CRS_DV_MARK), + PINMUX_GPIO(GPIO_FN_RMII0_TXD1, RMII0_TXD1_MARK), + PINMUX_GPIO(GPIO_FN_RMII0_TXD0, RMII0_TXD0_MARK), + PINMUX_GPIO(GPIO_FN_RMII0_TXEN, RMII0_TXEN_MARK), + PINMUX_GPIO(GPIO_FN_RMII0_REFCLK, RMII0_REFCLK_MARK), + PINMUX_GPIO(GPIO_FN_RMII0_RXD1, RMII0_RXD1_MARK), + PINMUX_GPIO(GPIO_FN_RMII0_RXD0, RMII0_RXD0_MARK), + PINMUX_GPIO(GPIO_FN_RMII0_RX_ER, RMII0_RX_ER_MARK), + + /* PTF (mobule: RMII, SerMux) */ + PINMUX_GPIO(GPIO_FN_RMII1_CRS_DV, RMII1_CRS_DV_MARK), + PINMUX_GPIO(GPIO_FN_RMII1_TXD1, RMII1_TXD1_MARK), + PINMUX_GPIO(GPIO_FN_RMII1_TXD0, RMII1_TXD0_MARK), + PINMUX_GPIO(GPIO_FN_RMII1_TXEN, RMII1_TXEN_MARK), + PINMUX_GPIO(GPIO_FN_RMII1_REFCLK, RMII1_REFCLK_MARK), + PINMUX_GPIO(GPIO_FN_RMII1_RXD1, RMII1_RXD1_MARK), + PINMUX_GPIO(GPIO_FN_RMII1_RXD0, RMII1_RXD0_MARK), + PINMUX_GPIO(GPIO_FN_RMII1_RX_ER, RMII1_RX_ER_MARK), + PINMUX_GPIO(GPIO_FN_RAC_RI, RAC_RI_MARK), + + /* PTG (mobule: system, LBSC, LPC, WDT, LPC, eMMC) */ + PINMUX_GPIO(GPIO_FN_BOOTFMS, BOOTFMS_MARK), + PINMUX_GPIO(GPIO_FN_BOOTWP, BOOTWP_MARK), + PINMUX_GPIO(GPIO_FN_A25, A25_MARK), + PINMUX_GPIO(GPIO_FN_A24, A24_MARK), PINMUX_GPIO(GPIO_FN_SERIRQ, SERIRQ_MARK), - PINMUX_GPIO(GPIO_FN_CLKRUN, CLKRUN_MARK), + PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK), PINMUX_GPIO(GPIO_FN_LPCPD, LPCPD_MARK), PINMUX_GPIO(GPIO_FN_LDRQ, LDRQ_MARK), + PINMUX_GPIO(GPIO_FN_MMCCLK, MMCCLK_MARK), + PINMUX_GPIO(GPIO_FN_MMCCMD, MMCCMD_MARK), - /* PTH (mobule: TMU, SCIF234, SPI1, SPI0) */ - PINMUX_GPIO(GPIO_FN_TCLK, TCLK_MARK), - PINMUX_GPIO(GPIO_FN_RXD4, RXD4_MARK), - PINMUX_GPIO(GPIO_FN_TXD4, TXD4_MARK), + /* PTH (mobule: SPI1, LPC, DMAC, ADC) */ PINMUX_GPIO(GPIO_FN_SP1_MOSI, SP1_MOSI_MARK), PINMUX_GPIO(GPIO_FN_SP1_MISO, SP1_MISO_MARK), PINMUX_GPIO(GPIO_FN_SP1_SCK, SP1_SCK_MARK), PINMUX_GPIO(GPIO_FN_SP1_SCK_FB, SP1_SCK_FB_MARK), PINMUX_GPIO(GPIO_FN_SP1_SS0, SP1_SS0_MARK), PINMUX_GPIO(GPIO_FN_SP1_SS1, SP1_SS1_MARK), - PINMUX_GPIO(GPIO_FN_SP0_SS1, SP0_SS1_MARK), + PINMUX_GPIO(GPIO_FN_WP, WP_MARK), + PINMUX_GPIO(GPIO_FN_FMS0, FMS0_MARK), + PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK), + PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), + PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), + PINMUX_GPIO(GPIO_FN_ADTRG1, ADTRG1_MARK), + PINMUX_GPIO(GPIO_FN_ADTRG0, ADTRG0_MARK), - /* PTI (mobule: INTC) */ - PINMUX_GPIO(GPIO_FN_IRQ15, IRQ15_MARK), - PINMUX_GPIO(GPIO_FN_IRQ14, IRQ14_MARK), - PINMUX_GPIO(GPIO_FN_IRQ13, IRQ13_MARK), - PINMUX_GPIO(GPIO_FN_IRQ12, IRQ12_MARK), - PINMUX_GPIO(GPIO_FN_IRQ11, IRQ11_MARK), - PINMUX_GPIO(GPIO_FN_IRQ10, IRQ10_MARK), - PINMUX_GPIO(GPIO_FN_IRQ9, IRQ9_MARK), - PINMUX_GPIO(GPIO_FN_IRQ8, IRQ8_MARK), + /* PTI (mobule: LBSC, SDHI) */ + PINMUX_GPIO(GPIO_FN_D15, D15_MARK), + PINMUX_GPIO(GPIO_FN_D14, D14_MARK), + PINMUX_GPIO(GPIO_FN_D13, D13_MARK), + PINMUX_GPIO(GPIO_FN_D12, D12_MARK), + PINMUX_GPIO(GPIO_FN_D11, D11_MARK), + PINMUX_GPIO(GPIO_FN_D10, D10_MARK), + PINMUX_GPIO(GPIO_FN_D9, D9_MARK), + PINMUX_GPIO(GPIO_FN_D8, D8_MARK), + PINMUX_GPIO(GPIO_FN_SD_WP, SD_WP_MARK), + PINMUX_GPIO(GPIO_FN_SD_CD, SD_CD_MARK), + PINMUX_GPIO(GPIO_FN_SD_CLK, SD_CLK_MARK), + PINMUX_GPIO(GPIO_FN_SD_CMD, SD_CMD_MARK), + PINMUX_GPIO(GPIO_FN_SD_D3, SD_D3_MARK), + PINMUX_GPIO(GPIO_FN_SD_D2, SD_D2_MARK), + PINMUX_GPIO(GPIO_FN_SD_D1, SD_D1_MARK), + PINMUX_GPIO(GPIO_FN_SD_D0, SD_D0_MARK), /* PTJ (mobule: SCIF234, SERMUX) */ - PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK), + PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK), + PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK), PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK), - PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK), - PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK), - PINMUX_GPIO(GPIO_FN_COM1_TXD, COM1_TXD_MARK), - PINMUX_GPIO(GPIO_FN_COM1_RXD, COM1_RXD_MARK), - PINMUX_GPIO(GPIO_FN_COM1_RTS, COM1_RTS_MARK), - PINMUX_GPIO(GPIO_FN_COM1_CTS, COM1_CTS_MARK), + PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK), + PINMUX_GPIO(GPIO_FN_RTS4, RTS4_MARK), + PINMUX_GPIO(GPIO_FN_RXD4, RXD4_MARK), + PINMUX_GPIO(GPIO_FN_TXD4, TXD4_MARK), - /* PTK (mobule: SERMUX) */ + /* PTK (mobule: SERMUX, LBSC, SCIF) */ PINMUX_GPIO(GPIO_FN_COM2_TXD, COM2_TXD_MARK), PINMUX_GPIO(GPIO_FN_COM2_RXD, COM2_RXD_MARK), PINMUX_GPIO(GPIO_FN_COM2_RTS, COM2_RTS_MARK), @@ -1349,62 +1510,65 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_FN_COM2_DTR, COM2_DTR_MARK), PINMUX_GPIO(GPIO_FN_COM2_DSR, COM2_DSR_MARK), PINMUX_GPIO(GPIO_FN_COM2_DCD, COM2_DCD_MARK), - PINMUX_GPIO(GPIO_FN_COM2_RI, COM2_RI_MARK), + PINMUX_GPIO(GPIO_FN_CLKOUT, CLKOUT_MARK), + PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK), + PINMUX_GPIO(GPIO_FN_SCK4, SCK4_MARK), + PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK), - /* PTL (mobule: SERMUX) */ - PINMUX_GPIO(GPIO_FN_RAC_TXD, RAC_TXD_MARK), + /* PTL (mobule: SERMUX, SCIF, LBSC, AUD) */ PINMUX_GPIO(GPIO_FN_RAC_RXD, RAC_RXD_MARK), PINMUX_GPIO(GPIO_FN_RAC_RTS, RAC_RTS_MARK), PINMUX_GPIO(GPIO_FN_RAC_CTS, RAC_CTS_MARK), PINMUX_GPIO(GPIO_FN_RAC_DTR, RAC_DTR_MARK), PINMUX_GPIO(GPIO_FN_RAC_DSR, RAC_DSR_MARK), PINMUX_GPIO(GPIO_FN_RAC_DCD, RAC_DCD_MARK), - PINMUX_GPIO(GPIO_FN_RAC_RI, RAC_RI_MARK), + PINMUX_GPIO(GPIO_FN_RAC_TXD, RAC_TXD_MARK), + PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK), + PINMUX_GPIO(GPIO_FN_CS5, CS5_MARK), + PINMUX_GPIO(GPIO_FN_CS6, CS6_MARK), + PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK), + PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK), + PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK), - /* PTM (mobule: IIC, LPC) */ + /* PTM (mobule: LBSC, IIC) */ + PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK), + PINMUX_GPIO(GPIO_FN_RD, RD_MARK), + PINMUX_GPIO(GPIO_FN_WE0, WE0_MARK), + PINMUX_GPIO(GPIO_FN_CS0, CS0_MARK), PINMUX_GPIO(GPIO_FN_SDA6, SDA6_MARK), PINMUX_GPIO(GPIO_FN_SCL6, SCL6_MARK), PINMUX_GPIO(GPIO_FN_SDA7, SDA7_MARK), PINMUX_GPIO(GPIO_FN_SCL7, SCL7_MARK), - PINMUX_GPIO(GPIO_FN_WP, WP_MARK), - PINMUX_GPIO(GPIO_FN_FMS0, FMS0_MARK), - PINMUX_GPIO(GPIO_FN_FMS1, FMS1_MARK), - /* PTN (mobule: SCIF234, EVC) */ - PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK), - PINMUX_GPIO(GPIO_FN_RTS4, RTS4_MARK), - PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK), - PINMUX_GPIO(GPIO_FN_RTS2, RTS2_MARK), - PINMUX_GPIO(GPIO_FN_CTS4, CTS4_MARK), - PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK), - PINMUX_GPIO(GPIO_FN_CTS2, CTS2_MARK), - PINMUX_GPIO(GPIO_FN_EVENT7, EVENT7_MARK), - PINMUX_GPIO(GPIO_FN_EVENT6, EVENT6_MARK), - PINMUX_GPIO(GPIO_FN_EVENT5, EVENT5_MARK), - PINMUX_GPIO(GPIO_FN_EVENT4, EVENT4_MARK), - PINMUX_GPIO(GPIO_FN_EVENT3, EVENT3_MARK), - PINMUX_GPIO(GPIO_FN_EVENT2, EVENT2_MARK), - PINMUX_GPIO(GPIO_FN_EVENT1, EVENT1_MARK), - PINMUX_GPIO(GPIO_FN_EVENT0, EVENT0_MARK), + /* PTN (mobule: USB, JMC, SGPIO, WDT) */ + PINMUX_GPIO(GPIO_FN_VBUS_EN, VBUS_EN_MARK), + PINMUX_GPIO(GPIO_FN_VBUS_OC, VBUS_OC_MARK), + PINMUX_GPIO(GPIO_FN_JMCTCK, JMCTCK_MARK), + PINMUX_GPIO(GPIO_FN_JMCTMS, JMCTMS_MARK), + PINMUX_GPIO(GPIO_FN_JMCTDO, JMCTDO_MARK), + PINMUX_GPIO(GPIO_FN_JMCTDI, JMCTDI_MARK), + PINMUX_GPIO(GPIO_FN_JMCTRST, JMCTRST_MARK), + PINMUX_GPIO(GPIO_FN_SGPIO1_CLK, SGPIO1_CLK_MARK), + PINMUX_GPIO(GPIO_FN_SGPIO1_LOAD, SGPIO1_LOAD_MARK), + PINMUX_GPIO(GPIO_FN_SGPIO1_DI, SGPIO1_DI_MARK), + PINMUX_GPIO(GPIO_FN_SGPIO1_DO, SGPIO1_DO_MARK), + PINMUX_GPIO(GPIO_FN_SUB_CLKIN, SUB_CLKIN_MARK), - /* PTO (mobule: SGPIO) */ + /* PTO (mobule: SGPIO, SerMux) */ PINMUX_GPIO(GPIO_FN_SGPIO0_CLK, SGPIO0_CLK_MARK), PINMUX_GPIO(GPIO_FN_SGPIO0_LOAD, SGPIO0_LOAD_MARK), PINMUX_GPIO(GPIO_FN_SGPIO0_DI, SGPIO0_DI_MARK), PINMUX_GPIO(GPIO_FN_SGPIO0_DO, SGPIO0_DO_MARK), - PINMUX_GPIO(GPIO_FN_SGPIO1_CLK, SGPIO1_CLK_MARK), - PINMUX_GPIO(GPIO_FN_SGPIO1_LOAD, SGPIO1_LOAD_MARK), - PINMUX_GPIO(GPIO_FN_SGPIO1_DI, SGPIO1_DI_MARK), - PINMUX_GPIO(GPIO_FN_SGPIO1_DO, SGPIO1_DO_MARK), + PINMUX_GPIO(GPIO_FN_SGPIO2_CLK, SGPIO2_CLK_MARK), + PINMUX_GPIO(GPIO_FN_SGPIO2_LOAD, SGPIO2_LOAD_MARK), + PINMUX_GPIO(GPIO_FN_SGPIO2_DI, SGPIO2_DI_MARK), + PINMUX_GPIO(GPIO_FN_SGPIO2_DO, SGPIO2_DO_MARK), + PINMUX_GPIO(GPIO_FN_COM1_TXD, COM1_TXD_MARK), + PINMUX_GPIO(GPIO_FN_COM1_RXD, COM1_RXD_MARK), + PINMUX_GPIO(GPIO_FN_COM1_RTS, COM1_RTS_MARK), + PINMUX_GPIO(GPIO_FN_COM1_CTS, COM1_CTS_MARK), - /* PTP (mobule: JMC, SCIF234) */ - PINMUX_GPIO(GPIO_FN_JMCTCK, JMCTCK_MARK), - PINMUX_GPIO(GPIO_FN_JMCTMS, JMCTMS_MARK), - PINMUX_GPIO(GPIO_FN_JMCTDO, JMCTDO_MARK), - PINMUX_GPIO(GPIO_FN_JMCTDI, JMCTDI_MARK), - PINMUX_GPIO(GPIO_FN_JMCRST, JMCRST_MARK), - PINMUX_GPIO(GPIO_FN_SCK4, SCK4_MARK), - PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK), + /* PTP (mobule: EVC, ADC) */ /* PTQ (mobule: LPC) */ PINMUX_GPIO(GPIO_FN_LAD3, LAD3_MARK), @@ -1439,31 +1603,41 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_FN_SDA3, SDA3_MARK), PINMUX_GPIO(GPIO_FN_SCL3, SCL3_MARK), - /* PTT (mobule: SYSTEM, PWMX) */ - PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK), - PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK), + /* PTT (mobule: PWMX, AUD) */ + PINMUX_GPIO(GPIO_FN_PWMX7, PWMX7_MARK), + PINMUX_GPIO(GPIO_FN_PWMX6, PWMX6_MARK), + PINMUX_GPIO(GPIO_FN_PWMX5, PWMX5_MARK), + PINMUX_GPIO(GPIO_FN_PWMX4, PWMX4_MARK), + PINMUX_GPIO(GPIO_FN_PWMX3, PWMX3_MARK), + PINMUX_GPIO(GPIO_FN_PWMX2, PWMX2_MARK), + PINMUX_GPIO(GPIO_FN_PWMX1, PWMX1_MARK), + PINMUX_GPIO(GPIO_FN_PWMX0, PWMX0_MARK), PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK), PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK), PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK), PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK), - PINMUX_GPIO(GPIO_FN_PWX7, PWX7_MARK), - PINMUX_GPIO(GPIO_FN_PWX6, PWX6_MARK), - PINMUX_GPIO(GPIO_FN_PWX5, PWX5_MARK), - PINMUX_GPIO(GPIO_FN_PWX4, PWX4_MARK), - - /* PTU (mobule: LBSC, DMAC) */ - PINMUX_GPIO(GPIO_FN_CS6, CS6_MARK), - PINMUX_GPIO(GPIO_FN_CS5, CS5_MARK), - PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK), - PINMUX_GPIO(GPIO_FN_CS0, CS0_MARK), - PINMUX_GPIO(GPIO_FN_RD, RD_MARK), - PINMUX_GPIO(GPIO_FN_WE0, WE0_MARK), - PINMUX_GPIO(GPIO_FN_A25, A25_MARK), - PINMUX_GPIO(GPIO_FN_A24, A24_MARK), - PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), - PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), + PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK), + PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), - /* PTV (mobule: LBSC, DMAC) */ + /* PTU (mobule: LPC, APM) */ + PINMUX_GPIO(GPIO_FN_LGPIO7, LGPIO7_MARK), + PINMUX_GPIO(GPIO_FN_LGPIO6, LGPIO6_MARK), + PINMUX_GPIO(GPIO_FN_LGPIO5, LGPIO5_MARK), + PINMUX_GPIO(GPIO_FN_LGPIO4, LGPIO4_MARK), + PINMUX_GPIO(GPIO_FN_LGPIO3, LGPIO3_MARK), + PINMUX_GPIO(GPIO_FN_LGPIO2, LGPIO2_MARK), + PINMUX_GPIO(GPIO_FN_LGPIO1, LGPIO1_MARK), + PINMUX_GPIO(GPIO_FN_LGPIO0, LGPIO0_MARK), + PINMUX_GPIO(GPIO_FN_APMONCTL_O, APMONCTL_O_MARK), + PINMUX_GPIO(GPIO_FN_APMPWBTOUT_O, APMPWBTOUT_O_MARK), + PINMUX_GPIO(GPIO_FN_APMSCI_O, APMSCI_O_MARK), + PINMUX_GPIO(GPIO_FN_APMVDDON, APMVDDON_MARK), + PINMUX_GPIO(GPIO_FN_APMSLPBTN, APMSLPBTN_MARK), + PINMUX_GPIO(GPIO_FN_APMPWRBTN, APMPWRBTN_MARK), + PINMUX_GPIO(GPIO_FN_APMS5N, APMS5N_MARK), + PINMUX_GPIO(GPIO_FN_APMS3N, APMS3N_MARK), + + /* PTV (mobule: LBSC, SerMux, R-SPI, EVC, GRA) */ PINMUX_GPIO(GPIO_FN_A23, A23_MARK), PINMUX_GPIO(GPIO_FN_A22, A22_MARK), PINMUX_GPIO(GPIO_FN_A21, A21_MARK), @@ -1472,12 +1646,20 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_FN_A18, A18_MARK), PINMUX_GPIO(GPIO_FN_A17, A17_MARK), PINMUX_GPIO(GPIO_FN_A16, A16_MARK), - PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK), - PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), - PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), - PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK), + PINMUX_GPIO(GPIO_FN_COM2_RI, COM2_RI_MARK), + PINMUX_GPIO(GPIO_FN_R_SPI_MOSI, R_SPI_MOSI_MARK), + PINMUX_GPIO(GPIO_FN_R_SPI_MISO, R_SPI_MISO_MARK), + PINMUX_GPIO(GPIO_FN_R_SPI_RSPCK, R_SPI_RSPCK_MARK), + PINMUX_GPIO(GPIO_FN_R_SPI_SSL0, R_SPI_SSL0_MARK), + PINMUX_GPIO(GPIO_FN_R_SPI_SSL1, R_SPI_SSL1_MARK), + PINMUX_GPIO(GPIO_FN_EVENT7, EVENT7_MARK), + PINMUX_GPIO(GPIO_FN_EVENT6, EVENT6_MARK), + PINMUX_GPIO(GPIO_FN_VBIOS_DI, VBIOS_DI_MARK), + PINMUX_GPIO(GPIO_FN_VBIOS_DO, VBIOS_DO_MARK), + PINMUX_GPIO(GPIO_FN_VBIOS_CLK, VBIOS_CLK_MARK), + PINMUX_GPIO(GPIO_FN_VBIOS_CS, VBIOS_CS_MARK), - /* PTW (mobule: LBSC) */ + /* PTW (mobule: LBSC, EVC, SCIF) */ PINMUX_GPIO(GPIO_FN_A16, A16_MARK), PINMUX_GPIO(GPIO_FN_A15, A15_MARK), PINMUX_GPIO(GPIO_FN_A14, A14_MARK), @@ -1487,6 +1669,14 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_FN_A10, A10_MARK), PINMUX_GPIO(GPIO_FN_A9, A9_MARK), PINMUX_GPIO(GPIO_FN_A8, A8_MARK), + PINMUX_GPIO(GPIO_FN_EVENT5, EVENT5_MARK), + PINMUX_GPIO(GPIO_FN_EVENT4, EVENT4_MARK), + PINMUX_GPIO(GPIO_FN_EVENT3, EVENT3_MARK), + PINMUX_GPIO(GPIO_FN_EVENT2, EVENT2_MARK), + PINMUX_GPIO(GPIO_FN_EVENT1, EVENT1_MARK), + PINMUX_GPIO(GPIO_FN_EVENT0, EVENT0_MARK), + PINMUX_GPIO(GPIO_FN_CTS4, CTS4_MARK), + PINMUX_GPIO(GPIO_FN_CTS2, CTS2_MARK), /* PTX (mobule: LBSC) */ PINMUX_GPIO(GPIO_FN_A7, A7_MARK), @@ -1497,6 +1687,10 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_FN_A2, A2_MARK), PINMUX_GPIO(GPIO_FN_A1, A1_MARK), PINMUX_GPIO(GPIO_FN_A0, A0_MARK), + PINMUX_GPIO(GPIO_FN_RTS2, RTS2_MARK), + PINMUX_GPIO(GPIO_FN_SIM_D, SIM_D_MARK), + PINMUX_GPIO(GPIO_FN_SIM_CLK, SIM_CLK_MARK), + PINMUX_GPIO(GPIO_FN_SIM_RST, SIM_RST_MARK), /* PTY (mobule: LBSC) */ PINMUX_GPIO(GPIO_FN_D7, D7_MARK), @@ -1507,18 +1701,36 @@ static struct pinmux_gpio pinmux_gpios[] = { PINMUX_GPIO(GPIO_FN_D2, D2_MARK), PINMUX_GPIO(GPIO_FN_D1, D1_MARK), PINMUX_GPIO(GPIO_FN_D0, D0_MARK), + + /* PTZ (mobule: eMMC, ONFI) */ + PINMUX_GPIO(GPIO_FN_MMCDAT7, MMCDAT7_MARK), + PINMUX_GPIO(GPIO_FN_MMCDAT6, MMCDAT6_MARK), + PINMUX_GPIO(GPIO_FN_MMCDAT5, MMCDAT5_MARK), + PINMUX_GPIO(GPIO_FN_MMCDAT4, MMCDAT4_MARK), + PINMUX_GPIO(GPIO_FN_MMCDAT3, MMCDAT3_MARK), + PINMUX_GPIO(GPIO_FN_MMCDAT2, MMCDAT2_MARK), + PINMUX_GPIO(GPIO_FN_MMCDAT1, MMCDAT1_MARK), + PINMUX_GPIO(GPIO_FN_MMCDAT0, MMCDAT0_MARK), + PINMUX_GPIO(GPIO_FN_ON_DQ7, ON_DQ7_MARK), + PINMUX_GPIO(GPIO_FN_ON_DQ6, ON_DQ6_MARK), + PINMUX_GPIO(GPIO_FN_ON_DQ5, ON_DQ5_MARK), + PINMUX_GPIO(GPIO_FN_ON_DQ4, ON_DQ4_MARK), + PINMUX_GPIO(GPIO_FN_ON_DQ3, ON_DQ3_MARK), + PINMUX_GPIO(GPIO_FN_ON_DQ2, ON_DQ2_MARK), + PINMUX_GPIO(GPIO_FN_ON_DQ1, ON_DQ1_MARK), + PINMUX_GPIO(GPIO_FN_ON_DQ0, ON_DQ0_MARK), }; static struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG("PACR", 0xffec0000, 16, 2) { - PTA7_FN, PTA7_OUT, PTA7_IN, 0, - PTA6_FN, PTA6_OUT, PTA6_IN, 0, - PTA5_FN, PTA5_OUT, PTA5_IN, 0, - PTA4_FN, PTA4_OUT, PTA4_IN, 0, - PTA3_FN, PTA3_OUT, PTA3_IN, 0, - PTA2_FN, PTA2_OUT, PTA2_IN, 0, - PTA1_FN, PTA1_OUT, PTA1_IN, 0, - PTA0_FN, PTA0_OUT, PTA0_IN, 0 } + PTA7_FN, PTA7_OUT, PTA7_IN, PTA7_IN_PU, + PTA6_FN, PTA6_OUT, PTA6_IN, PTA6_IN_PU, + PTA5_FN, PTA5_OUT, PTA5_IN, PTA5_IN_PU, + PTA4_FN, PTA4_OUT, PTA4_IN, PTA4_IN_PU, + PTA3_FN, PTA3_OUT, PTA3_IN, PTA3_IN_PU, + PTA2_FN, PTA2_OUT, PTA2_IN, PTA2_IN_PU, + PTA1_FN, PTA1_OUT, PTA1_IN, PTA1_IN_PU, + PTA0_FN, PTA0_OUT, PTA0_IN, PTA0_IN_PU } }, { PINMUX_CFG_REG("PBCR", 0xffec0002, 16, 2) { PTB7_FN, PTB7_OUT, PTB7_IN, 0, @@ -1541,125 +1753,126 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { PTC0_FN, PTC0_OUT, PTC0_IN, 0 } }, { PINMUX_CFG_REG("PDCR", 0xffec0006, 16, 2) { - PTD7_FN, PTD7_OUT, PTD7_IN, 0, - PTD6_FN, PTD6_OUT, PTD6_IN, 0, - PTD5_FN, PTD5_OUT, PTD5_IN, 0, - PTD4_FN, PTD4_OUT, PTD4_IN, 0, - PTD3_FN, PTD3_OUT, PTD3_IN, 0, - PTD2_FN, PTD2_OUT, PTD2_IN, 0, - PTD1_FN, PTD1_OUT, PTD1_IN, 0, - PTD0_FN, PTD0_OUT, PTD0_IN, 0 } + PTD7_FN, PTD7_OUT, PTD7_IN, PTD7_IN_PU, + PTD6_FN, PTD6_OUT, PTD6_IN, PTD6_IN_PU, + PTD5_FN, PTD5_OUT, PTD5_IN, PTD5_IN_PU, + PTD4_FN, PTD4_OUT, PTD4_IN, PTD4_IN_PU, + PTD3_FN, PTD3_OUT, PTD3_IN, PTD3_IN_PU, + PTD2_FN, PTD2_OUT, PTD2_IN, PTD2_IN_PU, + PTD1_FN, PTD1_OUT, PTD1_IN, PTD1_IN_PU, + PTD0_FN, PTD0_OUT, PTD0_IN, PTD0_IN_PU } }, { PINMUX_CFG_REG("PECR", 0xffec0008, 16, 2) { - PTE7_FN, PTE7_OUT, PTE7_IN, 0, - PTE6_FN, PTE6_OUT, PTE6_IN, 0, - PTE5_FN, PTE5_OUT, PTE5_IN, 0, - PTE4_FN, PTE4_OUT, PTE4_IN, 0, - PTE3_FN, PTE3_OUT, PTE3_IN, 0, - PTE2_FN, PTE2_OUT, PTE2_IN, 0, - PTE1_FN, PTE1_OUT, PTE1_IN, 0, - PTE0_FN, PTE0_OUT, PTE0_IN, 0 } + PTE7_FN, PTE7_OUT, PTE7_IN, PTE7_IN_PU, + PTE6_FN, PTE6_OUT, PTE6_IN, PTE6_IN_PU, + PTE5_FN, PTE5_OUT, PTE5_IN, PTE5_IN_PU, + PTE4_FN, PTE4_OUT, PTE4_IN, PTE4_IN_PU, + PTE3_FN, PTE3_OUT, PTE3_IN, PTE3_IN_PU, + PTE2_FN, PTE2_OUT, PTE2_IN, PTE2_IN_PU, + PTE1_FN, PTE1_OUT, PTE1_IN, PTE1_IN_PU, + PTE0_FN, PTE0_OUT, PTE0_IN, PTE0_IN_PU } }, { PINMUX_CFG_REG("PFCR", 0xffec000a, 16, 2) { - PTF7_FN, PTF7_OUT, PTF7_IN, 0, - PTF6_FN, PTF6_OUT, PTF6_IN, 0, - PTF5_FN, PTF5_OUT, PTF5_IN, 0, - PTF4_FN, PTF4_OUT, PTF4_IN, 0, - PTF3_FN, PTF3_OUT, PTF3_IN, 0, - PTF2_FN, PTF2_OUT, PTF2_IN, 0, - PTF1_FN, PTF1_OUT, PTF1_IN, 0, - PTF0_FN, PTF0_OUT, PTF0_IN, 0 } + PTF7_FN, PTF7_OUT, PTF7_IN, PTF7_IN_PU, + PTF6_FN, PTF6_OUT, PTF6_IN, PTF6_IN_PU, + PTF5_FN, PTF5_OUT, PTF5_IN, PTF5_IN_PU, + PTF4_FN, PTF4_OUT, PTF4_IN, PTF4_IN_PU, + PTF3_FN, PTF3_OUT, PTF3_IN, PTF3_IN_PU, + PTF2_FN, PTF2_OUT, PTF2_IN, PTF2_IN_PU, + PTF1_FN, PTF1_OUT, PTF1_IN, PTF1_IN_PU, + PTF0_FN, PTF0_OUT, PTF0_IN, PTF0_IN_PU } }, { PINMUX_CFG_REG("PGCR", 0xffec000c, 16, 2) { - PTG7_FN, PTG7_OUT, PTG7_IN, 0, - PTG6_FN, PTG6_OUT, PTG6_IN, 0, + PTG7_FN, PTG7_OUT, PTG7_IN, PTG7_IN_PU , + PTG6_FN, PTG6_OUT, PTG6_IN, PTG6_IN_PU , PTG5_FN, PTG5_OUT, PTG5_IN, 0, - PTG4_FN, PTG4_OUT, PTG4_IN, 0, + PTG4_FN, PTG4_OUT, PTG4_IN, PTG4_IN_PU , PTG3_FN, PTG3_OUT, PTG3_IN, 0, PTG2_FN, PTG2_OUT, PTG2_IN, 0, PTG1_FN, PTG1_OUT, PTG1_IN, 0, PTG0_FN, PTG0_OUT, PTG0_IN, 0 } }, { PINMUX_CFG_REG("PHCR", 0xffec000e, 16, 2) { - PTH7_FN, PTH7_OUT, PTH7_IN, 0, - PTH6_FN, PTH6_OUT, PTH6_IN, 0, - PTH5_FN, PTH5_OUT, PTH5_IN, 0, - PTH4_FN, PTH4_OUT, PTH4_IN, 0, - PTH3_FN, PTH3_OUT, PTH3_IN, 0, - PTH2_FN, PTH2_OUT, PTH2_IN, 0, - PTH1_FN, PTH1_OUT, PTH1_IN, 0, - PTH0_FN, PTH0_OUT, PTH0_IN, 0 } + PTH7_FN, PTH7_OUT, PTH7_IN, PTH7_IN_PU, + PTH6_FN, PTH6_OUT, PTH6_IN, PTH6_IN_PU, + PTH5_FN, PTH5_OUT, PTH5_IN, PTH5_IN_PU, + PTH4_FN, PTH4_OUT, PTH4_IN, PTH4_IN_PU, + PTH3_FN, PTH3_OUT, PTH3_IN, PTH3_IN_PU, + PTH2_FN, PTH2_OUT, PTH2_IN, PTH2_IN_PU, + PTH1_FN, PTH1_OUT, PTH1_IN, PTH1_IN_PU, + PTH0_FN, PTH0_OUT, PTH0_IN, PTH0_IN_PU } }, { PINMUX_CFG_REG("PICR", 0xffec0010, 16, 2) { - PTI7_FN, PTI7_OUT, PTI7_IN, 0, - PTI6_FN, PTI6_OUT, PTI6_IN, 0, + PTI7_FN, PTI7_OUT, PTI7_IN, PTI7_IN_PU, + PTI6_FN, PTI6_OUT, PTI6_IN, PTI6_IN_PU, PTI5_FN, PTI5_OUT, PTI5_IN, 0, - PTI4_FN, PTI4_OUT, PTI4_IN, 0, - PTI3_FN, PTI3_OUT, PTI3_IN, 0, - PTI2_FN, PTI2_OUT, PTI2_IN, 0, - PTI1_FN, PTI1_OUT, PTI1_IN, 0, - PTI0_FN, PTI0_OUT, PTI0_IN, 0 } + PTI4_FN, PTI4_OUT, PTI4_IN, PTI4_IN_PU, + PTI3_FN, PTI3_OUT, PTI3_IN, PTI3_IN_PU, + PTI2_FN, PTI2_OUT, PTI2_IN, PTI2_IN_PU, + PTI1_FN, PTI1_OUT, PTI1_IN, PTI1_IN_PU, + PTI0_FN, PTI0_OUT, PTI0_IN, PTI0_IN_PU } }, { PINMUX_CFG_REG("PJCR", 0xffec0012, 16, 2) { - PTJ7_FN, PTJ7_OUT, PTJ7_IN, 0, - PTJ6_FN, PTJ6_OUT, PTJ6_IN, 0, - PTJ5_FN, PTJ5_OUT, PTJ5_IN, 0, - PTJ4_FN, PTJ4_OUT, PTJ4_IN, 0, - PTJ3_FN, PTJ3_OUT, PTJ3_IN, 0, - PTJ2_FN, PTJ2_OUT, PTJ2_IN, 0, - PTJ1_FN, PTJ1_OUT, PTJ1_IN, 0, - PTJ0_FN, PTJ0_OUT, PTJ0_IN, 0 } + 0, 0, 0, 0, /* reserved: always set 1 */ + PTJ6_FN, PTJ6_OUT, PTJ6_IN, PTJ6_IN_PU, + PTJ5_FN, PTJ5_OUT, PTJ5_IN, PTJ5_IN_PU, + PTJ4_FN, PTJ4_OUT, PTJ4_IN, PTJ4_IN_PU, + PTJ3_FN, PTJ3_OUT, PTJ3_IN, PTJ3_IN_PU, + PTJ2_FN, PTJ2_OUT, PTJ2_IN, PTJ2_IN_PU, + PTJ1_FN, PTJ1_OUT, PTJ1_IN, PTJ1_IN_PU, + PTJ0_FN, PTJ0_OUT, PTJ0_IN, PTJ0_IN_PU } }, { PINMUX_CFG_REG("PKCR", 0xffec0014, 16, 2) { - PTK7_FN, PTK7_OUT, PTK7_IN, 0, - PTK6_FN, PTK6_OUT, PTK6_IN, 0, - PTK5_FN, PTK5_OUT, PTK5_IN, 0, - PTK4_FN, PTK4_OUT, PTK4_IN, 0, - PTK3_FN, PTK3_OUT, PTK3_IN, 0, - PTK2_FN, PTK2_OUT, PTK2_IN, 0, - PTK1_FN, PTK1_OUT, PTK1_IN, 0, - PTK0_FN, PTK0_OUT, PTK0_IN, 0 } + PTK7_FN, PTK7_OUT, PTK7_IN, PTK7_IN_PU, + PTK6_FN, PTK6_OUT, PTK6_IN, PTK6_IN_PU, + PTK5_FN, PTK5_OUT, PTK5_IN, PTK5_IN_PU, + PTK4_FN, PTK4_OUT, PTK4_IN, PTK4_IN_PU, + PTK3_FN, PTK3_OUT, PTK3_IN, PTK3_IN_PU, + PTK2_FN, PTK2_OUT, PTK2_IN, PTK2_IN_PU, + PTK1_FN, PTK1_OUT, PTK1_IN, PTK1_IN_PU, + PTK0_FN, PTK0_OUT, PTK0_IN, PTK0_IN_PU } }, { PINMUX_CFG_REG("PLCR", 0xffec0016, 16, 2) { - PTL7_FN, PTL7_OUT, PTL7_IN, 0, - PTL6_FN, PTL6_OUT, PTL6_IN, 0, - PTL5_FN, PTL5_OUT, PTL5_IN, 0, - PTL4_FN, PTL4_OUT, PTL4_IN, 0, - PTL3_FN, PTL3_OUT, PTL3_IN, 0, - PTL2_FN, PTL2_OUT, PTL2_IN, 0, - PTL1_FN, PTL1_OUT, PTL1_IN, 0, - PTL0_FN, PTL0_OUT, PTL0_IN, 0 } + 0, 0, 0, 0, /* reserved: always set 1 */ + PTL6_FN, PTL6_OUT, PTL6_IN, PTL6_IN_PU, + PTL5_FN, PTL5_OUT, PTL5_IN, PTL5_IN_PU, + PTL4_FN, PTL4_OUT, PTL4_IN, PTL4_IN_PU, + PTL3_FN, PTL3_OUT, PTL3_IN, PTL3_IN_PU, + PTL2_FN, PTL2_OUT, PTL2_IN, PTL2_IN_PU, + PTL1_FN, PTL1_OUT, PTL1_IN, PTL1_IN_PU, + PTL0_FN, PTL0_OUT, PTL0_IN, PTL0_IN_PU } }, { PINMUX_CFG_REG("PMCR", 0xffec0018, 16, 2) { - 0, 0, 0, 0, /* reserved: always set 1 */ - PTM6_FN, PTM6_OUT, PTM6_IN, 0, - PTM5_FN, PTM5_OUT, PTM5_IN, 0, - PTM4_FN, PTM4_OUT, PTM4_IN, 0, + PTM7_FN, PTM7_OUT, PTM7_IN, PTM7_IN_PU, + PTM6_FN, PTM6_OUT, PTM6_IN, PTM6_IN_PU, + PTM5_FN, PTM5_OUT, PTM5_IN, PTM5_IN_PU, + PTM4_FN, PTM4_OUT, PTM4_IN, PTM4_IN_PU, PTM3_FN, PTM3_OUT, PTM3_IN, 0, PTM2_FN, PTM2_OUT, PTM2_IN, 0, PTM1_FN, PTM1_OUT, PTM1_IN, 0, PTM0_FN, PTM0_OUT, PTM0_IN, 0 } }, { PINMUX_CFG_REG("PNCR", 0xffec001a, 16, 2) { - PTN7_FN, PTN7_OUT, PTN7_IN, 0, + 0, 0, 0, 0, /* reserved: always set 1 */ PTN6_FN, PTN6_OUT, PTN6_IN, 0, PTN5_FN, PTN5_OUT, PTN5_IN, 0, - PTN4_FN, PTN4_OUT, PTN4_IN, 0, - PTN3_FN, PTN3_OUT, PTN3_IN, 0, - PTN2_FN, PTN2_OUT, PTN2_IN, 0, - PTN1_FN, PTN1_OUT, PTN1_IN, 0, - PTN0_FN, PTN0_OUT, PTN0_IN, 0 } + PTN4_FN, PTN4_OUT, PTN4_IN, PTN4_IN_PU, + PTN3_FN, PTN3_OUT, PTN3_IN, PTN3_IN_PU, + PTN2_FN, PTN2_OUT, PTN2_IN, PTN2_IN_PU, + PTN1_FN, PTN1_OUT, PTN1_IN, PTN1_IN_PU, + PTN0_FN, PTN0_OUT, PTN0_IN, PTN0_IN_PU } }, { PINMUX_CFG_REG("POCR", 0xffec001c, 16, 2) { - PTO7_FN, PTO7_OUT, PTO7_IN, 0, - PTO6_FN, PTO6_OUT, PTO6_IN, 0, - PTO5_FN, PTO5_OUT, PTO5_IN, 0, - PTO4_FN, PTO4_OUT, PTO4_IN, 0, - PTO3_FN, PTO3_OUT, PTO3_IN, 0, - PTO2_FN, PTO2_OUT, PTO2_IN, 0, - PTO1_FN, PTO1_OUT, PTO1_IN, 0, - PTO0_FN, PTO0_OUT, PTO0_IN, 0 } + PTO7_FN, PTO7_OUT, PTO7_IN, PTO7_IN_PU, + PTO6_FN, PTO6_OUT, PTO6_IN, PTO6_IN_PU, + PTO5_FN, PTO5_OUT, PTO5_IN, PTO5_IN_PU, + PTO4_FN, PTO4_OUT, PTO4_IN, PTO4_IN_PU, + PTO3_FN, PTO3_OUT, PTO3_IN, PTO3_IN_PU, + PTO2_FN, PTO2_OUT, PTO2_IN, PTO2_IN_PU, + PTO1_FN, PTO1_OUT, PTO1_IN, PTO1_IN_PU, + PTO0_FN, PTO0_OUT, PTO0_IN, PTO0_IN_PU } }, +#if 0 /* FIXME: Remove it? */ { PINMUX_CFG_REG("PPCR", 0xffec001e, 16, 2) { 0, 0, 0, 0, /* reserved: always set 1 */ PTP6_FN, PTP6_OUT, PTP6_IN, 0, @@ -1670,6 +1883,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { PTP1_FN, PTP1_OUT, PTP1_IN, 0, PTP0_FN, PTP0_OUT, PTP0_IN, 0 } }, +#endif { PINMUX_CFG_REG("PQCR", 0xffec0020, 16, 2) { 0, 0, 0, 0, /* reserved: always set 1 */ PTQ6_FN, PTQ6_OUT, PTQ6_IN, 0, @@ -1701,14 +1915,14 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { PTS0_FN, PTS0_OUT, PTS0_IN, 0 } }, { PINMUX_CFG_REG("PTCR", 0xffec0026, 16, 2) { - 0, 0, 0, 0, /* reserved: always set 1 */ - 0, 0, 0, 0, /* reserved: always set 1 */ - PTT5_FN, PTT5_OUT, PTT5_IN, 0, - PTT4_FN, PTT4_OUT, PTT4_IN, 0, - PTT3_FN, PTT3_OUT, PTT3_IN, 0, - PTT2_FN, PTT2_OUT, PTT2_IN, 0, - PTT1_FN, PTT1_OUT, PTT1_IN, 0, - PTT0_FN, PTT0_OUT, PTT0_IN, 0 } + PTT7_FN, PTT7_OUT, PTT7_IN, PTO7_IN_PU, + PTT6_FN, PTT6_OUT, PTT6_IN, PTO6_IN_PU, + PTT5_FN, PTT5_OUT, PTT5_IN, PTO5_IN_PU, + PTT4_FN, PTT4_OUT, PTT4_IN, PTO4_IN_PU, + PTT3_FN, PTT3_OUT, PTT3_IN, PTO3_IN_PU, + PTT2_FN, PTT2_OUT, PTT2_IN, PTO2_IN_PU, + PTT1_FN, PTT1_OUT, PTT1_IN, PTO1_IN_PU, + PTT0_FN, PTT0_OUT, PTT0_IN, PTO0_IN_PU } }, { PINMUX_CFG_REG("PUCR", 0xffec0028, 16, 2) { PTU7_FN, PTU7_OUT, PTU7_IN, PTU7_IN_PU, @@ -1727,16 +1941,16 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { PTV4_FN, PTV4_OUT, PTV4_IN, PTV4_IN_PU, PTV3_FN, PTV3_OUT, PTV3_IN, PTV3_IN_PU, PTV2_FN, PTV2_OUT, PTV2_IN, PTV2_IN_PU, - PTV1_FN, PTV1_OUT, PTV1_IN, PTV1_IN_PU, - PTV0_FN, PTV0_OUT, PTV0_IN, PTV0_IN_PU } + PTV1_FN, PTV1_OUT, PTV1_IN, 0, + PTV0_FN, PTV0_OUT, PTV0_IN, 0 } }, { PINMUX_CFG_REG("PWCR", 0xffec002c, 16, 2) { - PTW7_FN, PTW7_OUT, PTW7_IN, PTW7_IN_PU, - PTW6_FN, PTW6_OUT, PTW6_IN, PTW6_IN_PU, - PTW5_FN, PTW5_OUT, PTW5_IN, PTW5_IN_PU, - PTW4_FN, PTW4_OUT, PTW4_IN, PTW4_IN_PU, - PTW3_FN, PTW3_OUT, PTW3_IN, PTW3_IN_PU, - PTW2_FN, PTW2_OUT, PTW2_IN, PTW2_IN_PU, + PTW7_FN, PTW7_OUT, PTW7_IN, 0, + PTW6_FN, PTW6_OUT, PTW6_IN, 0, + PTW5_FN, PTW5_OUT, PTW5_IN, 0, + PTW4_FN, PTW4_OUT, PTW4_IN, 0, + PTW3_FN, PTW3_OUT, PTW3_IN, 0, + PTW2_FN, PTW2_OUT, PTW2_IN, 0, PTW1_FN, PTW1_OUT, PTW1_IN, PTW1_IN_PU, PTW0_FN, PTW0_OUT, PTW0_IN, PTW0_IN_PU } }, @@ -1761,32 +1975,32 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { PTY0_FN, PTY0_OUT, PTY0_IN, PTY0_IN_PU } }, { PINMUX_CFG_REG("PZCR", 0xffec0032, 16, 2) { - 0, PTZ7_OUT, PTZ7_IN, 0, - 0, PTZ6_OUT, PTZ6_IN, 0, - 0, PTZ5_OUT, PTZ5_IN, 0, - 0, PTZ4_OUT, PTZ4_IN, 0, - 0, PTZ3_OUT, PTZ3_IN, 0, - 0, PTZ2_OUT, PTZ2_IN, 0, - 0, PTZ1_OUT, PTZ1_IN, 0, - 0, PTZ0_OUT, PTZ0_IN, 0 } + PTZ7_FN, PTZ7_OUT, PTZ7_IN, 0, + PTZ6_FN, PTZ6_OUT, PTZ6_IN, 0, + PTZ5_FN, PTZ5_OUT, PTZ5_IN, 0, + PTZ4_FN, PTZ4_OUT, PTZ4_IN, 0, + PTZ3_FN, PTZ3_OUT, PTZ3_IN, 0, + PTZ2_FN, PTZ2_OUT, PTZ2_IN, 0, + PTZ1_FN, PTZ1_OUT, PTZ1_IN, 0, + PTZ0_FN, PTZ0_OUT, PTZ0_IN, 0 } }, { PINMUX_CFG_REG("PSEL0", 0xffec0070, 16, 1) { - PS0_15_FN3, PS0_15_FN1, - PS0_14_FN3, PS0_14_FN1, - PS0_13_FN3, PS0_13_FN1, - PS0_12_FN3, PS0_12_FN1, - 0, 0, - 0, 0, + PS0_15_FN1, PS0_15_FN2, + PS0_14_FN1, PS0_14_FN2, + PS0_13_FN1, PS0_13_FN2, + PS0_12_FN1, PS0_12_FN2, + PS0_11_FN1, PS0_11_FN2, + PS0_10_FN1, PS0_10_FN2, + PS0_9_FN1, PS0_9_FN2, + PS0_8_FN1, PS0_8_FN2, + PS0_7_FN1, PS0_7_FN2, + PS0_6_FN1, PS0_6_FN2, + PS0_5_FN1, PS0_5_FN2, + PS0_4_FN1, PS0_4_FN2, + PS0_3_FN1, PS0_3_FN2, + PS0_2_FN1, PS0_2_FN2, 0, 0, - 0, 0, - PS0_7_FN2, PS0_7_FN1, - PS0_6_FN2, PS0_6_FN1, - PS0_5_FN2, PS0_5_FN1, - PS0_4_FN2, PS0_4_FN1, - PS0_3_FN2, PS0_3_FN1, - PS0_2_FN2, PS0_2_FN1, - PS0_1_FN2, PS0_1_FN1, 0, 0, } }, { PINMUX_CFG_REG("PSEL1", 0xffec0072, 16, 1) { @@ -1795,73 +2009,136 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, + PS1_10_FN1, PS1_10_FN2, + PS1_9_FN1, PS1_9_FN2, + PS1_8_FN1, PS1_8_FN2, 0, 0, 0, 0, 0, 0, - PS1_7_FN1, PS1_7_FN3, - PS1_6_FN1, PS1_6_FN3, - 0, 0, - 0, 0, 0, 0, 0, 0, + PS1_2_FN1, PS1_2_FN2, 0, 0, 0, 0, } }, { PINMUX_CFG_REG("PSEL2", 0xffec0074, 16, 1) { 0, 0, 0, 0, - PS2_13_FN3, PS2_13_FN1, - PS2_12_FN3, PS2_12_FN1, + PS2_13_FN1, PS2_13_FN2, + PS2_12_FN1, PS2_12_FN2, 0, 0, 0, 0, 0, 0, 0, 0, + PS2_7_FN1, PS2_7_FN2, + PS2_6_FN1, PS2_6_FN2, + PS2_5_FN1, PS2_5_FN2, + PS2_4_FN1, PS2_4_FN2, 0, 0, + PS2_2_FN1, PS2_2_FN2, 0, 0, + 0, 0, } + }, + { PINMUX_CFG_REG("PSEL3", 0xffec0076, 16, 1) { + PS3_15_FN1, PS3_15_FN2, + PS3_14_FN1, PS3_14_FN2, + PS3_13_FN1, PS3_13_FN2, + PS3_12_FN1, PS3_12_FN2, + PS3_11_FN1, PS3_11_FN2, + PS3_10_FN1, PS3_10_FN2, + PS3_9_FN1, PS3_9_FN2, + PS3_8_FN1, PS3_8_FN2, + PS3_7_FN1, PS3_7_FN2, 0, 0, 0, 0, 0, 0, 0, 0, - PS2_1_FN1, PS2_1_FN2, - PS2_0_FN1, PS2_0_FN2, } + PS3_2_FN1, PS3_2_FN2, + PS3_1_FN1, PS3_1_FN2, + 0, 0, } }, + { PINMUX_CFG_REG("PSEL4", 0xffec0078, 16, 1) { - PS4_15_FN2, PS4_15_FN1, - PS4_14_FN2, PS4_14_FN1, - PS4_13_FN2, PS4_13_FN1, - PS4_12_FN2, PS4_12_FN1, - PS4_11_FN2, PS4_11_FN1, - PS4_10_FN2, PS4_10_FN1, - PS4_9_FN2, PS4_9_FN1, 0, 0, + PS4_14_FN1, PS4_14_FN2, + PS4_13_FN1, PS4_13_FN2, + PS4_12_FN1, PS4_12_FN2, 0, 0, + PS4_10_FN1, PS4_10_FN2, + PS4_9_FN1, PS4_9_FN2, + PS4_8_FN1, PS4_8_FN2, 0, 0, 0, 0, 0, 0, - PS4_3_FN2, PS4_3_FN1, - PS4_2_FN2, PS4_2_FN1, - PS4_1_FN2, PS4_1_FN1, - PS4_0_FN2, PS4_0_FN1, } + PS4_4_FN1, PS4_4_FN2, + PS4_3_FN1, PS4_3_FN2, + PS4_2_FN1, PS4_2_FN2, + PS4_1_FN1, PS4_1_FN2, + PS4_0_FN1, PS4_0_FN2, } }, { PINMUX_CFG_REG("PSEL5", 0xffec007a, 16, 1) { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, - 0, 0, + PS5_11_FN1, PS5_11_FN2, + PS5_10_FN1, PS5_10_FN2, PS5_9_FN1, PS5_9_FN2, PS5_8_FN1, PS5_8_FN2, PS5_7_FN1, PS5_7_FN2, PS5_6_FN1, PS5_6_FN2, PS5_5_FN1, PS5_5_FN2, + PS5_4_FN1, PS5_4_FN2, + PS5_3_FN1, PS5_3_FN2, + PS5_2_FN1, PS5_2_FN2, + 0, 0, + 0, 0, } + }, + { PINMUX_CFG_REG("PSEL6", 0xffec007c, 16, 1) { + PS6_15_FN1, PS6_15_FN2, + PS6_14_FN1, PS6_14_FN2, + PS6_13_FN1, PS6_13_FN2, + PS6_12_FN1, PS6_12_FN2, + PS6_11_FN1, PS6_11_FN2, + PS6_10_FN1, PS6_10_FN2, + PS6_9_FN1, PS6_9_FN2, + PS6_8_FN1, PS6_8_FN2, + PS6_7_FN1, PS6_7_FN2, + PS6_6_FN1, PS6_6_FN2, + PS6_5_FN1, PS6_5_FN2, + PS6_4_FN1, PS6_4_FN2, + PS6_3_FN1, PS6_3_FN2, + PS6_2_FN1, PS6_2_FN2, + PS6_1_FN1, PS6_1_FN2, + PS6_0_FN1, PS6_0_FN2, } + }, + { PINMUX_CFG_REG("PSEL7", 0xffec0082, 16, 1) { + PS7_15_FN1, PS7_15_FN2, + PS7_14_FN1, PS7_14_FN2, + PS7_13_FN1, PS7_13_FN2, + PS7_12_FN1, PS7_12_FN2, + PS7_11_FN1, PS7_11_FN2, + PS7_10_FN1, PS7_10_FN2, + PS7_9_FN1, PS7_9_FN2, + PS7_8_FN1, PS7_8_FN2, + PS7_7_FN1, PS7_7_FN2, + PS7_6_FN1, PS7_6_FN2, + PS7_5_FN1, PS7_5_FN2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, } }, - { PINMUX_CFG_REG("PSEL6", 0xffec007c, 16, 1) { + { PINMUX_CFG_REG("PSEL8", 0xffec0084, 16, 1) { + PS8_15_FN1, PS8_15_FN2, + PS8_14_FN1, PS8_14_FN2, + PS8_13_FN1, PS8_13_FN2, + PS8_12_FN1, PS8_12_FN2, + PS8_11_FN1, PS8_11_FN2, + PS8_10_FN1, PS8_10_FN2, + PS8_9_FN1, PS8_9_FN2, + PS8_8_FN1, PS8_8_FN2, 0, 0, 0, 0, 0, 0, @@ -1869,15 +2146,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, - 0, 0, - PS6_7_FN_AN, PS6_7_FN_EV, - PS6_6_FN_AN, PS6_6_FN_EV, - PS6_5_FN_AN, PS6_5_FN_EV, - PS6_4_FN_AN, PS6_4_FN_EV, - PS6_3_FN_AN, PS6_3_FN_EV, - PS6_2_FN_AN, PS6_2_FN_EV, - PS6_1_FN_AN, PS6_1_FN_EV, - PS6_0_FN_AN, PS6_0_FN_EV, } + 0, 0, } }, {} }; @@ -1920,7 +2189,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = { PTI3_DATA, PTI2_DATA, PTI1_DATA, PTI0_DATA } }, { PINMUX_DATA_REG("PJDR", 0xffec0046, 8) { - PTJ7_DATA, PTJ6_DATA, PTJ5_DATA, PTJ4_DATA, + 0, PTJ6_DATA, PTJ5_DATA, PTJ4_DATA, PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA } }, { PINMUX_DATA_REG("PKDR", 0xffec0048, 8) { @@ -1928,15 +2197,15 @@ static struct pinmux_data_reg pinmux_data_regs[] = { PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA } }, { PINMUX_DATA_REG("PLDR", 0xffec004a, 8) { - PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA, + 0, PTL6_DATA, PTL5_DATA, PTL4_DATA, PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA } }, { PINMUX_DATA_REG("PMDR", 0xffec004c, 8) { - 0, PTM6_DATA, PTM5_DATA, PTM4_DATA, + PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA, PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA } }, { PINMUX_DATA_REG("PNDR", 0xffec004e, 8) { - PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA, + 0, PTN6_DATA, PTN5_DATA, PTN4_DATA, PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA } }, { PINMUX_DATA_REG("PODR", 0xffec0050, 8) { @@ -1944,7 +2213,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = { PTO3_DATA, PTO2_DATA, PTO1_DATA, PTO0_DATA } }, { PINMUX_DATA_REG("PPDR", 0xffec0052, 8) { - 0, PTP6_DATA, PTP5_DATA, PTP4_DATA, + PTP7_DATA, PTP6_DATA, PTP5_DATA, PTP4_DATA, PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA } }, { PINMUX_DATA_REG("PQDR", 0xffec0054, 8) { @@ -1960,7 +2229,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = { PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA } }, { PINMUX_DATA_REG("PTDR", 0xffec005a, 8) { - 0, 0, PTT5_DATA, PTT4_DATA, + PTT7_DATA, PTT6_DATA, PTT5_DATA, PTT4_DATA, PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA } }, { PINMUX_DATA_REG("PUDR", 0xffec005c, 8) { @@ -2000,8 +2269,8 @@ static struct pinmux_info sh7757_pinmux_info = { .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - .first_gpio = GPIO_PTA7, - .last_gpio = GPIO_FN_D0, + .first_gpio = GPIO_PTA0, + .last_gpio = GPIO_FN_ON_DQ0, .gpios = pinmux_gpios, .cfg_regs = pinmux_config_regs, @@ -2015,5 +2284,4 @@ static int __init plat_pinmux_setup(void) { return register_pinmux(&sh7757_pinmux_info); } - arch_initcall(plat_pinmux_setup); -- cgit v1.1 From 56c52986b163575402c2db83b2fec60234ace1e9 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Tue, 6 Jul 2010 04:32:05 +0000 Subject: sh: modify clock framework of SH7757 Signed-off-by: Yoshihiro Shimoda Signed-off-by: Paul Mundt --- arch/sh/Kconfig | 2 +- arch/sh/kernel/cpu/sh4a/clock-sh7757.c | 199 ++++++++++++++++++--------------- 2 files changed, 112 insertions(+), 89 deletions(-) (limited to 'arch') diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index e6b1f20..4b5a1d5 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -573,7 +573,7 @@ config SH_CLK_CPG config SH_CLK_CPG_LEGACY depends on SH_CLK_CPG def_bool y if !CPU_SUBTYPE_SH7785 && !ARCH_SHMOBILE && \ - !CPU_SUBTYPE_SH7786 + !CPU_SUBTYPE_SH7786 && !CPU_SUBTYPE_SH7757 config SH_CLK_MD int "CPU Mode Pin Setting" diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c index 0a752bd..ce39a2a 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c @@ -3,7 +3,7 @@ * * SH7757 support for the clock framework * - * Copyright (C) 2009 Renesas Solutions Corp. + * Copyright (C) 2009-2010 Renesas Solutions Corp. * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -16,124 +16,147 @@ #include #include -static int ifc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1, - 16, 1, 1, 32, 1, 1, 1, 1 }; -static int sfc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1, - 16, 1, 1, 32, 1, 1, 1, 1 }; -static int bfc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1, - 16, 1, 1, 32, 1, 1, 1, 1 }; -static int p1fc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1, - 16, 1, 1, 32, 1, 1, 1, 1 }; +/* + * Default rate for the root input clock, reset this with clk_set_rate() + * from the platform code. + */ +static struct clk extal_clk = { + .rate = 48000000, +}; -static void master_clk_init(struct clk *clk) +static unsigned long pll_recalc(struct clk *clk) { - clk->rate = CONFIG_SH_PCLK_FREQ * 16; -} + int multiplier; -static struct clk_ops sh7757_master_clk_ops = { - .init = master_clk_init, -}; + multiplier = test_mode_pin(MODE_PIN0) ? 24 : 16; -static void module_clk_recalc(struct clk *clk) -{ - int idx = __raw_readl(FRQCR) & 0x0000000f; - clk->rate = clk->parent->rate / p1fc_divisors[idx]; + return clk->parent->rate * multiplier; } -static struct clk_ops sh7757_module_clk_ops = { - .recalc = module_clk_recalc, +static struct clk_ops pll_clk_ops = { + .recalc = pll_recalc, }; -static void bus_clk_recalc(struct clk *clk) -{ - int idx = (__raw_readl(FRQCR) >> 8) & 0x0000000f; - clk->rate = clk->parent->rate / bfc_divisors[idx]; -} +static struct clk pll_clk = { + .ops = &pll_clk_ops, + .parent = &extal_clk, + .flags = CLK_ENABLE_ON_INIT, +}; -static struct clk_ops sh7757_bus_clk_ops = { - .recalc = bus_clk_recalc, +static struct clk *clks[] = { + &extal_clk, + &pll_clk, }; -static void cpu_clk_recalc(struct clk *clk) -{ - int idx = (__raw_readl(FRQCR) >> 20) & 0x0000000f; - clk->rate = clk->parent->rate / ifc_divisors[idx]; -} +static unsigned int div2[] = { 1, 1, 2, 1, 1, 4, 1, 6, + 1, 1, 1, 16, 1, 24, 1, 1 }; -static struct clk_ops sh7757_cpu_clk_ops = { - .recalc = cpu_clk_recalc, +static struct clk_div_mult_table div4_div_mult_table = { + .divisors = div2, + .nr_divisors = ARRAY_SIZE(div2), }; -static struct clk_ops *sh7757_clk_ops[] = { - &sh7757_master_clk_ops, - &sh7757_module_clk_ops, - &sh7757_bus_clk_ops, - &sh7757_cpu_clk_ops, +static struct clk_div4_table div4_table = { + .div_mult_table = &div4_div_mult_table, }; -void __init arch_init_clk_ops(struct clk_ops **ops, int idx) -{ - if (idx < ARRAY_SIZE(sh7757_clk_ops)) - *ops = sh7757_clk_ops[idx]; -} +enum { DIV4_I, DIV4_SH, DIV4_P, DIV4_NR }; -static void shyway_clk_recalc(struct clk *clk) -{ - int idx = (__raw_readl(FRQCR) >> 12) & 0x0000000f; - clk->rate = clk->parent->rate / sfc_divisors[idx]; -} - -static struct clk_ops sh7757_shyway_clk_ops = { - .recalc = shyway_clk_recalc, -}; +#define DIV4(_bit, _mask, _flags) \ + SH_CLK_DIV4(&pll_clk, FRQCR, _bit, _mask, _flags) -static struct clk sh7757_shyway_clk = { - .flags = CLK_ENABLE_ON_INIT, - .ops = &sh7757_shyway_clk_ops, +struct clk div4_clks[DIV4_NR] = { + /* + * P clock is always enable, because some P clock modules is used + * by Host PC. + */ + [DIV4_P] = DIV4(0, 0x2800, CLK_ENABLE_ON_INIT), + [DIV4_SH] = DIV4(12, 0x00a0, CLK_ENABLE_ON_INIT), + [DIV4_I] = DIV4(20, 0x0004, CLK_ENABLE_ON_INIT), }; -/* - * Additional sh7757-specific on-chip clocks that aren't already part of the - * clock framework - */ -static struct clk *sh7757_onchip_clocks[] = { - &sh7757_shyway_clk, +#define MSTPCR0 0xffc80030 +#define MSTPCR1 0xffc80034 + +enum { MSTP004, MSTP000, MSTP114, MSTP113, MSTP112, + MSTP111, MSTP110, MSTP103, MSTP102, + MSTP_NR }; + +static struct clk mstp_clks[MSTP_NR] = { + /* MSTPCR0 */ + [MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0), + [MSTP000] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 0, 0), + + /* MSTPCR1 */ + [MSTP114] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 14, 0), + [MSTP113] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 13, 0), + [MSTP112] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 12, 0), + [MSTP111] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 11, 0), + [MSTP110] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 10, 0), + [MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 3, 0), + [MSTP102] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 2, 0), }; #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } static struct clk_lookup lookups[] = { /* main clocks */ - CLKDEV_CON_ID("shyway_clk", &sh7757_shyway_clk), + CLKDEV_CON_ID("extal", &extal_clk), + CLKDEV_CON_ID("pll_clk", &pll_clk), + + /* DIV4 clocks */ + CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), + CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), + CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), + + /* MSTP32 clocks */ + CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP004]), + CLKDEV_CON_ID("riic", &mstp_clks[MSTP000]), + { + /* TMU0 */ + .dev_id = "sh_tmu.0", + .con_id = "tmu_fck", + .clk = &mstp_clks[MSTP113], + }, { + /* TMU1 */ + .dev_id = "sh_tmu.1", + .con_id = "tmu_fck", + .clk = &mstp_clks[MSTP114], + }, + { + /* SCIF4 (But, ID is 2) */ + .dev_id = "sh-sci.2", + .con_id = "sci_fck", + .clk = &mstp_clks[MSTP112], + }, { + /* SCIF3 */ + .dev_id = "sh-sci.1", + .con_id = "sci_fck", + .clk = &mstp_clks[MSTP111], + }, { + /* SCIF2 */ + .dev_id = "sh-sci.0", + .con_id = "sci_fck", + .clk = &mstp_clks[MSTP110], + }, + CLKDEV_CON_ID("usb0", &mstp_clks[MSTP102]), }; -static int __init sh7757_clk_init(void) +int __init arch_clk_init(void) { - struct clk *clk = clk_get(NULL, "master_clk"); - int i; - - for (i = 0; i < ARRAY_SIZE(sh7757_onchip_clocks); i++) { - struct clk *clkp = sh7757_onchip_clocks[i]; + int i, ret = 0; - clkp->parent = clk; - clk_register(clkp); - clk_enable(clkp); - } + for (i = 0; i < ARRAY_SIZE(clks); i++) + ret |= clk_register(clks[i]); + for (i = 0; i < ARRAY_SIZE(lookups); i++) + clkdev_add(&lookups[i]); - /* - * Now that we have the rest of the clocks registered, we need to - * force the parent clock to propagate so that these clocks will - * automatically figure out their rate. We cheat by handing the - * parent clock its current rate and forcing child propagation. - */ - clk_set_rate(clk, clk_get_rate(clk)); + if (!ret) + ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks), + &div4_table); + if (!ret) + ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR); - clk_put(clk); - - clkdev_add_table(lookups, ARRAY_SIZE(lookups)); - - return 0; + return ret; } -arch_initcall(sh7757_clk_init); - -- cgit v1.1 From 36239c6704b71da7fb8e2a9429e159a84d0c5a3e Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Tue, 6 Jul 2010 04:32:16 +0000 Subject: sh: add sh7757lcr board support This adds preliminary support for the sh7757lcr board. Signed-off-by: Yoshihiro Shimoda Signed-off-by: Paul Mundt --- arch/sh/boards/Kconfig | 5 + arch/sh/boards/Makefile | 1 + arch/sh/boards/board-sh7757lcr.c | 374 ++++++++++++ arch/sh/configs/sh7757lcr_defconfig | 1126 +++++++++++++++++++++++++++++++++++ arch/sh/tools/mach-types | 1 + 5 files changed, 1507 insertions(+) create mode 100644 arch/sh/boards/board-sh7757lcr.c create mode 100644 arch/sh/configs/sh7757lcr_defconfig (limited to 'arch') diff --git a/arch/sh/boards/Kconfig b/arch/sh/boards/Kconfig index 65abfd4..90ed1ec 100644 --- a/arch/sh/boards/Kconfig +++ b/arch/sh/boards/Kconfig @@ -165,6 +165,11 @@ config SH_HIGHLANDER select SYS_SUPPORTS_PCI select IO_TRAPPED if MMU +config SH_SH7757LCR + bool "SH7757LCR" + depends on CPU_SUBTYPE_SH7757 + select ARCH_REQUIRE_GPIOLIB + config SH_SH7785LCR bool "SH7785LCR" depends on CPU_SUBTYPE_SH7785 diff --git a/arch/sh/boards/Makefile b/arch/sh/boards/Makefile index 2049d95..38ef655 100644 --- a/arch/sh/boards/Makefile +++ b/arch/sh/boards/Makefile @@ -10,3 +10,4 @@ obj-$(CONFIG_SH_EDOSK7760) += board-edosk7760.o obj-$(CONFIG_SH_ESPT) += board-espt.o obj-$(CONFIG_SH_POLARIS) += board-polaris.o obj-$(CONFIG_SH_TITAN) += board-titan.o +obj-$(CONFIG_SH_SH7757LCR) += board-sh7757lcr.o diff --git a/arch/sh/boards/board-sh7757lcr.c b/arch/sh/boards/board-sh7757lcr.c new file mode 100644 index 0000000..c475f10 --- /dev/null +++ b/arch/sh/boards/board-sh7757lcr.c @@ -0,0 +1,374 @@ +/* + * Renesas R0P7757LC0012RL Support. + * + * Copyright (C) 2009 - 2010 Renesas Solutions Corp. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct resource heartbeat_resource = { + .start = 0xffec005c, /* PUDR */ + .end = 0xffec005c, + .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT, +}; + +static unsigned char heartbeat_bit_pos[] = { 0, 1, 2, 3 }; + +static struct heartbeat_data heartbeat_data = { + .bit_pos = heartbeat_bit_pos, + .nr_bits = ARRAY_SIZE(heartbeat_bit_pos), + .flags = HEARTBEAT_INVERTED, +}; + +static struct platform_device heartbeat_device = { + .name = "heartbeat", + .id = -1, + .dev = { + .platform_data = &heartbeat_data, + }, + .num_resources = 1, + .resource = &heartbeat_resource, +}; + +/* Fast Ethernet */ +static struct resource sh_eth0_resources[] = { + { + .start = 0xfef00000, + .end = 0xfef001ff, + .flags = IORESOURCE_MEM, + }, { + .start = 84, + .end = 84, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct sh_eth_plat_data sh7757_eth0_pdata = { + .phy = 1, + .edmac_endian = EDMAC_LITTLE_ENDIAN, +}; + +static struct platform_device sh7757_eth0_device = { + .name = "sh-eth", + .resource = sh_eth0_resources, + .id = 0, + .num_resources = ARRAY_SIZE(sh_eth0_resources), + .dev = { + .platform_data = &sh7757_eth0_pdata, + }, +}; + +static struct resource sh_eth1_resources[] = { + { + .start = 0xfef00800, + .end = 0xfef009ff, + .flags = IORESOURCE_MEM, + }, { + .start = 84, + .end = 84, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct sh_eth_plat_data sh7757_eth1_pdata = { + .phy = 1, + .edmac_endian = EDMAC_LITTLE_ENDIAN, +}; + +static struct platform_device sh7757_eth1_device = { + .name = "sh-eth", + .resource = sh_eth1_resources, + .id = 1, + .num_resources = ARRAY_SIZE(sh_eth1_resources), + .dev = { + .platform_data = &sh7757_eth1_pdata, + }, +}; + +static struct platform_device *sh7757lcr_devices[] __initdata = { + &heartbeat_device, + &sh7757_eth0_device, + &sh7757_eth1_device, +}; + +static int __init sh7757lcr_devices_setup(void) +{ + /* RGMII (PTA) */ + gpio_request(GPIO_FN_ET0_MDC, NULL); + gpio_request(GPIO_FN_ET0_MDIO, NULL); + gpio_request(GPIO_FN_ET1_MDC, NULL); + gpio_request(GPIO_FN_ET1_MDIO, NULL); + + /* ONFI (PTB, PTZ) */ + gpio_request(GPIO_FN_ON_NRE, NULL); + gpio_request(GPIO_FN_ON_NWE, NULL); + gpio_request(GPIO_FN_ON_NWP, NULL); + gpio_request(GPIO_FN_ON_NCE0, NULL); + gpio_request(GPIO_FN_ON_R_B0, NULL); + gpio_request(GPIO_FN_ON_ALE, NULL); + gpio_request(GPIO_FN_ON_CLE, NULL); + + gpio_request(GPIO_FN_ON_DQ7, NULL); + gpio_request(GPIO_FN_ON_DQ6, NULL); + gpio_request(GPIO_FN_ON_DQ5, NULL); + gpio_request(GPIO_FN_ON_DQ4, NULL); + gpio_request(GPIO_FN_ON_DQ3, NULL); + gpio_request(GPIO_FN_ON_DQ2, NULL); + gpio_request(GPIO_FN_ON_DQ1, NULL); + gpio_request(GPIO_FN_ON_DQ0, NULL); + + /* IRQ8 to 0 (PTB, PTC) */ + gpio_request(GPIO_FN_IRQ8, NULL); + gpio_request(GPIO_FN_IRQ7, NULL); + gpio_request(GPIO_FN_IRQ6, NULL); + gpio_request(GPIO_FN_IRQ5, NULL); + gpio_request(GPIO_FN_IRQ4, NULL); + gpio_request(GPIO_FN_IRQ3, NULL); + gpio_request(GPIO_FN_IRQ2, NULL); + gpio_request(GPIO_FN_IRQ1, NULL); + gpio_request(GPIO_FN_IRQ0, NULL); + + /* SPI0 (PTD) */ + gpio_request(GPIO_FN_SP0_MOSI, NULL); + gpio_request(GPIO_FN_SP0_MISO, NULL); + gpio_request(GPIO_FN_SP0_SCK, NULL); + gpio_request(GPIO_FN_SP0_SCK_FB, NULL); + gpio_request(GPIO_FN_SP0_SS0, NULL); + gpio_request(GPIO_FN_SP0_SS1, NULL); + gpio_request(GPIO_FN_SP0_SS2, NULL); + gpio_request(GPIO_FN_SP0_SS3, NULL); + + /* RMII 0/1 (PTE, PTF) */ + gpio_request(GPIO_FN_RMII0_CRS_DV, NULL); + gpio_request(GPIO_FN_RMII0_TXD1, NULL); + gpio_request(GPIO_FN_RMII0_TXD0, NULL); + gpio_request(GPIO_FN_RMII0_TXEN, NULL); + gpio_request(GPIO_FN_RMII0_REFCLK, NULL); + gpio_request(GPIO_FN_RMII0_RXD1, NULL); + gpio_request(GPIO_FN_RMII0_RXD0, NULL); + gpio_request(GPIO_FN_RMII0_RX_ER, NULL); + gpio_request(GPIO_FN_RMII1_CRS_DV, NULL); + gpio_request(GPIO_FN_RMII1_TXD1, NULL); + gpio_request(GPIO_FN_RMII1_TXD0, NULL); + gpio_request(GPIO_FN_RMII1_TXEN, NULL); + gpio_request(GPIO_FN_RMII1_REFCLK, NULL); + gpio_request(GPIO_FN_RMII1_RXD1, NULL); + gpio_request(GPIO_FN_RMII1_RXD0, NULL); + gpio_request(GPIO_FN_RMII1_RX_ER, NULL); + + /* eMMC (PTG) */ + gpio_request(GPIO_FN_MMCCLK, NULL); + gpio_request(GPIO_FN_MMCCMD, NULL); + gpio_request(GPIO_FN_MMCDAT7, NULL); + gpio_request(GPIO_FN_MMCDAT6, NULL); + gpio_request(GPIO_FN_MMCDAT5, NULL); + gpio_request(GPIO_FN_MMCDAT4, NULL); + gpio_request(GPIO_FN_MMCDAT3, NULL); + gpio_request(GPIO_FN_MMCDAT2, NULL); + gpio_request(GPIO_FN_MMCDAT1, NULL); + gpio_request(GPIO_FN_MMCDAT0, NULL); + + /* LPC (PTG, PTH, PTQ, PTU) */ + gpio_request(GPIO_FN_SERIRQ, NULL); + gpio_request(GPIO_FN_LPCPD, NULL); + gpio_request(GPIO_FN_LDRQ, NULL); + gpio_request(GPIO_FN_WP, NULL); + gpio_request(GPIO_FN_FMS0, NULL); + gpio_request(GPIO_FN_LAD3, NULL); + gpio_request(GPIO_FN_LAD2, NULL); + gpio_request(GPIO_FN_LAD1, NULL); + gpio_request(GPIO_FN_LAD0, NULL); + gpio_request(GPIO_FN_LFRAME, NULL); + gpio_request(GPIO_FN_LRESET, NULL); + gpio_request(GPIO_FN_LCLK, NULL); + gpio_request(GPIO_FN_LGPIO7, NULL); + gpio_request(GPIO_FN_LGPIO6, NULL); + gpio_request(GPIO_FN_LGPIO5, NULL); + gpio_request(GPIO_FN_LGPIO4, NULL); + + /* SPI1 (PTH) */ + gpio_request(GPIO_FN_SP1_MOSI, NULL); + gpio_request(GPIO_FN_SP1_MISO, NULL); + gpio_request(GPIO_FN_SP1_SCK, NULL); + gpio_request(GPIO_FN_SP1_SCK_FB, NULL); + gpio_request(GPIO_FN_SP1_SS0, NULL); + gpio_request(GPIO_FN_SP1_SS1, NULL); + + /* SDHI (PTI) */ + gpio_request(GPIO_FN_SD_WP, NULL); + gpio_request(GPIO_FN_SD_CD, NULL); + gpio_request(GPIO_FN_SD_CLK, NULL); + gpio_request(GPIO_FN_SD_CMD, NULL); + gpio_request(GPIO_FN_SD_D3, NULL); + gpio_request(GPIO_FN_SD_D2, NULL); + gpio_request(GPIO_FN_SD_D1, NULL); + gpio_request(GPIO_FN_SD_D0, NULL); + + /* SCIF3/4 (PTJ, PTW) */ + gpio_request(GPIO_FN_RTS3, NULL); + gpio_request(GPIO_FN_CTS3, NULL); + gpio_request(GPIO_FN_TXD3, NULL); + gpio_request(GPIO_FN_RXD3, NULL); + gpio_request(GPIO_FN_RTS4, NULL); + gpio_request(GPIO_FN_RXD4, NULL); + gpio_request(GPIO_FN_TXD4, NULL); + gpio_request(GPIO_FN_CTS4, NULL); + + /* SERMUX (PTK, PTL, PTO, PTV) */ + gpio_request(GPIO_FN_COM2_TXD, NULL); + gpio_request(GPIO_FN_COM2_RXD, NULL); + gpio_request(GPIO_FN_COM2_RTS, NULL); + gpio_request(GPIO_FN_COM2_CTS, NULL); + gpio_request(GPIO_FN_COM2_DTR, NULL); + gpio_request(GPIO_FN_COM2_DSR, NULL); + gpio_request(GPIO_FN_COM2_DCD, NULL); + gpio_request(GPIO_FN_COM2_RI, NULL); + gpio_request(GPIO_FN_RAC_RXD, NULL); + gpio_request(GPIO_FN_RAC_RTS, NULL); + gpio_request(GPIO_FN_RAC_CTS, NULL); + gpio_request(GPIO_FN_RAC_DTR, NULL); + gpio_request(GPIO_FN_RAC_DSR, NULL); + gpio_request(GPIO_FN_RAC_DCD, NULL); + gpio_request(GPIO_FN_RAC_TXD, NULL); + gpio_request(GPIO_FN_COM1_TXD, NULL); + gpio_request(GPIO_FN_COM1_RXD, NULL); + gpio_request(GPIO_FN_COM1_RTS, NULL); + gpio_request(GPIO_FN_COM1_CTS, NULL); + + writeb(0x10, 0xfe470000); /* SMR0: SerMux mode 0 */ + + /* IIC (PTM, PTR, PTS) */ + gpio_request(GPIO_FN_SDA7, NULL); + gpio_request(GPIO_FN_SCL7, NULL); + gpio_request(GPIO_FN_SDA6, NULL); + gpio_request(GPIO_FN_SCL6, NULL); + gpio_request(GPIO_FN_SDA5, NULL); + gpio_request(GPIO_FN_SCL5, NULL); + gpio_request(GPIO_FN_SDA4, NULL); + gpio_request(GPIO_FN_SCL4, NULL); + gpio_request(GPIO_FN_SDA3, NULL); + gpio_request(GPIO_FN_SCL3, NULL); + gpio_request(GPIO_FN_SDA2, NULL); + gpio_request(GPIO_FN_SCL2, NULL); + gpio_request(GPIO_FN_SDA1, NULL); + gpio_request(GPIO_FN_SCL1, NULL); + gpio_request(GPIO_FN_SDA0, NULL); + gpio_request(GPIO_FN_SCL0, NULL); + + /* USB (PTN) */ + gpio_request(GPIO_FN_VBUS_EN, NULL); + gpio_request(GPIO_FN_VBUS_OC, NULL); + + /* SGPIO1/0 (PTN, PTO) */ + gpio_request(GPIO_FN_SGPIO1_CLK, NULL); + gpio_request(GPIO_FN_SGPIO1_LOAD, NULL); + gpio_request(GPIO_FN_SGPIO1_DI, NULL); + gpio_request(GPIO_FN_SGPIO1_DO, NULL); + gpio_request(GPIO_FN_SGPIO0_CLK, NULL); + gpio_request(GPIO_FN_SGPIO0_LOAD, NULL); + gpio_request(GPIO_FN_SGPIO0_DI, NULL); + gpio_request(GPIO_FN_SGPIO0_DO, NULL); + + /* WDT (PTN) */ + gpio_request(GPIO_FN_SUB_CLKIN, NULL); + + /* System (PTT) */ + gpio_request(GPIO_FN_STATUS1, NULL); + gpio_request(GPIO_FN_STATUS0, NULL); + + /* PWMX (PTT) */ + gpio_request(GPIO_FN_PWMX1, NULL); + gpio_request(GPIO_FN_PWMX0, NULL); + + /* R-SPI (PTV) */ + gpio_request(GPIO_FN_R_SPI_MOSI, NULL); + gpio_request(GPIO_FN_R_SPI_MISO, NULL); + gpio_request(GPIO_FN_R_SPI_RSPCK, NULL); + gpio_request(GPIO_FN_R_SPI_SSL0, NULL); + gpio_request(GPIO_FN_R_SPI_SSL1, NULL); + + /* EVC (PTV, PTW) */ + gpio_request(GPIO_FN_EVENT7, NULL); + gpio_request(GPIO_FN_EVENT6, NULL); + gpio_request(GPIO_FN_EVENT5, NULL); + gpio_request(GPIO_FN_EVENT4, NULL); + gpio_request(GPIO_FN_EVENT3, NULL); + gpio_request(GPIO_FN_EVENT2, NULL); + gpio_request(GPIO_FN_EVENT1, NULL); + gpio_request(GPIO_FN_EVENT0, NULL); + + /* LED for heartbeat */ + gpio_request(GPIO_PTU3, NULL); + gpio_direction_output(GPIO_PTU3, 1); + gpio_request(GPIO_PTU2, NULL); + gpio_direction_output(GPIO_PTU2, 1); + gpio_request(GPIO_PTU1, NULL); + gpio_direction_output(GPIO_PTU1, 1); + gpio_request(GPIO_PTU0, NULL); + gpio_direction_output(GPIO_PTU0, 1); + + /* control for MDIO of Gigabit Ethernet */ + gpio_request(GPIO_PTT4, NULL); + gpio_direction_output(GPIO_PTT4, 1); + + /* control for eMMC */ + gpio_request(GPIO_PTT7, NULL); /* eMMC_RST# */ + gpio_direction_output(GPIO_PTT7, 0); + gpio_request(GPIO_PTT6, NULL); /* eMMC_INDEX# */ + gpio_direction_output(GPIO_PTT6, 0); + gpio_request(GPIO_PTT5, NULL); /* eMMC_PRST# */ + gpio_direction_output(GPIO_PTT5, 1); + + /* General platform */ + return platform_add_devices(sh7757lcr_devices, + ARRAY_SIZE(sh7757lcr_devices)); +} +arch_initcall(sh7757lcr_devices_setup); + +/* Initialize IRQ setting */ +void __init init_sh7757lcr_IRQ(void) +{ + plat_irq_setup_pins(IRQ_MODE_IRQ7654); + plat_irq_setup_pins(IRQ_MODE_IRQ3210); +} + +/* Initialize the board */ +static void __init sh7757lcr_setup(char **cmdline_p) +{ + printk(KERN_INFO "Renesas R0P7757LC0012RL support.\n"); +} + +static int sh7757lcr_mode_pins(void) +{ + int value = 0; + + /* These are the factory default settings of S3 (Low active). + * If you change these dip switches then you will need to + * adjust the values below as well. + */ + value |= MODE_PIN0; /* Clock Mode: 1 */ + + return value; +} + +/* The Machine Vector */ +static struct sh_machine_vector mv_sh7757lcr __initmv = { + .mv_name = "SH7757LCR", + .mv_setup = sh7757lcr_setup, + .mv_init_irq = init_sh7757lcr_IRQ, + .mv_mode_pins = sh7757lcr_mode_pins, +}; + diff --git a/arch/sh/configs/sh7757lcr_defconfig b/arch/sh/configs/sh7757lcr_defconfig new file mode 100644 index 0000000..635933e --- /dev/null +++ b/arch/sh/configs/sh7757lcr_defconfig @@ -0,0 +1,1126 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.35-rc3 +# Mon Jul 5 20:42:01 2010 +# +CONFIG_SUPERH=y +CONFIG_SUPERH32=y +# CONFIG_SUPERH64 is not set +CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_IRQ_PER_CPU=y +CONFIG_SPARSE_IRQ=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +# CONFIG_ARCH_SUSPEND_POSSIBLE is not set +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_SYS_SUPPORTS_HUGETLBFS=y +CONFIG_SYS_SUPPORTS_TMU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_NO_VIRT_TO_BUS=y +CONFIG_ARCH_HAS_DEFAULT_IDLE=y +CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_BZIP2=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_BSD_PROCESS_ACCT=y +# CONFIG_BSD_PROCESS_ACCT_V3 is not set +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_PERF_COUNTERS is not set +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_HW_BREAKPOINT=y +CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y + +# +# GCOV-based kernel profiling +# +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +# CONFIG_FREEZER is not set + +# +# System type +# +CONFIG_CPU_SH4=y +CONFIG_CPU_SH4A=y +CONFIG_CPU_SHX2=y +# CONFIG_CPU_SUBTYPE_SH7619 is not set +# CONFIG_CPU_SUBTYPE_SH7201 is not set +# CONFIG_CPU_SUBTYPE_SH7203 is not set +# CONFIG_CPU_SUBTYPE_SH7206 is not set +# CONFIG_CPU_SUBTYPE_SH7263 is not set +# CONFIG_CPU_SUBTYPE_MXG is not set +# CONFIG_CPU_SUBTYPE_SH7705 is not set +# CONFIG_CPU_SUBTYPE_SH7706 is not set +# CONFIG_CPU_SUBTYPE_SH7707 is not set +# CONFIG_CPU_SUBTYPE_SH7708 is not set +# CONFIG_CPU_SUBTYPE_SH7709 is not set +# CONFIG_CPU_SUBTYPE_SH7710 is not set +# CONFIG_CPU_SUBTYPE_SH7712 is not set +# CONFIG_CPU_SUBTYPE_SH7720 is not set +# CONFIG_CPU_SUBTYPE_SH7721 is not set +# CONFIG_CPU_SUBTYPE_SH7750 is not set +# CONFIG_CPU_SUBTYPE_SH7091 is not set +# CONFIG_CPU_SUBTYPE_SH7750R is not set +# CONFIG_CPU_SUBTYPE_SH7750S is not set +# CONFIG_CPU_SUBTYPE_SH7751 is not set +# CONFIG_CPU_SUBTYPE_SH7751R is not set +# CONFIG_CPU_SUBTYPE_SH7760 is not set +# CONFIG_CPU_SUBTYPE_SH4_202 is not set +# CONFIG_CPU_SUBTYPE_SH7723 is not set +# CONFIG_CPU_SUBTYPE_SH7724 is not set +CONFIG_CPU_SUBTYPE_SH7757=y +# CONFIG_CPU_SUBTYPE_SH7763 is not set +# CONFIG_CPU_SUBTYPE_SH7770 is not set +# CONFIG_CPU_SUBTYPE_SH7780 is not set +# CONFIG_CPU_SUBTYPE_SH7785 is not set +# CONFIG_CPU_SUBTYPE_SH7786 is not set +# CONFIG_CPU_SUBTYPE_SHX3 is not set +# CONFIG_CPU_SUBTYPE_SH7343 is not set +# CONFIG_CPU_SUBTYPE_SH7722 is not set +# CONFIG_CPU_SUBTYPE_SH7366 is not set + +# +# Memory management options +# +CONFIG_QUICKLIST=y +CONFIG_MMU=y +CONFIG_PAGE_OFFSET=0x80000000 +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_MEMORY_START=0x40000000 +CONFIG_MEMORY_SIZE=0x0f000000 +# CONFIG_29BIT is not set +CONFIG_32BIT=y +CONFIG_PMB=y +CONFIG_X2TLB=y +CONFIG_VSYSCALL=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SPARSEMEM_DEFAULT=y +CONFIG_MAX_ACTIVE_REGIONS=1 +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_IOREMAP_FIXED=y +CONFIG_UNCACHED_MAPPING=y +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_SPARSEMEM_STATIC=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_NR_QUICK=1 +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 + +# +# Cache configuration +# +CONFIG_CACHE_WRITEBACK=y +# CONFIG_CACHE_WRITETHROUGH is not set +# CONFIG_CACHE_OFF is not set + +# +# Processor features +# +CONFIG_CPU_LITTLE_ENDIAN=y +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_SH_FPU=y +# CONFIG_SH_STORE_QUEUES is not set +CONFIG_CPU_HAS_INTEVT=y +CONFIG_CPU_HAS_SR_RB=y +CONFIG_CPU_HAS_FPU=y + +# +# Board support +# +CONFIG_SH_SH7757LCR=y + +# +# Timer and clock configuration +# +CONFIG_SH_TIMER_TMU=y +CONFIG_SH_CLK_CPG=y +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y + +# +# CPU Frequency scaling +# +# CONFIG_CPU_FREQ is not set + +# +# DMA support +# +# CONFIG_SH_DMA is not set + +# +# Companion Chips +# + +# +# Additional SuperH Device Drivers +# +CONFIG_HEARTBEAT=y +# CONFIG_PUSH_SWITCH is not set + +# +# Kernel features +# +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=250 +# CONFIG_SCHED_HRTICK is not set +# CONFIG_KEXEC is not set +# CONFIG_CRASH_DUMP is not set +CONFIG_SECCOMP=y +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_GUSA=y +# CONFIG_INTC_USERIMASK is not set + +# +# Boot options +# +CONFIG_ZERO_PAGE_OFFSET=0x00001000 +CONFIG_BOOT_LINK_OFFSET=0x00800000 +CONFIG_ENTRY_OFFSET=0x00001000 +CONFIG_CMDLINE_OVERWRITE=y +# CONFIG_CMDLINE_EXTEND is not set +CONFIG_CMDLINE="console=ttySC2,115200 root=/dev/nfs ip=dhcp" + +# +# Bus options +# +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options (EXPERIMENTAL) +# +# CONFIG_PM is not set +# CONFIG_CPU_IDLE is not set +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=y +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=y +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_FW_LOADER is not set +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_HD is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +CONFIG_VITESSE_PHY=y +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_FIXED_PHY is not set +CONFIG_MDIO_BITBANG=y +# CONFIG_MDIO_GPIO is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_STNIC is not set +CONFIG_SH_ETH=y +# CONFIG_SMC91X is not set +# CONFIG_ETHOC is not set +# CONFIG_SMC911X is not set +# CONFIG_SMSC911X is not set +# CONFIG_DNET is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851_MLL is not set +CONFIG_NETDEV_1000=y +# CONFIG_NETDEV_10000 is not set +# CONFIG_WLAN is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_SH_KEYSC is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_INPUT_MOUSE=y +# CONFIG_MOUSE_PS2 is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=2 +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_SH_SCI=y +CONFIG_SERIAL_SH_SCI_NR_UARTS=3 +CONFIG_SERIAL_SH_SCI_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_RAMOOPS is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# +# CONFIG_GPIO_IT8761E is not set + +# +# I2C GPIO expanders: +# + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# + +# +# AC97 GPIO expanders: +# + +# +# MODULbus GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_MFD_SUPPORT=y +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SH_MOBILE_SDHI is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HIDRAW is not set +# CONFIG_HID_PID is not set + +# +# Special HID drivers +# +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +# CONFIG_MSDOS_FS is not set +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLBFS is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +CONFIG_SQUASHFS=y +# CONFIG_SQUASHFS_XATTRS is not set +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +# CONFIG_VXFS_FS is not set +CONFIG_MINIX_FS=y +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +# CONFIG_NFS_V3 is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +CONFIG_NLS_CODEPAGE_932=y +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_DETECT_SOFTLOCKUP is not set +# CONFIG_DETECT_HUNG_TASK is not set +# CONFIG_SCHED_DEBUG is not set +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_FRAME_POINTER is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_SH_STANDARD_BIOS is not set +# CONFIG_STACK_DEBUG is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_4KSTACKS is not set +# CONFIG_DUMP_CODE is not set +# CONFIG_DWARF_UNWINDER is not set +# CONFIG_SH_NO_BSS_INIT is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_MANAGER is not set +# CONFIG_CRYPTO_MANAGER2 is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y +# CONFIG_VIRTUALIZATION is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_HAVE_LMB=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y diff --git a/arch/sh/tools/mach-types b/arch/sh/tools/mach-types index 120a211..9f56eb9 100644 --- a/arch/sh/tools/mach-types +++ b/arch/sh/tools/mach-types @@ -53,6 +53,7 @@ RSK7201 SH_RSK7201 RSK7203 SH_RSK7203 AP325RXA SH_AP325RXA SH2007 SH_SH2007 +SH7757LCR SH_SH7757LCR SH7763RDP SH_SH7763RDP SH7785LCR SH_SH7785LCR SH7785LCR_PT SH_SH7785LCR_PT -- cgit v1.1 From 25897374297906eeebef8864299406bdcb5859c3 Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Tue, 27 Jul 2010 14:13:13 +0200 Subject: x86-32: Align IRQ stacks properly As suggested by Steven Rostedt we need to align the IRQ stacks to the stack size, not just the page size to make them work for stack traces and other things that depend on finding the stack slot itself with 8k stacks. Signed-off-by: Christoph Hellwig LKML-Reference: <20100727121313.GA19976@lst.de> Signed-off-by: H. Peter Anvin --- arch/x86/kernel/irq_32.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/x86/kernel/irq_32.c b/arch/x86/kernel/irq_32.c index 67f5f9f..3b5609f 100644 --- a/arch/x86/kernel/irq_32.c +++ b/arch/x86/kernel/irq_32.c @@ -55,7 +55,7 @@ static inline void print_stack_overflow(void) { } union irq_ctx { struct thread_info tinfo; u32 stack[THREAD_SIZE/sizeof(u32)]; -} __attribute__((aligned(PAGE_SIZE))); +} __attribute__((aligned(THREAD_SIZE))); static DEFINE_PER_CPU(union irq_ctx *, hardirq_ctx); static DEFINE_PER_CPU(union irq_ctx *, softirq_ctx); -- cgit v1.1 From e9a4c4a1a1ad0ac50a4f6db870f8215272aebca0 Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Wed, 28 Jul 2010 13:08:19 +0000 Subject: sh: Add sh7724 BEU resources Signed-off-by: Phil Edworthy Signed-off-by: Paul Mundt --- arch/sh/kernel/cpu/sh4a/setup-sh7724.c | 66 ++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) (limited to 'arch') diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c index 79c556e..828c965 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c @@ -524,6 +524,70 @@ static struct platform_device veu1_device = { }, }; +/* BEU0 */ +static struct uio_info beu0_platform_data = { + .name = "BEU0", + .version = "0", + .irq = evt2irq(0x8A0), +}; + +static struct resource beu0_resources[] = { + [0] = { + .name = "BEU0", + .start = 0xfe930000, + .end = 0xfe933400, + .flags = IORESOURCE_MEM, + }, + [1] = { + /* place holder for contiguous memory */ + }, +}; + +static struct platform_device beu0_device = { + .name = "uio_pdrv_genirq", + .id = 6, + .dev = { + .platform_data = &beu0_platform_data, + }, + .resource = beu0_resources, + .num_resources = ARRAY_SIZE(beu0_resources), + .archdata = { + .hwblk_id = HWBLK_BEU0, + }, +}; + +/* BEU1 */ +static struct uio_info beu1_platform_data = { + .name = "BEU1", + .version = "0", + .irq = evt2irq(0xA00), +}; + +static struct resource beu1_resources[] = { + [0] = { + .name = "BEU1", + .start = 0xfe940000, + .end = 0xfe943400, + .flags = IORESOURCE_MEM, + }, + [1] = { + /* place holder for contiguous memory */ + }, +}; + +static struct platform_device beu1_device = { + .name = "uio_pdrv_genirq", + .id = 7, + .dev = { + .platform_data = &beu1_platform_data, + }, + .resource = beu1_resources, + .num_resources = ARRAY_SIZE(beu1_resources), + .archdata = { + .hwblk_id = HWBLK_BEU1, + }, +}; + static struct sh_timer_config cmt_platform_data = { .channel_offset = 0x60, .timer_bit = 5, @@ -857,6 +921,8 @@ static struct platform_device *sh7724_devices[] __initdata = { &vpu_device, &veu0_device, &veu1_device, + &beu0_device, + &beu1_device, &jpu_device, &spu0_device, &spu1_device, -- cgit v1.1 From 32dfab3ced3a3d2bb0ac2ed6fd7ac395edf02e88 Mon Sep 17 00:00:00 2001 From: Kulikov Vasiliy Date: Wed, 28 Jul 2010 16:39:26 +0000 Subject: sh: dma: check return value of create_proc_read_entry() create_proc_read_entry() may fail, if so return -ENOMEM. Signed-off-by: Kulikov Vasiliy Signed-off-by: Paul Mundt --- arch/sh/drivers/dma/dma-api.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/sh/drivers/dma/dma-api.c b/arch/sh/drivers/dma/dma-api.c index 4a27722..f46848f 100644 --- a/arch/sh/drivers/dma/dma-api.c +++ b/arch/sh/drivers/dma/dma-api.c @@ -412,8 +412,8 @@ EXPORT_SYMBOL(unregister_dmac); static int __init dma_api_init(void) { printk(KERN_NOTICE "DMA: Registering DMA API.\n"); - create_proc_read_entry("dma", 0, 0, dma_read_proc, 0); - return 0; + return create_proc_read_entry("dma", 0, 0, dma_read_proc, 0) + ? 0 : -ENOMEM; } subsys_initcall(dma_api_init); -- cgit v1.1 From 57682827b9a5edb52e33af0be9082b51bffcd5c7 Mon Sep 17 00:00:00 2001 From: Andrew Murray Date: Wed, 4 Aug 2010 16:38:35 +0900 Subject: sh: Use __GFP_ZERO for dma_generic_alloc_coherent(). This follows the x86 change off of memset() and on to an unconditional __GFP_ZERO for wrapping in to optimized page clearing by way of clear_highpage(). Signed-off-by: Andrew Murray Signed-off-by: Paul Mundt --- arch/sh/mm/consistent.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/sh/mm/consistent.c b/arch/sh/mm/consistent.c index c86a085..0387932 100644 --- a/arch/sh/mm/consistent.c +++ b/arch/sh/mm/consistent.c @@ -38,11 +38,12 @@ void *dma_generic_alloc_coherent(struct device *dev, size_t size, void *ret, *ret_nocache; int order = get_order(size); + gfp |= __GFP_ZERO; + ret = (void *)__get_free_pages(gfp, order); if (!ret) return NULL; - memset(ret, 0, size); /* * Pages from the page allocator may have data present in * cache. So flush the cache before using uncached memory. -- cgit v1.1 From eef35c2d41ddcc653c20d26b977acaa45c811e1f Mon Sep 17 00:00:00 2001 From: Stefan Weil Date: Fri, 6 Aug 2010 21:11:15 +0200 Subject: Fix spelling fuction -> function in comments To avoid more patches, I also fixed other spelling and grammar bugs when they were in the same or following line: successfull -> successful parse -> parses controler -> controller controlers -> controllers Cc: Jiri Kosina Cc: linux-kernel@vger.kernel.org Signed-off-by: Stefan Weil Signed-off-by: Jiri Kosina --- arch/blackfin/mach-bf527/boards/ezkit.c | 2 +- arch/blackfin/mach-bf537/boards/stamp.c | 2 +- arch/xtensa/include/asm/uaccess.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c index a05c967..b182afb 100644 --- a/arch/blackfin/mach-bf527/boards/ezkit.c +++ b/arch/blackfin/mach-bf527/boards/ezkit.c @@ -884,7 +884,7 @@ static struct adp5520_keys_platform_data adp5520_keys_data = { }; /* - * ADP5520/5501 Multifuction Device Init Data + * ADP5520/5501 Multifunction Device Init Data */ static struct adp5520_platform_data adp5520_pdev_data = { diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c index 9eaf5b0..b342e1d 100644 --- a/arch/blackfin/mach-bf537/boards/stamp.c +++ b/arch/blackfin/mach-bf537/boards/stamp.c @@ -1644,7 +1644,7 @@ static struct adp5520_keys_platform_data adp5520_keys_data = { }; /* - * ADP5520/5501 Multifuction Device Init Data + * ADP5520/5501 Multifunction Device Init Data */ static struct adp5520_platform_data adp5520_pdev_data = { diff --git a/arch/xtensa/include/asm/uaccess.h b/arch/xtensa/include/asm/uaccess.h index b852842..5b0c18c 100644 --- a/arch/xtensa/include/asm/uaccess.h +++ b/arch/xtensa/include/asm/uaccess.h @@ -4,7 +4,7 @@ * User space memory access functions * * These routines provide basic accessing functions to the user memory - * space for the kernel. This header file provides fuctions such as: + * space for the kernel. This header file provides functions such as: * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive -- cgit v1.1 From 426d31071ac476ea62c62656b242930c17b58c00 Mon Sep 17 00:00:00 2001 From: Paul Bolle Date: Sat, 7 Aug 2010 12:30:03 +0200 Subject: fix printk typo 'faild' Signed-off-by: Paul Bolle Signed-off-by: Jiri Kosina --- arch/arm/mach-omap1/board-nokia770.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c index 8c28b10..bc93afb 100644 --- a/arch/arm/mach-omap1/board-nokia770.c +++ b/arch/arm/mach-omap1/board-nokia770.c @@ -362,7 +362,7 @@ static __init int omap_dsp_init(void) ret = dsp_kfunc_device_register(&nokia770_audio_device); if (ret) { printk(KERN_ERR - "KFUNC device registration faild: %s\n", + "KFUNC device registration failed: %s\n", nokia770_audio_device.name); goto out; } -- cgit v1.1 From f0fba2ad1b6b53d5360125c41953b7afcd6deff0 Mon Sep 17 00:00:00 2001 From: Liam Girdwood Date: Wed, 17 Mar 2010 20:15:21 +0000 Subject: ASoC: multi-component - ASoC Multi-Component Support This patch extends the ASoC API to allow sound cards to have more than one CODEC and more than one platform DMA controller. This is achieved by dividing some current ASoC structures that contain both driver data and device data into structures that only either contain device data or driver data. i.e. struct snd_soc_codec ---> struct snd_soc_codec (device data) +-> struct snd_soc_codec_driver (driver data) struct snd_soc_platform ---> struct snd_soc_platform (device data) +-> struct snd_soc_platform_driver (driver data) struct snd_soc_dai ---> struct snd_soc_dai (device data) +-> struct snd_soc_dai_driver (driver data) struct snd_soc_device ---> deleted This now allows ASoC to be more tightly aligned with the Linux driver model and also means that every ASoC codec, platform and (platform) DAI is a kernel device. ASoC component private data is now stored as device private data. The ASoC sound card struct snd_soc_card has also been updated to store lists of it's components rather than a pointer to a codec and platform. The PCM runtime struct soc_pcm_runtime now has pointers to all its components. This patch adds DAPM support for ASoC multi-component and removes struct snd_soc_socdev from DAPM core. All DAPM calls are now made on a card, codec or runtime PCM level basis rather than using snd_soc_socdev. Other notable multi-component changes:- * Stream operations now de-reference less structures. * close_delayed work() now runs on a DAI basis rather than looping all DAIs in a card. * PM suspend()/resume() operations can now handle N CODECs and Platforms per sound card. * Added soc_bind_dai_link() to bind the component devices to the sound card. * Added soc_dai_link_probe() and soc_dai_link_remove() to probe and remove DAI link components. * sysfs entries can now be registered per component per card. * snd_soc_new_pcms() functionailty rolled into dai_link_probe(). * snd_soc_register_codec() now does all the codec list and mutex init. This patch changes the probe() and remove() of the CODEC drivers as follows:- o Make CODEC driver a platform driver o Moved all struct snd_soc_codec list, mutex, etc initialiasation to core. o Removed all static codec pointers (drivers now support > 1 codec dev) o snd_soc_register_pcms() now done by core. o snd_soc_register_dai() folded into snd_soc_register_codec(). CS4270 portions: Acked-by: Timur Tabi Some TLV320aic23 and Cirrus platform fixes. Signed-off-by: Ryan Mallon TI CODEC and OMAP fixes Signed-off-by: Peter Ujfalusi Signed-off-by: Janusz Krzysztofik Signed-off-by: Jarkko Nikula Samsung platform and misc fixes :- Signed-off-by: Chanwoo Choi Signed-off-by: Joonyoung Shim Signed-off-by: Kyungmin Park Reviewed-by: Jassi Brar Signed-off-by: Seungwhan Youn MPC8610 and PPC fixes. Signed-off-by: Timur Tabi i.MX fixes and some core fixes. Signed-off-by: Sascha Hauer J4740 platform fixes:- Signed-off-by: Lars-Peter Clausen CC: Tony Lindgren CC: Nicolas Ferre CC: Kevin Hilman CC: Sascha Hauer CC: Atsushi Nemoto CC: Kuninori Morimoto CC: Daniel Gloeckner CC: Manuel Lauss CC: Mike Frysinger CC: Arnaud Patard CC: Wan ZongShun Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- arch/arm/mach-davinci/devices.c | 13 +++++++++ arch/arm/mach-ep93xx/core.c | 6 +++++ arch/arm/mach-kirkwood/common.c | 6 +++++ arch/arm/mach-mx2/clock_imx27.c | 4 +-- arch/arm/mach-mx2/devices.c | 2 +- arch/arm/mach-mx3/clock-imx31.c | 4 +-- arch/arm/mach-mx3/clock-imx35.c | 4 +-- arch/arm/mach-mx3/devices.c | 4 +-- arch/arm/mach-omap1/devices.c | 26 ++++++++++++++++++ arch/arm/mach-omap2/board-n8x0.c | 15 +++++++++++ arch/arm/mach-omap2/board-rx51-peripherals.c | 14 +++++++++- arch/arm/mach-omap2/board-zoom2.c | 28 ++++++++++++++++--- arch/arm/mach-omap2/devices.c | 39 +++++++++++++++++++++++++++ arch/arm/mach-omap2/include/mach/board-zoom.h | 2 ++ arch/arm/mach-pxa/devices.c | 25 +++++++++++++++++ arch/arm/mach-pxa/devices.h | 6 +++++ arch/arm/mach-pxa/pxa27x.c | 4 +++ arch/arm/mach-pxa/pxa3xx.c | 5 ++++ arch/arm/mach-pxa/zylonite.c | 11 ++++++++ arch/arm/mach-s3c64xx/dev-audio.c | 13 +++++++++ arch/arm/mach-s3c64xx/mach-smdk6410.c | 1 + arch/arm/plat-mxc/audmux-v2.c | 4 +-- arch/arm/plat-omap/include/plat/mcbsp.h | 7 +++++ arch/arm/plat-s3c24xx/devs.c | 30 +++++++++++++++++++-- arch/arm/plat-samsung/include/plat/devs.h | 2 ++ 25 files changed, 258 insertions(+), 17 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c index 8b7201e..de40e9c 100644 --- a/arch/arm/mach-davinci/devices.c +++ b/arch/arm/mach-davinci/devices.c @@ -295,6 +295,18 @@ static void davinci_init_wdt(void) /*-------------------------------------------------------------------------*/ +struct platform_device davinci_pcm_device = { + .name = "davinci-pcm-audio", + .id = -1, +}; + +static void davinci_init_pcm(void) +{ + platform_device_register(&davinci_pcm_device); +} + +/*-------------------------------------------------------------------------*/ + struct davinci_timer_instance davinci_timer_instance[2] = { { .base = DAVINCI_TIMER0_BASE, @@ -315,6 +327,7 @@ static int __init davinci_init_devices(void) /* please keep these calls, and their implementations above, * in alphabetical order so they're easier to sort through. */ + davinci_init_pcm(); davinci_init_wdt(); return 0; diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c index b4ee540..b5261d4 100644 --- a/arch/arm/mach-ep93xx/core.c +++ b/arch/arm/mach-ep93xx/core.c @@ -732,9 +732,15 @@ static struct platform_device ep93xx_i2s_device = { .resource = ep93xx_i2s_resource, }; +static struct platform_device ep93xx_pcm_device = { + .name = "ep93xx-pcm-audio", + .id = -1, +}; + void __init ep93xx_register_i2s(void) { platform_device_register(&ep93xx_i2s_device); + platform_device_register(&ep93xx_pcm_device); } #define EP93XX_SYSCON_DEVCFG_I2S_MASK (EP93XX_SYSCON_DEVCFG_I2SONSSP | \ diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index e1f3efe..0769013 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -896,10 +896,16 @@ static struct platform_device kirkwood_i2s_device = { }, }; +static struct platform_device kirkwood_pcm_device = { + .name = "kirkwood-pcm", + .id = -1, +}; + void __init kirkwood_audio_init(void) { kirkwood_clk_ctrl |= CGC_AUDIO; platform_device_register(&kirkwood_i2s_device); + platform_device_register(&kirkwood_pcm_device); } /***************************************************************************** diff --git a/arch/arm/mach-mx2/clock_imx27.c b/arch/arm/mach-mx2/clock_imx27.c index 0f0823c..379de9c 100644 --- a/arch/arm/mach-mx2/clock_imx27.c +++ b/arch/arm/mach-mx2/clock_imx27.c @@ -653,8 +653,8 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_clk1) _REGISTER_CLOCK("mxc-ehci.2", "usb", usb_clk) _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_clk1) - _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) - _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) + _REGISTER_CLOCK("imx-ssi-dai.0", NULL, ssi1_clk) + _REGISTER_CLOCK("imx-ssi-dai.1", NULL, ssi2_clk) _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk) _REGISTER_CLOCK(NULL, "vpu", vpu_clk) _REGISTER_CLOCK(NULL, "dma", dma_clk) diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c index a0aeb8a..2354d67 100644 --- a/arch/arm/mach-mx2/devices.c +++ b/arch/arm/mach-mx2/devices.c @@ -415,7 +415,7 @@ struct platform_device mxc_usbh2 = { }; \ \ struct platform_device imx_ssi_device ## n = { \ - .name = "imx-ssi", \ + .name = "imx-ssi-dai", \ .id = n, \ .num_resources = ARRAY_SIZE(imx_ssi_resources ## n), \ .resource = imx_ssi_resources ## n, \ diff --git a/arch/arm/mach-mx3/clock-imx31.c b/arch/arm/mach-mx3/clock-imx31.c index 9a9eb6d..9b52a67 100644 --- a/arch/arm/mach-mx3/clock-imx31.c +++ b/arch/arm/mach-mx3/clock-imx31.c @@ -558,8 +558,8 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk) _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk) _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk) - _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) - _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) + _REGISTER_CLOCK("imx-ssi-dai.0", NULL, ssi1_clk) + _REGISTER_CLOCK("imx-ssi-dai.1", NULL, ssi2_clk) _REGISTER_CLOCK(NULL, "firi", firi_clk) _REGISTER_CLOCK(NULL, "ata", ata_clk) _REGISTER_CLOCK(NULL, "rtic", rtic_clk) diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c index 9f3e943e..7b5acd5 100644 --- a/arch/arm/mach-mx3/clock-imx35.c +++ b/arch/arm/mach-mx3/clock-imx35.c @@ -464,8 +464,8 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK(NULL, "sdma", sdma_clk) _REGISTER_CLOCK(NULL, "spba", spba_clk) _REGISTER_CLOCK(NULL, "spdif", spdif_clk) - _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) - _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) + _REGISTER_CLOCK("imx-ssi-dai.0", NULL, ssi1_clk) + _REGISTER_CLOCK("imx-ssi-dai.1", NULL, ssi2_clk) _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c index db7acd6..27cfc39 100644 --- a/arch/arm/mach-mx3/devices.c +++ b/arch/arm/mach-mx3/devices.c @@ -562,14 +562,14 @@ static struct resource imx_ssi_resources1[] = { }; struct platform_device imx_ssi_device0 = { - .name = "imx-ssi", + .name = "imx-ssi-dai", .id = 0, .num_resources = ARRAY_SIZE(imx_ssi_resources0), .resource = imx_ssi_resources0, }; struct platform_device imx_ssi_device1 = { - .name = "imx-ssi", + .name = "imx-ssi-dai", .id = 1, .num_resources = ARRAY_SIZE(imx_ssi_resources1), .resource = imx_ssi_resources1, diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c index 379100c..eb98eb8 100644 --- a/arch/arm/mach-omap1/devices.c +++ b/arch/arm/mach-omap1/devices.c @@ -25,6 +25,7 @@ #include #include #include +#include /*-------------------------------------------------------------------------*/ @@ -267,6 +268,30 @@ static inline void omap_init_sti(void) static inline void omap_init_sti(void) {} #endif +#if defined(CONFIG_SND_SOC) || defined(CONFIG_SND_SOC_MODULE) + +static struct platform_device omap_pcm = { + .name = "omap-pcm-audio", + .id = -1, +}; + +OMAP_MCBSP_PLATFORM_DEVICE(1); +OMAP_MCBSP_PLATFORM_DEVICE(2); +OMAP_MCBSP_PLATFORM_DEVICE(3); + +static void omap_init_audio(void) +{ + platform_device_register(&omap_mcbsp1); + platform_device_register(&omap_mcbsp2); + if (!cpu_is_omap7xx()) + platform_device_register(&omap_mcbsp3); + platform_device_register(&omap_pcm); +} + +#else +static inline void omap_init_audio(void) {} +#endif + /*-------------------------------------------------------------------------*/ /* @@ -299,6 +324,7 @@ static int __init omap1_init_devices(void) omap_init_rtc(); omap_init_spi100k(); omap_init_sti(); + omap_init_audio(); return 0; } diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c index 3ccc34e..04df912 100644 --- a/arch/arm/mach-omap2/board-n8x0.c +++ b/arch/arm/mach-omap2/board-n8x0.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include @@ -612,11 +613,25 @@ static int n8x0_menelaus_late_init(struct device *dev) return 0; } +static struct aic3x_setup_data n810_aic33_setup = { + .gpio_func[0] = AIC3X_GPIO1_FUNC_DISABLED, + .gpio_func[1] = AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT, +}; + +static struct aic3x_pdata n810_aic33_data = { + .setup = &n810_aic33_setup, + .gpio_reset = -1, +}; + static struct i2c_board_info __initdata n8x0_i2c_board_info_1[] = { { I2C_BOARD_INFO("menelaus", 0x72), .irq = INT_24XX_SYS_NIRQ, }, + { + I2C_BOARD_INFO("tlv320aic3x", 0x1b), + .platform_data = &n810_aic33_data, + }, }; static struct menelaus_platform_data n8x0_menelaus_platform_data = { diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index abdf321..28978c0 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include @@ -686,7 +687,6 @@ static struct twl4030_power_data rx51_t2scripts_data __initdata = { }; - static struct twl4030_platform_data rx51_twldata __initdata = { .irq_base = TWL4030_IRQ_BASE, .irq_end = TWL4030_IRQ_END, @@ -716,9 +716,21 @@ static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_1[] = { }, }; +/* Audio setup data */ +static struct aic3x_setup_data rx51_aic34_setup = { + .gpio_func[0] = AIC3X_GPIO1_FUNC_DISABLED, + .gpio_func[1] = AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT, +}; + +static struct aic3x_pdata rx51_aic34_data = { + .setup = &rx51_aic34_setup, + .gpio_reset = 60, +}; + static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_2[] = { { I2C_BOARD_INFO("tlv320aic3x", 0x18), + .platform_data = &rx51_aic34_data, }, }; diff --git a/arch/arm/mach-omap2/board-zoom2.c b/arch/arm/mach-omap2/board-zoom2.c index 803ef14..410fe00 100644 --- a/arch/arm/mach-omap2/board-zoom2.c +++ b/arch/arm/mach-omap2/board-zoom2.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -34,8 +35,11 @@ static void __init omap_zoom2_init_irq(void) omap_gpio_init(); } -/* REVISIT: These audio entries can be removed once MFD code is merged */ -#if 0 +/* EXTMUTE callback function */ +void zoom2_set_hs_extmute(int mute) +{ + gpio_set_value(ZOOM2_HEADSET_EXTMUTE_GPIO, mute); +} static struct twl4030_madc_platform_data zoom2_madc_data = { .irq_line = 1, @@ -43,6 +47,9 @@ static struct twl4030_madc_platform_data zoom2_madc_data = { static struct twl4030_codec_audio_data zoom2_audio_data = { .audio_mclk = 26000000, + .ramp_delay_value = 3, /* 161 ms */ + .hs_extmute = 1, + .set_hs_extmute = zoom2_set_hs_extmute, }; static struct twl4030_codec_data zoom2_codec_data = { @@ -64,10 +71,24 @@ static struct twl4030_platform_data zoom2_twldata = { .vmmc1 = &zoom2_vmmc1, .vmmc2 = &zoom2_vmmc2, .vsim = &zoom2_vsim, +}; +static struct i2c_board_info __initdata zoom2_i2c_boardinfo[] = { + { + I2C_BOARD_INFO("twl4030", 0x48), + .flags = I2C_CLIENT_WAKE, + .irq = INT_34XX_SYS_NIRQ, + .platform_data = &zoom2_twldata, + }, }; -#endif +static int __init omap3_zoom2_i2c_init(void) +{ + omap_register_i2c_bus(1, 2600, zoom2_i2c_boardinfo, + ARRAY_SIZE(zoom2_i2c_boardinfo)); + return 0; +} + #ifdef CONFIG_OMAP_MUX static struct omap_board_mux board_mux[] __initdata = { @@ -81,6 +102,7 @@ static void __init omap_zoom2_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); zoom_peripherals_init(); + omap3_zoom2_i2c_init(); zoom_debugboard_init(); } diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 03e6c9e..f9a5961 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -29,6 +29,7 @@ #include #include #include +#include #include "mux.h" @@ -289,6 +290,43 @@ static inline void omap_init_sti(void) static inline void omap_init_sti(void) {} #endif +#if defined(CONFIG_SND_SOC) || defined(CONFIG_SND_SOC_MODULE) + +static struct platform_device omap_pcm = { + .name = "omap-pcm-audio", + .id = -1, +}; + +/* + * OMAP2420 has 2 McBSP ports + * OMAP2430 has 5 McBSP ports + * OMAP3 has 5 McBSP ports + * OMAP4 has 4 McBSP ports + */ +OMAP_MCBSP_PLATFORM_DEVICE(1); +OMAP_MCBSP_PLATFORM_DEVICE(2); +OMAP_MCBSP_PLATFORM_DEVICE(3); +OMAP_MCBSP_PLATFORM_DEVICE(4); +OMAP_MCBSP_PLATFORM_DEVICE(5); + +static void omap_init_audio(void) +{ + platform_device_register(&omap_mcbsp1); + platform_device_register(&omap_mcbsp2); + if (cpu_is_omap243x() || cpu_is_omap34xx() || cpu_is_omap44xx()) { + platform_device_register(&omap_mcbsp3); + platform_device_register(&omap_mcbsp4); + } + if (cpu_is_omap243x() || cpu_is_omap34xx()) + platform_device_register(&omap_mcbsp5); + + platform_device_register(&omap_pcm); +} + +#else +static inline void omap_init_audio(void) {} +#endif + #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE) #include @@ -901,6 +939,7 @@ static int __init omap2_init_devices(void) * in alphabetical order so they're easier to sort through. */ omap_hsmmc_reset(); + omap_init_audio(); omap_init_camera(); omap_init_mbox(); omap_init_mcspi(); diff --git a/arch/arm/mach-omap2/include/mach/board-zoom.h b/arch/arm/mach-omap2/include/mach/board-zoom.h index c93b29e..b6a010f 100644 --- a/arch/arm/mach-omap2/include/mach/board-zoom.h +++ b/arch/arm/mach-omap2/include/mach/board-zoom.h @@ -3,3 +3,5 @@ */ extern int __init zoom_debugboard_init(void); extern void __init zoom_peripherals_init(void); + +#define ZOOM2_HEADSET_EXTMUTE_GPIO 153 diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c index 8e10db1..200c31a 100644 --- a/arch/arm/mach-pxa/devices.c +++ b/arch/arm/mach-pxa/devices.c @@ -340,6 +340,31 @@ struct platform_device pxa_device_i2s = { .num_resources = ARRAY_SIZE(pxai2s_resources), }; +struct platform_device pxa_device_asoc_ssp1 = { + .name = "pxa-ssp-dai", + .id = 0, +}; + +struct platform_device pxa_device_asoc_ssp2= { + .name = "pxa-ssp-dai", + .id = 1, +}; + +struct platform_device pxa_device_asoc_ssp3 = { + .name = "pxa-ssp-dai", + .id = 2, +}; + +struct platform_device pxa_device_asoc_ssp4 = { + .name = "pxa-ssp-dai", + .id = 3, +}; + +struct platform_device pxa_device_asoc_platform = { + .name = "pxa-pcm-audio", + .id = -1, +}; + static u64 pxaficp_dmamask = ~(u32)0; struct platform_device pxa_device_ficp = { diff --git a/arch/arm/mach-pxa/devices.h b/arch/arm/mach-pxa/devices.h index 93817d9..506fd57 100644 --- a/arch/arm/mach-pxa/devices.h +++ b/arch/arm/mach-pxa/devices.h @@ -37,4 +37,10 @@ extern struct platform_device pxa3xx_device_i2c_power; extern struct platform_device pxa3xx_device_gcu; +extern struct platform_device pxa_device_asoc_platform; +extern struct platform_device pxa_device_asoc_ssp1; +extern struct platform_device pxa_device_asoc_ssp2; +extern struct platform_device pxa_device_asoc_ssp3; +extern struct platform_device pxa_device_asoc_ssp4; + void __init pxa_register_device(struct platform_device *dev, void *data); diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index 0af3617..4650082 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c @@ -384,6 +384,10 @@ void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info) static struct platform_device *devices[] __initdata = { &pxa27x_device_udc, &pxa_device_i2s, + &pxa_device_asoc_ssp1, + &pxa_device_asoc_ssp2, + &pxa_device_asoc_ssp3, + &pxa_device_asoc_platform, &sa1100_device_rtc, &pxa_device_rtc, &pxa27x_device_ssp1, diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index f544e58..f7a3b15 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c @@ -597,6 +597,11 @@ void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info) static struct platform_device *devices[] __initdata = { &pxa27x_device_udc, &pxa_device_i2s, + &pxa_device_asoc_ssp1, + &pxa_device_asoc_ssp2, + &pxa_device_asoc_ssp3, + &pxa_device_asoc_ssp4, + &pxa_device_asoc_platform, &sa1100_device_rtc, &pxa_device_rtc, &pxa27x_device_ssp1, diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c index c479cbe..5ba9d99 100644 --- a/arch/arm/mach-pxa/zylonite.c +++ b/arch/arm/mach-pxa/zylonite.c @@ -45,6 +45,16 @@ int wm9713_irq; int lcd_id; int lcd_orientation; +struct platform_device pxa_device_wm9713_audio = { + .name = "wm9713-codec", + .id = -1, +}; + +static void __init zylonite_init_wm9713_audio(void) +{ + platform_device_register(&pxa_device_wm9713_audio); +} + static struct resource smc91x_resources[] = { [0] = { .start = ZYLONITE_ETH_PHYS + 0x300, @@ -408,6 +418,7 @@ static void __init zylonite_init(void) zylonite_init_nand(); zylonite_init_leds(); zylonite_init_ohci(); + zylonite_init_wm9713_audio(); } MACHINE_START(ZYLONITE, "PXA3xx Platform Development Kit (aka Zylonite)") diff --git a/arch/arm/mach-s3c64xx/dev-audio.c b/arch/arm/mach-s3c64xx/dev-audio.c index c3e9e73..55ae1b0 100644 --- a/arch/arm/mach-s3c64xx/dev-audio.c +++ b/arch/arm/mach-s3c64xx/dev-audio.c @@ -333,3 +333,16 @@ void __init s3c64xx_ac97_setup_gpio(int num) else s3c_ac97_pdata.cfg_gpio = s3c64xx_ac97_cfg_gpe; } + +static u64 s3c_device_audio_dmamask = 0xffffffffUL; + +struct platform_device s3c_device_pcm = { + .name = "s3c24xx-pcm-audio", + .id = -1, + .dev = { + .dma_mask = &s3c_device_audio_dmamask, + .coherent_dma_mask = 0xffffffffUL + } +}; +EXPORT_SYMBOL(s3c_device_pcm); + diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c index d9a0355..362fc76 100644 --- a/arch/arm/mach-s3c64xx/mach-smdk6410.c +++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c @@ -256,6 +256,7 @@ static struct platform_device *smdk6410_devices[] __initdata = { &s3c_device_fb, &s3c_device_ohci, &s3c_device_usb_hsotg, + &s3c_device_pcm, &s3c64xx_device_iisv4, #ifdef CONFIG_REGULATOR diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c index 0c2cc5c..7c479e4 100644 --- a/arch/arm/plat-mxc/audmux-v2.c +++ b/arch/arm/plat-mxc/audmux-v2.c @@ -49,9 +49,9 @@ static const char *audmux_port_string(int port) { switch (port) { case MX31_AUDMUX_PORT1_SSI0: - return "imx-ssi.0"; + return "imx-ssi-dai.0"; case MX31_AUDMUX_PORT2_SSI1: - return "imx-ssi.1"; + return "imx-ssi-dai.1"; case MX31_AUDMUX_PORT3_SSI_PINS_3: return "SSI3"; case MX31_AUDMUX_PORT4_SSI_PINS_4: diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h index b4ff6a1..5b20103 100644 --- a/arch/arm/plat-omap/include/plat/mcbsp.h +++ b/arch/arm/plat-omap/include/plat/mcbsp.h @@ -30,6 +30,13 @@ #include #include +/* macro for building platform_device for McBSP ports */ +#define OMAP_MCBSP_PLATFORM_DEVICE(port_nr) \ +static struct platform_device omap_mcbsp##port_nr = { \ + .name = "omap-mcbsp-dai", \ + .id = OMAP_MCBSP##port_nr, \ +} + #define OMAP7XX_MCBSP1_BASE 0xfffb1000 #define OMAP7XX_MCBSP2_BASE 0xfffb1800 diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c index 452e184..9f8ee5e 100644 --- a/arch/arm/plat-s3c24xx/devs.c +++ b/arch/arm/plat-s3c24xx/devs.c @@ -481,7 +481,7 @@ static struct resource s3c_ac97_resource[] = { }, }; -static u64 s3c_device_ac97_dmamask = 0xffffffffUL; +static u64 s3c_device_audio_dmamask = 0xffffffffUL; struct platform_device s3c_device_ac97 = { .name = "s3c-ac97", @@ -489,11 +489,37 @@ struct platform_device s3c_device_ac97 = { .num_resources = ARRAY_SIZE(s3c_ac97_resource), .resource = s3c_ac97_resource, .dev = { - .dma_mask = &s3c_device_ac97_dmamask, + .dma_mask = &s3c_device_audio_dmamask, .coherent_dma_mask = 0xffffffffUL } }; EXPORT_SYMBOL(s3c_device_ac97); +/* ASoC PCM DMA */ + +struct platform_device s3c_device_pcm = { + .name = "s3c24xx-pcm-audio", + .id = -1, + .dev = { + .dma_mask = &s3c_device_audio_dmamask, + .coherent_dma_mask = 0xffffffffUL + } +}; + +EXPORT_SYMBOL(s3c_device_pcm); + +/* ASoC I2S */ + +struct platform_device s3c2412_device_iis = { + .name = "s3c2412-iis", + .id = -1, + .dev = { + .dma_mask = &s3c_device_audio_dmamask, + .coherent_dma_mask = 0xffffffffUL + } +}; + +EXPORT_SYMBOL(s3c2412_device_iis); + #endif // CONFIG_CPU_S32440 diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h index e6144e4..9ea6786 100644 --- a/arch/arm/plat-samsung/include/plat/devs.h +++ b/arch/arm/plat-samsung/include/plat/devs.h @@ -32,6 +32,8 @@ extern struct platform_device s3c64xx_device_iisv4; extern struct platform_device s3c64xx_device_spi0; extern struct platform_device s3c64xx_device_spi1; +extern struct platform_device s3c_device_pcm; + extern struct platform_device s3c64xx_device_pcm0; extern struct platform_device s3c64xx_device_pcm1; -- cgit v1.1 From 6e6f66226f0092a39526f8d6f02ebb447d995be2 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Thu, 22 Jul 2010 11:33:30 -0500 Subject: powerpc: rename immap_86xx.h to fsl_guts.h, and add 85xx support The immap_86xx.h header file only defines one data structure: the "global utilities" register set found on Freescale PowerPC SOCs. Rename this file to fsl_guts.h to reflect its true purpose, and extend it to cover the "GUTS" register set on 85xx chips. Signed-off-by: Timur Tabi Acked-by: Mark Brown Acked-by: Kumar Gala Signed-off-by: Liam Girdwood --- arch/powerpc/include/asm/fsl_guts.h | 197 ++++++++++++++++++++++++++++++++++ arch/powerpc/include/asm/immap_86xx.h | 156 --------------------------- 2 files changed, 197 insertions(+), 156 deletions(-) create mode 100644 arch/powerpc/include/asm/fsl_guts.h delete mode 100644 arch/powerpc/include/asm/immap_86xx.h (limited to 'arch') diff --git a/arch/powerpc/include/asm/fsl_guts.h b/arch/powerpc/include/asm/fsl_guts.h new file mode 100644 index 0000000..bebd124 --- /dev/null +++ b/arch/powerpc/include/asm/fsl_guts.h @@ -0,0 +1,197 @@ +/** + * Freecale 85xx and 86xx Global Utilties register set + * + * Authors: Jeff Brown + * Timur Tabi + * + * Copyright 2004,2007 Freescale Semiconductor, Inc + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __ASM_POWERPC_FSL_GUTS_H__ +#define __ASM_POWERPC_FSL_GUTS_H__ +#ifdef __KERNEL__ + +/* + * These #ifdefs are safe because it's not possible to build a kernel that + * runs on e500 and e600 cores. + */ + +#if !defined(CONFIG_PPC_85xx) && !defined(CONFIG_PPC_86xx) +#error Only 85xx and 86xx SOCs are supported +#endif + +/** + * Global Utility Registers. + * + * Not all registers defined in this structure are available on all chips, so + * you are expected to know whether a given register actually exists on your + * chip before you access it. + * + * Also, some registers are similar on different chips but have slightly + * different names. In these cases, one name is chosen to avoid extraneous + * #ifdefs. + */ +#ifdef CONFIG_PPC_85xx +struct ccsr_guts_85xx { +#else +struct ccsr_guts_86xx { +#endif + __be32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */ + __be32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */ + __be32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */ + __be32 pordevsr; /* 0x.000c - POR I/O Device Status Register */ + __be32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */ + __be32 pordevsr2; /* 0x.0014 - POR device status register 2 */ + u8 res018[0x20 - 0x18]; + __be32 porcir; /* 0x.0020 - POR Configuration Information Register */ + u8 res024[0x30 - 0x24]; + __be32 gpiocr; /* 0x.0030 - GPIO Control Register */ + u8 res034[0x40 - 0x34]; + __be32 gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */ + u8 res044[0x50 - 0x44]; + __be32 gpindr; /* 0x.0050 - General-Purpose Input Data Register */ + u8 res054[0x60 - 0x54]; + __be32 pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */ + __be32 pmuxcr2; /* 0x.0064 - Alternate function signal multiplex control 2 */ + __be32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */ + u8 res06c[0x70 - 0x6c]; + __be32 devdisr; /* 0x.0070 - Device Disable Control */ + __be32 devdisr2; /* 0x.0074 - Device Disable Control 2 */ + u8 res078[0x7c - 0x78]; + __be32 pmjcr; /* 0x.007c - 4 Power Management Jog Control Register */ + __be32 powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */ + __be32 pmrccr; /* 0x.0084 - Power Management Reset Counter Configuration Register */ + __be32 pmpdccr; /* 0x.0088 - Power Management Power Down Counter Configuration Register */ + __be32 pmcdr; /* 0x.008c - 4Power management clock disable register */ + __be32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */ + __be32 rstrscr; /* 0x.0094 - Reset Request Status and Control Register */ + __be32 ectrstcr; /* 0x.0098 - Exception reset control register */ + __be32 autorstsr; /* 0x.009c - Automatic reset status register */ + __be32 pvr; /* 0x.00a0 - Processor Version Register */ + __be32 svr; /* 0x.00a4 - System Version Register */ + u8 res0a8[0xb0 - 0xa8]; + __be32 rstcr; /* 0x.00b0 - Reset Control Register */ + u8 res0b4[0xc0 - 0xb4]; +#ifdef CONFIG_PPC_85xx + __be32 iovselsr; /* 0x.00c0 - I/O voltage select status register */ +#else + __be32 elbcvselcr; /* 0x.00c0 - eLBC Voltage Select Ctrl Reg */ +#endif + u8 res0c4[0x224 - 0xc4]; + __be32 iodelay1; /* 0x.0224 - IO delay control register 1 */ + __be32 iodelay2; /* 0x.0228 - IO delay control register 2 */ + u8 res22c[0x800 - 0x22c]; + __be32 clkdvdr; /* 0x.0800 - Clock Divide Register */ + u8 res804[0x900 - 0x804]; + __be32 ircr; /* 0x.0900 - Infrared Control Register */ + u8 res904[0x908 - 0x904]; + __be32 dmacr; /* 0x.0908 - DMA Control Register */ + u8 res90c[0x914 - 0x90c]; + __be32 elbccr; /* 0x.0914 - eLBC Control Register */ + u8 res918[0xb20 - 0x918]; + __be32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */ + __be32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */ + __be32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */ + u8 resb2c[0xe00 - 0xb2c]; + __be32 clkocr; /* 0x.0e00 - Clock Out Select Register */ + u8 rese04[0xe10 - 0xe04]; + __be32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */ + u8 rese14[0xe20 - 0xe14]; + __be32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */ + __be32 cpfor; /* 0x.0e24 - L2 charge pump fuse override register */ + u8 rese28[0xf04 - 0xe28]; + __be32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */ + __be32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */ + u8 resf0c[0xf2c - 0xf0c]; + __be32 itcr; /* 0x.0f2c - Internal transaction control register */ + u8 resf30[0xf40 - 0xf30]; + __be32 srds2cr0; /* 0x.0f40 - SerDes2 Control Register 0 */ + __be32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */ +} __attribute__ ((packed)); + +#ifdef CONFIG_PPC_86xx + +#define CCSR_GUTS_DMACR_DEV_SSI 0 /* DMA controller/channel set to SSI */ +#define CCSR_GUTS_DMACR_DEV_IR 1 /* DMA controller/channel set to IR */ + +/* + * Set the DMACR register in the GUTS + * + * The DMACR register determines the source of initiated transfers for each + * channel on each DMA controller. Rather than have a bunch of repetitive + * macros for the bit patterns, we just have a function that calculates + * them. + * + * guts: Pointer to GUTS structure + * co: The DMA controller (0 or 1) + * ch: The channel on the DMA controller (0, 1, 2, or 3) + * device: The device to set as the source (CCSR_GUTS_DMACR_DEV_xx) + */ +static inline void guts_set_dmacr(struct ccsr_guts_86xx __iomem *guts, + unsigned int co, unsigned int ch, unsigned int device) +{ + unsigned int shift = 16 + (8 * (1 - co) + 2 * (3 - ch)); + + clrsetbits_be32(&guts->dmacr, 3 << shift, device << shift); +} + +#define CCSR_GUTS_PMUXCR_LDPSEL 0x00010000 +#define CCSR_GUTS_PMUXCR_SSI1_MASK 0x0000C000 /* Bitmask for SSI1 */ +#define CCSR_GUTS_PMUXCR_SSI1_LA 0x00000000 /* Latched address */ +#define CCSR_GUTS_PMUXCR_SSI1_HI 0x00004000 /* High impedance */ +#define CCSR_GUTS_PMUXCR_SSI1_SSI 0x00008000 /* Used for SSI1 */ +#define CCSR_GUTS_PMUXCR_SSI2_MASK 0x00003000 /* Bitmask for SSI2 */ +#define CCSR_GUTS_PMUXCR_SSI2_LA 0x00000000 /* Latched address */ +#define CCSR_GUTS_PMUXCR_SSI2_HI 0x00001000 /* High impedance */ +#define CCSR_GUTS_PMUXCR_SSI2_SSI 0x00002000 /* Used for SSI2 */ +#define CCSR_GUTS_PMUXCR_LA_22_25_LA 0x00000000 /* Latched Address */ +#define CCSR_GUTS_PMUXCR_LA_22_25_HI 0x00000400 /* High impedance */ +#define CCSR_GUTS_PMUXCR_DBGDRV 0x00000200 /* Signals not driven */ +#define CCSR_GUTS_PMUXCR_DMA2_0 0x00000008 +#define CCSR_GUTS_PMUXCR_DMA2_3 0x00000004 +#define CCSR_GUTS_PMUXCR_DMA1_0 0x00000002 +#define CCSR_GUTS_PMUXCR_DMA1_3 0x00000001 + +/* + * Set the DMA external control bits in the GUTS + * + * The DMA external control bits in the PMUXCR are only meaningful for + * channels 0 and 3. Any other channels are ignored. + * + * guts: Pointer to GUTS structure + * co: The DMA controller (0 or 1) + * ch: The channel on the DMA controller (0, 1, 2, or 3) + * value: the new value for the bit (0 or 1) + */ +static inline void guts_set_pmuxcr_dma(struct ccsr_guts_86xx __iomem *guts, + unsigned int co, unsigned int ch, unsigned int value) +{ + if ((ch == 0) || (ch == 3)) { + unsigned int shift = 2 * (co + 1) - (ch & 1) - 1; + + clrsetbits_be32(&guts->pmuxcr, 1 << shift, value << shift); + } +} + +#define CCSR_GUTS_CLKDVDR_PXCKEN 0x80000000 +#define CCSR_GUTS_CLKDVDR_SSICKEN 0x20000000 +#define CCSR_GUTS_CLKDVDR_PXCKINV 0x10000000 +#define CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT 25 +#define CCSR_GUTS_CLKDVDR_PXCKDLY_MASK 0x06000000 +#define CCSR_GUTS_CLKDVDR_PXCKDLY(x) \ + (((x) & 3) << CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT) +#define CCSR_GUTS_CLKDVDR_PXCLK_SHIFT 16 +#define CCSR_GUTS_CLKDVDR_PXCLK_MASK 0x001F0000 +#define CCSR_GUTS_CLKDVDR_PXCLK(x) (((x) & 31) << CCSR_GUTS_CLKDVDR_PXCLK_SHIFT) +#define CCSR_GUTS_CLKDVDR_SSICLK_MASK 0x000000FF +#define CCSR_GUTS_CLKDVDR_SSICLK(x) ((x) & CCSR_GUTS_CLKDVDR_SSICLK_MASK) + +#endif + +#endif +#endif diff --git a/arch/powerpc/include/asm/immap_86xx.h b/arch/powerpc/include/asm/immap_86xx.h deleted file mode 100644 index 0f165e5..0000000 --- a/arch/powerpc/include/asm/immap_86xx.h +++ /dev/null @@ -1,156 +0,0 @@ -/** - * MPC86xx Internal Memory Map - * - * Authors: Jeff Brown - * Timur Tabi - * - * Copyright 2004,2007 Freescale Semiconductor, Inc - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * This header file defines structures for various 86xx SOC devices that are - * used by multiple source files. - */ - -#ifndef __ASM_POWERPC_IMMAP_86XX_H__ -#define __ASM_POWERPC_IMMAP_86XX_H__ -#ifdef __KERNEL__ - -/* Global Utility Registers */ -struct ccsr_guts { - __be32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */ - __be32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */ - __be32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */ - __be32 pordevsr; /* 0x.000c - POR I/O Device Status Register */ - __be32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */ - u8 res1[0x20 - 0x14]; - __be32 porcir; /* 0x.0020 - POR Configuration Information Register */ - u8 res2[0x30 - 0x24]; - __be32 gpiocr; /* 0x.0030 - GPIO Control Register */ - u8 res3[0x40 - 0x34]; - __be32 gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */ - u8 res4[0x50 - 0x44]; - __be32 gpindr; /* 0x.0050 - General-Purpose Input Data Register */ - u8 res5[0x60 - 0x54]; - __be32 pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */ - u8 res6[0x70 - 0x64]; - __be32 devdisr; /* 0x.0070 - Device Disable Control */ - __be32 devdisr2; /* 0x.0074 - Device Disable Control 2 */ - u8 res7[0x80 - 0x78]; - __be32 powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */ - u8 res8[0x90 - 0x84]; - __be32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */ - __be32 rstrscr; /* 0x.0094 - Reset Request Status and Control Register */ - u8 res9[0xA0 - 0x98]; - __be32 pvr; /* 0x.00a0 - Processor Version Register */ - __be32 svr; /* 0x.00a4 - System Version Register */ - u8 res10[0xB0 - 0xA8]; - __be32 rstcr; /* 0x.00b0 - Reset Control Register */ - u8 res11[0xC0 - 0xB4]; - __be32 elbcvselcr; /* 0x.00c0 - eLBC Voltage Select Ctrl Reg */ - u8 res12[0x800 - 0xC4]; - __be32 clkdvdr; /* 0x.0800 - Clock Divide Register */ - u8 res13[0x900 - 0x804]; - __be32 ircr; /* 0x.0900 - Infrared Control Register */ - u8 res14[0x908 - 0x904]; - __be32 dmacr; /* 0x.0908 - DMA Control Register */ - u8 res15[0x914 - 0x90C]; - __be32 elbccr; /* 0x.0914 - eLBC Control Register */ - u8 res16[0xB20 - 0x918]; - __be32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */ - __be32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */ - __be32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */ - u8 res17[0xE00 - 0xB2C]; - __be32 clkocr; /* 0x.0e00 - Clock Out Select Register */ - u8 res18[0xE10 - 0xE04]; - __be32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */ - u8 res19[0xE20 - 0xE14]; - __be32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */ - u8 res20[0xF04 - 0xE24]; - __be32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */ - __be32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */ - u8 res21[0xF40 - 0xF0C]; - __be32 srds2cr0; /* 0x.0f40 - SerDes1 Control Register 0 */ - __be32 srds2cr1; /* 0x.0f44 - SerDes1 Control Register 0 */ -} __attribute__ ((packed)); - -#define CCSR_GUTS_DMACR_DEV_SSI 0 /* DMA controller/channel set to SSI */ -#define CCSR_GUTS_DMACR_DEV_IR 1 /* DMA controller/channel set to IR */ - -/* - * Set the DMACR register in the GUTS - * - * The DMACR register determines the source of initiated transfers for each - * channel on each DMA controller. Rather than have a bunch of repetitive - * macros for the bit patterns, we just have a function that calculates - * them. - * - * guts: Pointer to GUTS structure - * co: The DMA controller (0 or 1) - * ch: The channel on the DMA controller (0, 1, 2, or 3) - * device: The device to set as the source (CCSR_GUTS_DMACR_DEV_xx) - */ -static inline void guts_set_dmacr(struct ccsr_guts __iomem *guts, - unsigned int co, unsigned int ch, unsigned int device) -{ - unsigned int shift = 16 + (8 * (1 - co) + 2 * (3 - ch)); - - clrsetbits_be32(&guts->dmacr, 3 << shift, device << shift); -} - -#define CCSR_GUTS_PMUXCR_LDPSEL 0x00010000 -#define CCSR_GUTS_PMUXCR_SSI1_MASK 0x0000C000 /* Bitmask for SSI1 */ -#define CCSR_GUTS_PMUXCR_SSI1_LA 0x00000000 /* Latched address */ -#define CCSR_GUTS_PMUXCR_SSI1_HI 0x00004000 /* High impedance */ -#define CCSR_GUTS_PMUXCR_SSI1_SSI 0x00008000 /* Used for SSI1 */ -#define CCSR_GUTS_PMUXCR_SSI2_MASK 0x00003000 /* Bitmask for SSI2 */ -#define CCSR_GUTS_PMUXCR_SSI2_LA 0x00000000 /* Latched address */ -#define CCSR_GUTS_PMUXCR_SSI2_HI 0x00001000 /* High impedance */ -#define CCSR_GUTS_PMUXCR_SSI2_SSI 0x00002000 /* Used for SSI2 */ -#define CCSR_GUTS_PMUXCR_LA_22_25_LA 0x00000000 /* Latched Address */ -#define CCSR_GUTS_PMUXCR_LA_22_25_HI 0x00000400 /* High impedance */ -#define CCSR_GUTS_PMUXCR_DBGDRV 0x00000200 /* Signals not driven */ -#define CCSR_GUTS_PMUXCR_DMA2_0 0x00000008 -#define CCSR_GUTS_PMUXCR_DMA2_3 0x00000004 -#define CCSR_GUTS_PMUXCR_DMA1_0 0x00000002 -#define CCSR_GUTS_PMUXCR_DMA1_3 0x00000001 - -/* - * Set the DMA external control bits in the GUTS - * - * The DMA external control bits in the PMUXCR are only meaningful for - * channels 0 and 3. Any other channels are ignored. - * - * guts: Pointer to GUTS structure - * co: The DMA controller (0 or 1) - * ch: The channel on the DMA controller (0, 1, 2, or 3) - * value: the new value for the bit (0 or 1) - */ -static inline void guts_set_pmuxcr_dma(struct ccsr_guts __iomem *guts, - unsigned int co, unsigned int ch, unsigned int value) -{ - if ((ch == 0) || (ch == 3)) { - unsigned int shift = 2 * (co + 1) - (ch & 1) - 1; - - clrsetbits_be32(&guts->pmuxcr, 1 << shift, value << shift); - } -} - -#define CCSR_GUTS_CLKDVDR_PXCKEN 0x80000000 -#define CCSR_GUTS_CLKDVDR_SSICKEN 0x20000000 -#define CCSR_GUTS_CLKDVDR_PXCKINV 0x10000000 -#define CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT 25 -#define CCSR_GUTS_CLKDVDR_PXCKDLY_MASK 0x06000000 -#define CCSR_GUTS_CLKDVDR_PXCKDLY(x) \ - (((x) & 3) << CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT) -#define CCSR_GUTS_CLKDVDR_PXCLK_SHIFT 16 -#define CCSR_GUTS_CLKDVDR_PXCLK_MASK 0x001F0000 -#define CCSR_GUTS_CLKDVDR_PXCLK(x) (((x) & 31) << CCSR_GUTS_CLKDVDR_PXCLK_SHIFT) -#define CCSR_GUTS_CLKDVDR_SSICLK_MASK 0x000000FF -#define CCSR_GUTS_CLKDVDR_SSICLK(x) ((x) & CCSR_GUTS_CLKDVDR_SSICLK_MASK) - -#endif /* __ASM_POWERPC_IMMAP_86XX_H__ */ -#endif /* __KERNEL__ */ -- cgit v1.1 From ff71334a46844d0ae6ff0055c549790bcd27bb10 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Wed, 4 Aug 2010 17:51:08 -0500 Subject: asoc/multi-component: fsl: add support for disabled SSI nodes Add support for adding "status = disabled" to an SSI node to incidate that it is not wired on the board. This replaces the not-so-intuitive previous method of omitting a codec-handle property. Signed-off-by: Timur Tabi Acked-by: Kumar Gala Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- arch/powerpc/boot/dts/mpc8610_hpcd.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/powerpc/boot/dts/mpc8610_hpcd.dts b/arch/powerpc/boot/dts/mpc8610_hpcd.dts index 9535ce6..83c3218 100644 --- a/arch/powerpc/boot/dts/mpc8610_hpcd.dts +++ b/arch/powerpc/boot/dts/mpc8610_hpcd.dts @@ -286,6 +286,7 @@ ssi@16100 { compatible = "fsl,mpc8610-ssi"; + status = "disabled"; cell-index = <1>; reg = <0x16100 0x100>; interrupt-parent = <&mpic>; -- cgit v1.1 From e583d6b3c25d4ce3867b345782abd7d11a0d384c Mon Sep 17 00:00:00 2001 From: Sam Ravnborg Date: Sat, 14 Aug 2010 12:23:39 +0000 Subject: sh: fix recursive dependency in Kconfig When executing: make ARCH=sh defconfig kconfig segfaulted. kconfig should obviously not segfault. But this indicated a problem in the sh files which was tracked down to a recursive dependency. We select HAVE_HW_BREAKPOINT and in the following line we use the same symbol in an expression. Drop the conditional as it is of no use. Signed-off-by: Sam Ravnborg Cc: Michal Marek Signed-off-by: Paul Mundt --- arch/sh/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index b2b90ee..2284215 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -46,7 +46,7 @@ config SUPERH32 select HAVE_ARCH_KGDB select HAVE_HW_BREAKPOINT select HAVE_MIXED_BREAKPOINTS_REGS - select PERF_EVENTS if HAVE_HW_BREAKPOINT + select PERF_EVENTS select ARCH_HIBERNATION_POSSIBLE if MMU config SUPERH64 -- cgit v1.1 From 3e497df14d3cb900377094f36eeb8c17cec6f795 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Mon, 16 Aug 2010 13:51:18 +0900 Subject: sh: wire up fanotify/prlimit64 syscalls. Signed-off-by: Paul Mundt --- arch/sh/include/asm/unistd_32.h | 5 ++++- arch/sh/include/asm/unistd_64.h | 5 ++++- arch/sh/kernel/syscalls_32.S | 3 +++ arch/sh/kernel/syscalls_64.S | 3 +++ 4 files changed, 14 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/sh/include/asm/unistd_32.h b/arch/sh/include/asm/unistd_32.h index 0e7f0fc..01183ad 100644 --- a/arch/sh/include/asm/unistd_32.h +++ b/arch/sh/include/asm/unistd_32.h @@ -345,8 +345,11 @@ #define __NR_pwritev 334 #define __NR_rt_tgsigqueueinfo 335 #define __NR_perf_event_open 336 +#define __NR_fanotify_init 337 +#define __NR_fanotify_mark 338 +#define __NR_prlimit64 339 -#define NR_syscalls 337 +#define NR_syscalls 340 #ifdef __KERNEL__ diff --git a/arch/sh/include/asm/unistd_64.h b/arch/sh/include/asm/unistd_64.h index 0580c33..09aa93f 100644 --- a/arch/sh/include/asm/unistd_64.h +++ b/arch/sh/include/asm/unistd_64.h @@ -387,10 +387,13 @@ #define __NR_perf_event_open 364 #define __NR_recvmmsg 365 #define __NR_accept4 366 +#define __NR_fanotify_init 367 +#define __NR_fanotify_mark 368 +#define __NR_prlimit64 369 #ifdef __KERNEL__ -#define NR_syscalls 367 +#define NR_syscalls 370 #define __ARCH_WANT_IPC_PARSE_VERSION #define __ARCH_WANT_OLD_READDIR diff --git a/arch/sh/kernel/syscalls_32.S b/arch/sh/kernel/syscalls_32.S index 19fd11d..3c6d669 100644 --- a/arch/sh/kernel/syscalls_32.S +++ b/arch/sh/kernel/syscalls_32.S @@ -353,3 +353,6 @@ ENTRY(sys_call_table) .long sys_pwritev .long sys_rt_tgsigqueueinfo /* 335 */ .long sys_perf_event_open + .long sys_fanotify_init + .long sys_fanotify_mark + .long sys_prlimit64 diff --git a/arch/sh/kernel/syscalls_64.S b/arch/sh/kernel/syscalls_64.S index 2048a20..6658570 100644 --- a/arch/sh/kernel/syscalls_64.S +++ b/arch/sh/kernel/syscalls_64.S @@ -393,3 +393,6 @@ sys_call_table: .long sys_perf_event_open .long sys_recvmmsg /* 365 */ .long sys_accept4 + .long sys_fanotify_init + .long sys_fanotify_mark + .long sys_prlimit64 -- cgit v1.1 From d5b7fb7bb8a014ee96cd39b410fc57a7dc239a91 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Mon, 16 Aug 2010 14:52:06 +0900 Subject: sh: fix up fallout from syscall arg constification. sys_execve() now takes a const pointer, so reflect this change where the syscall is actually defined, too. Fixes up a build error due to prototype mismatch. Signed-off-by: Paul Mundt --- arch/sh/kernel/process_32.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/sh/kernel/process_32.c b/arch/sh/kernel/process_32.c index 0529819..ee22a58 100644 --- a/arch/sh/kernel/process_32.c +++ b/arch/sh/kernel/process_32.c @@ -296,7 +296,8 @@ asmlinkage int sys_vfork(unsigned long r4, unsigned long r5, /* * sys_execve() executes a new program. */ -asmlinkage int sys_execve(char __user *ufilename, char __user * __user *uargv, +asmlinkage int sys_execve(const char __user *ufilename, + char __user * __user *uargv, char __user * __user *uenvp, unsigned long r7, struct pt_regs __regs) { -- cgit v1.1 From a8dc49b51ace4ff80cb764c250338cb9b311fb14 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Mon, 16 Aug 2010 14:53:01 +0900 Subject: sh: stub __flush_tlb_global() definition for nommu. This fixes up the nommu build with a stub definition for __flush_tlb_global(), now used by the reboot code. Signed-off-by: Paul Mundt --- arch/sh/mm/nommu.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/sh/mm/nommu.c b/arch/sh/mm/nommu.c index 7694f50..36312d2 100644 --- a/arch/sh/mm/nommu.c +++ b/arch/sh/mm/nommu.c @@ -67,6 +67,10 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) BUG(); } +void __flush_tlb_global(void) +{ +} + void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte) { } -- cgit v1.1 From 75a6d53b2b1b3f212ea0615ed3bb2d68a249af7b Mon Sep 17 00:00:00 2001 From: Jarkko Nikula Date: Tue, 17 Aug 2010 09:58:02 +0300 Subject: ASoC: multi-component - Drop board-n8x0.c changes These will conflict with queued changes to board-n8x0.c coming from linux-omap tree. Only side effect from this dropping is that the integrated digital microphone on Nokia N810 will stop working when ASoC multi-component is merged. As currently the N810 is not very usable in mainline, I consider this as a minor issue that can be fixed in linux-omap tree the after the multi-component is merged. Signed-off-by: Jarkko Nikula Acked-by: Liam Girdwood Signed-off-by: Mark Brown --- arch/arm/mach-omap2/board-n8x0.c | 15 --------------- 1 file changed, 15 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c index 4543b87..a3e2b49 100644 --- a/arch/arm/mach-omap2/board-n8x0.c +++ b/arch/arm/mach-omap2/board-n8x0.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include @@ -615,25 +614,11 @@ static int n8x0_menelaus_late_init(struct device *dev) return 0; } -static struct aic3x_setup_data n810_aic33_setup = { - .gpio_func[0] = AIC3X_GPIO1_FUNC_DISABLED, - .gpio_func[1] = AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT, -}; - -static struct aic3x_pdata n810_aic33_data = { - .setup = &n810_aic33_setup, - .gpio_reset = -1, -}; - static struct i2c_board_info __initdata n8x0_i2c_board_info_1[] = { { I2C_BOARD_INFO("menelaus", 0x72), .irq = INT_24XX_SYS_NIRQ, }, - { - I2C_BOARD_INFO("tlv320aic3x", 0x1b), - .platform_data = &n810_aic33_data, - }, }; static struct menelaus_platform_data n8x0_menelaus_platform_data = { -- cgit v1.1 From 7656e2486cb1ab7cdee65652ee695bdff894ea73 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 20 Aug 2010 15:59:40 +0900 Subject: sh: Support type 1 accesses for SH7786 PCI. This enables support for type 1 config space accesses on the SH7786 PCI controller. At the same time, add in some extra sanity checks for controller asserted errors. Signed-off-by: Paul Mundt --- arch/sh/drivers/pci/ops-sh7786.c | 28 +++++++++++++++++++++------- 1 file changed, 21 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/sh/drivers/pci/ops-sh7786.c b/arch/sh/drivers/pci/ops-sh7786.c index 48f594b9..57134a3 100644 --- a/arch/sh/drivers/pci/ops-sh7786.c +++ b/arch/sh/drivers/pci/ops-sh7786.c @@ -1,7 +1,7 @@ /* * Generic SH7786 PCI-Express operations. * - * Copyright (C) 2009 Paul Mundt + * Copyright (C) 2009 - 2010 Paul Mundt * * This file is subject to the terms and conditions of the GNU General Public * License v2. See the file "COPYING" in the main directory of this archive @@ -35,22 +35,34 @@ static int sh7786_pcie_config_access(unsigned char access_type, if (devfn) return PCIBIOS_DEVICE_NOT_FOUND; + /* Clear errors */ + pci_write_reg(chan, pci_read_reg(chan, SH4A_PCIEERRFR), SH4A_PCIEERRFR); + /* Set the PIO address */ pci_write_reg(chan, (bus->number << 24) | (dev << 19) | (func << 16) | (where & ~3), SH4A_PCIEPAR); /* Enable the configuration access */ - pci_write_reg(chan, (1 << 31), SH4A_PCIEPCTLR); + if (bus->number) { + /* Type 1 */ + pci_write_reg(chan, (1 << 31) | (1 << 8), SH4A_PCIEPCTLR); + } else { + /* Type 0 */ + pci_write_reg(chan, (1 << 31), SH4A_PCIEPCTLR); + } + + /* Check for errors */ + if (pci_read_reg(chan, SH4A_PCIEERRFR) & 0x10) + return PCIBIOS_DEVICE_NOT_FOUND; + /* Check for master and target aborts */ + if (pci_read_reg(chan, SH4A_PCIEPCICONF1) & ((1 << 29) | (1 << 28))) + return PCIBIOS_DEVICE_NOT_FOUND; if (access_type == PCI_ACCESS_READ) *data = pci_read_reg(chan, SH4A_PCIEPDR); else pci_write_reg(chan, *data, SH4A_PCIEPDR); - /* Check for master and target aborts */ - if (pci_read_reg(chan, SH4A_PCIEPCICONF1) & ((1 << 29) | (1 << 28))) - return PCIBIOS_DEVICE_NOT_FOUND; - return PCIBIOS_SUCCESSFUL; } @@ -69,8 +81,10 @@ static int sh7786_pcie_read(struct pci_bus *bus, unsigned int devfn, spin_lock_irqsave(&sh7786_pcie_lock, flags); ret = sh7786_pcie_config_access(PCI_ACCESS_READ, bus, devfn, where, &data); - if (ret != PCIBIOS_SUCCESSFUL) + if (ret != PCIBIOS_SUCCESSFUL) { + *val = 0xffffffff; goto out; + } if (size == 1) *val = (data >> ((where & 3) << 3)) & 0xff; -- cgit v1.1 From 53178d71b9f2d5c96bfcd2dd2c4b99c4e95a77d5 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 20 Aug 2010 16:04:59 +0900 Subject: sh: Fix up SH7786 PCIe PHY initialization. This brings the clocking and register setting in line with the somewhat factually ambiguous specification. Signed-off-by: Paul Mundt --- arch/sh/drivers/pci/pcie-sh7786.c | 30 ++++++++++++++++++------------ 1 file changed, 18 insertions(+), 12 deletions(-) (limited to 'arch') diff --git a/arch/sh/drivers/pci/pcie-sh7786.c b/arch/sh/drivers/pci/pcie-sh7786.c index 68cb9b0..03e6d82 100644 --- a/arch/sh/drivers/pci/pcie-sh7786.c +++ b/arch/sh/drivers/pci/pcie-sh7786.c @@ -148,16 +148,11 @@ static int pci_wait_for_irq(struct pci_channel *chan, unsigned int mask) static void phy_write_reg(struct pci_channel *chan, unsigned int addr, unsigned int lane, unsigned int data) { - unsigned long phyaddr, ctrl; + unsigned long phyaddr; phyaddr = (1 << BITS_CMD) + ((lane & 0xf) << BITS_LANE) + ((addr & 0xff) << BITS_ADR); - /* Enable clock */ - ctrl = pci_read_reg(chan, SH4A_PCIEPHYCTLR); - ctrl |= (1 << BITS_CKE); - pci_write_reg(chan, ctrl, SH4A_PCIEPHYCTLR); - /* Set write data */ pci_write_reg(chan, data, SH4A_PCIEPHYDOUTR); pci_write_reg(chan, phyaddr, SH4A_PCIEPHYADRR); @@ -165,20 +160,22 @@ static void phy_write_reg(struct pci_channel *chan, unsigned int addr, phy_wait_for_ack(chan); /* Clear command */ + pci_write_reg(chan, 0, SH4A_PCIEPHYDOUTR); pci_write_reg(chan, 0, SH4A_PCIEPHYADRR); phy_wait_for_ack(chan); - - /* Disable clock */ - ctrl = pci_read_reg(chan, SH4A_PCIEPHYCTLR); - ctrl &= ~(1 << BITS_CKE); - pci_write_reg(chan, ctrl, SH4A_PCIEPHYCTLR); } static int phy_init(struct pci_channel *chan) { + unsigned long ctrl; unsigned int timeout = 100; + /* Enable clock */ + ctrl = pci_read_reg(chan, SH4A_PCIEPHYCTLR); + ctrl |= (1 << BITS_CKE); + pci_write_reg(chan, ctrl, SH4A_PCIEPHYCTLR); + /* Initialize the phy */ phy_write_reg(chan, 0x60, 0xf, 0x004b008b); phy_write_reg(chan, 0x61, 0xf, 0x00007b41); @@ -187,9 +184,15 @@ static int phy_init(struct pci_channel *chan) phy_write_reg(chan, 0x66, 0xf, 0x00000010); phy_write_reg(chan, 0x74, 0xf, 0x0007001c); phy_write_reg(chan, 0x79, 0xf, 0x01fc000d); + phy_write_reg(chan, 0xb0, 0xf, 0x00000610); /* Deassert Standby */ - phy_write_reg(chan, 0x67, 0xf, 0x00000400); + phy_write_reg(chan, 0x67, 0x1, 0x00000400); + + /* Disable clock */ + ctrl = pci_read_reg(chan, SH4A_PCIEPHYCTLR); + ctrl &= ~(1 << BITS_CKE); + pci_write_reg(chan, ctrl, SH4A_PCIEPHYCTLR); while (timeout--) { if (pci_read_reg(chan, SH4A_PCIEPHYSR)) @@ -287,6 +290,9 @@ static int pcie_init(struct sh7786_pcie_port *port) __raw_writel(memphys, chan->reg_base + SH4A_PCIELAR0); __raw_writel((memsize - SZ_256) | 1, chan->reg_base + SH4A_PCIELAMR0); + __raw_writel(memphys, chan->reg_base + SH4A_PCIEPCICONF4); + __raw_writel(0, chan->reg_base + SH4A_PCIEPCICONF5); + /* Finish initialization */ data = pci_read_reg(chan, SH4A_PCIETCTLR); data |= 0x1; -- cgit v1.1 From 65c23f54c01fabae171d54c0e78df354b3709b93 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 20 Aug 2010 20:26:41 +0900 Subject: sh: Relax devfn constraints for SH7786 PCIe. SH7786 PCIe has 1 slot per port, but no specific restriction on function. Relax the devfn restriction and look to the slot number instead when configured as a root complex. Signed-off-by: Paul Mundt --- arch/sh/drivers/pci/ops-sh7786.c | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) (limited to 'arch') diff --git a/arch/sh/drivers/pci/ops-sh7786.c b/arch/sh/drivers/pci/ops-sh7786.c index 57134a3..79a5dda 100644 --- a/arch/sh/drivers/pci/ops-sh7786.c +++ b/arch/sh/drivers/pci/ops-sh7786.c @@ -25,14 +25,15 @@ static int sh7786_pcie_config_access(unsigned char access_type, struct pci_bus *bus, unsigned int devfn, int where, u32 *data) { struct pci_channel *chan = bus->sysdata; - int dev, func; + int dev, func, type; dev = PCI_SLOT(devfn); func = PCI_FUNC(devfn); + type = !!bus->parent; if (bus->number > 255 || dev > 31 || func > 7) return PCIBIOS_FUNC_NOT_SUPPORTED; - if (devfn) + if (bus->parent == NULL && dev) return PCIBIOS_DEVICE_NOT_FOUND; /* Clear errors */ @@ -43,13 +44,7 @@ static int sh7786_pcie_config_access(unsigned char access_type, (func << 16) | (where & ~3), SH4A_PCIEPAR); /* Enable the configuration access */ - if (bus->number) { - /* Type 1 */ - pci_write_reg(chan, (1 << 31) | (1 << 8), SH4A_PCIEPCTLR); - } else { - /* Type 0 */ - pci_write_reg(chan, (1 << 31), SH4A_PCIEPCTLR); - } + pci_write_reg(chan, (1 << 31) | (type << 8), SH4A_PCIEPCTLR); /* Check for errors */ if (pci_read_reg(chan, SH4A_PCIEERRFR) & 0x10) -- cgit v1.1 From d2d5bc58d79321bd29ed1c8c61e806ec0541e3bf Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 20 Aug 2010 20:38:24 +0900 Subject: sh: sh2007/sh7757lcr defconfig reduction. These were newly added while the defconfig reduction work was ongoing, strip them down now. Signed-off-by: Paul Mundt --- arch/sh/configs/sh2007_defconfig | 1144 ----------------------------------- arch/sh/configs/sh7757lcr_defconfig | 1041 ------------------------------- 2 files changed, 2185 deletions(-) (limited to 'arch') diff --git a/arch/sh/configs/sh2007_defconfig b/arch/sh/configs/sh2007_defconfig index adf7a6b..c492796 100644 --- a/arch/sh/configs/sh2007_defconfig +++ b/arch/sh/configs/sh2007_defconfig @@ -1,1096 +1,132 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.35-rc2 -# Fri Jun 18 19:46:14 2010 -# -CONFIG_SUPERH=y -CONFIG_SUPERH32=y -# CONFIG_SUPERH64 is not set -CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_FIND_NEXT_BIT=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -CONFIG_IRQ_PER_CPU=y -CONFIG_SPARSE_IRQ=y -# CONFIG_GENERIC_GPIO is not set -CONFIG_GENERIC_TIME=y -CONFIG_GENERIC_CLOCKEVENTS=y -# CONFIG_ARCH_SUSPEND_POSSIBLE is not set -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_SYS_SUPPORTS_HUGETLBFS=y -CONFIG_SYS_SUPPORTS_TMU=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_HAVE_LATENCYTOP_SUPPORT=y -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set -CONFIG_ARCH_NO_VIRT_TO_BUS=y -CONFIG_ARCH_HAS_DEFAULT_IDLE=y -CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y -CONFIG_NO_IOPORT=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -CONFIG_CONSTRUCTORS=y - -# -# General setup -# CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 -CONFIG_CROSS_COMPILE="" -CONFIG_LOCALVERSION="" # CONFIG_LOCALVERSION_AUTO is not set -CONFIG_HAVE_KERNEL_GZIP=y -CONFIG_HAVE_KERNEL_BZIP2=y -CONFIG_HAVE_KERNEL_LZMA=y -CONFIG_HAVE_KERNEL_LZO=y -CONFIG_KERNEL_GZIP=y -# CONFIG_KERNEL_BZIP2 is not set -# CONFIG_KERNEL_LZMA is not set -# CONFIG_KERNEL_LZO is not set -CONFIG_SWAP=y CONFIG_SYSVIPC=y -CONFIG_SYSVIPC_SYSCTL=y CONFIG_POSIX_MQUEUE=y -CONFIG_POSIX_MQUEUE_SYSCTL=y CONFIG_BSD_PROCESS_ACCT=y -# CONFIG_BSD_PROCESS_ACCT_V3 is not set -# CONFIG_TASKSTATS is not set CONFIG_AUDIT=y CONFIG_AUDITSYSCALL=y -CONFIG_AUDIT_TREE=y - -# -# RCU Subsystem -# -CONFIG_TREE_RCU=y -# CONFIG_TREE_PREEMPT_RCU is not set -# CONFIG_TINY_RCU is not set -# CONFIG_RCU_TRACE is not set -CONFIG_RCU_FANOUT=32 -# CONFIG_RCU_FANOUT_EXACT is not set -# CONFIG_TREE_RCU_TRACE is not set CONFIG_IKCONFIG=y -# CONFIG_IKCONFIG_PROC is not set CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_CGROUPS is not set -CONFIG_SYSFS_DEPRECATED=y CONFIG_SYSFS_DEPRECATED_V2=y -# CONFIG_RELAY is not set -# CONFIG_NAMESPACES is not set -# CONFIG_BLK_DEV_INITRD is not set # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y -CONFIG_EMBEDDED=y -CONFIG_UID16=y -CONFIG_SYSCTL_SYSCALL=y -CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y -CONFIG_EVENTFD=y -CONFIG_SHMEM=y -CONFIG_AIO=y -CONFIG_HAVE_PERF_EVENTS=y -CONFIG_PERF_USE_VMALLOC=y - -# -# Kernel Performance Events And Counters -# -CONFIG_PERF_EVENTS=y -# CONFIG_PERF_COUNTERS is not set -# CONFIG_DEBUG_PERF_USE_VMALLOC is not set -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_COMPAT_BRK=y CONFIG_SLAB=y -# CONFIG_SLUB is not set -# CONFIG_SLOB is not set -# CONFIG_PROFILING is not set -CONFIG_HAVE_OPROFILE=y -CONFIG_HAVE_IOREMAP_PROT=y -CONFIG_HAVE_KPROBES=y -CONFIG_HAVE_KRETPROBES=y -CONFIG_HAVE_ARCH_TRACEHOOK=y -CONFIG_HAVE_DMA_ATTRS=y -CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y -CONFIG_HAVE_CLK=y -CONFIG_HAVE_DMA_API_DEBUG=y -CONFIG_HAVE_HW_BREAKPOINT=y -CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y - -# -# GCOV-based kernel profiling -# -# CONFIG_GCOV_KERNEL is not set -# CONFIG_SLOW_WORK is not set -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_SLABINFO=y -CONFIG_RT_MUTEXES=y -CONFIG_BASE_SMALL=0 -# CONFIG_MODULES is not set -CONFIG_BLOCK=y -CONFIG_LBDAF=y # CONFIG_BLK_DEV_BSG is not set -# CONFIG_BLK_DEV_INTEGRITY is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -# CONFIG_DEFAULT_DEADLINE is not set -CONFIG_DEFAULT_CFQ=y -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="cfq" -# CONFIG_INLINE_SPIN_TRYLOCK is not set -# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set -# CONFIG_INLINE_SPIN_LOCK is not set -# CONFIG_INLINE_SPIN_LOCK_BH is not set -# CONFIG_INLINE_SPIN_LOCK_IRQ is not set -# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set -CONFIG_INLINE_SPIN_UNLOCK=y -# CONFIG_INLINE_SPIN_UNLOCK_BH is not set -CONFIG_INLINE_SPIN_UNLOCK_IRQ=y -# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set -# CONFIG_INLINE_READ_TRYLOCK is not set -# CONFIG_INLINE_READ_LOCK is not set -# CONFIG_INLINE_READ_LOCK_BH is not set -# CONFIG_INLINE_READ_LOCK_IRQ is not set -# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set -CONFIG_INLINE_READ_UNLOCK=y -# CONFIG_INLINE_READ_UNLOCK_BH is not set -CONFIG_INLINE_READ_UNLOCK_IRQ=y -# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set -# CONFIG_INLINE_WRITE_TRYLOCK is not set -# CONFIG_INLINE_WRITE_LOCK is not set -# CONFIG_INLINE_WRITE_LOCK_BH is not set -# CONFIG_INLINE_WRITE_LOCK_IRQ is not set -# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set -CONFIG_INLINE_WRITE_UNLOCK=y -# CONFIG_INLINE_WRITE_UNLOCK_BH is not set -CONFIG_INLINE_WRITE_UNLOCK_IRQ=y -# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set -# CONFIG_MUTEX_SPIN_ON_OWNER is not set -# CONFIG_FREEZER is not set - -# -# System type -# -CONFIG_CPU_SH4=y -CONFIG_CPU_SH4A=y -# CONFIG_CPU_SUBTYPE_SH7619 is not set -# CONFIG_CPU_SUBTYPE_SH7201 is not set -# CONFIG_CPU_SUBTYPE_SH7203 is not set -# CONFIG_CPU_SUBTYPE_SH7206 is not set -# CONFIG_CPU_SUBTYPE_SH7263 is not set -# CONFIG_CPU_SUBTYPE_MXG is not set -# CONFIG_CPU_SUBTYPE_SH7705 is not set -# CONFIG_CPU_SUBTYPE_SH7706 is not set -# CONFIG_CPU_SUBTYPE_SH7707 is not set -# CONFIG_CPU_SUBTYPE_SH7708 is not set -# CONFIG_CPU_SUBTYPE_SH7709 is not set -# CONFIG_CPU_SUBTYPE_SH7710 is not set -# CONFIG_CPU_SUBTYPE_SH7712 is not set -# CONFIG_CPU_SUBTYPE_SH7720 is not set -# CONFIG_CPU_SUBTYPE_SH7721 is not set -# CONFIG_CPU_SUBTYPE_SH7750 is not set -# CONFIG_CPU_SUBTYPE_SH7091 is not set -# CONFIG_CPU_SUBTYPE_SH7750R is not set -# CONFIG_CPU_SUBTYPE_SH7750S is not set -# CONFIG_CPU_SUBTYPE_SH7751 is not set -# CONFIG_CPU_SUBTYPE_SH7751R is not set -# CONFIG_CPU_SUBTYPE_SH7760 is not set -# CONFIG_CPU_SUBTYPE_SH4_202 is not set -# CONFIG_CPU_SUBTYPE_SH7723 is not set -# CONFIG_CPU_SUBTYPE_SH7724 is not set -# CONFIG_CPU_SUBTYPE_SH7757 is not set -# CONFIG_CPU_SUBTYPE_SH7763 is not set -# CONFIG_CPU_SUBTYPE_SH7770 is not set CONFIG_CPU_SUBTYPE_SH7780=y -# CONFIG_CPU_SUBTYPE_SH7785 is not set -# CONFIG_CPU_SUBTYPE_SH7786 is not set -# CONFIG_CPU_SUBTYPE_SHX3 is not set -# CONFIG_CPU_SUBTYPE_SH7343 is not set -# CONFIG_CPU_SUBTYPE_SH7722 is not set -# CONFIG_CPU_SUBTYPE_SH7366 is not set - -# -# Memory management options -# -CONFIG_QUICKLIST=y -CONFIG_MMU=y -CONFIG_PAGE_OFFSET=0x80000000 -CONFIG_FORCE_MAX_ZONEORDER=11 -CONFIG_MEMORY_START=0x08000000 CONFIG_MEMORY_SIZE=0x08000000 -CONFIG_29BIT=y -# CONFIG_PMB is not set # CONFIG_VSYSCALL is not set -CONFIG_ARCH_FLATMEM_ENABLE=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SPARSEMEM_DEFAULT=y -CONFIG_MAX_ACTIVE_REGIONS=1 -CONFIG_ARCH_POPULATES_NODE_MAP=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_UNCACHED_MAPPING=y -CONFIG_PAGE_SIZE_4KB=y -# CONFIG_PAGE_SIZE_8KB is not set -# CONFIG_PAGE_SIZE_16KB is not set -# CONFIG_PAGE_SIZE_64KB is not set -CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_SPARSEMEM_STATIC=y -CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_PHYS_ADDR_T_64BIT is not set -CONFIG_ZONE_DMA_FLAG=0 -CONFIG_NR_QUICK=1 -# CONFIG_KSM is not set -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 - -# -# Cache configuration -# -CONFIG_CACHE_WRITEBACK=y -# CONFIG_CACHE_WRITETHROUGH is not set -# CONFIG_CACHE_OFF is not set - -# -# Processor features -# -CONFIG_CPU_LITTLE_ENDIAN=y -# CONFIG_CPU_BIG_ENDIAN is not set -CONFIG_SH_FPU=y -# CONFIG_SH_STORE_QUEUES is not set -# CONFIG_SPECULATIVE_EXECUTION is not set -CONFIG_CPU_HAS_INTEVT=y -CONFIG_CPU_HAS_SR_RB=y -CONFIG_CPU_HAS_FPU=y - -# -# Board support -# -# CONFIG_SH_7780_SOLUTION_ENGINE is not set -# CONFIG_SH_SDK7780 is not set -# CONFIG_SH_HIGHLANDER is not set CONFIG_SH_SH2007=y - -# -# Timer and clock configuration -# -CONFIG_SH_TIMER_TMU=y -CONFIG_SH_PCLK_FREQ=50000000 -CONFIG_SH_CLK_CPG=y -CONFIG_SH_CLK_CPG_LEGACY=y -CONFIG_TICK_ONESHOT=y -# CONFIG_NO_HZ is not set CONFIG_HIGH_RES_TIMERS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y - -# -# CPU Frequency scaling -# -# CONFIG_CPU_FREQ is not set - -# -# DMA support -# CONFIG_SH_DMA=y -CONFIG_SH_DMA_IRQ_MULTI=y CONFIG_SH_DMA_API=y -CONFIG_NR_ONCHIP_DMA_CHANNELS=12 CONFIG_NR_DMA_CHANNELS_BOOL=y -CONFIG_NR_DMA_CHANNELS=12 - -# -# Companion Chips -# - -# -# Additional SuperH Device Drivers -# -# CONFIG_HEARTBEAT is not set -# CONFIG_PUSH_SWITCH is not set - -# -# Kernel features -# CONFIG_HZ_100=y -# CONFIG_HZ_250 is not set -# CONFIG_HZ_300 is not set -# CONFIG_HZ_1000 is not set -CONFIG_HZ=100 -CONFIG_SCHED_HRTICK=y -# CONFIG_KEXEC is not set -# CONFIG_CRASH_DUMP is not set -# CONFIG_SECCOMP is not set -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set -# CONFIG_PREEMPT is not set -CONFIG_GUSA=y -# CONFIG_INTC_USERIMASK is not set - -# -# Boot options -# -CONFIG_ZERO_PAGE_OFFSET=0x00001000 -CONFIG_BOOT_LINK_OFFSET=0x00800000 -CONFIG_ENTRY_OFFSET=0x00001000 CONFIG_CMDLINE_OVERWRITE=y -# CONFIG_CMDLINE_EXTEND is not set CONFIG_CMDLINE="console=ttySC1,115200 ip=dhcp root=/dev/nfs rw nfsroot=/nfs/rootfs,rsize=1024,wsize=1024 earlyprintk=sh-sci.1" - -# -# Bus options -# -# CONFIG_ARCH_SUPPORTS_MSI is not set CONFIG_PCCARD=y -CONFIG_PCMCIA=y -CONFIG_PCMCIA_LOAD_CIS=y - -# -# PC-card bridges -# - -# -# Executable file formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -# CONFIG_HAVE_AOUT is not set CONFIG_BINFMT_MISC=y - -# -# Power management options (EXPERIMENTAL) -# -# CONFIG_PM is not set -# CONFIG_CPU_IDLE is not set -CONFIG_NET=y - -# -# Networking options -# CONFIG_PACKET=y CONFIG_UNIX=y -CONFIG_XFRM=y CONFIG_XFRM_USER=y -# CONFIG_XFRM_SUB_POLICY is not set -CONFIG_XFRM_MIGRATE=y -# CONFIG_XFRM_STATISTICS is not set CONFIG_NET_KEY=y CONFIG_NET_KEY_MIGRATE=y CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_ASK_IP_FIB_HASH=y -# CONFIG_IP_FIB_TRIE is not set -CONFIG_IP_FIB_HASH=y CONFIG_IP_MULTIPLE_TABLES=y CONFIG_IP_ROUTE_MULTIPATH=y CONFIG_IP_ROUTE_VERBOSE=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y -# CONFIG_IP_PNP_BOOTP is not set -# CONFIG_IP_PNP_RARP is not set CONFIG_NET_IPIP=y -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -CONFIG_INET_TUNNEL=y # CONFIG_INET_XFRM_MODE_TRANSPORT is not set # CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_TCP_MD5SIG is not set # CONFIG_IPV6 is not set CONFIG_NETWORK_SECMARK=y -# CONFIG_NETFILTER is not set -# CONFIG_IP_DCCP is not set -# CONFIG_IP_SCTP is not set -# CONFIG_RDS is not set -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_L2TP is not set -# CONFIG_BRIDGE is not set -# CONFIG_NET_DSA is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_PHONET is not set -# CONFIG_IEEE802154 is not set -# CONFIG_NET_SCHED is not set -# CONFIG_DCB is not set - -# -# Network testing -# CONFIG_NET_PKTGEN=y -# CONFIG_HAMRADIO is not set -# CONFIG_CAN is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -# CONFIG_AF_RXRPC is not set -CONFIG_FIB_RULES=y -CONFIG_WIRELESS=y -# CONFIG_CFG80211 is not set -# CONFIG_LIB80211 is not set - -# -# CFG80211 needs to be enabled for MAC80211 -# - -# -# Some wireless drivers require a rate control algorithm -# -# CONFIG_WIMAX is not set -# CONFIG_RFKILL is not set -# CONFIG_NET_9P is not set -# CONFIG_CAIF is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_DEVTMPFS is not set -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y -CONFIG_FIRMWARE_IN_KERNEL=y -CONFIG_EXTRA_FIRMWARE="" -# CONFIG_DEBUG_DRIVER is not set -# CONFIG_DEBUG_DEVRES is not set -# CONFIG_SYS_HYPERVISOR is not set -# CONFIG_CONNECTOR is not set -# CONFIG_MTD is not set -# CONFIG_PARPORT is not set -CONFIG_BLK_DEV=y -# CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set - -# -# DRBD disabled because PROC_FS, INET or CONNECTOR not selected -# -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_UB is not set CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=4096 -# CONFIG_BLK_DEV_XIP is not set CONFIG_CDROM_PKTCDVD=y -CONFIG_CDROM_PKTCDVD_BUFFERS=8 -# CONFIG_CDROM_PKTCDVD_WCACHE is not set -# CONFIG_ATA_OVER_ETH is not set # CONFIG_MISC_DEVICES is not set - -# -# SCSI device support -# -CONFIG_SCSI_MOD=y CONFIG_RAID_ATTRS=y CONFIG_SCSI=y -CONFIG_SCSI_DMA=y CONFIG_SCSI_TGT=y -CONFIG_SCSI_NETLINK=y -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# CONFIG_BLK_DEV_SD=y -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set CONFIG_BLK_DEV_SR=y -# CONFIG_BLK_DEV_SR_VENDOR is not set CONFIG_CHR_DEV_SG=y -# CONFIG_CHR_DEV_SCH is not set CONFIG_SCSI_MULTI_LUN=y CONFIG_SCSI_CONSTANTS=y CONFIG_SCSI_LOGGING=y CONFIG_SCSI_SCAN_ASYNC=y - -# -# SCSI Transports -# CONFIG_SCSI_SPI_ATTRS=y CONFIG_SCSI_FC_ATTRS=y -# CONFIG_SCSI_FC_TGT_ATTRS is not set CONFIG_SCSI_ISCSI_ATTRS=y -# CONFIG_SCSI_SAS_LIBSAS is not set CONFIG_SCSI_SRP_ATTRS=y -# CONFIG_SCSI_SRP_TGT_ATTRS is not set # CONFIG_SCSI_LOWLEVEL is not set -# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set -# CONFIG_SCSI_DH is not set -# CONFIG_SCSI_OSD_INITIATOR is not set -# CONFIG_ATA is not set -# CONFIG_MD is not set CONFIG_NETDEVICES=y CONFIG_DUMMY=y -# CONFIG_BONDING is not set -# CONFIG_MACVLAN is not set CONFIG_EQUALIZER=y CONFIG_TUN=y CONFIG_VETH=y -CONFIG_PHYLIB=y - -# -# MII PHY device drivers -# -# CONFIG_MARVELL_PHY is not set -# CONFIG_DAVICOM_PHY is not set -# CONFIG_QSEMI_PHY is not set -# CONFIG_LXT_PHY is not set -# CONFIG_CICADA_PHY is not set -# CONFIG_VITESSE_PHY is not set -# CONFIG_SMSC_PHY is not set -# CONFIG_BROADCOM_PHY is not set -# CONFIG_ICPLUS_PHY is not set -# CONFIG_REALTEK_PHY is not set -# CONFIG_NATIONAL_PHY is not set -# CONFIG_STE10XP is not set -# CONFIG_LSI_ET1011C_PHY is not set -# CONFIG_MICREL_PHY is not set -# CONFIG_FIXED_PHY is not set -# CONFIG_MDIO_BITBANG is not set CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_AX88796 is not set -# CONFIG_STNIC is not set -# CONFIG_SMC91X is not set -# CONFIG_ETHOC is not set -# CONFIG_SMC911X is not set CONFIG_SMSC911X=y -# CONFIG_DNET is not set -# CONFIG_IBM_NEW_EMAC_ZMII is not set -# CONFIG_IBM_NEW_EMAC_RGMII is not set -# CONFIG_IBM_NEW_EMAC_TAH is not set -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set -# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set -# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set -# CONFIG_B44 is not set -# CONFIG_KS8842 is not set -# CONFIG_KS8851_MLL is not set # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set # CONFIG_WLAN is not set - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# - -# -# USB Network Adapters -# -# CONFIG_USB_CATC is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_RTL8150 is not set -# CONFIG_USB_USBNET is not set -# CONFIG_USB_IPHETH is not set -# CONFIG_NET_PCMCIA is not set -# CONFIG_WAN is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_ISDN is not set -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y CONFIG_INPUT_FF_MEMLESS=y -# CONFIG_INPUT_POLLDEV is not set -# CONFIG_INPUT_SPARSEKMAP is not set - -# -# Userland interfaces -# # CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# # CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TABLET is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# # CONFIG_SERIO is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y CONFIG_VT_HW_CONSOLE_BINDING=y # CONFIG_DEVKMEM is not set -# CONFIG_SERIAL_NONSTANDARD is not set -# CONFIG_N_GSM is not set - -# -# Serial drivers -# -# CONFIG_SERIAL_8250 is not set - -# -# Non-8250 serial port support -# CONFIG_SERIAL_SH_SCI=y -CONFIG_SERIAL_SH_SCI_NR_UARTS=2 CONFIG_SERIAL_SH_SCI_CONSOLE=y -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_TIMBERDALE is not set -# CONFIG_SERIAL_ALTERA_JTAGUART is not set -# CONFIG_SERIAL_ALTERA_UART is not set -CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set # CONFIG_LEGACY_PTYS is not set -# CONFIG_IPMI_HANDLER is not set -CONFIG_HW_RANDOM=y -# CONFIG_HW_RANDOM_TIMERIOMEM is not set -# CONFIG_R3964 is not set - -# -# PCMCIA character devices -# -# CONFIG_SYNCLINK_CS is not set -# CONFIG_CARDMAN_4000 is not set -# CONFIG_CARDMAN_4040 is not set -# CONFIG_IPWIRELESS is not set -# CONFIG_RAW_DRIVER is not set -# CONFIG_TCG_TPM is not set -# CONFIG_RAMOOPS is not set -# CONFIG_I2C is not set -# CONFIG_SPI is not set - -# -# PPS support -# -# CONFIG_PPS is not set -# CONFIG_W1 is not set -# CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set -# CONFIG_THERMAL is not set CONFIG_WATCHDOG=y -# CONFIG_WATCHDOG_NOWAYOUT is not set - -# -# Watchdog Device Drivers -# -# CONFIG_SOFT_WATCHDOG is not set CONFIG_SH_WDT=y -# CONFIG_SH_WDT_MMAP is not set - -# -# USB-based Watchdog Cards -# -# CONFIG_USBPCWATCHDOG is not set -CONFIG_SSB_POSSIBLE=y - -# -# Sonics Silicon Backplane -# CONFIG_SSB=y -CONFIG_SSB_PCMCIAHOST_POSSIBLE=y -# CONFIG_SSB_PCMCIAHOST is not set -# CONFIG_SSB_SILENT is not set -# CONFIG_SSB_DEBUG is not set -CONFIG_MFD_SUPPORT=y -# CONFIG_MFD_CORE is not set -# CONFIG_MFD_SM501 is not set -# CONFIG_MFD_SH_MOBILE_SDHI is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_MFD_TMIO is not set -# CONFIG_ABX500_CORE is not set -# CONFIG_REGULATOR is not set -# CONFIG_MEDIA_SUPPORT is not set - -# -# Graphics support -# -# CONFIG_VGASTATE is not set -# CONFIG_VIDEO_OUTPUT_CONTROL is not set CONFIG_FB=y -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FB_DDC is not set -# CONFIG_FB_BOOT_VESA_SUPPORT is not set -# CONFIG_FB_CFB_FILLRECT is not set -# CONFIG_FB_CFB_COPYAREA is not set -# CONFIG_FB_CFB_IMAGEBLIT is not set -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set -# CONFIG_FB_SYS_FILLRECT is not set -# CONFIG_FB_SYS_COPYAREA is not set -# CONFIG_FB_SYS_IMAGEBLIT is not set -# CONFIG_FB_FOREIGN_ENDIAN is not set -# CONFIG_FB_SYS_FOPS is not set -# CONFIG_FB_SVGALIB is not set -# CONFIG_FB_MACMODES is not set -# CONFIG_FB_BACKLIGHT is not set -# CONFIG_FB_MODE_HELPERS is not set -# CONFIG_FB_TILEBLITTING is not set - -# -# Frame buffer hardware drivers -# -# CONFIG_FB_S1D13XXX is not set -# CONFIG_FB_SH_MOBILE_LCDC is not set -# CONFIG_FB_VIRTUAL is not set -# CONFIG_FB_METRONOME is not set -# CONFIG_FB_MB862XX is not set -# CONFIG_FB_BROADSHEET is not set CONFIG_BACKLIGHT_LCD_SUPPORT=y # CONFIG_LCD_CLASS_DEVICE is not set -CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_GENERIC=y - -# -# Display device support -# -# CONFIG_DISPLAY_SUPPORT is not set - -# -# Console display driver support -# -CONFIG_DUMMY_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set -# CONFIG_FONTS is not set -CONFIG_FONT_8x8=y -CONFIG_FONT_8x16=y CONFIG_LOGO=y -CONFIG_LOGO_LINUX_MONO=y -CONFIG_LOGO_LINUX_VGA16=y -CONFIG_LOGO_LINUX_CLUT224=y -CONFIG_LOGO_SUPERH_MONO=y -CONFIG_LOGO_SUPERH_VGA16=y -CONFIG_LOGO_SUPERH_CLUT224=y -# CONFIG_SOUND is not set # CONFIG_HID_SUPPORT is not set -CONFIG_USB_SUPPORT=y -CONFIG_USB_ARCH_HAS_HCD=y -# CONFIG_USB_ARCH_HAS_OHCI is not set -# CONFIG_USB_ARCH_HAS_EHCI is not set CONFIG_USB=y -# CONFIG_USB_DEBUG is not set -# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set - -# -# Miscellaneous USB options -# CONFIG_USB_DEVICEFS=y # CONFIG_USB_DEVICE_CLASS is not set -# CONFIG_USB_DYNAMIC_MINORS is not set -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set CONFIG_USB_MON=y -# CONFIG_USB_WUSB is not set -# CONFIG_USB_WUSB_CBAF is not set - -# -# USB Host Controller Drivers -# -# CONFIG_USB_C67X00_HCD is not set -# CONFIG_USB_OXU210HP_HCD is not set -# CONFIG_USB_ISP116X_HCD is not set -# CONFIG_USB_ISP1760_HCD is not set -# CONFIG_USB_ISP1362_HCD is not set -# CONFIG_USB_SL811_HCD is not set -# CONFIG_USB_R8A66597_HCD is not set -# CONFIG_USB_HWA_HCD is not set - -# -# USB Device Class drivers -# -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set -# CONFIG_USB_WDM is not set -# CONFIG_USB_TMC is not set - -# -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may -# - -# -# also be needed; see USB_STORAGE Help for more info -# -# CONFIG_USB_STORAGE is not set -# CONFIG_USB_LIBUSUAL is not set - -# -# USB Imaging devices -# -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_MICROTEK is not set - -# -# USB port drivers -# -# CONFIG_USB_SERIAL is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_EMI62 is not set -# CONFIG_USB_EMI26 is not set -# CONFIG_USB_ADUTUX is not set -# CONFIG_USB_SEVSEG is not set -# CONFIG_USB_RIO500 is not set -# CONFIG_USB_LEGOTOWER is not set -# CONFIG_USB_LCD is not set -# CONFIG_USB_LED is not set -# CONFIG_USB_CYPRESS_CY7C63 is not set -# CONFIG_USB_CYTHERM is not set -# CONFIG_USB_IDMOUSE is not set -# CONFIG_USB_FTDI_ELAN is not set -# CONFIG_USB_APPLEDISPLAY is not set -# CONFIG_USB_LD is not set -# CONFIG_USB_TRANCEVIBRATOR is not set -# CONFIG_USB_IOWARRIOR is not set -# CONFIG_USB_TEST is not set -# CONFIG_USB_ISIGHTFW is not set -# CONFIG_USB_GADGET is not set - -# -# OTG and related infrastructure -# -# CONFIG_NOP_USB_XCEIV is not set -# CONFIG_MMC is not set -# CONFIG_MEMSTICK is not set CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y - -# -# LED drivers -# CONFIG_LEDS_TRIGGERS=y - -# -# LED Triggers -# -# CONFIG_LEDS_TRIGGER_TIMER is not set -# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set -# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set -# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set - -# -# iptables trigger is under Netfilter config (LED target) -# -# CONFIG_ACCESSIBILITY is not set -CONFIG_RTC_LIB=y CONFIG_RTC_CLASS=y -CONFIG_RTC_HCTOSYS=y -CONFIG_RTC_HCTOSYS_DEVICE="rtc0" -# CONFIG_RTC_DEBUG is not set - -# -# RTC interfaces -# -CONFIG_RTC_INTF_SYSFS=y -CONFIG_RTC_INTF_PROC=y -CONFIG_RTC_INTF_DEV=y CONFIG_RTC_INTF_DEV_UIE_EMUL=y -# CONFIG_RTC_DRV_TEST is not set - -# -# SPI RTC drivers -# - -# -# Platform RTC drivers -# -# CONFIG_RTC_DRV_DS1286 is not set -# CONFIG_RTC_DRV_DS1511 is not set -# CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_DS1742 is not set -# CONFIG_RTC_DRV_STK17TA8 is not set -# CONFIG_RTC_DRV_M48T86 is not set -# CONFIG_RTC_DRV_M48T35 is not set -# CONFIG_RTC_DRV_M48T59 is not set -# CONFIG_RTC_DRV_MSM6242 is not set -# CONFIG_RTC_DRV_BQ4802 is not set -# CONFIG_RTC_DRV_RP5C01 is not set -# CONFIG_RTC_DRV_V3020 is not set - -# -# on-CPU RTC drivers -# -# CONFIG_RTC_DRV_SH is not set -# CONFIG_RTC_DRV_GENERIC is not set CONFIG_DMADEVICES=y -# CONFIG_DMADEVICES_DEBUG is not set - -# -# DMA Devices -# CONFIG_TIMB_DMA=y -CONFIG_DMA_ENGINE=y - -# -# DMA Clients -# -# CONFIG_NET_DMA is not set -# CONFIG_ASYNC_TX_DMA is not set -# CONFIG_DMATEST is not set -# CONFIG_AUXDISPLAY is not set -# CONFIG_UIO is not set -# CONFIG_STAGING is not set - -# -# File systems -# -# CONFIG_EXT2_FS is not set CONFIG_EXT3_FS=y -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set -CONFIG_EXT3_FS_XATTR=y -# CONFIG_EXT3_FS_POSIX_ACL is not set -# CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4_FS is not set -CONFIG_JBD=y -# CONFIG_JBD_DEBUG is not set -CONFIG_FS_MBCACHE=y -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -CONFIG_FS_POSIX_ACL=y -# CONFIG_XFS_FS is not set -# CONFIG_GFS2_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set -# CONFIG_NILFS2_FS is not set -CONFIG_FILE_LOCKING=y -CONFIG_FSNOTIFY=y -CONFIG_DNOTIFY=y -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -# CONFIG_QUOTA is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_FUSE_FS is not set -CONFIG_GENERIC_ACL=y - -# -# Caches -# -# CONFIG_FSCACHE is not set - -# -# CD-ROM/DVD Filesystems -# CONFIG_ISO9660_FS=y CONFIG_JOLIET=y CONFIG_ZISOFS=y CONFIG_UDF_FS=y -CONFIG_UDF_NLS=y - -# -# DOS/FAT/NT Filesystems -# -CONFIG_FAT_FS=y CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y CONFIG_FAT_DEFAULT_CODEPAGE=932 CONFIG_FAT_DEFAULT_IOCHARSET="ascii" -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y -CONFIG_PROC_SYSCTL=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_SYSFS=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y -# CONFIG_HUGETLBFS is not set -# CONFIG_HUGETLB_PAGE is not set CONFIG_CONFIGFS_FS=y # CONFIG_MISC_FILESYSTEMS is not set -CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V3=y CONFIG_NFS_V3_ACL=y CONFIG_NFS_V4=y -# CONFIG_NFS_V4_1 is not set CONFIG_ROOT_NFS=y -# CONFIG_NFSD is not set -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_NFS_ACL_SUPPORT=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -CONFIG_SUNRPC_GSS=y -CONFIG_RPCSEC_GSS_KRB5=y -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CEPH_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y -CONFIG_NLS=y CONFIG_NLS_DEFAULT="utf8" CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_737=y @@ -1130,177 +166,31 @@ CONFIG_NLS_ISO8859_15=y CONFIG_NLS_KOI8_R=y CONFIG_NLS_KOI8_U=y CONFIG_NLS_UTF8=y -# CONFIG_DLM is not set - -# -# Kernel hacking -# -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -# CONFIG_PRINTK_TIME is not set # CONFIG_ENABLE_WARN_DEPRECATED is not set # CONFIG_ENABLE_MUST_CHECK is not set -CONFIG_FRAME_WARN=1024 -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_STRIP_ASM_SYMS is not set -# CONFIG_UNUSED_SYMBOLS is not set CONFIG_DEBUG_FS=y -# CONFIG_HEADERS_CHECK is not set CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_SHIRQ is not set # CONFIG_DETECT_SOFTLOCKUP is not set -# CONFIG_DETECT_HUNG_TASK is not set # CONFIG_SCHED_DEBUG is not set -# CONFIG_SCHEDSTATS is not set -# CONFIG_TIMER_STATS is not set -# CONFIG_DEBUG_OBJECTS is not set -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_KMEMLEAK is not set -# CONFIG_DEBUG_RT_MUTEXES is not set -# CONFIG_RT_MUTEX_TESTER is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_DEBUG_MUTEXES is not set -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_PROVE_LOCKING is not set -# CONFIG_LOCK_STAT is not set -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -# CONFIG_DEBUG_KOBJECT is not set -CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_INFO=y -# CONFIG_DEBUG_VM is not set -# CONFIG_DEBUG_WRITECOUNT is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_SG is not set -# CONFIG_DEBUG_NOTIFIERS is not set -# CONFIG_DEBUG_CREDENTIALS is not set CONFIG_FRAME_POINTER=y -# CONFIG_RCU_TORTURE_TEST is not set # CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_BACKTRACE_SELF_TEST is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set -# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set -# CONFIG_LKDTM is not set -# CONFIG_FAULT_INJECTION is not set -# CONFIG_LATENCYTOP is not set -# CONFIG_SYSCTL_SYSCALL_CHECK is not set -# CONFIG_PAGE_POISONING is not set -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y -CONFIG_HAVE_SYSCALL_TRACEPOINTS=y -CONFIG_TRACING_SUPPORT=y -CONFIG_FTRACE=y -# CONFIG_FUNCTION_TRACER is not set -# CONFIG_IRQSOFF_TRACER is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_ENABLE_DEFAULT_TRACERS is not set -# CONFIG_FTRACE_SYSCALLS is not set -# CONFIG_BOOT_TRACER is not set -CONFIG_BRANCH_PROFILE_NONE=y -# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set -# CONFIG_PROFILE_ALL_BRANCHES is not set -# CONFIG_KSYM_TRACER is not set -# CONFIG_STACK_TRACER is not set -# CONFIG_KMEMTRACE is not set -# CONFIG_WORKQUEUE_TRACER is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_DYNAMIC_DEBUG is not set -# CONFIG_DMA_API_DEBUG is not set -# CONFIG_ATOMIC64_SELFTEST is not set -# CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_KGDB is not set CONFIG_SH_STANDARD_BIOS=y -# CONFIG_STACK_DEBUG is not set -# CONFIG_DEBUG_STACK_USAGE is not set -# CONFIG_4KSTACKS is not set -CONFIG_DUMP_CODE=y -# CONFIG_DWARF_UNWINDER is not set -# CONFIG_SH_NO_BSS_INIT is not set - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set -# CONFIG_SECURITYFS is not set -# CONFIG_DEFAULT_SECURITY_SELINUX is not set -# CONFIG_DEFAULT_SECURITY_SMACK is not set -# CONFIG_DEFAULT_SECURITY_TOMOYO is not set -CONFIG_DEFAULT_SECURITY_DAC=y -CONFIG_DEFAULT_SECURITY="" -CONFIG_CRYPTO=y - -# -# Crypto core or helper -# -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_ALGAPI2=y -CONFIG_CRYPTO_AEAD=y -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_BLKCIPHER2=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_PCOMP=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -CONFIG_CRYPTO_GF128MUL=y CONFIG_CRYPTO_NULL=y -CONFIG_CRYPTO_WORKQUEUE=y -# CONFIG_CRYPTO_CRYPTD is not set CONFIG_CRYPTO_AUTHENC=y - -# -# Authenticated Encryption with Associated Data -# -# CONFIG_CRYPTO_CCM is not set -# CONFIG_CRYPTO_GCM is not set -# CONFIG_CRYPTO_SEQIV is not set - -# -# Block modes -# -CONFIG_CRYPTO_CBC=y -# CONFIG_CRYPTO_CTR is not set -# CONFIG_CRYPTO_CTS is not set CONFIG_CRYPTO_ECB=y CONFIG_CRYPTO_LRW=y CONFIG_CRYPTO_PCBC=y CONFIG_CRYPTO_XTS=y - -# -# Hash modes -# CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_XCBC=y -# CONFIG_CRYPTO_VMAC is not set - -# -# Digest -# -CONFIG_CRYPTO_CRC32C=y -# CONFIG_CRYPTO_GHASH is not set CONFIG_CRYPTO_MD4=y -CONFIG_CRYPTO_MD5=y CONFIG_CRYPTO_MICHAEL_MIC=y -# CONFIG_CRYPTO_RMD128 is not set -# CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set CONFIG_CRYPTO_SHA1=y CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y CONFIG_CRYPTO_TGR192=y CONFIG_CRYPTO_WP512=y - -# -# Ciphers -# CONFIG_CRYPTO_AES=y CONFIG_CRYPTO_ANUBIS=y CONFIG_CRYPTO_ARC4=y @@ -1308,50 +198,16 @@ CONFIG_CRYPTO_BLOWFISH=y CONFIG_CRYPTO_CAMELLIA=y CONFIG_CRYPTO_CAST5=y CONFIG_CRYPTO_CAST6=y -CONFIG_CRYPTO_DES=y CONFIG_CRYPTO_FCRYPT=y CONFIG_CRYPTO_KHAZAD=y -# CONFIG_CRYPTO_SALSA20 is not set CONFIG_CRYPTO_SEED=y CONFIG_CRYPTO_SERPENT=y CONFIG_CRYPTO_TEA=y CONFIG_CRYPTO_TWOFISH=y -CONFIG_CRYPTO_TWOFISH_COMMON=y - -# -# Compression -# CONFIG_CRYPTO_DEFLATE=y -# CONFIG_CRYPTO_ZLIB is not set CONFIG_CRYPTO_LZO=y - -# -# Random Number Generation -# # CONFIG_CRYPTO_ANSI_CPRNG is not set # CONFIG_CRYPTO_HW is not set -# CONFIG_VIRTUALIZATION is not set -# CONFIG_BINARY_PRINTF is not set - -# -# Library routines -# -CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y CONFIG_CRC_CCITT=y CONFIG_CRC16=y -# CONFIG_CRC_T10DIF is not set -CONFIG_CRC_ITU_T=y -CONFIG_CRC32=y -# CONFIG_CRC7 is not set CONFIG_LIBCRC32C=y -CONFIG_AUDIT_GENERIC=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_DMA=y -CONFIG_HAVE_LMB=y -CONFIG_NLATTR=y -CONFIG_GENERIC_ATOMIC64=y diff --git a/arch/sh/configs/sh7757lcr_defconfig b/arch/sh/configs/sh7757lcr_defconfig index 635933e..273f3fa 100644 --- a/arch/sh/configs/sh7757lcr_defconfig +++ b/arch/sh/configs/sh7757lcr_defconfig @@ -1,1126 +1,85 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.35-rc3 -# Mon Jul 5 20:42:01 2010 -# -CONFIG_SUPERH=y -CONFIG_SUPERH32=y -# CONFIG_SUPERH64 is not set -CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_FIND_NEXT_BIT=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -CONFIG_IRQ_PER_CPU=y -CONFIG_SPARSE_IRQ=y -CONFIG_GENERIC_GPIO=y -CONFIG_GENERIC_TIME=y -CONFIG_GENERIC_CLOCKEVENTS=y -# CONFIG_ARCH_SUSPEND_POSSIBLE is not set -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_SYS_SUPPORTS_HUGETLBFS=y -CONFIG_SYS_SUPPORTS_TMU=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_HAVE_LATENCYTOP_SUPPORT=y -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set -CONFIG_ARCH_NO_VIRT_TO_BUS=y -CONFIG_ARCH_HAS_DEFAULT_IDLE=y -CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -CONFIG_CONSTRUCTORS=y - -# -# General setup -# CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 -CONFIG_CROSS_COMPILE="" -CONFIG_LOCALVERSION="" -CONFIG_LOCALVERSION_AUTO=y -CONFIG_HAVE_KERNEL_GZIP=y -CONFIG_HAVE_KERNEL_BZIP2=y -CONFIG_HAVE_KERNEL_LZMA=y -CONFIG_HAVE_KERNEL_LZO=y -CONFIG_KERNEL_GZIP=y -# CONFIG_KERNEL_BZIP2 is not set -# CONFIG_KERNEL_LZMA is not set -# CONFIG_KERNEL_LZO is not set # CONFIG_SWAP is not set CONFIG_SYSVIPC=y -CONFIG_SYSVIPC_SYSCTL=y CONFIG_POSIX_MQUEUE=y -CONFIG_POSIX_MQUEUE_SYSCTL=y CONFIG_BSD_PROCESS_ACCT=y -# CONFIG_BSD_PROCESS_ACCT_V3 is not set CONFIG_TASKSTATS=y CONFIG_TASK_DELAY_ACCT=y CONFIG_TASK_XACCT=y CONFIG_TASK_IO_ACCOUNTING=y -# CONFIG_AUDIT is not set - -# -# RCU Subsystem -# -CONFIG_TREE_RCU=y -# CONFIG_TREE_PREEMPT_RCU is not set -# CONFIG_TINY_RCU is not set -# CONFIG_RCU_TRACE is not set -CONFIG_RCU_FANOUT=32 -# CONFIG_RCU_FANOUT_EXACT is not set -# CONFIG_TREE_RCU_TRACE is not set -# CONFIG_IKCONFIG is not set CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_CGROUPS is not set -# CONFIG_SYSFS_DEPRECATED_V2 is not set -# CONFIG_RELAY is not set -# CONFIG_NAMESPACES is not set CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_RD_GZIP=y -# CONFIG_RD_BZIP2 is not set -# CONFIG_RD_LZMA is not set -# CONFIG_RD_LZO is not set # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y -CONFIG_EMBEDDED=y -CONFIG_UID16=y # CONFIG_SYSCTL_SYSCALL is not set -CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y -CONFIG_EVENTFD=y -CONFIG_SHMEM=y -CONFIG_AIO=y -CONFIG_HAVE_PERF_EVENTS=y -CONFIG_PERF_USE_VMALLOC=y - -# -# Kernel Performance Events And Counters -# -CONFIG_PERF_EVENTS=y -# CONFIG_PERF_COUNTERS is not set -# CONFIG_DEBUG_PERF_USE_VMALLOC is not set -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_COMPAT_BRK=y CONFIG_SLAB=y -# CONFIG_SLUB is not set -# CONFIG_SLOB is not set -# CONFIG_PROFILING is not set -CONFIG_HAVE_OPROFILE=y -# CONFIG_KPROBES is not set -CONFIG_HAVE_KPROBES=y -CONFIG_HAVE_KRETPROBES=y -CONFIG_HAVE_ARCH_TRACEHOOK=y -CONFIG_HAVE_DMA_ATTRS=y -CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y -CONFIG_HAVE_CLK=y -CONFIG_HAVE_DMA_API_DEBUG=y -CONFIG_HAVE_HW_BREAKPOINT=y -CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y - -# -# GCOV-based kernel profiling -# -# CONFIG_SLOW_WORK is not set -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_SLABINFO=y -CONFIG_RT_MUTEXES=y -CONFIG_BASE_SMALL=0 CONFIG_MODULES=y -# CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -# CONFIG_MODVERSIONS is not set -# CONFIG_MODULE_SRCVERSION_ALL is not set -CONFIG_BLOCK=y -CONFIG_LBDAF=y # CONFIG_BLK_DEV_BSG is not set -# CONFIG_BLK_DEV_INTEGRITY is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -# CONFIG_DEFAULT_DEADLINE is not set -CONFIG_DEFAULT_CFQ=y -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="cfq" -# CONFIG_INLINE_SPIN_TRYLOCK is not set -# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set -# CONFIG_INLINE_SPIN_LOCK is not set -# CONFIG_INLINE_SPIN_LOCK_BH is not set -# CONFIG_INLINE_SPIN_LOCK_IRQ is not set -# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set -CONFIG_INLINE_SPIN_UNLOCK=y -# CONFIG_INLINE_SPIN_UNLOCK_BH is not set -CONFIG_INLINE_SPIN_UNLOCK_IRQ=y -# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set -# CONFIG_INLINE_READ_TRYLOCK is not set -# CONFIG_INLINE_READ_LOCK is not set -# CONFIG_INLINE_READ_LOCK_BH is not set -# CONFIG_INLINE_READ_LOCK_IRQ is not set -# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set -CONFIG_INLINE_READ_UNLOCK=y -# CONFIG_INLINE_READ_UNLOCK_BH is not set -CONFIG_INLINE_READ_UNLOCK_IRQ=y -# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set -# CONFIG_INLINE_WRITE_TRYLOCK is not set -# CONFIG_INLINE_WRITE_LOCK is not set -# CONFIG_INLINE_WRITE_LOCK_BH is not set -# CONFIG_INLINE_WRITE_LOCK_IRQ is not set -# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set -CONFIG_INLINE_WRITE_UNLOCK=y -# CONFIG_INLINE_WRITE_UNLOCK_BH is not set -CONFIG_INLINE_WRITE_UNLOCK_IRQ=y -# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set -# CONFIG_MUTEX_SPIN_ON_OWNER is not set -# CONFIG_FREEZER is not set - -# -# System type -# -CONFIG_CPU_SH4=y -CONFIG_CPU_SH4A=y -CONFIG_CPU_SHX2=y -# CONFIG_CPU_SUBTYPE_SH7619 is not set -# CONFIG_CPU_SUBTYPE_SH7201 is not set -# CONFIG_CPU_SUBTYPE_SH7203 is not set -# CONFIG_CPU_SUBTYPE_SH7206 is not set -# CONFIG_CPU_SUBTYPE_SH7263 is not set -# CONFIG_CPU_SUBTYPE_MXG is not set -# CONFIG_CPU_SUBTYPE_SH7705 is not set -# CONFIG_CPU_SUBTYPE_SH7706 is not set -# CONFIG_CPU_SUBTYPE_SH7707 is not set -# CONFIG_CPU_SUBTYPE_SH7708 is not set -# CONFIG_CPU_SUBTYPE_SH7709 is not set -# CONFIG_CPU_SUBTYPE_SH7710 is not set -# CONFIG_CPU_SUBTYPE_SH7712 is not set -# CONFIG_CPU_SUBTYPE_SH7720 is not set -# CONFIG_CPU_SUBTYPE_SH7721 is not set -# CONFIG_CPU_SUBTYPE_SH7750 is not set -# CONFIG_CPU_SUBTYPE_SH7091 is not set -# CONFIG_CPU_SUBTYPE_SH7750R is not set -# CONFIG_CPU_SUBTYPE_SH7750S is not set -# CONFIG_CPU_SUBTYPE_SH7751 is not set -# CONFIG_CPU_SUBTYPE_SH7751R is not set -# CONFIG_CPU_SUBTYPE_SH7760 is not set -# CONFIG_CPU_SUBTYPE_SH4_202 is not set -# CONFIG_CPU_SUBTYPE_SH7723 is not set -# CONFIG_CPU_SUBTYPE_SH7724 is not set CONFIG_CPU_SUBTYPE_SH7757=y -# CONFIG_CPU_SUBTYPE_SH7763 is not set -# CONFIG_CPU_SUBTYPE_SH7770 is not set -# CONFIG_CPU_SUBTYPE_SH7780 is not set -# CONFIG_CPU_SUBTYPE_SH7785 is not set -# CONFIG_CPU_SUBTYPE_SH7786 is not set -# CONFIG_CPU_SUBTYPE_SHX3 is not set -# CONFIG_CPU_SUBTYPE_SH7343 is not set -# CONFIG_CPU_SUBTYPE_SH7722 is not set -# CONFIG_CPU_SUBTYPE_SH7366 is not set - -# -# Memory management options -# -CONFIG_QUICKLIST=y -CONFIG_MMU=y -CONFIG_PAGE_OFFSET=0x80000000 -CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_MEMORY_START=0x40000000 CONFIG_MEMORY_SIZE=0x0f000000 -# CONFIG_29BIT is not set -CONFIG_32BIT=y CONFIG_PMB=y -CONFIG_X2TLB=y -CONFIG_VSYSCALL=y -CONFIG_ARCH_FLATMEM_ENABLE=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SPARSEMEM_DEFAULT=y -CONFIG_MAX_ACTIVE_REGIONS=1 -CONFIG_ARCH_POPULATES_NODE_MAP=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_IOREMAP_FIXED=y -CONFIG_UNCACHED_MAPPING=y -CONFIG_PAGE_SIZE_4KB=y -# CONFIG_PAGE_SIZE_8KB is not set -# CONFIG_PAGE_SIZE_16KB is not set -# CONFIG_PAGE_SIZE_64KB is not set -CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_SPARSEMEM_STATIC=y -CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_PHYS_ADDR_T_64BIT is not set -CONFIG_ZONE_DMA_FLAG=0 -CONFIG_NR_QUICK=1 -# CONFIG_KSM is not set -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 - -# -# Cache configuration -# -CONFIG_CACHE_WRITEBACK=y -# CONFIG_CACHE_WRITETHROUGH is not set -# CONFIG_CACHE_OFF is not set - -# -# Processor features -# -CONFIG_CPU_LITTLE_ENDIAN=y -# CONFIG_CPU_BIG_ENDIAN is not set -CONFIG_SH_FPU=y -# CONFIG_SH_STORE_QUEUES is not set -CONFIG_CPU_HAS_INTEVT=y -CONFIG_CPU_HAS_SR_RB=y -CONFIG_CPU_HAS_FPU=y - -# -# Board support -# CONFIG_SH_SH7757LCR=y - -# -# Timer and clock configuration -# -CONFIG_SH_TIMER_TMU=y -CONFIG_SH_CLK_CPG=y -# CONFIG_NO_HZ is not set -# CONFIG_HIGH_RES_TIMERS is not set -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y - -# -# CPU Frequency scaling -# -# CONFIG_CPU_FREQ is not set - -# -# DMA support -# -# CONFIG_SH_DMA is not set - -# -# Companion Chips -# - -# -# Additional SuperH Device Drivers -# CONFIG_HEARTBEAT=y -# CONFIG_PUSH_SWITCH is not set - -# -# Kernel features -# -# CONFIG_HZ_100 is not set -CONFIG_HZ_250=y -# CONFIG_HZ_300 is not set -# CONFIG_HZ_1000 is not set -CONFIG_HZ=250 -# CONFIG_SCHED_HRTICK is not set -# CONFIG_KEXEC is not set -# CONFIG_CRASH_DUMP is not set CONFIG_SECCOMP=y -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set -# CONFIG_PREEMPT is not set -CONFIG_GUSA=y -# CONFIG_INTC_USERIMASK is not set - -# -# Boot options -# -CONFIG_ZERO_PAGE_OFFSET=0x00001000 -CONFIG_BOOT_LINK_OFFSET=0x00800000 -CONFIG_ENTRY_OFFSET=0x00001000 CONFIG_CMDLINE_OVERWRITE=y -# CONFIG_CMDLINE_EXTEND is not set CONFIG_CMDLINE="console=ttySC2,115200 root=/dev/nfs ip=dhcp" - -# -# Bus options -# -# CONFIG_ARCH_SUPPORTS_MSI is not set -# CONFIG_PCCARD is not set - -# -# Executable file formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -# CONFIG_HAVE_AOUT is not set -# CONFIG_BINFMT_MISC is not set - -# -# Power management options (EXPERIMENTAL) -# -# CONFIG_PM is not set -# CONFIG_CPU_IDLE is not set CONFIG_NET=y - -# -# Networking options -# CONFIG_PACKET=y CONFIG_UNIX=y -CONFIG_XFRM=y -# CONFIG_XFRM_USER is not set -# CONFIG_XFRM_SUB_POLICY is not set -# CONFIG_XFRM_MIGRATE is not set -# CONFIG_XFRM_STATISTICS is not set -# CONFIG_NET_KEY is not set CONFIG_INET=y CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y -# CONFIG_IP_PNP_BOOTP is not set -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -CONFIG_INET_TUNNEL=y -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y # CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_TCP_MD5SIG is not set CONFIG_IPV6=y -# CONFIG_IPV6_PRIVACY is not set -# CONFIG_IPV6_ROUTER_PREF is not set -# CONFIG_IPV6_OPTIMISTIC_DAD is not set -# CONFIG_INET6_AH is not set -# CONFIG_INET6_ESP is not set -# CONFIG_INET6_IPCOMP is not set -# CONFIG_IPV6_MIP6 is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET6_TUNNEL is not set -CONFIG_INET6_XFRM_MODE_TRANSPORT=y -CONFIG_INET6_XFRM_MODE_TUNNEL=y -CONFIG_INET6_XFRM_MODE_BEET=y -# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set -CONFIG_IPV6_SIT=y -# CONFIG_IPV6_SIT_6RD is not set -CONFIG_IPV6_NDISC_NODETYPE=y -# CONFIG_IPV6_TUNNEL is not set -# CONFIG_IPV6_MULTIPLE_TABLES is not set -# CONFIG_IPV6_MROUTE is not set -# CONFIG_NETWORK_SECMARK is not set -# CONFIG_NETFILTER is not set -# CONFIG_IP_DCCP is not set -# CONFIG_IP_SCTP is not set -# CONFIG_RDS is not set -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_L2TP is not set -# CONFIG_BRIDGE is not set -# CONFIG_NET_DSA is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_PHONET is not set -# CONFIG_IEEE802154 is not set -# CONFIG_NET_SCHED is not set -# CONFIG_DCB is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_CAN is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -# CONFIG_AF_RXRPC is not set # CONFIG_WIRELESS is not set -# CONFIG_WIMAX is not set -# CONFIG_RFKILL is not set -# CONFIG_NET_9P is not set -# CONFIG_CAIF is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_DEVTMPFS is not set -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_FW_LOADER is not set -# CONFIG_DEBUG_DRIVER is not set -# CONFIG_DEBUG_DEVRES is not set -# CONFIG_SYS_HYPERVISOR is not set -# CONFIG_CONNECTOR is not set -# CONFIG_MTD is not set -# CONFIG_PARPORT is not set -CONFIG_BLK_DEV=y -# CONFIG_BLK_DEV_COW_COMMON is not set -# CONFIG_BLK_DEV_LOOP is not set - -# -# DRBD disabled because PROC_FS, INET or CONNECTOR not selected -# -# CONFIG_BLK_DEV_NBD is not set CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=4096 -# CONFIG_BLK_DEV_XIP is not set -# CONFIG_CDROM_PKTCDVD is not set -# CONFIG_ATA_OVER_ETH is not set -# CONFIG_BLK_DEV_HD is not set # CONFIG_MISC_DEVICES is not set -CONFIG_HAVE_IDE=y -# CONFIG_IDE is not set - -# -# SCSI device support -# -CONFIG_SCSI_MOD=y -# CONFIG_RAID_ATTRS is not set -# CONFIG_SCSI is not set -# CONFIG_SCSI_DMA is not set -# CONFIG_SCSI_NETLINK is not set -# CONFIG_ATA is not set -# CONFIG_MD is not set CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_MACVLAN is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_VETH is not set CONFIG_PHYLIB=y - -# -# MII PHY device drivers -# -# CONFIG_MARVELL_PHY is not set -# CONFIG_DAVICOM_PHY is not set -# CONFIG_QSEMI_PHY is not set -# CONFIG_LXT_PHY is not set -# CONFIG_CICADA_PHY is not set CONFIG_VITESSE_PHY=y -# CONFIG_SMSC_PHY is not set -# CONFIG_BROADCOM_PHY is not set -# CONFIG_ICPLUS_PHY is not set -# CONFIG_REALTEK_PHY is not set -# CONFIG_NATIONAL_PHY is not set -# CONFIG_STE10XP is not set -# CONFIG_LSI_ET1011C_PHY is not set -# CONFIG_MICREL_PHY is not set -# CONFIG_FIXED_PHY is not set CONFIG_MDIO_BITBANG=y -# CONFIG_MDIO_GPIO is not set CONFIG_NET_ETHERNET=y CONFIG_MII=y -# CONFIG_AX88796 is not set -# CONFIG_STNIC is not set -CONFIG_SH_ETH=y -# CONFIG_SMC91X is not set -# CONFIG_ETHOC is not set -# CONFIG_SMC911X is not set -# CONFIG_SMSC911X is not set -# CONFIG_DNET is not set -# CONFIG_IBM_NEW_EMAC_ZMII is not set -# CONFIG_IBM_NEW_EMAC_RGMII is not set -# CONFIG_IBM_NEW_EMAC_TAH is not set -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set -# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set -# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set -# CONFIG_B44 is not set -# CONFIG_KS8842 is not set -# CONFIG_KS8851_MLL is not set -CONFIG_NETDEV_1000=y # CONFIG_NETDEV_10000 is not set # CONFIG_WLAN is not set - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# -# CONFIG_WAN is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_ISDN is not set -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y -# CONFIG_INPUT_FF_MEMLESS is not set -# CONFIG_INPUT_POLLDEV is not set -# CONFIG_INPUT_SPARSEKMAP is not set - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -CONFIG_INPUT_KEYBOARD=y # CONFIG_KEYBOARD_ATKBD is not set -# CONFIG_KEYBOARD_LKKBD is not set -# CONFIG_KEYBOARD_GPIO is not set -# CONFIG_KEYBOARD_MATRIX is not set -# CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_OPENCORES is not set -# CONFIG_KEYBOARD_STOWAWAY is not set -# CONFIG_KEYBOARD_SUNKBD is not set -# CONFIG_KEYBOARD_SH_KEYSC is not set -# CONFIG_KEYBOARD_XTKBD is not set -CONFIG_INPUT_MOUSE=y # CONFIG_MOUSE_PS2 is not set -# CONFIG_MOUSE_SERIAL is not set -# CONFIG_MOUSE_VSXXXAA is not set -# CONFIG_MOUSE_GPIO is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TABLET is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# # CONFIG_SERIO is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -# CONFIG_VT_HW_CONSOLE_BINDING is not set -CONFIG_DEVKMEM=y -# CONFIG_SERIAL_NONSTANDARD is not set -# CONFIG_N_GSM is not set - -# -# Serial drivers -# CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_NR_UARTS=2 -CONFIG_SERIAL_8250_RUNTIME_UARTS=2 -# CONFIG_SERIAL_8250_EXTENDED is not set - -# -# Non-8250 serial port support -# CONFIG_SERIAL_SH_SCI=y CONFIG_SERIAL_SH_SCI_NR_UARTS=3 CONFIG_SERIAL_SH_SCI_CONSOLE=y -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_TIMBERDALE is not set -# CONFIG_SERIAL_ALTERA_JTAGUART is not set -# CONFIG_SERIAL_ALTERA_UART is not set -CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set # CONFIG_LEGACY_PTYS is not set -# CONFIG_IPMI_HANDLER is not set # CONFIG_HW_RANDOM is not set -# CONFIG_R3964 is not set -# CONFIG_RAW_DRIVER is not set -# CONFIG_TCG_TPM is not set -# CONFIG_RAMOOPS is not set -# CONFIG_I2C is not set -# CONFIG_SPI is not set - -# -# PPS support -# -# CONFIG_PPS is not set -CONFIG_ARCH_REQUIRE_GPIOLIB=y -CONFIG_GPIOLIB=y -# CONFIG_DEBUG_GPIO is not set -# CONFIG_GPIO_SYSFS is not set - -# -# Memory mapped GPIO expanders: -# -# CONFIG_GPIO_IT8761E is not set - -# -# I2C GPIO expanders: -# - -# -# PCI GPIO expanders: -# - -# -# SPI GPIO expanders: -# - -# -# AC97 GPIO expanders: -# - -# -# MODULbus GPIO expanders: -# -# CONFIG_W1 is not set -# CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set -# CONFIG_THERMAL is not set -# CONFIG_WATCHDOG is not set -CONFIG_SSB_POSSIBLE=y - -# -# Sonics Silicon Backplane -# -# CONFIG_SSB is not set -CONFIG_MFD_SUPPORT=y -# CONFIG_MFD_CORE is not set -# CONFIG_MFD_SM501 is not set -# CONFIG_MFD_SH_MOBILE_SDHI is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_MFD_TMIO is not set -# CONFIG_ABX500_CORE is not set -# CONFIG_REGULATOR is not set -# CONFIG_MEDIA_SUPPORT is not set - -# -# Graphics support -# -# CONFIG_VGASTATE is not set -# CONFIG_VIDEO_OUTPUT_CONTROL is not set -# CONFIG_FB is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - -# -# Display device support -# -# CONFIG_DISPLAY_SUPPORT is not set - -# -# Console display driver support -# -CONFIG_DUMMY_CONSOLE=y -# CONFIG_SOUND is not set -CONFIG_HID_SUPPORT=y -CONFIG_HID=y -# CONFIG_HIDRAW is not set -# CONFIG_HID_PID is not set - -# -# Special HID drivers -# # CONFIG_USB_SUPPORT is not set -# CONFIG_MMC is not set -# CONFIG_MEMSTICK is not set -# CONFIG_NEW_LEDS is not set -# CONFIG_ACCESSIBILITY is not set -CONFIG_RTC_LIB=y -# CONFIG_RTC_CLASS is not set -# CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set -# CONFIG_UIO is not set -# CONFIG_STAGING is not set - -# -# File systems -# CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=y -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set -CONFIG_EXT3_FS_XATTR=y -# CONFIG_EXT3_FS_POSIX_ACL is not set -# CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4_FS is not set -CONFIG_JBD=y -CONFIG_FS_MBCACHE=y -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_FS_POSIX_ACL is not set -# CONFIG_XFS_FS is not set -# CONFIG_GFS2_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set -# CONFIG_NILFS2_FS is not set -CONFIG_FILE_LOCKING=y -CONFIG_FSNOTIFY=y -CONFIG_DNOTIFY=y CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -# CONFIG_QUOTA is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_FUSE_FS is not set - -# -# Caches -# -# CONFIG_FSCACHE is not set - -# -# CD-ROM/DVD Filesystems -# CONFIG_ISO9660_FS=y -# CONFIG_JOLIET is not set -# CONFIG_ZISOFS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -CONFIG_FAT_FS=y -# CONFIG_MSDOS_FS is not set CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y -CONFIG_PROC_SYSCTL=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_SYSFS=y CONFIG_TMPFS=y -# CONFIG_TMPFS_POSIX_ACL is not set -# CONFIG_HUGETLBFS is not set -# CONFIG_HUGETLB_PAGE is not set -# CONFIG_CONFIGFS_FS is not set -CONFIG_MISC_FILESYSTEMS=y -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_LOGFS is not set -# CONFIG_CRAMFS is not set CONFIG_SQUASHFS=y -# CONFIG_SQUASHFS_XATTRS is not set -# CONFIG_SQUASHFS_EMBEDDED is not set -CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 -# CONFIG_VXFS_FS is not set CONFIG_MINIX_FS=y -# CONFIG_OMFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set -CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y -# CONFIG_NFS_V3 is not set -# CONFIG_NFS_V4 is not set CONFIG_ROOT_NFS=y -# CONFIG_NFSD is not set -CONFIG_LOCKD=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CEPH_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" CONFIG_NLS_CODEPAGE_437=y -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set CONFIG_NLS_CODEPAGE_932=y -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set CONFIG_NLS_ISO8859_1=y -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set -# CONFIG_DLM is not set - -# -# Kernel hacking -# -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -# CONFIG_PRINTK_TIME is not set -CONFIG_ENABLE_WARN_DEPRECATED=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FRAME_WARN=1024 -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_STRIP_ASM_SYMS is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_FS is not set -# CONFIG_HEADERS_CHECK is not set CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_SHIRQ is not set # CONFIG_DETECT_SOFTLOCKUP is not set -# CONFIG_DETECT_HUNG_TASK is not set # CONFIG_SCHED_DEBUG is not set -# CONFIG_SCHEDSTATS is not set -# CONFIG_TIMER_STATS is not set -# CONFIG_DEBUG_OBJECTS is not set -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_KMEMLEAK is not set -# CONFIG_DEBUG_RT_MUTEXES is not set -# CONFIG_RT_MUTEX_TESTER is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_DEBUG_MUTEXES is not set -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_PROVE_LOCKING is not set -# CONFIG_LOCK_STAT is not set -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -# CONFIG_DEBUG_KOBJECT is not set # CONFIG_DEBUG_BUGVERBOSE is not set CONFIG_DEBUG_INFO=y -# CONFIG_DEBUG_VM is not set -# CONFIG_DEBUG_WRITECOUNT is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_SG is not set -# CONFIG_DEBUG_NOTIFIERS is not set -# CONFIG_DEBUG_CREDENTIALS is not set -# CONFIG_FRAME_POINTER is not set -# CONFIG_RCU_TORTURE_TEST is not set # CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_BACKTRACE_SELF_TEST is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set -# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set -# CONFIG_FAULT_INJECTION is not set -# CONFIG_LATENCYTOP is not set -# CONFIG_SYSCTL_SYSCALL_CHECK is not set -# CONFIG_PAGE_POISONING is not set -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y -CONFIG_HAVE_SYSCALL_TRACEPOINTS=y -CONFIG_TRACING_SUPPORT=y # CONFIG_FTRACE is not set -# CONFIG_DMA_API_DEBUG is not set -# CONFIG_ATOMIC64_SELFTEST is not set -# CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_KGDB is not set -# CONFIG_SH_STANDARD_BIOS is not set -# CONFIG_STACK_DEBUG is not set -# CONFIG_DEBUG_STACK_USAGE is not set -# CONFIG_4KSTACKS is not set -# CONFIG_DUMP_CODE is not set -# CONFIG_DWARF_UNWINDER is not set -# CONFIG_SH_NO_BSS_INIT is not set - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set -# CONFIG_SECURITYFS is not set -# CONFIG_DEFAULT_SECURITY_SELINUX is not set -# CONFIG_DEFAULT_SECURITY_SMACK is not set -# CONFIG_DEFAULT_SECURITY_TOMOYO is not set -CONFIG_DEFAULT_SECURITY_DAC=y -CONFIG_DEFAULT_SECURITY="" -CONFIG_CRYPTO=y - -# -# Crypto core or helper -# -# CONFIG_CRYPTO_MANAGER is not set -# CONFIG_CRYPTO_MANAGER2 is not set -# CONFIG_CRYPTO_GF128MUL is not set -# CONFIG_CRYPTO_NULL is not set -# CONFIG_CRYPTO_CRYPTD is not set -# CONFIG_CRYPTO_AUTHENC is not set -# CONFIG_CRYPTO_TEST is not set - -# -# Authenticated Encryption with Associated Data -# -# CONFIG_CRYPTO_CCM is not set -# CONFIG_CRYPTO_GCM is not set -# CONFIG_CRYPTO_SEQIV is not set - -# -# Block modes -# -# CONFIG_CRYPTO_CBC is not set -# CONFIG_CRYPTO_CTR is not set -# CONFIG_CRYPTO_CTS is not set -# CONFIG_CRYPTO_ECB is not set -# CONFIG_CRYPTO_LRW is not set -# CONFIG_CRYPTO_PCBC is not set -# CONFIG_CRYPTO_XTS is not set - -# -# Hash modes -# -# CONFIG_CRYPTO_HMAC is not set -# CONFIG_CRYPTO_XCBC is not set -# CONFIG_CRYPTO_VMAC is not set - -# -# Digest -# -# CONFIG_CRYPTO_CRC32C is not set -# CONFIG_CRYPTO_GHASH is not set -# CONFIG_CRYPTO_MD4 is not set -# CONFIG_CRYPTO_MD5 is not set -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_RMD128 is not set -# CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set -# CONFIG_CRYPTO_SHA1 is not set -# CONFIG_CRYPTO_SHA256 is not set -# CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_WP512 is not set - -# -# Ciphers -# -# CONFIG_CRYPTO_AES is not set -# CONFIG_CRYPTO_ANUBIS is not set -# CONFIG_CRYPTO_ARC4 is not set -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -# CONFIG_CRYPTO_DES is not set -# CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_SALSA20 is not set -# CONFIG_CRYPTO_SEED is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_TWOFISH is not set - -# -# Compression -# -# CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_ZLIB is not set -# CONFIG_CRYPTO_LZO is not set - -# -# Random Number Generation -# # CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRYPTO_HW=y -# CONFIG_VIRTUALIZATION is not set -# CONFIG_BINARY_PRINTF is not set - -# -# Library routines -# -CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y -# CONFIG_CRC_CCITT is not set -# CONFIG_CRC16 is not set -# CONFIG_CRC_T10DIF is not set -# CONFIG_CRC_ITU_T is not set -CONFIG_CRC32=y -# CONFIG_CRC7 is not set -# CONFIG_LIBCRC32C is not set -CONFIG_ZLIB_INFLATE=y -CONFIG_DECOMPRESS_GZIP=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_DMA=y -CONFIG_HAVE_LMB=y -CONFIG_NLATTR=y -CONFIG_GENERIC_ATOMIC64=y -- cgit v1.1 From fd0964c5f1bdaa979a7ea5cfc9af2de9b0a1e766 Mon Sep 17 00:00:00 2001 From: Heikki Krogerus Date: Thu, 19 Aug 2010 15:09:37 +0300 Subject: omap: rx51: Add support for USB chargers This enables isp1704 power supply driver on RX51, allowing USB charger detection with N900. Signed-off-by: Heikki Krogerus Acked-by: Tony Lindgren Signed-off-by: Anton Vorontsov --- arch/arm/mach-omap2/board-rx51-peripherals.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index 9a5eb87..a4b1f8b 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -104,6 +104,10 @@ static struct spi_board_info rx51_peripherals_spi_board_info[] __initdata = { }, }; +static struct platform_device rx51_charger_device = { + .name = "isp1704_charger", +}; + #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) #define RX51_GPIO_CAMERA_LENS_COVER 110 @@ -909,5 +913,6 @@ void __init rx51_peripherals_init(void) spi_register_board_info(rx51_peripherals_spi_board_info, ARRAY_SIZE(rx51_peripherals_spi_board_info)); omap2_hsmmc_init(mmc); + platform_device_register(&rx51_charger_device); } -- cgit v1.1 From a8165e0e6f0511d14132423b4bce2d285e890fc8 Mon Sep 17 00:00:00 2001 From: Jarkko Nikula Date: Mon, 23 Aug 2010 10:35:05 +0300 Subject: omap: rx51: Remove redefinition of rx51_aic3x_data Redefinition of rx51_aic3x_data got introduced when merging upstread changes for 2.6.36 and ASoC Multi-Component Support. This must go together with multi-component commit f0fba2a. Signed-off-by: Jarkko Nikula Cc: Tony Lindgren Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- arch/arm/mach-omap2/board-rx51-peripherals.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index 897d960..11ce4b2 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -710,10 +710,6 @@ static struct twl4030_platform_data rx51_twldata __initdata = { .vio = &rx51_vio, }; -static struct aic3x_pdata rx51_aic3x_data __initdata = { - .gpio_reset = 60, -}; - static struct tpa6130a2_platform_data rx51_tpa6130a2_data __initdata = { .id = TPA6130A2, .power_gpio = 98, -- cgit v1.1 From e4b6b74ffd32d114227a5dcfe814e2cecd80554b Mon Sep 17 00:00:00 2001 From: Dimitris Papastamos Date: Thu, 26 Aug 2010 16:07:23 +0100 Subject: ARM: S3C64XX: Fix fallthrough bug in i2sv3 gpio configuration, improve logging If the platform device id is 1, the code will fallthrough the case and incorrectly return -EINVAL. Add a break to avoid fallthrough. Make logging slightly more verbose by including the device id. This fixes an issue only present in multi-component. Signed-off-by: Dimitris Papastamos Acked-by: Liam Girdwood Signed-off-by: Mark Brown --- arch/arm/mach-s3c64xx/dev-audio.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-s3c64xx/dev-audio.c b/arch/arm/mach-s3c64xx/dev-audio.c index f094258..3838335 100644 --- a/arch/arm/mach-s3c64xx/dev-audio.c +++ b/arch/arm/mach-s3c64xx/dev-audio.c @@ -43,8 +43,10 @@ static int s3c64xx_i2sv3_cfg_gpio(struct platform_device *pdev) s3c_gpio_cfgpin(S3C64XX_GPE(2), S3C64XX_GPE2_I2S1_LRCLK); s3c_gpio_cfgpin(S3C64XX_GPE(3), S3C64XX_GPE3_I2S1_DI); s3c_gpio_cfgpin(S3C64XX_GPE(4), S3C64XX_GPE4_I2S1_D0); + break; default: - printk(KERN_DEBUG "Invalid I2S Controller number!"); + printk(KERN_DEBUG "Invalid I2S Controller number: %d\n", + pdev->id); return -EINVAL; } @@ -184,7 +186,8 @@ static int s3c64xx_pcm_cfg_gpio(struct platform_device *pdev) s3c_gpio_cfgpin(S3C64XX_GPE(4), S3C64XX_GPE4_PCM1_SOUT); break; default: - printk(KERN_DEBUG "Invalid PCM Controller number!"); + printk(KERN_DEBUG "Invalid PCM Controller number: %d\n", + pdev->id); return -EINVAL; } -- cgit v1.1 From ffc4fdbbe1b4be79e98340ebcd5a0ade6f5de318 Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Thu, 26 Aug 2010 14:53:51 +0200 Subject: ASoC: fix au1x platform This patch fixes up the au1x audio platform after the multi-component merge: - compile fixes and updates to get DB1200 platform audio working again, - removal of global variables in AC97/I2S/DMA(PCM) modules. The AC97 part is limited to one instance only for now due to issues with getting at driver data in the soc_ac97_ops. Signed-off-by: Manuel Lauss Acked-by: Liam Girdwood Signed-off-by: Mark Brown --- arch/mips/alchemy/devboards/db1200/platform.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/mips/alchemy/devboards/db1200/platform.c b/arch/mips/alchemy/devboards/db1200/platform.c index 3fa34c3..fbb5593 100644 --- a/arch/mips/alchemy/devboards/db1200/platform.c +++ b/arch/mips/alchemy/devboards/db1200/platform.c @@ -429,6 +429,11 @@ static struct platform_device db1200_audio_dev = { .resource = au1200_psc1_res, }; +static struct platform_device db1200_stac_dev = { + .name = "ac97-codec", + .id = 1, /* on PSC1 */ +}; + static struct platform_device *db1200_devs[] __initdata = { NULL, /* PSC0, selected by S6.8 */ &db1200_ide_dev, @@ -436,6 +441,7 @@ static struct platform_device *db1200_devs[] __initdata = { &db1200_rtc_dev, &db1200_nand_dev, &db1200_audio_dev, + &db1200_stac_dev, }; static int __init db1200_dev_init(void) -- cgit v1.1 From ada69e3c1c0be591aa2e6282fb252c668ccb9a1c Mon Sep 17 00:00:00 2001 From: Vasily Khoruzhick Date: Mon, 30 Aug 2010 11:28:09 +0300 Subject: ARM: S3C24XX: I2S multi-component-related fixes Export s3c_device_pcm for all S3C24xx-devices, not only for S3C2440; Fix device name for s3c_device_iis; Signed-off-by: Vasily Khoruzhick Acked-by: Liam Girdwood Signed-off-by: Mark Brown --- arch/arm/plat-s3c24xx/devs.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c index 9f8ee5e..2f91057 100644 --- a/arch/arm/plat-s3c24xx/devs.c +++ b/arch/arm/plat-s3c24xx/devs.c @@ -247,7 +247,7 @@ static struct resource s3c_iis_resource[] = { static u64 s3c_device_iis_dmamask = 0xffffffffUL; struct platform_device s3c_device_iis = { - .name = "s3c2410-iis", + .name = "s3c24xx-iis", .id = -1, .num_resources = ARRAY_SIZE(s3c_iis_resource), .resource = s3c_iis_resource, @@ -259,6 +259,21 @@ struct platform_device s3c_device_iis = { EXPORT_SYMBOL(s3c_device_iis); +/* ASoC PCM DMA */ + +static u64 s3c_device_audio_dmamask = 0xffffffffUL; + +struct platform_device s3c_device_pcm = { + .name = "s3c24xx-pcm-audio", + .id = -1, + .dev = { + .dma_mask = &s3c_device_audio_dmamask, + .coherent_dma_mask = 0xffffffffUL + } +}; + +EXPORT_SYMBOL(s3c_device_pcm); + /* RTC */ static struct resource s3c_rtc_resource[] = { @@ -481,8 +496,6 @@ static struct resource s3c_ac97_resource[] = { }, }; -static u64 s3c_device_audio_dmamask = 0xffffffffUL; - struct platform_device s3c_device_ac97 = { .name = "s3c-ac97", .id = -1, @@ -496,19 +509,6 @@ struct platform_device s3c_device_ac97 = { EXPORT_SYMBOL(s3c_device_ac97); -/* ASoC PCM DMA */ - -struct platform_device s3c_device_pcm = { - .name = "s3c24xx-pcm-audio", - .id = -1, - .dev = { - .dma_mask = &s3c_device_audio_dmamask, - .coherent_dma_mask = 0xffffffffUL - } -}; - -EXPORT_SYMBOL(s3c_device_pcm); - /* ASoC I2S */ struct platform_device s3c2412_device_iis = { -- cgit v1.1 From c88e7b93a80bd46899c4cb09a9b2d52bb04d79bd Mon Sep 17 00:00:00 2001 From: "Arnaud Patard (Rtp)" Date: Mon, 30 Aug 2010 16:00:05 +0200 Subject: ASoC: OpenRD Client : Fix naming breakage due to multicomponent support multicomponent support added/changed some device name but added some typos, breaking existing OpenRD Client support. Signed-off-by: Arnaud Patard Acked-by: Liam Girdwood Signed-off-by: Mark Brown --- arch/arm/mach-kirkwood/common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index 0f6ee32..51ff23b 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -904,7 +904,7 @@ static struct platform_device kirkwood_i2s_device = { }; static struct platform_device kirkwood_pcm_device = { - .name = "kirkwood-pcm", + .name = "kirkwood-pcm-audio", .id = -1, }; -- cgit v1.1 From a17f79553f052f04d47689a842118f775f81b7e3 Mon Sep 17 00:00:00 2001 From: Abraham Arce Date: Tue, 31 Aug 2010 17:05:27 -0700 Subject: Input: add support for OMAP4 keyboard controller OMAP4 keyboard controller includes: - built-in scanning algorithm - debouncing feature Driver implementation is based on matrix_keypad.c Signed-off-by: Syed Rafiuddin Signed-off-by: Abraham Arce Signed-off-by: Dmitry Torokhov --- arch/arm/plat-omap/include/plat/omap4-keypad.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 arch/arm/plat-omap/include/plat/omap4-keypad.h (limited to 'arch') diff --git a/arch/arm/plat-omap/include/plat/omap4-keypad.h b/arch/arm/plat-omap/include/plat/omap4-keypad.h new file mode 100644 index 0000000..522a8ab --- /dev/null +++ b/arch/arm/plat-omap/include/plat/omap4-keypad.h @@ -0,0 +1,16 @@ +#ifndef ARCH_ARM_PLAT_OMAP4_KEYPAD_H +#define ARCH_ARM_PLAT_OMAP4_KEYPAD_H + +#include + +struct omap4_keypad_platform_data { + const struct matrix_keymap_data *keymap_data; + + u8 rows; + u8 cols; + + u16 irq; + void __iomem *base; +}; + +#endif -- cgit v1.1 From b744c679f62b368cb94c21c1dcd4618e42d88d63 Mon Sep 17 00:00:00 2001 From: Dmitry Kasatkin Date: Fri, 3 Sep 2010 19:13:55 +0800 Subject: crypto: updates to enable omap aes Signed-off-by: Dmitry Kasatkin Signed-off-by: Herbert Xu --- arch/arm/mach-omap2/clock2420_data.c | 2 +- arch/arm/mach-omap2/clock2430_data.c | 2 +- arch/arm/mach-omap2/clock3xxx_data.c | 2 +- arch/arm/mach-omap2/devices.c | 71 ++++++++++++++++++++++++++++++++++++ 4 files changed, 74 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c index 37d65d6..5f2066a 100644 --- a/arch/arm/mach-omap2/clock2420_data.c +++ b/arch/arm/mach-omap2/clock2420_data.c @@ -1838,7 +1838,7 @@ static struct omap_clk omap2420_clks[] = { CLK(NULL, "des_ick", &des_ick, CK_242X), CLK("omap-sham", "ick", &sha_ick, CK_242X), CLK("omap_rng", "ick", &rng_ick, CK_242X), - CLK(NULL, "aes_ick", &aes_ick, CK_242X), + CLK("omap-aes", "ick", &aes_ick, CK_242X), CLK(NULL, "pka_ick", &pka_ick, CK_242X), CLK(NULL, "usb_fck", &usb_fck, CK_242X), CLK("musb_hdrc", "fck", &osc_ck, CK_242X), diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c index b33118f..701a171 100644 --- a/arch/arm/mach-omap2/clock2430_data.c +++ b/arch/arm/mach-omap2/clock2430_data.c @@ -1926,7 +1926,7 @@ static struct omap_clk omap2430_clks[] = { CLK(NULL, "des_ick", &des_ick, CK_243X), CLK("omap-sham", "ick", &sha_ick, CK_243X), CLK("omap_rng", "ick", &rng_ick, CK_243X), - CLK(NULL, "aes_ick", &aes_ick, CK_243X), + CLK("omap-aes", "ick", &aes_ick, CK_243X), CLK(NULL, "pka_ick", &pka_ick, CK_243X), CLK(NULL, "usb_fck", &usb_fck, CK_243X), CLK("musb_hdrc", "ick", &usbhs_ick, CK_243X), diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index d337441..e3e65d1 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -3288,7 +3288,7 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2 | CK_AM35XX), CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2 | CK_AM35XX), CLK(NULL, "icr_ick", &icr_ick, CK_343X), - CLK(NULL, "aes2_ick", &aes2_ick, CK_343X), + CLK("omap-aes", "ick", &aes2_ick, CK_343X), CLK("omap-sham", "ick", &sha12_ick, CK_343X), CLK(NULL, "des2_ick", &des2_ick, CK_343X), CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_3XXX), diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 03e6c9e..072893a 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -552,6 +552,76 @@ static void omap_init_sham(void) static inline void omap_init_sham(void) { } #endif +#if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE) + +#ifdef CONFIG_ARCH_OMAP24XX +static struct resource omap2_aes_resources[] = { + { + .start = OMAP24XX_SEC_AES_BASE, + .end = OMAP24XX_SEC_AES_BASE + 0x4C, + .flags = IORESOURCE_MEM, + }, + { + .start = OMAP24XX_DMA_AES_TX, + .flags = IORESOURCE_DMA, + }, + { + .start = OMAP24XX_DMA_AES_RX, + .flags = IORESOURCE_DMA, + } +}; +static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources); +#else +#define omap2_aes_resources NULL +#define omap2_aes_resources_sz 0 +#endif + +#ifdef CONFIG_ARCH_OMAP34XX +static struct resource omap3_aes_resources[] = { + { + .start = OMAP34XX_SEC_AES_BASE, + .end = OMAP34XX_SEC_AES_BASE + 0x4C, + .flags = IORESOURCE_MEM, + }, + { + .start = OMAP34XX_DMA_AES2_TX, + .flags = IORESOURCE_DMA, + }, + { + .start = OMAP34XX_DMA_AES2_RX, + .flags = IORESOURCE_DMA, + } +}; +static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources); +#else +#define omap3_aes_resources NULL +#define omap3_aes_resources_sz 0 +#endif + +static struct platform_device aes_device = { + .name = "omap-aes", + .id = -1, +}; + +static void omap_init_aes(void) +{ + if (cpu_is_omap24xx()) { + aes_device.resource = omap2_aes_resources; + aes_device.num_resources = omap2_aes_resources_sz; + } else if (cpu_is_omap34xx()) { + aes_device.resource = omap3_aes_resources; + aes_device.num_resources = omap3_aes_resources_sz; + } else { + pr_err("%s: platform not supported\n", __func__); + return; + } + platform_device_register(&aes_device); +} + +#else +static inline void omap_init_aes(void) { } +#endif + /*-------------------------------------------------------------------------*/ #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) @@ -908,6 +978,7 @@ static int __init omap2_init_devices(void) omap_hdq_init(); omap_init_sti(); omap_init_sham(); + omap_init_aes(); omap_init_vout(); return 0; -- cgit v1.1 From fe8e0c25cad28e8858ecfa5863333c70685a6811 Mon Sep 17 00:00:00 2001 From: Alexander van Heukelum Date: Mon, 6 Sep 2010 20:53:42 +0200 Subject: x86, 32-bit: Align percpu area and irq stacks to THREAD_SIZE The irq stacks, located in the percpu-area, need to be THREAD_SIZE aligned. Add the infrastucture to align percpu variables to larger-than-pagesize amounts within the percpu area, and use it to specify the alignment for the irq stacks. Also align the percpu area itself to THREAD_SIZE. This should make irq stacks work with 8K THREAD_SIZE. Signed-off-by: Alexander van Heukelum Cc: Tejun Heo Cc: hch@lst.de LKML-Reference: <1283799222.15941.1393621887@webmail.messagingengine.com> Signed-off-by: Ingo Molnar --- arch/x86/kernel/irq_32.c | 4 ++-- arch/x86/kernel/vmlinux.lds.S | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/x86/kernel/irq_32.c b/arch/x86/kernel/irq_32.c index 3b5609f..50fbbe6 100644 --- a/arch/x86/kernel/irq_32.c +++ b/arch/x86/kernel/irq_32.c @@ -60,8 +60,8 @@ union irq_ctx { static DEFINE_PER_CPU(union irq_ctx *, hardirq_ctx); static DEFINE_PER_CPU(union irq_ctx *, softirq_ctx); -static DEFINE_PER_CPU_PAGE_ALIGNED(union irq_ctx, hardirq_stack); -static DEFINE_PER_CPU_PAGE_ALIGNED(union irq_ctx, softirq_stack); +static DEFINE_PER_CPU_MULTIPAGE_ALIGNED(union irq_ctx, hardirq_stack, THREAD_SIZE); +static DEFINE_PER_CPU_MULTIPAGE_ALIGNED(union irq_ctx, softirq_stack, THREAD_SIZE); static void call_on_stack(void *func, void *stack) { diff --git a/arch/x86/kernel/vmlinux.lds.S b/arch/x86/kernel/vmlinux.lds.S index d0bb522..bb89947 100644 --- a/arch/x86/kernel/vmlinux.lds.S +++ b/arch/x86/kernel/vmlinux.lds.S @@ -273,7 +273,7 @@ SECTIONS } #if !defined(CONFIG_X86_64) || !defined(CONFIG_SMP) - PERCPU(PAGE_SIZE) + PERCPU(THREAD_SIZE) #endif . = ALIGN(PAGE_SIZE); -- cgit v1.1 From 9ec165166850930dc3079bfa39f4c1397abd7337 Mon Sep 17 00:00:00 2001 From: Matt Fleming Date: Tue, 7 Sep 2010 16:09:14 +0900 Subject: sh: Additional register definitions for SH7786 PCIe. Signed-off-by: Matt Fleming Signed-off-by: Paul Mundt --- arch/sh/drivers/pci/pcie-sh7786.h | 56 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 54 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/sh/drivers/pci/pcie-sh7786.h b/arch/sh/drivers/pci/pcie-sh7786.h index 90a6992..1ee054e 100644 --- a/arch/sh/drivers/pci/pcie-sh7786.h +++ b/arch/sh/drivers/pci/pcie-sh7786.h @@ -55,8 +55,11 @@ #define BITS_ERRRCV (0) /* 0 ERRRCV 0 */ #define MASK_ERRRCV (1< Date: Tue, 7 Sep 2010 16:11:04 +0900 Subject: sh: Make SH7786 PCIe port reset logic more aggressive. This attempts a more complete port reset, building on top of the existing approach. Signed-off-by: Paul Mundt --- arch/sh/drivers/pci/pcie-sh7786.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/sh/drivers/pci/pcie-sh7786.c b/arch/sh/drivers/pci/pcie-sh7786.c index 03e6d82..40b0ed0 100644 --- a/arch/sh/drivers/pci/pcie-sh7786.c +++ b/arch/sh/drivers/pci/pcie-sh7786.c @@ -204,6 +204,16 @@ static int phy_init(struct pci_channel *chan) return -ETIMEDOUT; } +static void pcie_reset(struct sh7786_pcie_port *port) +{ + struct pci_channel *chan = port->hose; + + pci_write_reg(chan, 1, SH4A_PCIESRSTR); + pci_write_reg(chan, 0, SH4A_PCIETCTLR); + pci_write_reg(chan, 0, SH4A_PCIESRSTR); + pci_write_reg(chan, 0, SH4A_PCIETXVC0SR); +} + static int pcie_init(struct sh7786_pcie_port *port) { struct pci_channel *chan = port->hose; @@ -213,7 +223,7 @@ static int pcie_init(struct sh7786_pcie_port *port) int ret, i; /* Begin initialization */ - pci_write_reg(chan, 0, SH4A_PCIETCTLR); + pcie_reset(port); /* Initialize as type1. */ data = pci_read_reg(chan, SH4A_PCIEPCICONF3); -- cgit v1.1 From 2c5f674339d5e4c02cca7af13ec02bd9b5a96b60 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Tue, 7 Sep 2010 16:12:26 +0900 Subject: sh: Establish a SuperHyway<->PCIe window mapping on SH7786 PCIe. This bumps up the low address to match the physical memory windows for SHway<->PCIe transfers. The previous implementation was banking on a 1:1 virt<->phys SHway mapping, which doesn't apply here. Signed-off-by: Paul Mundt --- arch/sh/drivers/pci/pcie-sh7786.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/sh/drivers/pci/pcie-sh7786.c b/arch/sh/drivers/pci/pcie-sh7786.c index 40b0ed0..4cd8314 100644 --- a/arch/sh/drivers/pci/pcie-sh7786.c +++ b/arch/sh/drivers/pci/pcie-sh7786.c @@ -354,8 +354,8 @@ static int pcie_init(struct sh7786_pcie_port *port) __raw_writel(((roundup_pow_of_two(size) / SZ_256K) - 1) << 18, chan->reg_base + SH4A_PCIEPAMR(i)); + pci_write_reg(chan, res->start, SH4A_PCIEPARL(i)); pci_write_reg(chan, 0x00000000, SH4A_PCIEPARH(i)); - pci_write_reg(chan, 0x00000000, SH4A_PCIEPARL(i)); enable_mask = MASK_PARE; if (res->flags & IORESOURCE_IO) -- cgit v1.1 From da03a63ac843711887a85e5d90dd69399b1b9164 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Tue, 7 Sep 2010 17:03:10 +0900 Subject: sh: Ignore 32-bit windows in 29-bit mode for SH7786 PCIe. Certain memory windows are only available for 32-bit space, so skip over these in 29-bit mode. This will severely restrict the amount of memory that can be mapped, but since a boot loader bug makes booting in 29-bit mode close to impossible anyways, everything is ok. Signed-off-by: Paul Mundt --- arch/sh/drivers/pci/pcie-sh7786.c | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/sh/drivers/pci/pcie-sh7786.c b/arch/sh/drivers/pci/pcie-sh7786.c index 4cd8314..4f79fd9 100644 --- a/arch/sh/drivers/pci/pcie-sh7786.c +++ b/arch/sh/drivers/pci/pcie-sh7786.c @@ -220,7 +220,7 @@ static int pcie_init(struct sh7786_pcie_port *port) unsigned int data; phys_addr_t memphys; size_t memsize; - int ret, i; + int ret, i, win; /* Begin initialization */ pcie_reset(port); @@ -337,13 +337,19 @@ static int pcie_init(struct sh7786_pcie_port *port) printk(KERN_NOTICE "PCI: PCIe#%d link width %d\n", port->index, (data >> 20) & 0x3f); - - for (i = 0; i < chan->nr_resources; i++) { + for (i = win = 0; i < chan->nr_resources; i++) { struct resource *res = chan->resources + i; resource_size_t size; u32 enable_mask; - pci_write_reg(chan, 0x00000000, SH4A_PCIEPTCTLR(i)); + /* + * We can't use the 32-bit mode windows in legacy 29-bit + * mode, so just skip them entirely. + */ + if ((res->flags & IORESOURCE_MEM_32BIT) && __in_29bit_mode()) + continue; + + pci_write_reg(chan, 0x00000000, SH4A_PCIEPTCTLR(win)); size = resource_size(res); @@ -352,16 +358,18 @@ static int pcie_init(struct sh7786_pcie_port *port) * keeps things pretty simple. */ __raw_writel(((roundup_pow_of_two(size) / SZ_256K) - 1) << 18, - chan->reg_base + SH4A_PCIEPAMR(i)); + chan->reg_base + SH4A_PCIEPAMR(win)); - pci_write_reg(chan, res->start, SH4A_PCIEPARL(i)); - pci_write_reg(chan, 0x00000000, SH4A_PCIEPARH(i)); + pci_write_reg(chan, res->start, SH4A_PCIEPARL(win)); + pci_write_reg(chan, 0x00000000, SH4A_PCIEPARH(win)); enable_mask = MASK_PARE; if (res->flags & IORESOURCE_IO) enable_mask |= MASK_SPC; - pci_write_reg(chan, enable_mask, SH4A_PCIEPTCTLR(i)); + pci_write_reg(chan, enable_mask, SH4A_PCIEPTCTLR(win)); + + win++; } return 0; -- cgit v1.1 From f048519309dbaedd03807ddbb9fa22f5616cfd43 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Tue, 7 Sep 2010 17:05:08 +0900 Subject: sh: Properly wire up channel 2's I/O window on SH7786 PCIe. An IORESOURCE_IO was missing here, which meant that we weren't properly establishing the I/O window for this particular slot. With this corrected, cards with I/O BARs have them actually assigned and accessible. Signed-off-by: Paul Mundt --- arch/sh/drivers/pci/pcie-sh7786.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/sh/drivers/pci/pcie-sh7786.c b/arch/sh/drivers/pci/pcie-sh7786.c index 4f79fd9..c1e862a 100644 --- a/arch/sh/drivers/pci/pcie-sh7786.c +++ b/arch/sh/drivers/pci/pcie-sh7786.c @@ -82,6 +82,7 @@ static struct resource sh7786_pci2_resources[] = { .name = "PCIe2 IO", .start = 0xfc800000, .end = 0xfc800000 + SZ_4M - 1, + .flags = IORESOURCE_IO, }, { .name = "PCIe2 MEM 0", .start = 0x80000000, -- cgit v1.1 From 1c3bb3871af53a2a8620bc48b5535f6d83386773 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Tue, 7 Sep 2010 17:07:05 +0900 Subject: sh: Hook up 3rd memory window for all SH7786 PCIe channels. Now that the resource assignment issues are resolved, we can finally wire up the small third memory window -- in the future we may reclaim this for MSI. Signed-off-by: Paul Mundt --- arch/sh/drivers/pci/pcie-sh7786.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/sh/drivers/pci/pcie-sh7786.c b/arch/sh/drivers/pci/pcie-sh7786.c index c1e862a..5acbaa2 100644 --- a/arch/sh/drivers/pci/pcie-sh7786.c +++ b/arch/sh/drivers/pci/pcie-sh7786.c @@ -51,6 +51,7 @@ static struct resource sh7786_pci0_resources[] = { .name = "PCIe0 MEM 2", .start = 0xfe100000, .end = 0xfe100000 + SZ_1M - 1, + .flags = IORESOURCE_MEM, }, }; @@ -74,6 +75,7 @@ static struct resource sh7786_pci1_resources[] = { .name = "PCIe1 MEM 2", .start = 0xfe300000, .end = 0xfe300000 + SZ_1M - 1, + .flags = IORESOURCE_MEM, }, }; @@ -97,6 +99,7 @@ static struct resource sh7786_pci2_resources[] = { .name = "PCIe2 MEM 2", .start = 0xfcd00000, .end = 0xfcd00000 + SZ_1M - 1, + .flags = IORESOURCE_MEM, }, }; -- cgit v1.1 From d36deae75011a7890f0e730dd0f867c64081cb50 Mon Sep 17 00:00:00 2001 From: Jan Glauber Date: Tue, 7 Sep 2010 21:14:39 +0000 Subject: qdio: extend API to allow polling Extend the qdio API to allow polling in the upper-layer driver. This is needed by qeth to use NAPI. To use the new interface the upper-layer driver must specify the queue_start_poll(). This callback is used to signal the upper-layer driver that is has initiative and must process the inbound queue by calling qdio_get_next_buffers(). If the upper-layer driver wants to stop polling it calls qdio_start_irq(). Since adapter interrupts are not completely stoppable qdio implements a software bit QDIO_QUEUE_IRQS_DISABLED to safely disable interrupts for an input queue. The old interface is preserved and will be used as is by zfcp. Signed-off-by: Jan Glauber Signed-off-by: Martin Schwidefsky Signed-off-by: Frank Blaschka Signed-off-by: David S. Miller --- arch/s390/include/asm/qdio.h | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/s390/include/asm/qdio.h b/arch/s390/include/asm/qdio.h index 2ba6302..46e96bc 100644 --- a/arch/s390/include/asm/qdio.h +++ b/arch/s390/include/asm/qdio.h @@ -360,6 +360,7 @@ struct qdio_initialize { unsigned int no_output_qs; qdio_handler_t *input_handler; qdio_handler_t *output_handler; + void (*queue_start_poll) (struct ccw_device *, int, unsigned long); unsigned long int_parm; void **input_sbal_addr_array; void **output_sbal_addr_array; @@ -377,11 +378,13 @@ struct qdio_initialize { extern int qdio_allocate(struct qdio_initialize *); extern int qdio_establish(struct qdio_initialize *); extern int qdio_activate(struct ccw_device *); - -extern int do_QDIO(struct ccw_device *cdev, unsigned int callflags, - int q_nr, unsigned int bufnr, unsigned int count); -extern int qdio_shutdown(struct ccw_device*, int); +extern int do_QDIO(struct ccw_device *, unsigned int, int, unsigned int, + unsigned int); +extern int qdio_start_irq(struct ccw_device *, int); +extern int qdio_stop_irq(struct ccw_device *, int); +extern int qdio_get_next_buffers(struct ccw_device *, int, int *, int *); +extern int qdio_shutdown(struct ccw_device *, int); extern int qdio_free(struct ccw_device *); -extern int qdio_get_ssqd_desc(struct ccw_device *dev, struct qdio_ssqd_desc*); +extern int qdio_get_ssqd_desc(struct ccw_device *, struct qdio_ssqd_desc *); #endif /* __QDIO_H__ */ -- cgit v1.1 From db7829c6cc32f3c0c9a324118d743acb1abff081 Mon Sep 17 00:00:00 2001 From: Brian Gerst Date: Thu, 9 Sep 2010 18:17:26 +0200 Subject: x86, percpu: Optimize this_cpu_ptr Allow arches to implement __this_cpu_ptr, and provide an x86 version. Before: movq $foo, %rax movq %gs:this_cpu_off, %rdx addq %rdx, %rax After: movq $foo, %rax addq %gs:this_cpu_off, %rax The benefit is doing it in one less instruction and not clobbering a temporary register. tj: * Beefed up the comment a bit and renamed in-macro temp variable to match neighboring macros. * Folded fix for const pointer case found in linux-next. * Fixed sparse notation. Signed-off-by: Brian Gerst Signed-off-by: Tejun Heo --- arch/x86/include/asm/percpu.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch') diff --git a/arch/x86/include/asm/percpu.h b/arch/x86/include/asm/percpu.h index cd28f9a..f899e01 100644 --- a/arch/x86/include/asm/percpu.h +++ b/arch/x86/include/asm/percpu.h @@ -47,6 +47,20 @@ #ifdef CONFIG_SMP #define __percpu_arg(x) "%%"__stringify(__percpu_seg)":%P" #x #define __my_cpu_offset percpu_read(this_cpu_off) + +/* + * Compared to the generic __my_cpu_offset version, the following + * saves one instruction and avoids clobbering a temp register. + */ +#define __this_cpu_ptr(ptr) \ +({ \ + unsigned long tcp_ptr__; \ + __verify_pcpu_ptr(ptr); \ + asm volatile("add " __percpu_arg(1) ", %0" \ + : "=r" (tcp_ptr__) \ + : "m" (this_cpu_off), "0" (ptr)); \ + (typeof(*(ptr)) __kernel __force *)tcp_ptr__; \ +}) #else #define __percpu_arg(x) "%P" #x #endif -- cgit v1.1 From ef7315084ede82ea55f251003a6f0088d95d9fa6 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Fri, 27 Aug 2010 09:49:50 +0000 Subject: ARM: mach-shmobile: ap4evb: modify tsc2007 platform settings This patch modify x_plate_ohms to correct value for tsc2007, and removed un-necessary ts_get_pendown_state(). gpio_pull_up() was removed also. Signed-off-by: Kuninori Morimoto Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/board-ap4evb.c | 51 +++-------------------------------- 1 file changed, 3 insertions(+), 48 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c index 95935c8..0cb9e7c 100644 --- a/arch/arm/mach-shmobile/board-ap4evb.c +++ b/arch/arm/mach-shmobile/board-ap4evb.c @@ -756,7 +756,6 @@ device_initcall(hdmi_init_pm_clock); * FIXME !! * * gpio_no_direction - * gpio_pull_up * are quick_hack. * * current gpio frame work doesn't have @@ -768,58 +767,12 @@ static void __init gpio_no_direction(u32 addr) __raw_writeb(0x00, addr); } -static void __init gpio_pull_up(u32 addr) -{ - u8 data = __raw_readb(addr); - - data &= 0x0F; - data |= 0xC0; - __raw_writeb(data, addr); -} - /* TouchScreen */ #define IRQ28 evt2irq(0x3380) /* IRQ28A */ #define IRQ7 evt2irq(0x02e0) /* IRQ7A */ -static int ts_get_pendown_state(void) -{ - int val1, val2; - - gpio_free(GPIO_FN_IRQ28_123); - gpio_free(GPIO_FN_IRQ7_40); - - gpio_request(GPIO_PORT123, NULL); - gpio_request(GPIO_PORT40, NULL); - - gpio_direction_input(GPIO_PORT123); - gpio_direction_input(GPIO_PORT40); - - val1 = gpio_get_value(GPIO_PORT123); - val2 = gpio_get_value(GPIO_PORT40); - - gpio_request(GPIO_FN_IRQ28_123, NULL); /* for QHD */ - gpio_request(GPIO_FN_IRQ7_40, NULL); /* for WVGA */ - - return val1 ^ val2; -} - -#define PORT40CR 0xE6051028 -#define PORT123CR 0xE605007B -static int ts_init(void) -{ - gpio_request(GPIO_FN_IRQ28_123, NULL); /* for QHD */ - gpio_request(GPIO_FN_IRQ7_40, NULL); /* for WVGA */ - - gpio_pull_up(PORT40CR); - gpio_pull_up(PORT123CR); - - return 0; -} - static struct tsc2007_platform_data tsc2007_info = { .model = 2007, - .x_plate_ohms = 180, - .get_pendown_state = ts_get_pendown_state, - .init_platform_hw = ts_init, + .x_plate_ohms = 1000, }; static struct i2c_board_info tsc_device = { @@ -994,6 +947,7 @@ static void __init ap4evb_init(void) gpio_request(GPIO_FN_KEYIN4, NULL); /* enable TouchScreen */ + gpio_request(GPIO_FN_IRQ28_123, NULL); set_irq_type(IRQ28, IRQ_TYPE_LEVEL_LOW); tsc_device.irq = IRQ28; @@ -1069,6 +1023,7 @@ static void __init ap4evb_init(void) lcdc_info.ch[0].lcd_size_cfg.height = 91; /* enable TouchScreen */ + gpio_request(GPIO_FN_IRQ7_40, NULL); set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW); tsc_device.irq = IRQ7; -- cgit v1.1 From dd8a61a739f98c2cd2fbf811b5b659433f0023f6 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 31 Aug 2010 09:22:36 +0000 Subject: ARM: mach-shmobile: Extend AP4EVB LCD comments Extend dip switch comments for QHD and WVGA LCD panels on AP4EVB. Similar to the Ecovec comments. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/board-ap4evb.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c index 0cb9e7c..31e5b28 100644 --- a/arch/arm/mach-shmobile/board-ap4evb.c +++ b/arch/arm/mach-shmobile/board-ap4evb.c @@ -930,8 +930,10 @@ static void __init ap4evb_init(void) ARRAY_SIZE(i2c1_devices)); #ifdef CONFIG_AP4EVB_QHD + /* - * QHD + * For QHD Panel (MIPI-DSI, CONFIG_AP4EVB_QHD=y) and + * IRQ28 for Touch Panel, set dip switches S3, S43 as OFF, ON. */ /* enable KEYSC */ @@ -976,8 +978,10 @@ static void __init ap4evb_init(void) #else /* - * WVGA + * For WVGA Panel (18-bit RGB, CONFIG_AP4EVB_WVGA=y) and + * IRQ7 for Touch Panel, set dip switches S3, S43 to ON, OFF. */ + gpio_request(GPIO_FN_LCDD17, NULL); gpio_request(GPIO_FN_LCDD16, NULL); gpio_request(GPIO_FN_LCDD15, NULL); -- cgit v1.1 From f989ae5b01b065b2124f5b83fffaddda07f6a38c Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 31 Aug 2010 09:27:53 +0000 Subject: ARM: mach-shmobile: Use evt2irq() for sh7372 DMAC Use evt2irq() for DMAC resources on sh7372. This makes the code easier to read and also allows adjusting the INTC base offset without breaking platform data. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/setup-sh7372.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c index e26686c..f6cdf76 100644 --- a/arch/arm/mach-shmobile/setup-sh7372.c +++ b/arch/arm/mach-shmobile/setup-sh7372.c @@ -419,14 +419,14 @@ static struct resource sh7372_dmae0_resources[] = { }, { /* DMA error IRQ */ - .start = 246, - .end = 246, + .start = evt2irq(0x20c0), + .end = evt2irq(0x20c0), .flags = IORESOURCE_IRQ, }, { /* IRQ for channels 0-5 */ - .start = 240, - .end = 245, + .start = evt2irq(0x2000), + .end = evt2irq(0x20a0), .flags = IORESOURCE_IRQ, }, }; @@ -447,14 +447,14 @@ static struct resource sh7372_dmae1_resources[] = { }, { /* DMA error IRQ */ - .start = 254, - .end = 254, + .start = evt2irq(0x21c0), + .end = evt2irq(0x21c0), .flags = IORESOURCE_IRQ, }, { /* IRQ for channels 0-5 */ - .start = 248, - .end = 253, + .start = evt2irq(0x2100), + .end = evt2irq(0x21a0), .flags = IORESOURCE_IRQ, }, }; @@ -475,14 +475,14 @@ static struct resource sh7372_dmae2_resources[] = { }, { /* DMA error IRQ */ - .start = 262, - .end = 262, + .start = evt2irq(0x22c0), + .end = evt2irq(0x22c0), .flags = IORESOURCE_IRQ, }, { /* IRQ for channels 0-5 */ - .start = 256, - .end = 261, + .start = evt2irq(0x2200), + .end = evt2irq(0x22a0), .flags = IORESOURCE_IRQ, }, }; -- cgit v1.1 From 53b29b4c36cdfcb3d0641edf180db7ebd53ec029 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 2 Sep 2010 07:20:40 +0000 Subject: ARM: mach-shmobile: pfc-sh7372: modify wrong comment Signed-off-by: Kuninori Morimoto Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/pfc-sh7372.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/pfc-sh7372.c b/arch/arm/mach-shmobile/pfc-sh7372.c index ec42035..9c265da 100644 --- a/arch/arm/mach-shmobile/pfc-sh7372.c +++ b/arch/arm/mach-shmobile/pfc-sh7372.c @@ -166,12 +166,12 @@ enum { MSIOF2_TSYNC_MARK, MSIOF2_TSCK_MARK, MSIOF2_RXD_MARK, MSIOF2_TXD_MARK, - /* MSIOF3 */ + /* BBIF1 */ BBIF1_RXD_MARK, BBIF1_TSYNC_MARK, BBIF1_TSCK_MARK, BBIF1_TXD_MARK, BBIF1_RSCK_MARK, BBIF1_RSYNC_MARK, BBIF1_FLOW_MARK, BB_RX_FLOW_N_MARK, - /* MSIOF4 */ + /* BBIF2 */ BBIF2_TSCK1_MARK, BBIF2_TSYNC1_MARK, BBIF2_TXD1_MARK, BBIF2_RXD_MARK, @@ -976,12 +976,12 @@ static struct pinmux_gpio pinmux_gpios[] = { GPIO_FN(MSIOF2_TSYNC), GPIO_FN(MSIOF2_TSCK), GPIO_FN(MSIOF2_RXD), GPIO_FN(MSIOF2_TXD), - /* MSIOF3 */ + /* BBIF1 */ GPIO_FN(BBIF1_RXD), GPIO_FN(BBIF1_TSYNC), GPIO_FN(BBIF1_TSCK), GPIO_FN(BBIF1_TXD), GPIO_FN(BBIF1_RSCK), GPIO_FN(BBIF1_RSYNC), GPIO_FN(BBIF1_FLOW), GPIO_FN(BB_RX_FLOW_N), - /* MSIOF4 */ + /* BBIF2 */ GPIO_FN(BBIF2_TSCK1), GPIO_FN(BBIF2_TSYNC1), GPIO_FN(BBIF2_TXD1), GPIO_FN(BBIF2_RXD), -- cgit v1.1 From 7923ac133b5dcdbb0cfff245d8045f1ff9694cba Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Fri, 3 Sep 2010 05:36:43 +0000 Subject: ARM: mach-shmobile: sh7372: modify INTCS table Add ignored device name by comment-out in INTCS. And MSIOF which has been forgotten is added Signed-off-by: Kuninori Morimoto Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/intc-sh7372.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c index e3551b5..4cd3cae 100644 --- a/arch/arm/mach-shmobile/intc-sh7372.c +++ b/arch/arm/mach-shmobile/intc-sh7372.c @@ -369,9 +369,13 @@ enum { INTCS, /* interrupt sources INTCS */ + + /* IRQ0S - IRQ31S */ VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3, RTDMAC_1_DEI0, RTDMAC_1_DEI1, RTDMAC_1_DEI2, RTDMAC_1_DEI3, CEU, BEU_BEU0, BEU_BEU1, BEU_BEU2, + /* MFI */ + /* BBIF2 */ VPU, TSIF1, _3DG_SGX530, @@ -379,13 +383,17 @@ enum { IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2, IPMMU_IPMMUR, IPMMU_IPMMUR2, RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR, + /* KEYSC */ + /* TTI20 */ MSIOF, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0, TMU_TUNI0, TMU_TUNI1, TMU_TUNI2, CMT0, TSIF0, + /* CMT2 */ LMB, CTI, + /* RWDT0 */ ICB, JPU_JPEG, LCDC, @@ -397,11 +405,17 @@ enum { CSIRX, DSITX_DSITX0, DSITX_DSITX1, + /* SPU2 */ + /* FSI */ + /* FMSI */ + /* HDMI */ TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, CMT4, DSITX1_DSITX1_0, DSITX1_DSITX1_1, + /* MFIS2 */ CPORTS2R, + /* CEC */ JPU6E, /* interrupt groups INTCS */ @@ -410,12 +424,15 @@ enum { }; static struct intc_vect intcs_vectors[] = { + /* IRQ0S - IRQ31S */ INTCS_VECT(VEU_VEU0, 0x700), INTCS_VECT(VEU_VEU1, 0x720), INTCS_VECT(VEU_VEU2, 0x740), INTCS_VECT(VEU_VEU3, 0x760), INTCS_VECT(RTDMAC_1_DEI0, 0x800), INTCS_VECT(RTDMAC_1_DEI1, 0x820), INTCS_VECT(RTDMAC_1_DEI2, 0x840), INTCS_VECT(RTDMAC_1_DEI3, 0x860), INTCS_VECT(CEU, 0x880), INTCS_VECT(BEU_BEU0, 0x8a0), INTCS_VECT(BEU_BEU1, 0x8c0), INTCS_VECT(BEU_BEU2, 0x8e0), + /* MFI */ + /* BBIF2 */ INTCS_VECT(VPU, 0x980), INTCS_VECT(TSIF1, 0x9a0), INTCS_VECT(_3DG_SGX530, 0x9e0), @@ -425,14 +442,19 @@ static struct intc_vect intcs_vectors[] = { INTCS_VECT(IPMMU_IPMMUR, 0xb00), INTCS_VECT(IPMMU_IPMMUR2, 0xb20), INTCS_VECT(RTDMAC_2_DEI4, 0xb80), INTCS_VECT(RTDMAC_2_DEI5, 0xba0), INTCS_VECT(RTDMAC_2_DADERR, 0xbc0), + /* KEYSC */ + /* TTI20 */ + INTCS_VECT(MSIOF, 0x0d20), INTCS_VECT(IIC0_ALI0, 0xe00), INTCS_VECT(IIC0_TACKI0, 0xe20), INTCS_VECT(IIC0_WAITI0, 0xe40), INTCS_VECT(IIC0_DTEI0, 0xe60), INTCS_VECT(TMU_TUNI0, 0xe80), INTCS_VECT(TMU_TUNI1, 0xea0), INTCS_VECT(TMU_TUNI2, 0xec0), INTCS_VECT(CMT0, 0xf00), INTCS_VECT(TSIF0, 0xf20), + /* CMT2 */ INTCS_VECT(LMB, 0xf60), INTCS_VECT(CTI, 0x400), + /* RWDT0 */ INTCS_VECT(ICB, 0x480), INTCS_VECT(JPU_JPEG, 0x560), INTCS_VECT(LCDC, 0x580), @@ -446,12 +468,18 @@ static struct intc_vect intcs_vectors[] = { INTCS_VECT(CSIRX, 0x17a0), INTCS_VECT(DSITX_DSITX0, 0x17c0), INTCS_VECT(DSITX_DSITX1, 0x17e0), + /* SPU2 */ + /* FSI */ + /* FMSI */ + /* HDMI */ INTCS_VECT(TMU1_TUNI0, 0x1900), INTCS_VECT(TMU1_TUNI1, 0x1920), INTCS_VECT(TMU1_TUNI2, 0x1940), INTCS_VECT(CMT4, 0x1980), INTCS_VECT(DSITX1_DSITX1_0, 0x19a0), INTCS_VECT(DSITX1_DSITX1_1, 0x19c0), + /* MFIS2 */ INTCS_VECT(CPORTS2R, 0x1a20), + /* CEC */ INTCS_VECT(JPU6E, 0x1a80), INTC_VECT(INTCS, 0xf80), -- cgit v1.1 From 44432407d9f5e4b2e56c7eccb65d98cad4bba191 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Fri, 3 Sep 2010 07:20:04 +0000 Subject: fbdev: sh_mobile_lcdcfb: Support multiple video modes in platform data This is a preparation for HDMI hotplug support. This patch just moves all platform defined video modes for the sh_mobile_lcdcfb driver to separate arrays and switches all users to use element 0 of that array, so, this patch doesn't introduce any functional changes and as such should not cause any regressions. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/board-ap4evb.c | 98 ++++++++++++++++++++--------------- arch/sh/boards/mach-ap325rxa/setup.c | 29 ++++++----- arch/sh/boards/mach-ecovec24/setup.c | 60 ++++++++++++--------- arch/sh/boards/mach-kfr2r09/setup.c | 29 ++++++----- arch/sh/boards/mach-migor/setup.c | 58 +++++++++++---------- arch/sh/boards/mach-se/7724/setup.c | 54 ++++++++++++------- 6 files changed, 192 insertions(+), 136 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c index 31e5b28..4e883e0 100644 --- a/arch/arm/mach-shmobile/board-ap4evb.c +++ b/arch/arm/mach-shmobile/board-ap4evb.c @@ -375,10 +375,40 @@ static struct platform_device usb1_host_device = { .resource = usb1_host_resources, }; +const static struct fb_videomode ap4evb_lcdc_modes[] = { + { +#ifdef CONFIG_AP4EVB_QHD + .name = "R63302(QHD)", + .xres = 544, + .yres = 961, + .left_margin = 72, + .right_margin = 600, + .hsync_len = 16, + .upper_margin = 8, + .lower_margin = 8, + .vsync_len = 2, + .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT, +#else + .name = "WVGA Panel", + .xres = 800, + .yres = 480, + .left_margin = 220, + .right_margin = 110, + .hsync_len = 70, + .upper_margin = 20, + .lower_margin = 5, + .vsync_len = 5, + .sync = 0, +#endif + }, +}; + static struct sh_mobile_lcdc_info lcdc_info = { .ch[0] = { .chan = LCDC_CHAN_MAINLCD, .bpp = 16, + .lcd_cfg = ap4evb_lcdc_modes, + .num_cfg = ARRAY_SIZE(ap4evb_lcdc_modes), } }; @@ -569,6 +599,31 @@ static struct platform_device fsi_device = { }, }; +const static struct fb_videomode ap4evb_hdmi_modes[] = { + { + .name = "HDMI 720p", + .xres = 1280, + .yres = 720, + + /* + * If left and right margins are not multiples of 8, + * LDHAJR will be adjusted accordingly by the LCDC + * driver. Until we start using EDID, these values + * might have to be adjusted for different monitors. + */ + .left_margin = 200, + .right_margin = 88, + .hsync_len = 48, + + .upper_margin = 20, + .lower_margin = 5, + .vsync_len = 5, + + .pixclock = 13468, + .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT, + }, +}; + static struct sh_mobile_lcdc_info sh_mobile_lcdc1_info = { .clock_source = LCDC_CLK_EXTERNAL, .ch[0] = { @@ -577,26 +632,8 @@ static struct sh_mobile_lcdc_info sh_mobile_lcdc1_info = { .interface_type = RGB24, .clock_divider = 1, .flags = LCDC_FLAGS_DWPOL, - .lcd_cfg = { - .name = "HDMI", - /* So far only 720p is supported */ - .xres = 1280, - .yres = 720, - /* - * If left and right margins are not multiples of 8, - * LDHAJR will be adjusted accordingly by the LCDC - * driver. Until we start using EDID, these values - * might have to be adjusted for different monitors. - */ - .left_margin = 200, - .right_margin = 88, - .hsync_len = 48, - .upper_margin = 20, - .lower_margin = 5, - .vsync_len = 5, - .pixclock = 13468, - .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT, - }, + .lcd_cfg = ap4evb_hdmi_modes, + .num_cfg = ARRAY_SIZE(ap4evb_hdmi_modes), } }; @@ -960,17 +997,6 @@ static void __init ap4evb_init(void) lcdc_info.ch[0].interface_type = RGB24; lcdc_info.ch[0].clock_divider = 1; lcdc_info.ch[0].flags = LCDC_FLAGS_DWPOL; - lcdc_info.ch[0].lcd_cfg.name = "R63302(QHD)"; - lcdc_info.ch[0].lcd_cfg.xres = 544; - lcdc_info.ch[0].lcd_cfg.yres = 961; - lcdc_info.ch[0].lcd_cfg.left_margin = 72; - lcdc_info.ch[0].lcd_cfg.right_margin = 600; - lcdc_info.ch[0].lcd_cfg.hsync_len = 16; - lcdc_info.ch[0].lcd_cfg.upper_margin = 8; - lcdc_info.ch[0].lcd_cfg.lower_margin = 8; - lcdc_info.ch[0].lcd_cfg.vsync_len = 2; - lcdc_info.ch[0].lcd_cfg.sync = FB_SYNC_VERT_HIGH_ACT | - FB_SYNC_HOR_HIGH_ACT; lcdc_info.ch[0].lcd_size_cfg.width = 44; lcdc_info.ch[0].lcd_size_cfg.height = 79; @@ -1013,16 +1039,6 @@ static void __init ap4evb_init(void) lcdc_info.ch[0].interface_type = RGB18; lcdc_info.ch[0].clock_divider = 2; lcdc_info.ch[0].flags = 0; - lcdc_info.ch[0].lcd_cfg.name = "WVGA Panel"; - lcdc_info.ch[0].lcd_cfg.xres = 800; - lcdc_info.ch[0].lcd_cfg.yres = 480; - lcdc_info.ch[0].lcd_cfg.left_margin = 220; - lcdc_info.ch[0].lcd_cfg.right_margin = 110; - lcdc_info.ch[0].lcd_cfg.hsync_len = 70; - lcdc_info.ch[0].lcd_cfg.upper_margin = 20; - lcdc_info.ch[0].lcd_cfg.lower_margin = 5; - lcdc_info.ch[0].lcd_cfg.vsync_len = 5; - lcdc_info.ch[0].lcd_cfg.sync = 0; lcdc_info.ch[0].lcd_size_cfg.width = 152; lcdc_info.ch[0].lcd_size_cfg.height = 91; diff --git a/arch/sh/boards/mach-ap325rxa/setup.c b/arch/sh/boards/mach-ap325rxa/setup.c index 3da116f4..0055323 100644 --- a/arch/sh/boards/mach-ap325rxa/setup.c +++ b/arch/sh/boards/mach-ap325rxa/setup.c @@ -176,6 +176,21 @@ static void ap320_wvga_power_off(void *board_data) __raw_writew(0, FPGA_LCDREG); } +const static struct fb_videomode ap325rxa_lcdc_modes[] = { + { + .name = "LB070WV1", + .xres = 800, + .yres = 480, + .left_margin = 32, + .right_margin = 160, + .hsync_len = 8, + .upper_margin = 63, + .lower_margin = 80, + .vsync_len = 1, + .sync = 0, /* hsync and vsync are active low */ + }, +}; + static struct sh_mobile_lcdc_info lcdc_info = { .clock_source = LCDC_CLK_EXTERNAL, .ch[0] = { @@ -183,18 +198,8 @@ static struct sh_mobile_lcdc_info lcdc_info = { .bpp = 16, .interface_type = RGB18, .clock_divider = 1, - .lcd_cfg = { - .name = "LB070WV1", - .xres = 800, - .yres = 480, - .left_margin = 32, - .right_margin = 160, - .hsync_len = 8, - .upper_margin = 63, - .lower_margin = 80, - .vsync_len = 1, - .sync = 0, /* hsync and vsync are active low */ - }, + .lcd_cfg = ap325rxa_lcdc_modes, + .num_cfg = ARRAY_SIZE(ap325rxa_lcdc_modes), .lcd_size_cfg = { /* 7.0 inch */ .width = 152, .height = 91, diff --git a/arch/sh/boards/mach-ecovec24/setup.c b/arch/sh/boards/mach-ecovec24/setup.c index 1d7b495..feadf5d 100644 --- a/arch/sh/boards/mach-ecovec24/setup.c +++ b/arch/sh/boards/mach-ecovec24/setup.c @@ -231,14 +231,41 @@ static struct platform_device usb1_common_device = { }; /* LCDC */ +const static struct fb_videomode ecovec_lcd_modes[] = { + { + .name = "Panel", + .xres = 800, + .yres = 480, + .left_margin = 220, + .right_margin = 110, + .hsync_len = 70, + .upper_margin = 20, + .lower_margin = 5, + .vsync_len = 5, + .sync = 0, /* hsync and vsync are active low */ + }, +}; + +const static struct fb_videomode ecovec_dvi_modes[] = { + { + .name = "DVI", + .xres = 1280, + .yres = 720, + .left_margin = 220, + .right_margin = 110, + .hsync_len = 40, + .upper_margin = 20, + .lower_margin = 5, + .vsync_len = 5, + .sync = 0, /* hsync and vsync are active low */ + }, +}; + static struct sh_mobile_lcdc_info lcdc_info = { .ch[0] = { .interface_type = RGB18, .chan = LCDC_CHAN_MAINLCD, .bpp = 16, - .lcd_cfg = { - .sync = 0, /* hsync and vsync are active low */ - }, .lcd_size_cfg = { /* 7.0 inch */ .width = 152, .height = 91, @@ -1079,33 +1106,18 @@ static int __init arch_setup(void) if (gpio_get_value(GPIO_PTE6)) { /* DVI */ lcdc_info.clock_source = LCDC_CLK_EXTERNAL; - lcdc_info.ch[0].clock_divider = 1, - lcdc_info.ch[0].lcd_cfg.name = "DVI"; - lcdc_info.ch[0].lcd_cfg.xres = 1280; - lcdc_info.ch[0].lcd_cfg.yres = 720; - lcdc_info.ch[0].lcd_cfg.left_margin = 220; - lcdc_info.ch[0].lcd_cfg.right_margin = 110; - lcdc_info.ch[0].lcd_cfg.hsync_len = 40; - lcdc_info.ch[0].lcd_cfg.upper_margin = 20; - lcdc_info.ch[0].lcd_cfg.lower_margin = 5; - lcdc_info.ch[0].lcd_cfg.vsync_len = 5; + lcdc_info.ch[0].clock_divider = 1; + lcdc_info.ch[0].lcd_cfg = ecovec_dvi_modes; + lcdc_info.ch[0].num_cfg = ARRAY_SIZE(ecovec_dvi_modes); gpio_set_value(GPIO_PTA2, 1); gpio_set_value(GPIO_PTU1, 1); } else { /* Panel */ - lcdc_info.clock_source = LCDC_CLK_PERIPHERAL; - lcdc_info.ch[0].clock_divider = 2, - lcdc_info.ch[0].lcd_cfg.name = "Panel"; - lcdc_info.ch[0].lcd_cfg.xres = 800; - lcdc_info.ch[0].lcd_cfg.yres = 480; - lcdc_info.ch[0].lcd_cfg.left_margin = 220; - lcdc_info.ch[0].lcd_cfg.right_margin = 110; - lcdc_info.ch[0].lcd_cfg.hsync_len = 70; - lcdc_info.ch[0].lcd_cfg.upper_margin = 20; - lcdc_info.ch[0].lcd_cfg.lower_margin = 5; - lcdc_info.ch[0].lcd_cfg.vsync_len = 5; + lcdc_info.ch[0].clock_divider = 2; + lcdc_info.ch[0].lcd_cfg = ecovec_lcd_modes; + lcdc_info.ch[0].num_cfg = ARRAY_SIZE(ecovec_lcd_modes); gpio_set_value(GPIO_PTR1, 1); diff --git a/arch/sh/boards/mach-kfr2r09/setup.c b/arch/sh/boards/mach-kfr2r09/setup.c index 68994a1..87d4b90 100644 --- a/arch/sh/boards/mach-kfr2r09/setup.c +++ b/arch/sh/boards/mach-kfr2r09/setup.c @@ -126,6 +126,21 @@ static struct platform_device kfr2r09_sh_keysc_device = { }, }; +const static struct fb_videomode kfr2r09_lcdc_modes[] = { + { + .name = "TX07D34VM0AAA", + .xres = 240, + .yres = 400, + .left_margin = 0, + .right_margin = 16, + .hsync_len = 8, + .upper_margin = 0, + .lower_margin = 1, + .vsync_len = 1, + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + }, +}; + static struct sh_mobile_lcdc_info kfr2r09_sh_lcdc_info = { .clock_source = LCDC_CLK_BUS, .ch[0] = { @@ -134,18 +149,8 @@ static struct sh_mobile_lcdc_info kfr2r09_sh_lcdc_info = { .interface_type = SYS18, .clock_divider = 6, .flags = LCDC_FLAGS_DWPOL, - .lcd_cfg = { - .name = "TX07D34VM0AAA", - .xres = 240, - .yres = 400, - .left_margin = 0, - .right_margin = 16, - .hsync_len = 8, - .upper_margin = 0, - .lower_margin = 1, - .vsync_len = 1, - .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, - }, + .lcd_cfg = kfr2r09_lcdc_modes, + .num_cfg = ARRAY_SIZE(kfr2r09_lcdc_modes), .lcd_size_cfg = { .width = 35, .height = 58, diff --git a/arch/sh/boards/mach-migor/setup.c b/arch/sh/boards/mach-migor/setup.c index 662debe..9204cbb 100644 --- a/arch/sh/boards/mach-migor/setup.c +++ b/arch/sh/boards/mach-migor/setup.c @@ -213,51 +213,55 @@ static struct platform_device migor_nand_flash_device = { } }; +const static struct fb_videomode migor_lcd_modes[] = { + { +#if defined(CONFIG_SH_MIGOR_RTA_WVGA) + .name = "LB070WV1", + .xres = 800, + .yres = 480, + .left_margin = 64, + .right_margin = 16, + .hsync_len = 120, + .sync = 0, +#elif defined(CONFIG_SH_MIGOR_QVGA) + .name = "PH240320T", + .xres = 320, + .yres = 240, + .left_margin = 0, + .right_margin = 16, + .hsync_len = 8, + .sync = FB_SYNC_HOR_HIGH_ACT, +#endif + .upper_margin = 1, + .lower_margin = 17, + .vsync_len = 2, + }, +}; + static struct sh_mobile_lcdc_info sh_mobile_lcdc_info = { -#ifdef CONFIG_SH_MIGOR_RTA_WVGA +#if defined(CONFIG_SH_MIGOR_RTA_WVGA) .clock_source = LCDC_CLK_BUS, .ch[0] = { .chan = LCDC_CHAN_MAINLCD, .bpp = 16, .interface_type = RGB16, .clock_divider = 2, - .lcd_cfg = { - .name = "LB070WV1", - .xres = 800, - .yres = 480, - .left_margin = 64, - .right_margin = 16, - .hsync_len = 120, - .upper_margin = 1, - .lower_margin = 17, - .vsync_len = 2, - .sync = 0, - }, + .lcd_cfg = migor_lcd_modes, + .num_cfg = ARRAY_SIZE(migor_lcd_modes), .lcd_size_cfg = { /* 7.0 inch */ .width = 152, .height = 91, }, } -#endif -#ifdef CONFIG_SH_MIGOR_QVGA +#elif defined(CONFIG_SH_MIGOR_QVGA) .clock_source = LCDC_CLK_PERIPHERAL, .ch[0] = { .chan = LCDC_CHAN_MAINLCD, .bpp = 16, .interface_type = SYS16A, .clock_divider = 10, - .lcd_cfg = { - .name = "PH240320T", - .xres = 320, - .yres = 240, - .left_margin = 0, - .right_margin = 16, - .hsync_len = 8, - .upper_margin = 1, - .lower_margin = 17, - .vsync_len = 2, - .sync = FB_SYNC_HOR_HIGH_ACT, - }, + .lcd_cfg = migor_lcd_modes, + .num_cfg = ARRAY_SIZE(migor_lcd_modes), .lcd_size_cfg = { /* 2.4 inch */ .width = 49, .height = 37, diff --git a/arch/sh/boards/mach-se/7724/setup.c b/arch/sh/boards/mach-se/7724/setup.c index 552ebd9..3099c36 100644 --- a/arch/sh/boards/mach-se/7724/setup.c +++ b/arch/sh/boards/mach-se/7724/setup.c @@ -144,16 +144,42 @@ static struct platform_device nor_flash_device = { }; /* LCDC */ +const static struct fb_videomode lcdc_720p_modes[] = { + { + .name = "LB070WV1", + .sync = 0, /* hsync and vsync are active low */ + .xres = 1280; + .yres = 720; + .left_margin = 220; + .right_margin = 110; + .hsync_len = 40; + .upper_margin = 20; + .lower_margin = 5; + .vsync_len = 5; + }, +}; + +const static struct fb_videomode lcdc_vga_modes[] = { + { + .name = "LB070WV1", + .sync = 0, /* hsync and vsync are active low */ + .xres = 640; + .yres = 480; + .left_margin = 105; + .right_margin = 50; + .hsync_len = 96; + .upper_margin = 33; + .lower_margin = 10; + .vsync_len = 2; + }, +}; + static struct sh_mobile_lcdc_info lcdc_info = { .clock_source = LCDC_CLK_EXTERNAL, .ch[0] = { .chan = LCDC_CHAN_MAINLCD, .bpp = 16, .clock_divider = 1, - .lcd_cfg = { - .name = "LB070WV1", - .sync = 0, /* hsync and vsync are active low */ - }, .lcd_size_cfg = { /* 7.0 inch */ .width = 152, .height = 91, @@ -909,24 +935,12 @@ static int __init devices_setup(void) if (sw & SW41_B) { /* 720p */ - lcdc_info.ch[0].lcd_cfg.xres = 1280; - lcdc_info.ch[0].lcd_cfg.yres = 720; - lcdc_info.ch[0].lcd_cfg.left_margin = 220; - lcdc_info.ch[0].lcd_cfg.right_margin = 110; - lcdc_info.ch[0].lcd_cfg.hsync_len = 40; - lcdc_info.ch[0].lcd_cfg.upper_margin = 20; - lcdc_info.ch[0].lcd_cfg.lower_margin = 5; - lcdc_info.ch[0].lcd_cfg.vsync_len = 5; + lcdc_info.ch[0].lcd_cfg = lcdc_720p_modes; + lcdc_info.ch[0].num_cfg = ARRAY_SIZE(lcdc_720p_modes); } else { /* VGA */ - lcdc_info.ch[0].lcd_cfg.xres = 640; - lcdc_info.ch[0].lcd_cfg.yres = 480; - lcdc_info.ch[0].lcd_cfg.left_margin = 105; - lcdc_info.ch[0].lcd_cfg.right_margin = 50; - lcdc_info.ch[0].lcd_cfg.hsync_len = 96; - lcdc_info.ch[0].lcd_cfg.upper_margin = 33; - lcdc_info.ch[0].lcd_cfg.lower_margin = 10; - lcdc_info.ch[0].lcd_cfg.vsync_len = 2; + lcdc_info.ch[0].lcd_cfg = lcdc_vga_modes; + lcdc_info.ch[0].num_cfg = ARRAY_SIZE(lcdc_vga_modes); } if (sw & SW41_A) { -- cgit v1.1 From a91a2d06c9797c0a533a71dbeea37b2d5a60c7f5 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Fri, 3 Sep 2010 07:20:42 +0000 Subject: ARM: mach-shmobile: add two more video modes for HDMI Add video modes for 480p and SXGA (1280x1024). Signed-off-by: Guennadi Liakhovetski Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/board-ap4evb.c | 41 ++++++++++++++++++++++++++++++----- 1 file changed, 35 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c index 4e883e0..0053379 100644 --- a/arch/arm/mach-shmobile/board-ap4evb.c +++ b/arch/arm/mach-shmobile/board-ap4evb.c @@ -599,18 +599,18 @@ static struct platform_device fsi_device = { }, }; +/* + * If left and right margins are not multiples of 8, + * LDHAJR will be adjusted accordingly by the LCDC + * driver. Until we start using EDID, these values + * might have to be adjusted for different monitors. + */ const static struct fb_videomode ap4evb_hdmi_modes[] = { { .name = "HDMI 720p", .xres = 1280, .yres = 720, - /* - * If left and right margins are not multiples of 8, - * LDHAJR will be adjusted accordingly by the LCDC - * driver. Until we start using EDID, these values - * might have to be adjusted for different monitors. - */ .left_margin = 200, .right_margin = 88, .hsync_len = 48, @@ -621,6 +621,35 @@ const static struct fb_videomode ap4evb_hdmi_modes[] = { .pixclock = 13468, .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT, + }, { + .name = "1280x1024", + .xres = 1280, + .yres = 1024, + + .left_margin = 144, + .right_margin = 48, + .hsync_len = 64, + + .upper_margin = 35, + .lower_margin = 5, + .vsync_len = 3, + + .pixclock = 9800, + .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT, + }, { + .name = "HDMI 480p", + .xres = 720, + .yres = 480, + + .left_margin = 36, + .right_margin = 18, + .hsync_len = 68, + + .upper_margin = 36, + .lower_margin = 3, + .vsync_len = 6, + .pixclock = 37037, + .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT, }, }; -- cgit v1.1 From 52d5ac0073eb5faf284574bd98a25a65053eaae0 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Tue, 14 Sep 2010 17:28:55 +0900 Subject: ARM: mach-shmobile: ap4evb: modify touchpanel judgment condition Current touchpanel had below 2 issues - LCDD2 pin which is needed for WVGA was changed to IRQ28_123 pin on ts_get_pendown_state - GPIO pull up on ts_init was disabled by gpio_request on ts_get_pendown_state. This mean the return value from gpio_get_value is untrusted. This patch solve these issues Signed-off-by: Kuninori Morimoto Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/board-ap4evb.c | 38 ++++++++++++++++++++++++++++++++--- 1 file changed, 35 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c index 0053379..3dd76f0 100644 --- a/arch/arm/mach-shmobile/board-ap4evb.c +++ b/arch/arm/mach-shmobile/board-ap4evb.c @@ -834,11 +834,45 @@ static void __init gpio_no_direction(u32 addr) } /* TouchScreen */ +#ifdef CONFIG_AP4EVB_QHD +# define GPIO_TSC_IRQ GPIO_FN_IRQ28_123 +# define GPIO_TSC_PORT GPIO_PORT123 +#else /* WVGA */ +# define GPIO_TSC_IRQ GPIO_FN_IRQ7_40 +# define GPIO_TSC_PORT GPIO_PORT40 +#endif + #define IRQ28 evt2irq(0x3380) /* IRQ28A */ #define IRQ7 evt2irq(0x02e0) /* IRQ7A */ +static int ts_get_pendown_state(void) +{ + int val; + + gpio_free(GPIO_TSC_IRQ); + + gpio_request(GPIO_TSC_PORT, NULL); + + gpio_direction_input(GPIO_TSC_PORT); + + val = gpio_get_value(GPIO_TSC_PORT); + + gpio_request(GPIO_TSC_IRQ, NULL); + + return !val; +} + +static int ts_init(void) +{ + gpio_request(GPIO_TSC_IRQ, NULL); + + return 0; +} + static struct tsc2007_platform_data tsc2007_info = { .model = 2007, - .x_plate_ohms = 1000, + .x_plate_ohms = 180, + .get_pendown_state = ts_get_pendown_state, + .init_platform_hw = ts_init, }; static struct i2c_board_info tsc_device = { @@ -1015,7 +1049,6 @@ static void __init ap4evb_init(void) gpio_request(GPIO_FN_KEYIN4, NULL); /* enable TouchScreen */ - gpio_request(GPIO_FN_IRQ28_123, NULL); set_irq_type(IRQ28, IRQ_TYPE_LEVEL_LOW); tsc_device.irq = IRQ28; @@ -1072,7 +1105,6 @@ static void __init ap4evb_init(void) lcdc_info.ch[0].lcd_size_cfg.height = 91; /* enable TouchScreen */ - gpio_request(GPIO_FN_IRQ7_40, NULL); set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW); tsc_device.irq = IRQ7; -- cgit v1.1 From 248bc0d93bde744751a05d322d85269323d3af0c Mon Sep 17 00:00:00 2001 From: Matt Fleming Date: Sat, 21 Aug 2010 14:49:38 +0000 Subject: sh: Set CONFIG_SYSFS_DEPRECATED_V2=n As the help for the config option suggests, this option really shouldn't be set by default for any recent distribution as it changes the layout of sysfs. I spotted this while running debian when udev got very confused by the sysfs layout and failed to create some device nodes. Signed-off-by: Matt Fleming Signed-off-by: Paul Mundt --- arch/sh/configs/ap325rxa_defconfig | 1 - arch/sh/configs/cayman_defconfig | 1 - arch/sh/configs/dreamcast_defconfig | 1 - arch/sh/configs/ecovec24-romimage_defconfig | 1 - arch/sh/configs/edosk7760_defconfig | 1 - arch/sh/configs/espt_defconfig | 1 - arch/sh/configs/hp6xx_defconfig | 1 - arch/sh/configs/kfr2r09-romimage_defconfig | 1 - arch/sh/configs/kfr2r09_defconfig | 1 - arch/sh/configs/landisk_defconfig | 1 - arch/sh/configs/lboxre2_defconfig | 1 - arch/sh/configs/magicpanelr2_defconfig | 1 - arch/sh/configs/microdev_defconfig | 1 - arch/sh/configs/migor_defconfig | 1 - arch/sh/configs/polaris_defconfig | 1 - arch/sh/configs/r7780mp_defconfig | 1 - arch/sh/configs/r7785rp_defconfig | 1 - arch/sh/configs/rts7751r2d1_defconfig | 1 - arch/sh/configs/rts7751r2dplus_defconfig | 1 - arch/sh/configs/sdk7780_defconfig | 1 - arch/sh/configs/se7343_defconfig | 1 - arch/sh/configs/se7712_defconfig | 1 - arch/sh/configs/se7721_defconfig | 1 - arch/sh/configs/se7722_defconfig | 1 - arch/sh/configs/se7724_defconfig | 1 - arch/sh/configs/se7750_defconfig | 1 - arch/sh/configs/se7751_defconfig | 1 - arch/sh/configs/se7780_defconfig | 1 - arch/sh/configs/sh03_defconfig | 1 - arch/sh/configs/sh2007_defconfig | 1 - arch/sh/configs/sh7710voipgw_defconfig | 1 - arch/sh/configs/sh7763rdp_defconfig | 1 - arch/sh/configs/sh7785lcr_defconfig | 1 - arch/sh/configs/shx3_defconfig | 1 - arch/sh/configs/snapgear_defconfig | 1 - arch/sh/configs/systemh_defconfig | 1 - arch/sh/configs/titan_defconfig | 1 - arch/sh/configs/ul2_defconfig | 1 - 38 files changed, 38 deletions(-) (limited to 'arch') diff --git a/arch/sh/configs/ap325rxa_defconfig b/arch/sh/configs/ap325rxa_defconfig index 238d683..e533512 100644 --- a/arch/sh/configs/ap325rxa_defconfig +++ b/arch/sh/configs/ap325rxa_defconfig @@ -3,7 +3,6 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_KALLSYMS is not set CONFIG_SLAB=y CONFIG_MODULES=y diff --git a/arch/sh/configs/cayman_defconfig b/arch/sh/configs/cayman_defconfig index b3bf11b..67e1506 100644 --- a/arch/sh/configs/cayman_defconfig +++ b/arch/sh/configs/cayman_defconfig @@ -1,7 +1,6 @@ CONFIG_EXPERIMENTAL=y CONFIG_POSIX_MQUEUE=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_SLAB=y CONFIG_MODULES=y diff --git a/arch/sh/configs/dreamcast_defconfig b/arch/sh/configs/dreamcast_defconfig index 3cdee4f..ec243ca 100644 --- a/arch/sh/configs/dreamcast_defconfig +++ b/arch/sh/configs/dreamcast_defconfig @@ -2,7 +2,6 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_SYSCTL_SYSCALL is not set CONFIG_SLAB=y CONFIG_PROFILING=y diff --git a/arch/sh/configs/ecovec24-romimage_defconfig b/arch/sh/configs/ecovec24-romimage_defconfig index 021633b..5fcb17b 100644 --- a/arch/sh/configs/ecovec24-romimage_defconfig +++ b/arch/sh/configs/ecovec24-romimage_defconfig @@ -5,7 +5,6 @@ CONFIG_BSD_PROCESS_ACCT=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y # CONFIG_KALLSYMS is not set CONFIG_SLAB=y diff --git a/arch/sh/configs/edosk7760_defconfig b/arch/sh/configs/edosk7760_defconfig index 365f231..e1077a0 100644 --- a/arch/sh/configs/edosk7760_defconfig +++ b/arch/sh/configs/edosk7760_defconfig @@ -5,7 +5,6 @@ CONFIG_POSIX_MQUEUE=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y -CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y CONFIG_KALLSYMS_ALL=y CONFIG_MODULES=y diff --git a/arch/sh/configs/espt_defconfig b/arch/sh/configs/espt_defconfig index ca7fc1b..67cb109 100644 --- a/arch/sh/configs/espt_defconfig +++ b/arch/sh/configs/espt_defconfig @@ -3,7 +3,6 @@ CONFIG_SYSVIPC=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_NAMESPACES=y CONFIG_UTS_NS=y CONFIG_IPC_NS=y diff --git a/arch/sh/configs/hp6xx_defconfig b/arch/sh/configs/hp6xx_defconfig index 45c18a3..496edcd 100644 --- a/arch/sh/configs/hp6xx_defconfig +++ b/arch/sh/configs/hp6xx_defconfig @@ -3,7 +3,6 @@ CONFIG_BSD_PROCESS_ACCT=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set # CONFIG_SYSCTL_SYSCALL is not set CONFIG_SLAB=y diff --git a/arch/sh/configs/kfr2r09-romimage_defconfig b/arch/sh/configs/kfr2r09-romimage_defconfig index d4268b1..029a506 100644 --- a/arch/sh/configs/kfr2r09-romimage_defconfig +++ b/arch/sh/configs/kfr2r09-romimage_defconfig @@ -5,7 +5,6 @@ CONFIG_BSD_PROCESS_ACCT=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y # CONFIG_KALLSYMS is not set CONFIG_SLAB=y diff --git a/arch/sh/configs/kfr2r09_defconfig b/arch/sh/configs/kfr2r09_defconfig index ad5d296..fac13de 100644 --- a/arch/sh/configs/kfr2r09_defconfig +++ b/arch/sh/configs/kfr2r09_defconfig @@ -5,7 +5,6 @@ CONFIG_BSD_PROCESS_ACCT=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y # CONFIG_KALLSYMS is not set CONFIG_SLAB=y diff --git a/arch/sh/configs/landisk_defconfig b/arch/sh/configs/landisk_defconfig index 14e658e..3670e93 100644 --- a/arch/sh/configs/landisk_defconfig +++ b/arch/sh/configs/landisk_defconfig @@ -1,7 +1,6 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_SYSCTL_SYSCALL is not set CONFIG_KALLSYMS_EXTRA_PASS=y CONFIG_SLAB=y diff --git a/arch/sh/configs/lboxre2_defconfig b/arch/sh/configs/lboxre2_defconfig index 6be7eaa..e3c0894 100644 --- a/arch/sh/configs/lboxre2_defconfig +++ b/arch/sh/configs/lboxre2_defconfig @@ -1,7 +1,6 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_SYSCTL_SYSCALL is not set CONFIG_KALLSYMS_EXTRA_PASS=y CONFIG_SLAB=y diff --git a/arch/sh/configs/magicpanelr2_defconfig b/arch/sh/configs/magicpanelr2_defconfig index 4d61b77..9479872 100644 --- a/arch/sh/configs/magicpanelr2_defconfig +++ b/arch/sh/configs/magicpanelr2_defconfig @@ -5,7 +5,6 @@ CONFIG_POSIX_MQUEUE=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_BSD_PROCESS_ACCT_V3=y CONFIG_AUDIT=y -CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set diff --git a/arch/sh/configs/microdev_defconfig b/arch/sh/configs/microdev_defconfig index 0e32a24..f1d2e1b 100644 --- a/arch/sh/configs/microdev_defconfig +++ b/arch/sh/configs/microdev_defconfig @@ -1,7 +1,6 @@ CONFIG_EXPERIMENTAL=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set # CONFIG_SYSCTL_SYSCALL is not set diff --git a/arch/sh/configs/migor_defconfig b/arch/sh/configs/migor_defconfig index c19fcdf..9ad904a 100644 --- a/arch/sh/configs/migor_defconfig +++ b/arch/sh/configs/migor_defconfig @@ -3,7 +3,6 @@ CONFIG_SYSVIPC=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set # CONFIG_SYSCTL_SYSCALL is not set diff --git a/arch/sh/configs/polaris_defconfig b/arch/sh/configs/polaris_defconfig index 984e3fe..f3d5d9f 100644 --- a/arch/sh/configs/polaris_defconfig +++ b/arch/sh/configs/polaris_defconfig @@ -7,7 +7,6 @@ CONFIG_BSD_PROCESS_ACCT=y CONFIG_BSD_PROCESS_ACCT_V3=y CONFIG_AUDIT=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_SLAB=y CONFIG_MODULES=y diff --git a/arch/sh/configs/r7780mp_defconfig b/arch/sh/configs/r7780mp_defconfig index e8b5472..920b847 100644 --- a/arch/sh/configs/r7780mp_defconfig +++ b/arch/sh/configs/r7780mp_defconfig @@ -4,7 +4,6 @@ CONFIG_BSD_PROCESS_ACCT=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_FUTEX is not set # CONFIG_EPOLL is not set diff --git a/arch/sh/configs/r7785rp_defconfig b/arch/sh/configs/r7785rp_defconfig index fd88480..c77da6b 100644 --- a/arch/sh/configs/r7785rp_defconfig +++ b/arch/sh/configs/r7785rp_defconfig @@ -8,7 +8,6 @@ CONFIG_RCU_TRACE=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_SYSCTL_SYSCALL is not set CONFIG_SLAB=y CONFIG_PROFILING=y diff --git a/arch/sh/configs/rts7751r2d1_defconfig b/arch/sh/configs/rts7751r2d1_defconfig index a42f7c2..a3d0810 100644 --- a/arch/sh/configs/rts7751r2d1_defconfig +++ b/arch/sh/configs/rts7751r2d1_defconfig @@ -1,7 +1,6 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set # CONFIG_SYSCTL_SYSCALL is not set CONFIG_SLAB=y diff --git a/arch/sh/configs/rts7751r2dplus_defconfig b/arch/sh/configs/rts7751r2dplus_defconfig index 742aa61..b1a04f3 100644 --- a/arch/sh/configs/rts7751r2dplus_defconfig +++ b/arch/sh/configs/rts7751r2dplus_defconfig @@ -1,7 +1,6 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set # CONFIG_SYSCTL_SYSCALL is not set CONFIG_SLAB=y diff --git a/arch/sh/configs/sdk7780_defconfig b/arch/sh/configs/sdk7780_defconfig index aed394d..ae111584 100644 --- a/arch/sh/configs/sdk7780_defconfig +++ b/arch/sh/configs/sdk7780_defconfig @@ -6,7 +6,6 @@ CONFIG_BSD_PROCESS_ACCT=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=18 -CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_RELAY=y CONFIG_KALLSYMS_ALL=y CONFIG_MODULES=y diff --git a/arch/sh/configs/se7343_defconfig b/arch/sh/configs/se7343_defconfig index 7a7e138..be9c4741 100644 --- a/arch/sh/configs/se7343_defconfig +++ b/arch/sh/configs/se7343_defconfig @@ -3,7 +3,6 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_FUTEX is not set # CONFIG_EPOLL is not set diff --git a/arch/sh/configs/se7712_defconfig b/arch/sh/configs/se7712_defconfig index 3620a7f..1248635 100644 --- a/arch/sh/configs/se7712_defconfig +++ b/arch/sh/configs/se7712_defconfig @@ -5,7 +5,6 @@ CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_KALLSYMS_ALL=y # CONFIG_BUG is not set diff --git a/arch/sh/configs/se7721_defconfig b/arch/sh/configs/se7721_defconfig index fe22f59..c3ba6e8 100644 --- a/arch/sh/configs/se7721_defconfig +++ b/arch/sh/configs/se7721_defconfig @@ -5,7 +5,6 @@ CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_KALLSYMS_ALL=y # CONFIG_BUG is not set diff --git a/arch/sh/configs/se7722_defconfig b/arch/sh/configs/se7722_defconfig index b9b64c3..ae998c7 100644 --- a/arch/sh/configs/se7722_defconfig +++ b/arch/sh/configs/se7722_defconfig @@ -4,7 +4,6 @@ CONFIG_BSD_PROCESS_ACCT=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y CONFIG_PROFILING=y CONFIG_MODULES=y diff --git a/arch/sh/configs/se7724_defconfig b/arch/sh/configs/se7724_defconfig index 03e7367..ed35093 100644 --- a/arch/sh/configs/se7724_defconfig +++ b/arch/sh/configs/se7724_defconfig @@ -3,7 +3,6 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_KALLSYMS is not set CONFIG_SLAB=y CONFIG_MODULES=y diff --git a/arch/sh/configs/se7750_defconfig b/arch/sh/configs/se7750_defconfig index 1a686b6..912c985 100644 --- a/arch/sh/configs/se7750_defconfig +++ b/arch/sh/configs/se7750_defconfig @@ -5,7 +5,6 @@ CONFIG_BSD_PROCESS_ACCT=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_HOTPLUG is not set diff --git a/arch/sh/configs/se7751_defconfig b/arch/sh/configs/se7751_defconfig index 7e03451..75c92fc 100644 --- a/arch/sh/configs/se7751_defconfig +++ b/arch/sh/configs/se7751_defconfig @@ -2,7 +2,6 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set # CONFIG_SYSCTL_SYSCALL is not set diff --git a/arch/sh/configs/se7780_defconfig b/arch/sh/configs/se7780_defconfig index 4cfc4de..c8c5e7f 100644 --- a/arch/sh/configs/se7780_defconfig +++ b/arch/sh/configs/se7780_defconfig @@ -3,7 +3,6 @@ CONFIG_SYSVIPC=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_KALLSYMS is not set # CONFIG_HOTPLUG is not set # CONFIG_EPOLL is not set diff --git a/arch/sh/configs/sh03_defconfig b/arch/sh/configs/sh03_defconfig index b95dc76..2051821 100644 --- a/arch/sh/configs/sh03_defconfig +++ b/arch/sh/configs/sh03_defconfig @@ -3,7 +3,6 @@ CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y # CONFIG_SYSCTL_SYSCALL is not set CONFIG_SLAB=y diff --git a/arch/sh/configs/sh2007_defconfig b/arch/sh/configs/sh2007_defconfig index c492796..0d2f414 100644 --- a/arch/sh/configs/sh2007_defconfig +++ b/arch/sh/configs/sh2007_defconfig @@ -7,7 +7,6 @@ CONFIG_AUDIT=y CONFIG_AUDITSYSCALL=y CONFIG_IKCONFIG=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_KALLSYMS_ALL=y CONFIG_SLAB=y diff --git a/arch/sh/configs/sh7710voipgw_defconfig b/arch/sh/configs/sh7710voipgw_defconfig index b804641..f92ad17 100644 --- a/arch/sh/configs/sh7710voipgw_defconfig +++ b/arch/sh/configs/sh7710voipgw_defconfig @@ -3,7 +3,6 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_FUTEX is not set # CONFIG_EPOLL is not set diff --git a/arch/sh/configs/sh7763rdp_defconfig b/arch/sh/configs/sh7763rdp_defconfig index 3618767..4795364 100644 --- a/arch/sh/configs/sh7763rdp_defconfig +++ b/arch/sh/configs/sh7763rdp_defconfig @@ -3,7 +3,6 @@ CONFIG_SYSVIPC=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_NAMESPACES=y CONFIG_UTS_NS=y CONFIG_IPC_NS=y diff --git a/arch/sh/configs/sh7785lcr_defconfig b/arch/sh/configs/sh7785lcr_defconfig index ee6b81f..51561f5 100644 --- a/arch/sh/configs/sh7785lcr_defconfig +++ b/arch/sh/configs/sh7785lcr_defconfig @@ -4,7 +4,6 @@ CONFIG_BSD_PROCESS_ACCT=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_SLAB=y CONFIG_PROFILING=y CONFIG_MODULES=y diff --git a/arch/sh/configs/shx3_defconfig b/arch/sh/configs/shx3_defconfig index bb4f60c..3f92d37 100644 --- a/arch/sh/configs/shx3_defconfig +++ b/arch/sh/configs/shx3_defconfig @@ -15,7 +15,6 @@ CONFIG_CGROUP_DEVICE=y CONFIG_CGROUP_CPUACCT=y CONFIG_RESOURCE_COUNTERS=y CONFIG_CGROUP_MEM_RES_CTLR=y -CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_RELAY=y CONFIG_NAMESPACES=y CONFIG_UTS_NS=y diff --git a/arch/sh/configs/snapgear_defconfig b/arch/sh/configs/snapgear_defconfig index f38c983..7eae4e5 100644 --- a/arch/sh/configs/snapgear_defconfig +++ b/arch/sh/configs/snapgear_defconfig @@ -1,7 +1,6 @@ CONFIG_EXPERIMENTAL=y # CONFIG_SWAP is not set CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y # CONFIG_SYSCTL_SYSCALL is not set # CONFIG_HOTPLUG is not set diff --git a/arch/sh/configs/systemh_defconfig b/arch/sh/configs/systemh_defconfig index 7007d00c6..b58dfc50 100644 --- a/arch/sh/configs/systemh_defconfig +++ b/arch/sh/configs/systemh_defconfig @@ -1,6 +1,5 @@ CONFIG_EXPERIMENTAL=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set # CONFIG_SYSCTL_SYSCALL is not set diff --git a/arch/sh/configs/titan_defconfig b/arch/sh/configs/titan_defconfig index 45c309f..0f55891 100644 --- a/arch/sh/configs/titan_defconfig +++ b/arch/sh/configs/titan_defconfig @@ -5,7 +5,6 @@ CONFIG_POSIX_MQUEUE=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=16 -CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set # CONFIG_SYSCTL_SYSCALL is not set diff --git a/arch/sh/configs/ul2_defconfig b/arch/sh/configs/ul2_defconfig index e107d42..2d288b8 100644 --- a/arch/sh/configs/ul2_defconfig +++ b/arch/sh/configs/ul2_defconfig @@ -4,7 +4,6 @@ CONFIG_BSD_PROCESS_ACCT=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y CONFIG_PROFILING=y CONFIG_MODULES=y -- cgit v1.1 From e0009b0a44f28227571d8cddebc5ccdae86027a6 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Fri, 27 Aug 2010 09:49:30 +0000 Subject: sh: ecovec24: modify tsc2007 platform settings This patch modify x_plate_ohms to correct value for tsc2007 panel, and removed un-necessary ts_get_pendown_state() Signed-off-by: Kuninori Morimoto Signed-off-by: Paul Mundt --- arch/sh/boards/mach-ecovec24/setup.c | 26 ++------------------------ 1 file changed, 2 insertions(+), 24 deletions(-) (limited to 'arch') diff --git a/arch/sh/boards/mach-ecovec24/setup.c b/arch/sh/boards/mach-ecovec24/setup.c index 1d7b495..db7a7c0 100644 --- a/arch/sh/boards/mach-ecovec24/setup.c +++ b/arch/sh/boards/mach-ecovec24/setup.c @@ -400,32 +400,9 @@ static struct platform_device keysc_device = { /* TouchScreen */ #define IRQ0 32 -static int ts_get_pendown_state(void) -{ - int val = 0; - gpio_free(GPIO_FN_INTC_IRQ0); - gpio_request(GPIO_PTZ0, NULL); - gpio_direction_input(GPIO_PTZ0); - - val = gpio_get_value(GPIO_PTZ0); - - gpio_free(GPIO_PTZ0); - gpio_request(GPIO_FN_INTC_IRQ0, NULL); - - return val ? 0 : 1; -} - -static int ts_init(void) -{ - gpio_request(GPIO_FN_INTC_IRQ0, NULL); - return 0; -} - static struct tsc2007_platform_data tsc2007_info = { .model = 2007, - .x_plate_ohms = 180, - .get_pendown_state = ts_get_pendown_state, - .init_platform_hw = ts_init, + .x_plate_ohms = 1000, }; static struct i2c_board_info ts_i2c_clients = { @@ -1119,6 +1096,7 @@ static int __init arch_setup(void) gpio_direction_output(GPIO_PTF4, 1); /* enable TouchScreen */ + gpio_request(GPIO_FN_INTC_IRQ0, NULL); i2c_register_board_info(0, &ts_i2c_clients, 1); set_irq_type(IRQ0, IRQ_TYPE_LEVEL_LOW); } -- cgit v1.1 From 459ebb34bd90f1ff12725a17289b7defbc6cd655 Mon Sep 17 00:00:00 2001 From: Carmelo AMOROSO Date: Wed, 1 Sep 2010 01:49:29 +0000 Subject: sh: Add syscall entries for non multiplexed socket calls Linux kernel already has socket syscalls that can be invoked without the multiplexing sys_socketcall wrapper. C library wrappers are ready to use them directly. It needs just to define the missing syscall numbers and provide the related entries into the syscalls table, like sh64 aleady does. Signed-off-by: Francesco Rundo Signed-off-by: Carmelo Amoroso Signed-off-by: Paul Mundt --- arch/sh/include/asm/unistd_32.h | 21 ++++++++++++++++++++- arch/sh/kernel/syscalls_32.S | 18 ++++++++++++++++++ 2 files changed, 38 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/sh/include/asm/unistd_32.h b/arch/sh/include/asm/unistd_32.h index 01183ad..2000709 100644 --- a/arch/sh/include/asm/unistd_32.h +++ b/arch/sh/include/asm/unistd_32.h @@ -349,7 +349,26 @@ #define __NR_fanotify_mark 338 #define __NR_prlimit64 339 -#define NR_syscalls 340 +/* Non-multiplexed socket family */ +#define __NR_socket 340 +#define __NR_bind 341 +#define __NR_connect 342 +#define __NR_listen 343 +#define __NR_accept 344 +#define __NR_getsockname 345 +#define __NR_getpeername 346 +#define __NR_socketpair 347 +#define __NR_send 348 +#define __NR_sendto 349 +#define __NR_recv 350 +#define __NR_recvfrom 351 +#define __NR_shutdown 352 +#define __NR_setsockopt 353 +#define __NR_getsockopt 354 +#define __NR_sendmsg 355 +#define __NR_recvmsg 356 + +#define NR_syscalls 357 #ifdef __KERNEL__ diff --git a/arch/sh/kernel/syscalls_32.S b/arch/sh/kernel/syscalls_32.S index 3c6d669..0847433 100644 --- a/arch/sh/kernel/syscalls_32.S +++ b/arch/sh/kernel/syscalls_32.S @@ -356,3 +356,21 @@ ENTRY(sys_call_table) .long sys_fanotify_init .long sys_fanotify_mark .long sys_prlimit64 + /* Broken-out socket family */ + .long sys_socket /* 340 */ + .long sys_bind + .long sys_connect + .long sys_listen + .long sys_accept + .long sys_getsockname /* 345 */ + .long sys_getpeername + .long sys_socketpair + .long sys_send + .long sys_sendto + .long sys_recv /* 350 */ + .long sys_recvfrom + .long sys_shutdown + .long sys_setsockopt + .long sys_getsockopt + .long sys_sendmsg /* 355 */ + .long sys_recvmsg -- cgit v1.1 From 51d149be0a535634b86493a4d910e3320cc984ea Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Tue, 14 Sep 2010 17:43:11 +0900 Subject: sh: Provide a non-multiplexed sys_recvmmsg path. Now that the rest of the socket calls are provided through their own paths, do the same for sys_recvmmsg. It's unlikely we'll ever be able to kill off the socketcall path, but this at least permits userspace to gradually begin migrating. Signed-off-by: Paul Mundt --- arch/sh/include/asm/unistd_32.h | 39 +++++++++++++++++++-------------------- arch/sh/kernel/syscalls_32.S | 1 + 2 files changed, 20 insertions(+), 20 deletions(-) (limited to 'arch') diff --git a/arch/sh/include/asm/unistd_32.h b/arch/sh/include/asm/unistd_32.h index 2000709..903cd618e 100644 --- a/arch/sh/include/asm/unistd_32.h +++ b/arch/sh/include/asm/unistd_32.h @@ -350,30 +350,29 @@ #define __NR_prlimit64 339 /* Non-multiplexed socket family */ -#define __NR_socket 340 -#define __NR_bind 341 -#define __NR_connect 342 -#define __NR_listen 343 -#define __NR_accept 344 -#define __NR_getsockname 345 -#define __NR_getpeername 346 -#define __NR_socketpair 347 -#define __NR_send 348 -#define __NR_sendto 349 -#define __NR_recv 350 -#define __NR_recvfrom 351 -#define __NR_shutdown 352 -#define __NR_setsockopt 353 -#define __NR_getsockopt 354 -#define __NR_sendmsg 355 -#define __NR_recvmsg 356 +#define __NR_socket 340 +#define __NR_bind 341 +#define __NR_connect 342 +#define __NR_listen 343 +#define __NR_accept 344 +#define __NR_getsockname 345 +#define __NR_getpeername 346 +#define __NR_socketpair 347 +#define __NR_send 348 +#define __NR_sendto 349 +#define __NR_recv 350 +#define __NR_recvfrom 351 +#define __NR_shutdown 352 +#define __NR_setsockopt 353 +#define __NR_getsockopt 354 +#define __NR_sendmsg 355 +#define __NR_recvmsg 356 +#define __NR_recvmmsg 357 -#define NR_syscalls 357 +#define NR_syscalls 358 #ifdef __KERNEL__ -#define __IGNORE_recvmmsg - #define __ARCH_WANT_IPC_PARSE_VERSION #define __ARCH_WANT_OLD_READDIR #define __ARCH_WANT_OLD_STAT diff --git a/arch/sh/kernel/syscalls_32.S b/arch/sh/kernel/syscalls_32.S index 0847433..e872e81 100644 --- a/arch/sh/kernel/syscalls_32.S +++ b/arch/sh/kernel/syscalls_32.S @@ -374,3 +374,4 @@ ENTRY(sys_call_table) .long sys_getsockopt .long sys_sendmsg /* 355 */ .long sys_recvmsg + .long sys_recvmmsg -- cgit v1.1 From 5d75b3a2476d848a354d939d2b89c36d3394ac59 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Tue, 14 Sep 2010 18:26:38 +0900 Subject: Revert "sh: ecovec24: modify tsc2007 platform settings" According to Morimoto-san, this is no longer needed. Revert it. This reverts commit e0009b0a44f28227571d8cddebc5ccdae86027a6. Signed-off-by: Paul Mundt --- arch/sh/boards/mach-ecovec24/setup.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/sh/boards/mach-ecovec24/setup.c b/arch/sh/boards/mach-ecovec24/setup.c index db7a7c0..1d7b495 100644 --- a/arch/sh/boards/mach-ecovec24/setup.c +++ b/arch/sh/boards/mach-ecovec24/setup.c @@ -400,9 +400,32 @@ static struct platform_device keysc_device = { /* TouchScreen */ #define IRQ0 32 +static int ts_get_pendown_state(void) +{ + int val = 0; + gpio_free(GPIO_FN_INTC_IRQ0); + gpio_request(GPIO_PTZ0, NULL); + gpio_direction_input(GPIO_PTZ0); + + val = gpio_get_value(GPIO_PTZ0); + + gpio_free(GPIO_PTZ0); + gpio_request(GPIO_FN_INTC_IRQ0, NULL); + + return val ? 0 : 1; +} + +static int ts_init(void) +{ + gpio_request(GPIO_FN_INTC_IRQ0, NULL); + return 0; +} + static struct tsc2007_platform_data tsc2007_info = { .model = 2007, - .x_plate_ohms = 1000, + .x_plate_ohms = 180, + .get_pendown_state = ts_get_pendown_state, + .init_platform_hw = ts_init, }; static struct i2c_board_info ts_i2c_clients = { @@ -1096,7 +1119,6 @@ static int __init arch_setup(void) gpio_direction_output(GPIO_PTF4, 1); /* enable TouchScreen */ - gpio_request(GPIO_FN_INTC_IRQ0, NULL); i2c_register_board_info(0, &ts_i2c_clients, 1); set_irq_type(IRQ0, IRQ_TYPE_LEVEL_LOW); } -- cgit v1.1 From 892df7f81c31ce7f85778aa78094e8d1f19b8413 Mon Sep 17 00:00:00 2001 From: Udo van den Heuvel Date: Tue, 14 Sep 2010 07:15:08 +0200 Subject: x86: HPET force enable for CX700 / VIA Epia LT Allow using HPET with the hpet=force command line option on VIA EPIA CX700 systems. Signed-off-by: Udo van den Heuvel Cc: Robert Hancock LKML-Reference: <4C8F04DC.5060303@xs4all.nl> Signed-off-by: Thomas Gleixner --- arch/x86/kernel/quirks.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/x86/kernel/quirks.c b/arch/x86/kernel/quirks.c index 939b9e9..8bbe8c5 100644 --- a/arch/x86/kernel/quirks.c +++ b/arch/x86/kernel/quirks.c @@ -344,6 +344,8 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, vt8237_force_enable_hpet); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, vt8237_force_enable_hpet); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_CX700, + vt8237_force_enable_hpet); static void ati_force_hpet_resume(void) { -- cgit v1.1 From d71415e88447f31ec63026e69b64a7e99465b7f4 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 14 Sep 2010 19:35:00 +0000 Subject: sh: kill big kernel lock The only BKL user in arch/sh protects a single bit, so we can trivially replace it with test_and_set_bit. Signed-off-by: Arnd Bergmann Cc: Paul Mundt Cc: linux-sh@vger.kernel.org Signed-off-by: Paul Mundt --- arch/sh/kernel/ptrace_64.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/sh/kernel/ptrace_64.c b/arch/sh/kernel/ptrace_64.c index b978170..e0fb065 100644 --- a/arch/sh/kernel/ptrace_64.c +++ b/arch/sh/kernel/ptrace_64.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include #include @@ -474,10 +474,9 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) asmlinkage int sh64_ptrace(long request, long pid, long addr, long data) { #define WPC_DBRMODE 0x0d104008 - static int first_call = 1; + static unsigned long first_call; - lock_kernel(); - if (first_call) { + if (!test_and_set_bit(0, &first_call)) { /* Set WPC.DBRMODE to 0. This makes all debug events get * delivered through RESVEC, i.e. into the handlers in entry.S. * (If the kernel was downloaded using a remote gdb, WPC.DBRMODE @@ -487,9 +486,7 @@ asmlinkage int sh64_ptrace(long request, long pid, long addr, long data) * the remote gdb.) */ printk("DBRMODE set to 0 to permit native debugging\n"); poke_real_address_q(WPC_DBRMODE, 0); - first_call = 0; } - unlock_kernel(); return sys_ptrace(request, pid, addr, data); } -- cgit v1.1 From 5d8e3451d172441ac9f4aa1d0ff8706412bc7deb Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 15 Sep 2010 06:38:07 +0000 Subject: ARM: mach-shmobile: modify wrong array size of div6_reparent_clks Signed-off-by: Kuninori Morimoto Reviewed-by: Guennadi Liakhovetski Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/clock-sh7372.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c index 7594689..ea384e1 100644 --- a/arch/arm/mach-shmobile/clock-sh7372.c +++ b/arch/arm/mach-shmobile/clock-sh7372.c @@ -548,7 +548,7 @@ void __init sh7372_clock_init(void) ret = sh_clk_div6_register(div6_clks, DIV6_NR); if (!ret) - ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_NR); + ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_REPARENT_NR); if (!ret) ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR); -- cgit v1.1 From c0b0aca0e0e8c479c43c1e126cddc5fc82b2803a Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 6 Jul 2010 19:16:33 +0200 Subject: arm/omap: use generic_file_llseek in iommu_debug In future kernels, debugfs files need to specify the llseek operation explicitly to allow seeking. This sets the llseek operation in the omap iommu debugfs files to generic_file_llseek, which is appropriate for files using simple_read_from_buffer. Signed-off-by: Arnd Bergmann Cc: Tony Lindgren Cc: linux-omap@vger.kernel.org --- arch/arm/plat-omap/iommu-debug.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/plat-omap/iommu-debug.c b/arch/arm/plat-omap/iommu-debug.c index e6c0d53..f07cf2f 100644 --- a/arch/arm/plat-omap/iommu-debug.c +++ b/arch/arm/plat-omap/iommu-debug.c @@ -328,12 +328,14 @@ static int debug_open_generic(struct inode *inode, struct file *file) .open = debug_open_generic, \ .read = debug_read_##name, \ .write = debug_write_##name, \ + .llseek = generic_file_llseek, \ }; #define DEBUG_FOPS_RO(name) \ static const struct file_operations debug_##name##_fops = { \ .open = debug_open_generic, \ .read = debug_read_##name, \ + .llseek = generic_file_llseek, \ }; DEBUG_FOPS_RO(ver); -- cgit v1.1 From fe3b79dfdc34e562b8378fa958a503a2d5b077ff Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 6 Jul 2010 22:40:19 +0200 Subject: spufs: use llseek in all file operations The default for llseek is changing, so we need explicit operations everywhere. Signed-off-by: Arnd Bergmann Cc: Jeremy Kerr Cc: linuxppc-dev@ozlabs.org --- arch/powerpc/platforms/cell/spufs/file.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch') diff --git a/arch/powerpc/platforms/cell/spufs/file.c b/arch/powerpc/platforms/cell/spufs/file.c index 1a40da9..02f7b11 100644 --- a/arch/powerpc/platforms/cell/spufs/file.c +++ b/arch/powerpc/platforms/cell/spufs/file.c @@ -154,6 +154,7 @@ static const struct file_operations __fops = { \ .release = spufs_attr_release, \ .read = spufs_attr_read, \ .write = spufs_attr_write, \ + .llseek = generic_file_llseek, \ }; @@ -521,6 +522,7 @@ static const struct file_operations spufs_cntl_fops = { .release = spufs_cntl_release, .read = simple_attr_read, .write = simple_attr_write, + .llseek = generic_file_llseek, .mmap = spufs_cntl_mmap, }; @@ -714,6 +716,7 @@ static ssize_t spufs_mbox_read(struct file *file, char __user *buf, static const struct file_operations spufs_mbox_fops = { .open = spufs_pipe_open, .read = spufs_mbox_read, + .llseek = no_llseek, }; static ssize_t spufs_mbox_stat_read(struct file *file, char __user *buf, @@ -743,6 +746,7 @@ static ssize_t spufs_mbox_stat_read(struct file *file, char __user *buf, static const struct file_operations spufs_mbox_stat_fops = { .open = spufs_pipe_open, .read = spufs_mbox_stat_read, + .llseek = no_llseek, }; /* low-level ibox access function */ @@ -863,6 +867,7 @@ static const struct file_operations spufs_ibox_fops = { .read = spufs_ibox_read, .poll = spufs_ibox_poll, .fasync = spufs_ibox_fasync, + .llseek = no_llseek, }; static ssize_t spufs_ibox_stat_read(struct file *file, char __user *buf, @@ -890,6 +895,7 @@ static ssize_t spufs_ibox_stat_read(struct file *file, char __user *buf, static const struct file_operations spufs_ibox_stat_fops = { .open = spufs_pipe_open, .read = spufs_ibox_stat_read, + .llseek = no_llseek, }; /* low-level mailbox write */ @@ -1011,6 +1017,7 @@ static const struct file_operations spufs_wbox_fops = { .write = spufs_wbox_write, .poll = spufs_wbox_poll, .fasync = spufs_wbox_fasync, + .llseek = no_llseek, }; static ssize_t spufs_wbox_stat_read(struct file *file, char __user *buf, @@ -1038,6 +1045,7 @@ static ssize_t spufs_wbox_stat_read(struct file *file, char __user *buf, static const struct file_operations spufs_wbox_stat_fops = { .open = spufs_pipe_open, .read = spufs_wbox_stat_read, + .llseek = no_llseek, }; static int spufs_signal1_open(struct inode *inode, struct file *file) @@ -1166,6 +1174,7 @@ static const struct file_operations spufs_signal1_fops = { .read = spufs_signal1_read, .write = spufs_signal1_write, .mmap = spufs_signal1_mmap, + .llseek = no_llseek, }; static const struct file_operations spufs_signal1_nosched_fops = { @@ -1173,6 +1182,7 @@ static const struct file_operations spufs_signal1_nosched_fops = { .release = spufs_signal1_release, .write = spufs_signal1_write, .mmap = spufs_signal1_mmap, + .llseek = no_llseek, }; static int spufs_signal2_open(struct inode *inode, struct file *file) @@ -1305,6 +1315,7 @@ static const struct file_operations spufs_signal2_fops = { .read = spufs_signal2_read, .write = spufs_signal2_write, .mmap = spufs_signal2_mmap, + .llseek = no_llseek, }; static const struct file_operations spufs_signal2_nosched_fops = { @@ -1312,6 +1323,7 @@ static const struct file_operations spufs_signal2_nosched_fops = { .release = spufs_signal2_release, .write = spufs_signal2_write, .mmap = spufs_signal2_mmap, + .llseek = no_llseek, }; /* @@ -1451,6 +1463,7 @@ static const struct file_operations spufs_mss_fops = { .open = spufs_mss_open, .release = spufs_mss_release, .mmap = spufs_mss_mmap, + .llseek = no_llseek, }; static int @@ -1508,6 +1521,7 @@ static const struct file_operations spufs_psmap_fops = { .open = spufs_psmap_open, .release = spufs_psmap_release, .mmap = spufs_psmap_mmap, + .llseek = no_llseek, }; @@ -1871,6 +1885,7 @@ static const struct file_operations spufs_mfc_fops = { .fsync = spufs_mfc_fsync, .fasync = spufs_mfc_fasync, .mmap = spufs_mfc_mmap, + .llseek = no_llseek, }; static int spufs_npc_set(void *data, u64 val) @@ -2246,6 +2261,7 @@ static ssize_t spufs_dma_info_read(struct file *file, char __user *buf, static const struct file_operations spufs_dma_info_fops = { .open = spufs_info_open, .read = spufs_dma_info_read, + .llseek = no_llseek, }; static ssize_t __spufs_proxydma_info_read(struct spu_context *ctx, @@ -2299,6 +2315,7 @@ static ssize_t spufs_proxydma_info_read(struct file *file, char __user *buf, static const struct file_operations spufs_proxydma_info_fops = { .open = spufs_info_open, .read = spufs_proxydma_info_read, + .llseek = no_llseek, }; static int spufs_show_tid(struct seq_file *s, void *private) @@ -2585,6 +2602,7 @@ static const struct file_operations spufs_switch_log_fops = { .read = spufs_switch_log_read, .poll = spufs_switch_log_poll, .release = spufs_switch_log_release, + .llseek = no_llseek, }; /** -- cgit v1.1 From 995bd3bb5c78f3ff71339803c0b8337ed36d64fb Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 15 Sep 2010 15:11:57 +0200 Subject: x86: Hpet: Avoid the comparator readback penalty Due to the overly intelligent design of HPETs, we need to workaround the problem that the compare value which we write is already behind the actual counter value at the point where the value hits the real compare register. This happens for two reasons: 1) We read out the counter, add the delta and write the result to the compare register. When a NMI or SMI hits between the read out and the write then the counter can be ahead of the event already 2) The write to the compare register is delayed by up to two HPET cycles in certain chipsets. We worked around this by reading back the compare register to make sure that the written value has hit the hardware. For certain ICH9+ chipsets this can require two readouts, as the first one can return the previous compare register value. That's bad performance wise for the normal case where the event is far enough in the future. As we already know that the write can be delayed by up to two cycles we can avoid the read back of the compare register completely if we make the decision whether the delta has elapsed already or not based on the following calculation: cmp = event - actual_count; If cmp is less than 8 HPET clock cycles, then we decide that the event has happened already and return -ETIME. That covers the above #1 and #2 problems which would cause a wait for HPET wraparound (~306 seconds). Signed-off-by: Thomas Gleixner Tested-by: Nix Tested-by: Artur Skawina Cc: Damien Wyart Tested-by: John Drescher Cc: Venkatesh Pallipadi Cc: Arjan van de Ven Cc: Andreas Herrmann Tested-by: Borislav Petkov Cc: Suresh Siddha LKML-Reference: --- arch/x86/kernel/hpet.c | 51 +++++++++++++++++++++----------------------------- 1 file changed, 21 insertions(+), 30 deletions(-) (limited to 'arch') diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c index 410fdb3..0b568b30 100644 --- a/arch/x86/kernel/hpet.c +++ b/arch/x86/kernel/hpet.c @@ -380,44 +380,35 @@ static int hpet_next_event(unsigned long delta, struct clock_event_device *evt, int timer) { u32 cnt; + s32 res; cnt = hpet_readl(HPET_COUNTER); cnt += (u32) delta; hpet_writel(cnt, HPET_Tn_CMP(timer)); /* - * We need to read back the CMP register on certain HPET - * implementations (ATI chipsets) which seem to delay the - * transfer of the compare register into the internal compare - * logic. With small deltas this might actually be too late as - * the counter could already be higher than the compare value - * at that point and we would wait for the next hpet interrupt - * forever. We found out that reading the CMP register back - * forces the transfer so we can rely on the comparison with - * the counter register below. If the read back from the - * compare register does not match the value we programmed - * then we might have a real hardware problem. We can not do - * much about it here, but at least alert the user/admin with - * a prominent warning. - * - * An erratum on some chipsets (ICH9,..), results in - * comparator read immediately following a write returning old - * value. Workaround for this is to read this value second - * time, when first read returns old value. - * - * In fact the write to the comparator register is delayed up - * to two HPET cycles so the workaround we tried to restrict - * the readback to those known to be borked ATI chipsets - * failed miserably. So we give up on optimizations forever - * and penalize all HPET incarnations unconditionally. + * HPETs are a complete disaster. The compare register is + * based on a equal comparison and neither provides a less + * than or equal functionality (which would require to take + * the wraparound into account) nor a simple count down event + * mode. Further the write to the comparator register is + * delayed internally up to two HPET clock cycles in certain + * chipsets (ATI, ICH9,10). We worked around that by reading + * back the compare register, but that required another + * workaround for ICH9,10 chips where the first readout after + * write can return the old stale value. We already have a + * minimum delta of 5us enforced, but a NMI or SMI hitting + * between the counter readout and the comparator write can + * move us behind that point easily. Now instead of reading + * the compare register back several times, we make the ETIME + * decision based on the following: Return ETIME if the + * counter value after the write is less than 8 HPET cycles + * away from the event or if the counter is already ahead of + * the event. */ - if (unlikely((u32)hpet_readl(HPET_Tn_CMP(timer)) != cnt)) { - if (hpet_readl(HPET_Tn_CMP(timer)) != cnt) - printk_once(KERN_WARNING - "hpet: compare register read back failed.\n"); - } + res = (s32)(cnt - hpet_readl(HPET_COUNTER)); - return (s32)(hpet_readl(HPET_COUNTER) - cnt) >= 0 ? -ETIME : 0; + return res < 8 ? -ETIME : 0; } static void hpet_legacy_set_mode(enum clock_event_mode mode, -- cgit v1.1 From c62e3fae58198fc1f5d7922f84fe91b3fcf61177 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Sun, 19 Sep 2010 13:51:15 +0900 Subject: sh: pci: Use generic pci_enable_resources() for pcibios_enable_device(). Signed-off-by: Paul Mundt --- arch/sh/drivers/pci/pci.c | 35 +---------------------------------- 1 file changed, 1 insertion(+), 34 deletions(-) (limited to 'arch') diff --git a/arch/sh/drivers/pci/pci.c b/arch/sh/drivers/pci/pci.c index 1e9598d..e4c988d 100644 --- a/arch/sh/drivers/pci/pci.c +++ b/arch/sh/drivers/pci/pci.c @@ -233,40 +233,7 @@ void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, int pcibios_enable_device(struct pci_dev *dev, int mask) { - u16 cmd, old_cmd; - int idx; - struct resource *r; - - pci_read_config_word(dev, PCI_COMMAND, &cmd); - old_cmd = cmd; - for (idx=0; idx < PCI_NUM_RESOURCES; idx++) { - /* Only set up the requested stuff */ - if (!(mask & (1<resource[idx]; - if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) - continue; - if ((idx == PCI_ROM_RESOURCE) && - (!(r->flags & IORESOURCE_ROM_ENABLE))) - continue; - if (!r->start && r->end) { - printk(KERN_ERR "PCI: Device %s not available " - "because of resource collisions\n", - pci_name(dev)); - return -EINVAL; - } - if (r->flags & IORESOURCE_IO) - cmd |= PCI_COMMAND_IO; - if (r->flags & IORESOURCE_MEM) - cmd |= PCI_COMMAND_MEMORY; - } - if (cmd != old_cmd) { - printk("PCI: Enabling device %s (%04x -> %04x)\n", - pci_name(dev), old_cmd, cmd); - pci_write_config_word(dev, PCI_COMMAND, cmd); - } - return 0; + return pci_enable_resources(dev, mask); } /* -- cgit v1.1 From bdf7499081fc3c521d0f8fc28c6950c7c9bd7e97 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Sun, 19 Sep 2010 13:54:50 +0900 Subject: sh: pci: Toggle configuration accesses on SH7786. After configuration accesses have been completed deassert the configuration access enable cleanly. Signed-off-by: Paul Mundt --- arch/sh/drivers/pci/ops-sh7786.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/sh/drivers/pci/ops-sh7786.c b/arch/sh/drivers/pci/ops-sh7786.c index 79a5dda..4728199 100644 --- a/arch/sh/drivers/pci/ops-sh7786.c +++ b/arch/sh/drivers/pci/ops-sh7786.c @@ -58,6 +58,9 @@ static int sh7786_pcie_config_access(unsigned char access_type, else pci_write_reg(chan, *data, SH4A_PCIEPDR); + /* Disable the configuration access */ + pci_write_reg(chan, 0, SH4A_PCIEPCTLR); + return PCIBIOS_SUCCESSFUL; } -- cgit v1.1 From 81df84f4060f4f19c7e6f39c7c527a6098436a2a Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Sun, 19 Sep 2010 13:57:51 +0900 Subject: sh: pci: Give SH7786 PHY some time to settle. The spec suggests waiting up to 500ms for the PHY to settle before testing link state, but practice shows that 100ms is sufficient (this is the delay value we also use on the other SH-4A PCI controllers, too). This makes device detection much more reliable, although in the future it should be a bit faster to simply serialize with a TLP IRQ. Signed-off-by: Paul Mundt --- arch/sh/drivers/pci/pcie-sh7786.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/sh/drivers/pci/pcie-sh7786.c b/arch/sh/drivers/pci/pcie-sh7786.c index 5ae58ec..4e6cf88 100644 --- a/arch/sh/drivers/pci/pcie-sh7786.c +++ b/arch/sh/drivers/pci/pcie-sh7786.c @@ -312,6 +312,9 @@ static int pcie_init(struct sh7786_pcie_port *port) data |= 0x1; pci_write_reg(chan, data, SH4A_PCIETCTLR); + /* Let things settle down a bit.. */ + mdelay(100); + /* Enable DL_Active Interrupt generation */ data = pci_read_reg(chan, SH4A_PCIEDLINTENR); data |= PCIEDLINTENR_DLL_ACT_ENABLE; -- cgit v1.1 From 7d25d64441a8ce9fb8c0e1c889badb14d8af9370 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Fri, 17 Sep 2010 12:30:00 +0200 Subject: sh: fix an SIU device name mismatch Recent ASoC changes unified all PCM names, fix the platform code to match. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Mark Brown --- arch/sh/kernel/cpu/sh4a/setup-sh7722.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c index 156ccc9..d551ed8 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c @@ -551,7 +551,7 @@ static struct resource siu_resources[] = { }; static struct platform_device siu_device = { - .name = "sh_siu", + .name = "siu-pcm-audio", .id = -1, .dev = { .platform_data = &siu_platform_data, -- cgit v1.1 From 838a2e55e6a4e9e8a10451ed2ef0f7a08dabdb04 Mon Sep 17 00:00:00 2001 From: Arnaud Lacombe Date: Sat, 4 Sep 2010 17:10:20 -0400 Subject: kbuild: migrate all arch to the kconfig mainmenu upgrade Signed-off-by: Arnaud Lacombe Reviewed-by: Sam Ravnborg Reviewed-by: Michal Marek --- arch/alpha/Kconfig | 4 ---- arch/arm/Kconfig | 7 ------- arch/avr32/Kconfig | 7 ------- arch/blackfin/Kconfig | 7 ------- arch/cris/Kconfig | 7 ------- arch/frv/Kconfig | 6 ------ arch/h8300/Kconfig | 7 ------- arch/ia64/Kconfig | 7 ------- arch/m32r/Kconfig | 7 ------- arch/m68k/Kconfig | 6 ------ arch/m68knommu/Kconfig | 7 ------- arch/microblaze/Kconfig | 5 ----- arch/mips/Kconfig | 2 -- arch/mn10300/Kconfig | 9 --------- arch/parisc/Kconfig | 7 ------- arch/powerpc/Kconfig | 6 ------ arch/s390/Kconfig | 7 ------- arch/score/Kconfig | 5 ----- arch/sh/Kconfig | 7 ------- arch/sparc/Kconfig | 6 ------ arch/um/Kconfig.common | 2 -- arch/x86/Kconfig | 3 --- arch/xtensa/Kconfig | 5 ----- 23 files changed, 136 deletions(-) (limited to 'arch') diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig index 3e2e540..95808c1 100644 --- a/arch/alpha/Kconfig +++ b/arch/alpha/Kconfig @@ -1,7 +1,3 @@ -# -# For a description of the syntax of this configuration file, -# see Documentation/kbuild/kconfig-language.txt. -# config ALPHA bool default y diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 98922f7..c3f4fd9 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1,10 +1,3 @@ -# -# For a description of the syntax of this configuration file, -# see Documentation/kbuild/kconfig-language.txt. -# - -mainmenu "Linux Kernel Configuration" - config ARM bool default y diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig index f2b3193..ead727e 100644 --- a/arch/avr32/Kconfig +++ b/arch/avr32/Kconfig @@ -1,10 +1,3 @@ -# -# For a description of the syntax of this configuration file, -# see Documentation/kbuild/kconfig-language.txt. -# - -mainmenu "Linux Kernel Configuration" - config AVR32 def_bool y # With EMBEDDED=n, we get lots of stuff automatically selected diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index f66294b..7051c4c 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -1,10 +1,3 @@ -# -# For a description of the syntax of this configuration file, -# see Documentation/kbuild/kconfig-language.txt. -# - -mainmenu "Blackfin Kernel Configuration" - config SYMBOL_PREFIX string default "_" diff --git a/arch/cris/Kconfig b/arch/cris/Kconfig index e25bf44..af8e982 100644 --- a/arch/cris/Kconfig +++ b/arch/cris/Kconfig @@ -1,10 +1,3 @@ -# -# For a description of the syntax of this configuration file, -# see the Configure script. -# - -mainmenu "Linux/CRIS Kernel Configuration" - config MMU bool default y diff --git a/arch/frv/Kconfig b/arch/frv/Kconfig index 4b5830b..0625679 100644 --- a/arch/frv/Kconfig +++ b/arch/frv/Kconfig @@ -1,7 +1,3 @@ -# -# For a description of the syntax of this configuration file, -# see Documentation/kbuild/kconfig-language.txt. -# config FRV bool default y @@ -64,8 +60,6 @@ config HZ int default 1000 -mainmenu "Fujitsu FR-V Kernel Configuration" - source "init/Kconfig" source "kernel/Kconfig.freezer" diff --git a/arch/h8300/Kconfig b/arch/h8300/Kconfig index 53cc669..3fe4d5a 100644 --- a/arch/h8300/Kconfig +++ b/arch/h8300/Kconfig @@ -1,10 +1,3 @@ -# -# For a description of the syntax of this configuration file, -# see Documentation/kbuild/kconfig-language.txt. -# - -mainmenu "uClinux/h8300 (w/o MMU) Kernel Configuration" - config H8300 bool default y diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig index 9561082..09ce2ab 100644 --- a/arch/ia64/Kconfig +++ b/arch/ia64/Kconfig @@ -1,10 +1,3 @@ -# -# For a description of the syntax of this configuration file, -# see Documentation/kbuild/kconfig-language.txt. -# - -mainmenu "IA-64 Linux Kernel Configuration" - source "init/Kconfig" source "kernel/Kconfig.freezer" diff --git a/arch/m32r/Kconfig b/arch/m32r/Kconfig index 3a9319f..190270e 100644 --- a/arch/m32r/Kconfig +++ b/arch/m32r/Kconfig @@ -1,10 +1,3 @@ -# -# For a description of the syntax of this configuration file, -# see Documentation/kbuild/kconfig-language.txt. -# - -mainmenu "Linux/M32R Kernel Configuration" - config M32R bool default y diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig index 2e3737b..1812aa0 100644 --- a/arch/m68k/Kconfig +++ b/arch/m68k/Kconfig @@ -1,7 +1,3 @@ -# -# For a description of the syntax of this configuration file, -# see Documentation/kbuild/kconfig-language.txt. -# config M68K bool default y @@ -65,8 +61,6 @@ config GENERIC_TIME config ARCH_USES_GETTIMEOFFSET def_bool y -mainmenu "Linux/68k Kernel Configuration" - source "init/Kconfig" source "kernel/Kconfig.freezer" diff --git a/arch/m68knommu/Kconfig b/arch/m68knommu/Kconfig index efeb603..e86842d 100644 --- a/arch/m68knommu/Kconfig +++ b/arch/m68knommu/Kconfig @@ -1,10 +1,3 @@ -# -# For a description of the syntax of this configuration file, -# see Documentation/kbuild/kconfig-language.txt. -# - -mainmenu "uClinux/68k (w/o MMU) Kernel Configuration" - config M68K bool default y diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index 505a085..0c5f437 100644 --- a/arch/microblaze/Kconfig +++ b/arch/microblaze/Kconfig @@ -1,8 +1,3 @@ -# For a description of the syntax of this configuration file, -# see Documentation/kbuild/kconfig-language.txt. - -mainmenu "Linux/Microblaze Kernel Configuration" - config MICROBLAZE def_bool y select HAVE_MEMBLOCK diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index cdaae94..3377167 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -12,8 +12,6 @@ config MIPS select HAVE_FUNCTION_GRAPH_TRACER select RTC_LIB if !MACH_LOONGSON -mainmenu "Linux/MIPS Kernel Configuration" - menu "Machine selection" config ZONE_DMA diff --git a/arch/mn10300/Kconfig b/arch/mn10300/Kconfig index 1c4565a..7bd617c 100644 --- a/arch/mn10300/Kconfig +++ b/arch/mn10300/Kconfig @@ -1,10 +1,3 @@ -# -# For a description of the syntax of this configuration file, -# see Documentation/kbuild/kconfig-language.txt. -# - -mainmenu "Linux Kernel Configuration" - config MN10300 def_bool y select HAVE_OPROFILE @@ -69,8 +62,6 @@ config HZ int default 1000 -mainmenu "Matsushita MN10300/AM33 Kernel Configuration" - source "init/Kconfig" source "kernel/Kconfig.freezer" diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig index 05a366a..82cec34 100644 --- a/arch/parisc/Kconfig +++ b/arch/parisc/Kconfig @@ -1,10 +1,3 @@ -# -# For a description of the syntax of this configuration file, -# see Documentation/kbuild/kconfig-language.txt. -# - -mainmenu "Linux/PA-RISC Kernel Configuration" - config PARISC def_bool y select HAVE_IDE diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 2031a28..182743b 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -1,9 +1,3 @@ -# For a description of the syntax of this configuration file, -# see Documentation/kbuild/kconfig-language.txt. -# - -mainmenu "Linux/PowerPC Kernel Configuration" - source "arch/powerpc/platforms/Kconfig.cputype" config PPC32 diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig index bee1c0f..3c4d4e6 100644 --- a/arch/s390/Kconfig +++ b/arch/s390/Kconfig @@ -1,8 +1,3 @@ -# -# For a description of the syntax of this configuration file, -# see Documentation/kbuild/kconfig-language.txt. -# - config SCHED_MC def_bool y depends on SMP @@ -78,8 +73,6 @@ config VIRT_CPU_ACCOUNTING config ARCH_SUPPORTS_DEBUG_PAGEALLOC def_bool y -mainmenu "Linux Kernel Configuration" - config S390 def_bool y select USE_GENERIC_SMP_HELPERS if SMP diff --git a/arch/score/Kconfig b/arch/score/Kconfig index 55d413e..5cbc148 100644 --- a/arch/score/Kconfig +++ b/arch/score/Kconfig @@ -1,8 +1,3 @@ -# For a description of the syntax of this configuration file, -# see Documentation/kbuild/kconfig-language.txt. - -mainmenu "Linux/SCORE Kernel Configuration" - menu "Machine selection" choice diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 82868fe..8ada475 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -1,10 +1,3 @@ -# -# For a description of the syntax of this configuration file, -# see Documentation/kbuild/kconfig-language.txt. -# - -mainmenu "Linux/SuperH Kernel Configuration" - config SUPERH def_bool y select EMBEDDED diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig index c0015db..19aa7b25 100644 --- a/arch/sparc/Kconfig +++ b/arch/sparc/Kconfig @@ -1,9 +1,3 @@ -# For a description of the syntax of this configuration file, -# see Documentation/kbuild/kconfig-language.txt. -# - -mainmenu "Linux/SPARC Kernel Configuration" - config 64BIT bool "64-bit kernel" if ARCH = "sparc" default ARCH = "sparc64" diff --git a/arch/um/Kconfig.common b/arch/um/Kconfig.common index 0d207e7..e90ca86 100644 --- a/arch/um/Kconfig.common +++ b/arch/um/Kconfig.common @@ -19,8 +19,6 @@ config MMU config NO_IOMEM def_bool y -mainmenu "Linux/Usermode Kernel Configuration" - config ISA bool diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index dcb0593..6c30b9e 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1,6 +1,3 @@ -# x86 configuration -mainmenu "Linux Kernel Configuration for x86" - # Select 32 or 64 bit config 64BIT bool "64-bit kernel" if ARCH = "x86" diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index ebe228d..9e4ef66 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -1,8 +1,3 @@ -# For a description of the syntax of this configuration file, -# see Documentation/kbuild/kconfig-language.txt. - -mainmenu "Linux/Xtensa Kernel Configuration" - config FRAME_POINTER def_bool n -- cgit v1.1 From cabdf8bf488bfa3b565360b9fa1322d2db7747eb Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Mon, 20 Sep 2010 15:37:25 +0900 Subject: sh: pci: Move Renesas PCI IDs to a better place. Previously these IDs were only used by one driver, so there was not much need for having them generically defined. Now that this will no longer hold true, move them over. Signed-off-by: Paul Mundt --- arch/sh/drivers/pci/pci-sh7780.h | 6 ------ 1 file changed, 6 deletions(-) (limited to 'arch') diff --git a/arch/sh/drivers/pci/pci-sh7780.h b/arch/sh/drivers/pci/pci-sh7780.h index 205dcbe..1742e2c 100644 --- a/arch/sh/drivers/pci/pci-sh7780.h +++ b/arch/sh/drivers/pci/pci-sh7780.h @@ -12,12 +12,6 @@ #ifndef _PCI_SH7780_H_ #define _PCI_SH7780_H_ -#define PCI_VENDOR_ID_RENESAS 0x1912 -#define PCI_DEVICE_ID_RENESAS_SH7781 0x0001 -#define PCI_DEVICE_ID_RENESAS_SH7780 0x0002 -#define PCI_DEVICE_ID_RENESAS_SH7763 0x0004 -#define PCI_DEVICE_ID_RENESAS_SH7785 0x0007 - /* SH7780 Control Registers */ #define PCIECR 0xFE000008 #define PCIECR_ENBL 0x01 -- cgit v1.1 From 2c65d75ec4dde5e619a462e70cdd7b67e0e64bb8 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Mon, 20 Sep 2010 15:39:54 +0900 Subject: sh: pci: Support root complex config accesses on SH7786 PCIe. The SH7786 PCIe is presently unable to enumerate itself in root complex mode, and has no visibility through either type 0 or type 1 accesses, despite having a mostly sensible extended config space for each port. Attempts to generate type 0 or type 1 config cycles result in completer aborts, so we're ultimately forced to use SuperHyway transactions instead. As each port has a single port <-> device mapping that resolves for any PCI_SLOT definition, we simply hijack devfn 0 for the SuperHyway transaction and bump up the devfn limit. With enumeration of the root complex now possible, we also need to insert an early fixup to hide the BARs from the kernel. With all of that done, it's now possible to use the pcieport services with all of the PCIe ports, which is the first step to power management support. Signed-off-by: Paul Mundt --- arch/sh/drivers/pci/ops-sh7786.c | 35 +++++++++++++++++++++++++++++++---- arch/sh/drivers/pci/pcie-sh7786.c | 29 ++++++++++++++++++++++++----- 2 files changed, 55 insertions(+), 9 deletions(-) (limited to 'arch') diff --git a/arch/sh/drivers/pci/ops-sh7786.c b/arch/sh/drivers/pci/ops-sh7786.c index 4728199..01cb70f 100644 --- a/arch/sh/drivers/pci/ops-sh7786.c +++ b/arch/sh/drivers/pci/ops-sh7786.c @@ -25,23 +25,49 @@ static int sh7786_pcie_config_access(unsigned char access_type, struct pci_bus *bus, unsigned int devfn, int where, u32 *data) { struct pci_channel *chan = bus->sysdata; - int dev, func, type; + int dev, func, type, reg; dev = PCI_SLOT(devfn); func = PCI_FUNC(devfn); type = !!bus->parent; + reg = where & ~3; if (bus->number > 255 || dev > 31 || func > 7) return PCIBIOS_FUNC_NOT_SUPPORTED; - if (bus->parent == NULL && dev) - return PCIBIOS_DEVICE_NOT_FOUND; + + /* + * While each channel has its own memory-mapped extended config + * space, it's generally only accessible when in endpoint mode. + * When in root complex mode, the controller is unable to target + * itself with either type 0 or type 1 accesses, and indeed, any + * controller initiated target transfer to its own config space + * result in a completer abort. + * + * Each channel effectively only supports a single device, but as + * the same channel <-> device access works for any PCI_SLOT() + * value, we cheat a bit here and bind the controller's config + * space to devfn 0 in order to enable self-enumeration. In this + * case the regular PAR/PDR path is sidelined and the mangled + * config access itself is initiated as a SuperHyway transaction. + */ + if (pci_is_root_bus(bus)) { + if (dev == 0) { + if (access_type == PCI_ACCESS_READ) + *data = pci_read_reg(chan, PCI_REG(reg)); + else + pci_write_reg(chan, *data, PCI_REG(reg)); + + return PCIBIOS_SUCCESSFUL; + } else if (dev > 1) + return PCIBIOS_DEVICE_NOT_FOUND; + } /* Clear errors */ pci_write_reg(chan, pci_read_reg(chan, SH4A_PCIEERRFR), SH4A_PCIEERRFR); /* Set the PIO address */ pci_write_reg(chan, (bus->number << 24) | (dev << 19) | - (func << 16) | (where & ~3), SH4A_PCIEPAR); + (func << 16) | reg, SH4A_PCIEPAR); /* Enable the configuration access */ pci_write_reg(chan, (1 << 31) | (type << 8), SH4A_PCIEPCTLR); @@ -49,6 +75,7 @@ static int sh7786_pcie_config_access(unsigned char access_type, /* Check for errors */ if (pci_read_reg(chan, SH4A_PCIEERRFR) & 0x10) return PCIBIOS_DEVICE_NOT_FOUND; + /* Check for master and target aborts */ if (pci_read_reg(chan, SH4A_PCIEPCICONF1) & ((1 << 29) | (1 << 28))) return PCIBIOS_DEVICE_NOT_FOUND; diff --git a/arch/sh/drivers/pci/pcie-sh7786.c b/arch/sh/drivers/pci/pcie-sh7786.c index 4e6cf88..3dfc250 100644 --- a/arch/sh/drivers/pci/pcie-sh7786.c +++ b/arch/sh/drivers/pci/pcie-sh7786.c @@ -121,6 +121,24 @@ static struct pci_channel sh7786_pci_channels[] = { DEFINE_CONTROLLER(0xfcc00000, 2), }; +static void __devinit sh7786_pci_fixup(struct pci_dev *dev) +{ + /* + * Prevent enumeration of root complex resources. + */ + if (pci_is_root_bus(dev->bus) && dev->devfn == 0) { + int i; + + for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { + dev->resource[i].start = 0; + dev->resource[i].end = 0; + dev->resource[i].flags = 0; + } + } +} +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_SH7786, + sh7786_pci_fixup); + static int phy_wait_for_ack(struct pci_channel *chan) { unsigned int timeout = 100; @@ -229,11 +247,12 @@ static int pcie_init(struct sh7786_pcie_port *port) /* Begin initialization */ pcie_reset(port); - /* Initialize as type1. */ - data = pci_read_reg(chan, SH4A_PCIEPCICONF3); - data &= ~(0x7f << 16); - data |= PCI_HEADER_TYPE_BRIDGE << 16; - pci_write_reg(chan, data, SH4A_PCIEPCICONF3); + /* + * Initial header for port config space is type 1, set the device + * class to match. Hardware takes care of propagating the IDSETR + * settings, so there is no need to bother with a quirk. + */ + pci_write_reg(chan, PCI_CLASS_BRIDGE_PCI << 16, SH4A_PCIEIDSETR1); /* Initialize default capabilities. */ data = pci_read_reg(chan, SH4A_PCIEEXPCAP0); -- cgit v1.1 From beb54ad9c6fb60901d9445056d40bdaccdc3e819 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Mon, 20 Sep 2010 16:00:42 +0900 Subject: sh: pci: Discard initial PCICONF4/5 settings for SH7786 PCIe. These settings are properly propagated by the hardware already, so there's no need to bother with them manually. Signed-off-by: Paul Mundt --- arch/sh/drivers/pci/pcie-sh7786.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch') diff --git a/arch/sh/drivers/pci/pcie-sh7786.c b/arch/sh/drivers/pci/pcie-sh7786.c index 3dfc250..21854eb 100644 --- a/arch/sh/drivers/pci/pcie-sh7786.c +++ b/arch/sh/drivers/pci/pcie-sh7786.c @@ -323,9 +323,6 @@ static int pcie_init(struct sh7786_pcie_port *port) __raw_writel(memphys, chan->reg_base + SH4A_PCIELAR0); __raw_writel((memsize - SZ_256) | 1, chan->reg_base + SH4A_PCIELAMR0); - __raw_writel(memphys, chan->reg_base + SH4A_PCIEPCICONF4); - __raw_writel(0, chan->reg_base + SH4A_PCIEPCICONF5); - /* Finish initialization */ data = pci_read_reg(chan, SH4A_PCIETCTLR); data |= 0x1; -- cgit v1.1 From bd792aea441a3dcdede462486ab8c63045803844 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Mon, 20 Sep 2010 16:12:58 +0900 Subject: sh: pci: Support ports with disabled links on SH7786 PCIe. Presently we error out if a link is disabled and simply drop the port registration outright. This follows the PPC changes and simply reports on the link state on boot, leaving the port registered, in order to more easily deal with hotplug on future parts. Signed-off-by: Paul Mundt --- arch/sh/drivers/pci/pcie-sh7786.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/sh/drivers/pci/pcie-sh7786.c b/arch/sh/drivers/pci/pcie-sh7786.c index 21854eb..aacd0fc 100644 --- a/arch/sh/drivers/pci/pcie-sh7786.c +++ b/arch/sh/drivers/pci/pcie-sh7786.c @@ -341,9 +341,12 @@ static int pcie_init(struct sh7786_pcie_port *port) data |= PCIEMACCTLR_SCR_DIS | (0xff << 16); pci_write_reg(chan, data, SH4A_PCIEMACCTLR); + /* + * This will timeout if we don't have a link, but we permit the + * port to register anyways in order to support hotplug on future + * hardware. + */ ret = pci_wait_for_irq(chan, MASK_INT_TX_CTRL); - if (unlikely(ret != 0)) - return -ENODEV; data = pci_read_reg(chan, SH4A_PCIEPCICONF1); data &= ~(PCI_STATUS_DEVSEL_MASK << 16); @@ -356,9 +359,13 @@ static int pcie_init(struct sh7786_pcie_port *port) wmb(); - data = pci_read_reg(chan, SH4A_PCIEMACSR); - printk(KERN_NOTICE "PCI: PCIe#%d link width %d\n", - port->index, (data >> 20) & 0x3f); + if (ret == 0) { + data = pci_read_reg(chan, SH4A_PCIEMACSR); + printk(KERN_NOTICE "PCI: PCIe#%d x%d link detected\n", + port->index, (data >> 20) & 0x3f); + } else + printk(KERN_NOTICE "PCI: PCIe#%d link down\n", + port->index); for (i = win = 0; i < chan->nr_resources; i++) { struct resource *res = chan->resources + i; -- cgit v1.1 From cecf48e23fd9270053850643a56e8e791322e3d5 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Mon, 20 Sep 2010 17:10:02 +0900 Subject: sh: pci: Use I/O accessors consistently in SH7786 PCIe init code. Some of the existing code is flipping between __raw_xxx() and pci_{read,write}_reg(). As the latter are just wrappers for the former, flip over to using them consistently. Signed-off-by: Paul Mundt --- arch/sh/drivers/pci/pcie-sh7786.c | 35 ++++++++++++++++++----------------- arch/sh/drivers/pci/pcie-sh7786.h | 7 +++++++ 2 files changed, 25 insertions(+), 17 deletions(-) (limited to 'arch') diff --git a/arch/sh/drivers/pci/pcie-sh7786.c b/arch/sh/drivers/pci/pcie-sh7786.c index aacd0fc..b0ef380 100644 --- a/arch/sh/drivers/pci/pcie-sh7786.c +++ b/arch/sh/drivers/pci/pcie-sh7786.c @@ -304,24 +304,24 @@ static int pcie_init(struct sh7786_pcie_port *port) * LAR1/LAMR1. */ if (memsize > SZ_512M) { - __raw_writel(memphys + SZ_512M, chan->reg_base + SH4A_PCIELAR1); - __raw_writel(((memsize - SZ_512M) - SZ_256) | 1, - chan->reg_base + SH4A_PCIELAMR1); + pci_write_reg(chan, memphys + SZ_512M, SH4A_PCIELAR1); + pci_write_reg(chan, ((memsize - SZ_512M) - SZ_256) | 1, + SH4A_PCIELAMR1); memsize = SZ_512M; } else { /* * Otherwise just zero it out and disable it. */ - __raw_writel(0, chan->reg_base + SH4A_PCIELAR1); - __raw_writel(0, chan->reg_base + SH4A_PCIELAMR1); + pci_write_reg(chan, 0, SH4A_PCIELAR1); + pci_write_reg(chan, 0, SH4A_PCIELAMR1); } /* * LAR0/LAMR0 covers up to the first 512MB, which is enough to * cover all of lowmem on most platforms. */ - __raw_writel(memphys, chan->reg_base + SH4A_PCIELAR0); - __raw_writel((memsize - SZ_256) | 1, chan->reg_base + SH4A_PCIELAMR0); + pci_write_reg(chan, memphys, SH4A_PCIELAR0); + pci_write_reg(chan, (memsize - SZ_256) | 1, SH4A_PCIELAMR0); /* Finish initialization */ data = pci_read_reg(chan, SH4A_PCIETCTLR); @@ -370,7 +370,7 @@ static int pcie_init(struct sh7786_pcie_port *port) for (i = win = 0; i < chan->nr_resources; i++) { struct resource *res = chan->resources + i; resource_size_t size; - u32 enable_mask; + u32 mask; /* * We can't use the 32-bit mode windows in legacy 29-bit @@ -381,23 +381,24 @@ static int pcie_init(struct sh7786_pcie_port *port) pci_write_reg(chan, 0x00000000, SH4A_PCIEPTCTLR(win)); - size = resource_size(res); - /* * The PAMR mask is calculated in units of 256kB, which * keeps things pretty simple. */ - __raw_writel(((roundup_pow_of_two(size) / SZ_256K) - 1) << 18, - chan->reg_base + SH4A_PCIEPAMR(win)); + size = resource_size(res); + mask = (roundup_pow_of_two(size) / SZ_256K) - 1; + pci_write_reg(chan, mask << 18, SH4A_PCIEPAMR(win)); - pci_write_reg(chan, res->start, SH4A_PCIEPARL(win)); - pci_write_reg(chan, 0x00000000, SH4A_PCIEPARH(win)); + pci_write_reg(chan, RES_TO_U32_HIGH(res->start), + SH4A_PCIEPARH(win)); + pci_write_reg(chan, RES_TO_U32_LOW(res->start), + SH4A_PCIEPARL(win)); - enable_mask = MASK_PARE; + mask = MASK_PARE; if (res->flags & IORESOURCE_IO) - enable_mask |= MASK_SPC; + mask |= MASK_SPC; - pci_write_reg(chan, enable_mask, SH4A_PCIEPTCTLR(win)); + pci_write_reg(chan, mask, SH4A_PCIEPTCTLR(win)); win++; } diff --git a/arch/sh/drivers/pci/pcie-sh7786.h b/arch/sh/drivers/pci/pcie-sh7786.h index 1ee054e..a2a0ca6 100644 --- a/arch/sh/drivers/pci/pcie-sh7786.h +++ b/arch/sh/drivers/pci/pcie-sh7786.h @@ -568,6 +568,13 @@ #define PCI_REG(x) ((x) + 0x40000) +#define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL)) +#define U64_TO_U32_HIGH(val) ((u32)((val) >> 32)) +#define RES_TO_U32_LOW(val) \ + ((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_LOW(val) : (val)) +#define RES_TO_U32_HIGH(val) \ + ((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_HIGH(val) : (0)) + static inline void pci_write_reg(struct pci_channel *chan, unsigned long val, unsigned long reg) { -- cgit v1.1 From c524ebf5a6b78d25219d64a05b3876cde719b5ff Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Mon, 20 Sep 2010 18:45:11 +0900 Subject: sh: pci: clock framework support for SH7786 PCIe. This gets each port handling its MSTP bit, as well as moving the PHY clock management in to the clock framework. Signed-off-by: Paul Mundt --- arch/sh/drivers/pci/pcie-sh7786.c | 107 ++++++++++++++++++++++++++++++-------- 1 file changed, 86 insertions(+), 21 deletions(-) (limited to 'arch') diff --git a/arch/sh/drivers/pci/pcie-sh7786.c b/arch/sh/drivers/pci/pcie-sh7786.c index b0ef380..8ec4af1 100644 --- a/arch/sh/drivers/pci/pcie-sh7786.c +++ b/arch/sh/drivers/pci/pcie-sh7786.c @@ -13,11 +13,15 @@ #include #include #include +#include +#include #include "pcie-sh7786.h" #include +#include struct sh7786_pcie_port { struct pci_channel *hose; + struct clk *fclk, phy_clk; unsigned int index; int endpoint; int link; @@ -121,6 +125,10 @@ static struct pci_channel sh7786_pci_channels[] = { DEFINE_CONTROLLER(0xfcc00000, 2), }; +static struct clk fixed_pciexclkp = { + .rate = 100000000, /* 100 MHz reference clock */ +}; + static void __devinit sh7786_pci_fixup(struct pci_dev *dev) { /* @@ -139,7 +147,7 @@ static void __devinit sh7786_pci_fixup(struct pci_dev *dev) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_SH7786, sh7786_pci_fixup); -static int phy_wait_for_ack(struct pci_channel *chan) +static int __init phy_wait_for_ack(struct pci_channel *chan) { unsigned int timeout = 100; @@ -153,7 +161,7 @@ static int phy_wait_for_ack(struct pci_channel *chan) return -ETIMEDOUT; } -static int pci_wait_for_irq(struct pci_channel *chan, unsigned int mask) +static int __init pci_wait_for_irq(struct pci_channel *chan, unsigned int mask) { unsigned int timeout = 100; @@ -167,8 +175,8 @@ static int pci_wait_for_irq(struct pci_channel *chan, unsigned int mask) return -ETIMEDOUT; } -static void phy_write_reg(struct pci_channel *chan, unsigned int addr, - unsigned int lane, unsigned int data) +static void __init phy_write_reg(struct pci_channel *chan, unsigned int addr, + unsigned int lane, unsigned int data) { unsigned long phyaddr; @@ -188,15 +196,67 @@ static void phy_write_reg(struct pci_channel *chan, unsigned int addr, phy_wait_for_ack(chan); } -static int phy_init(struct pci_channel *chan) +static int __init pcie_clk_init(struct sh7786_pcie_port *port) +{ + struct pci_channel *chan = port->hose; + struct clk *clk; + char fclk_name[16]; + int ret; + + /* + * First register the fixed clock + */ + ret = clk_register(&fixed_pciexclkp); + if (unlikely(ret != 0)) + return ret; + + /* + * Grab the port's function clock, which the PHY clock depends + * on. clock lookups don't help us much at this point, since no + * dev_id is available this early. Lame. + */ + snprintf(fclk_name, sizeof(fclk_name), "pcie%d_fck", port->index); + + port->fclk = clk_get(NULL, fclk_name); + if (IS_ERR(port->fclk)) { + ret = PTR_ERR(port->fclk); + goto err_fclk; + } + + clk_enable(port->fclk); + + /* + * And now, set up the PHY clock + */ + clk = &port->phy_clk; + + memset(clk, 0, sizeof(struct clk)); + + clk->parent = &fixed_pciexclkp; + clk->enable_reg = (void __iomem *)(chan->reg_base + SH4A_PCIEPHYCTLR); + clk->enable_bit = BITS_CKE; + + ret = sh_clk_mstp32_register(clk, 1); + if (unlikely(ret < 0)) + goto err_phy; + + return 0; + +err_phy: + clk_disable(port->fclk); + clk_put(port->fclk); +err_fclk: + clk_unregister(&fixed_pciexclkp); + + return ret; +} + +static int __init phy_init(struct sh7786_pcie_port *port) { - unsigned long ctrl; + struct pci_channel *chan = port->hose; unsigned int timeout = 100; - /* Enable clock */ - ctrl = pci_read_reg(chan, SH4A_PCIEPHYCTLR); - ctrl |= (1 << BITS_CKE); - pci_write_reg(chan, ctrl, SH4A_PCIEPHYCTLR); + clk_enable(&port->phy_clk); /* Initialize the phy */ phy_write_reg(chan, 0x60, 0xf, 0x004b008b); @@ -212,9 +272,7 @@ static int phy_init(struct pci_channel *chan) phy_write_reg(chan, 0x67, 0x1, 0x00000400); /* Disable clock */ - ctrl = pci_read_reg(chan, SH4A_PCIEPHYCTLR); - ctrl &= ~(1 << BITS_CKE); - pci_write_reg(chan, ctrl, SH4A_PCIEPHYCTLR); + clk_disable(&port->phy_clk); while (timeout--) { if (pci_read_reg(chan, SH4A_PCIEPHYSR)) @@ -226,7 +284,7 @@ static int phy_init(struct pci_channel *chan) return -ETIMEDOUT; } -static void pcie_reset(struct sh7786_pcie_port *port) +static void __init pcie_reset(struct sh7786_pcie_port *port) { struct pci_channel *chan = port->hose; @@ -236,7 +294,7 @@ static void pcie_reset(struct sh7786_pcie_port *port) pci_write_reg(chan, 0, SH4A_PCIETXVC0SR); } -static int pcie_init(struct sh7786_pcie_port *port) +static int __init pcie_init(struct sh7786_pcie_port *port) { struct pci_channel *chan = port->hose; unsigned int data; @@ -411,26 +469,33 @@ int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin) return 71; } -static int sh7786_pcie_core_init(void) +static int __init sh7786_pcie_core_init(void) { /* Return the number of ports */ return test_mode_pin(MODE_PIN12) ? 3 : 2; } -static int __devinit sh7786_pcie_init_hw(struct sh7786_pcie_port *port) +static int __init sh7786_pcie_init_hw(struct sh7786_pcie_port *port) { int ret; - ret = phy_init(port->hose); - if (unlikely(ret < 0)) - return ret; - /* * Check if we are configured in endpoint or root complex mode, * this is a fixed pin setting that applies to all PCIe ports. */ port->endpoint = test_mode_pin(MODE_PIN11); + /* + * Setup clocks, needed both for PHY and PCIe registers. + */ + ret = pcie_clk_init(port); + if (unlikely(ret < 0)) + return ret; + + ret = phy_init(port); + if (unlikely(ret < 0)) + return ret; + ret = pcie_init(port); if (unlikely(ret < 0)) return ret; -- cgit v1.1 From 39a90865f07f05343c450e91a56578bb8f69c5e8 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Mon, 20 Sep 2010 18:56:13 +0900 Subject: sh: pci: Use a generic raw spinlock for PCI config access locking. This copies the pci_config_lock idea from x86 over, allowing us to kill off a couple of existing private locks. At the same time, these need to be converted to raw spinlocks for -rt kernels, so we make that change at the same time. This should make it easier for future parts to get the locking right instead of inevitable ending up with lock type mismatches. Signed-off-by: Paul Mundt --- arch/sh/drivers/pci/ops-sh4.c | 11 +++++------ arch/sh/drivers/pci/ops-sh7786.c | 10 ++++------ arch/sh/drivers/pci/pci.c | 6 ++++++ arch/sh/include/asm/pci.h | 2 ++ 4 files changed, 17 insertions(+), 12 deletions(-) (limited to 'arch') diff --git a/arch/sh/drivers/pci/ops-sh4.c b/arch/sh/drivers/pci/ops-sh4.c index 0b81999..b623420 100644 --- a/arch/sh/drivers/pci/ops-sh4.c +++ b/arch/sh/drivers/pci/ops-sh4.c @@ -9,6 +9,7 @@ */ #include #include +#include #include #include "pci-sh4.h" @@ -18,8 +19,6 @@ #define CONFIG_CMD(bus, devfn, where) \ (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3)) -static DEFINE_SPINLOCK(sh4_pci_lock); - /* * Functions for accessing PCI configuration space with type 1 accesses */ @@ -34,10 +33,10 @@ static int sh4_pci_read(struct pci_bus *bus, unsigned int devfn, * PCIPDR may only be accessed as 32 bit words, * so we must do byte alignment by hand */ - spin_lock_irqsave(&sh4_pci_lock, flags); + raw_spin_lock_irqsave(&pci_config_lock, flags); pci_write_reg(chan, CONFIG_CMD(bus, devfn, where), SH4_PCIPAR); data = pci_read_reg(chan, SH4_PCIPDR); - spin_unlock_irqrestore(&sh4_pci_lock, flags); + raw_spin_unlock_irqrestore(&pci_config_lock, flags); switch (size) { case 1: @@ -69,10 +68,10 @@ static int sh4_pci_write(struct pci_bus *bus, unsigned int devfn, int shift; u32 data; - spin_lock_irqsave(&sh4_pci_lock, flags); + raw_spin_lock_irqsave(&pci_config_lock, flags); pci_write_reg(chan, CONFIG_CMD(bus, devfn, where), SH4_PCIPAR); data = pci_read_reg(chan, SH4_PCIPDR); - spin_unlock_irqrestore(&sh4_pci_lock, flags); + raw_spin_unlock_irqrestore(&pci_config_lock, flags); switch (size) { case 1: diff --git a/arch/sh/drivers/pci/ops-sh7786.c b/arch/sh/drivers/pci/ops-sh7786.c index 01cb70f..1284210 100644 --- a/arch/sh/drivers/pci/ops-sh7786.c +++ b/arch/sh/drivers/pci/ops-sh7786.c @@ -19,8 +19,6 @@ enum { PCI_ACCESS_WRITE, }; -static DEFINE_SPINLOCK(sh7786_pcie_lock); - static int sh7786_pcie_config_access(unsigned char access_type, struct pci_bus *bus, unsigned int devfn, int where, u32 *data) { @@ -103,7 +101,7 @@ static int sh7786_pcie_read(struct pci_bus *bus, unsigned int devfn, else if ((size == 4) && (where & 3)) return PCIBIOS_BAD_REGISTER_NUMBER; - spin_lock_irqsave(&sh7786_pcie_lock, flags); + raw_spin_lock_irqsave(&pci_config_lock, flags); ret = sh7786_pcie_config_access(PCI_ACCESS_READ, bus, devfn, where, &data); if (ret != PCIBIOS_SUCCESSFUL) { @@ -123,7 +121,7 @@ static int sh7786_pcie_read(struct pci_bus *bus, unsigned int devfn, devfn, where, size, (unsigned long)*val); out: - spin_unlock_irqrestore(&sh7786_pcie_lock, flags); + raw_spin_unlock_irqrestore(&pci_config_lock, flags); return ret; } @@ -139,7 +137,7 @@ static int sh7786_pcie_write(struct pci_bus *bus, unsigned int devfn, else if ((size == 4) && (where & 3)) return PCIBIOS_BAD_REGISTER_NUMBER; - spin_lock_irqsave(&sh7786_pcie_lock, flags); + raw_spin_lock_irqsave(&pci_config_lock, flags); ret = sh7786_pcie_config_access(PCI_ACCESS_READ, bus, devfn, where, &data); if (ret != PCIBIOS_SUCCESSFUL) @@ -163,7 +161,7 @@ static int sh7786_pcie_write(struct pci_bus *bus, unsigned int devfn, ret = sh7786_pcie_config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data); out: - spin_unlock_irqrestore(&sh7786_pcie_lock, flags); + raw_spin_unlock_irqrestore(&pci_config_lock, flags); return ret; } diff --git a/arch/sh/drivers/pci/pci.c b/arch/sh/drivers/pci/pci.c index e4c988d..af4191b 100644 --- a/arch/sh/drivers/pci/pci.c +++ b/arch/sh/drivers/pci/pci.c @@ -19,6 +19,7 @@ #include #include #include +#include unsigned long PCIBIOS_MIN_IO = 0x0000; unsigned long PCIBIOS_MIN_MEM = 0; @@ -56,6 +57,11 @@ static void __devinit pcibios_scanbus(struct pci_channel *hose) } } +/* + * This interrupt-safe spinlock protects all accesses to PCI + * configuration space. + */ +DEFINE_RAW_SPINLOCK(pci_config_lock); static DEFINE_MUTEX(pci_scan_mutex); int __devinit register_pci_controller(struct pci_channel *hose) diff --git a/arch/sh/include/asm/pci.h b/arch/sh/include/asm/pci.h index 8bd952f..f0efe97f 100644 --- a/arch/sh/include/asm/pci.h +++ b/arch/sh/include/asm/pci.h @@ -37,6 +37,8 @@ struct pci_channel { }; /* arch/sh/drivers/pci/pci.c */ +extern raw_spinlock_t pci_config_lock; + extern int register_pci_controller(struct pci_channel *hose); extern void pcibios_report_status(unsigned int status_mask, int warn); -- cgit v1.1 From c3083411062106452649e464e55c7b856de0d29b Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 20 Sep 2010 14:53:15 -0700 Subject: omap: Fix CONFIG_LOCAL_TIMERS initialization for multi-omap Fix CONFIG_LOCAL_TIMERS initialization for multi-omap Signed-off-by: Tony Lindgren Acked-By: Santosh Shilimkar --- arch/arm/mach-omap2/timer-gp.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c index 74fbed8..5a3e606 100644 --- a/arch/arm/mach-omap2/timer-gp.c +++ b/arch/arm/mach-omap2/timer-gp.c @@ -228,8 +228,10 @@ static void __init omap2_gp_clocksource_init(void) static void __init omap2_gp_timer_init(void) { #ifdef CONFIG_LOCAL_TIMERS - twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256); - BUG_ON(!twd_base); + if (cpu_is_omap44xx()) { + twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256); + BUG_ON(!twd_base); + } #endif omap_dm_timer_init(); -- cgit v1.1 From 61e9beafdd6f2b2d27ad5935a2de9c46709b9671 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 20 Sep 2010 14:53:38 -0700 Subject: omap: Update omap3_defconfig to work with SMP_ON_UP With the recent changes to core ARM kernel code, we can now boot SMP kernel on UP systems. Update omap3_defconfig to enable SMP. This allows us to remove omap_4430sdp_defconfig. In addition to enabling SMP, we also need to disable some options to make the system boot: - For some reason LOCK_STAT causes tons of WARNING: at mm/percpu-vm.c:320 pcpu_alloc+0x2fc/0x888() so disable it for now. - MUSB init fails for multi-omap, disable it for now. - LOCAL_TIMERS hangs on omap4, disable it for now. Also disable DEBUG_LL as this should be only enabled for debugging. Signed-off-by: Tony Lindgren --- arch/arm/configs/omap3_defconfig | 11 +-- arch/arm/configs/omap_4430sdp_defconfig | 125 -------------------------------- 2 files changed, 6 insertions(+), 130 deletions(-) delete mode 100644 arch/arm/configs/omap_4430sdp_defconfig (limited to 'arch') diff --git a/arch/arm/configs/omap3_defconfig b/arch/arm/configs/omap3_defconfig index 5db9a6b..833a9bc 100644 --- a/arch/arm/configs/omap3_defconfig +++ b/arch/arm/configs/omap3_defconfig @@ -55,6 +55,8 @@ CONFIG_MACH_OMAP_4430SDP=y CONFIG_ARM_THUMBEE=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y +CONFIG_SMP=y +# CONFIG_LOCAL_TIMERS is not set CONFIG_AEABI=y CONFIG_LEDS=y CONFIG_ZBOOT_ROM_TEXT=0x0 @@ -218,9 +220,9 @@ CONFIG_USB_DEVICEFS=y CONFIG_USB_SUSPEND=y # CONFIG_USB_OTG_WHITELIST is not set CONFIG_USB_MON=y -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_OTG=y -CONFIG_USB_GADGET_MUSB_HDRC=y +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_MUSB_OTG is not set +# CONFIG_USB_GADGET_MUSB_HDRC is not set CONFIG_USB_MUSB_DEBUG=y CONFIG_USB_WDM=y CONFIG_USB_STORAGE=y @@ -276,12 +278,11 @@ CONFIG_DEBUG_KERNEL=y CONFIG_SCHEDSTATS=y CONFIG_TIMER_STATS=y CONFIG_PROVE_LOCKING=y -CONFIG_LOCK_STAT=y +# CONFIG_LOCK_STAT is not set CONFIG_DEBUG_SPINLOCK_SLEEP=y # CONFIG_DEBUG_BUGVERBOSE is not set CONFIG_DEBUG_INFO=y # CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_DEBUG_LL=y CONFIG_SECURITY=y CONFIG_CRYPTO_MICHAEL_MIC=y # CONFIG_CRYPTO_ANSI_CPRNG is not set diff --git a/arch/arm/configs/omap_4430sdp_defconfig b/arch/arm/configs/omap_4430sdp_defconfig deleted file mode 100644 index 14c1e18..0000000 --- a/arch/arm/configs/omap_4430sdp_defconfig +++ /dev/null @@ -1,125 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y -# CONFIG_SYSCTL_SYSCALL is not set -# CONFIG_ELF_CORE is not set -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_ARCH_OMAP=y -CONFIG_ARCH_OMAP4=y -# CONFIG_ARCH_OMAP2PLUS_TYPICAL is not set -# CONFIG_ARCH_OMAP2 is not set -# CONFIG_ARCH_OMAP3 is not set -# CONFIG_OMAP_MUX is not set -CONFIG_OMAP_32K_TIMER=y -CONFIG_OMAP_DM_TIMER=y -CONFIG_MACH_OMAP_4430SDP=y -# CONFIG_ARM_THUMB is not set -CONFIG_PL310_ERRATA_588369=y -CONFIG_SMP=y -CONFIG_NR_CPUS=2 -# CONFIG_LOCAL_TIMERS is not set -CONFIG_PREEMPT=y -CONFIG_AEABI=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="root=/dev/ram0 rw mem=128M console=ttyS2,115200n8 initrd=0x81600000,20M ramdisk_size=20480" -CONFIG_VFP=y -CONFIG_NEON=y -CONFIG_BINFMT_MISC=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_IPV6 is not set -# CONFIG_WIRELESS is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_FW_LOADER is not set -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=16384 -# CONFIG_MISC_DEVICES is not set -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_KS8851=y -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_WLAN is not set -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=32 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_DETECT_IRQ=y -CONFIG_SERIAL_8250_RSA=y -# CONFIG_LEGACY_PTYS is not set -CONFIG_HW_RANDOM=y -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_OMAP=y -CONFIG_SPI=y -CONFIG_SPI_OMAP24XX=y -# CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -CONFIG_OMAP_WATCHDOG=y -CONFIG_TWL4030_CORE=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_TWL4030=y -# CONFIG_VGA_CONSOLE is not set -# CONFIG_HID_SUPPORT is not set -# CONFIG_USB_SUPPORT is not set -CONFIG_MMC=y -CONFIG_MMC_OMAP_HS=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_TWL4030=y -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -# CONFIG_EXT3_FS_XATTR is not set -CONFIG_INOTIFY=y -CONFIG_QUOTA=y -CONFIG_QFMT_V2=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V3_ACL=y -CONFIG_NFS_V4=y -CONFIG_ROOT_NFS=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -# CONFIG_ENABLE_WARN_DEPRECATED is not set -# CONFIG_ENABLE_MUST_CHECK is not set -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_KERNEL=y -# CONFIG_DETECT_SOFTLOCKUP is not set -CONFIG_DETECT_HUNG_TASK=y -# CONFIG_SCHED_DEBUG is not set -# CONFIG_DEBUG_PREEMPT is not set -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_FTRACE is not set -# CONFIG_ARM_UNWIND is not set -CONFIG_CRYPTO_ECB=m -CONFIG_CRYPTO_PCBC=m -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRC_CCITT=y -CONFIG_CRC_T10DIF=y -CONFIG_LIBCRC32C=y -- cgit v1.1 From 455d4d2dc76471baec0c70daf8ff6c09fc743c24 Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Wed, 15 Sep 2010 22:40:19 +0530 Subject: omap: Update and rename common defconfig for omap2plus devices This patch addresses below things - Renaming existing omap3_defconfig which has OMAP2, OMAP3 and OMAP4 builds enabled to more appropriate name 'omap2plus_defconfig' - L1 cache shift is suppose to be 5 on OMAP4 where as it is 6 on previous OMAPs. Keeping it to 5 is safer option for OMAP4 and previous OMAPs. For OMAP3 only build the shift would be still 6 - Enable needed Errata's for OMAP4 to work with DMA based device drivers CONFIG_PL310_ERRATA_588369=y CONFIG_ARM_ERRATA_720789=y - Enable the Micrel ethernet controller CONFIG_KS8851=y CONFIG_KS8851_MLL=y With above three changes, OMAP4 ethernet, mmc etc works reliably. Signed-off-by: Santosh Shilimkar Signed-off-by: Tony Lindgren --- arch/arm/configs/omap2plus_defconfig | 296 +++++++++++++++++++++++++++++++++++ arch/arm/configs/omap3_defconfig | 293 ---------------------------------- arch/arm/mach-omap2/Kconfig | 4 +- 3 files changed, 299 insertions(+), 294 deletions(-) create mode 100644 arch/arm/configs/omap2plus_defconfig delete mode 100644 arch/arm/configs/omap3_defconfig (limited to 'arch') diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig new file mode 100644 index 0000000..3d27dd0 --- /dev/null +++ b/arch/arm/configs/omap2plus_defconfig @@ -0,0 +1,296 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_BLK_DEV_INITRD=y +CONFIG_EMBEDDED=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS_EXTRA_PASS=y +CONFIG_SLAB=y +CONFIG_PROFILING=y +CONFIG_OPROFILE=y +CONFIG_KPROBES=y +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_ARCH_OMAP=y +CONFIG_ARCH_OMAP2=y +CONFIG_ARCH_OMAP3=y +CONFIG_ARCH_OMAP4=y +CONFIG_OMAP_RESET_CLOCKS=y +CONFIG_OMAP_MUX_DEBUG=y +CONFIG_OMAP_32K_TIMER=y +CONFIG_MACH_OMAP_GENERIC=y +CONFIG_ARCH_OMAP2420=y +CONFIG_ARCH_OMAP2430=y +CONFIG_ARCH_OMAP3430=y +CONFIG_MACH_OMAP_H4=y +CONFIG_MACH_OMAP_APOLLON=y +CONFIG_MACH_OMAP_2430SDP=y +CONFIG_MACH_OMAP3_BEAGLE=y +CONFIG_MACH_DEVKIT8000=y +CONFIG_MACH_OMAP_LDP=y +CONFIG_MACH_OVERO=y +CONFIG_MACH_OMAP3EVM=y +CONFIG_MACH_OMAP3517EVM=y +CONFIG_MACH_OMAP3_PANDORA=y +CONFIG_MACH_OMAP3_TOUCHBOOK=y +CONFIG_MACH_OMAP_3430SDP=y +CONFIG_MACH_NOKIA_N8X0=y +CONFIG_MACH_NOKIA_RX51=y +CONFIG_MACH_OMAP_ZOOM2=y +CONFIG_MACH_OMAP_ZOOM3=y +CONFIG_MACH_CM_T35=y +CONFIG_MACH_IGEP0020=y +CONFIG_MACH_SBC3530=y +CONFIG_MACH_OMAP_3630SDP=y +CONFIG_MACH_OMAP_4430SDP=y +CONFIG_ARM_THUMBEE=y +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_SMP=y +# CONFIG_LOCAL_TIMERS is not set +CONFIG_AEABI=y +CONFIG_LEDS=y +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="root=/dev/mmcblk0p2 rootwait console=ttyS2,115200" +CONFIG_KEXEC=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT_DETAILS=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_FPE_NWFPE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_BINFMT_MISC=y +CONFIG_PM=y +CONFIG_PM_DEBUG=y +CONFIG_PM_RUNTIME=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM_USER=y +CONFIG_NET_KEY=y +CONFIG_NET_KEY_MIGRATE=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +# CONFIG_INET_LRO is not set +# CONFIG_IPV6 is not set +CONFIG_NETFILTER=y +CONFIG_BT=y +CONFIG_BT_L2CAP=y +CONFIG_BT_SCO=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=y +CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_H4=y +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_LL=y +CONFIG_BT_HCIBCM203X=y +CONFIG_BT_HCIBPA10X=y +CONFIG_CFG80211=y +CONFIG_MAC80211=y +CONFIG_MAC80211_RC_PID=y +CONFIG_MAC80211_RC_DEFAULT_PID=y +CONFIG_MAC80211_LEDS=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_CONNECTOR=y +CONFIG_MTD=y +CONFIG_MTD_CONCAT=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_OOPS=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_OMAP2=y +CONFIG_MTD_ONENAND=y +CONFIG_MTD_ONENAND_VERIFY_WRITE=y +CONFIG_MTD_ONENAND_OMAP2=y +CONFIG_MTD_UBI=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=16384 +CONFIG_EEPROM_LEGACY=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_MULTI_LUN=y +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_MD=y +CONFIG_NETDEVICES=y +CONFIG_SMSC_PHY=y +CONFIG_NET_ETHERNET=y +CONFIG_SMC91X=y +CONFIG_SMSC911X=y +CONFIG_KS8851=y +CONFIG_KS8851_MLL=y +CONFIG_LIBERTAS=y +CONFIG_LIBERTAS_USB=y +CONFIG_LIBERTAS_SDIO=y +CONFIG_LIBERTAS_DEBUG=y +CONFIG_USB_USBNET=y +CONFIG_USB_ALI_M5632=y +CONFIG_USB_AN2720=y +CONFIG_USB_EPSON2888=y +CONFIG_USB_KC2190=y +CONFIG_INPUT_JOYDEV=y +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_TWL4030=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADS7846=y +CONFIG_INPUT_MISC=y +CONFIG_INPUT_TWL4030_PWRBUTTON=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=32 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_DETECT_IRQ=y +CONFIG_SERIAL_8250_RSA=y +# CONFIG_LEGACY_PTYS is not set +CONFIG_HW_RANDOM=y +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_OMAP=y +CONFIG_SPI=y +CONFIG_SPI_OMAP24XX=y +CONFIG_DEBUG_GPIO=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_TWL4030=y +CONFIG_W1=y +CONFIG_POWER_SUPPLY=y +CONFIG_WATCHDOG=y +CONFIG_OMAP_WATCHDOG=y +CONFIG_TWL4030_WATCHDOG=y +CONFIG_MENELAUS=y +CONFIG_TWL4030_CORE=y +CONFIG_TWL4030_POWER=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_TWL4030=y +CONFIG_REGULATOR_TPS65023=y +CONFIG_REGULATOR_TPS6507X=y +CONFIG_FB=y +CONFIG_FIRMWARE_EDID=y +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_TILEBLITTING=y +CONFIG_FB_OMAP_LCD_VGA=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_LCD_PLATFORM=y +CONFIG_DISPLAY_SUPPORT=y +# CONFIG_VGA_CONSOLE is not set +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_MIXER_OSS=y +CONFIG_SND_PCM_OSS=y +CONFIG_SND_VERBOSE_PRINTK=y +CONFIG_SND_DEBUG=y +CONFIG_SND_USB_AUDIO=y +CONFIG_SND_SOC=y +CONFIG_SND_OMAP_SOC=y +CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=y +CONFIG_USB=y +CONFIG_USB_DEBUG=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_DEVICEFS=y +CONFIG_USB_SUSPEND=y +# CONFIG_USB_OTG_WHITELIST is not set +CONFIG_USB_MON=y +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_MUSB_OTG is not set +# CONFIG_USB_GADGET_MUSB_HDRC is not set +CONFIG_USB_MUSB_DEBUG=y +CONFIG_USB_WDM=y +CONFIG_USB_STORAGE=y +CONFIG_USB_LIBUSUAL=y +CONFIG_USB_TEST=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DEBUG=y +CONFIG_USB_GADGET_DEBUG_FILES=y +CONFIG_USB_GADGET_DEBUG_FS=y +CONFIG_USB_ZERO=m +CONFIG_MMC=y +CONFIG_MMC_UNSAFE_RESUME=y +CONFIG_SDIO_UART=y +CONFIG_MMC_OMAP=y +CONFIG_MMC_OMAP_HS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_TWL92330=y +CONFIG_RTC_DRV_TWL4030=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +CONFIG_INOTIFY=y +CONFIG_QUOTA=y +CONFIG_QFMT_V2=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_SUMMARY=y +CONFIG_JFFS2_FS_XATTR=y +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_LZO=y +CONFIG_JFFS2_RUBIN=y +CONFIG_UBIFS_FS=y +CONFIG_CRAMFS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_ROOT_NFS=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_PRINTK_TIME=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_KERNEL=y +CONFIG_SCHEDSTATS=y +CONFIG_TIMER_STATS=y +CONFIG_PROVE_LOCKING=y +# CONFIG_LOCK_STAT is not set +CONFIG_DEBUG_SPINLOCK_SLEEP=y +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_INFO=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +CONFIG_SECURITY=y +CONFIG_CRYPTO_MICHAEL_MIC=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRC_CCITT=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC_ITU_T=y +CONFIG_CRC7=y +CONFIG_LIBCRC32C=y diff --git a/arch/arm/configs/omap3_defconfig b/arch/arm/configs/omap3_defconfig deleted file mode 100644 index 833a9bc..0000000 --- a/arch/arm/configs/omap3_defconfig +++ /dev/null @@ -1,293 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=16 -CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_KALLSYMS_EXTRA_PASS=y -CONFIG_SLAB=y -CONFIG_PROFILING=y -CONFIG_OPROFILE=y -CONFIG_KPROBES=y -CONFIG_MODULES=y -CONFIG_MODULE_FORCE_LOAD=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_ARCH_OMAP=y -CONFIG_ARCH_OMAP2=y -CONFIG_ARCH_OMAP3=y -CONFIG_ARCH_OMAP4=y -CONFIG_OMAP_RESET_CLOCKS=y -CONFIG_OMAP_MUX_DEBUG=y -CONFIG_OMAP_32K_TIMER=y -CONFIG_MACH_OMAP_GENERIC=y -CONFIG_ARCH_OMAP2420=y -CONFIG_ARCH_OMAP2430=y -CONFIG_ARCH_OMAP3430=y -CONFIG_MACH_OMAP_H4=y -CONFIG_MACH_OMAP_APOLLON=y -CONFIG_MACH_OMAP_2430SDP=y -CONFIG_MACH_OMAP3_BEAGLE=y -CONFIG_MACH_DEVKIT8000=y -CONFIG_MACH_OMAP_LDP=y -CONFIG_MACH_OVERO=y -CONFIG_MACH_OMAP3EVM=y -CONFIG_MACH_OMAP3517EVM=y -CONFIG_MACH_OMAP3_PANDORA=y -CONFIG_MACH_OMAP3_TOUCHBOOK=y -CONFIG_MACH_OMAP_3430SDP=y -CONFIG_MACH_NOKIA_N8X0=y -CONFIG_MACH_NOKIA_RX51=y -CONFIG_MACH_OMAP_ZOOM2=y -CONFIG_MACH_OMAP_ZOOM3=y -CONFIG_MACH_CM_T35=y -CONFIG_MACH_IGEP0020=y -CONFIG_MACH_SBC3530=y -CONFIG_MACH_OMAP_3630SDP=y -CONFIG_MACH_OMAP_4430SDP=y -CONFIG_ARM_THUMBEE=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_SMP=y -# CONFIG_LOCAL_TIMERS is not set -CONFIG_AEABI=y -CONFIG_LEDS=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="root=/dev/mmcblk0p2 rootwait console=ttyS2,115200" -CONFIG_KEXEC=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_STAT_DETAILS=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_FPE_NWFPE=y -CONFIG_VFP=y -CONFIG_NEON=y -CONFIG_BINFMT_MISC=y -CONFIG_PM=y -CONFIG_PM_DEBUG=y -CONFIG_PM_RUNTIME=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_XFRM_USER=y -CONFIG_NET_KEY=y -CONFIG_NET_KEY_MIGRATE=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_INET_LRO is not set -# CONFIG_IPV6 is not set -CONFIG_NETFILTER=y -CONFIG_BT=y -CONFIG_BT_L2CAP=y -CONFIG_BT_SCO=y -CONFIG_BT_RFCOMM=y -CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_BNEP=y -CONFIG_BT_BNEP_MC_FILTER=y -CONFIG_BT_BNEP_PROTO_FILTER=y -CONFIG_BT_HIDP=y -CONFIG_BT_HCIUART=y -CONFIG_BT_HCIUART_H4=y -CONFIG_BT_HCIUART_BCSP=y -CONFIG_BT_HCIUART_LL=y -CONFIG_BT_HCIBCM203X=y -CONFIG_BT_HCIBPA10X=y -CONFIG_CFG80211=y -CONFIG_MAC80211=y -CONFIG_MAC80211_RC_PID=y -CONFIG_MAC80211_RC_DEFAULT_PID=y -CONFIG_MAC80211_LEDS=y -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_CONNECTOR=y -CONFIG_MTD=y -CONFIG_MTD_CONCAT=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_OOPS=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_OMAP2=y -CONFIG_MTD_ONENAND=y -CONFIG_MTD_ONENAND_VERIFY_WRITE=y -CONFIG_MTD_ONENAND_OMAP2=y -CONFIG_MTD_UBI=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=16384 -CONFIG_EEPROM_LEGACY=y -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_SCSI_MULTI_LUN=y -CONFIG_SCSI_SCAN_ASYNC=y -CONFIG_MD=y -CONFIG_NETDEVICES=y -CONFIG_SMSC_PHY=y -CONFIG_NET_ETHERNET=y -CONFIG_SMC91X=y -CONFIG_SMSC911X=y -CONFIG_LIBERTAS=y -CONFIG_LIBERTAS_USB=y -CONFIG_LIBERTAS_SDIO=y -CONFIG_LIBERTAS_DEBUG=y -CONFIG_USB_USBNET=y -CONFIG_USB_ALI_M5632=y -CONFIG_USB_AN2720=y -CONFIG_USB_EPSON2888=y -CONFIG_USB_KC2190=y -CONFIG_INPUT_JOYDEV=y -CONFIG_INPUT_EVDEV=y -CONFIG_KEYBOARD_GPIO=y -CONFIG_KEYBOARD_TWL4030=y -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ADS7846=y -CONFIG_INPUT_MISC=y -CONFIG_INPUT_TWL4030_PWRBUTTON=y -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=32 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_DETECT_IRQ=y -CONFIG_SERIAL_8250_RSA=y -# CONFIG_LEGACY_PTYS is not set -CONFIG_HW_RANDOM=y -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_OMAP=y -CONFIG_SPI=y -CONFIG_SPI_OMAP24XX=y -CONFIG_DEBUG_GPIO=y -CONFIG_GPIO_SYSFS=y -CONFIG_GPIO_TWL4030=y -CONFIG_W1=y -CONFIG_POWER_SUPPLY=y -CONFIG_WATCHDOG=y -CONFIG_OMAP_WATCHDOG=y -CONFIG_TWL4030_WATCHDOG=y -CONFIG_MENELAUS=y -CONFIG_TWL4030_CORE=y -CONFIG_TWL4030_POWER=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_TWL4030=y -CONFIG_REGULATOR_TPS65023=y -CONFIG_REGULATOR_TPS6507X=y -CONFIG_FB=y -CONFIG_FIRMWARE_EDID=y -CONFIG_FB_MODE_HELPERS=y -CONFIG_FB_TILEBLITTING=y -CONFIG_FB_OMAP_LCD_VGA=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y -CONFIG_LCD_CLASS_DEVICE=y -CONFIG_LCD_PLATFORM=y -CONFIG_DISPLAY_SUPPORT=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -CONFIG_FONTS=y -CONFIG_FONT_8x8=y -CONFIG_FONT_8x16=y -CONFIG_LOGO=y -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_SND_MIXER_OSS=y -CONFIG_SND_PCM_OSS=y -CONFIG_SND_VERBOSE_PRINTK=y -CONFIG_SND_DEBUG=y -CONFIG_SND_USB_AUDIO=y -CONFIG_SND_SOC=y -CONFIG_SND_OMAP_SOC=y -CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=y -CONFIG_USB=y -CONFIG_USB_DEBUG=y -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -CONFIG_USB_DEVICEFS=y -CONFIG_USB_SUSPEND=y -# CONFIG_USB_OTG_WHITELIST is not set -CONFIG_USB_MON=y -# CONFIG_USB_MUSB_HDRC is not set -# CONFIG_USB_MUSB_OTG is not set -# CONFIG_USB_GADGET_MUSB_HDRC is not set -CONFIG_USB_MUSB_DEBUG=y -CONFIG_USB_WDM=y -CONFIG_USB_STORAGE=y -CONFIG_USB_LIBUSUAL=y -CONFIG_USB_TEST=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_DEBUG=y -CONFIG_USB_GADGET_DEBUG_FILES=y -CONFIG_USB_GADGET_DEBUG_FS=y -CONFIG_USB_ZERO=m -CONFIG_MMC=y -CONFIG_MMC_UNSAFE_RESUME=y -CONFIG_SDIO_UART=y -CONFIG_MMC_OMAP=y -CONFIG_MMC_OMAP_HS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_TRIGGER_TIMER=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_LEDS_TRIGGER_DEFAULT_ON=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_TWL92330=y -CONFIG_RTC_DRV_TWL4030=y -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -# CONFIG_EXT3_FS_XATTR is not set -CONFIG_INOTIFY=y -CONFIG_QUOTA=y -CONFIG_QFMT_V2=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_SUMMARY=y -CONFIG_JFFS2_FS_XATTR=y -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_JFFS2_LZO=y -CONFIG_JFFS2_RUBIN=y -CONFIG_UBIFS_FS=y -CONFIG_CRAMFS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V3_ACL=y -CONFIG_NFS_V4=y -CONFIG_ROOT_NFS=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_PRINTK_TIME=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_FS=y -CONFIG_DEBUG_KERNEL=y -CONFIG_SCHEDSTATS=y -CONFIG_TIMER_STATS=y -CONFIG_PROVE_LOCKING=y -# CONFIG_LOCK_STAT is not set -CONFIG_DEBUG_SPINLOCK_SLEEP=y -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_SECURITY=y -CONFIG_CRYPTO_MICHAEL_MIC=y -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRC_CCITT=y -CONFIG_CRC_T10DIF=y -CONFIG_CRC_ITU_T=y -CONFIG_CRC7=y -CONFIG_LIBCRC32C=y diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index b48bacf..bb85f24 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -35,7 +35,7 @@ config ARCH_OMAP3 default y select CPU_V7 select USB_ARCH_HAS_EHCI - select ARM_L1_CACHE_SHIFT_6 + select ARM_L1_CACHE_SHIFT_6 if !ARCH_OMAP4 config ARCH_OMAP4 bool "TI OMAP4" @@ -43,6 +43,8 @@ config ARCH_OMAP4 depends on ARCH_OMAP2PLUS select CPU_V7 select ARM_GIC + select PL310_ERRATA_588369 + select ARM_ERRATA_720789 comment "OMAP Core Type" depends on ARCH_OMAP2 -- cgit v1.1 From d31f59f31d602e8c3a34ce1f20d1e8fcfe50dd59 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 20 Sep 2010 14:53:38 -0700 Subject: omap: Update omap3_defconfig for omap2 We need to enable ARM_ERRATA_411920 for omap2 and remove the omap2 specific defconfigs. Signed-off-by: Tony Lindgren --- arch/arm/configs/n8x0_defconfig | 94 ---------------------------- arch/arm/configs/omap2plus_defconfig | 1 + arch/arm/configs/omap_generic_2420_defconfig | 37 ----------- 3 files changed, 1 insertion(+), 131 deletions(-) delete mode 100644 arch/arm/configs/n8x0_defconfig delete mode 100644 arch/arm/configs/omap_generic_2420_defconfig (limited to 'arch') diff --git a/arch/arm/configs/n8x0_defconfig b/arch/arm/configs/n8x0_defconfig deleted file mode 100644 index 56aebb6..0000000 --- a/arch/arm/configs/n8x0_defconfig +++ /dev/null @@ -1,94 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_LBDAF is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_IOSCHED_DEADLINE is not set -CONFIG_ARCH_OMAP=y -CONFIG_ARCH_OMAP2=y -CONFIG_OMAP_RESET_CLOCKS=y -# CONFIG_OMAP_MUX is not set -# CONFIG_OMAP_MCBSP is not set -CONFIG_OMAP_MBOX_FWK=y -CONFIG_OMAP_32K_TIMER=y -CONFIG_ARCH_OMAP2420=y -CONFIG_MACH_NOKIA_N8X0=y -CONFIG_AEABI=y -CONFIG_LEDS=y -CONFIG_ZBOOT_ROM_TEXT=0x10C08000 -CONFIG_ZBOOT_ROM_BSS=0x10200000 -CONFIG_CMDLINE="root=/dev/mmcblk0p2 console=ttyS2,115200n8 debug earlyprintk rootwait" -CONFIG_FPE_NWFPE=y -CONFIG_VFP=y -CONFIG_PM=y -CONFIG_PM_RUNTIME=y -CONFIG_NET=y -CONFIG_UNIX=y -CONFIG_INET=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set -# CONFIG_IPV6 is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_ONENAND=y -CONFIG_MTD_ONENAND_OMAP2=y -CONFIG_MTD_ONENAND_OTP=y -CONFIG_BLK_DEV_RAM=y -# CONFIG_MISC_DEVICES is not set -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y -# CONFIG_I2C_COMPAT is not set -# CONFIG_I2C_HELPER_AUTO is not set -CONFIG_I2C_OMAP=y -CONFIG_SPI=y -CONFIG_SPI_OMAP24XX=y -# CONFIG_HWMON is not set -CONFIG_MENELAUS=y -CONFIG_REGULATOR=y -# CONFIG_VGA_CONSOLE is not set -# CONFIG_HID_SUPPORT is not set -CONFIG_USB=y -CONFIG_USB_DEBUG=y -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -CONFIG_USB_DEVICEFS=y -CONFIG_USB_SUSPEND=y -# CONFIG_USB_OTG_WHITELIST is not set -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_OTG=y -CONFIG_USB_GADGET_MUSB_HDRC=y -# CONFIG_MUSB_PIO_ONLY is not set -CONFIG_USB_MUSB_DEBUG=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_DEBUG=y -CONFIG_USB_GADGET_DEBUG_FILES=y -CONFIG_USB_ETH=m -CONFIG_USB_ETH_EEM=y -CONFIG_MMC=y -CONFIG_MMC_OMAP=y -CONFIG_EXT3_FS=y -CONFIG_INOTIFY=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_SUMMARY=y -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_JFFS2_LZO=y -CONFIG_PRINTK_TIME=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_INFO=y -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y -CONFIG_CRC_CCITT=y diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index 3d27dd0..9ca8df0 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -54,6 +54,7 @@ CONFIG_MACH_OMAP_3630SDP=y CONFIG_MACH_OMAP_4430SDP=y CONFIG_ARM_THUMBEE=y CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_ERRATA_411920=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_SMP=y diff --git a/arch/arm/configs/omap_generic_2420_defconfig b/arch/arm/configs/omap_generic_2420_defconfig deleted file mode 100644 index ac08e51..0000000 --- a/arch/arm/configs/omap_generic_2420_defconfig +++ /dev/null @@ -1,37 +0,0 @@ -CONFIG_EXPERIMENTAL=y -CONFIG_SYSVIPC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_ARCH_OMAP=y -CONFIG_ARCH_OMAP2=y -# CONFIG_OMAP_MUX is not set -CONFIG_MACH_OMAP_GENERIC=y -CONFIG_ARCH_OMAP2420=y -CONFIG_LEDS=y -CONFIG_ZBOOT_ROM_TEXT=0x10C08000 -CONFIG_ZBOOT_ROM_BSS=0x10200000 -CONFIG_FPE_NWFPE=y -CONFIG_BLK_DEV_RAM=y -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -# CONFIG_LEGACY_PTYS is not set -CONFIG_WATCHDOG=y -CONFIG_WATCHDOG_NOWAYOUT=y -CONFIG_VIDEO_OUTPUT_CONTROL=m -# CONFIG_VGA_CONSOLE is not set -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_INOTIFY=y -CONFIG_ROMFS_FS=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y -CONFIG_DEBUG_LL=y -CONFIG_CRC_CCITT=y -- cgit v1.1 From c1f9a095600e07fefe64eb94eb711f410100824a Mon Sep 17 00:00:00 2001 From: Ohad Ben-Cohen Date: Thu, 16 Sep 2010 13:16:02 +0200 Subject: wl12xx: make wl12xx.h common to both spi and sdio Move wl12xx.h outside of the spi-specific location, so it can be shared with both spi and sdio solutions. Update all users of spi/wl12xx.h accordingly Signed-off-by: Ohad Ben-Cohen Acked-by: Luciano Coelho Acked-by: Tony Lindgren Signed-off-by: John W. Linville --- arch/arm/mach-omap2/board-omap3pandora.c | 1 + arch/arm/mach-omap2/board-rx51-peripherals.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c index c0f4f12..9b62b62 100644 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ b/arch/arm/mach-omap2/board-omap3pandora.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index 0348392..1cf9942 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include #include -- cgit v1.1 From b642fde7f137566c993991fd2e7bf6b8274bf625 Mon Sep 17 00:00:00 2001 From: Ohad Ben-Cohen Date: Thu, 16 Sep 2010 01:32:09 +0200 Subject: omap: zoom: add fixed regulator device for wlan Add a fixed regulator vmmc device to enable power control of the wl1271 wlan device. Signed-off-by: Ohad Ben-Cohen Acked-by: Tony Lindgren Signed-off-by: John W. Linville --- arch/arm/mach-omap2/board-zoom-peripherals.c | 35 ++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c index 6b39849..f5df9a2 100644 --- a/arch/arm/mach-omap2/board-zoom-peripherals.c +++ b/arch/arm/mach-omap2/board-zoom-peripherals.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include @@ -27,6 +28,8 @@ #include "mux.h" #include "hsmmc.h" +#define OMAP_ZOOM_WLAN_PMENA_GPIO (101) + /* Zoom2 has Qwerty keyboard*/ static int board_keymap[] = { KEY(0, 0, KEY_E), @@ -106,6 +109,11 @@ static struct regulator_consumer_supply zoom_vmmc2_supply = { .supply = "vmmc", }; +static struct regulator_consumer_supply zoom_vmmc3_supply = { + .supply = "vmmc", + .dev_name = "mmci-omap-hs.2", +}; + /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ static struct regulator_init_data zoom_vmmc1 = { .constraints = { @@ -151,6 +159,32 @@ static struct regulator_init_data zoom_vsim = { .consumer_supplies = &zoom_vsim_supply, }; +static struct regulator_init_data zoom_vmmc3 = { + .constraints = { + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &zoom_vmmc3_supply, +}; + +static struct fixed_voltage_config zoom_vwlan = { + .supply_name = "vwl1271", + .microvolts = 1800000, /* 1.8V */ + .gpio = OMAP_ZOOM_WLAN_PMENA_GPIO, + .startup_delay = 70000, /* 70msec */ + .enable_high = 1, + .enabled_at_boot = 0, + .init_data = &zoom_vmmc3, +}; + +static struct platform_device omap_vwlan_device = { + .name = "reg-fixed-voltage", + .id = 1, + .dev = { + .platform_data = &zoom_vwlan, + }, +}; + static struct omap2_hsmmc_info mmc[] __initdata = { { .name = "external", @@ -280,6 +314,7 @@ static void enable_board_wakeup_source(void) void __init zoom_peripherals_init(void) { omap_i2c_init(); + platform_device_register(&omap_vwlan_device); usb_musb_init(&musb_board_data); enable_board_wakeup_source(); } -- cgit v1.1 From 80b517f362605f2b6a6cfe086604534290aab2de Mon Sep 17 00:00:00 2001 From: Ohad Ben-Cohen Date: Thu, 16 Sep 2010 01:32:30 +0200 Subject: omap: zoom: add mmc3/wl1271 device support Add MMC3 support on ZOOM, which has the wl1271 device hardwired to. The wl1271 is a 4-wire, 1.8V, embedded SDIO WLAN device with an external IRQ line, and power-controlled by a GPIO-based fixed regulator. Signed-off-by: Ohad Ben-Cohen Acked-by: Tony Lindgren Signed-off-by: John W. Linville --- arch/arm/mach-omap2/board-zoom-peripherals.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c index f5df9a2..6aa0728 100644 --- a/arch/arm/mach-omap2/board-zoom-peripherals.c +++ b/arch/arm/mach-omap2/board-zoom-peripherals.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -29,6 +30,7 @@ #include "hsmmc.h" #define OMAP_ZOOM_WLAN_PMENA_GPIO (101) +#define OMAP_ZOOM_WLAN_IRQ_GPIO (162) /* Zoom2 has Qwerty keyboard*/ static int board_keymap[] = { @@ -185,6 +187,12 @@ static struct platform_device omap_vwlan_device = { }, }; +struct wl12xx_platform_data omap_zoom_wlan_data __initdata = { + .irq = OMAP_GPIO_IRQ(OMAP_ZOOM_WLAN_IRQ_GPIO), + /* ZOOM ref clock is 26 MHz */ + .board_ref_clock = 1, +}; + static struct omap2_hsmmc_info mmc[] __initdata = { { .name = "external", @@ -202,6 +210,14 @@ static struct omap2_hsmmc_info mmc[] __initdata = { .nonremovable = true, .power_saving = true, }, + { + .name = "wl1271", + .mmc = 3, + .wires = 4, + .gpio_wp = -EINVAL, + .gpio_cd = -EINVAL, + .nonremovable = true, + }, {} /* Terminator */ }; @@ -313,6 +329,9 @@ static void enable_board_wakeup_source(void) void __init zoom_peripherals_init(void) { + if (wl12xx_set_platform_data(&omap_zoom_wlan_data)) + pr_err("error setting wl12xx data\n"); + omap_i2c_init(); platform_device_register(&omap_vwlan_device); usb_musb_init(&musb_board_data); -- cgit v1.1 From 9ee9fff92e02e8c5f84794b3a5ce47646c2dfc39 Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Tue, 21 Sep 2010 10:34:08 -0600 Subject: OMAP: hwmod: Rename dma_ch to dma_req The dma request line attribute was named dma channel, which leads to confusion with the real dma channel definition. Signed-off-by: Benoit Cousson Signed-off-by: Paul Walmsley Tested-by: Kevin Hilman --- arch/arm/mach-omap2/omap_hwmod.c | 10 +++++----- arch/arm/plat-omap/include/plat/omap_hwmod.h | 12 ++++++------ 2 files changed, 11 insertions(+), 11 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index cb911d7..8bf19a7 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -1468,7 +1468,7 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh) { int ret, i; - ret = oh->mpu_irqs_cnt + oh->sdma_chs_cnt; + ret = oh->mpu_irqs_cnt + oh->sdma_reqs_cnt; for (i = 0; i < oh->slaves_cnt; i++) ret += oh->slaves[i]->addr_cnt; @@ -1501,10 +1501,10 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) r++; } - for (i = 0; i < oh->sdma_chs_cnt; i++) { - (res + r)->name = (oh->sdma_chs + i)->name; - (res + r)->start = (oh->sdma_chs + i)->dma_ch; - (res + r)->end = (oh->sdma_chs + i)->dma_ch; + for (i = 0; i < oh->sdma_reqs_cnt; i++) { + (res + r)->name = (oh->sdma_reqs + i)->name; + (res + r)->start = (oh->sdma_reqs + i)->dma_req; + (res + r)->end = (oh->sdma_reqs + i)->dma_req; (res + r)->flags = IORESOURCE_DMA; r++; } diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index a4e508d..5506d80 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -96,7 +96,7 @@ struct omap_hwmod_irq_info { /** * struct omap_hwmod_dma_info - DMA channels used by the hwmod * @name: name of the DMA channel (module local name) - * @dma_ch: DMA channel ID + * @dma_req: DMA request ID * * @name should be something short, e.g., "tx" or "rx". It is for use * by platform_get_resource_byname(). It is defined locally to the @@ -104,7 +104,7 @@ struct omap_hwmod_irq_info { */ struct omap_hwmod_dma_info { const char *name; - u16 dma_ch; + u16 dma_req; }; /** @@ -410,7 +410,7 @@ struct omap_hwmod_class { * @class: struct omap_hwmod_class * to the class of this hwmod * @od: struct omap_device currently associated with this hwmod (internal use) * @mpu_irqs: ptr to an array of MPU IRQs (see also mpu_irqs_cnt) - * @sdma_chs: ptr to an array of SDMA channel IDs (see also sdma_chs_cnt) + * @sdma_reqs: ptr to an array of System DMA request IDs (see sdma_reqs_cnt) * @prcm: PRCM data pertaining to this hwmod * @main_clk: main clock: OMAP clock name * @_clk: pointer to the main struct clk (filled in at runtime) @@ -424,7 +424,7 @@ struct omap_hwmod_class { * @msuspendmux_reg_id: CONTROL_MSUSPENDMUX register ID (1-6) * @msuspendmux_shift: CONTROL_MSUSPENDMUX register bit shift * @mpu_irqs_cnt: number of @mpu_irqs - * @sdma_chs_cnt: number of @sdma_chs + * @sdma_reqs_cnt: number of @sdma_reqs * @opt_clks_cnt: number of @opt_clks * @master_cnt: number of @master entries * @slaves_cnt: number of @slave entries @@ -448,7 +448,7 @@ struct omap_hwmod { struct omap_hwmod_class *class; struct omap_device *od; struct omap_hwmod_irq_info *mpu_irqs; - struct omap_hwmod_dma_info *sdma_chs; + struct omap_hwmod_dma_info *sdma_reqs; union { struct omap_hwmod_omap2_prcm omap2; struct omap_hwmod_omap4_prcm omap4; @@ -468,7 +468,7 @@ struct omap_hwmod { u8 msuspendmux_shift; u8 response_lat; u8 mpu_irqs_cnt; - u8 sdma_chs_cnt; + u8 sdma_reqs_cnt; u8 opt_clks_cnt; u8 masters_cnt; u8 slaves_cnt; -- cgit v1.1 From d5c47d7e97c141edb620b3932e1e1cb39e70c654 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Tue, 10 Aug 2010 16:04:35 -0700 Subject: OMAP3: PM: whitespace cleanup around IO wakeup enable Cleanup indentation around IO wakeup enable, the '\' terminator is not required in C when wrapping an expression past end-of-line. Whitespace change only. Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/pm34xx.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 7b03426..b5e5bcb 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -385,9 +385,9 @@ void omap_sram_idle(void) /* Enable IO-PAD and IO-CHAIN wakeups */ per_next_state = pwrdm_read_next_pwrst(per_pwrdm); core_next_state = pwrdm_read_next_pwrst(core_pwrdm); - if (omap3_has_io_wakeup() && \ - (per_next_state < PWRDM_POWER_ON || - core_next_state < PWRDM_POWER_ON)) { + if (omap3_has_io_wakeup() && + (per_next_state < PWRDM_POWER_ON || + core_next_state < PWRDM_POWER_ON)) { prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); omap3_enable_io_chain(); } -- cgit v1.1 From 6cdee91257bee23a46dc869ca62469b67cba2c7e Mon Sep 17 00:00:00 2001 From: Thara Gopinath Date: Thu, 12 Aug 2010 13:52:25 +0530 Subject: OMAP: PM debugfs removing OMAP3 hardcodings. This patch removes omap3 hardcodings from pm-debug.c so that enabling PM debugfs support does break compilation for other OMAP's. This is a preparatory patch for supporting OMAP4 pm entries through PM debugfs. Signed-off-by: Thara Gopinath Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/pm-debug.c | 21 ++++++++++++++++----- arch/arm/mach-omap2/pm34xx.c | 5 ----- 2 files changed, 16 insertions(+), 10 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c index 723b44e..056ff17 100644 --- a/arch/arm/mach-omap2/pm-debug.c +++ b/arch/arm/mach-omap2/pm-debug.c @@ -37,6 +37,10 @@ #include "pm.h" int omap2_pm_debug; +u32 enable_off_mode; +u32 sleep_while_idle; +u32 wakeup_timer_seconds; +u32 wakeup_timer_milliseconds; #define DUMP_PRM_MOD_REG(mod, reg) \ regs[reg_count].name = #mod "." #reg; \ @@ -494,8 +498,10 @@ int pm_dbg_regset_init(int reg_set) static int pwrdm_suspend_get(void *data, u64 *val) { - int ret; - ret = omap3_pm_get_suspend_state((struct powerdomain *)data); + int ret = -EINVAL; + + if (cpu_is_omap34xx()) + ret = omap3_pm_get_suspend_state((struct powerdomain *)data); *val = ret; if (ret >= 0) @@ -505,7 +511,10 @@ static int pwrdm_suspend_get(void *data, u64 *val) static int pwrdm_suspend_set(void *data, u64 val) { - return omap3_pm_set_suspend_state((struct powerdomain *)data, (int)val); + if (cpu_is_omap34xx()) + return omap3_pm_set_suspend_state( + (struct powerdomain *)data, (int)val); + return -EINVAL; } DEFINE_SIMPLE_ATTRIBUTE(pwrdm_suspend_fops, pwrdm_suspend_get, @@ -553,8 +562,10 @@ static int option_set(void *data, u64 val) *option = val; - if (option == &enable_off_mode) - omap3_pm_off_mode_enable(val); + if (option == &enable_off_mode) { + if (cpu_is_omap34xx()) + omap3_pm_off_mode_enable(val); + } return 0; } diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index b5e5bcb..429268e 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -55,11 +55,6 @@ #define OMAP343X_TABLE_VALUE_OFFSET 0x30 #define OMAP343X_CONTROL_REG_VALUE_OFFSET 0x32 -u32 enable_off_mode; -u32 sleep_while_idle; -u32 wakeup_timer_seconds; -u32 wakeup_timer_milliseconds; - struct power_state { struct powerdomain *pwrdm; u32 next_state; -- cgit v1.1 From 57e6fe7b888e17f814bd35b7700ded51aa9a6a83 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Thu, 5 Nov 2009 19:06:01 -0800 Subject: OMAP2+: PM: initial runtime PM core support Implement the new runtime PM framework as a thin layer on top of the omap_device API. OMAP specific runtime PM methods are registered with the as custom methods on the platform_bus. In order to determine if a device is an omap_device, its parent device is checked. All omap_devices have a new 'omap_device_parent_ device as their parent device, so checking for this parent is used to check for valid omap_devices. If a device is an omap_device, then the appropriate omap_device functions are called for it. If not, only the generic runtime PM functions are called. Device driver's ->runtime_idle() hook is called when the runtime PM usecount reaches zero for that device. Driver's ->runtime_suspend() hooks are called just before the device is disabled (via omap_device_idle()), and device driver ->runtime_resume() hooks are called just after device has been enabled (via omap_device_enable().) OMAP4 build support from Rajendra Nayak . OMAP2 build support from Charulatha V Cc: Rajendra Nayak Cc: Charulatha V Acked-by: Grant Likely Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/Makefile | 10 ++++-- arch/arm/mach-omap2/pm_bus.c | 85 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 92 insertions(+), 3 deletions(-) create mode 100644 arch/arm/mach-omap2/pm_bus.c (limited to 'arch') diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 88d3a1e..b48ca60 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -49,14 +49,18 @@ obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o # Power Management ifeq ($(CONFIG_PM),y) obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o -obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o -obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o cpuidle34xx.o -obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o +obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o pm_bus.o +obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o cpuidle34xx.o pm_bus.o +obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o pm_bus.o obj-$(CONFIG_PM_DEBUG) += pm-debug.o AFLAGS_sleep24xx.o :=-Wa,-march=armv6 AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a +ifeq ($(CONFIG_PM_VERBOSE),y) +CFLAGS_pm_bus.o += -DDEBUG +endif + endif # PRCM diff --git a/arch/arm/mach-omap2/pm_bus.c b/arch/arm/mach-omap2/pm_bus.c new file mode 100644 index 0000000..784989f --- /dev/null +++ b/arch/arm/mach-omap2/pm_bus.c @@ -0,0 +1,85 @@ +/* + * Runtime PM support code for OMAP + * + * Author: Kevin Hilman, Deep Root Systems, LLC + * + * Copyright (C) 2010 Texas Instruments, Inc. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ +#include +#include +#include +#include +#include +#include + +#include +#include + +#ifdef CONFIG_PM_RUNTIME +int omap_pm_runtime_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + int r, ret = 0; + + dev_dbg(dev, "%s\n", __func__); + + ret = pm_generic_runtime_suspend(dev); + + if (!ret && dev->parent == &omap_device_parent) { + r = omap_device_idle(pdev); + WARN_ON(r); + } + + return ret; +}; + +int omap_pm_runtime_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + int r; + + dev_dbg(dev, "%s\n", __func__); + + if (dev->parent == &omap_device_parent) { + r = omap_device_enable(pdev); + WARN_ON(r); + } + + return pm_generic_runtime_resume(dev); +}; +#else +#define omap_pm_runtime_suspend NULL +#define omap_pm_runtime_resume NULL +#endif /* CONFIG_PM_RUNTIME */ + +static int __init omap_pm_runtime_init(void) +{ + const struct dev_pm_ops *pm; + struct dev_pm_ops *omap_pm; + + pm = platform_bus_get_pm_ops(); + if (!pm) { + pr_err("%s: unable to get dev_pm_ops from platform_bus\n", + __func__); + return -ENODEV; + } + + omap_pm = kmemdup(pm, sizeof(struct dev_pm_ops), GFP_KERNEL); + if (!omap_pm) { + pr_err("%s: unable to alloc memory for new dev_pm_ops\n", + __func__); + return -ENOMEM; + } + + omap_pm->runtime_suspend = omap_pm_runtime_suspend; + omap_pm->runtime_resume = omap_pm_runtime_resume; + + platform_bus_set_pm_ops(omap_pm); + + return 0; +} +core_initcall(omap_pm_runtime_init); -- cgit v1.1 From e933ec7c4ebd7e7daaad67b22e5f4a9a0ab102ea Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Thu, 17 Jun 2010 15:48:43 -0700 Subject: OMAP1: PM: add simple runtime PM layer to manage clocks On OMAP1, we do not have omap_device + omap_hwmod to manage the device-specific idle, enable and shutdown. Instead, just enable/disable device clocks automatically at the runtime PM level. This allows drivers to not have any OMAP1 specific clock management and allows them to simply use the runtime PM API to manage clocks. OMAP1 compile fixes Manjunatha GK Cc: Manjunatha GK Signed-off-by: Kevin Hilman --- arch/arm/mach-omap1/Makefile | 2 +- arch/arm/mach-omap1/pm_bus.c | 98 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 99 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-omap1/pm_bus.c (limited to 'arch') diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile index facfaeb..9a304d8 100644 --- a/arch/arm/mach-omap1/Makefile +++ b/arch/arm/mach-omap1/Makefile @@ -12,7 +12,7 @@ obj-$(CONFIG_OMAP_MPU_TIMER) += time.o obj-$(CONFIG_OMAP_32K_TIMER) += timer32k.o # Power Management -obj-$(CONFIG_PM) += pm.o sleep.o +obj-$(CONFIG_PM) += pm.o sleep.o pm_bus.o # DSP obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o diff --git a/arch/arm/mach-omap1/pm_bus.c b/arch/arm/mach-omap1/pm_bus.c new file mode 100644 index 0000000..8b66392 --- /dev/null +++ b/arch/arm/mach-omap1/pm_bus.c @@ -0,0 +1,98 @@ +/* + * Runtime PM support code for OMAP1 + * + * Author: Kevin Hilman, Deep Root Systems, LLC + * + * Copyright (C) 2010 Texas Instruments, Inc. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#ifdef CONFIG_PM_RUNTIME +static int omap1_pm_runtime_suspend(struct device *dev) +{ + struct clk *iclk, *fclk; + int ret = 0; + + dev_dbg(dev, "%s\n", __func__); + + ret = pm_generic_runtime_suspend(dev); + + fclk = clk_get(dev, "fck"); + if (!IS_ERR(fclk)) { + clk_disable(fclk); + clk_put(fclk); + } + + iclk = clk_get(dev, "ick"); + if (!IS_ERR(iclk)) { + clk_disable(iclk); + clk_put(iclk); + } + + return 0; +}; + +static int omap1_pm_runtime_resume(struct device *dev) +{ + int ret = 0; + struct clk *iclk, *fclk; + + dev_dbg(dev, "%s\n", __func__); + + iclk = clk_get(dev, "ick"); + if (!IS_ERR(iclk)) { + clk_enable(iclk); + clk_put(iclk); + } + + fclk = clk_get(dev, "fck"); + if (!IS_ERR(fclk)) { + clk_enable(fclk); + clk_put(fclk); + } + + return pm_generic_runtime_resume(dev); +}; + +static int __init omap1_pm_runtime_init(void) +{ + const struct dev_pm_ops *pm; + struct dev_pm_ops *omap_pm; + + pm = platform_bus_get_pm_ops(); + if (!pm) { + pr_err("%s: unable to get dev_pm_ops from platform_bus\n", + __func__); + return -ENODEV; + } + + omap_pm = kmemdup(pm, sizeof(struct dev_pm_ops), GFP_KERNEL); + if (!omap_pm) { + pr_err("%s: unable to alloc memory for new dev_pm_ops\n", + __func__); + return -ENOMEM; + } + + omap_pm->runtime_suspend = omap1_pm_runtime_suspend; + omap_pm->runtime_resume = omap1_pm_runtime_resume; + + platform_bus_set_pm_ops(omap_pm); + + return 0; +} +core_initcall(omap1_pm_runtime_init); +#endif /* CONFIG_PM_RUNTIME */ -- cgit v1.1 From 3827f9492bdff045ae57fe67e65ce7e259ed4219 Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Tue, 21 Sep 2010 10:34:08 -0600 Subject: OMAP: hwmod: Do not disable clocks if hwmod already in idle The disable function was disabling clocks and dependencies from both enable and idle state. Since idle function is already disabling both, an enable -> idle -> disable sequence will try to disable twice the clocks and thus generate a "Trying disable clock XXX with 0 usecount" warning. Signed-off-by: Benoit Cousson Signed-off-by: Paul Walmsley Tested-by: Kevin Hilman --- arch/arm/mach-omap2/omap_hwmod.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 8bf19a7..5bb25e3 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -982,9 +982,13 @@ static int _shutdown(struct omap_hwmod *oh) if (oh->class->sysc) _sysc_shutdown(oh); - _del_initiator_dep(oh, mpu_oh); - /* XXX what about the other system initiators here? DMA, tesla, d2d */ - _disable_clocks(oh); + + /* clocks and deps are already disabled in idle */ + if (oh->_state == _HWMOD_STATE_ENABLED) { + _del_initiator_dep(oh, mpu_oh); + /* XXX what about the other system initiators here? dma, dsp */ + _disable_clocks(oh); + } /* XXX Should this code also force-disable the optional clocks? */ /* XXX mux any associated balls to safe mode */ -- cgit v1.1 From 9b579114efc4bd00532de33c783b4cb4638910ff Mon Sep 17 00:00:00 2001 From: Liam Girdwood Date: Tue, 21 Sep 2010 10:34:09 -0600 Subject: OMAP: hwmod: Fix omap_hwmod_reset wrong state test The reset function wrongly used the state flag as a bit mask and was trying to re-enable after a reset. hwmod is still enabled for the PRCM point of view after a softreset so there is no need to re-enable. Remove the state check from omap_hwmod_reset since the _reset function is checking that as well and in addition can generate a warning Signed-off-by: Liam Girdwood [b-cousson@ti.com: remove the wrong test, remove the re-enable] Signed-off-by: Benoit Cousson Signed-off-by: Paul Walmsley Tested-by: Kevin Hilman Cc: Rajendra Nayak --- arch/arm/mach-omap2/omap_hwmod.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 5bb25e3..100115f 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -1434,19 +1434,17 @@ void omap_hwmod_ocp_barrier(struct omap_hwmod *oh) * * Under some conditions, a driver may wish to reset the entire device. * Called from omap_device code. Returns -EINVAL on error or passes along - * the return value from _reset()/_enable(). + * the return value from _reset(). */ int omap_hwmod_reset(struct omap_hwmod *oh) { int r; - if (!oh || !(oh->_state & _HWMOD_STATE_ENABLED)) + if (!oh) return -EINVAL; mutex_lock(&omap_hwmod_mutex); r = _reset(oh); - if (!r) - r = _omap_hwmod_enable(oh); mutex_unlock(&omap_hwmod_mutex); return r; -- cgit v1.1 From ff4d3e186b7b92c74a4f64360f723c603193f344 Mon Sep 17 00:00:00 2001 From: Rajeev Kulkarni Date: Tue, 21 Sep 2010 10:34:09 -0600 Subject: OMAP4: prcm: Fix global warm reset bit position OMAP4 platform has different register bits for Warm and Cold Resets. Write one into appropriate bits. Signed-off-by: Rajeev Kulkarni Cc: Leed Aguilar [b-cousson@ti.com: Change the define with the proper one from omap4 headers] Signed-off-by: Benoit Cousson Signed-off-by: Paul Walmsley Tested-by: Kevin Hilman --- arch/arm/mach-omap2/prcm.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c index c201374..96f4616 100644 --- a/arch/arm/mach-omap2/prcm.c +++ b/arch/arm/mach-omap2/prcm.c @@ -33,6 +33,7 @@ #include "cm.h" #include "prm.h" #include "prm-regbits-24xx.h" +#include "prm-regbits-44xx.h" static void __iomem *prm_base; static void __iomem *cm_base; @@ -161,8 +162,8 @@ void omap_prcm_arch_reset(char mode, const char *cmd) prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs, OMAP2_RM_RSTCTRL); if (cpu_is_omap44xx()) - prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs, - OMAP4_RM_RSTCTRL); + prm_set_mod_reg_bits(OMAP4430_RST_GLOBAL_WARM_SW_MASK, + prcm_offs, OMAP4_RM_RSTCTRL); } static inline u32 __omap_prcm_read(void __iomem *base, s16 module, u16 reg) -- cgit v1.1 From 12b1fdb45c2594070bb36e39cd89a33547aad8fb Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Tue, 21 Sep 2010 10:34:09 -0600 Subject: OMAP: hwmod: separate list locking and hwmod hardware locking Currently omap_hwmod_mutex is being used to protect both the list access/modification and concurrent access to hwmod functions. This patch separates these two types of locking. First, omap_hwmod_mutex is used only to protect access and modification of omap_hwmod_list. Also cleaned up some comments referring to this mutex that are no longer needed. Then, for protecting concurrent access to hwmod functions, use a per-hwmod mutex. This protects concurrent access to a single hwmod, but would allow concurrent access to different hwmods. Signed-off-by: Kevin Hilman [paul@pwsan.com: added structure documentation; changed mutex variable name] Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/omap_hwmod.c | 62 ++++++++++++++-------------- arch/arm/plat-omap/include/plat/omap_hwmod.h | 3 ++ 2 files changed, 33 insertions(+), 32 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 100115f..3084409 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -767,10 +767,10 @@ static struct omap_hwmod *_lookup(const char *name) * @data: not used; pass NULL * * Called by omap_hwmod_late_init() (after omap2_clk_init()). - * Resolves all clock names embedded in the hwmod. Must be called - * with omap_hwmod_mutex held. Returns -EINVAL if the omap_hwmod - * has not yet been registered or if the clocks have already been - * initialized, 0 on success, or a non-zero error on failure. + * Resolves all clock names embedded in the hwmod. Returns -EINVAL if + * the omap_hwmod has not yet been registered or if the clocks have + * already been initialized, 0 on success, or a non-zero error on + * failure. */ static int _init_clocks(struct omap_hwmod *oh, void *data) { @@ -838,10 +838,9 @@ static int _wait_target_ready(struct omap_hwmod *oh) * @oh: struct omap_hwmod * * * Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit. hwmod must be - * enabled for this to work. Must be called with omap_hwmod_mutex - * held. Returns -EINVAL if the hwmod cannot be reset this way or if - * the hwmod is in the wrong state, -ETIMEDOUT if the module did not - * reset in time, or 0 upon success. + * enabled for this to work. Returns -EINVAL if the hwmod cannot be + * reset this way or if the hwmod is in the wrong state, -ETIMEDOUT if + * the module did not reset in time, or 0 upon success. */ static int _reset(struct omap_hwmod *oh) { @@ -891,9 +890,8 @@ static int _reset(struct omap_hwmod *oh) * @oh: struct omap_hwmod * * * Enables an omap_hwmod @oh such that the MPU can access the hwmod's - * register target. Must be called with omap_hwmod_mutex held. - * Returns -EINVAL if the hwmod is in the wrong state or passes along - * the return value of _wait_target_ready(). + * register target. Returns -EINVAL if the hwmod is in the wrong + * state or passes along the return value of _wait_target_ready(). */ int _omap_hwmod_enable(struct omap_hwmod *oh) { @@ -1004,11 +1002,10 @@ static int _shutdown(struct omap_hwmod *oh) * @skip_setup_idle_p: do not idle hwmods at the end of the fn if 1 * * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh - * OCP_SYSCONFIG register. Must be called with omap_hwmod_mutex held. - * @skip_setup_idle is intended to be used on a system that will not - * call omap_hwmod_enable() to enable devices (e.g., a system without - * PM runtime). Returns -EINVAL if the hwmod is in the wrong state or - * returns 0. + * OCP_SYSCONFIG register. @skip_setup_idle is intended to be used on + * a system that will not call omap_hwmod_enable() to enable devices + * (e.g., a system without PM runtime). Returns -EINVAL if the hwmod + * is in the wrong state or returns 0. */ static int _setup(struct omap_hwmod *oh, void *data) { @@ -1038,6 +1035,7 @@ static int _setup(struct omap_hwmod *oh, void *data) } } + mutex_init(&oh->_mutex); oh->_state = _HWMOD_STATE_INITIALIZED; r = _omap_hwmod_enable(oh); @@ -1323,9 +1321,9 @@ int omap_hwmod_enable(struct omap_hwmod *oh) if (!oh) return -EINVAL; - mutex_lock(&omap_hwmod_mutex); + mutex_lock(&oh->_mutex); r = _omap_hwmod_enable(oh); - mutex_unlock(&omap_hwmod_mutex); + mutex_unlock(&oh->_mutex); return r; } @@ -1343,9 +1341,9 @@ int omap_hwmod_idle(struct omap_hwmod *oh) if (!oh) return -EINVAL; - mutex_lock(&omap_hwmod_mutex); + mutex_lock(&oh->_mutex); _omap_hwmod_idle(oh); - mutex_unlock(&omap_hwmod_mutex); + mutex_unlock(&oh->_mutex); return 0; } @@ -1363,9 +1361,9 @@ int omap_hwmod_shutdown(struct omap_hwmod *oh) if (!oh) return -EINVAL; - mutex_lock(&omap_hwmod_mutex); + mutex_lock(&oh->_mutex); _shutdown(oh); - mutex_unlock(&omap_hwmod_mutex); + mutex_unlock(&oh->_mutex); return 0; } @@ -1378,9 +1376,9 @@ int omap_hwmod_shutdown(struct omap_hwmod *oh) */ int omap_hwmod_enable_clocks(struct omap_hwmod *oh) { - mutex_lock(&omap_hwmod_mutex); + mutex_lock(&oh->_mutex); _enable_clocks(oh); - mutex_unlock(&omap_hwmod_mutex); + mutex_unlock(&oh->_mutex); return 0; } @@ -1393,9 +1391,9 @@ int omap_hwmod_enable_clocks(struct omap_hwmod *oh) */ int omap_hwmod_disable_clocks(struct omap_hwmod *oh) { - mutex_lock(&omap_hwmod_mutex); + mutex_lock(&oh->_mutex); _disable_clocks(oh); - mutex_unlock(&omap_hwmod_mutex); + mutex_unlock(&oh->_mutex); return 0; } @@ -1443,9 +1441,9 @@ int omap_hwmod_reset(struct omap_hwmod *oh) if (!oh) return -EINVAL; - mutex_lock(&omap_hwmod_mutex); + mutex_lock(&oh->_mutex); r = _reset(oh); - mutex_unlock(&omap_hwmod_mutex); + mutex_unlock(&oh->_mutex); return r; } @@ -1646,9 +1644,9 @@ int omap_hwmod_enable_wakeup(struct omap_hwmod *oh) !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) return -EINVAL; - mutex_lock(&omap_hwmod_mutex); + mutex_lock(&oh->_mutex); _enable_wakeup(oh); - mutex_unlock(&omap_hwmod_mutex); + mutex_unlock(&oh->_mutex); return 0; } @@ -1671,9 +1669,9 @@ int omap_hwmod_disable_wakeup(struct omap_hwmod *oh) !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) return -EINVAL; - mutex_lock(&omap_hwmod_mutex); + mutex_lock(&oh->_mutex); _disable_wakeup(oh); - mutex_unlock(&omap_hwmod_mutex); + mutex_unlock(&oh->_mutex); return 0; } diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index 5506d80..03350ba 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -35,6 +35,7 @@ #include #include #include +#include #include struct omap_device; @@ -433,6 +434,7 @@ struct omap_hwmod_class { * @_state: internal-use hwmod state * @flags: hwmod flags (documented below) * @omap_chip: OMAP chips this hwmod is present on + * @_mutex: mutex serializing operations on this hwmod * @node: list node for hwmod list (internal use) * * @main_clk refers to this module's "main clock," which for our @@ -461,6 +463,7 @@ struct omap_hwmod { void *dev_attr; u32 _sysc_cache; void __iomem *_mpu_rt_va; + struct mutex _mutex; struct list_head node; u16 flags; u8 _mpu_port_index; -- cgit v1.1 From 16b040129e324598d13ff2e2b3469dc2e909ce12 Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Tue, 21 Sep 2010 10:34:10 -0600 Subject: OMAP4: prcm: Add temporarily helper functions for rmw and read inside the PRM Since OMAP4 is using an absolute address, the current PRM accessors are not useable. OMAP4 adaptation for these API are currently ongoing, so define temp version until the proper ones are defined. Signed-off-by: Benoit Cousson Signed-off-by: Paul Walmsley Tested-by: Kevin Hilman --- arch/arm/mach-omap2/prcm.c | 24 ++++++++++++++++++++++++ arch/arm/plat-omap/include/plat/prcm.h | 2 ++ 2 files changed, 26 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c index 96f4616..d4388d34 100644 --- a/arch/arm/mach-omap2/prcm.c +++ b/arch/arm/mach-omap2/prcm.c @@ -216,6 +216,30 @@ u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask) return v; } +/* Read a PRM register, AND it, and shift the result down to bit 0 */ +u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask) +{ + u32 v; + + v = __raw_readl(reg); + v &= mask; + v >>= __ffs(mask); + + return v; +} + +/* Read-modify-write a register in a PRM module. Caller must lock */ +u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg) +{ + u32 v; + + v = __raw_readl(reg); + v &= ~mask; + v |= bits; + __raw_writel(v, reg); + + return v; +} /* Read a register in a CM module */ u32 cm_read_mod_reg(s16 module, u16 idx) { diff --git a/arch/arm/plat-omap/include/plat/prcm.h b/arch/arm/plat-omap/include/plat/prcm.h index 9fbd914..ab77442 100644 --- a/arch/arm/plat-omap/include/plat/prcm.h +++ b/arch/arm/plat-omap/include/plat/prcm.h @@ -38,6 +38,8 @@ u32 prm_read_mod_reg(s16 module, u16 idx); void prm_write_mod_reg(u32 val, s16 module, u16 idx); u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask); +u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask); +u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg); u32 cm_read_mod_reg(s16 module, u16 idx); void cm_write_mod_reg(u32 val, s16 module, u16 idx); u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); -- cgit v1.1 From 0be1621a749907ada0101e4139a1f57168c5410b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Cousson?= Date: Tue, 21 Sep 2010 10:34:10 -0600 Subject: OMAP4: PRM: add module hard reset support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Most processor modules (e.g., DSP, IVA, IPU) on OMAPs can be reset under the control of the PRM. This patch adds an API for this purpose for OMAP4 devices: int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift); int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift); int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift); This API is intended to be used only by the hwmod code - a subsequent patch will add that support to hwmod. This patch is a collaboration between Benoît Cousson and Paul Walmsley . Signed-off-by: Paul Walmsley Signed-off-by: Benoît Cousson Tested-by: Kevin Hilman --- arch/arm/mach-omap2/Makefile | 2 +- arch/arm/mach-omap2/prm.h | 13 ++++- arch/arm/mach-omap2/prm44xx.c | 116 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 129 insertions(+), 2 deletions(-) create mode 100644 arch/arm/mach-omap2/prm44xx.c (limited to 'arch') diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 88d3a1e..c0da784 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -15,7 +15,7 @@ clock-common = clock.o clock_common_data.o \ obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(hwmod-common) obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(hwmod-common) -obj-$(CONFIG_ARCH_OMAP4) += $(prcm-common) $(hwmod-common) +obj-$(CONFIG_ARCH_OMAP4) += $(prcm-common) prm44xx.o $(hwmod-common) obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h index 588873b..bc7e6e6 100644 --- a/arch/arm/mach-omap2/prm.h +++ b/arch/arm/mach-omap2/prm.h @@ -5,7 +5,7 @@ * OMAP2/3 Power/Reset Management (PRM) register definitions * * Copyright (C) 2007-2009 Texas Instruments, Inc. - * Copyright (C) 2009 Nokia Corporation + * Copyright (C) 2010 Nokia Corporation * * Written by Paul Walmsley * @@ -246,6 +246,10 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) return prm_rmw_mod_reg_bits(bits, 0x0, module, idx); } +int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift); +int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift); +int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift); + #endif /* @@ -398,4 +402,11 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) #define OMAP_POWERSTATE_MASK (0x3 << 0) +/* + * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP + * submodule to exit hardreset + */ +#define MAX_MODULE_HARDRESET_WAIT 10000 + + #endif diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c new file mode 100644 index 0000000..a1ff918 --- /dev/null +++ b/arch/arm/mach-omap2/prm44xx.c @@ -0,0 +1,116 @@ +/* + * OMAP4 PRM module functions + * + * Copyright (C) 2010 Texas Instruments, Inc. + * Copyright (C) 2010 Nokia Corporation + * Benoît Cousson + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include +#include +#include + +#include "prm.h" +#include "prm-regbits-44xx.h" + +/* + * Address offset (in bytes) between the reset control and the reset + * status registers: 4 bytes on OMAP4 + */ +#define OMAP4_RST_CTRL_ST_OFFSET 4 + +/** + * omap4_prm_is_hardreset_asserted - read the HW reset line state of + * submodules contained in the hwmod module + * @rstctrl_reg: RM_RSTCTRL register address for this module + * @shift: register bit shift corresponding to the reset line to check + * + * Returns 1 if the (sub)module hardreset line is currently asserted, + * 0 if the (sub)module hardreset line is not currently asserted, or + * -EINVAL upon parameter error. + */ +int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift) +{ + if (!cpu_is_omap44xx() || !rstctrl_reg) + return -EINVAL; + + return omap4_prm_read_bits_shift(rstctrl_reg, (1 << shift)); +} + +/** + * omap4_prm_assert_hardreset - assert the HW reset line of a submodule + * @rstctrl_reg: RM_RSTCTRL register address for this module + * @shift: register bit shift corresponding to the reset line to assert + * + * Some IPs like dsp, ipu or iva contain processors that require an HW + * reset line to be asserted / deasserted in order to fully enable the + * IP. These modules may have multiple hard-reset lines that reset + * different 'submodules' inside the IP block. This function will + * place the submodule into reset. Returns 0 upon success or -EINVAL + * upon an argument error. + */ +int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift) +{ + u32 mask; + + if (!cpu_is_omap44xx() || !rstctrl_reg) + return -EINVAL; + + mask = 1 << shift; + omap4_prm_rmw_reg_bits(mask, mask, rstctrl_reg); + + return 0; +} + +/** + * omap4_prm_deassert_hardreset - deassert a submodule hardreset line and wait + * @rstctrl_reg: RM_RSTCTRL register address for this module + * @shift: register bit shift corresponding to the reset line to deassert + * + * Some IPs like dsp, ipu or iva contain processors that require an HW + * reset line to be asserted / deasserted in order to fully enable the + * IP. These modules may have multiple hard-reset lines that reset + * different 'submodules' inside the IP block. This function will + * take the submodule out of reset and wait until the PRCM indicates + * that the reset has completed before returning. Returns 0 upon success or + * -EINVAL upon an argument error, -EEXIST if the submodule was already out + * of reset, or -EBUSY if the submodule did not exit reset promptly. + */ +int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift) +{ + u32 mask; + void __iomem *rstst_reg; + int c; + + if (!cpu_is_omap44xx() || !rstctrl_reg) + return -EINVAL; + + rstst_reg = rstctrl_reg + OMAP4_RST_CTRL_ST_OFFSET; + + mask = 1 << shift; + + /* Check the current status to avoid de-asserting the line twice */ + if (omap4_prm_read_bits_shift(rstctrl_reg, mask) == 0) + return -EEXIST; + + /* Clear the reset status by writing 1 to the status bit */ + omap4_prm_rmw_reg_bits(0xffffffff, mask, rstst_reg); + /* de-assert the reset control line */ + omap4_prm_rmw_reg_bits(mask, 0, rstctrl_reg); + /* wait the status to be set */ + omap_test_timeout(omap4_prm_read_bits_shift(rstst_reg, mask), + MAX_MODULE_HARDRESET_WAIT, c); + + return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0; +} + -- cgit v1.1 From cf21405fd51b416f071edb546631a6ecd2112263 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Tue, 21 Sep 2010 10:34:10 -0600 Subject: OMAP2/3: PRM: add module hard reset support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch adds hard-reset support for processor modules (e.g., DSP, IVA) on OMAP2/3 platforms. It's based on the OMAP4 hard-reset support that Benoît developed in the previous patch. This patch is a collaboration between Benoît Cousson and Paul Walmsley . Signed-off-by: Paul Walmsley Cc: Benoît Cousson --- arch/arm/mach-omap2/Makefile | 2 +- arch/arm/mach-omap2/prm.h | 5 ++ arch/arm/mach-omap2/prm2xxx_3xxx.c | 110 +++++++++++++++++++++++++++++++++++++ 3 files changed, 116 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-omap2/prm2xxx_3xxx.c (limited to 'arch') diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index c0da784..eb2504a 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -5,7 +5,7 @@ # Common support obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o pm.o -omap-2-3-common = irq.o sdrc.o +omap-2-3-common = irq.o sdrc.o prm2xxx_3xxx.o hwmod-common = omap_hwmod.o \ omap_hwmod_common_data.o prcm-common = prcm.o powerdomain.o diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h index bc7e6e6..7be040b 100644 --- a/arch/arm/mach-omap2/prm.h +++ b/arch/arm/mach-omap2/prm.h @@ -246,6 +246,11 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) return prm_rmw_mod_reg_bits(bits, 0x0, module, idx); } +/* These omap2_ PRM functions apply to both OMAP2 and 3 */ +int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift); +int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift); +int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift); + int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift); int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift); int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift); diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c new file mode 100644 index 0000000..421771e --- /dev/null +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c @@ -0,0 +1,110 @@ +/* + * OMAP2/3 PRM module functions + * + * Copyright (C) 2010 Texas Instruments, Inc. + * Copyright (C) 2010 Nokia Corporation + * Benoît Cousson + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include +#include +#include + +#include "prm.h" +#include "prm-regbits-24xx.h" +#include "prm-regbits-34xx.h" + +/** + * omap2_prm_is_hardreset_asserted - read the HW reset line state of + * submodules contained in the hwmod module + * @prm_mod: PRM submodule base (e.g. CORE_MOD) + * @shift: register bit shift corresponding to the reset line to check + * + * Returns 1 if the (sub)module hardreset line is currently asserted, + * 0 if the (sub)module hardreset line is not currently asserted, or + * -EINVAL if called while running on a non-OMAP2/3 chip. + */ +int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift) +{ + if (!(cpu_is_omap24xx() || cpu_is_omap34xx())) + return -EINVAL; + + return prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, + (1 << shift)); +} + +/** + * omap2_prm_assert_hardreset - assert the HW reset line of a submodule + * @prm_mod: PRM submodule base (e.g. CORE_MOD) + * @shift: register bit shift corresponding to the reset line to assert + * + * Some IPs like dsp or iva contain processors that require an HW + * reset line to be asserted / deasserted in order to fully enable the + * IP. These modules may have multiple hard-reset lines that reset + * different 'submodules' inside the IP block. This function will + * place the submodule into reset. Returns 0 upon success or -EINVAL + * upon an argument error. + */ +int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift) +{ + u32 mask; + + if (!(cpu_is_omap24xx() || cpu_is_omap34xx())) + return -EINVAL; + + mask = 1 << shift; + prm_rmw_mod_reg_bits(mask, mask, prm_mod, OMAP2_RM_RSTCTRL); + + return 0; +} + +/** + * omap2_prm_deassert_hardreset - deassert a submodule hardreset line and wait + * @prm_mod: PRM submodule base (e.g. CORE_MOD) + * @shift: register bit shift corresponding to the reset line to deassert + * + * Some IPs like dsp or iva contain processors that require an HW + * reset line to be asserted / deasserted in order to fully enable the + * IP. These modules may have multiple hard-reset lines that reset + * different 'submodules' inside the IP block. This function will + * take the submodule out of reset and wait until the PRCM indicates + * that the reset has completed before returning. Returns 0 upon success or + * -EINVAL upon an argument error, -EEXIST if the submodule was already out + * of reset, or -EBUSY if the submodule did not exit reset promptly. + */ +int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift) +{ + u32 mask; + int c; + + if (!(cpu_is_omap24xx() || cpu_is_omap34xx())) + return -EINVAL; + + mask = 1 << shift; + + /* Check the current status to avoid de-asserting the line twice */ + if (prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, mask) == 0) + return -EEXIST; + + /* Clear the reset status by writing 1 to the status bit */ + prm_rmw_mod_reg_bits(0xffffffff, mask, prm_mod, OMAP2_RM_RSTST); + /* de-assert the reset control line */ + prm_rmw_mod_reg_bits(mask, 0, prm_mod, OMAP2_RM_RSTCTRL); + /* wait the status to be set */ + omap_test_timeout(prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTST, + mask), + MAX_MODULE_HARDRESET_WAIT, c); + + return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0; +} + -- cgit v1.1 From 5365efbe29250a227502256cc912351fe2157b42 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Cousson?= Date: Tue, 21 Sep 2010 10:34:11 -0600 Subject: OMAP: hwmod: Add hardreset management support Most processor IPs does have a hardreset signal controlled by the PRM. This is different of the softreset used for local IP reset from the SYSCONFIG register. The granularity can be much finer than orginal HWMOD, for ex, the IVA hwmod contains 3 reset lines, the IPU 3 as well, the DSP 2... Since this granularity is needed by the driver, we have to ensure than one hwmod exist for each hardreset line. - Store reset lines as hwmod resources that a driver can query by name like an irq or sdma line. - Add two functions for asserting / deasserting reset lines in hwmods processor that require manual reset control. - Add one functions to get the current reset state. - If an hwmod contains only one line, an automatic assertion / de-assertion is done. -> de-assert the hardreset line only during enable from disable transition -> assert the hardreset line only during shutdown Note: The hwmods with hardreset line and HWMOD_INIT_NO_RESET flag must be kept in INITIALIZED state. They can be properly enabled only if the hardreset line is de-asserted before. For information here is the list of IPs with HW reset control on an OMAP4430 device: RM_DSP_RSTCTRL 1,1,'RST2','RW','1','DSP - MMU, cache and slave interface reset control' 0,0,'RST1','RW','1','DSP - DSP reset control' RM_IVA_RSTCTRL 2,2,'RST3','RW','1','IVA logic and SL2 reset control' 1,1,'RST2','RW','1','IVA Sequencer2 reset control' 0,0,'RST1','RW','1','IVA sequencer1 reset control' RM_IPU_RSTCTRL 2,2,'RST3','RW','1','IPU MMU and CACHE interface reset control.' 1,1,'RST2','RW','1','IPU Cortex M3 CPU2 reset control.' 0,0,'RST1','RW','1','IPU Cortex M3 CPU1 reset control.' PRM_RSTCTRL 1,1,'RST_GLOBAL_COLD_SW','RW','0','Global COLD software reset control.' 0,0,'RST_GLOBAL_WARM_SW','RW','0','Global WARM software reset control.' RM_CPU0_CPU0_RSTCTRL RM_CPU1_CPU1_RSTCTRL 0,0,'RST','RW','0','Cortex A9 CPU0&1 warm local reset control' Signed-off-by: Benoit Cousson [paul@pwsan.com: made the hardreset functions static; moved the register twiddling into prm*.c functions in previous patches; changed the function names to conform with hwmod practice] Signed-off-by: Paul Walmsley Cc: Kevin Hilman Cc: Rajendra Nayak --- arch/arm/mach-omap2/omap_hwmod.c | 168 +++++++++++++++++++++++++-- arch/arm/plat-omap/include/plat/omap_hwmod.h | 17 +++ 2 files changed, 177 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 3084409..f4a569c 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -50,11 +50,13 @@ #include #include #include +#include #include "cm.h" +#include "prm.h" -/* Maximum microseconds to wait for OMAP module to reset */ -#define MAX_MODULE_RESET_WAIT 10000 +/* Maximum microseconds to wait for OMAP module to softreset */ +#define MAX_MODULE_SOFTRESET_WAIT 10000 /* Name of the OMAP hwmod for the MPU */ #define MPU_INITIATOR_NAME "mpu" @@ -834,6 +836,130 @@ static int _wait_target_ready(struct omap_hwmod *oh) } /** + * _lookup_hardreset - return the register bit shift for this hwmod/reset line + * @oh: struct omap_hwmod * + * @name: name of the reset line in the context of this hwmod + * + * Return the bit position of the reset line that match the + * input name. Return -ENOENT if not found. + */ +static u8 _lookup_hardreset(struct omap_hwmod *oh, const char *name) +{ + int i; + + for (i = 0; i < oh->rst_lines_cnt; i++) { + const char *rst_line = oh->rst_lines[i].name; + if (!strcmp(rst_line, name)) { + u8 shift = oh->rst_lines[i].rst_shift; + pr_debug("omap_hwmod: %s: _lookup_hardreset: %s: %d\n", + oh->name, rst_line, shift); + + return shift; + } + } + + return -ENOENT; +} + +/** + * _assert_hardreset - assert the HW reset line of submodules + * contained in the hwmod module. + * @oh: struct omap_hwmod * + * @name: name of the reset line to lookup and assert + * + * Some IP like dsp, ipu or iva contain processor that require + * an HW reset line to be assert / deassert in order to enable fully + * the IP. + */ +static int _assert_hardreset(struct omap_hwmod *oh, const char *name) +{ + u8 shift; + + if (!oh) + return -EINVAL; + + shift = _lookup_hardreset(oh, name); + if (IS_ERR_VALUE(shift)) + return shift; + + if (cpu_is_omap24xx() || cpu_is_omap34xx()) + return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs, + shift); + else if (cpu_is_omap44xx()) + return omap4_prm_assert_hardreset(oh->prcm.omap4.rstctrl_reg, + shift); + else + return -EINVAL; +} + +/** + * _deassert_hardreset - deassert the HW reset line of submodules contained + * in the hwmod module. + * @oh: struct omap_hwmod * + * @name: name of the reset line to look up and deassert + * + * Some IP like dsp, ipu or iva contain processor that require + * an HW reset line to be assert / deassert in order to enable fully + * the IP. + */ +static int _deassert_hardreset(struct omap_hwmod *oh, const char *name) +{ + u8 shift; + int r; + + if (!oh) + return -EINVAL; + + shift = _lookup_hardreset(oh, name); + if (IS_ERR_VALUE(shift)) + return shift; + + if (cpu_is_omap24xx() || cpu_is_omap34xx()) + r = omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs, + shift); + else if (cpu_is_omap44xx()) + r = omap4_prm_deassert_hardreset(oh->prcm.omap4.rstctrl_reg, + shift); + else + return -EINVAL; + + if (r == -EBUSY) + pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name); + + return r; +} + +/** + * _read_hardreset - read the HW reset line state of submodules + * contained in the hwmod module + * @oh: struct omap_hwmod * + * @name: name of the reset line to look up and read + * + * Return the state of the reset line. + */ +static int _read_hardreset(struct omap_hwmod *oh, const char *name) +{ + u8 shift; + + if (!oh) + return -EINVAL; + + shift = _lookup_hardreset(oh, name); + if (IS_ERR_VALUE(shift)) + return shift; + + if (cpu_is_omap24xx() || cpu_is_omap34xx()) { + return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs, + shift); + } else if (cpu_is_omap44xx()) { + return omap4_prm_is_hardreset_asserted(oh->prcm.omap4.rstctrl_reg, + shift); + } else { + return -EINVAL; + } +} + +/** * _reset - reset an omap_hwmod * @oh: struct omap_hwmod * * @@ -869,20 +995,20 @@ static int _reset(struct omap_hwmod *oh) omap_test_timeout((omap_hwmod_readl(oh, oh->class->sysc->syss_offs) & SYSS_RESETDONE_MASK), - MAX_MODULE_RESET_WAIT, c); + MAX_MODULE_SOFTRESET_WAIT, c); - if (c == MAX_MODULE_RESET_WAIT) - WARN(1, "omap_hwmod: %s: failed to reset in %d usec\n", - oh->name, MAX_MODULE_RESET_WAIT); + if (c == MAX_MODULE_SOFTRESET_WAIT) + WARN(1, "omap_hwmod: %s: softreset failed (waited %d usec)\n", + oh->name, MAX_MODULE_SOFTRESET_WAIT); else - pr_debug("omap_hwmod: %s: reset in %d usec\n", oh->name, c); + pr_debug("omap_hwmod: %s: softreset in %d usec\n", oh->name, c); /* * XXX add _HWMOD_STATE_WEDGED for modules that don't come back from * _wait_target_ready() or _reset() */ - return (c == MAX_MODULE_RESET_WAIT) ? -ETIMEDOUT : 0; + return (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0; } /** @@ -907,6 +1033,15 @@ int _omap_hwmod_enable(struct omap_hwmod *oh) pr_debug("omap_hwmod: %s: enabling\n", oh->name); + /* + * If an IP contains only one HW reset line, then de-assert it in order + * to allow to enable the clocks. Otherwise the PRCM will return + * Intransition status, and the init will failed. + */ + if ((oh->_state == _HWMOD_STATE_INITIALIZED || + oh->_state == _HWMOD_STATE_DISABLED) && oh->rst_lines_cnt == 1) + _deassert_hardreset(oh, oh->rst_lines[0].name); + /* XXX mux balls */ _add_initiator_dep(oh, mpu_oh); @@ -981,6 +1116,13 @@ static int _shutdown(struct omap_hwmod *oh) if (oh->class->sysc) _sysc_shutdown(oh); + /* + * If an IP contains only one HW reset line, then assert it + * before disabling the clocks and shutting down the IP. + */ + if (oh->rst_lines_cnt == 1) + _assert_hardreset(oh, oh->rst_lines[0].name); + /* clocks and deps are already disabled in idle */ if (oh->_state == _HWMOD_STATE_ENABLED) { _del_initiator_dep(oh, mpu_oh); @@ -1038,6 +1180,16 @@ static int _setup(struct omap_hwmod *oh, void *data) mutex_init(&oh->_mutex); oh->_state = _HWMOD_STATE_INITIALIZED; + /* + * In the case of hwmod with hardreset that should not be + * de-assert at boot time, we have to keep the module + * initialized, because we cannot enable it properly with the + * reset asserted. Exit without warning because that behavior is + * expected. + */ + if ((oh->flags & HWMOD_INIT_NO_RESET) && oh->rst_lines_cnt == 1) + return 0; + r = _omap_hwmod_enable(oh); if (r) { pr_warning("omap_hwmod: %s: cannot be enabled (%d)\n", diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index 03350ba..590bfae 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -109,6 +109,19 @@ struct omap_hwmod_dma_info { }; /** + * struct omap_hwmod_rst_info - IPs reset lines use by hwmod + * @name: name of the reset line (module local name) + * @rst_shift: Offset of the reset bit + * + * @name should be something short, e.g., "cpu0" or "rst". It is defined + * locally to the hwmod. + */ +struct omap_hwmod_rst_info { + const char *name; + u8 rst_shift; +}; + +/** * struct omap_hwmod_opt_clk - optional clocks used by this hwmod * @role: "sys", "32k", "tv", etc -- for use in clk_get() * @clk: opt clock: OMAP clock name @@ -328,10 +341,12 @@ struct omap_hwmod_omap2_prcm { /** * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data * @clkctrl_reg: PRCM address of the clock control register + * @rstctrl_reg: adress of the XXX_RSTCTRL register located in the PRM * @submodule_wkdep_bit: bit shift of the WKDEP range */ struct omap_hwmod_omap4_prcm { void __iomem *clkctrl_reg; + void __iomem *rstctrl_reg; u8 submodule_wkdep_bit; }; @@ -451,6 +466,7 @@ struct omap_hwmod { struct omap_device *od; struct omap_hwmod_irq_info *mpu_irqs; struct omap_hwmod_dma_info *sdma_reqs; + struct omap_hwmod_rst_info *rst_lines; union { struct omap_hwmod_omap2_prcm omap2; struct omap_hwmod_omap4_prcm omap4; @@ -472,6 +488,7 @@ struct omap_hwmod { u8 response_lat; u8 mpu_irqs_cnt; u8 sdma_reqs_cnt; + u8 rst_lines_cnt; u8 opt_clks_cnt; u8 masters_cnt; u8 slaves_cnt; -- cgit v1.1 From 76e5589e5b7cd0fd589264ab193f10550e1d8ab6 Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Tue, 21 Sep 2010 10:34:11 -0600 Subject: OMAP: hwmod: Force a softreset during _setup Force the softreset of every IPs during the _setup phase. IPs that cannot support softreset or that should not be reset must set the HWMOD_INIT_NO_RESET flag in the hwmod struct. Signed-off-by: Benoit Cousson Signed-off-by: Paul Walmsley Tested-by: Kevin Hilman --- arch/arm/mach-omap2/omap_hwmod.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index f4a569c..3e90984 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -980,8 +980,8 @@ static int _reset(struct omap_hwmod *oh) /* clocks must be on for this operation */ if (oh->_state != _HWMOD_STATE_ENABLED) { - WARN(1, "omap_hwmod: %s: reset can only be entered from " - "enabled state\n", oh->name); + pr_warning("omap_hwmod: %s: reset can only be entered from " + "enabled state\n", oh->name); return -EINVAL; } @@ -998,8 +998,8 @@ static int _reset(struct omap_hwmod *oh) MAX_MODULE_SOFTRESET_WAIT, c); if (c == MAX_MODULE_SOFTRESET_WAIT) - WARN(1, "omap_hwmod: %s: softreset failed (waited %d usec)\n", - oh->name, MAX_MODULE_SOFTRESET_WAIT); + pr_warning("omap_hwmod: %s: softreset failed (waited %d usec)\n", + oh->name, MAX_MODULE_SOFTRESET_WAIT); else pr_debug("omap_hwmod: %s: softreset in %d usec\n", oh->name, c); @@ -1198,12 +1198,12 @@ static int _setup(struct omap_hwmod *oh, void *data) } if (!(oh->flags & HWMOD_INIT_NO_RESET)) { + _reset(oh); + /* - * XXX Do the OCP_SYSCONFIG bits need to be - * reprogrammed after a reset? If not, then this can - * be removed. If they do, then probably the - * _omap_hwmod_enable() function should be split to avoid the - * rewrite of the OCP_SYSCONFIG register. + * OCP_SYSCONFIG bits need to be reprogrammed after a softreset. + * The _omap_hwmod_enable() function should be split to + * avoid the rewrite of the OCP_SYSCONFIG register. */ if (oh->class->sysc) { _update_sysc_cache(oh); -- cgit v1.1 From aee48e3c9cee3698d17b4cf4203551de0a804760 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Tue, 21 Sep 2010 10:34:11 -0600 Subject: OMAP: hwmod: add an hardreset API for use by other core code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Expose an hardreset API from hwmod in order to assert / deassert all the individual reset lines that belong to an hwmod. This API is needed by some of the more complicated processor drivers, e.g., DSP/Bridge, Syslink, etc. Signed-off-by: Paul Walmsley Cc: Benoît Cousson --- arch/arm/mach-omap2/omap_hwmod.c | 78 ++++++++++++++++++++++++++++ arch/arm/plat-omap/include/plat/omap_hwmod.h | 4 ++ 2 files changed, 82 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 3e90984..8c27923 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -1829,6 +1829,84 @@ int omap_hwmod_disable_wakeup(struct omap_hwmod *oh) } /** + * omap_hwmod_assert_hardreset - assert the HW reset line of submodules + * contained in the hwmod module. + * @oh: struct omap_hwmod * + * @name: name of the reset line to lookup and assert + * + * Some IP like dsp, ipu or iva contain processor that require + * an HW reset line to be assert / deassert in order to enable fully + * the IP. Returns -EINVAL if @oh is null or if the operation is not + * yet supported on this OMAP; otherwise, passes along the return value + * from _assert_hardreset(). + */ +int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name) +{ + int ret; + + if (!oh) + return -EINVAL; + + mutex_lock(&oh->_mutex); + ret = _assert_hardreset(oh, name); + mutex_unlock(&oh->_mutex); + + return ret; +} + +/** + * omap_hwmod_deassert_hardreset - deassert the HW reset line of submodules + * contained in the hwmod module. + * @oh: struct omap_hwmod * + * @name: name of the reset line to look up and deassert + * + * Some IP like dsp, ipu or iva contain processor that require + * an HW reset line to be assert / deassert in order to enable fully + * the IP. Returns -EINVAL if @oh is null or if the operation is not + * yet supported on this OMAP; otherwise, passes along the return value + * from _deassert_hardreset(). + */ +int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name) +{ + int ret; + + if (!oh) + return -EINVAL; + + mutex_lock(&oh->_mutex); + ret = _deassert_hardreset(oh, name); + mutex_unlock(&oh->_mutex); + + return ret; +} + +/** + * omap_hwmod_read_hardreset - read the HW reset line state of submodules + * contained in the hwmod module + * @oh: struct omap_hwmod * + * @name: name of the reset line to look up and read + * + * Return the current state of the hwmod @oh's reset line named @name: + * returns -EINVAL upon parameter error or if this operation + * is unsupported on the current OMAP; otherwise, passes along the return + * value from _read_hardreset(). + */ +int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name) +{ + int ret; + + if (!oh) + return -EINVAL; + + mutex_lock(&oh->_mutex); + ret = _read_hardreset(oh, name); + mutex_unlock(&oh->_mutex); + + return ret; +} + + +/** * omap_hwmod_for_each_by_class - call @fn for each hwmod of class @classname * @classname: struct omap_hwmod_class name to search for * @fn: callback function pointer to call for each hwmod in class @classname diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index 590bfae..7fde44d 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -512,6 +512,10 @@ int omap_hwmod_idle(struct omap_hwmod *oh); int _omap_hwmod_idle(struct omap_hwmod *oh); int omap_hwmod_shutdown(struct omap_hwmod *oh); +int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name); +int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name); +int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name); + int omap_hwmod_enable_clocks(struct omap_hwmod *oh); int omap_hwmod_disable_clocks(struct omap_hwmod *oh); -- cgit v1.1 From 2cb068149c365f1c2b10f2ece6786139527dcc16 Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Tue, 21 Sep 2010 18:57:59 +0200 Subject: OMAP: hwmod: Fix softreset status check for some new OMAP4 IPs In OMAP3 a specific SYSSTATUS register was used to get the softreset status. Starting in OMAP4, some IPs does not have SYSSTATUS register and instead use the SYSC softreset bit to provide the status. Other cases might exist: - Some IPs like McBSP does have a softreset control but no reset status. - Some IPs that represent subsystem, like the DSS, can contains a reset status without softreset control. The status is the aggregation of all the sub modules reset status. - Add a new flag (SYSC_HAS_RESET_STATUS) to identify the new programming model and replace the previous SYSS_MISSING, that was used to flag IP with softreset control but without the SYSSTATUS register, with a specific SYSS_HAS_RESET_STATUS flag. - MCSPI and MMC contains both programming models, so the legacy one will be prevented by removing the syss offset field that become useless. Signed-off-by: Benoit Cousson Signed-off-by: Paul Walmsley Cc: Kevin Hilman Cc: Rajendra Nayak --- arch/arm/mach-omap2/omap_hwmod.c | 22 +++++++++++++++++----- arch/arm/plat-omap/include/plat/omap_hwmod.h | 3 ++- 2 files changed, 19 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 8c27923..5027879b 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -967,6 +967,12 @@ static int _read_hardreset(struct omap_hwmod *oh, const char *name) * enabled for this to work. Returns -EINVAL if the hwmod cannot be * reset this way or if the hwmod is in the wrong state, -ETIMEDOUT if * the module did not reset in time, or 0 upon success. + * + * In OMAP3 a specific SYSSTATUS register is used to get the reset status. + * Starting in OMAP4, some IPs does not have SYSSTATUS register and instead + * use the SYSCONFIG softreset bit to provide the status. + * + * Note that some IP like McBSP does have a reset control but no reset status. */ static int _reset(struct omap_hwmod *oh) { @@ -974,8 +980,7 @@ static int _reset(struct omap_hwmod *oh) int c = 0; if (!oh->class->sysc || - !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET) || - (oh->class->sysc->sysc_flags & SYSS_MISSING)) + !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) return -EINVAL; /* clocks must be on for this operation */ @@ -993,9 +998,16 @@ static int _reset(struct omap_hwmod *oh) return r; _write_sysconfig(v, oh); - omap_test_timeout((omap_hwmod_readl(oh, oh->class->sysc->syss_offs) & - SYSS_RESETDONE_MASK), - MAX_MODULE_SOFTRESET_WAIT, c); + if (oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS) + omap_test_timeout((omap_hwmod_readl(oh, + oh->class->sysc->syss_offs) + & SYSS_RESETDONE_MASK), + MAX_MODULE_SOFTRESET_WAIT, c); + else if (oh->class->sysc->sysc_flags & SYSC_HAS_RESET_STATUS) + omap_test_timeout(!(omap_hwmod_readl(oh, + oh->class->sysc->sysc_offs) + & SYSC_TYPE2_SOFTRESET_MASK), + MAX_MODULE_SOFTRESET_WAIT, c); if (c == MAX_MODULE_SOFTRESET_WAIT) pr_warning("omap_hwmod: %s: softreset failed (waited %d usec)\n", diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index 7fde44d..faa0827 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -251,8 +251,9 @@ struct omap_hwmod_ocp_if { #define SYSC_HAS_CLOCKACTIVITY (1 << 4) #define SYSC_HAS_SIDLEMODE (1 << 5) #define SYSC_HAS_MIDLEMODE (1 << 6) -#define SYSS_MISSING (1 << 7) +#define SYSS_HAS_RESET_STATUS (1 << 7) #define SYSC_NO_CACHE (1 << 8) /* XXX SW flag, belongs elsewhere */ +#define SYSC_HAS_RESET_STATUS (1 << 9) /* omap_hwmod_sysconfig.clockact flags */ #define CLOCKACT_TEST_BOTH 0x0 -- cgit v1.1 From 96835af970e5d6aeedf868e53590a947be5e4a7a Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Tue, 21 Sep 2010 18:57:58 +0200 Subject: OMAP: hwmod: Fix softreset for modules with optional clocks Some modules (like GPIO, DSS...) require optionals clock to be enabled in order to complete the sofreset properly. Add a HWMOD_CONTROL_OPT_CLKS_IN_RESET flag to force all optional clocks to be enabled before reset. Disabled them once the reset is done. TODO: For the moment it is very hard to understand from the HW spec, which optional clock is needed and which one is not. So the current approach will enable all the optional clocks. Paul proposed a much finer approach that will allow to tag only the needed clock in the optional clock table. This might be doable as soon as we have a clear understanding of these dependencies. Reported-by: Partha Basak Signed-off-by: Benoit Cousson Signed-off-by: Paul Walmsley Cc: Kevin Hilman --- arch/arm/mach-omap2/omap_hwmod.c | 51 +++++++++++++++++++++++++--- arch/arm/plat-omap/include/plat/omap_hwmod.h | 5 +++ 2 files changed, 51 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 5027879b..f320cfb 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -546,6 +546,36 @@ static int _disable_clocks(struct omap_hwmod *oh) return 0; } +static void _enable_optional_clocks(struct omap_hwmod *oh) +{ + struct omap_hwmod_opt_clk *oc; + int i; + + pr_debug("omap_hwmod: %s: enabling optional clocks\n", oh->name); + + for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) + if (oc->_clk) { + pr_debug("omap_hwmod: enable %s:%s\n", oc->role, + oc->_clk->name); + clk_enable(oc->_clk); + } +} + +static void _disable_optional_clocks(struct omap_hwmod *oh) +{ + struct omap_hwmod_opt_clk *oc; + int i; + + pr_debug("omap_hwmod: %s: disabling optional clocks\n", oh->name); + + for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) + if (oc->_clk) { + pr_debug("omap_hwmod: disable %s:%s\n", oc->role, + oc->_clk->name); + clk_disable(oc->_clk); + } +} + /** * _find_mpu_port_index - find hwmod OCP slave port ID intended for MPU use * @oh: struct omap_hwmod * @@ -976,8 +1006,9 @@ static int _read_hardreset(struct omap_hwmod *oh, const char *name) */ static int _reset(struct omap_hwmod *oh) { - u32 r, v; + u32 v; int c = 0; + int ret = 0; if (!oh->class->sysc || !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) @@ -990,12 +1021,16 @@ static int _reset(struct omap_hwmod *oh) return -EINVAL; } + /* For some modules, all optionnal clocks need to be enabled as well */ + if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) + _enable_optional_clocks(oh); + pr_debug("omap_hwmod: %s: resetting\n", oh->name); v = oh->_sysc_cache; - r = _set_softreset(oh, &v); - if (r) - return r; + ret = _set_softreset(oh, &v); + if (ret) + goto dis_opt_clks; _write_sysconfig(v, oh); if (oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS) @@ -1020,7 +1055,13 @@ static int _reset(struct omap_hwmod *oh) * _wait_target_ready() or _reset() */ - return (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0; + ret = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0; + +dis_opt_clks: + if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) + _disable_optional_clocks(oh); + + return ret; } /** diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index faa0827..ee53758 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -369,6 +369,10 @@ struct omap_hwmod_omap4_prcm { * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup * HWMOD_NO_IDLEST : this module does not have idle status - this is the case * only for few initiator modules on OMAP2 & 3. + * HWMOD_CONTROL_OPT_CLKS_IN_RESET: Enable all optional clocks during reset. + * This is needed for devices like DSS that require optional clocks enabled + * in order to complete the reset. Optional clocks will be disabled + * again after the reset. */ #define HWMOD_SWSUP_SIDLE (1 << 0) #define HWMOD_SWSUP_MSTANDBY (1 << 1) @@ -377,6 +381,7 @@ struct omap_hwmod_omap4_prcm { #define HWMOD_NO_OCP_AUTOIDLE (1 << 4) #define HWMOD_SET_DEFAULT_CLOCKACT (1 << 5) #define HWMOD_NO_IDLEST (1 << 6) +#define HWMOD_CONTROL_OPT_CLKS_IN_RESET (1 << 7) /* * omap_hwmod._int_flags definitions -- cgit v1.1 From 9980ce53c97392a3dbdc9d1ac3e455d79b4167ed Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Tue, 21 Sep 2010 19:58:30 +0530 Subject: OMAP: hwmod: Enable module wakeup if in smartidle MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If a module's OCP slave port is programmed to be in smartidle, its also necessary that they have module level wakeup enabled. Update _sysc_enable in hwmod framework to do this. The thread "[PATCH 7/8] : Hwmod api changes" archived here: http://www.mail-archive.com/linux-omap@vger.kernel.org/msg34212.html has additional technical information on the rationale of this patch. Sergei Shtylyov identified an indentation problem with this patch - thanks, Sergei. Signed-off-by: Rajendra Nayak Signed-off-by: Partha Basak Signed-off-by: Benoît Cousson [paul@pwsan.com: revised patch description] Signed-off-by: Paul Walmsley Cc: Kevin Hilman Cc: Sergei Shtylyov --- arch/arm/mach-omap2/omap_hwmod.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index f320cfb..d694067 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -691,8 +691,6 @@ static void _sysc_enable(struct omap_hwmod *oh) _set_module_autoidle(oh, idlemode, &v); } - /* XXX OCP ENAWAKEUP bit? */ - /* * XXX The clock framework should handle this, by * calling into this code. But this must wait until the @@ -703,6 +701,10 @@ static void _sysc_enable(struct omap_hwmod *oh) _set_clockactivity(oh, oh->class->sysc->clockact, &v); _write_sysconfig(v, oh); + + /* If slave is in SMARTIDLE, also enable wakeup */ + if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE)) + _enable_wakeup(oh); } /** -- cgit v1.1 From 4ef7aca895b2d06c07ff9d5f378af84bbf757e43 Mon Sep 17 00:00:00 2001 From: Partha Basak Date: Tue, 21 Sep 2010 19:23:04 +0200 Subject: OMAP: hwmod: Handle opt clocks node using clk_add_alias For every optional clock present per hwmod per omap-device, this function adds an entry in the clocks list of the form , if an entry is already present in the list of the form . The function is called from within the framework inside omap_device_build_ss(), after omap_device_register. This allows drivers to get a pointer to its optional clocks based on its role by calling clk_get(, ). Link to discussions related to this patch: http://www.spinics.net/lists/linux-omap/msg34809.html Signed-off-by: Charulatha V Signed-off-by: Partha Basak Signed-off-by: Benoit Cousson Signed-off-by: Rajendra Nayak [paul@pwsan.com: simplified loop iterator; removed the superfluous clk_get(), using the clk_get() in clk_add_alias() instead] Signed-off-by: Paul Walmsley Acked-by: Kevin Hilman --- arch/arm/plat-omap/omap_device.c | 43 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c index d2b1609..ceba58a 100644 --- a/arch/arm/plat-omap/omap_device.c +++ b/arch/arm/plat-omap/omap_device.c @@ -82,6 +82,7 @@ #include #include #include +#include #include #include @@ -243,6 +244,44 @@ static inline struct omap_device *_find_by_pdev(struct platform_device *pdev) return container_of(pdev, struct omap_device, pdev); } +/** + * _add_optional_clock_alias - Add clock alias for hwmod optional clocks + * @od: struct omap_device *od + * + * For every optional clock present per hwmod per omap_device, this function + * adds an entry in the clocks list of the form + * if an entry is already present in it with the form + * + * The function is called from inside omap_device_build_ss(), after + * omap_device_register. + * + * This allows drivers to get a pointer to its optional clocks based on its role + * by calling clk_get(, ). + * + * No return value. + */ +static void _add_optional_clock_alias(struct omap_device *od, + struct omap_hwmod *oh) +{ + int i; + + for (i = 0; i < oh->opt_clks_cnt; i++) { + struct omap_hwmod_opt_clk *oc; + int r; + + oc = &oh->opt_clks[i]; + + if (!oc->_clk) + continue; + + r = clk_add_alias(oc->role, dev_name(&od->pdev.dev), + (char *)oc->clk, &od->pdev.dev); + if (r) + pr_err("omap_device: %s: clk_add_alias for %s failed\n", + dev_name(&od->pdev.dev), oc->role); + } +} + /* Public functions for use by core code */ @@ -421,8 +460,10 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id, else ret = omap_device_register(od); - for (i = 0; i < oh_cnt; i++) + for (i = 0; i < oh_cnt; i++) { hwmods[i]->od = od; + _add_optional_clock_alias(od, hwmods[i]); + } if (ret) goto odbs_exit4; -- cgit v1.1 From 74ff3a68ed11f1e9eede4fe301f42cc3cdf7396a Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Tue, 21 Sep 2010 15:02:23 -0600 Subject: OMAP: hwmod: improve documentation, clean up function names MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch: - adds more documentation to the hwmod code - fixes some documentation typos elsewhere in the file - changes the _sysc_*() function names to appear in (verb, noun) order, to match the rest of the function names. This patch should not result in any functional change. Signed-off-by: Paul Walmsley Cc: Kevin Hilman Cc: Benoît Cousson --- arch/arm/mach-omap2/omap_hwmod.c | 141 ++++++++++++++++++++++----- arch/arm/plat-omap/include/plat/omap_hwmod.h | 11 +-- 2 files changed, 123 insertions(+), 29 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index d694067..c3a5889 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -13,10 +13,102 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * - * This code manages "OMAP modules" (on-chip devices) and their - * integration with Linux device driver and bus code. - * - * References: + * Introduction + * ------------ + * One way to view an OMAP SoC is as a collection of largely unrelated + * IP blocks connected by interconnects. The IP blocks include + * devices such as ARM processors, audio serial interfaces, UARTs, + * etc. Some of these devices, like the DSP, are created by TI; + * others, like the SGX, largely originate from external vendors. In + * TI's documentation, on-chip devices are referred to as "OMAP + * modules." Some of these IP blocks are identical across several + * OMAP versions. Others are revised frequently. + * + * These OMAP modules are tied together by various interconnects. + * Most of the address and data flow between modules is via OCP-based + * interconnects such as the L3 and L4 buses; but there are other + * interconnects that distribute the hardware clock tree, handle idle + * and reset signaling, supply power, and connect the modules to + * various pads or balls on the OMAP package. + * + * OMAP hwmod provides a consistent way to describe the on-chip + * hardware blocks and their integration into the rest of the chip. + * This description can be automatically generated from the TI + * hardware database. OMAP hwmod provides a standard, consistent API + * to reset, enable, idle, and disable these hardware blocks. And + * hwmod provides a way for other core code, such as the Linux device + * code or the OMAP power management and address space mapping code, + * to query the hardware database. + * + * Using hwmod + * ----------- + * Drivers won't call hwmod functions directly. That is done by the + * omap_device code, and in rare occasions, by custom integration code + * in arch/arm/ *omap*. The omap_device code includes functions to + * build a struct platform_device using omap_hwmod data, and that is + * currently how hwmod data is communicated to drivers and to the + * Linux driver model. Most drivers will call omap_hwmod functions only + * indirectly, via pm_runtime*() functions. + * + * From a layering perspective, here is where the OMAP hwmod code + * fits into the kernel software stack: + * + * +-------------------------------+ + * | Device driver code | + * | (e.g., drivers/) | + * +-------------------------------+ + * | Linux driver model | + * | (platform_device / | + * | platform_driver data/code) | + * +-------------------------------+ + * | OMAP core-driver integration | + * |(arch/arm/mach-omap2/devices.c)| + * +-------------------------------+ + * | omap_device code | + * | (../plat-omap/omap_device.c) | + * +-------------------------------+ + * ----> | omap_hwmod code/data | <----- + * | (../mach-omap2/omap_hwmod*) | + * +-------------------------------+ + * | OMAP clock/PRCM/register fns | + * | (__raw_{read,write}l, clk*) | + * +-------------------------------+ + * + * Device drivers should not contain any OMAP-specific code or data in + * them. They should only contain code to operate the IP block that + * the driver is responsible for. This is because these IP blocks can + * also appear in other SoCs, either from TI (such as DaVinci) or from + * other manufacturers; and drivers should be reusable across other + * platforms. + * + * The OMAP hwmod code also will attempt to reset and idle all on-chip + * devices upon boot. The goal here is for the kernel to be + * completely self-reliant and independent from bootloaders. This is + * to ensure a repeatable configuration, both to ensure consistent + * runtime behavior, and to make it easier for others to reproduce + * bugs. + * + * OMAP module activity states + * --------------------------- + * The hwmod code considers modules to be in one of several activity + * states. IP blocks start out in an UNKNOWN state, then once they + * are registered via the hwmod code, proceed to the REGISTERED state. + * Once their clock names are resolved to clock pointers, the module + * enters the CLKS_INITED state; and finally, once the module has been + * reset and the integration registers programmed, the INITIALIZED state + * is entered. The hwmod code will then place the module into either + * the IDLE state to save power, or in the case of a critical system + * module, the ENABLED state. + * + * OMAP core integration code can then call omap_hwmod*() functions + * directly to move the module between the IDLE, ENABLED, and DISABLED + * states, as needed. This is done during both the PM idle loop, and + * in the OMAP core integration code's implementation of the PM runtime + * functions. + * + * References + * ---------- + * This is a partial list. * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064) * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090) * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108) @@ -654,7 +746,7 @@ static void __iomem *_find_mpu_rt_base(struct omap_hwmod *oh, u8 index) } /** - * _sysc_enable - try to bring a module out of idle via OCP_SYSCONFIG + * _enable_sysc - try to bring a module out of idle via OCP_SYSCONFIG * @oh: struct omap_hwmod * * * If module is marked as SWSUP_SIDLE, force the module out of slave @@ -662,7 +754,7 @@ static void __iomem *_find_mpu_rt_base(struct omap_hwmod *oh, u8 index) * as SWSUP_MSUSPEND, force the module out of master standby; * otherwise, configure it for smart-standby. No return value. */ -static void _sysc_enable(struct omap_hwmod *oh) +static void _enable_sysc(struct omap_hwmod *oh) { u8 idlemode, sf; u32 v; @@ -708,7 +800,7 @@ static void _sysc_enable(struct omap_hwmod *oh) } /** - * _sysc_idle - try to put a module into idle via OCP_SYSCONFIG + * _idle_sysc - try to put a module into idle via OCP_SYSCONFIG * @oh: struct omap_hwmod * * * If module is marked as SWSUP_SIDLE, force the module into slave @@ -716,7 +808,7 @@ static void _sysc_enable(struct omap_hwmod *oh) * as SWSUP_MSUSPEND, force the module into master standby; otherwise, * configure it for smart-standby. No return value. */ -static void _sysc_idle(struct omap_hwmod *oh) +static void _idle_sysc(struct omap_hwmod *oh) { u8 idlemode, sf; u32 v; @@ -743,13 +835,13 @@ static void _sysc_idle(struct omap_hwmod *oh) } /** - * _sysc_shutdown - force a module into idle via OCP_SYSCONFIG + * _shutdown_sysc - force a module into idle via OCP_SYSCONFIG * @oh: struct omap_hwmod * * * Force the module into slave idle and master suspend. No return * value. */ -static void _sysc_shutdown(struct omap_hwmod *oh) +static void _shutdown_sysc(struct omap_hwmod *oh) { u32 v; u8 sf; @@ -1071,8 +1163,11 @@ dis_opt_clks: * @oh: struct omap_hwmod * * * Enables an omap_hwmod @oh such that the MPU can access the hwmod's - * register target. Returns -EINVAL if the hwmod is in the wrong - * state or passes along the return value of _wait_target_ready(). + * register target. (This function has a full name -- + * _omap_hwmod_enable() rather than simply _enable() -- because it is + * currently required by the pm34xx.c idle loop.) Returns -EINVAL if + * the hwmod is in the wrong state or passes along the return value of + * _wait_target_ready(). */ int _omap_hwmod_enable(struct omap_hwmod *oh) { @@ -1110,7 +1205,7 @@ int _omap_hwmod_enable(struct omap_hwmod *oh) if (oh->class->sysc) { if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED)) _update_sysc_cache(oh); - _sysc_enable(oh); + _enable_sysc(oh); } } else { pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n", @@ -1121,12 +1216,14 @@ int _omap_hwmod_enable(struct omap_hwmod *oh) } /** - * _idle - idle an omap_hwmod + * _omap_hwmod_idle - idle an omap_hwmod * @oh: struct omap_hwmod * * * Idles an omap_hwmod @oh. This should be called once the hwmod has - * no further work. Returns -EINVAL if the hwmod is in the wrong - * state or returns 0. + * no further work. (This function has a full name -- + * _omap_hwmod_idle() rather than simply _idle() -- because it is + * currently required by the pm34xx.c idle loop.) Returns -EINVAL if + * the hwmod is in the wrong state or returns 0. */ int _omap_hwmod_idle(struct omap_hwmod *oh) { @@ -1139,7 +1236,7 @@ int _omap_hwmod_idle(struct omap_hwmod *oh) pr_debug("omap_hwmod: %s: idling\n", oh->name); if (oh->class->sysc) - _sysc_idle(oh); + _idle_sysc(oh); _del_initiator_dep(oh, mpu_oh); _disable_clocks(oh); @@ -1169,7 +1266,7 @@ static int _shutdown(struct omap_hwmod *oh) pr_debug("omap_hwmod: %s: disabling\n", oh->name); if (oh->class->sysc) - _sysc_shutdown(oh); + _shutdown_sysc(oh); /* * If an IP contains only one HW reset line, then assert it @@ -1262,7 +1359,7 @@ static int _setup(struct omap_hwmod *oh, void *data) */ if (oh->class->sysc) { _update_sysc_cache(oh); - _sysc_enable(oh); + _enable_sysc(oh); } } @@ -1518,7 +1615,7 @@ int omap_hwmod_unregister(struct omap_hwmod *oh) * omap_hwmod_enable - enable an omap_hwmod * @oh: struct omap_hwmod * * - * Enable an omap_hwomd @oh. Intended to be called by omap_device_enable(). + * Enable an omap_hwmod @oh. Intended to be called by omap_device_enable(). * Returns -EINVAL on error or passes along the return value from _enable(). */ int omap_hwmod_enable(struct omap_hwmod *oh) @@ -1540,7 +1637,7 @@ int omap_hwmod_enable(struct omap_hwmod *oh) * omap_hwmod_idle - idle an omap_hwmod * @oh: struct omap_hwmod * * - * Idle an omap_hwomd @oh. Intended to be called by omap_device_idle(). + * Idle an omap_hwmod @oh. Intended to be called by omap_device_idle(). * Returns -EINVAL on error or passes along the return value from _idle(). */ int omap_hwmod_idle(struct omap_hwmod *oh) @@ -1559,7 +1656,7 @@ int omap_hwmod_idle(struct omap_hwmod *oh) * omap_hwmod_shutdown - shutdown an omap_hwmod * @oh: struct omap_hwmod * * - * Shutdown an omap_hwomd @oh. Intended to be called by + * Shutdown an omap_hwmod @oh. Intended to be called by * omap_device_shutdown(). Returns -EINVAL on error or passes along * the return value from _shutdown(). */ diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index ee53758..7290281 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -14,19 +14,16 @@ * * These headers and macros are used to define OMAP on-chip module * data and their integration with other OMAP modules and Linux. - * - * References: - * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064) - * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090) - * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108) - * - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140) - * - Open Core Protocol Specification 2.2 + * Copious documentation and references can also be found in the + * omap_hwmod code, in arch/arm/mach-omap2/omap_hwmod.c (as of this + * writing). * * To do: * - add interconnect error log structures * - add pinmuxing * - init_conn_id_bit (CONNID_BIT_VECTOR) * - implement default hwmod SMS/SDRC flags? + * - remove unused fields * */ #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H -- cgit v1.1 From 0747c7bae5c93377f4ea81b55d6851eaddc677fe Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 9 Aug 2010 12:07:36 +0000 Subject: DMAENGINE: ste_dma40: config checks Added various configuration checks. Signed-off-by: Jonas Aaberg Signed-off-by: Linus Walleij Signed-off-by: Dan Williams --- arch/arm/plat-nomadik/include/plat/ste_dma40.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/plat-nomadik/include/plat/ste_dma40.h b/arch/arm/plat-nomadik/include/plat/ste_dma40.h index 5fbde4b..ee5d8b2 100644 --- a/arch/arm/plat-nomadik/include/plat/ste_dma40.h +++ b/arch/arm/plat-nomadik/include/plat/ste_dma40.h @@ -98,7 +98,7 @@ struct stedma40_half_channel_info { }; enum stedma40_xfer_dir { - STEDMA40_MEM_TO_MEM, + STEDMA40_MEM_TO_MEM = 1, STEDMA40_MEM_TO_PERIPH, STEDMA40_PERIPH_TO_MEM, STEDMA40_PERIPH_TO_PERIPH -- cgit v1.1 From 767a9675c4a68ada55f0f30d629db627bd47f012 Mon Sep 17 00:00:00 2001 From: Jonas Aaberg Date: Mon, 9 Aug 2010 12:08:34 +0000 Subject: DMAENGINE: ste_dma40: code clean-up This patch includes non functional code clean up changes, file header updates and a few magic numbers got defined. Signed-off-by: Jonas Aaberg Signed-off-by: Linus Walleij Signed-off-by: Dan Williams --- arch/arm/plat-nomadik/include/plat/ste_dma40.h | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-nomadik/include/plat/ste_dma40.h b/arch/arm/plat-nomadik/include/plat/ste_dma40.h index ee5d8b2..879a6c1 100644 --- a/arch/arm/plat-nomadik/include/plat/ste_dma40.h +++ b/arch/arm/plat-nomadik/include/plat/ste_dma40.h @@ -1,10 +1,8 @@ /* - * arch/arm/plat-nomadik/include/plat/ste_dma40.h - * - * Copyright (C) ST-Ericsson 2007-2010 + * Copyright (C) ST-Ericsson SA 2007-2010 + * Author: Per Friden for ST-Ericsson + * Author: Jonas Aaberg for ST-Ericsson * License terms: GNU General Public License (GPL) version 2 - * Author: Per Friden - * Author: Jonas Aaberg */ @@ -73,6 +71,9 @@ #define STEDMA40_PSIZE_LOG_8 STEDMA40_PSIZE_PHY_8 #define STEDMA40_PSIZE_LOG_16 STEDMA40_PSIZE_PHY_16 +/* Maximum number of possible physical channels */ +#define STEDMA40_MAX_PHYS 32 + enum stedma40_flow_ctrl { STEDMA40_NO_FLOW_CTRL, STEDMA40_FLOW_CTRL, @@ -160,7 +161,7 @@ struct stedma40_platform_data { struct stedma40_chan_cfg *memcpy_conf_phy; struct stedma40_chan_cfg *memcpy_conf_log; unsigned int llis_per_log; - int disabled_channels[8]; + int disabled_channels[STEDMA40_MAX_PHYS]; }; /** -- cgit v1.1 From 8f6fd7f50f7059e5725a36885af52e54b9df96b2 Mon Sep 17 00:00:00 2001 From: Jonas Aaberg Date: Mon, 9 Aug 2010 12:09:04 +0000 Subject: DMAENGINE: ste_dma40: removed non-used variable from struct The reqrite of the LCLA code rendered this variable unused. Signed-off-by: Jonas Aaberg Signed-off-by: Linus Walleij Signed-off-by: Dan Williams --- arch/arm/mach-ux500/devices-db8500.c | 1 - arch/arm/plat-nomadik/include/plat/ste_dma40.h | 2 -- 2 files changed, 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c index 9280d25..58b3e72 100644 --- a/arch/arm/mach-ux500/devices-db8500.c +++ b/arch/arm/mach-ux500/devices-db8500.c @@ -193,7 +193,6 @@ static struct stedma40_platform_data dma40_plat_data = { .memcpy_len = ARRAY_SIZE(dma40_memcpy_event), .memcpy_conf_phy = &dma40_memcpy_conf_phy, .memcpy_conf_log = &dma40_memcpy_conf_log, - .llis_per_log = 8, .disabled_channels = {-1}, }; diff --git a/arch/arm/plat-nomadik/include/plat/ste_dma40.h b/arch/arm/plat-nomadik/include/plat/ste_dma40.h index 879a6c1..1620492 100644 --- a/arch/arm/plat-nomadik/include/plat/ste_dma40.h +++ b/arch/arm/plat-nomadik/include/plat/ste_dma40.h @@ -148,7 +148,6 @@ struct stedma40_chan_cfg { * @memcpy_len: length of memcpy * @memcpy_conf_phy: default configuration of physical channel memcpy * @memcpy_conf_log: default configuration of logical channel memcpy - * @llis_per_log: number of max linked list items per logical channel * @disabled_channels: A vector, ending with -1, that marks physical channels * that are for different reasons not available for the driver. */ @@ -160,7 +159,6 @@ struct stedma40_platform_data { u32 memcpy_len; struct stedma40_chan_cfg *memcpy_conf_phy; struct stedma40_chan_cfg *memcpy_conf_log; - unsigned int llis_per_log; int disabled_channels[STEDMA40_MAX_PHYS]; }; -- cgit v1.1 From 3c0f24019f69c5199996ed9c76d05c92c6186ba8 Mon Sep 17 00:00:00 2001 From: Jonas Aaberg Date: Mon, 9 Aug 2010 12:09:21 +0000 Subject: DMAENGINE: ste_dma40: added kernel doc for struct The half-channel struct was undocumented. Signed-off-by: Jonas Aaberg Signed-off-by: Linus Walleij Signed-off-by: Dan Williams --- arch/arm/plat-nomadik/include/plat/ste_dma40.h | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-nomadik/include/plat/ste_dma40.h b/arch/arm/plat-nomadik/include/plat/ste_dma40.h index 1620492..1127af2 100644 --- a/arch/arm/plat-nomadik/include/plat/ste_dma40.h +++ b/arch/arm/plat-nomadik/include/plat/ste_dma40.h @@ -91,13 +91,6 @@ enum stedma40_periph_data_width { STEDMA40_DOUBLEWORD_WIDTH = STEDMA40_ESIZE_64_BIT }; -struct stedma40_half_channel_info { - enum stedma40_endianess endianess; - enum stedma40_periph_data_width data_width; - int psize; - enum stedma40_flow_ctrl flow_ctrl; -}; - enum stedma40_xfer_dir { STEDMA40_MEM_TO_MEM = 1, STEDMA40_MEM_TO_PERIPH, @@ -107,6 +100,21 @@ enum stedma40_xfer_dir { /** + * struct stedma40_chan_cfg - dst/src channel configuration + * + * @endianess: Endianess of the src/dst hardware + * @data_width: Data width of the src/dst hardware + * @p_size: Burst size + * @flow_ctrl: Flow control on/off. + */ +struct stedma40_half_channel_info { + enum stedma40_endianess endianess; + enum stedma40_periph_data_width data_width; + int psize; + enum stedma40_flow_ctrl flow_ctrl; +}; + +/** * struct stedma40_chan_cfg - Structure to be filled by client drivers. * * @dir: MEM 2 MEM, PERIPH 2 MEM , MEM 2 PERIPH, PERIPH 2 PERIPH -- cgit v1.1 From a234ca0faa65dcd5cc473915bd925130ebb7b74b Mon Sep 17 00:00:00 2001 From: matt mooney Date: Thu, 23 Sep 2010 06:51:21 +0000 Subject: sh: change to new flag variable Replace EXTRA_CFLAGS with ccflags-y. Signed-off-by: matt mooney Signed-off-by: Paul Mundt --- arch/sh/cchips/hd6446x/Makefile | 2 +- arch/sh/kernel/Makefile | 2 +- arch/sh/lib/Makefile | 2 +- arch/sh/mm/Makefile | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/sh/cchips/hd6446x/Makefile b/arch/sh/cchips/hd6446x/Makefile index 9682e3a..59c3483 100644 --- a/arch/sh/cchips/hd6446x/Makefile +++ b/arch/sh/cchips/hd6446x/Makefile @@ -1,3 +1,3 @@ obj-$(CONFIG_HD64461) += hd64461.o -EXTRA_CFLAGS += -Werror +ccflags-y := -Werror diff --git a/arch/sh/kernel/Makefile b/arch/sh/kernel/Makefile index 1086ba1..a1effb6 100644 --- a/arch/sh/kernel/Makefile +++ b/arch/sh/kernel/Makefile @@ -44,4 +44,4 @@ obj-$(CONFIG_HAS_IOPORT) += io_generic.o obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o obj-$(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) += localtimer.o -EXTRA_CFLAGS += -Werror +ccflags-y := -Werror diff --git a/arch/sh/lib/Makefile b/arch/sh/lib/Makefile index dab4d21..7b95f29 100644 --- a/arch/sh/lib/Makefile +++ b/arch/sh/lib/Makefile @@ -30,4 +30,4 @@ lib-$(CONFIG_MMU) += copy_page.o __clear_user.o lib-$(CONFIG_MCOUNT) += mcount.o lib-y += $(memcpy-y) $(memset-y) $(udivsi3-y) -EXTRA_CFLAGS += -Werror +ccflags-y := -Werror diff --git a/arch/sh/mm/Makefile b/arch/sh/mm/Makefile index 53f7c68..939663c 100644 --- a/arch/sh/mm/Makefile +++ b/arch/sh/mm/Makefile @@ -66,4 +66,4 @@ CFLAGS_fault_64.o += -ffixed-r7 \ -ffixed-r60 -ffixed-r61 -ffixed-r62 \ -fomit-frame-pointer -EXTRA_CFLAGS += -Werror +ccflags-y := -Werror -- cgit v1.1 From 0b1974de66f9ed44f1423449628f4926bf95b854 Mon Sep 17 00:00:00 2001 From: Thomas Weber Date: Thu, 23 Sep 2010 11:46:48 +0200 Subject: Fix typo: configuation => configuration Signed-off-by: Thomas Weber Acked-by: David S. Miller Signed-off-by: Jiri Kosina --- arch/arm/mach-omap2/hsmmc.h | 2 +- arch/mips/sibyte/common/sb_tbprof.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/hsmmc.h b/arch/arm/mach-omap2/hsmmc.h index 36f0ba8..6536c31 100644 --- a/arch/arm/mach-omap2/hsmmc.h +++ b/arch/arm/mach-omap2/hsmmc.h @@ -21,7 +21,7 @@ struct omap2_hsmmc_info { char *name; /* or NULL for default */ struct device *dev; /* returned: pointer to mmc adapter */ int ocr_mask; /* temporary HACK */ - /* Remux (pad configuation) when powering on/off */ + /* Remux (pad configuration) when powering on/off */ void (*remux)(struct device *dev, int slot, int power_on); }; diff --git a/arch/mips/sibyte/common/sb_tbprof.c b/arch/mips/sibyte/common/sb_tbprof.c index d4ed7a9..a2bdb2e 100644 --- a/arch/mips/sibyte/common/sb_tbprof.c +++ b/arch/mips/sibyte/common/sb_tbprof.c @@ -43,7 +43,7 @@ #include #include #else -#error invalid SiByte UART configuation +#error invalid SiByte UART configuration #endif #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) -- cgit v1.1 From b42e17963c20ecb80905083ceaecc79fd9bd30f1 Mon Sep 17 00:00:00 2001 From: Thomas Weber Date: Thu, 23 Sep 2010 11:46:50 +0200 Subject: Fix typo configue => configure in comments Signed-off-by: Thomas Weber Acked-by: David S. Miller Signed-off-by: Jiri Kosina --- arch/mips/pci/fixup-fuloong2e.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/mips/pci/fixup-fuloong2e.c b/arch/mips/pci/fixup-fuloong2e.c index 4f6d8da..d5d4c01 100644 --- a/arch/mips/pci/fixup-fuloong2e.c +++ b/arch/mips/pci/fixup-fuloong2e.c @@ -52,7 +52,7 @@ static void __init loongson2e_nec_fixup(struct pci_dev *pdev) { unsigned int val; - /* Configues port 1, 2, 3, 4 to be validate*/ + /* Configures port 1, 2, 3, 4 to be validate*/ pci_read_config_dword(pdev, 0xe0, &val); pci_write_config_dword(pdev, 0xe0, (val & ~7) | 0x4); -- cgit v1.1 From aa88bc0a072b9f02891592d0aa6d0e8d138abf8f Mon Sep 17 00:00:00 2001 From: H Hartley Sweeten Date: Fri, 6 Aug 2010 09:36:42 -0700 Subject: arm: scoop.c: remove C99 comments Comments should be /* */ not //. Signed-off-by: H Hartley Sweeten Cc: Jiri Kosina Signed-off-by: Jiri Kosina --- arch/arm/common/scoop.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/common/scoop.c b/arch/arm/common/scoop.c index 9012004..c11af1e 100644 --- a/arch/arm/common/scoop.c +++ b/arch/arm/common/scoop.c @@ -44,12 +44,12 @@ void reset_scoop(struct device *dev) { struct scoop_dev *sdev = dev_get_drvdata(dev); - iowrite16(0x0100, sdev->base + SCOOP_MCR); // 00 - iowrite16(0x0000, sdev->base + SCOOP_CDR); // 04 - iowrite16(0x0000, sdev->base + SCOOP_CCR); // 10 - iowrite16(0x0000, sdev->base + SCOOP_IMR); // 18 - iowrite16(0x00FF, sdev->base + SCOOP_IRM); // 14 - iowrite16(0x0000, sdev->base + SCOOP_ISR); // 1C + iowrite16(0x0100, sdev->base + SCOOP_MCR); /* 00 */ + iowrite16(0x0000, sdev->base + SCOOP_CDR); /* 04 */ + iowrite16(0x0000, sdev->base + SCOOP_CCR); /* 10 */ + iowrite16(0x0000, sdev->base + SCOOP_IMR); /* 18 */ + iowrite16(0x00FF, sdev->base + SCOOP_IRM); /* 14 */ + iowrite16(0x0000, sdev->base + SCOOP_ISR); /* 1C */ iowrite16(0x0000, sdev->base + SCOOP_IRM); } -- cgit v1.1 From 909ea93b12541a0bac27c495c810ac6d79343986 Mon Sep 17 00:00:00 2001 From: H Hartley Sweeten Date: Fri, 6 Aug 2010 09:40:42 -0700 Subject: arm: uengine.c: remove C99 comments Comments should be /* */ not //. Signed-off-by: H Hartley Sweeten Cc: Jiri Kosina Signed-off-by: Jiri Kosina --- arch/arm/common/uengine.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'arch') diff --git a/arch/arm/common/uengine.c b/arch/arm/common/uengine.c index b520e56..bef408f 100644 --- a/arch/arm/common/uengine.c +++ b/arch/arm/common/uengine.c @@ -312,16 +312,16 @@ static void generate_ucode(u8 *ucode, u32 *gpr_a, u32 *gpr_b) b1 = (gpr_a[i] >> 8) & 0xff; b0 = gpr_a[i] & 0xff; - // immed[@ai, (b1 << 8) | b0] - // 11110000 0000VVVV VVVV11VV VVVVVV00 1IIIIIII + /* immed[@ai, (b1 << 8) | b0] */ + /* 11110000 0000VVVV VVVV11VV VVVVVV00 1IIIIIII */ ucode[offset++] = 0xf0; ucode[offset++] = (b1 >> 4); ucode[offset++] = (b1 << 4) | 0x0c | (b0 >> 6); ucode[offset++] = (b0 << 2); ucode[offset++] = 0x80 | i; - // immed_w1[@ai, (b3 << 8) | b2] - // 11110100 0100VVVV VVVV11VV VVVVVV00 1IIIIIII + /* immed_w1[@ai, (b3 << 8) | b2] */ + /* 11110100 0100VVVV VVVV11VV VVVVVV00 1IIIIIII */ ucode[offset++] = 0xf4; ucode[offset++] = 0x40 | (b3 >> 4); ucode[offset++] = (b3 << 4) | 0x0c | (b2 >> 6); @@ -340,16 +340,16 @@ static void generate_ucode(u8 *ucode, u32 *gpr_a, u32 *gpr_b) b1 = (gpr_b[i] >> 8) & 0xff; b0 = gpr_b[i] & 0xff; - // immed[@bi, (b1 << 8) | b0] - // 11110000 0000VVVV VVVV001I IIIIII11 VVVVVVVV + /* immed[@bi, (b1 << 8) | b0] */ + /* 11110000 0000VVVV VVVV001I IIIIII11 VVVVVVVV */ ucode[offset++] = 0xf0; ucode[offset++] = (b1 >> 4); ucode[offset++] = (b1 << 4) | 0x02 | (i >> 6); ucode[offset++] = (i << 2) | 0x03; ucode[offset++] = b0; - // immed_w1[@bi, (b3 << 8) | b2] - // 11110100 0100VVVV VVVV001I IIIIII11 VVVVVVVV + /* immed_w1[@bi, (b3 << 8) | b2] */ + /* 11110100 0100VVVV VVVV001I IIIIII11 VVVVVVVV */ ucode[offset++] = 0xf4; ucode[offset++] = 0x40 | (b3 >> 4); ucode[offset++] = (b3 << 4) | 0x02 | (i >> 6); @@ -357,7 +357,7 @@ static void generate_ucode(u8 *ucode, u32 *gpr_a, u32 *gpr_b) ucode[offset++] = b2; } - // ctx_arb[kill] + /* ctx_arb[kill] */ ucode[offset++] = 0xe0; ucode[offset++] = 0x00; ucode[offset++] = 0x01; -- cgit v1.1 From 493c32a0de2bfbcc33d52f32a39f3c301c6ffd62 Mon Sep 17 00:00:00 2001 From: Cory Maccarrone Date: Wed, 18 Aug 2010 04:35:46 +0000 Subject: HTCHERALD: MMC, I2C, HTCPLD, SPI, TSC2046 This change adds in MMC and I2C support to the HTC Herald board, as well as adding the HTCPLD driver for the PLD used on this phone. It also adds in the gpio-keys entries for the front directional keys and selector and the cursor keys on the slide-out keyboard, and gpio-leds support for the LEDs attached to the htcpld. Additionally, SPI bus support (using the spi100k driver) and touchscreen support (using the ads7846 driver) were added. Signed-off-by: Cory Maccarrone Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/board-htcherald.c | 322 +++++++++++++++++++++++++++++++++- 1 file changed, 316 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c index 311899f..7ea75c1 100644 --- a/arch/arm/mach-omap1/board-htcherald.c +++ b/arch/arm/mach-omap1/board-htcherald.c @@ -30,6 +30,13 @@ #include #include #include +#include +#include +#include +#include +#include +#include +#include #include #include @@ -39,6 +46,7 @@ #include #include #include +#include #include @@ -52,13 +60,123 @@ #define OMAP_LCDC_CTRL_LCD_EN (1 << 0) #define OMAP_LCDC_STAT_DONE (1 << 0) -static struct omap_lcd_config htcherald_lcd_config __initdata = { - .ctrl_name = "internal", -}; +/* GPIO definitions for the power button and keyboard slide switch */ +#define HTCHERALD_GPIO_POWER 139 +#define HTCHERALD_GPIO_SLIDE 174 +#define HTCHERALD_GIRQ_BTNS 141 -static struct omap_board_config_kernel htcherald_config[] __initdata = { - { OMAP_TAG_LCD, &htcherald_lcd_config }, -}; +/* GPIO definitions for the touchscreen */ +#define HTCHERALD_GPIO_TS 76 + +/* HTCPLD definitions */ + +/* + * CPLD Logic + * + * Chip 3 - 0x03 + * + * Function 7 6 5 4 3 2 1 0 + * ------------------------------------ + * DPAD light x x x x x x x 1 + * SoundDev x x x x 1 x x x + * Screen white 1 x x x x x x x + * MMC power on x x x x x 1 x x + * Happy times (n) 0 x x x x 1 x x + * + * Chip 4 - 0x04 + * + * Function 7 6 5 4 3 2 1 0 + * ------------------------------------ + * Keyboard light x x x x x x x 1 + * LCD Bright (4) x x x x x 1 1 x + * LCD Bright (3) x x x x x 0 1 x + * LCD Bright (2) x x x x x 1 0 x + * LCD Bright (1) x x x x x 0 0 x + * LCD Off x x x x 0 x x x + * LCD image (fb) 1 x x x x x x x + * LCD image (white) 0 x x x x x x x + * Caps lock LED x x 1 x x x x x + * + * Chip 5 - 0x05 + * + * Function 7 6 5 4 3 2 1 0 + * ------------------------------------ + * Red (solid) x x x x x 1 x x + * Red (flash) x x x x x x 1 x + * Green (GSM flash) x x x x 1 x x x + * Green (GSM solid) x x x 1 x x x x + * Green (wifi flash) x x 1 x x x x x + * Blue (bt flash) x 1 x x x x x x + * DPAD Int Enable 1 x x x x x x 0 + * + * (Combinations of the above can be made for different colors.) + * The direction pad interrupt enable must be set each time the + * interrupt is handled. + * + * Chip 6 - 0x06 + * + * Function 7 6 5 4 3 2 1 0 + * ------------------------------------ + * Vibrator x x x x 1 x x x + * Alt LED x x x 1 x x x x + * Screen white 1 x x x x x x x + * Screen white x x 1 x x x x x + * Screen white x 0 x x x x x x + * Enable kbd dpad x x x x x x 0 x + * Happy Times 0 1 0 x x x 0 x + */ + +/* + * HTCPLD GPIO lines start 16 after OMAP_MAX_GPIO_LINES to account + * for the 16 MPUIO lines. + */ +#define HTCPLD_GPIO_START_OFFSET (OMAP_MAX_GPIO_LINES + 16) +#define HTCPLD_IRQ(chip, offset) (OMAP_IRQ_END + 8 * (chip) + (offset)) +#define HTCPLD_BASE(chip, offset) \ + (HTCPLD_GPIO_START_OFFSET + 8 * (chip) + (offset)) + +#define HTCPLD_GPIO_LED_DPAD HTCPLD_BASE(0, 0) +#define HTCPLD_GPIO_LED_KBD HTCPLD_BASE(1, 0) +#define HTCPLD_GPIO_LED_CAPS HTCPLD_BASE(1, 5) +#define HTCPLD_GPIO_LED_RED_FLASH HTCPLD_BASE(2, 1) +#define HTCPLD_GPIO_LED_RED_SOLID HTCPLD_BASE(2, 2) +#define HTCPLD_GPIO_LED_GREEN_FLASH HTCPLD_BASE(2, 3) +#define HTCPLD_GPIO_LED_GREEN_SOLID HTCPLD_BASE(2, 4) +#define HTCPLD_GPIO_LED_WIFI HTCPLD_BASE(2, 5) +#define HTCPLD_GPIO_LED_BT HTCPLD_BASE(2, 6) +#define HTCPLD_GPIO_LED_VIBRATE HTCPLD_BASE(3, 3) +#define HTCPLD_GPIO_LED_ALT HTCPLD_BASE(3, 4) + +#define HTCPLD_GPIO_RIGHT_KBD HTCPLD_BASE(6, 7) +#define HTCPLD_GPIO_UP_KBD HTCPLD_BASE(6, 6) +#define HTCPLD_GPIO_LEFT_KBD HTCPLD_BASE(6, 5) +#define HTCPLD_GPIO_DOWN_KBD HTCPLD_BASE(6, 4) + +#define HTCPLD_GPIO_RIGHT_DPAD HTCPLD_BASE(7, 7) +#define HTCPLD_GPIO_UP_DPAD HTCPLD_BASE(7, 6) +#define HTCPLD_GPIO_LEFT_DPAD HTCPLD_BASE(7, 5) +#define HTCPLD_GPIO_DOWN_DPAD HTCPLD_BASE(7, 4) +#define HTCPLD_GPIO_ENTER_DPAD HTCPLD_BASE(7, 3) + +/* + * The htcpld chip requires a gpio write to a specific line + * to re-enable interrupts after one has occurred. + */ +#define HTCPLD_GPIO_INT_RESET_HI HTCPLD_BASE(2, 7) +#define HTCPLD_GPIO_INT_RESET_LO HTCPLD_BASE(2, 0) + +/* Chip 5 */ +#define HTCPLD_IRQ_RIGHT_KBD HTCPLD_IRQ(0, 7) +#define HTCPLD_IRQ_UP_KBD HTCPLD_IRQ(0, 6) +#define HTCPLD_IRQ_LEFT_KBD HTCPLD_IRQ(0, 5) +#define HTCPLD_IRQ_DOWN_KBD HTCPLD_IRQ(0, 4) + +/* Chip 6 */ +#define HTCPLD_IRQ_RIGHT_DPAD HTCPLD_IRQ(1, 7) +#define HTCPLD_IRQ_UP_DPAD HTCPLD_IRQ(1, 6) +#define HTCPLD_IRQ_LEFT_DPAD HTCPLD_IRQ(1, 5) +#define HTCPLD_IRQ_DOWN_DPAD HTCPLD_IRQ(1, 4) +#define HTCPLD_IRQ_ENTER_DPAD HTCPLD_IRQ(1, 3) /* Keyboard definition */ @@ -140,6 +258,129 @@ static struct platform_device kp_device = { .resource = kp_resources, }; +/* GPIO buttons for keyboard slide and power button */ +static struct gpio_keys_button herald_gpio_keys_table[] = { + {BTN_0, HTCHERALD_GPIO_POWER, 1, "POWER", EV_KEY, 1, 20}, + {SW_LID, HTCHERALD_GPIO_SLIDE, 0, "SLIDE", EV_SW, 1, 20}, + + {KEY_LEFT, HTCPLD_GPIO_LEFT_KBD, 1, "LEFT", EV_KEY, 1, 20}, + {KEY_RIGHT, HTCPLD_GPIO_RIGHT_KBD, 1, "RIGHT", EV_KEY, 1, 20}, + {KEY_UP, HTCPLD_GPIO_UP_KBD, 1, "UP", EV_KEY, 1, 20}, + {KEY_DOWN, HTCPLD_GPIO_DOWN_KBD, 1, "DOWN", EV_KEY, 1, 20}, + + {KEY_LEFT, HTCPLD_GPIO_LEFT_DPAD, 1, "DLEFT", EV_KEY, 1, 20}, + {KEY_RIGHT, HTCPLD_GPIO_RIGHT_DPAD, 1, "DRIGHT", EV_KEY, 1, 20}, + {KEY_UP, HTCPLD_GPIO_UP_DPAD, 1, "DUP", EV_KEY, 1, 20}, + {KEY_DOWN, HTCPLD_GPIO_DOWN_DPAD, 1, "DDOWN", EV_KEY, 1, 20}, + {KEY_ENTER, HTCPLD_GPIO_ENTER_DPAD, 1, "DENTER", EV_KEY, 1, 20}, +}; + +static struct gpio_keys_platform_data herald_gpio_keys_data = { + .buttons = herald_gpio_keys_table, + .nbuttons = ARRAY_SIZE(herald_gpio_keys_table), + .rep = 1, +}; + +static struct platform_device herald_gpiokeys_device = { + .name = "gpio-keys", + .id = -1, + .dev = { + .platform_data = &herald_gpio_keys_data, + }, +}; + +/* LEDs for the Herald. These connect to the HTCPLD GPIO device. */ +static struct gpio_led gpio_leds[] = { + {"dpad", NULL, HTCPLD_GPIO_LED_DPAD, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, + {"kbd", NULL, HTCPLD_GPIO_LED_KBD, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, + {"vibrate", NULL, HTCPLD_GPIO_LED_VIBRATE, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, + {"green_solid", NULL, HTCPLD_GPIO_LED_GREEN_SOLID, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, + {"green_flash", NULL, HTCPLD_GPIO_LED_GREEN_FLASH, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, + {"red_solid", "mmc0", HTCPLD_GPIO_LED_RED_SOLID, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, + {"red_flash", NULL, HTCPLD_GPIO_LED_RED_FLASH, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, + {"wifi", NULL, HTCPLD_GPIO_LED_WIFI, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, + {"bt", NULL, HTCPLD_GPIO_LED_BT, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, + {"caps", NULL, HTCPLD_GPIO_LED_CAPS, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, + {"alt", NULL, HTCPLD_GPIO_LED_ALT, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, +}; + +static struct gpio_led_platform_data gpio_leds_data = { + .leds = gpio_leds, + .num_leds = ARRAY_SIZE(gpio_leds), +}; + +static struct platform_device gpio_leds_device = { + .name = "leds-gpio", + .id = 0, + .dev = { + .platform_data = &gpio_leds_data, + }, +}; + +/* HTC PLD chips */ + +static struct resource htcpld_resources[] = { + [0] = { + .start = OMAP_GPIO_IRQ(HTCHERALD_GIRQ_BTNS), + .end = OMAP_GPIO_IRQ(HTCHERALD_GIRQ_BTNS), + .flags = IORESOURCE_IRQ, + }, +}; + +struct htcpld_chip_platform_data htcpld_chips[] = { + [0] = { + .addr = 0x03, + .reset = 0x04, + .num_gpios = 8, + .gpio_out_base = HTCPLD_BASE(0, 0), + .gpio_in_base = HTCPLD_BASE(4, 0), + }, + [1] = { + .addr = 0x04, + .reset = 0x8e, + .num_gpios = 8, + .gpio_out_base = HTCPLD_BASE(1, 0), + .gpio_in_base = HTCPLD_BASE(5, 0), + }, + [2] = { + .addr = 0x05, + .reset = 0x80, + .num_gpios = 8, + .gpio_out_base = HTCPLD_BASE(2, 0), + .gpio_in_base = HTCPLD_BASE(6, 0), + .irq_base = HTCPLD_IRQ(0, 0), + .num_irqs = 8, + }, + [3] = { + .addr = 0x06, + .reset = 0x40, + .num_gpios = 8, + .gpio_out_base = HTCPLD_BASE(3, 0), + .gpio_in_base = HTCPLD_BASE(7, 0), + .irq_base = HTCPLD_IRQ(1, 0), + .num_irqs = 8, + }, +}; + +struct htcpld_core_platform_data htcpld_pfdata = { + .int_reset_gpio_hi = HTCPLD_GPIO_INT_RESET_HI, + .int_reset_gpio_lo = HTCPLD_GPIO_INT_RESET_LO, + .i2c_adapter_id = 1, + + .chip = htcpld_chips, + .num_chip = ARRAY_SIZE(htcpld_chips), +}; + +static struct platform_device htcpld_device = { + .name = "i2c-htcpld", + .id = -1, + .resource = htcpld_resources, + .num_resources = ARRAY_SIZE(htcpld_resources), + .dev = { + .platform_data = &htcpld_pfdata, + }, +}; + /* USB Device */ static struct omap_usb_config htcherald_usb_config __initdata = { .otg = 0, @@ -150,14 +391,72 @@ static struct omap_usb_config htcherald_usb_config __initdata = { }; /* LCD Device resources */ +static struct omap_lcd_config htcherald_lcd_config __initdata = { + .ctrl_name = "internal", +}; + +static struct omap_board_config_kernel htcherald_config[] __initdata = { + { OMAP_TAG_LCD, &htcherald_lcd_config }, +}; + static struct platform_device lcd_device = { .name = "lcd_htcherald", .id = -1, }; +/* MMC Card */ +#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) +static struct omap_mmc_platform_data htc_mmc1_data = { + .nr_slots = 1, + .switch_slot = NULL, + .slots[0] = { + .ocr_mask = MMC_VDD_28_29 | MMC_VDD_30_31 | + MMC_VDD_32_33 | MMC_VDD_33_34, + .name = "mmcblk", + .nomux = 1, + .wires = 4, + .switch_pin = -1, + }, +}; + +static struct omap_mmc_platform_data *htc_mmc_data[1]; +#endif + + +/* Platform devices for the Herald */ static struct platform_device *devices[] __initdata = { &kp_device, &lcd_device, + &htcpld_device, + &gpio_leds_device, + &herald_gpiokeys_device, +}; + +/* + * Touchscreen + */ +static const struct ads7846_platform_data htcherald_ts_platform_data = { + .model = 7846, + .keep_vref_on = 1, + .x_plate_ohms = 496, + .gpio_pendown = HTCHERALD_GPIO_TS, + .pressure_max = 100000, + .pressure_min = 5000, + .x_min = 528, + .x_max = 3760, + .y_min = 624, + .y_max = 3760, +}; + +static struct spi_board_info __initdata htcherald_spi_board_info[] = { + { + .modalias = "ads7846", + .platform_data = &htcherald_ts_platform_data, + .irq = OMAP_GPIO_IRQ(HTCHERALD_GPIO_TS), + .max_speed_hz = 2500000, + .bus_num = 2, + .chip_select = 1, + } }; /* @@ -278,6 +577,7 @@ static void __init htcherald_init(void) { printk(KERN_INFO "HTC Herald init.\n"); + /* Do board initialization before we register all the devices */ omap_gpio_init(); omap_board_config = htcherald_config; @@ -288,6 +588,16 @@ static void __init htcherald_init(void) htcherald_usb_enable(); omap1_usb_init(&htcherald_usb_config); + + spi_register_board_info(htcherald_spi_board_info, + ARRAY_SIZE(htcherald_spi_board_info)); + + omap_register_i2c_bus(1, 100, NULL, 0); + +#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) + htc_mmc_data[0] = &htc_mmc1_data; + omap1_init_mmc(htc_mmc_data, 1); +#endif } static void __init htcherald_init_irq(void) -- cgit v1.1 From 6554287b1de0448f1e02e200d02b43914e997d15 Mon Sep 17 00:00:00 2001 From: Bart Oldeman Date: Thu, 23 Sep 2010 13:16:58 -0400 Subject: x86, vm86: Fix preemption bug for int1 debug and int3 breakpoint handlers. Impact: fix kernel bug such as: BUG: scheduling while atomic: dosemu.bin/19680/0x00000004 See also Ubuntu bug 455067 at https://bugs.launchpad.net/ubuntu/+source/linux/+bug/455067 Commits 4915a35e35a037254550a2ba9f367a812bc37d40 ("Use preempt_conditional_sti/cli in do_int3, like on x86_64.") and 3d2a71a596bd9c761c8487a2178e95f8a61da083 ("x86, traps: converge do_debug handlers") started disabling preemption in int1 and int3 handlers on i386. The problem with vm86 is that the call to handle_vm86_trap() may jump straight to entry_32.S and never returns so preempt is never enabled again, and there is an imbalance in the preempt count. Commit be716615fe596ee117292dc615e95f707fb67fd1 ("x86, vm86: fix preemption bug"), which was later (accidentally?) reverted by commit 08d68323d1f0c34452e614263b212ca556dae47f ("hw-breakpoints: modifying generic debug exception to use thread-specific debug registers") fixed the problem for debug exceptions but not for breakpoints. There are three solutions to this problem. 1. Reenable preemption before calling handle_vm86_trap(). This was the approach that was later reverted. 2. Do not disable preemption for i386 in breakpoint and debug handlers. This was the situation before October 2008. As far as I understand preemption only needs to be disabled on x86_64 because a seperate stack is used, but it's nice to have things work the same way on i386 and x86_64. 3. Let handle_vm86_trap() return instead of jumping to assembly code. By setting a flag in _TIF_WORK_MASK, either TIF_IRET or TIF_NOTIFY_RESUME, the code in entry_32.S is instructed to return to 32 bit mode from V86 mode. The logic in entry_32.S was already present to handle signals. (I chose TIF_IRET because it's slightly more efficient in do_notify_resume() in signal.c, but in fact TIF_IRET can probably be replaced by TIF_NOTIFY_RESUME everywhere.) I'm submitting approach 3, because I believe it is the most elegant and prevents future confusion. Still, an obvious preempt_conditional_cli(regs); is necessary in traps.c to correct the bug. [ hpa: This is technically a regression, but because: 1. the regression is so old, 2. the patch seems relatively high risk, justifying more testing, and 3. we're late in the 2.6.36-rc cycle, I'm queuing it up for the 2.6.37 merge window. It might, however, justify as a -stable backport at a latter time, hence Cc: stable. ] Signed-off-by: Bart Oldeman LKML-Reference: Cc: Frederic Weisbecker Cc: K.Prasad Cc: Alan Stern Cc: Alexander van Heukelum Cc: Signed-off-by: H. Peter Anvin --- arch/x86/kernel/traps.c | 1 + arch/x86/kernel/vm86_32.c | 10 ++++++++-- 2 files changed, 9 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index 60788de..9f4edeb 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -575,6 +575,7 @@ dotraplinkage void __kprobes do_debug(struct pt_regs *regs, long error_code) if (regs->flags & X86_VM_MASK) { handle_vm86_trap((struct kernel_vm86_regs *) regs, error_code, 1); + preempt_conditional_cli(regs); return; } diff --git a/arch/x86/kernel/vm86_32.c b/arch/x86/kernel/vm86_32.c index 5ffb5622..61fb985 100644 --- a/arch/x86/kernel/vm86_32.c +++ b/arch/x86/kernel/vm86_32.c @@ -551,8 +551,14 @@ cannot_handle: int handle_vm86_trap(struct kernel_vm86_regs *regs, long error_code, int trapno) { if (VMPI.is_vm86pus) { - if ((trapno == 3) || (trapno == 1)) - return_to_32bit(regs, VM86_TRAP + (trapno << 8)); + if ((trapno == 3) || (trapno == 1)) { + KVM86->regs32->ax = VM86_TRAP + (trapno << 8); + /* setting this flag forces the code in entry_32.S to + call save_v86_state() and change the stack pointer + to KVM86->regs32 */ + set_thread_flag(TIF_IRET); + return 0; + } do_int(regs, trapno, (unsigned char __user *) (regs->pt.ss << 4), SP(regs)); return 0; } -- cgit v1.1 From 3f224f4e057ce67713f3e7a8890f2fbe12d047a5 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 24 Sep 2010 04:04:26 +0900 Subject: sh: provide generic arch_debugfs_dir. While sh previously had its own debugfs root, there now exists a common arch_debugfs_dir prototype, so we switch everything over to that. Presumably once more architectures start making use of this we'll be able to just kill off the stub kdebugfs wrapper. Signed-off-by: Paul Mundt --- arch/sh/include/asm/system.h | 2 -- arch/sh/kernel/Makefile | 4 ++-- arch/sh/kernel/kdebugfs.c | 16 ++++++++++++++++ arch/sh/kernel/setup.c | 15 --------------- arch/sh/mm/asids-debugfs.c | 2 +- arch/sh/mm/cache-debugfs.c | 10 ++-------- arch/sh/mm/pmb.c | 4 +--- arch/sh/mm/tlb-debugfs.c | 11 ++--------- 8 files changed, 24 insertions(+), 40 deletions(-) create mode 100644 arch/sh/kernel/kdebugfs.c (limited to 'arch') diff --git a/arch/sh/include/asm/system.h b/arch/sh/include/asm/system.h index 0bd7a17..1f1af5a 100644 --- a/arch/sh/include/asm/system.h +++ b/arch/sh/include/asm/system.h @@ -140,8 +140,6 @@ extern unsigned int instruction_size(unsigned int insn); extern unsigned long cached_to_uncached; extern unsigned long uncached_size; -extern struct dentry *sh_debugfs_root; - void per_cpu_trap_init(void); void default_idle(void); void cpu_idle_wait(void); diff --git a/arch/sh/kernel/Makefile b/arch/sh/kernel/Makefile index a1effb6..8eed6a4 100644 --- a/arch/sh/kernel/Makefile +++ b/arch/sh/kernel/Makefile @@ -12,8 +12,8 @@ endif CFLAGS_REMOVE_return_address.o = -pg obj-y := clkdev.o debugtraps.o dma-nommu.o dumpstack.o \ - idle.o io.o irq.o \ - irq_$(BITS).o machvec.o nmi_debug.o process.o \ + idle.o io.o irq.o irq_$(BITS).o kdebugfs.o \ + machvec.o nmi_debug.o process.o \ process_$(BITS).o ptrace.o ptrace_$(BITS).o \ reboot.o return_address.o \ setup.o signal_$(BITS).o sys_sh.o sys_sh$(BITS).o \ diff --git a/arch/sh/kernel/kdebugfs.c b/arch/sh/kernel/kdebugfs.c new file mode 100644 index 0000000..e11c30b --- /dev/null +++ b/arch/sh/kernel/kdebugfs.c @@ -0,0 +1,16 @@ +#include +#include +#include + +struct dentry *arch_debugfs_dir; +EXPORT_SYMBOL(arch_debugfs_dir); + +static int __init arch_kdebugfs_init(void) +{ + arch_debugfs_dir = debugfs_create_dir("sh", NULL); + if (!arch_debugfs_dir) + return -ENOMEM; + + return 0; +} +arch_initcall(arch_kdebugfs_init); diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c index e769401..f24d0ea 100644 --- a/arch/sh/kernel/setup.c +++ b/arch/sh/kernel/setup.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include #include @@ -458,17 +457,3 @@ const struct seq_operations cpuinfo_op = { .show = show_cpuinfo, }; #endif /* CONFIG_PROC_FS */ - -struct dentry *sh_debugfs_root; - -static int __init sh_debugfs_init(void) -{ - sh_debugfs_root = debugfs_create_dir("sh", NULL); - if (!sh_debugfs_root) - return -ENOMEM; - if (IS_ERR(sh_debugfs_root)) - return PTR_ERR(sh_debugfs_root); - - return 0; -} -arch_initcall(sh_debugfs_init); diff --git a/arch/sh/mm/asids-debugfs.c b/arch/sh/mm/asids-debugfs.c index cd8c3bf3..74c03ec 100644 --- a/arch/sh/mm/asids-debugfs.c +++ b/arch/sh/mm/asids-debugfs.c @@ -63,7 +63,7 @@ static int __init asids_debugfs_init(void) { struct dentry *asids_dentry; - asids_dentry = debugfs_create_file("asids", S_IRUSR, sh_debugfs_root, + asids_dentry = debugfs_create_file("asids", S_IRUSR, arch_debugfs_dir, NULL, &asids_debugfs_fops); if (!asids_dentry) return -ENOMEM; diff --git a/arch/sh/mm/cache-debugfs.c b/arch/sh/mm/cache-debugfs.c index 690ed01..5241146 100644 --- a/arch/sh/mm/cache-debugfs.c +++ b/arch/sh/mm/cache-debugfs.c @@ -126,25 +126,19 @@ static int __init cache_debugfs_init(void) { struct dentry *dcache_dentry, *icache_dentry; - dcache_dentry = debugfs_create_file("dcache", S_IRUSR, sh_debugfs_root, + dcache_dentry = debugfs_create_file("dcache", S_IRUSR, arch_debugfs_dir, (unsigned int *)CACHE_TYPE_DCACHE, &cache_debugfs_fops); if (!dcache_dentry) return -ENOMEM; - if (IS_ERR(dcache_dentry)) - return PTR_ERR(dcache_dentry); - icache_dentry = debugfs_create_file("icache", S_IRUSR, sh_debugfs_root, + icache_dentry = debugfs_create_file("icache", S_IRUSR, arch_debugfs_dir, (unsigned int *)CACHE_TYPE_ICACHE, &cache_debugfs_fops); if (!icache_dentry) { debugfs_remove(dcache_dentry); return -ENOMEM; } - if (IS_ERR(icache_dentry)) { - debugfs_remove(dcache_dentry); - return PTR_ERR(icache_dentry); - } return 0; } diff --git a/arch/sh/mm/pmb.c b/arch/sh/mm/pmb.c index 6379091..233c011 100644 --- a/arch/sh/mm/pmb.c +++ b/arch/sh/mm/pmb.c @@ -866,11 +866,9 @@ static int __init pmb_debugfs_init(void) struct dentry *dentry; dentry = debugfs_create_file("pmb", S_IFREG | S_IRUGO, - sh_debugfs_root, NULL, &pmb_debugfs_fops); + arch_debugfs_dir, NULL, &pmb_debugfs_fops); if (!dentry) return -ENOMEM; - if (IS_ERR(dentry)) - return PTR_ERR(dentry); return 0; } diff --git a/arch/sh/mm/tlb-debugfs.c b/arch/sh/mm/tlb-debugfs.c index 229bf75..dea637a 100644 --- a/arch/sh/mm/tlb-debugfs.c +++ b/arch/sh/mm/tlb-debugfs.c @@ -151,15 +151,13 @@ static int __init tlb_debugfs_init(void) { struct dentry *itlb, *utlb; - itlb = debugfs_create_file("itlb", S_IRUSR, sh_debugfs_root, + itlb = debugfs_create_file("itlb", S_IRUSR, arch_debugfs_dir, (unsigned int *)TLB_TYPE_ITLB, &tlb_debugfs_fops); if (unlikely(!itlb)) return -ENOMEM; - if (IS_ERR(itlb)) - return PTR_ERR(itlb); - utlb = debugfs_create_file("utlb", S_IRUSR, sh_debugfs_root, + utlb = debugfs_create_file("utlb", S_IRUSR, arch_debugfs_dir, (unsigned int *)TLB_TYPE_UTLB, &tlb_debugfs_fops); if (unlikely(!utlb)) { @@ -167,11 +165,6 @@ static int __init tlb_debugfs_init(void) return -ENOMEM; } - if (IS_ERR(utlb)) { - debugfs_remove(itlb); - return PTR_ERR(utlb); - } - return 0; } module_init(tlb_debugfs_init); -- cgit v1.1 From e7410cf7831c2e5106a90dac6179df5d2c9bd60e Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Wed, 8 Sep 2010 16:37:42 -0700 Subject: OMAP3: PM: move device-specific special cases from PM core into CPUidle In an effort to simplify the core idle path, move any device-specific special case handling from the core PM idle path into the CPUidle pre-idle checking path. This keeps the core, interrupts-disabled idle path streamlined and independent of any device-specific handling, and also allows CPUidle to do the checking only for certain C-states as needed. This patch has the device checks in place for all states with the CHECK_BM flag, namely all states >= C2. This patch was inspired by a similar patch written by Tero Kristo as part of a larger series to add INACTIVE state support. NOTE: This is a baby-step towards decoupling device idle (or system idle) from CPU idle. Eventually, CPUidle should only manage the CPU, and device/system idle should be managed elsewhere. Cc: Tero Kristo Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/cpuidle34xx.c | 58 +++++++++++++++++++++++++++++++++++++-- arch/arm/mach-omap2/pm34xx.c | 14 +--------- 2 files changed, 56 insertions(+), 16 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c index 3d3d035..8ea012e 100644 --- a/arch/arm/mach-omap2/cpuidle34xx.c +++ b/arch/arm/mach-omap2/cpuidle34xx.c @@ -60,7 +60,8 @@ struct omap3_processor_cx { struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES]; struct omap3_processor_cx current_cx_state; -struct powerdomain *mpu_pd, *core_pd; +struct powerdomain *mpu_pd, *core_pd, *per_pd; +struct powerdomain *cam_pd; /* * The latencies/thresholds for various C states have @@ -233,14 +234,62 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev, struct cpuidle_state *state) { struct cpuidle_state *new_state = next_valid_state(dev, state); + u32 core_next_state, per_next_state = 0, per_saved_state = 0; + u32 cam_state; + struct omap3_processor_cx *cx; + int ret; if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) { BUG_ON(!dev->safe_state); new_state = dev->safe_state; + goto select_state; + } + + cx = cpuidle_get_statedata(state); + core_next_state = cx->core_state; + + /* + * FIXME: we currently manage device-specific idle states + * for PER and CORE in combination with CPU-specific + * idle states. This is wrong, and device-specific + * idle managment needs to be separated out into + * its own code. + */ + + /* + * Prevent idle completely if CAM is active. + * CAM does not have wakeup capability in OMAP3. + */ + cam_state = pwrdm_read_pwrst(cam_pd); + if (cam_state == PWRDM_POWER_ON) { + new_state = dev->safe_state; + goto select_state; + } + + /* + * Prevent PER off if CORE is not in retention or off as this + * would disable PER wakeups completely. + */ + per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd); + if ((per_next_state == PWRDM_POWER_OFF) && + (core_next_state > PWRDM_POWER_RET)) { + per_next_state = PWRDM_POWER_RET; + pwrdm_set_next_pwrst(per_pd, per_next_state); } + /* Are we changing PER target state? */ + if (per_next_state != per_saved_state) + pwrdm_set_next_pwrst(per_pd, per_next_state); + +select_state: dev->last_state = new_state; - return omap3_enter_idle(dev, new_state); + ret = omap3_enter_idle(dev, new_state); + + /* Restore original PER state if it was modified */ + if (per_next_state != per_saved_state) + pwrdm_set_next_pwrst(per_pd, per_saved_state); + + return ret; } DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev); @@ -328,7 +377,8 @@ void omap_init_power_states(void) cpuidle_params_table[OMAP3_STATE_C2].threshold; omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_ON; omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON; - omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID; + omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID | + CPUIDLE_FLAG_CHECK_BM; /* C3 . MPU CSWR + Core inactive */ omap3_power_states[OMAP3_STATE_C3].valid = @@ -426,6 +476,8 @@ int __init omap3_idle_init(void) mpu_pd = pwrdm_lookup("mpu_pwrdm"); core_pd = pwrdm_lookup("core_pwrdm"); + per_pd = pwrdm_lookup("per_pwrdm"); + cam_pd = pwrdm_lookup("cam_pwrdm"); omap_init_power_states(); cpuidle_register_driver(&omap3_idle_driver); diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 429268e..bb2ba1e 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -346,7 +346,6 @@ void omap_sram_idle(void) int core_next_state = PWRDM_POWER_ON; int core_prev_state, per_prev_state; u32 sdrc_pwr = 0; - int per_state_modified = 0; if (!_omap_sram_idle) return; @@ -391,19 +390,10 @@ void omap_sram_idle(void) if (per_next_state < PWRDM_POWER_ON) { omap_uart_prepare_idle(2); omap2_gpio_prepare_for_idle(per_next_state); - if (per_next_state == PWRDM_POWER_OFF) { - if (core_next_state == PWRDM_POWER_ON) { - per_next_state = PWRDM_POWER_RET; - pwrdm_set_next_pwrst(per_pwrdm, per_next_state); - per_state_modified = 1; - } else + if (per_next_state == PWRDM_POWER_OFF) omap3_per_save_context(); - } } - if (pwrdm_read_pwrst(cam_pwrdm) == PWRDM_POWER_ON) - omap2_clkdm_deny_idle(mpu_pwrdm->pwrdm_clkdms[0]); - /* CORE */ if (core_next_state < PWRDM_POWER_ON) { omap_uart_prepare_idle(0); @@ -470,8 +460,6 @@ void omap_sram_idle(void) if (per_prev_state == PWRDM_POWER_OFF) omap3_per_restore_context(); omap_uart_resume_idle(2); - if (per_state_modified) - pwrdm_set_next_pwrst(per_pwrdm, PWRDM_POWER_OFF); } /* Disable IO-PAD and IO-CHAIN wakeup */ -- cgit v1.1 From b3294e2327718e9487e662d1392b36b39f07d70b Mon Sep 17 00:00:00 2001 From: Thara Gopinath Date: Wed, 1 Sep 2010 13:44:53 +0530 Subject: OMAP4: pm.c extensions for OMAP4 support OMAP4 has an iva device and a dsp devcice where as OMAP2/3 has only an iva device. In this file the iva device in the system is registered under the name dsp_dev and the API to retrieve the iva device is omap2_get_dsp_device. This patch renames the dsp_dev to iva_dev, renames omap2_get_dsp_device to omap2_get_iva_device, registers dsp_dev for OMAP4 and adds a new API omap4_get_dsp_device to retrieve the dep_dev. Signed-off-by: Thara Gopinath Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/pm.c | 20 +++++++++++++++----- arch/arm/plat-omap/include/plat/common.h | 3 ++- 2 files changed, 17 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index 68f9f2e..c93921d 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c @@ -21,8 +21,9 @@ static struct omap_device_pm_latency *pm_lats; static struct device *mpu_dev; -static struct device *dsp_dev; +static struct device *iva_dev; static struct device *l3_dev; +static struct device *dsp_dev; struct device *omap2_get_mpuss_device(void) { @@ -30,10 +31,10 @@ struct device *omap2_get_mpuss_device(void) return mpu_dev; } -struct device *omap2_get_dsp_device(void) +struct device *omap2_get_iva_device(void) { - WARN_ON_ONCE(!dsp_dev); - return dsp_dev; + WARN_ON_ONCE(!iva_dev); + return iva_dev; } struct device *omap2_get_l3_device(void) @@ -42,6 +43,13 @@ struct device *omap2_get_l3_device(void) return l3_dev; } +struct device *omap4_get_dsp_device(void) +{ + WARN_ON_ONCE(!dsp_dev); + return dsp_dev; +} +EXPORT_SYMBOL(omap4_get_dsp_device); + /* static int _init_omap_device(struct omap_hwmod *oh, void *user) */ static int _init_omap_device(char *name, struct device **new_dev) { @@ -69,7 +77,9 @@ static int _init_omap_device(char *name, struct device **new_dev) static void omap2_init_processor_devices(void) { _init_omap_device("mpu", &mpu_dev); - _init_omap_device("iva", &dsp_dev); + _init_omap_device("iva", &iva_dev); + if (cpu_is_omap44xx()) + _init_omap_device("dsp", &dsp_dev); _init_omap_device("l3_main", &l3_dev); } diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h index 9776b41..c45dbb9 100644 --- a/arch/arm/plat-omap/include/plat/common.h +++ b/arch/arm/plat-omap/include/plat/common.h @@ -91,7 +91,8 @@ void omap3_map_io(void); }) extern struct device *omap2_get_mpuss_device(void); -extern struct device *omap2_get_dsp_device(void); +extern struct device *omap2_get_iva_device(void); extern struct device *omap2_get_l3_device(void); +extern struct device *omap4_get_dsp_device(void); #endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */ -- cgit v1.1 From 86b0c1e3c07f7fc3a8197a934d9a04476061bed9 Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Wed, 15 Sep 2010 01:03:59 +0530 Subject: omap: pm-debug: Move common debug code to pm-debug.c This patch moves omap2_pm_wakeup_on_timer() and pm debug entries form pm34xx.c to pm-debug.c and export it, so that it is available to other OMAPs Signed-off-by: Santosh Shilimkar Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/pm-debug.c | 18 ++++++++++++++++++ arch/arm/mach-omap2/pm.h | 2 ++ arch/arm/mach-omap2/pm34xx.c | 18 ------------------ 3 files changed, 20 insertions(+), 18 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c index 056ff17..655f9df 100644 --- a/arch/arm/mach-omap2/pm-debug.c +++ b/arch/arm/mach-omap2/pm-debug.c @@ -31,6 +31,7 @@ #include #include #include +#include #include "prm.h" #include "cm.h" @@ -353,6 +354,23 @@ void pm_dbg_update_time(struct powerdomain *pwrdm, int prev) pwrdm->timer = t; } +void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds) +{ + u32 tick_rate, cycles; + + if (!seconds && !milliseconds) + return; + + tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup)); + cycles = tick_rate * seconds + tick_rate * milliseconds / 1000; + omap_dm_timer_stop(gptimer_wakeup); + omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles); + + pr_info("PM: Resume timer in %u.%03u secs" + " (%d ticks at %d ticks/sec.)\n", + seconds, milliseconds, cycles, tick_rate); +} + static int clkdm_dbg_show_counter(struct clockdomain *clkdm, void *user) { struct seq_file *s = (struct seq_file *)user; diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index 3de6ece..4fd021f 100644 --- a/arch/arm/mach-omap2/pm.h +++ b/arch/arm/mach-omap2/pm.h @@ -48,9 +48,11 @@ extern struct omap_dm_timer *gptimer_wakeup; #ifdef CONFIG_PM_DEBUG extern void omap2_pm_dump(int mode, int resume, unsigned int us); +extern void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds); extern int omap2_pm_debug; #else #define omap2_pm_dump(mode, resume, us) do {} while (0); +#define omap2_pm_wakeup_on_timer(seconds, milliseconds) do {} while (0); #define omap2_pm_debug 0 #endif diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index bb2ba1e..bc24fbd 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -38,7 +38,6 @@ #include #include #include -#include #include @@ -550,23 +549,6 @@ out: #ifdef CONFIG_SUSPEND static suspend_state_t suspend_state; -static void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds) -{ - u32 tick_rate, cycles; - - if (!seconds && !milliseconds) - return; - - tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup)); - cycles = tick_rate * seconds + tick_rate * milliseconds / 1000; - omap_dm_timer_stop(gptimer_wakeup); - omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles); - - pr_info("PM: Resume timer in %u.%03u secs" - " (%d ticks at %d ticks/sec.)\n", - seconds, milliseconds, cycles, tick_rate); -} - static int omap3_pm_prepare(void) { disable_hlt(); -- cgit v1.1 From 315e2556f62adb51c40d5422f4134bd3630d8157 Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Wed, 15 Sep 2010 01:04:00 +0530 Subject: omap: pm-debug: Enable wakeup_timer_milliseconds debugfs entry Commit 8e2efde9 added milliseconds suspend wakeup time support but same interface is not exported through debugfs This patch enables the debugfs hook for wakeup_timer_milliseconds Signed-off-by: Santosh Shilimkar Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/pm-debug.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c index 655f9df..af00c17 100644 --- a/arch/arm/mach-omap2/pm-debug.c +++ b/arch/arm/mach-omap2/pm-debug.c @@ -638,6 +638,9 @@ static int __init pm_dbg_init(void) &sleep_while_idle, &pm_dbg_option_fops); (void) debugfs_create_file("wakeup_timer_seconds", S_IRUGO | S_IWUGO, d, &wakeup_timer_seconds, &pm_dbg_option_fops); + (void) debugfs_create_file("wakeup_timer_milliseconds", + S_IRUGO | S_IWUGO, d, &wakeup_timer_milliseconds, + &pm_dbg_option_fops); pm_dbg_init_done = 1; return 0; -- cgit v1.1 From eb6a2c7550560e6619eadb912ea8384ce27964b8 Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Wed, 15 Sep 2010 01:04:01 +0530 Subject: omap: pm: Move set_pwrdm_state routine to common pm.c The set_pwrdm_state() is needed on omap4 as well so move this routine to common pm.c file so that it's available for omap3/4 Signed-off-by: Rajendra Nayak Signed-off-by: Santosh Shilimkar Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/pm.c | 50 +++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-omap2/pm.h | 2 +- arch/arm/mach-omap2/pm34xx.c | 53 ++++---------------------------------------- 3 files changed, 55 insertions(+), 50 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index c93921d..4477d5d 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c @@ -18,6 +18,9 @@ #include #include +#include +#include + static struct omap_device_pm_latency *pm_lats; static struct device *mpu_dev; @@ -83,6 +86,53 @@ static void omap2_init_processor_devices(void) _init_omap_device("l3_main", &l3_dev); } +/* + * This sets pwrdm state (other than mpu & core. Currently only ON & + * RET are supported. Function is assuming that clkdm doesn't have + * hw_sup mode enabled. + */ +int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state) +{ + u32 cur_state; + int sleep_switch = 0; + int ret = 0; + + if (pwrdm == NULL || IS_ERR(pwrdm)) + return -EINVAL; + + while (!(pwrdm->pwrsts & (1 << state))) { + if (state == PWRDM_POWER_OFF) + return ret; + state--; + } + + cur_state = pwrdm_read_next_pwrst(pwrdm); + if (cur_state == state) + return ret; + + if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) { + omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]); + sleep_switch = 1; + pwrdm_wait_transition(pwrdm); + } + + ret = pwrdm_set_next_pwrst(pwrdm, state); + if (ret) { + printk(KERN_ERR "Unable to set state of powerdomain: %s\n", + pwrdm->name); + goto err; + } + + if (sleep_switch) { + omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]); + pwrdm_wait_transition(pwrdm); + pwrdm_state_switch(pwrdm); + } + +err: + return ret; +} + static int __init omap2_common_pm_init(void) { omap2_init_processor_devices(); diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index 4fd021f..77770a1 100644 --- a/arch/arm/mach-omap2/pm.h +++ b/arch/arm/mach-omap2/pm.h @@ -20,7 +20,7 @@ extern void *omap3_secure_ram_storage; extern void omap3_pm_off_mode_enable(int); extern void omap_sram_idle(void); extern int omap3_can_sleep(void); -extern int set_pwrdm_state(struct powerdomain *pwrdm, u32 state); +extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state); extern int omap3_idle_init(void); struct cpuidle_params { diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index bc24fbd..f5f1dbd 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -483,51 +483,6 @@ int omap3_can_sleep(void) return 1; } -/* This sets pwrdm state (other than mpu & core. Currently only ON & - * RET are supported. Function is assuming that clkdm doesn't have - * hw_sup mode enabled. */ -int set_pwrdm_state(struct powerdomain *pwrdm, u32 state) -{ - u32 cur_state; - int sleep_switch = 0; - int ret = 0; - - if (pwrdm == NULL || IS_ERR(pwrdm)) - return -EINVAL; - - while (!(pwrdm->pwrsts & (1 << state))) { - if (state == PWRDM_POWER_OFF) - return ret; - state--; - } - - cur_state = pwrdm_read_next_pwrst(pwrdm); - if (cur_state == state) - return ret; - - if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) { - omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]); - sleep_switch = 1; - pwrdm_wait_transition(pwrdm); - } - - ret = pwrdm_set_next_pwrst(pwrdm, state); - if (ret) { - printk(KERN_ERR "Unable to set state of powerdomain: %s\n", - pwrdm->name); - goto err; - } - - if (sleep_switch) { - omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]); - pwrdm_wait_transition(pwrdm); - pwrdm_state_switch(pwrdm); - } - -err: - return ret; -} - static void omap3_pm_idle(void) { local_irq_disable(); @@ -569,7 +524,7 @@ static int omap3_pm_suspend(void) pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); /* Set ones wanted by suspend */ list_for_each_entry(pwrst, &pwrst_list, node) { - if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) + if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) goto restore; if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) goto restore; @@ -590,7 +545,7 @@ restore: pwrst->pwrdm->name, pwrst->next_state); ret = -1; } - set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); + omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); } if (ret) printk(KERN_ERR "Could not enter target state in pm_suspend\n"); @@ -939,7 +894,7 @@ void omap3_pm_off_mode_enable(int enable) list_for_each_entry(pwrst, &pwrst_list, node) { pwrst->next_state = state; - set_pwrdm_state(pwrst->pwrdm, state); + omap_set_pwrdm_state(pwrst->pwrdm, state); } } @@ -984,7 +939,7 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) if (pwrdm_has_hdwr_sar(pwrdm)) pwrdm_enable_hdwr_sar(pwrdm); - return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); + return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); } /* -- cgit v1.1 From 6f7f63cc9adf3192e6fcac4e8bed5cc10fd924aa Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Tue, 14 Sep 2010 15:56:53 -0600 Subject: OMAP clockdomain: initialize clockdomain registers when the clockdomain layer starts When the clockdomain layer initializes, place all clockdomains into software-supervised mode, and clear all wakeup and sleep dependencies immediately, rather than waiting for the PM code to do this later. This fixes a major bug where critical sleep dependencies added by the hwmod code are cleared during late PM init. As a side benefit, the _init_{wk,sleep}dep_usecount() functions are no longer needed, so remove them. Kevin Hilman did all the really hard work on this, identifying the problem and finding the bug. Signed-off-by: Paul Walmsley Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/clockdomain.c | 110 ++++++-------------------------------- arch/arm/mach-omap2/pm34xx.c | 3 -- 2 files changed, 15 insertions(+), 98 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index 5d80cb8..6fb61b1 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -258,97 +258,6 @@ static void _omap2_clkdm_set_hwsup(struct clockdomain *clkdm, int enable) } -/** - * _init_wkdep_usecount - initialize wkdep usecounts to match hardware - * @clkdm: clockdomain to initialize wkdep usecounts - * - * Initialize the wakeup dependency usecount variables for clockdomain @clkdm. - * If a wakeup dependency is present in the hardware, the usecount will be - * set to 1; otherwise, it will be set to 0. Software should clear all - * software wakeup dependencies prior to calling this function if it wishes - * to ensure that all usecounts start at 0. No return value. - */ -static void _init_wkdep_usecount(struct clockdomain *clkdm) -{ - u32 v; - struct clkdm_dep *cd; - - if (!clkdm->wkdep_srcs) - return; - - for (cd = clkdm->wkdep_srcs; cd->clkdm_name; cd++) { - if (!omap_chip_is(cd->omap_chip)) - continue; - - if (!cd->clkdm && cd->clkdm_name) - cd->clkdm = _clkdm_lookup(cd->clkdm_name); - - if (!cd->clkdm) { - WARN(!cd->clkdm, "clockdomain: %s: wkdep clkdm %s not " - "found\n", clkdm->name, cd->clkdm_name); - continue; - } - - v = prm_read_mod_bits_shift(clkdm->pwrdm.ptr->prcm_offs, - PM_WKDEP, - (1 << cd->clkdm->dep_bit)); - - if (v) - pr_debug("clockdomain: %s: wakeup dependency already " - "set to wake up when %s wakes\n", - clkdm->name, cd->clkdm->name); - - atomic_set(&cd->wkdep_usecount, (v) ? 1 : 0); - } -} - -/** - * _init_sleepdep_usecount - initialize sleepdep usecounts to match hardware - * @clkdm: clockdomain to initialize sleepdep usecounts - * - * Initialize the sleep dependency usecount variables for clockdomain @clkdm. - * If a sleep dependency is present in the hardware, the usecount will be - * set to 1; otherwise, it will be set to 0. Software should clear all - * software sleep dependencies prior to calling this function if it wishes - * to ensure that all usecounts start at 0. No return value. - */ -static void _init_sleepdep_usecount(struct clockdomain *clkdm) -{ - u32 v; - struct clkdm_dep *cd; - - if (!cpu_is_omap34xx()) - return; - - if (!clkdm->sleepdep_srcs) - return; - - for (cd = clkdm->sleepdep_srcs; cd->clkdm_name; cd++) { - if (!omap_chip_is(cd->omap_chip)) - continue; - - if (!cd->clkdm && cd->clkdm_name) - cd->clkdm = _clkdm_lookup(cd->clkdm_name); - - if (!cd->clkdm) { - WARN(!cd->clkdm, "clockdomain: %s: sleepdep clkdm %s " - "not found\n", clkdm->name, cd->clkdm_name); - continue; - } - - v = prm_read_mod_bits_shift(clkdm->pwrdm.ptr->prcm_offs, - OMAP3430_CM_SLEEPDEP, - (1 << cd->clkdm->dep_bit)); - - if (v) - pr_debug("clockdomain: %s: sleep dependency already " - "set to prevent from idling until %s " - "idles\n", clkdm->name, cd->clkdm->name); - - atomic_set(&cd->sleepdep_usecount, (v) ? 1 : 0); - } -}; - /* Public functions */ /** @@ -379,12 +288,17 @@ void clkdm_init(struct clockdomain **clkdms, _autodep_lookup(autodep); /* - * Ensure that the *dep_usecount registers reflect the current - * state of the PRCM. + * Put all clockdomains into software-supervised mode; PM code + * should later enable hardware-supervised mode as appropriate */ list_for_each_entry(clkdm, &clkdm_list, node) { - _init_wkdep_usecount(clkdm); - _init_sleepdep_usecount(clkdm); + if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP) + omap2_clkdm_wakeup(clkdm); + else if (clkdm->flags & CLKDM_CAN_DISABLE_AUTO) + omap2_clkdm_deny_idle(clkdm); + + clkdm_clear_all_wkdeps(clkdm); + clkdm_clear_all_sleepdeps(clkdm); } } @@ -592,6 +506,9 @@ int clkdm_clear_all_wkdeps(struct clockdomain *clkdm) if (!omap_chip_is(cd->omap_chip)) continue; + if (!cd->clkdm && cd->clkdm_name) + cd->clkdm = _clkdm_lookup(cd->clkdm_name); + /* PRM accesses are slow, so minimize them */ mask |= 1 << cd->clkdm->dep_bit; atomic_set(&cd->wkdep_usecount, 0); @@ -752,6 +669,9 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm) if (!omap_chip_is(cd->omap_chip)) continue; + if (!cd->clkdm && cd->clkdm_name) + cd->clkdm = _clkdm_lookup(cd->clkdm_name); + /* PRM accesses are slow, so minimize them */ mask |= 1 << cd->clkdm->dep_bit; atomic_set(&cd->sleepdep_usecount, 0); diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index f5f1dbd..d2b940c 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -949,9 +949,6 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) */ static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) { - clkdm_clear_all_wkdeps(clkdm); - clkdm_clear_all_sleepdeps(clkdm); - if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) omap2_clkdm_allow_idle(clkdm); else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && -- cgit v1.1 From a1ed40cb258ba7a8574e662de5ae6ba4dc314436 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Mon, 23 Aug 2010 10:53:10 -0700 Subject: Revert "OMAP: omap_device: add omap_device_is_valid()" This reverts commit 0007122ad85cc36b1c18c0b59344093ca210d206. The dereference method of checking for a valid omap_device when wrapping a platform_device is rather unsafe and dangerous. Instead, a better way of checking for a valid omap-device is to use a common parent device for all omap_devices, then a check can simply be made using the device parent. The only user of this API was the initial version of the runtime PM core for OMAP. This has now been switched to check device parent, so there are no more users of this API. Acked-by: Paul Walmsley Signed-off-by: Kevin Hilman --- arch/arm/plat-omap/include/plat/omap_device.h | 2 -- arch/arm/plat-omap/omap_device.c | 20 -------------------- 2 files changed, 22 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h index 25cd9ac..bad4c3d 100644 --- a/arch/arm/plat-omap/include/plat/omap_device.h +++ b/arch/arm/plat-omap/include/plat/omap_device.h @@ -62,7 +62,6 @@ * */ struct omap_device { - u32 magic; struct platform_device pdev; struct omap_hwmod **hwmods; struct omap_device_pm_latency *pm_lats; @@ -82,7 +81,6 @@ int omap_device_shutdown(struct platform_device *pdev); /* Core code interface */ -bool omap_device_is_valid(struct omap_device *od); int omap_device_count_resources(struct omap_device *od); int omap_device_fill_resources(struct omap_device *od, struct resource *res); diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c index d2b1609..7f05f49 100644 --- a/arch/arm/plat-omap/omap_device.c +++ b/arch/arm/plat-omap/omap_device.c @@ -90,12 +90,6 @@ #define USE_WAKEUP_LAT 0 #define IGNORE_WAKEUP_LAT 1 -/* - * OMAP_DEVICE_MAGIC: used to determine whether a struct omap_device - * obtained via container_of() is in fact a struct omap_device - */ -#define OMAP_DEVICE_MAGIC 0xf00dcafe - /* Private functions */ /** @@ -414,8 +408,6 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id, od->pm_lats = pm_lats; od->pm_lats_cnt = pm_lats_cnt; - od->magic = OMAP_DEVICE_MAGIC; - if (is_early_device) ret = omap_early_device_register(od); else @@ -627,18 +619,6 @@ int omap_device_align_pm_lat(struct platform_device *pdev, } /** - * omap_device_is_valid - Check if pointer is a valid omap_device - * @od: struct omap_device * - * - * Return whether struct omap_device pointer @od points to a valid - * omap_device. - */ -bool omap_device_is_valid(struct omap_device *od) -{ - return (od && od->magic == OMAP_DEVICE_MAGIC); -} - -/** * omap_device_get_pwrdm - return the powerdomain * associated with @od * @od: struct omap_device * * -- cgit v1.1 From 0d5e825252e184a5608c8a9827b79f591535b806 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Mon, 23 Aug 2010 08:10:55 -0700 Subject: OMAP: omap_device: make all devices a child of a new parent device In order to help differentiate omap_devices from normal platform_devices, make them all a parent of a new common parent device. Then, in order to determine if a platform_device is also an omap_device, checking the parent is all that is needed. Users of this feature are the runtime PM core for OMAP, where we need to know if a device being passed in is an omap_device or not in order to know whether to call the omap_device API with it. In addition, all omap_devices will now show up under /sys/devices/omap instead of /sys/devices/platform Acked-by: Paul Walmsley Signed-off-by: Kevin Hilman --- arch/arm/plat-omap/include/plat/omap_device.h | 2 ++ arch/arm/plat-omap/omap_device.c | 12 ++++++++++++ 2 files changed, 14 insertions(+) (limited to 'arch') diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h index bad4c3d..28e2d1a 100644 --- a/arch/arm/plat-omap/include/plat/omap_device.h +++ b/arch/arm/plat-omap/include/plat/omap_device.h @@ -36,6 +36,8 @@ #include +extern struct device omap_device_parent; + /* omap_device._state values */ #define OMAP_DEVICE_STATE_UNKNOWN 0 #define OMAP_DEVICE_STATE_ENABLED 1 diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c index 7f05f49..8215b1b 100644 --- a/arch/arm/plat-omap/omap_device.c +++ b/arch/arm/plat-omap/omap_device.c @@ -465,6 +465,7 @@ int omap_device_register(struct omap_device *od) { pr_debug("omap_device: %s: registering\n", od->pdev.name); + od->pdev.dev.parent = &omap_device_parent; return platform_device_register(&od->pdev); } @@ -737,3 +738,14 @@ int omap_device_enable_clocks(struct omap_device *od) /* XXX pass along return value here? */ return 0; } + +struct device omap_device_parent = { + .init_name = "omap", + .parent = &platform_bus, +}; + +static int __init omap_device_init(void) +{ + return device_register(&omap_device_parent); +} +core_initcall(omap_device_init); -- cgit v1.1 From 55d2cb0814f4285f89be8ed474a8ae7042fb5735 Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Wed, 12 May 2010 17:54:36 +0200 Subject: OMAP4: hwmod: Add initial data for OMAP4430 ES1 & ES2 The current version contains only the interconnects and the mpu hwmods. The remaining hwmods will be introduced by further patches on top of this one. - enable as well omap_hwmod.c build for OMAP4 Soc Please not that this file uses the new naming convention for naming HW IPs. This convention will be backported soon for previous OMAP2 & 3 data files. new name trm name ------------- ------------------- counter_32k synctimer_32k l3_main l3 timerX gptimerX / dmtimerX mmcX mmchsX / sdmmcX dma_system sdma smartreflex_X sr_X / sr? usb_host_fs usbfshost usb_otg_hs hsusbotg usb_tll_hs usbtllhs_config wd_timerX wdtimerX ipu cortexm3 / ducati dsp c6x / tesla iva ivahd / iva2.2 kbd kbdocp / keyboard mailbox system_mailbox mpu cortexa9 / chiron Signed-off-by: Benoit Cousson Cc: Paul Walmsley Cc: Kevin Hilman Cc: Rajendra Nayak Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/Makefile | 1 + arch/arm/mach-omap2/io.c | 7 +- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 482 +++++++++++++++++++++++++++ arch/arm/plat-omap/Makefile | 2 +- arch/arm/plat-omap/include/plat/omap_hwmod.h | 1 + 5 files changed, 489 insertions(+), 4 deletions(-) create mode 100644 arch/arm/mach-omap2/omap_hwmod_44xx_data.c (limited to 'arch') diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 88d3a1e..29d40b2 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -87,6 +87,7 @@ obj-$(CONFIG_ARCH_OMAP2430) += opp2430_data.o obj-$(CONFIG_ARCH_OMAP2420) += omap_hwmod_2420_data.o obj-$(CONFIG_ARCH_OMAP2430) += omap_hwmod_2430_data.o obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o +obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o # EMU peripherals obj-$(CONFIG_OMAP3_EMU) += emu.o diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index b9ea70b..490d870 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -323,6 +323,9 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, omap2430_hwmod_init(); else if (cpu_is_omap34xx()) omap3xxx_hwmod_init(); + else if (cpu_is_omap44xx()) + omap44xx_hwmod_init(); + /* The OPP tables have to be registered before a clk init */ omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps); @@ -342,9 +345,7 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, #ifndef CONFIG_PM_RUNTIME skip_setup_idle = 1; #endif - if (cpu_is_omap24xx() || cpu_is_omap34xx()) /* FIXME: OMAP4 */ - omap_hwmod_late_init(skip_setup_idle); - + omap_hwmod_late_init(skip_setup_idle); if (cpu_is_omap24xx() || cpu_is_omap34xx()) { omap2_sdrc_init(sdrc_cs0, sdrc_cs1); _omap2_init_reprogram_sdrc(); diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c new file mode 100644 index 0000000..e20b0ee --- /dev/null +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -0,0 +1,482 @@ +/* + * Hardware modules present on the OMAP44xx chips + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * Copyright (C) 2009-2010 Nokia Corporation + * + * Paul Walmsley + * Benoit Cousson + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include + +#include +#include + +#include "omap_hwmod_common_data.h" + +#include "cm.h" +#include "prm-regbits-44xx.h" + +/* Base offset for all OMAP4 interrupts external to MPUSS */ +#define OMAP44XX_IRQ_GIC_START 32 + +/* Base offset for all OMAP4 dma requests */ +#define OMAP44XX_DMA_REQ_START 1 + +/* Backward references (IPs with Bus Master capability) */ +static struct omap_hwmod omap44xx_dmm_hwmod; +static struct omap_hwmod omap44xx_emif_fw_hwmod; +static struct omap_hwmod omap44xx_l3_instr_hwmod; +static struct omap_hwmod omap44xx_l3_main_1_hwmod; +static struct omap_hwmod omap44xx_l3_main_2_hwmod; +static struct omap_hwmod omap44xx_l3_main_3_hwmod; +static struct omap_hwmod omap44xx_l4_abe_hwmod; +static struct omap_hwmod omap44xx_l4_cfg_hwmod; +static struct omap_hwmod omap44xx_l4_per_hwmod; +static struct omap_hwmod omap44xx_l4_wkup_hwmod; +static struct omap_hwmod omap44xx_mpu_hwmod; +static struct omap_hwmod omap44xx_mpu_private_hwmod; + +/* + * Interconnects omap_hwmod structures + * hwmods that compose the global OMAP interconnect + */ + +/* + * 'dmm' class + * instance(s): dmm + */ +static struct omap_hwmod_class omap44xx_dmm_hwmod_class = { + .name = "dmm", +}; + +/* dmm interface data */ +/* l3_main_1 -> dmm */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { + .master = &omap44xx_l3_main_1_hwmod, + .slave = &omap44xx_dmm_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mpu -> dmm */ +static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = { + .master = &omap44xx_mpu_hwmod, + .slave = &omap44xx_dmm_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dmm slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = { + &omap44xx_l3_main_1__dmm, + &omap44xx_mpu__dmm, +}; + +static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = { + { .irq = 113 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod omap44xx_dmm_hwmod = { + .name = "dmm", + .class = &omap44xx_dmm_hwmod_class, + .slaves = omap44xx_dmm_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves), + .mpu_irqs = omap44xx_dmm_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmm_irqs), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* + * 'emif_fw' class + * instance(s): emif_fw + */ +static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = { + .name = "emif_fw", +}; + +/* emif_fw interface data */ +/* dmm -> emif_fw */ +static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = { + .master = &omap44xx_dmm_hwmod, + .slave = &omap44xx_emif_fw_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_cfg -> emif_fw */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_emif_fw_hwmod, + .clk = "l4_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* emif_fw slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = { + &omap44xx_dmm__emif_fw, + &omap44xx_l4_cfg__emif_fw, +}; + +static struct omap_hwmod omap44xx_emif_fw_hwmod = { + .name = "emif_fw", + .class = &omap44xx_emif_fw_hwmod_class, + .slaves = omap44xx_emif_fw_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* + * 'l3' class + * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3 + */ +static struct omap_hwmod_class omap44xx_l3_hwmod_class = { + .name = "l3", +}; + +/* l3_instr interface data */ +/* l3_main_3 -> l3_instr */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = { + .master = &omap44xx_l3_main_3_hwmod, + .slave = &omap44xx_l3_instr_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_instr slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = { + &omap44xx_l3_main_3__l3_instr, +}; + +static struct omap_hwmod omap44xx_l3_instr_hwmod = { + .name = "l3_instr", + .class = &omap44xx_l3_hwmod_class, + .slaves = omap44xx_l3_instr_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* l3_main_2 -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_l3_main_1_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_cfg -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_l3_main_1_hwmod, + .clk = "l4_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mpu -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { + .master = &omap44xx_mpu_hwmod, + .slave = &omap44xx_l3_main_1_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = { + &omap44xx_l3_main_2__l3_main_1, + &omap44xx_l4_cfg__l3_main_1, + &omap44xx_mpu__l3_main_1, +}; + +static struct omap_hwmod omap44xx_l3_main_1_hwmod = { + .name = "l3_main_1", + .class = &omap44xx_l3_hwmod_class, + .slaves = omap44xx_l3_main_1_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* l3_main_2 interface data */ +/* l3_main_1 -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { + .master = &omap44xx_l3_main_1_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_cfg -> l3_main_2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_l3_main_2_hwmod, + .clk = "l4_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_2 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = { + &omap44xx_l3_main_1__l3_main_2, + &omap44xx_l4_cfg__l3_main_2, +}; + +static struct omap_hwmod omap44xx_l3_main_2_hwmod = { + .name = "l3_main_2", + .class = &omap44xx_l3_hwmod_class, + .slaves = omap44xx_l3_main_2_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* l3_main_3 interface data */ +/* l3_main_1 -> l3_main_3 */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = { + .master = &omap44xx_l3_main_1_hwmod, + .slave = &omap44xx_l3_main_3_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_2 -> l3_main_3 */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_l3_main_3_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_cfg -> l3_main_3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_l3_main_3_hwmod, + .clk = "l4_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_3 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = { + &omap44xx_l3_main_1__l3_main_3, + &omap44xx_l3_main_2__l3_main_3, + &omap44xx_l4_cfg__l3_main_3, +}; + +static struct omap_hwmod omap44xx_l3_main_3_hwmod = { + .name = "l3_main_3", + .class = &omap44xx_l3_hwmod_class, + .slaves = omap44xx_l3_main_3_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* + * 'l4' class + * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup + */ +static struct omap_hwmod_class omap44xx_l4_hwmod_class = { + .name = "l4", +}; + +/* l4_abe interface data */ +/* l3_main_1 -> l4_abe */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = { + .master = &omap44xx_l3_main_1_hwmod, + .slave = &omap44xx_l4_abe_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mpu -> l4_abe */ +static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = { + .master = &omap44xx_mpu_hwmod, + .slave = &omap44xx_l4_abe_hwmod, + .clk = "ocp_abe_iclk", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_abe slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = { + &omap44xx_l3_main_1__l4_abe, + &omap44xx_mpu__l4_abe, +}; + +static struct omap_hwmod omap44xx_l4_abe_hwmod = { + .name = "l4_abe", + .class = &omap44xx_l4_hwmod_class, + .slaves = omap44xx_l4_abe_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* l4_cfg interface data */ +/* l3_main_1 -> l4_cfg */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = { + .master = &omap44xx_l3_main_1_hwmod, + .slave = &omap44xx_l4_cfg_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_cfg slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = { + &omap44xx_l3_main_1__l4_cfg, +}; + +static struct omap_hwmod omap44xx_l4_cfg_hwmod = { + .name = "l4_cfg", + .class = &omap44xx_l4_hwmod_class, + .slaves = omap44xx_l4_cfg_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* l4_per interface data */ +/* l3_main_2 -> l4_per */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_l4_per_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = { + &omap44xx_l3_main_2__l4_per, +}; + +static struct omap_hwmod omap44xx_l4_per_hwmod = { + .name = "l4_per", + .class = &omap44xx_l4_hwmod_class, + .slaves = omap44xx_l4_per_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* l4_wkup interface data */ +/* l4_cfg -> l4_wkup */ +static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = { + .master = &omap44xx_l4_cfg_hwmod, + .slave = &omap44xx_l4_wkup_hwmod, + .clk = "l4_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = { + &omap44xx_l4_cfg__l4_wkup, +}; + +static struct omap_hwmod omap44xx_l4_wkup_hwmod = { + .name = "l4_wkup", + .class = &omap44xx_l4_hwmod_class, + .slaves = omap44xx_l4_wkup_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* + * 'mpu_bus' class + * instance(s): mpu_private + */ +static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = { + .name = "mpu_bus", +}; + +/* mpu_private interface data */ +/* mpu -> mpu_private */ +static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = { + .master = &omap44xx_mpu_hwmod, + .slave = &omap44xx_mpu_private_hwmod, + .clk = "l3_div_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mpu_private slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = { + &omap44xx_mpu__mpu_private, +}; + +static struct omap_hwmod omap44xx_mpu_private_hwmod = { + .name = "mpu_private", + .class = &omap44xx_mpu_bus_hwmod_class, + .slaves = omap44xx_mpu_private_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* + * 'mpu' class + * mpu sub-system + */ + +static struct omap_hwmod_class omap44xx_mpu_hwmod_class = { + .name = "mpu", +}; + +/* mpu */ +static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = { + { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START }, + { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START }, + { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START }, +}; + +/* mpu master ports */ +static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = { + &omap44xx_mpu__l3_main_1, + &omap44xx_mpu__l4_abe, + &omap44xx_mpu__dmm, +}; + +static struct omap_hwmod omap44xx_mpu_hwmod = { + .name = "mpu", + .class = &omap44xx_mpu_hwmod_class, + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), + .mpu_irqs = omap44xx_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mpu_irqs), + .main_clk = "dpll_mpu_m2_ck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL, + }, + }, + .masters = omap44xx_mpu_masters, + .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +static __initdata struct omap_hwmod *omap44xx_hwmods[] = { + /* dmm class */ + &omap44xx_dmm_hwmod, + /* emif_fw class */ + &omap44xx_emif_fw_hwmod, + /* l3 class */ + &omap44xx_l3_instr_hwmod, + &omap44xx_l3_main_1_hwmod, + &omap44xx_l3_main_2_hwmod, + &omap44xx_l3_main_3_hwmod, + /* l4 class */ + &omap44xx_l4_abe_hwmod, + &omap44xx_l4_cfg_hwmod, + &omap44xx_l4_per_hwmod, + &omap44xx_l4_wkup_hwmod, + /* mpu_bus class */ + &omap44xx_mpu_private_hwmod, + + /* mpu class */ + &omap44xx_mpu_hwmod, + NULL, +}; + +int __init omap44xx_hwmod_init(void) +{ + return omap_hwmod_init(omap44xx_hwmods); +} + diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile index 9405831..2a15191 100644 --- a/arch/arm/plat-omap/Makefile +++ b/arch/arm/plat-omap/Makefile @@ -31,4 +31,4 @@ obj-y += $(i2c-omap-m) $(i2c-omap-y) # OMAP mailbox framework obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox.o -obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o \ No newline at end of file +obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index a4e508d..cab4a68 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -534,5 +534,6 @@ int omap_hwmod_for_each_by_class(const char *classname, extern int omap2420_hwmod_init(void); extern int omap2430_hwmod_init(void); extern int omap3xxx_hwmod_init(void); +extern int omap44xx_hwmod_init(void); #endif -- cgit v1.1 From cbf27660e692d8c74087c0ccb80225207d280af1 Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Thu, 5 Aug 2010 15:22:35 +0200 Subject: OMAP4: pm: Change l3_main to l3_main_1 during bus device init The OMAP4 L3 interconnect is split in 3 part for power saving reason. Because of that there is no l3_main like on OMAP2 & 3 but 3 differentes l3_main_X instances. In the case of OMAP4, query only the l3_main_1 part. The clock and voltage are shared across the 3 instances. Signed-off-by: Benoit Cousson Cc: Paul Walmsley Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/pm.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index 4477d5d..59ca03b 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c @@ -81,9 +81,12 @@ static void omap2_init_processor_devices(void) { _init_omap_device("mpu", &mpu_dev); _init_omap_device("iva", &iva_dev); - if (cpu_is_omap44xx()) + if (cpu_is_omap44xx()) { + _init_omap_device("l3_main_1", &l3_dev); _init_omap_device("dsp", &dsp_dev); - _init_omap_device("l3_main", &l3_dev); + } else { + _init_omap_device("l3_main", &l3_dev); + } } /* -- cgit v1.1 From 0aed043517ad4135cb458a46e9e99e21cbb59c69 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Wed, 22 Sep 2010 16:06:27 -0700 Subject: OMAP: GPIO: ensure debounce clocks are disabled during idle/suspend If a GPIO bank has more than one GPIO with debounce enabled, the debounce clock will not be fully disabled before going to idle/suspend. In the idle path, we just do a single clk_disable() of the bank's debounce clock. If there are multiple debounce-enabled GPIOs in the bank, that clocks usage count will be > 1, so the clk_disable() will not actually disable the clock. So the fix is to clk_disable() for every debounce-enabled GPIO in the bank (and an equivalent clk_enable() of course.) Signed-off-by: Kevin Hilman --- arch/arm/plat-omap/gpio.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index 7951eef..11c5b0e 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -2085,8 +2085,9 @@ void omap2_gpio_prepare_for_idle(int power_state) for (i = min; i < gpio_bank_count; i++) { struct gpio_bank *bank = &gpio_bank[i]; u32 l1, l2; + int j; - if (bank->dbck_enable_mask) + for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) clk_disable(bank->dbck); if (power_state > PWRDM_POWER_OFF) @@ -2152,8 +2153,9 @@ void omap2_gpio_resume_after_idle(void) for (i = min; i < gpio_bank_count; i++) { struct gpio_bank *bank = &gpio_bank[i]; u32 l, gen, gen0, gen1; + int j; - if (bank->dbck_enable_mask) + for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) clk_enable(bank->dbck); if (!workaround_enabled) -- cgit v1.1 From 0df891bb9c36c57d09c8b7cf28904e3672d93f9e Mon Sep 17 00:00:00 2001 From: Shubhrajyoti Datta Date: Thu, 23 Sep 2010 18:22:47 -0700 Subject: hmc5843: Digital compass board file The board file changes for the digital compass hmc5843. The interface to the device is i2c. Signed-off-by: Shubhrajyoti D Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-4430sdp.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index 9447644..5b6a48d 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -412,6 +412,11 @@ static struct i2c_board_info __initdata sdp4430_i2c_3_boardinfo[] = { I2C_BOARD_INFO("tmp105", 0x48), }, }; +static struct i2c_board_info __initdata sdp4430_i2c_4_boardinfo[] = { + { + I2C_BOARD_INFO("hmc5843", 0x1e), + }, +}; static int __init omap4_i2c_init(void) { /* @@ -423,7 +428,8 @@ static int __init omap4_i2c_init(void) omap_register_i2c_bus(2, 400, NULL, 0); omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo, ARRAY_SIZE(sdp4430_i2c_3_boardinfo)); - omap_register_i2c_bus(4, 400, NULL, 0); + omap_register_i2c_bus(4, 400, sdp4430_i2c_4_boardinfo, + ARRAY_SIZE(sdp4430_i2c_4_boardinfo)); return 0; } static void __init omap_4430sdp_init(void) -- cgit v1.1 From 954bed046fe57724851879a9db813eecb1d15f55 Mon Sep 17 00:00:00 2001 From: Robert Nelson Date: Thu, 23 Sep 2010 18:22:47 -0700 Subject: omap: Beagle: revision detection Due to the omap3530 ES3.0 Silicon being used on both the B5/B6 and C1/2/3 Beagle we can't use the cpu_is_omap34xx() routines to differentiate the Beagle Boards. However gpio pins 171,172,173 where setup for this prupose, so lets use them. Changes: for older U-Boot's, use omap_mux_init_gpio() keep Beagle Rev in board-omap3beagle.c gpio_free on gpio request failure Tested on Beagle Revisions: B5, C2, C4, and xMA Signed-off-by: Robert Nelson Acked-by: Jarkko Nikula Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-omap3beagle.c | 88 +++++++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 87969c7..1aebb3f 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -50,6 +50,93 @@ #define NAND_BLOCK_SIZE SZ_128K +/* + * OMAP3 Beagle revision + * Run time detection of Beagle revision is done by reading GPIO. + * GPIO ID - + * AXBX = GPIO173, GPIO172, GPIO171: 1 1 1 + * C1_3 = GPIO173, GPIO172, GPIO171: 1 1 0 + * C4 = GPIO173, GPIO172, GPIO171: 1 0 1 + * XM = GPIO173, GPIO172, GPIO171: 0 0 0 + */ +enum { + OMAP3BEAGLE_BOARD_UNKN = 0, + OMAP3BEAGLE_BOARD_AXBX, + OMAP3BEAGLE_BOARD_C1_3, + OMAP3BEAGLE_BOARD_C4, + OMAP3BEAGLE_BOARD_XM, +}; + +static u8 omap3_beagle_version; + +static u8 omap3_beagle_get_rev(void) +{ + return omap3_beagle_version; +} + +static void __init omap3_beagle_init_rev(void) +{ + int ret; + u16 beagle_rev = 0; + + omap_mux_init_gpio(171, OMAP_PIN_INPUT_PULLUP); + omap_mux_init_gpio(172, OMAP_PIN_INPUT_PULLUP); + omap_mux_init_gpio(173, OMAP_PIN_INPUT_PULLUP); + + ret = gpio_request(171, "rev_id_0"); + if (ret < 0) + goto fail0; + + ret = gpio_request(172, "rev_id_1"); + if (ret < 0) + goto fail1; + + ret = gpio_request(173, "rev_id_2"); + if (ret < 0) + goto fail2; + + gpio_direction_input(171); + gpio_direction_input(172); + gpio_direction_input(173); + + beagle_rev = gpio_get_value(171) | (gpio_get_value(172) << 1) + | (gpio_get_value(173) << 2); + + switch (beagle_rev) { + case 7: + printk(KERN_INFO "OMAP3 Beagle Rev: Ax/Bx\n"); + omap3_beagle_version = OMAP3BEAGLE_BOARD_AXBX; + break; + case 6: + printk(KERN_INFO "OMAP3 Beagle Rev: C1/C2/C3\n"); + omap3_beagle_version = OMAP3BEAGLE_BOARD_C1_3; + break; + case 5: + printk(KERN_INFO "OMAP3 Beagle Rev: C4\n"); + omap3_beagle_version = OMAP3BEAGLE_BOARD_C4; + break; + case 0: + printk(KERN_INFO "OMAP3 Beagle Rev: xM\n"); + omap3_beagle_version = OMAP3BEAGLE_BOARD_XM; + break; + default: + printk(KERN_INFO "OMAP3 Beagle Rev: unknown %hd\n", beagle_rev); + omap3_beagle_version = OMAP3BEAGLE_BOARD_UNKN; + } + + return; + +fail2: + gpio_free(172); +fail1: + gpio_free(171); +fail0: + printk(KERN_ERR "Unable to get revision detection GPIO pins\n"); + omap3_beagle_version = OMAP3BEAGLE_BOARD_UNKN; + + return; +} + static struct mtd_partition omap3beagle_nand_partitions[] = { /* All the partition sizes are listed in terms of NAND block size */ { @@ -464,6 +551,7 @@ static struct omap_musb_board_data musb_board_data = { static void __init omap3_beagle_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); + omap3_beagle_init_rev(); omap3_beagle_i2c_init(); platform_add_devices(omap3_beagle_devices, ARRAY_SIZE(omap3_beagle_devices)); -- cgit v1.1 From e4916e117a4fcd001a1be777e406ec1f98b75de4 Mon Sep 17 00:00:00 2001 From: Robert Nelson Date: Thu, 23 Sep 2010 18:22:48 -0700 Subject: omap: Beagle: only Cx boards use pin 23 for write protect system_rev comes from u-boot and is a constant 0x20, so Bx boards also fall in this 'if' and will get setup with the wrong gpio_wp pin. Switch to using the Beagle revision routine to correcly set pin 23 only for C1/2/3 and C4 Boards. Bx boards will then use the correct default pin setting. Signed-off-by: Robert Nelson Acked-by: Jarkko Nikula Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-omap3beagle.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 1aebb3f..1908b33 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -272,7 +272,8 @@ static struct gpio_led gpio_leds[]; static int beagle_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio) { - if (system_rev >= 0x20 && system_rev <= 0x34301000) { + if ((omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_C1_3) || + (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_C4)) { omap_mux_init_gpio(23, OMAP_PIN_INPUT); mmc[0].gpio_wp = 23; } else { -- cgit v1.1 From cf74d41ea07fe6066daea7df74d9550bc2c64284 Mon Sep 17 00:00:00 2001 From: Robert Nelson Date: Thu, 23 Sep 2010 18:22:48 -0700 Subject: omap: Beagle: no gpio_wp pin connection on xM The omap3630 based BeagleBoard xM uses a MicroSD card slot with no write protection. Signed-off-by: Robert Nelson Acked-by: Jarkko Nikula Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-omap3beagle.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 1908b33..5534841 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -272,7 +272,9 @@ static struct gpio_led gpio_leds[]; static int beagle_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio) { - if ((omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_C1_3) || + if (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_XM) { + mmc[0].gpio_wp = -EINVAL; + } else if ((omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_C1_3) || (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_C4)) { omap_mux_init_gpio(23, OMAP_PIN_INPUT); mmc[0].gpio_wp = 23; -- cgit v1.1 From e3333f48dd5cb21b8d43d6d3a434055815084f1e Mon Sep 17 00:00:00 2001 From: "Mathieu J. Poirier" Date: Thu, 23 Sep 2010 18:22:48 -0700 Subject: omap: Adding beagle i2c eeprom driver to read EDID Adding i2c eeprom driver to access monitor EDID binary information from user space, something that is required by 'decode-edid' and 'parse-edid'. BugLink: https://bugs.launchpad.net/bugs/608279 Signed-off-by: Mathieu Poirier Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-omap3beagle.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 5534841..e27f3bf 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -412,13 +412,19 @@ static struct i2c_board_info __initdata beagle_i2c_boardinfo[] = { }, }; +static struct i2c_board_info __initdata beagle_i2c_eeprom[] = { + { + I2C_BOARD_INFO("eeprom", 0x50), + }, +}; + static int __init omap3_beagle_i2c_init(void) { omap_register_i2c_bus(1, 2600, beagle_i2c_boardinfo, ARRAY_SIZE(beagle_i2c_boardinfo)); /* Bus 3 is attached to the DVI port where devices like the pico DLP * projector don't work reliably with 400kHz */ - omap_register_i2c_bus(3, 100, NULL, 0); + omap_register_i2c_bus(3, 100, beagle_i2c_eeprom, ARRAY_SIZE(beagle_i2c_eeprom)); return 0; } -- cgit v1.1 From ca828760f96ee8f0b6c93400599844761aa69dc0 Mon Sep 17 00:00:00 2001 From: Sanjeev Premi Date: Thu, 23 Sep 2010 18:27:18 -0700 Subject: omap2: fix assorted compiler warnings This patch fixes these compiler warnings: CC arch/arm/mach-omap2/mux.o arch/arm/mach-omap2/mux.c: In function 'omap_mux_init_gpio': arch/arm/mach-omap2/mux.c:90: warning: 'gpio_mux' may be used uninitial ized in this function CC arch/arm/plat-omap/gpio.o arch/arm/plat-omap/gpio.c: In function 'omap2_gpio_resume_after_idle': arch/arm/plat-omap/gpio.c:2152: warning: 'l' may be used uninitialized in this function arch/arm/plat-omap/gpio.c: In function 'omap2_gpio_prepare_for_idle': arch/arm/plat-omap/gpio.c:2085: warning: 'l2' may be used uninitialized in this function arch/arm/plat-omap/gpio.c:2085: warning: 'l1' may be used uninitialized in this function CC arch/arm/mach-omap2/board-omap4panda.o arch/arm/mach-omap2/board-omap4panda.c: In function 'omap4_panda_init': arch/arm/mach-omap2/board-omap4panda.c:277: warning: unused variable 's tatus' Signed-off-by: Sanjeev Premi Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-omap4panda.c | 2 -- arch/arm/mach-omap2/mux.c | 2 +- arch/arm/plat-omap/gpio.c | 4 ++-- 3 files changed, 3 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index c03d1d5..96f5bbb 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -274,8 +274,6 @@ static int __init omap4_panda_i2c_init(void) } static void __init omap4_panda_init(void) { - int status; - omap4_panda_i2c_init(); omap_serial_init(); omap4_twl6030_hsmmc_init(mmc); diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index ab403b2..6c2f8f0 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c @@ -87,7 +87,7 @@ static char *omap_mux_options; int __init omap_mux_init_gpio(int gpio, int val) { struct omap_mux_entry *e; - struct omap_mux *gpio_mux; + struct omap_mux *gpio_mux = NULL; u16 old_mode; u16 mux_mode; int found = 0; diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index 11c5b0e..c05c653 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -2084,7 +2084,7 @@ void omap2_gpio_prepare_for_idle(int power_state) for (i = min; i < gpio_bank_count; i++) { struct gpio_bank *bank = &gpio_bank[i]; - u32 l1, l2; + u32 l1 = 0, l2 = 0; int j; for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) @@ -2152,7 +2152,7 @@ void omap2_gpio_resume_after_idle(void) min = 1; for (i = min; i < gpio_bank_count; i++) { struct gpio_bank *bank = &gpio_bank[i]; - u32 l, gen, gen0, gen1; + u32 l = 0, gen, gen0, gen1; int j; for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) -- cgit v1.1 From a7f97d25c707e1020bd7bcb443e183860e5abf48 Mon Sep 17 00:00:00 2001 From: Jarkko Nikula Date: Fri, 20 Aug 2010 09:36:28 +0300 Subject: omap: n8x0: Cleanup i2c1 and menelaus registration - Move n8x0_i2c_board_info_1 out from #ifdef CONFIG_MENELAUS block, register i2c1 in n8x0_init_machine and do a few clean-ups around these. Code looks better if board infos are grouped together - Mark n8x0_i2c_board_info_1 and n8x0_menelaus_platform_data with __initdata Signed-off-by: Jarkko Nikula Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-n8x0.c | 34 +++++++++++++++------------------- 1 file changed, 15 insertions(+), 19 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c index a3e2b49..313ce5e 100644 --- a/arch/arm/mach-omap2/board-n8x0.c +++ b/arch/arm/mach-omap2/board-n8x0.c @@ -614,30 +614,25 @@ static int n8x0_menelaus_late_init(struct device *dev) return 0; } -static struct i2c_board_info __initdata n8x0_i2c_board_info_1[] = { +#else +static int n8x0_menelaus_late_init(struct device *dev) +{ + return 0; +} +#endif + +static struct menelaus_platform_data n8x0_menelaus_platform_data __initdata = { + .late_init = n8x0_menelaus_late_init, +}; + +static struct i2c_board_info __initdata n8x0_i2c_board_info_1[] __initdata = { { I2C_BOARD_INFO("menelaus", 0x72), .irq = INT_24XX_SYS_NIRQ, + .platform_data = &n8x0_menelaus_platform_data, }, }; -static struct menelaus_platform_data n8x0_menelaus_platform_data = { - .late_init = n8x0_menelaus_late_init, -}; - -static void __init n8x0_menelaus_init(void) -{ - n8x0_i2c_board_info_1[0].platform_data = &n8x0_menelaus_platform_data; - omap_register_i2c_bus(1, 400, n8x0_i2c_board_info_1, - ARRAY_SIZE(n8x0_i2c_board_info_1)); -} - -#else -static inline void __init n8x0_menelaus_init(void) -{ -} -#endif - static void __init n8x0_map_io(void) { omap2_set_globals_242x(); @@ -665,9 +660,10 @@ static void __init n8x0_init_machine(void) /* FIXME: add n810 spi devices */ spi_register_board_info(n800_spi_board_info, ARRAY_SIZE(n800_spi_board_info)); + omap_register_i2c_bus(1, 400, n8x0_i2c_board_info_1, + ARRAY_SIZE(n8x0_i2c_board_info_1)); omap_serial_init(); - n8x0_menelaus_init(); n8x0_onenand_init(); n8x0_mmc_init(); n8x0_usb_init(); -- cgit v1.1 From 366498d4f2aef7640ae467a986d69d1cc06a141b Mon Sep 17 00:00:00 2001 From: Jarkko Nikula Date: Fri, 20 Aug 2010 09:36:28 +0300 Subject: omap: n8x0: Register i2c2 and add board info with tlv320aic3xfor N810 Second i2c bus on Nokia N800 and N810 shares both common and hw specific peripherals. Register now this bus and add board info with tlv320aic3x for N810. Common peripherals may be added as an additional board info to omap_register_i2c_bus(2, ...); Signed-off-by: Jarkko Nikula Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-n8x0.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c index 313ce5e..7863633 100644 --- a/arch/arm/mach-omap2/board-n8x0.c +++ b/arch/arm/mach-omap2/board-n8x0.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include @@ -633,6 +634,17 @@ static struct i2c_board_info __initdata n8x0_i2c_board_info_1[] __initdata = { }, }; +static struct aic3x_pdata n810_aic33_data __initdata = { + .gpio_reset = 118, +}; + +static struct i2c_board_info n810_i2c_board_info_2[] __initdata = { + { + I2C_BOARD_INFO("tlv320aic3x", 0x18), + .platform_data = &n810_aic33_data, + }, +}; + static void __init n8x0_map_io(void) { omap2_set_globals_242x(); @@ -662,6 +674,10 @@ static void __init n8x0_init_machine(void) ARRAY_SIZE(n800_spi_board_info)); omap_register_i2c_bus(1, 400, n8x0_i2c_board_info_1, ARRAY_SIZE(n8x0_i2c_board_info_1)); + omap_register_i2c_bus(2, 400, NULL, 0); + if (machine_is_nokia_n810()) + i2c_register_board_info(2, n810_i2c_board_info_2, + ARRAY_SIZE(n810_i2c_board_info_2)); omap_serial_init(); n8x0_onenand_init(); -- cgit v1.1 From 04be1e9ba49657347b4e1969a217e5fc33bbf72a Mon Sep 17 00:00:00 2001 From: Jarkko Nikula Date: Fri, 20 Aug 2010 09:36:28 +0300 Subject: omap: n8x0: Mux i2s codec port pins for McBSP block Bootloader on Nokia N800 and N810 muxes I2C codec port pins for EAC block. As there is no driver and use for EAC, mux those pins for McBSP instead since N810 ASoC drivers can use it. Signed-off-by: Jarkko Nikula Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-n8x0.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c index 7863633..8fd2269 100644 --- a/arch/arm/mach-omap2/board-n8x0.c +++ b/arch/arm/mach-omap2/board-n8x0.c @@ -660,6 +660,11 @@ static void __init n8x0_init_irq(void) #ifdef CONFIG_OMAP_MUX static struct omap_board_mux board_mux[] __initdata = { + /* I2S codec port pins for McBSP block */ + OMAP2420_MUX(EAC_AC_SCLK, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), + OMAP2420_MUX(EAC_AC_FS, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), + OMAP2420_MUX(EAC_AC_DIN, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), + OMAP2420_MUX(EAC_AC_DOUT, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT), { .reg_offset = OMAP_MUX_TERMINATOR }, }; #else -- cgit v1.1 From 2a27753fdc2ab046c754e3e203953dd0d4c1611b Mon Sep 17 00:00:00 2001 From: Vikram Pandita Date: Thu, 16 Sep 2010 18:19:24 +0530 Subject: omap: sram: fix is_sram_locked check For OMAP24xx/34xx/44xx: omap_type() returns the correct type: OMAP2_DEVICE_TYPE_TEST OMAP2_DEVICE_TYPE_EMU OMAP2_DEVICE_TYPE_SEC OMAP2_DEVICE_TYPE_GP OMAP2_DEVICE_TYPE_BAD In current implementation there are two problems: Problem 1: For 34xx, the current if check will never return true. Problem 2: For 24xx the correct type check should be with omap_type() function Verified by checking the TRM 24xx for CONTROL_STATUS register bits Signed-off-by: Vikram Pandita Acked-by: Santosh Shilimkar --- arch/arm/plat-omap/sram.c | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index 226b2e8..112b807 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -93,16 +93,7 @@ extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart, */ static int is_sram_locked(void) { - int type = 0; - - if (cpu_is_omap44xx()) - /* Not yet supported */ - return 0; - - if (cpu_is_omap242x()) - type = omap_rev() & OMAP2_DEVICETYPE_MASK; - - if (type == GP_DEVICE) { + if (OMAP2_DEVICE_TYPE_GP == omap_type()) { /* RAMFW: R/W access to all initiators for all qualifier sets */ if (cpu_is_omap242x()) { __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */ -- cgit v1.1 From f47d8c694e666843653f06c257d8cfb87e376f5d Mon Sep 17 00:00:00 2001 From: Vikram Pandita Date: Thu, 16 Sep 2010 18:19:25 +0530 Subject: omap4: sram: Fix start address On OMAP4 there is no need to have SRAM_BOOTLOADER_SZ provision Hence put this macro under CONFIG_ARCH_OMAP2PLUS check Signed-off-by: Vikram Pandita Reviewed-by: Santosh Shilimkar --- arch/arm/plat-omap/sram.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index 112b807..98c86ff1 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -53,7 +53,7 @@ #define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000) #define OMAP4_SRAM_PUB_VA (OMAP4_SRAM_VA + 0x4000) -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) +#if defined(CONFIG_ARCH_OMAP2PLUS) #define SRAM_BOOTLOADER_SZ 0x00 #else #define SRAM_BOOTLOADER_SZ 0x80 -- cgit v1.1 From ed6be0bafc7781634a197ddd85b575ffcd7736b6 Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Thu, 16 Sep 2010 18:44:46 +0530 Subject: omap4: Update id.c and cpu.h for es2.0 This patch updates the id.c and cpu.h files to support omap4 ES2.0 silicon detection. Few initial omap4 es2 samples IDCODE is same as es1. So the patch uses ARM cpuid register to detect the ES version for such samples Signed-off-by: Santosh Shilimkar --- arch/arm/mach-omap2/id.c | 38 ++++++++++++++++++++++++++++------- arch/arm/plat-omap/include/plat/cpu.h | 5 ++++- 2 files changed, 35 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 9a879f9..91d7df4 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -298,7 +298,6 @@ static void __init omap4_check_revision(void) u32 idcode; u16 hawkeye; u8 rev; - char *rev_name = "ES1.0"; /* * The IC rev detection is done with hawkeye and rev. @@ -309,14 +308,39 @@ static void __init omap4_check_revision(void) hawkeye = (idcode >> 12) & 0xffff; rev = (idcode >> 28) & 0xff; - if ((hawkeye == 0xb852) && (rev == 0x0)) { - omap_revision = OMAP4430_REV_ES1_0; - omap_chip.oc |= CHIP_IS_OMAP4430ES1; - pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name); - return; + /* + * Few initial ES2.0 samples IDCODE is same as ES1.0 + * Use ARM register to detect the correct ES version + */ + if (!rev) { + idcode = read_cpuid(CPUID_ID); + rev = (idcode & 0xf) - 1; + } + + switch (hawkeye) { + case 0xb852: + switch (rev) { + case 0: + omap_revision = OMAP4430_REV_ES1_0; + omap_chip.oc |= CHIP_IS_OMAP4430ES1; + break; + case 1: + omap_revision = OMAP4430_REV_ES2_0; + omap_chip.oc |= CHIP_IS_OMAP4430ES2; + break; + default: + omap_revision = OMAP4430_REV_ES2_0; + omap_chip.oc |= CHIP_IS_OMAP4430ES2; + } + break; + default: + /* Unknown default to latest silicon rev as default*/ + omap_revision = OMAP4430_REV_ES2_0; + omap_chip.oc |= CHIP_IS_OMAP4430ES2; } - pr_err("Unknown OMAP4 CPU id\n"); + pr_info("OMAP%04x ES%d.0\n", + omap_rev() >> 16, ((omap_rev() >> 12) & 0xf) + 1); } #define OMAP3_SHOW_FEATURE(feat) \ diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h index 2e2ae53..9b38e4b 100644 --- a/arch/arm/plat-omap/include/plat/cpu.h +++ b/arch/arm/plat-omap/include/plat/cpu.h @@ -391,6 +391,7 @@ IS_OMAP_TYPE(3517, 0x3517) #define OMAP443X_CLASS 0x44300044 #define OMAP4430_REV_ES1_0 0x44300044 +#define OMAP4430_REV_ES2_0 0x44301044 /* * omap_chip bits @@ -417,10 +418,12 @@ IS_OMAP_TYPE(3517, 0x3517) #define CHIP_IS_OMAP4430ES1 (1 << 8) #define CHIP_IS_OMAP3630ES1_1 (1 << 9) #define CHIP_IS_OMAP3630ES1_2 (1 << 10) +#define CHIP_IS_OMAP4430ES2 (1 << 11) #define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430) -#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1) +#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1 | \ + CHIP_IS_OMAP4430ES2) /* * "GE" here represents "greater than or equal to" in terms of ES -- cgit v1.1 From a777b7277ef9b04481d4ceaac353bb4bd82e2f1e Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Thu, 16 Sep 2010 18:44:47 +0530 Subject: omap4: l2x0: Fix init parameter for es2.0 On ES2.0 the L2 cache init parameter ineeds to be changed to take care of cache size. The cache size is 1MB on ES2.0 vs 512KB on ES1.0 This patch fixes the init parameter to update the same using dynamic cpu version check Signed-off-by: Santosh Shilimkar --- arch/arm/mach-omap2/omap4-common.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index 13dc979..923f9f5 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -61,10 +61,14 @@ static int __init omap_l2_cache_init(void) omap_smc1(0x102, 0x1); /* - * 32KB way size, 16-way associativity, - * parity disabled + * 16-way associativity, parity disabled + * Way size - 32KB (es1.0) + * Way size - 64KB (es2.0 +) */ - l2x0_init(l2cache_base, 0x0e050000, 0xc0000fff); + if (omap_rev() == OMAP4430_REV_ES1_0) + l2x0_init(l2cache_base, 0x0e050000, 0xc0000fff); + else + l2x0_init(l2cache_base, 0x0e070000, 0xc0000fff); return 0; } -- cgit v1.1 From b5be6b66b7a33f48bf0dfb466443ae9b65e69871 Mon Sep 17 00:00:00 2001 From: David Anders Date: Thu, 16 Sep 2010 18:44:47 +0530 Subject: omap4: Panda: Add DEBUG_LL support Add support for use of DEBUG_LL for use with PandaBoard. Signed-off-by: David Anders --- arch/arm/plat-omap/include/plat/uncompress.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h index ddf723b..57dffa7 100644 --- a/arch/arm/plat-omap/include/plat/uncompress.h +++ b/arch/arm/plat-omap/include/plat/uncompress.h @@ -153,6 +153,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id) /* omap4 based boards using UART3 */ DEBUG_LL_OMAP4(3, omap_4430sdp); + DEBUG_LL_OMAP4(3, omap4_panda); /* zoom2/3 external uart */ DEBUG_LL_ZOOM(omap_zoom2); -- cgit v1.1 From e7193cc8e7b67b29483d9fd4fec04ec7b42861f0 Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Thu, 16 Sep 2010 18:44:48 +0530 Subject: omap4: Fix bootup crash observed with higher CPU clocks This patch is temporary fix to below crash. This is observed when CPU is clocked more than 600 MHz. Unhandled fault: imprecise external abort (0x1406) at 0xbf9ef65c Internal error: : 1406 [#1] PREEMPT SMP last sysfs file: Modules linked in: CPU: 0 Not tainted (2.6.36-rc3+ #18) PC is at kernel_thread_helper+0x0/0x14 LR is at kernel_thread_helper+0x0/0x14 pc : [] lr : [] psr: 00000093 sp : dc83bff8 ip : 00000000 fp : 00000000 r10: 00000000 r9 : 00000000 r8 : 00000000 r7 : 00000013 r6 : c003ce28 r5 : c008935c r4 : 00000000 r3 : 00000000 r2 : 00000000 r1 : 00000000 r0 : 00000000 Flags: nzcv IRQs off FIQs on Mode SVC_32 ISA ARM Segment kernel Control: 10c53c7f Table: 8000404a DAC: 00000017 Process swapper (pid: 2, stack limit = 0xdc83a2f0) Stack: (0xdc83bff8 to 0xdc83c000) bfe0: 00000000 ffffffff [] (kernel_thread_helper+0x0/0x14) from [] (0xfffffffe) Code: c03a0ba3 c03a5fcb c045c880 c0394035 (eb017701) ---[ end trace 1b75b31a2719ed1c ]--- The timer hwmod adaptation will eventually fix it in a proper way. Signed-off-by: Rajendra Nayak Signed-off-by: Santosh Shilimkar --- arch/arm/plat-omap/dmtimer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index 44bafda..1d706cf 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -581,7 +581,7 @@ int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) * When the functional clock disappears, too quick writes seem * to cause an abort. XXX Is this still necessary? */ - __delay(150000); + __delay(300000); return ret; } -- cgit v1.1 From db549d22c4b84824f90558eb8e6b116cf134794d Mon Sep 17 00:00:00 2001 From: Sekhar Nori Date: Mon, 28 Jun 2010 17:16:38 +0530 Subject: davinci: da850 evm: sparse cleanup: make file local variables static Without this cleanup, sparse checker reports warnings of the type: CHECK arch/arm/mach-davinci/board-da850-evm.c arch/arm/mach-davinci/board-da850-evm.c:112:22: warning: symbol 'da850_evm_nandflash_partition' was not declared. Should it be static? The nand flash partitions and regulator supplies are used within the EVM file and so should have been static This patch has been boot tested on DA830 and DA850 EVMs. Signed-off-by: Sekhar Nori Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/board-da850-evm.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index fdc2cc5..711a56a 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -110,7 +110,7 @@ static struct platform_device da850_pm_device = { * to boot, using TI's tools to install the secondary boot loader * (UBL) and U-Boot. */ -struct mtd_partition da850_evm_nandflash_partition[] = { +static struct mtd_partition da850_evm_nandflash_partition[] = { { .name = "u-boot env", .offset = 0, @@ -406,7 +406,7 @@ static int da850_lcd_hw_init(void) /* TPS65070 voltage regulator support */ /* 3.3V */ -struct regulator_consumer_supply tps65070_dcdc1_consumers[] = { +static struct regulator_consumer_supply tps65070_dcdc1_consumers[] = { { .supply = "usb0_vdda33", }, @@ -416,7 +416,7 @@ struct regulator_consumer_supply tps65070_dcdc1_consumers[] = { }; /* 3.3V or 1.8V */ -struct regulator_consumer_supply tps65070_dcdc2_consumers[] = { +static struct regulator_consumer_supply tps65070_dcdc2_consumers[] = { { .supply = "dvdd3318_a", }, @@ -429,14 +429,14 @@ struct regulator_consumer_supply tps65070_dcdc2_consumers[] = { }; /* 1.2V */ -struct regulator_consumer_supply tps65070_dcdc3_consumers[] = { +static struct regulator_consumer_supply tps65070_dcdc3_consumers[] = { { .supply = "cvdd", }, }; /* 1.8V LDO */ -struct regulator_consumer_supply tps65070_ldo1_consumers[] = { +static struct regulator_consumer_supply tps65070_ldo1_consumers[] = { { .supply = "sata_vddr", }, @@ -452,7 +452,7 @@ struct regulator_consumer_supply tps65070_ldo1_consumers[] = { }; /* 1.2V LDO */ -struct regulator_consumer_supply tps65070_ldo2_consumers[] = { +static struct regulator_consumer_supply tps65070_ldo2_consumers[] = { { .supply = "sata_vdd", }, @@ -475,7 +475,7 @@ static struct tps6507x_reg_platform_data tps6507x_platform_data = { .defdcdc_default = true, }; -struct regulator_init_data tps65070_regulator_data[] = { +static struct regulator_init_data tps65070_regulator_data[] = { /* dcdc1 */ { .constraints = { -- cgit v1.1 From c89f1681450822c74afb3217ed4c24a177a23f43 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Thu, 5 Aug 2010 10:55:16 -0700 Subject: davinci: clock: make 'disable unused clocks' printk debug only The long list of clocks being disabled on boot is noisy and not needed for standard boots. Make this a debug printk instead. Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/clock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c index 054c303..5b0cb62 100644 --- a/arch/arm/mach-davinci/clock.c +++ b/arch/arm/mach-davinci/clock.c @@ -236,7 +236,7 @@ static int __init clk_disable_unused(void) if (!davinci_psc_is_clk_active(ck->gpsc, ck->lpsc)) continue; - pr_info("Clocks: disable unused %s\n", ck->name); + pr_debug("Clocks: disable unused %s\n", ck->name); davinci_psc_config(psc_domain(ck), ck->gpsc, ck->lpsc, (ck->flags & PSC_SWRSTDISABLE) ? -- cgit v1.1 From fca97b3337edb6b12707d167460b224dd8ef6052 Mon Sep 17 00:00:00 2001 From: Sekhar Nori Date: Tue, 20 Jul 2010 16:46:48 +0530 Subject: davinci: cpufreq: bailout on regulator errors Current cpufreq code does not consider errors that can occur while changing voltage. Code to increase CPU frequency goes ahead even in the case the regulator has failed to increase the voltage. This leads to hard error since lower voltages cannot support increased frequency. Prevent this by not increasing frequency in case increasing voltage is not successful. Also, do not lower the voltage if changing the cpu frequency has failed for some reason. Note that we do not return error on failure to decrease voltage as that is not a hard error. Build fix for non-cpufreq kernels by Caglar Akyuz. Signed-off-by: Sekhar Nori Cc: Caglar Akyuz Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/cpufreq.c | 10 ++++++++-- arch/arm/mach-davinci/da850.c | 2 +- 2 files changed, 9 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-davinci/cpufreq.c b/arch/arm/mach-davinci/cpufreq.c index d3fa6de..bc80142 100644 --- a/arch/arm/mach-davinci/cpufreq.c +++ b/arch/arm/mach-davinci/cpufreq.c @@ -104,15 +104,21 @@ static int davinci_target(struct cpufreq_policy *policy, cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); /* if moving to higher frequency, up the voltage beforehand */ - if (pdata->set_voltage && freqs.new > freqs.old) - pdata->set_voltage(idx); + if (pdata->set_voltage && freqs.new > freqs.old) { + ret = pdata->set_voltage(idx); + if (ret) + goto out; + } ret = clk_set_rate(armclk, idx); + if (ret) + goto out; /* if moving to lower freq, lower the voltage after lowering freq */ if (pdata->set_voltage && freqs.new < freqs.old) pdata->set_voltage(idx); +out: cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); return ret; diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index 68ed58a..868227e 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -983,7 +983,7 @@ static int da850_set_pll0rate(struct clk *clk, unsigned long index) return 0; } #else -int __init da850_register_cpufreq(void) +int __init da850_register_cpufreq(char *async_clk) { return 0; } -- cgit v1.1 From a7884f454b75ac57e92b8c3fb3b20148f92f7688 Mon Sep 17 00:00:00 2001 From: Sekhar Nori Date: Thu, 1 Jul 2010 19:00:49 +0530 Subject: davinci: clean up inconsistent usage of spaces in Kconfig In arch/arm/mach-davinci/Kconfig, some of the configuration items are indented with multiple spaces instead of tabs. Also, in couple of places, two spaces are used in the middle of help text where one should do. This patch fixes both issues. Signed-off-by: Sekhar Nori Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/Kconfig | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 71f90f8..b291da1 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -20,17 +20,17 @@ config ARCH_DAVINCI_DM644x select ARCH_DAVINCI_DMx config ARCH_DAVINCI_DM355 - bool "DaVinci 355 based system" + bool "DaVinci 355 based system" select AINTC select ARCH_DAVINCI_DMx config ARCH_DAVINCI_DM646x - bool "DaVinci 646x based system" + bool "DaVinci 646x based system" select AINTC select ARCH_DAVINCI_DMx config ARCH_DAVINCI_DA830 - bool "DA830/OMAP-L137 based system" + bool "DA830/OMAP-L137 based system" select CP_INTC select ARCH_DAVINCI_DA8XX select CPU_DCACHE_WRITETHROUGH # needed on silicon revs 1.0, 1.1 @@ -140,7 +140,7 @@ config DA830_UI_LCD config DA830_UI_NAND bool "NAND flash" help - Say Y here to use the NAND flash. Do not forget to setup + Say Y here to use the NAND flash. Do not forget to setup the switch correctly. endchoice @@ -195,20 +195,20 @@ config DAVINCI_MUX say Y. config DAVINCI_MUX_DEBUG - bool "Multiplexing debug output" - depends on DAVINCI_MUX - help - Makes the multiplexing functions print out a lot of debug info. - This is useful if you want to find out the correct values of the - multiplexing registers. + bool "Multiplexing debug output" + depends on DAVINCI_MUX + help + Makes the multiplexing functions print out a lot of debug info. + This is useful if you want to find out the correct values of the + multiplexing registers. config DAVINCI_MUX_WARNINGS - bool "Warn about pins the bootloader didn't set up" - depends on DAVINCI_MUX - help - Choose Y here to warn whenever driver initialization logic needs - to change the pin multiplexing setup. When there are no warnings - printed, it's safe to deselect DAVINCI_MUX for your product. + bool "Warn about pins the bootloader didn't set up" + depends on DAVINCI_MUX + help + Choose Y here to warn whenever driver initialization logic needs + to change the pin multiplexing setup. When there are no warnings + printed, it's safe to deselect DAVINCI_MUX for your product. config DAVINCI_RESET_CLOCKS bool "Reset unused clocks during boot" -- cgit v1.1 From 48ea89eabee96019a4a84615af921f8703320abb Mon Sep 17 00:00:00 2001 From: Sekhar Nori Date: Thu, 1 Jul 2010 19:00:50 +0530 Subject: davinci: introduce support for AM1x ARM9 microprocessors The Sitara AM17x SoCs from TI are an OMAP-L137 pin-to-pin compatible ARM9 microprocessor offering from TI. The Sitara AM18x SoCs from TI are an OMAP-L138 pin-to-pin compatible ARM9 microprocessor offering from TI. More information about these processors available at: www.ti.com/am1x Because of their compatibiliy with OMAP-L1x, the kernel support for OMAP-L1x is fully relevant to AM1x processors. This patch updates the Kconfig prompt and help text to include the AM1x part names to help users select configurations required for these parts easily. Also, the hardware information that shows up in /proc/cpuinfo is updated to show applicability of the respective OMAP-L1x EVMs for AM1x parts. Signed-off-by: Sekhar Nori Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/Kconfig | 30 +++++++++++++++--------------- arch/arm/mach-davinci/board-da830-evm.c | 2 +- arch/arm/mach-davinci/board-da850-evm.c | 2 +- 3 files changed, 17 insertions(+), 17 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index b291da1..2bf03e9 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -30,13 +30,13 @@ config ARCH_DAVINCI_DM646x select ARCH_DAVINCI_DMx config ARCH_DAVINCI_DA830 - bool "DA830/OMAP-L137 based system" + bool "DA830/OMAP-L137/AM17x based system" select CP_INTC select ARCH_DAVINCI_DA8XX select CPU_DCACHE_WRITETHROUGH # needed on silicon revs 1.0, 1.1 config ARCH_DAVINCI_DA850 - bool "DA850/OMAP-L138 based system" + bool "DA850/OMAP-L138/AM18x based system" select CP_INTC select ARCH_DAVINCI_DA8XX select ARCH_HAS_CPUFREQ @@ -115,21 +115,21 @@ config MACH_DAVINCI_DM365_EVM for development is a DM365 EVM config MACH_DAVINCI_DA830_EVM - bool "TI DA830/OMAP-L137 Reference Platform" + bool "TI DA830/OMAP-L137/AM17x Reference Platform" default ARCH_DAVINCI_DA830 depends on ARCH_DAVINCI_DA830 select GPIO_PCF857X help - Say Y here to select the TI DA830/OMAP-L137 Evaluation Module. + Say Y here to select the TI DA830/OMAP-L137/AM17x Evaluation Module. choice - prompt "Select DA830/OMAP-L137 UI board peripheral" + prompt "Select DA830/OMAP-L137/AM17x UI board peripheral" depends on MACH_DAVINCI_DA830_EVM help - The presence of UI card on the DA830/OMAP-L137 EVM is detected - automatically based on successful probe of the I2C based GPIO - expander on that board. This option selected in this menu has - an effect only in case of a successful UI card detection. + The presence of UI card on the DA830/OMAP-L137/AM17x EVM is + detected automatically based on successful probe of the I2C + based GPIO expander on that board. This option selected in this + menu has an effect only in case of a successful UI card detection. config DA830_UI_LCD bool "LCD" @@ -145,18 +145,18 @@ config DA830_UI_NAND endchoice config MACH_DAVINCI_DA850_EVM - bool "TI DA850/OMAP-L138 Reference Platform" + bool "TI DA850/OMAP-L138/AM18x Reference Platform" default ARCH_DAVINCI_DA850 depends on ARCH_DAVINCI_DA850 select GPIO_PCA953X help - Say Y here to select the TI DA850/OMAP-L138 Evaluation Module. + Say Y here to select the TI DA850/OMAP-L138/AM18x Evaluation Module. choice prompt "Select peripherals connected to expander on UI board" depends on MACH_DAVINCI_DA850_EVM help - The presence of User Interface (UI) card on the DA850/OMAP-L138 + The presence of User Interface (UI) card on the DA850/OMAP-L138/AM18x EVM is detected automatically based on successful probe of the I2C based GPIO expander on that card. This option selected in this menu has an effect only in case of a successful UI card detection. @@ -165,13 +165,13 @@ config DA850_UI_NONE bool "No peripheral is enabled" help Say Y if you do not want to enable any of the peripherals connected - to TCA6416 expander on DA850/OMAP-L138 EVM UI card + to TCA6416 expander on DA850/OMAP-L138/AM18x EVM UI card config DA850_UI_RMII bool "RMII Ethernet PHY" help - Say Y if you want to use the RMII PHY on the DA850/OMAP-L138 EVM. - This PHY is found on the UI daughter card that is supplied with + Say Y if you want to use the RMII PHY on the DA850/OMAP-L138/AM18x + EVM. This PHY is found on the UI daughter card that is supplied with the EVM. NOTE: Please take care while choosing this option, MII PHY will not be functional if RMII mode is selected. diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c index c3994f3..292e8b7 100644 --- a/arch/arm/mach-davinci/board-da830-evm.c +++ b/arch/arm/mach-davinci/board-da830-evm.c @@ -596,7 +596,7 @@ static void __init da830_evm_map_io(void) da830_init(); } -MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137 EVM") +MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137/AM17x EVM") .phys_io = IO_PHYS, .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, .boot_params = (DA8XX_DDR_BASE + 0x100), diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index 711a56a..f5f9472 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -816,7 +816,7 @@ static void __init da850_evm_map_io(void) da850_init(); } -MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138 EVM") +MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138/AM18x EVM") .phys_io = IO_PHYS, .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, .boot_params = (DA8XX_DDR_BASE + 0x100), -- cgit v1.1 From 6ef62f8204402e32259451857c1a4a04f155b56e Mon Sep 17 00:00:00 2001 From: Sekhar Nori Date: Wed, 7 Jul 2010 14:02:49 +0530 Subject: davinci: am18x/da850/omap-l138: use 'NOM' voltage defined in datasheet as min voltage For each DA850 OPP, the normal ('NOM') voltage defined in the tecnical reference manual (TRM) is actually the minimum voltage the frequency is supported at. The minimum ('MIN') voltage defined in TRM is meant to take care of voltage fluctuations and the device should not be run at this voltage for extended periods of time. Fix the OPP definitions to define the cvdd_min as the normal voltage defined in the datasheet. Signed-off-by: Sekhar Nori Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/da850.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index 868227e..6932d80 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -851,7 +851,7 @@ static const struct da850_opp da850_opp_300 = { .prediv = 1, .mult = 25, .postdiv = 2, - .cvdd_min = 1140000, + .cvdd_min = 1200000, .cvdd_max = 1320000, }; @@ -860,7 +860,7 @@ static const struct da850_opp da850_opp_200 = { .prediv = 1, .mult = 25, .postdiv = 3, - .cvdd_min = 1050000, + .cvdd_min = 1100000, .cvdd_max = 1160000, }; @@ -869,7 +869,7 @@ static const struct da850_opp da850_opp_96 = { .prediv = 1, .mult = 20, .postdiv = 5, - .cvdd_min = 950000, + .cvdd_min = 1000000, .cvdd_max = 1050000, }; -- cgit v1.1 From 0a477f6b8c1849701981f6e00e7afcd35af75546 Mon Sep 17 00:00:00 2001 From: Sekhar Nori Date: Wed, 14 Jul 2010 17:09:45 +0530 Subject: davinci: dm365: disable pulldowns for all MMC/SD1 pins. This patch disables internal pulldowns for all MMC/SD1 pins. Presently only MMCSD1_CMD pin's pull down is disabled, but with this some MMC/SD cards do not get detected on MMC/SD1 slot of the EVM. The problem was reproducible with SanDisk 4GB SDHC card. Reported-by: Stephane Bovagne Signed-off-by: Sekhar Nori Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/devices.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c index 8b7201e..2a9a2523 100644 --- a/arch/arm/mach-davinci/devices.c +++ b/arch/arm/mach-davinci/devices.c @@ -213,7 +213,7 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config) IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE + 0x7c); /* Configure pull down control */ - __raw_writel((__raw_readl(pupdctl1) & ~0x400), + __raw_writel((__raw_readl(pupdctl1) & ~0xfc0), pupdctl1); mmcsd1_resources[0].start = DM365_MMCSD1_BASE; -- cgit v1.1 From b39639b820ca64e55c39b5217773919ca7973cec Mon Sep 17 00:00:00 2001 From: Sekhar Nori Date: Tue, 20 Jul 2010 16:46:49 +0530 Subject: davinci: clock: add support for setting sysclk rate Setting sysclk rate will be useful in cases where the sysclk is not at a fixed ratio to the PLL output but can asynchronously be changed. This support forms the basis of attempt to keep the AEMIF clock constant on OMAP-L138 even as PLL0 output changes as ARM clock is changed to save power. This patch has been tested on OMAP-L138. Signed-off-by: Sekhar Nori Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/clock.c | 73 +++++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-davinci/clock.h | 5 +++ 2 files changed, 78 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c index 5b0cb62..01ba080 100644 --- a/arch/arm/mach-davinci/clock.c +++ b/arch/arm/mach-davinci/clock.c @@ -287,6 +287,79 @@ static unsigned long clk_sysclk_recalc(struct clk *clk) return rate; } +int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate) +{ + unsigned v; + struct pll_data *pll; + unsigned long input; + unsigned ratio = 0; + + /* If this is the PLL base clock, wrong function to call */ + if (clk->pll_data) + return -EINVAL; + + /* There must be a parent... */ + if (WARN_ON(!clk->parent)) + return -EINVAL; + + /* ... the parent must be a PLL... */ + if (WARN_ON(!clk->parent->pll_data)) + return -EINVAL; + + /* ... and this clock must have a divider. */ + if (WARN_ON(!clk->div_reg)) + return -EINVAL; + + pll = clk->parent->pll_data; + + input = clk->parent->rate; + + /* If pre-PLL, source clock is before the multiplier and divider(s) */ + if (clk->flags & PRE_PLL) + input = pll->input_rate; + + if (input > rate) { + /* + * Can afford to provide an output little higher than requested + * only if maximum rate supported by hardware on this sysclk + * is known. + */ + if (clk->maxrate) { + ratio = DIV_ROUND_CLOSEST(input, rate); + if (input / ratio > clk->maxrate) + ratio = 0; + } + + if (ratio == 0) + ratio = DIV_ROUND_UP(input, rate); + + ratio--; + } + + if (ratio > PLLDIV_RATIO_MASK) + return -EINVAL; + + do { + v = __raw_readl(pll->base + PLLSTAT); + } while (v & PLLSTAT_GOSTAT); + + v = __raw_readl(pll->base + clk->div_reg); + v &= ~PLLDIV_RATIO_MASK; + v |= ratio | PLLDIV_EN; + __raw_writel(v, pll->base + clk->div_reg); + + v = __raw_readl(pll->base + PLLCMD); + v |= PLLCMD_GOSET; + __raw_writel(v, pll->base + PLLCMD); + + do { + v = __raw_readl(pll->base + PLLSTAT); + } while (v & PLLSTAT_GOSTAT); + + return 0; +} +EXPORT_SYMBOL(davinci_set_sysclk_rate); + static unsigned long clk_leafclk_recalc(struct clk *clk) { if (WARN_ON(!clk->parent)) diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h index 01e3648..1109998 100644 --- a/arch/arm/mach-davinci/clock.h +++ b/arch/arm/mach-davinci/clock.h @@ -70,6 +70,9 @@ #include #include +#define PLLSTAT_GOSTAT BIT(0) +#define PLLCMD_GOSET BIT(0) + struct pll_data { u32 phys_base; void __iomem *base; @@ -86,6 +89,7 @@ struct clk { struct module *owner; const char *name; unsigned long rate; + unsigned long maxrate; /* H/W supported max rate */ u8 usecount; u8 lpsc; u8 gpsc; @@ -118,6 +122,7 @@ struct clk { int davinci_clk_init(struct clk_lookup *clocks); int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv, unsigned int mult, unsigned int postdiv); +int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate); extern struct platform_device davinci_wdt_device; extern void davinci_watchdog_reset(struct platform_device *); -- cgit v1.1 From 30a2c5d2f0134df6175af26ce554aacaee304280 Mon Sep 17 00:00:00 2001 From: Sekhar Nori Date: Tue, 20 Jul 2010 16:46:50 +0530 Subject: davinci: cpufreq: add support for keeping an additional clock constant On OMAP-L138 SoC, some of the sysclks need not be at a fixed ratio to CPU clock and can be kept at a relatively constant rate by adjusting the PLLDIVn ratio even as cpufreq goes ahead and changes the CPU clock. This feature can be used to keep the EMIFA (PLL0 SYSCLK3) clock at a constant rate so that the EMIF timings need not be re-programmed whenever the CPU frequency changes. This patch adds the required suppport to cpufreq driver. Signed-off-by: Sekhar Nori Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/cpufreq.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-davinci/cpufreq.c b/arch/arm/mach-davinci/cpufreq.c index bc80142..343de73 100644 --- a/arch/arm/mach-davinci/cpufreq.c +++ b/arch/arm/mach-davinci/cpufreq.c @@ -34,6 +34,8 @@ struct davinci_cpufreq { struct device *dev; struct clk *armclk; + struct clk *asyncclk; + unsigned long asyncrate; }; static struct davinci_cpufreq cpufreq; @@ -114,6 +116,12 @@ static int davinci_target(struct cpufreq_policy *policy, if (ret) goto out; + if (cpufreq.asyncclk) { + ret = clk_set_rate(cpufreq.asyncclk, cpufreq.asyncrate); + if (ret) + goto out; + } + /* if moving to lower freq, lower the voltage after lowering freq */ if (pdata->set_voltage && freqs.new < freqs.old) pdata->set_voltage(idx); @@ -191,6 +199,7 @@ static struct cpufreq_driver davinci_driver = { static int __init davinci_cpufreq_probe(struct platform_device *pdev) { struct davinci_cpufreq_config *pdata = pdev->dev.platform_data; + struct clk *asyncclk; if (!pdata) return -EINVAL; @@ -205,6 +214,12 @@ static int __init davinci_cpufreq_probe(struct platform_device *pdev) return PTR_ERR(cpufreq.armclk); } + asyncclk = clk_get(cpufreq.dev, "async"); + if (!IS_ERR(asyncclk)) { + cpufreq.asyncclk = asyncclk; + cpufreq.asyncrate = clk_get_rate(asyncclk); + } + return cpufreq_register_driver(&davinci_driver); } @@ -212,6 +227,9 @@ static int __exit davinci_cpufreq_remove(struct platform_device *pdev) { clk_put(cpufreq.armclk); + if (cpufreq.asyncclk) + clk_put(cpufreq.asyncclk); + return cpufreq_unregister_driver(&davinci_driver); } -- cgit v1.1 From b987c4b2c9c9db2393f4c089e63d1734301214e5 Mon Sep 17 00:00:00 2001 From: Sekhar Nori Date: Tue, 20 Jul 2010 16:46:51 +0530 Subject: davinci: am18x/da850/omap-l138: keep async clock constant with cpufreq Keep PLL0 SYSCLK3 at a constant rate of 100MHz. This enables the AEMIF timing to remain valid even as the PLL0 output is changed by cpufreq driver to save power. Signed-off-by: Sekhar Nori Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/board-da850-evm.c | 2 +- arch/arm/mach-davinci/da850.c | 10 +++++++++- arch/arm/mach-davinci/include/mach/da8xx.h | 2 +- 3 files changed, 11 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index f5f9472..c2800a9 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -787,7 +787,7 @@ static __init void da850_evm_init(void) if (ret) pr_warning("da850_evm_init: rtc setup failed: %d\n", ret); - ret = da850_register_cpufreq(); + ret = da850_register_cpufreq("pll0_sysclk3"); if (ret) pr_warning("da850_evm_init: cpufreq registration failed: %d\n", ret); diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index 6932d80..5af7cfb 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -86,6 +86,8 @@ static struct clk pll0_sysclk3 = { .parent = &pll0_clk, .flags = CLK_PLL, .div_reg = PLLDIV3, + .set_rate = davinci_set_sysclk_rate, + .maxrate = 100000000, }; static struct clk pll0_sysclk4 = { @@ -929,10 +931,16 @@ static struct platform_device da850_cpufreq_device = { .dev = { .platform_data = &cpufreq_info, }, + .id = -1, }; -int __init da850_register_cpufreq(void) +int __init da850_register_cpufreq(char *async_clk) { + /* cpufreq driver can help keep an "async" clock constant */ + if (async_clk) + clk_add_alias("async", da850_cpufreq_device.name, + async_clk, NULL); + return platform_device_register(&da850_cpufreq_device); } diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h index 3c07059..2c3f418 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx.h +++ b/arch/arm/mach-davinci/include/mach/da8xx.h @@ -78,7 +78,7 @@ int da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata); int da8xx_register_mmcsd0(struct davinci_mmc_config *config); void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata); int da8xx_register_rtc(void); -int da850_register_cpufreq(void); +int da850_register_cpufreq(char *async_clk); int da8xx_register_cpuidle(void); void __iomem * __init da8xx_get_mem_ctlr(void); int da850_register_pm(struct platform_device *pdev); -- cgit v1.1 From 7173d5493799944d47317d9490365a89ee079f2a Mon Sep 17 00:00:00 2001 From: Cyril Chemparathy Date: Tue, 3 Aug 2010 21:04:16 -0400 Subject: Davinci: tnetv107x: retain psc reg base after init This is a bugfix for the original tnetv107x submission series. The psc_regs base array was being discarded post-init, and this was causing a crash during post-init clock enable/disable. Signed-off-by: Cyril Chemparathy Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/tnetv107x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-davinci/tnetv107x.c b/arch/arm/mach-davinci/tnetv107x.c index 864e604..06d2ac9 100644 --- a/arch/arm/mach-davinci/tnetv107x.c +++ b/arch/arm/mach-davinci/tnetv107x.c @@ -104,7 +104,7 @@ static u32 pll_ext_freq[] = { }; /* PSC control registers */ -static u32 psc_regs[] __initconst = { TNETV107X_PSC_BASE }; +static u32 psc_regs[] = { TNETV107X_PSC_BASE }; /* Host map for interrupt controller */ static u32 intc_host_map[] = { 0x01010000, 0x01010101, -1 }; -- cgit v1.1 From f48ecc2f73763e9d94d5847692ed25ab0f4fb73c Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sun, 1 Aug 2010 21:15:16 +0400 Subject: DA850: move NAND/NOR pin lists to the board file The NAND/NOR flash pin lists (da850_nand_pins/da850_nor_pins) are purely board specific and as such shouldn't be in da850.c -- copy them to board-da850-evm.c, renaming to da850_evm_nand_pins/da850_evm_nor_pins respectively, and merge the two lists in da850.c into one, representing the EMIF 2.5 module as a whole, just like we have it in da830.c... While at it, remove the '__init' modifier from da850_evm_setup_nor_nand() as this function is called from non '__init' code... Signed-off-by: Sergei Shtylyov Tested-by: Ben Gardiner Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/board-da850-evm.c | 30 +++++++++++++++++++++++++--- arch/arm/mach-davinci/da850.c | 32 +++++++++++------------------- arch/arm/mach-davinci/include/mach/da8xx.h | 3 +-- 3 files changed, 40 insertions(+), 25 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index c2800a9..482d458 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -196,6 +196,30 @@ static void __init da850_evm_init_nor(void) iounmap(aemif_addr); } +static const short da850_evm_nand_pins[] = { + DA850_EMA_D_0, DA850_EMA_D_1, DA850_EMA_D_2, DA850_EMA_D_3, + DA850_EMA_D_4, DA850_EMA_D_5, DA850_EMA_D_6, DA850_EMA_D_7, + DA850_EMA_A_1, DA850_EMA_A_2, DA850_NEMA_CS_3, DA850_NEMA_CS_4, + DA850_NEMA_WE, DA850_NEMA_OE, + -1 +}; + +static const short da850_evm_nor_pins[] = { + DA850_EMA_BA_1, DA850_EMA_CLK, DA850_EMA_WAIT_1, DA850_NEMA_CS_2, + DA850_NEMA_WE, DA850_NEMA_OE, DA850_EMA_D_0, DA850_EMA_D_1, + DA850_EMA_D_2, DA850_EMA_D_3, DA850_EMA_D_4, DA850_EMA_D_5, + DA850_EMA_D_6, DA850_EMA_D_7, DA850_EMA_D_8, DA850_EMA_D_9, + DA850_EMA_D_10, DA850_EMA_D_11, DA850_EMA_D_12, DA850_EMA_D_13, + DA850_EMA_D_14, DA850_EMA_D_15, DA850_EMA_A_0, DA850_EMA_A_1, + DA850_EMA_A_2, DA850_EMA_A_3, DA850_EMA_A_4, DA850_EMA_A_5, + DA850_EMA_A_6, DA850_EMA_A_7, DA850_EMA_A_8, DA850_EMA_A_9, + DA850_EMA_A_10, DA850_EMA_A_11, DA850_EMA_A_12, DA850_EMA_A_13, + DA850_EMA_A_14, DA850_EMA_A_15, DA850_EMA_A_16, DA850_EMA_A_17, + DA850_EMA_A_18, DA850_EMA_A_19, DA850_EMA_A_20, DA850_EMA_A_21, + DA850_EMA_A_22, DA850_EMA_A_23, + -1 +}; + static u32 ui_card_detected; #if defined(CONFIG_MMC_DAVINCI) || \ @@ -205,17 +229,17 @@ static u32 ui_card_detected; #define HAS_MMC 0 #endif -static __init void da850_evm_setup_nor_nand(void) +static inline void da850_evm_setup_nor_nand(void) { int ret = 0; if (ui_card_detected & !HAS_MMC) { - ret = davinci_cfg_reg_list(da850_nand_pins); + ret = davinci_cfg_reg_list(da850_evm_nand_pins); if (ret) pr_warning("da850_evm_init: nand mux setup failed: " "%d\n", ret); - ret = davinci_cfg_reg_list(da850_nor_pins); + ret = davinci_cfg_reg_list(da850_evm_nor_pins); if (ret) pr_warning("da850_evm_init: nor mux setup failed: %d\n", ret); diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index 5af7cfb..efb904e 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -609,27 +609,19 @@ const short da850_mmcsd0_pins[] __initdata = { -1 }; -const short da850_nand_pins[] __initdata = { - DA850_EMA_D_7, DA850_EMA_D_6, DA850_EMA_D_5, DA850_EMA_D_4, - DA850_EMA_D_3, DA850_EMA_D_2, DA850_EMA_D_1, DA850_EMA_D_0, - DA850_EMA_A_1, DA850_EMA_A_2, DA850_NEMA_CS_3, DA850_NEMA_CS_4, - DA850_NEMA_WE, DA850_NEMA_OE, - -1 -}; - -const short da850_nor_pins[] __initdata = { +const short da850_emif25_pins[] __initdata = { DA850_EMA_BA_1, DA850_EMA_CLK, DA850_EMA_WAIT_1, DA850_NEMA_CS_2, - DA850_NEMA_WE, DA850_NEMA_OE, DA850_EMA_D_0, DA850_EMA_D_1, - DA850_EMA_D_2, DA850_EMA_D_3, DA850_EMA_D_4, DA850_EMA_D_5, - DA850_EMA_D_6, DA850_EMA_D_7, DA850_EMA_D_8, DA850_EMA_D_9, - DA850_EMA_D_10, DA850_EMA_D_11, DA850_EMA_D_12, DA850_EMA_D_13, - DA850_EMA_D_14, DA850_EMA_D_15, DA850_EMA_A_0, DA850_EMA_A_1, - DA850_EMA_A_2, DA850_EMA_A_3, DA850_EMA_A_4, DA850_EMA_A_5, - DA850_EMA_A_6, DA850_EMA_A_7, DA850_EMA_A_8, DA850_EMA_A_9, - DA850_EMA_A_10, DA850_EMA_A_11, DA850_EMA_A_12, DA850_EMA_A_13, - DA850_EMA_A_14, DA850_EMA_A_15, DA850_EMA_A_16, DA850_EMA_A_17, - DA850_EMA_A_18, DA850_EMA_A_19, DA850_EMA_A_20, DA850_EMA_A_21, - DA850_EMA_A_22, DA850_EMA_A_23, + DA850_NEMA_CS_3, DA850_NEMA_CS_4, DA850_NEMA_WE, DA850_NEMA_OE, + DA850_EMA_D_0, DA850_EMA_D_1, DA850_EMA_D_2, DA850_EMA_D_3, + DA850_EMA_D_4, DA850_EMA_D_5, DA850_EMA_D_6, DA850_EMA_D_7, + DA850_EMA_D_8, DA850_EMA_D_9, DA850_EMA_D_10, DA850_EMA_D_11, + DA850_EMA_D_12, DA850_EMA_D_13, DA850_EMA_D_14, DA850_EMA_D_15, + DA850_EMA_A_0, DA850_EMA_A_1, DA850_EMA_A_2, DA850_EMA_A_3, + DA850_EMA_A_4, DA850_EMA_A_5, DA850_EMA_A_6, DA850_EMA_A_7, + DA850_EMA_A_8, DA850_EMA_A_9, DA850_EMA_A_10, DA850_EMA_A_11, + DA850_EMA_A_12, DA850_EMA_A_13, DA850_EMA_A_14, DA850_EMA_A_15, + DA850_EMA_A_16, DA850_EMA_A_17, DA850_EMA_A_18, DA850_EMA_A_19, + DA850_EMA_A_20, DA850_EMA_A_21, DA850_EMA_A_22, DA850_EMA_A_23, -1 }; diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h index 2c3f418..8de2dbb 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx.h +++ b/arch/arm/mach-davinci/include/mach/da8xx.h @@ -125,7 +125,6 @@ extern const short da850_rmii_pins[]; extern const short da850_mcasp_pins[]; extern const short da850_lcdcntl_pins[]; extern const short da850_mmcsd0_pins[]; -extern const short da850_nand_pins[]; -extern const short da850_nor_pins[]; +extern const short da850_emif25_pins[]; #endif /* __ASM_ARCH_DAVINCI_DA8XX_H */ -- cgit v1.1 From 85b8307fd03badbff0da5a75776c62cb45ee6551 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sun, 1 Aug 2010 21:17:00 +0400 Subject: DA850: move MII/RMII pin lists to the board file The CPGMAC pin list in da850.c was incorrectly split into two MII/RMII mode specific pin lists, while what pin group is used is a function of how the board is wired. Copy the pin lists to board-da850-evm.c, renaming them accordingly, and merge the two lists in da850.c into one, da850_cpgmac_pins[], representing the CPGMAC module as a whole... Signed-off-by: Sergei Shtylyov Tested-by: Ben Gardiner Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/board-da850-evm.c | 21 +++++++++++++++++++-- arch/arm/mach-davinci/da850.c | 12 +++--------- arch/arm/mach-davinci/include/mach/da8xx.h | 1 - 3 files changed, 22 insertions(+), 12 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index 482d458..190ebd3 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -600,6 +600,23 @@ static const short da850_evm_lcdc_pins[] = { -1 }; +static const short da850_evm_mii_pins[] = { + DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3, + DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER, + DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3, + DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK, + DA850_MDIO_D, + -1 +}; + +static const short da850_evm_rmii_pins[] = { + DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN, + DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1, + DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK, + DA850_MDIO_D, + -1 +}; + static int __init da850_evm_config_emac(void) { void __iomem *cfg_chip3_base; @@ -617,12 +634,12 @@ static int __init da850_evm_config_emac(void) if (rmii_en) { val |= BIT(8); - ret = davinci_cfg_reg_list(da850_rmii_pins); + ret = davinci_cfg_reg_list(da850_evm_rmii_pins); pr_info("EMAC: RMII PHY configured, MII PHY will not be" " functional\n"); } else { val &= ~BIT(8); - ret = davinci_cfg_reg_list(da850_cpgmac_pins); + ret = davinci_cfg_reg_list(da850_evm_mii_pins); pr_info("EMAC: MII PHY configured, RMII PHY will not be" " functional\n"); } diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index efb904e..c2a3ce5 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -574,15 +574,9 @@ const short da850_cpgmac_pins[] __initdata = { DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER, DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3, DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK, - DA850_MDIO_D, - -1 -}; - -const short da850_rmii_pins[] __initdata = { - DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN, - DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1, - DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK, - DA850_MDIO_D, + DA850_MDIO_D, DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN, + DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1, DA850_RMII_RXER, + DA850_RMII_MHZ_50_CLK, -1 }; diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h index 8de2dbb..504f2f6 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx.h +++ b/arch/arm/mach-davinci/include/mach/da8xx.h @@ -121,7 +121,6 @@ extern const short da850_uart2_pins[]; extern const short da850_i2c0_pins[]; extern const short da850_i2c1_pins[]; extern const short da850_cpgmac_pins[]; -extern const short da850_rmii_pins[]; extern const short da850_mcasp_pins[]; extern const short da850_lcdcntl_pins[]; extern const short da850_mmcsd0_pins[]; -- cgit v1.1 From 93fe23d8a9d95d8a85dfe2cb37cd9f220bef11b8 Mon Sep 17 00:00:00 2001 From: Kulikov Vasiliy Date: Sat, 17 Jul 2010 19:19:07 +0400 Subject: arm: mach-davinci: check irq2ctlr() result If irq2ctlr() fails return IRQ_NONE. Also as it can fail make 'ctlr' signed. The semantic patch that finds this problem (many false-positive results): (http://coccinelle.lip6.fr/) // @ r1 @ identifier f; @@ int f(...) { ... } @@ identifier r1.f; type T; unsigned T x; @@ *x = f(...) ... *x > 0 Signed-off-by: Kulikov Vasiliy Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/dma.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c index 2ede598..6b96698 100644 --- a/arch/arm/mach-davinci/dma.c +++ b/arch/arm/mach-davinci/dma.c @@ -354,10 +354,12 @@ static int irq2ctlr(int irq) static irqreturn_t dma_irq_handler(int irq, void *data) { int i; - unsigned ctlr; + int ctlr; unsigned int cnt = 0; ctlr = irq2ctlr(irq); + if (ctlr < 0) + return IRQ_NONE; dev_dbg(data, "dma_irq_handler\n"); @@ -408,10 +410,12 @@ static irqreturn_t dma_irq_handler(int irq, void *data) static irqreturn_t dma_ccerr_handler(int irq, void *data) { int i; - unsigned ctlr; + int ctlr; unsigned int cnt = 0; ctlr = irq2ctlr(irq); + if (ctlr < 0) + return IRQ_NONE; dev_dbg(data, "dma_ccerr_handler\n"); -- cgit v1.1 From d2b8622c9122841db9c0a09a02d92823d924a1a5 Mon Sep 17 00:00:00 2001 From: Juha Kuikka Date: Thu, 26 Aug 2010 12:40:45 -0700 Subject: DA850: Add LPSC id for MMCSD1 peripheral Add LPSC id for DA850's MMCSD1 peripheral. Signed-off-by: Juha Kuikka Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/include/mach/psc.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h index 983da6e..62b0858 100644 --- a/arch/arm/mach-davinci/include/mach/psc.h +++ b/arch/arm/mach-davinci/include/mach/psc.h @@ -172,6 +172,7 @@ #define DA8XX_LPSC1_UART2 13 #define DA8XX_LPSC1_LCDC 16 #define DA8XX_LPSC1_PWM 17 +#define DA850_LPSC1_MMC_SD1 18 #define DA8XX_LPSC1_ECAP 20 #define DA830_LPSC1_EQEP 21 #define DA850_LPSC1_TPTC2 21 -- cgit v1.1 From 051a6687336d3310abc85991db7a8917ecc603fc Mon Sep 17 00:00:00 2001 From: Juha Kuikka Date: Thu, 26 Aug 2010 12:40:46 -0700 Subject: DA850: Split MMCSD clock into two to support both MMCSD peripherals Split mmcsd_clk into mmcsd0_clk and mmcsd1_clk and add davinci_mmc.1 in preparation for adding support for MMCSD1 peripheral in DA850. Signed-off-by: Juha Kuikka Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/da850.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index c2a3ce5..63916b9 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -325,12 +325,19 @@ static struct clk lcdc_clk = { .gpsc = 1, }; -static struct clk mmcsd_clk = { - .name = "mmcsd", +static struct clk mmcsd0_clk = { + .name = "mmcsd0", .parent = &pll0_sysclk2, .lpsc = DA8XX_LPSC0_MMC_SD, }; +static struct clk mmcsd1_clk = { + .name = "mmcsd1", + .parent = &pll0_sysclk2, + .lpsc = DA850_LPSC1_MMC_SD1, + .gpsc = 1, +}; + static struct clk aemif_clk = { .name = "aemif", .parent = &pll0_sysclk3, @@ -377,7 +384,8 @@ static struct clk_lookup da850_clks[] = { CLK("davinci_emac.1", NULL, &emac_clk), CLK("davinci-mcasp.0", NULL, &mcasp_clk), CLK("da8xx_lcdc.0", NULL, &lcdc_clk), - CLK("davinci_mmc.0", NULL, &mmcsd_clk), + CLK("davinci_mmc.0", NULL, &mmcsd0_clk), + CLK("davinci_mmc.1", NULL, &mmcsd1_clk), CLK(NULL, "aemif", &aemif_clk), CLK(NULL, NULL, NULL), }; -- cgit v1.1 From b8241aef7eb54c6e5126b3aa309c2cf0f343c52d Mon Sep 17 00:00:00 2001 From: Juha Kuikka Date: Thu, 26 Aug 2010 12:40:47 -0700 Subject: DA850: Add MMCSD1 resources, platform device and convenience registration function Add resources, platform device and convenience registration function for DA850's second MMC/SD controller (MMCSD1). Signed-off-by: Juha Kuikka Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/devices-da8xx.c | 39 ++++++++++++++++++++++++++++++ arch/arm/mach-davinci/include/mach/da8xx.h | 1 + 2 files changed, 40 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c index 52bc7b1..caeb7f4 100644 --- a/arch/arm/mach-davinci/devices-da8xx.c +++ b/arch/arm/mach-davinci/devices-da8xx.c @@ -24,6 +24,7 @@ #include "clock.h" #define DA8XX_TPCC_BASE 0x01c00000 +#define DA850_MMCSD1_BASE 0x01e1b000 #define DA850_TPCC1_BASE 0x01e30000 #define DA8XX_TPTC0_BASE 0x01c08000 #define DA8XX_TPTC1_BASE 0x01c08400 @@ -566,6 +567,44 @@ int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config) return platform_device_register(&da8xx_mmcsd0_device); } +#ifdef CONFIG_ARCH_DAVINCI_DA850 +static struct resource da850_mmcsd1_resources[] = { + { /* registers */ + .start = DA850_MMCSD1_BASE, + .end = DA850_MMCSD1_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { /* interrupt */ + .start = IRQ_DA850_MMCSDINT0_1, + .end = IRQ_DA850_MMCSDINT0_1, + .flags = IORESOURCE_IRQ, + }, + { /* DMA RX */ + .start = EDMA_CTLR_CHAN(1, 28), + .end = EDMA_CTLR_CHAN(1, 28), + .flags = IORESOURCE_DMA, + }, + { /* DMA TX */ + .start = EDMA_CTLR_CHAN(1, 29), + .end = EDMA_CTLR_CHAN(1, 29), + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device da850_mmcsd1_device = { + .name = "davinci_mmc", + .id = 1, + .num_resources = ARRAY_SIZE(da850_mmcsd1_resources), + .resource = da850_mmcsd1_resources, +}; + +int __init da850_register_mmcsd1(struct davinci_mmc_config *config) +{ + da850_mmcsd1_device.dev.platform_data = config; + return platform_device_register(&da850_mmcsd1_device); +} +#endif + static struct resource da8xx_rtc_resources[] = { { .start = DA8XX_RTC_BASE, diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h index 504f2f6..4247b3f 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx.h +++ b/arch/arm/mach-davinci/include/mach/da8xx.h @@ -76,6 +76,7 @@ int da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata); int da8xx_register_emac(void); int da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata); int da8xx_register_mmcsd0(struct davinci_mmc_config *config); +int da850_register_mmcsd1(struct davinci_mmc_config *config); void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata); int da8xx_register_rtc(void); int da850_register_cpufreq(char *async_clk); -- cgit v1.1 From 13d36a923da6a1e0584e07d91320373c790c01c3 Mon Sep 17 00:00:00 2001 From: Sekhar Nori Date: Fri, 27 Aug 2010 14:14:03 +0530 Subject: davinci: dm365 evm: use EDMAQ_3 as the audio DMA queue By default the audio driver uses EDMAQ_0 as the DMA queue, but on DM365 this queue is specially designed for video transfers with a large fifo size. Having both audio and video transfers on the same queue leads to noise on the audio side. This patch changes the audio queue number for DM365 to EDMAQ_3. Signed-off-by: Sekhar Nori Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/board-dm365-evm.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c index 84acef1..bdea2da 100644 --- a/arch/arm/mach-davinci/board-dm365-evm.c +++ b/arch/arm/mach-davinci/board-dm365-evm.c @@ -175,7 +175,9 @@ static struct at24_platform_data eeprom_info = { .context = (void *)0x7f00, }; -static struct snd_platform_data dm365_evm_snd_data; +static struct snd_platform_data dm365_evm_snd_data = { + .asp_chan_q = EVENTQ_3, +}; static struct i2c_board_info i2c_info[] = { { -- cgit v1.1 From 8060ef4da9e73f461adf2ba1922ea5400a61cf98 Mon Sep 17 00:00:00 2001 From: Sekhar Nori Date: Mon, 9 Aug 2010 15:46:35 +0530 Subject: davinci: add support for aemif timing configuration This patch adds support to configure the AEMIF interface with supplied timing values. Since this capability is useful both from NOR and NAND flashes, it is provided as a new interface and in a file of its own. AEMIF timing configuration is required in cases: 1) Where the AEMIF clock rate can change at runtime (a side affect of cpu frequency change). 2) Where U-Boot does not support NAND/NOR but supports other media like SPI Flash or MMC/SD and thus does not care about setting up the AEMIF timing for kernel to use. 3) Where U-Boot just hasn't configured the timing values and cannot be upgraded because the box is already in the field. Since there is now a header file for AEMIF interface, the common (non-NAND specific) defines for AEMIF registers have been moved from nand.h into the newly created aemif.h Signed-off-by: Sekhar Nori Acked-by: Kevin Hilman Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/Makefile | 2 +- arch/arm/mach-davinci/aemif.c | 133 +++++++++++++++++++++++++++++ arch/arm/mach-davinci/include/mach/aemif.h | 36 ++++++++ arch/arm/mach-davinci/include/mach/nand.h | 3 - 4 files changed, 170 insertions(+), 4 deletions(-) create mode 100644 arch/arm/mach-davinci/aemif.c create mode 100644 arch/arm/mach-davinci/include/mach/aemif.h (limited to 'arch') diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index eab4c0f..77a0f71 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -5,7 +5,7 @@ # Common objects obj-y := time.o clock.o serial.o io.o psc.o \ - gpio.o dma.o usb.o common.o sram.o + gpio.o dma.o usb.o common.o sram.o aemif.o obj-$(CONFIG_DAVINCI_MUX) += mux.o diff --git a/arch/arm/mach-davinci/aemif.c b/arch/arm/mach-davinci/aemif.c new file mode 100644 index 0000000..9c3f500 --- /dev/null +++ b/arch/arm/mach-davinci/aemif.c @@ -0,0 +1,133 @@ +/* + * AEMIF support for DaVinci SoCs + * + * Copyright (C) 2010 Texas Instruments Incorporated. http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include + +#include + +/* Timing value configuration */ + +#define TA(x) ((x) << 2) +#define RHOLD(x) ((x) << 4) +#define RSTROBE(x) ((x) << 7) +#define RSETUP(x) ((x) << 13) +#define WHOLD(x) ((x) << 17) +#define WSTROBE(x) ((x) << 20) +#define WSETUP(x) ((x) << 26) + +#define TA_MAX 0x3 +#define RHOLD_MAX 0x7 +#define RSTROBE_MAX 0x3f +#define RSETUP_MAX 0xf +#define WHOLD_MAX 0x7 +#define WSTROBE_MAX 0x3f +#define WSETUP_MAX 0xf + +#define TIMING_MASK (TA(TA_MAX) | \ + RHOLD(RHOLD_MAX) | \ + RSTROBE(RSTROBE_MAX) | \ + RSETUP(RSETUP_MAX) | \ + WHOLD(WHOLD_MAX) | \ + WSTROBE(WSTROBE_MAX) | \ + WSETUP(WSETUP_MAX)) + +/* + * aemif_calc_rate - calculate timing data. + * @wanted: The cycle time needed in nanoseconds. + * @clk: The input clock rate in kHz. + * @max: The maximum divider value that can be programmed. + * + * On success, returns the calculated timing value minus 1 for easy + * programming into AEMIF timing registers, else negative errno. + */ +static int aemif_calc_rate(int wanted, unsigned long clk, int max) +{ + int result; + + result = DIV_ROUND_UP((wanted * clk), NSEC_PER_MSEC) - 1; + + pr_debug("%s: result %d from %ld, %d\n", __func__, result, clk, wanted); + + /* It is generally OK to have a more relaxed timing than requested... */ + if (result < 0) + result = 0; + + /* ... But configuring tighter timings is not an option. */ + else if (result > max) + result = -EINVAL; + + return result; +} + +/** + * davinci_aemif_setup_timing - setup timing values for a given AEMIF interface + * @t: timing values to be progammed + * @base: The virtual base address of the AEMIF interface + * @cs: chip-select to program the timing values for + * + * This function programs the given timing values (in real clock) into the + * AEMIF registers taking the AEMIF clock into account. + * + * This function does not use any locking while programming the AEMIF + * because it is expected that there is only one user of a given + * chip-select. + * + * Returns 0 on success, else negative errno. + */ +int davinci_aemif_setup_timing(struct davinci_aemif_timing *t, + void __iomem *base, unsigned cs) +{ + unsigned set, val; + unsigned ta, rhold, rstrobe, rsetup, whold, wstrobe, wsetup; + unsigned offset = A1CR_OFFSET + cs * 4; + struct clk *aemif_clk; + unsigned long clkrate; + + if (!t) + return 0; /* Nothing to do */ + + aemif_clk = clk_get(NULL, "aemif"); + if (IS_ERR(aemif_clk)) + return PTR_ERR(aemif_clk); + + clkrate = clk_get_rate(aemif_clk); + + clkrate /= 1000; /* turn clock into kHz for ease of use */ + + ta = aemif_calc_rate(t->ta, clkrate, TA_MAX); + rhold = aemif_calc_rate(t->rhold, clkrate, RHOLD_MAX); + rstrobe = aemif_calc_rate(t->rstrobe, clkrate, RSTROBE_MAX); + rsetup = aemif_calc_rate(t->rsetup, clkrate, RSETUP_MAX); + whold = aemif_calc_rate(t->whold, clkrate, WHOLD_MAX); + wstrobe = aemif_calc_rate(t->wstrobe, clkrate, WSTROBE_MAX); + wsetup = aemif_calc_rate(t->wsetup, clkrate, WSETUP_MAX); + + if (ta < 0 || rhold < 0 || rstrobe < 0 || rsetup < 0 || + whold < 0 || wstrobe < 0 || wsetup < 0) { + pr_err("%s: cannot get suitable timings\n", __func__); + return -EINVAL; + } + + set = TA(ta) | RHOLD(rhold) | RSTROBE(rstrobe) | RSETUP(rsetup) | + WHOLD(whold) | WSTROBE(wstrobe) | WSETUP(wsetup); + + val = __raw_readl(base + offset); + val &= ~TIMING_MASK; + val |= set; + __raw_writel(val, base + offset); + + return 0; +} +EXPORT_SYMBOL(davinci_aemif_setup_timing); diff --git a/arch/arm/mach-davinci/include/mach/aemif.h b/arch/arm/mach-davinci/include/mach/aemif.h new file mode 100644 index 0000000..05b2934 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/aemif.h @@ -0,0 +1,36 @@ +/* + * TI DaVinci AEMIF support + * + * Copyright 2010 (C) Texas Instruments, Inc. http://www.ti.com/ + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ +#ifndef _MACH_DAVINCI_AEMIF_H +#define _MACH_DAVINCI_AEMIF_H + +#define NRCSR_OFFSET 0x00 +#define AWCCR_OFFSET 0x04 +#define A1CR_OFFSET 0x10 + +#define ACR_ASIZE_MASK 0x3 +#define ACR_EW_MASK BIT(30) +#define ACR_SS_MASK BIT(31) + +/* All timings in nanoseconds */ +struct davinci_aemif_timing { + u8 wsetup; + u8 wstrobe; + u8 whold; + + u8 rsetup; + u8 rstrobe; + u8 rhold; + + u8 ta; +}; + +int davinci_aemif_setup_timing(struct davinci_aemif_timing *t, + void __iomem *base, unsigned cs); +#endif diff --git a/arch/arm/mach-davinci/include/mach/nand.h b/arch/arm/mach-davinci/include/mach/nand.h index b2ad809..b5893f0 100644 --- a/arch/arm/mach-davinci/include/mach/nand.h +++ b/arch/arm/mach-davinci/include/mach/nand.h @@ -30,9 +30,6 @@ #include -#define NRCSR_OFFSET 0x00 -#define AWCCR_OFFSET 0x04 -#define A1CR_OFFSET 0x10 #define NANDFCR_OFFSET 0x60 #define NANDFSR_OFFSET 0x64 #define NANDF1ECC_OFFSET 0x70 -- cgit v1.1 From a88dbc5bfdd26132bbf0ad19dd672e036971d74d Mon Sep 17 00:00:00 2001 From: Sekhar Nori Date: Mon, 9 Aug 2010 15:46:36 +0530 Subject: nand: davinci: add support for timing configuration This patch modifies the DaVinci NAND driver to use the new AEMIF timing setup API to configure the NAND access timings. Earlier, AEMIF configuration was being done as a special case for DM644x board, but now more boards emerge which have capability to boot for other media (SPI flash, NOR flash) and have the kernel access NAND flash. This means that kernel cannot always depend on the bootloader to setup the NAND. Also, on platforms such as da850/omap-l138, the aemif input frequency changes as cpu frequency changes; necessiating re-calculation of timimg values as part of cpufreq transtitions. This patch forms the basis for adding that support. Signed-off-by: Sekhar Nori Acked-by: Kevin Hilman Signed-off-by: Artem Bityutskiy --- arch/arm/mach-davinci/include/mach/nand.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-davinci/include/mach/nand.h b/arch/arm/mach-davinci/include/mach/nand.h index b5893f0..0251510 100644 --- a/arch/arm/mach-davinci/include/mach/nand.h +++ b/arch/arm/mach-davinci/include/mach/nand.h @@ -80,6 +80,9 @@ struct davinci_nand_pdata { /* platform_data */ /* Main and mirror bbt descriptor overrides */ struct nand_bbt_descr *bbt_td; struct nand_bbt_descr *bbt_md; + + /* Access timings */ + struct davinci_aemif_timing *timing; }; #endif /* __ARCH_ARM_DAVINCI_NAND_H */ -- cgit v1.1 From fe69c82d0862f54b1a5aa5ece046468b4e76b40c Mon Sep 17 00:00:00 2001 From: Sekhar Nori Date: Mon, 9 Aug 2010 15:46:37 +0530 Subject: davinci: dm644x evm: setup NAND flash timing The DM644x EVM nand flash timing was earlier being done as a special case in the NAND driver itself. With the NAND driver now capable of progamming the AEMIF interface using timing data passed from the platform, the timing values are being moved into their rightful place in the EVM specific board file. The values being programmed match what was being done earlier and thus do not represent any change in performance/functionality. Signed-off-by: Sekhar Nori Acked-by: Kevin Hilman Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/board-dm644x-evm.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c index 34c8b41..65bb940 100644 --- a/arch/arm/mach-davinci/board-dm644x-evm.c +++ b/arch/arm/mach-davinci/board-dm644x-evm.c @@ -37,6 +37,7 @@ #include #include #include +#include #define DM644X_EVM_PHY_MASK (0x2) #define DM644X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ @@ -137,11 +138,22 @@ static struct mtd_partition davinci_evm_nandflash_partition[] = { */ }; +static struct davinci_aemif_timing davinci_evm_nandflash_timing = { + .wsetup = 20, + .wstrobe = 40, + .whold = 20, + .rsetup = 10, + .rstrobe = 40, + .rhold = 10, + .ta = 40, +}; + static struct davinci_nand_pdata davinci_evm_nandflash_data = { .parts = davinci_evm_nandflash_partition, .nr_parts = ARRAY_SIZE(davinci_evm_nandflash_partition), .ecc_mode = NAND_ECC_HW, .options = NAND_USE_FLASH_BBT, + .timing = &davinci_evm_nandflash_timing, }; static struct resource davinci_evm_nandflash_resource[] = { -- cgit v1.1 From 217f13662f291d8eaac5a3dfd7ba35be0a91c9fc Mon Sep 17 00:00:00 2001 From: Sudhakar Rajashekhara Date: Mon, 9 Aug 2010 15:46:38 +0530 Subject: davinci: am17x/da830/omap-l137 evm: setup NAND flash timing Setup the NAND flash timings for DA830 EVM. Before configuring the timing values, throughput calculation using dd command yielded 477 kB/s write and 970 kB/s read speed. After the timing configuration, the throughput was measured to be 2.5 MB/s write and 5.1 MB/s read. [Mukul Bhatnagar: actual calculation of timing values from the NAND datasheet] Signed-off-by: Sudhakar Rajashekhara Cc: Mukul Bhatnagar Signed-off-by: Sekhar Nori Acked-by: Kevin Hilman Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/board-da830-evm.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c index 292e8b7..de82739 100644 --- a/arch/arm/mach-davinci/board-da830-evm.c +++ b/arch/arm/mach-davinci/board-da830-evm.c @@ -29,6 +29,7 @@ #include #include #include +#include #define DA830_EVM_PHY_MASK 0x0 #define DA830_EVM_MDIO_FREQUENCY 2200000 /* PHY bus frequency */ @@ -360,6 +361,16 @@ static struct nand_bbt_descr da830_evm_nand_bbt_mirror_descr = { .pattern = da830_evm_nand_mirror_pattern }; +static struct davinci_aemif_timing da830_evm_nandflash_timing = { + .wsetup = 24, + .wstrobe = 21, + .whold = 14, + .rsetup = 19, + .rstrobe = 50, + .rhold = 0, + .ta = 20, +}; + static struct davinci_nand_pdata da830_evm_nand_pdata = { .parts = da830_evm_nand_partitions, .nr_parts = ARRAY_SIZE(da830_evm_nand_partitions), @@ -368,6 +379,7 @@ static struct davinci_nand_pdata da830_evm_nand_pdata = { .options = NAND_USE_FLASH_BBT, .bbt_td = &da830_evm_nand_bbt_main_descr, .bbt_md = &da830_evm_nand_bbt_mirror_descr, + .timing = &da830_evm_nandflash_timing, }; static struct resource da830_evm_nand_resources[] = { -- cgit v1.1 From 18a8505cc130448c8c0a29a46573b46697bf0e42 Mon Sep 17 00:00:00 2001 From: Sekhar Nori Date: Mon, 9 Aug 2010 15:46:39 +0530 Subject: davinci: am18x/da850/omap-l138 evm: setup NAND flash timing Setup the NAND flash timings for DA850 EVM Before configuring the timing values, throughput calculation using dd command yielded 469 kB/s write and 966 kB/s read speed. After the timing configuration, the throughput was measured to be 2.4 MB/s write and 5 MB/s read. [Mukul Bhatnagar: actual calculation of timing values from the NAND datasheet] Signed-off-by: Sekhar Nori Cc: Mukul Bhatnagar Acked-by: Kevin Hilman Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/board-da850-evm.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index 190ebd3..c1d45d7 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -36,6 +36,7 @@ #include #include #include +#include #define DA850_EVM_PHY_MASK 0x1 #define DA850_EVM_MDIO_FREQUENCY 2200000 /* PHY bus frequency */ @@ -143,12 +144,23 @@ static struct mtd_partition da850_evm_nandflash_partition[] = { }, }; +static struct davinci_aemif_timing da850_evm_nandflash_timing = { + .wsetup = 24, + .wstrobe = 21, + .whold = 14, + .rsetup = 19, + .rstrobe = 50, + .rhold = 0, + .ta = 20, +}; + static struct davinci_nand_pdata da850_evm_nandflash_data = { .parts = da850_evm_nandflash_partition, .nr_parts = ARRAY_SIZE(da850_evm_nandflash_partition), .ecc_mode = NAND_ECC_HW, .ecc_bits = 4, .options = NAND_USE_FLASH_BBT, + .timing = &da850_evm_nandflash_timing, }; static struct resource da850_evm_nandflash_resource[] = { -- cgit v1.1 From 0b3fc7bb88243371a2bd4a4990fb62a0b722efe7 Mon Sep 17 00:00:00 2001 From: Sekhar Nori Date: Mon, 9 Aug 2010 15:46:40 +0530 Subject: davinci: dm6467t evm: setup NAND flash timing Setup NAND flash timing on DM6467T EVM. Without the timing setup, the NAND flash on DM6467T RevC EVM reports a number of random bad blocks because of read errors. Also, with this, copying a 100M file on RevB EVM takes ~35 sec against 1 minute 30 seconds earlier. Signed-off-by: Sekhar Nori Acked-by: Kevin Hilman Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/board-dm646x-evm.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c index 4502f34..5a29955 100644 --- a/arch/arm/mach-davinci/board-dm646x-evm.c +++ b/arch/arm/mach-davinci/board-dm646x-evm.c @@ -42,6 +42,7 @@ #include #include #include +#include #include "clock.h" @@ -71,6 +72,16 @@ static struct mtd_partition davinci_nand_partitions[] = { } }; +static struct davinci_aemif_timing dm6467tevm_nandflash_timing = { + .wsetup = 29, + .wstrobe = 24, + .whold = 14, + .rsetup = 19, + .rstrobe = 33, + .rhold = 0, + .ta = 29, +}; + static struct davinci_nand_pdata davinci_nand_data = { .mask_cle = 0x80000, .mask_ale = 0x40000, @@ -763,6 +774,9 @@ static __init void evm_init(void) dm646x_init_mcasp0(&dm646x_evm_snd_data[0]); dm646x_init_mcasp1(&dm646x_evm_snd_data[1]); + if (machine_is_davinci_dm6467tevm()) + davinci_nand_data.timing = &dm6467tevm_nandflash_timing; + platform_device_register(&davinci_nand_device); dm646x_init_edma(dm646x_edma_rsv); -- cgit v1.1 From 1aa5f2a9c1575279baf06e94a4bd3b3b86b7f176 Mon Sep 17 00:00:00 2001 From: Michael Williamson Date: Tue, 31 Aug 2010 14:30:15 -0400 Subject: davinci: Add machine checks to DA8XX serial console init routines This patch adds machine checks in the serial console init routines for the DA8XX EVM boards. This is needed because there are other DA8XX based machines that use a different UART/tty as the console and may be included in a common kernel build. Signed-off-by: Michael Williamson Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/board-da830-evm.c | 3 +++ arch/arm/mach-davinci/board-da850-evm.c | 3 +++ 2 files changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c index de82739..ef1ab0b 100644 --- a/arch/arm/mach-davinci/board-da830-evm.c +++ b/arch/arm/mach-davinci/board-da830-evm.c @@ -598,6 +598,9 @@ static __init void da830_evm_init(void) #ifdef CONFIG_SERIAL_8250_CONSOLE static int __init da830_evm_console_init(void) { + if (!machine_is_davinci_da830_evm()) + return 0; + return add_preferred_console("ttyS", 2, "115200"); } console_initcall(da830_evm_console_init); diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index c1d45d7..ac2297c 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -859,6 +859,9 @@ static __init void da850_evm_init(void) #ifdef CONFIG_SERIAL_8250_CONSOLE static int __init da850_evm_console_init(void) { + if (!machine_is_davinci_da850_evm()) + return 0; + return add_preferred_console("ttyS", 2, "115200"); } console_initcall(da850_evm_console_init); -- cgit v1.1 From 9c6fbbee8d67eca75e9ffde3a10eb7ac0a73360d Mon Sep 17 00:00:00 2001 From: Michael Williamson Date: Tue, 31 Aug 2010 14:42:32 -0400 Subject: davinci: Add CONFIG_REGULATOR_DUMMY to DA8XX defconfig file. In order to support reference DA8XX machines not providing a voltage regulator control for the core voltage, the REGULATOR_DUMMY option is required. Signed-off-by: Michael Williamson Signed-off-by: Kevin Hilman --- arch/arm/configs/da8xx_omapl_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/configs/da8xx_omapl_defconfig b/arch/arm/configs/da8xx_omapl_defconfig index ba66705..3952a4e 100644 --- a/arch/arm/configs/da8xx_omapl_defconfig +++ b/arch/arm/configs/da8xx_omapl_defconfig @@ -79,6 +79,7 @@ CONFIG_I2C_DAVINCI=y # CONFIG_HWMON is not set CONFIG_WATCHDOG=y CONFIG_REGULATOR=y +CONFIG_REGULATOR_DUMMY=y CONFIG_REGULATOR_TPS6507X=y CONFIG_FB=y CONFIG_FB_DA8XX=y -- cgit v1.1 From f2dbb6d91b53d3ffbc85152aa7265599f0a4d850 Mon Sep 17 00:00:00 2001 From: Michael Williamson Date: Thu, 2 Sep 2010 13:58:07 -0400 Subject: davinci: Initial support for MityDSP-L138/MityARM-1808 This patch adds initial support for the MityDSP-L138 and MityDSP-1808 system on Module (SOM) under the machine name "mityomapl138". These SOMs are based on the da850 davinci CPU architecture. Information on these SOMs may be found at http://www.mitydsp.com. Basic support for the console UART, NAND, and EMAC (MII interface) is included in this patch. Signed-off-by: Michael Williamson Signed-off-by: Kevin Hilman --- arch/arm/configs/da8xx_omapl_defconfig | 1 + arch/arm/mach-davinci/Kconfig | 8 + arch/arm/mach-davinci/Makefile | 1 + arch/arm/mach-davinci/board-mityomapl138.c | 221 ++++++++++++++++++++++++ arch/arm/mach-davinci/include/mach/uncompress.h | 1 + 5 files changed, 232 insertions(+) create mode 100644 arch/arm/mach-davinci/board-mityomapl138.c (limited to 'arch') diff --git a/arch/arm/configs/da8xx_omapl_defconfig b/arch/arm/configs/da8xx_omapl_defconfig index 3952a4e..f8a47ee 100644 --- a/arch/arm/configs/da8xx_omapl_defconfig +++ b/arch/arm/configs/da8xx_omapl_defconfig @@ -17,6 +17,7 @@ CONFIG_MODVERSIONS=y CONFIG_ARCH_DAVINCI=y CONFIG_ARCH_DAVINCI_DA830=y CONFIG_ARCH_DAVINCI_DA850=y +CONFIG_MACH_MITYOMAPL138=y CONFIG_DAVINCI_RESET_CLOCKS=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 2bf03e9..9aca60c 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -185,6 +185,14 @@ config MACH_TNETV107X help Say Y here to select the TI TNETV107X Evaluation Module. +config MACH_MITYOMAPL138 + bool "Critical Link MityDSP-L138/MityARM-1808 SoM" + depends on ARCH_DAVINCI_DA850 + help + Say Y here to select the Critical Link MityDSP-L138/MityARM-1808 + System on Module. Information on this SoM may be found at + http://www.mitydsp.com + config DAVINCI_MUX bool "DAVINCI multiplexing support" depends on ARCH_DAVINCI diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index 77a0f71..a7a70d1 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -33,6 +33,7 @@ obj-$(CONFIG_MACH_DAVINCI_DM365_EVM) += board-dm365-evm.o obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += board-da830-evm.o obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += board-da850-evm.o obj-$(CONFIG_MACH_TNETV107X) += board-tnetv107x-evm.o +obj-$(CONFIG_MACH_MITYOMAPL138) += board-mityomapl138.o # Power Management obj-$(CONFIG_CPU_FREQ) += cpufreq.o diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c new file mode 100644 index 0000000..7146916 --- /dev/null +++ b/arch/arm/mach-davinci/board-mityomapl138.c @@ -0,0 +1,221 @@ +/* + * Critical Link MityOMAP-L138 SoM + * + * Copyright (C) 2010 Critical Link LLC - http://www.criticallink.com + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of + * any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#define MITYOMAPL138_PHY_MASK 0x08 /* hardcoded for now */ +#define MITYOMAPL138_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ + +/* + * MityDSP-L138 includes a 256 MByte large-page NAND flash + * (128K blocks). + */ +struct mtd_partition mityomapl138_nandflash_partition[] = { + { + .name = "rootfs", + .offset = 0, + .size = SZ_128M, + .mask_flags = 0, /* MTD_WRITEABLE, */ + }, + { + .name = "homefs", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0, + }, +}; + +static struct davinci_nand_pdata mityomapl138_nandflash_data = { + .parts = mityomapl138_nandflash_partition, + .nr_parts = ARRAY_SIZE(mityomapl138_nandflash_partition), + .ecc_mode = NAND_ECC_HW, + .options = NAND_USE_FLASH_BBT | NAND_BUSWIDTH_16, + .ecc_bits = 1, /* 4 bit mode is not supported with 16 bit NAND */ +}; + +static struct resource mityomapl138_nandflash_resource[] = { + { + .start = DA8XX_AEMIF_CS3_BASE, + .end = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = DA8XX_AEMIF_CTL_BASE, + .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device mityomapl138_nandflash_device = { + .name = "davinci_nand", + .id = 0, + .dev = { + .platform_data = &mityomapl138_nandflash_data, + }, + .num_resources = ARRAY_SIZE(mityomapl138_nandflash_resource), + .resource = mityomapl138_nandflash_resource, +}; + +static struct platform_device *mityomapl138_devices[] __initdata = { + &mityomapl138_nandflash_device, +}; + +static void __init mityomapl138_setup_nand(void) +{ + platform_add_devices(mityomapl138_devices, + ARRAY_SIZE(mityomapl138_devices)); +} + +static struct davinci_uart_config mityomapl138_uart_config __initdata = { + .enabled_uarts = 0x7, +}; + +static const short mityomap_mii_pins[] = { + DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3, + DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER, + DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3, + DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK, + DA850_MDIO_D, + -1 +}; + +static const short mityomap_rmii_pins[] = { + DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN, + DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1, + DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK, + DA850_MDIO_D, + -1 +}; + +static void __init mityomapl138_config_emac(void) +{ + void __iomem *cfg_chip3_base; + int ret; + u32 val; + struct davinci_soc_info *soc_info = &davinci_soc_info; + + soc_info->emac_pdata->rmii_en = 0; /* hardcoded for now */ + + cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG); + val = __raw_readl(cfg_chip3_base); + + if (soc_info->emac_pdata->rmii_en) { + val |= BIT(8); + ret = davinci_cfg_reg_list(mityomap_rmii_pins); + pr_info("RMII PHY configured\n"); + } else { + val &= ~BIT(8); + ret = davinci_cfg_reg_list(mityomap_mii_pins); + pr_info("MII PHY configured\n"); + } + + if (ret) { + pr_warning("mii/rmii mux setup failed: %d\n", ret); + return; + } + + /* configure the CFGCHIP3 register for RMII or MII */ + __raw_writel(val, cfg_chip3_base); + + soc_info->emac_pdata->phy_mask = MITYOMAPL138_PHY_MASK; + pr_debug("setting phy_mask to %x\n", soc_info->emac_pdata->phy_mask); + soc_info->emac_pdata->mdio_max_freq = MITYOMAPL138_MDIO_FREQUENCY; + + ret = da8xx_register_emac(); + if (ret) + pr_warning("emac registration failed: %d\n", ret); +} + +static struct davinci_pm_config da850_pm_pdata = { + .sleepcount = 128, +}; + +static struct platform_device da850_pm_device = { + .name = "pm-davinci", + .dev = { + .platform_data = &da850_pm_pdata, + }, + .id = -1, +}; + +static void __init mityomapl138_init(void) +{ + int ret; + + /* for now, no special EDMA channels are reserved */ + ret = da850_register_edma(NULL); + if (ret) + pr_warning("edma registration failed: %d\n", ret); + + ret = da8xx_register_watchdog(); + if (ret) + pr_warning("watchdog registration failed: %d\n", ret); + + davinci_serial_init(&mityomapl138_uart_config); + + mityomapl138_setup_nand(); + + mityomapl138_config_emac(); + + ret = da8xx_register_rtc(); + if (ret) + pr_warning("rtc setup failed: %d\n", ret); + + ret = da850_register_cpufreq("pll0_sysclk3"); + if (ret) + pr_warning("cpufreq registration failed: %d\n", ret); + + ret = da8xx_register_cpuidle(); + if (ret) + pr_warning("cpuidle registration failed: %d\n", ret); + + ret = da850_register_pm(&da850_pm_device); + if (ret) + pr_warning("da850_evm_init: suspend registration failed: %d\n", + ret); +} + +#ifdef CONFIG_SERIAL_8250_CONSOLE +static int __init mityomapl138_console_init(void) +{ + if (!machine_is_mityomapl138()) + return 0; + + return add_preferred_console("ttyS", 1, "115200"); +} +console_initcall(mityomapl138_console_init); +#endif + +static void __init mityomapl138_map_io(void) +{ + da850_init(); +} + +MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808") + .phys_io = IO_PHYS, + .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, + .boot_params = (DA8XX_DDR_BASE + 0x100), + .map_io = mityomapl138_map_io, + .init_irq = cp_intc_init, + .timer = &davinci_timer, + .init_machine = mityomapl138_init, +MACHINE_END diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h index 15a6192..d370391 100644 --- a/arch/arm/mach-davinci/include/mach/uncompress.h +++ b/arch/arm/mach-davinci/include/mach/uncompress.h @@ -88,6 +88,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id) /* DA8xx boards */ DEBUG_LL_DA8XX(davinci_da830_evm, 2); DEBUG_LL_DA8XX(davinci_da850_evm, 2); + DEBUG_LL_DA8XX(mityomapl138, 1); /* TNETV107x boards */ DEBUG_LL_TNETV107X(tnetv107x, 1); -- cgit v1.1 From b41547c153436712daef544c0f18547fcb70f4ac Mon Sep 17 00:00:00 2001 From: Cyril Chemparathy Date: Fri, 3 Sep 2010 16:01:59 -0400 Subject: davinci: add idcode for tnetv107x rev 1.1/1.2 This patch adds an entry into the idcode table for tnetv107x silicon revision 1.1 and 1.2 devices. Signed-off-by: Cyril Chemparathy Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/tnetv107x.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-davinci/tnetv107x.c b/arch/arm/mach-davinci/tnetv107x.c index 06d2ac9..daeae06 100644 --- a/arch/arm/mach-davinci/tnetv107x.c +++ b/arch/arm/mach-davinci/tnetv107x.c @@ -581,7 +581,14 @@ static struct davinci_id ids[] = { .part_no = 0xb8a1, .manufacturer = 0x017, .cpu_id = DAVINCI_CPU_ID_TNETV107X, - .name = "tnetv107x rev1.0", + .name = "tnetv107x rev 1.0", + }, + { + .variant = 0x1, + .part_no = 0xb8a1, + .manufacturer = 0x017, + .cpu_id = DAVINCI_CPU_ID_TNETV107X, + .name = "tnetv107x rev 1.1/1.2", }, }; -- cgit v1.1 From 8774882394190fe52d1df449b1e1c6cff9c3088c Mon Sep 17 00:00:00 2001 From: Michael Williamson Date: Sun, 5 Sep 2010 13:29:39 -0400 Subject: davinci: Add I2C0 devices to MityDSP-L138/MityARM-1808 platform This patch adds the i2c0 bus and attached devices to the MityDSP-L138 and MityARM-1808 davinci SoM. Included is a TPS65023 voltage regulator needed for power management and a small 24c02 EPROM that contains factory configuration data. Signed-off-by: Michael Williamson Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/board-mityomapl138.c | 145 +++++++++++++++++++++++++++++ 1 file changed, 145 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c index 7146916..84d5aff5 100644 --- a/arch/arm/mach-davinci/board-mityomapl138.c +++ b/arch/arm/mach-davinci/board-mityomapl138.c @@ -13,6 +13,8 @@ #include #include #include +#include +#include #include #include @@ -25,6 +27,141 @@ #define MITYOMAPL138_PHY_MASK 0x08 /* hardcoded for now */ #define MITYOMAPL138_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ +static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = { + .bus_freq = 100, /* kHz */ + .bus_delay = 0, /* usec */ +}; + +/* TPS65023 voltage regulator support */ +/* 1.2V Core */ +struct regulator_consumer_supply tps65023_dcdc1_consumers[] = { + { + .supply = "cvdd", + }, +}; + +/* 1.8V */ +struct regulator_consumer_supply tps65023_dcdc2_consumers[] = { + { + .supply = "usb0_vdda18", + }, + { + .supply = "usb1_vdda18", + }, + { + .supply = "ddr_dvdd18", + }, + { + .supply = "sata_vddr", + }, +}; + +/* 1.2V */ +struct regulator_consumer_supply tps65023_dcdc3_consumers[] = { + { + .supply = "sata_vdd", + }, + { + .supply = "usb_cvdd", + }, + { + .supply = "pll0_vdda", + }, + { + .supply = "pll1_vdda", + }, +}; + +/* 1.8V Aux LDO, not used */ +struct regulator_consumer_supply tps65023_ldo1_consumers[] = { + { + .supply = "1.8v_aux", + }, +}; + +/* FPGA VCC Aux (2.5 or 3.3) LDO */ +struct regulator_consumer_supply tps65023_ldo2_consumers[] = { + { + .supply = "vccaux", + }, +}; + +struct regulator_init_data tps65023_regulator_data[] = { + /* dcdc1 */ + { + .constraints = { + .min_uV = 1150000, + .max_uV = 1350000, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc1_consumers), + .consumer_supplies = tps65023_dcdc1_consumers, + }, + /* dcdc2 */ + { + .constraints = { + .min_uV = 1800000, + .max_uV = 1800000, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc2_consumers), + .consumer_supplies = tps65023_dcdc2_consumers, + }, + /* dcdc3 */ + { + .constraints = { + .min_uV = 1200000, + .max_uV = 1200000, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc3_consumers), + .consumer_supplies = tps65023_dcdc3_consumers, + }, + /* ldo1 */ + { + .constraints = { + .min_uV = 1800000, + .max_uV = 1800000, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo1_consumers), + .consumer_supplies = tps65023_ldo1_consumers, + }, + /* ldo2 */ + { + .constraints = { + .min_uV = 2500000, + .max_uV = 3300000, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo2_consumers), + .consumer_supplies = tps65023_ldo2_consumers, + }, +}; + +static struct i2c_board_info __initdata mityomap_tps65023_info[] = { + { + I2C_BOARD_INFO("tps65023", 0x48), + .platform_data = &tps65023_regulator_data[0], + }, + { + I2C_BOARD_INFO("24c02", 0x50), + }, +}; + +static int __init pmic_tps65023_init(void) +{ + return i2c_register_board_info(1, mityomap_tps65023_info, + ARRAY_SIZE(mityomap_tps65023_info)); +} + /* * MityDSP-L138 includes a 256 MByte large-page NAND flash * (128K blocks). @@ -172,6 +309,14 @@ static void __init mityomapl138_init(void) davinci_serial_init(&mityomapl138_uart_config); + ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata); + if (ret) + pr_warning("i2c0 registration failed: %d\n", ret); + + ret = pmic_tps65023_init(); + if (ret) + pr_warning("TPS65023 PMIC init failed: %d\n", ret); + mityomapl138_setup_nand(); mityomapl138_config_emac(); -- cgit v1.1 From d22960c8bbb8f685c2d8c4051e1f335ab13dca24 Mon Sep 17 00:00:00 2001 From: Cyril Chemparathy Date: Wed, 15 Sep 2010 10:11:22 -0400 Subject: davinci: add mdio platform devices This patch adds mdio platform devices on SoCs that have the necessary hardware. Clock lookup entries (aliases) have also been added, so that the MDIO and EMAC drivers can independently enable/disable a shared underlying clock. Further, the EMAC MMR region has been split down into separate MDIO and EMAC regions. Signed-off-by: Cyril Chemparathy Acked-by: David S. Miller Tested-by: Michael Williamson Tested-by: Caglar Akyuz Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/devices-da8xx.c | 29 +++++++++++++++++++++++++++-- arch/arm/mach-davinci/dm365.c | 22 +++++++++++++++++++++- arch/arm/mach-davinci/dm644x.c | 22 +++++++++++++++++++++- arch/arm/mach-davinci/dm646x.c | 21 ++++++++++++++++++++- arch/arm/mach-davinci/include/mach/dm365.h | 1 + arch/arm/mach-davinci/include/mach/dm644x.h | 1 + arch/arm/mach-davinci/include/mach/dm646x.h | 1 + 7 files changed, 92 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c index caeb7f4..9039221 100644 --- a/arch/arm/mach-davinci/devices-da8xx.c +++ b/arch/arm/mach-davinci/devices-da8xx.c @@ -352,7 +352,7 @@ int __init da8xx_register_watchdog(void) static struct resource da8xx_emac_resources[] = { { .start = DA8XX_EMAC_CPPI_PORT_BASE, - .end = DA8XX_EMAC_CPPI_PORT_BASE + 0x5000 - 1, + .end = DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1, .flags = IORESOURCE_MEM, }, { @@ -396,9 +396,34 @@ static struct platform_device da8xx_emac_device = { .resource = da8xx_emac_resources, }; +static struct resource da8xx_mdio_resources[] = { + { + .start = DA8XX_EMAC_MDIO_BASE, + .end = DA8XX_EMAC_MDIO_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device da8xx_mdio_device = { + .name = "davinci_mdio", + .id = 0, + .num_resources = ARRAY_SIZE(da8xx_mdio_resources), + .resource = da8xx_mdio_resources, +}; + int __init da8xx_register_emac(void) { - return platform_device_register(&da8xx_emac_device); + int ret; + + ret = platform_device_register(&da8xx_mdio_device); + if (ret < 0) + return ret; + ret = platform_device_register(&da8xx_emac_device); + if (ret < 0) + return ret; + ret = clk_add_alias(NULL, dev_name(&da8xx_mdio_device.dev), + NULL, &da8xx_emac_device.dev); + return ret; } static struct resource da830_mcasp1_resources[] = { diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index 6b6f4c6..71f0f9d 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -699,7 +699,7 @@ static struct emac_platform_data dm365_emac_pdata = { static struct resource dm365_emac_resources[] = { { .start = DM365_EMAC_BASE, - .end = DM365_EMAC_BASE + 0x47ff, + .end = DM365_EMAC_BASE + SZ_16K - 1, .flags = IORESOURCE_MEM, }, { @@ -734,6 +734,21 @@ static struct platform_device dm365_emac_device = { .resource = dm365_emac_resources, }; +static struct resource dm365_mdio_resources[] = { + { + .start = DM365_EMAC_MDIO_BASE, + .end = DM365_EMAC_MDIO_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device dm365_mdio_device = { + .name = "davinci_mdio", + .id = 0, + .num_resources = ARRAY_SIZE(dm365_mdio_resources), + .resource = dm365_mdio_resources, +}; + static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = { [IRQ_VDINT0] = 2, [IRQ_VDINT1] = 6, @@ -1220,7 +1235,12 @@ static int __init dm365_init_devices(void) davinci_cfg_reg(DM365_INT_EDMA_CC); platform_device_register(&dm365_edma_device); + + platform_device_register(&dm365_mdio_device); platform_device_register(&dm365_emac_device); + clk_add_alias(NULL, dev_name(&dm365_mdio_device.dev), + NULL, &dm365_emac_device.dev); + /* Add isif clock alias */ clk_add_alias("master", dm365_isif_dev.name, "vpss_master", NULL); platform_device_register(&dm365_vpss_device); diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index 40fec31..c103b2c 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -330,7 +330,7 @@ static struct emac_platform_data dm644x_emac_pdata = { static struct resource dm644x_emac_resources[] = { { .start = DM644X_EMAC_BASE, - .end = DM644X_EMAC_BASE + 0x47ff, + .end = DM644X_EMAC_BASE + SZ_16K - 1, .flags = IORESOURCE_MEM, }, { @@ -350,6 +350,21 @@ static struct platform_device dm644x_emac_device = { .resource = dm644x_emac_resources, }; +static struct resource dm644x_mdio_resources[] = { + { + .start = DM644X_EMAC_MDIO_BASE, + .end = DM644X_EMAC_MDIO_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device dm644x_mdio_device = { + .name = "davinci_mdio", + .id = 0, + .num_resources = ARRAY_SIZE(dm644x_mdio_resources), + .resource = dm644x_mdio_resources, +}; + /* * Device specific mux setup * @@ -777,7 +792,12 @@ static int __init dm644x_init_devices(void) clk_add_alias("master", dm644x_ccdc_dev.name, "vpss_master", NULL); clk_add_alias("slave", dm644x_ccdc_dev.name, "vpss_slave", NULL); platform_device_register(&dm644x_edma_device); + + platform_device_register(&dm644x_mdio_device); platform_device_register(&dm644x_emac_device); + clk_add_alias(NULL, dev_name(&dm644x_mdio_device.dev), + NULL, &dm644x_emac_device.dev); + platform_device_register(&dm644x_vpss_device); platform_device_register(&dm644x_ccdc_dev); platform_device_register(&vpfe_capture_dev); diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c index e4a3df1..8da886b 100644 --- a/arch/arm/mach-davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c @@ -366,7 +366,7 @@ static struct emac_platform_data dm646x_emac_pdata = { static struct resource dm646x_emac_resources[] = { { .start = DM646X_EMAC_BASE, - .end = DM646X_EMAC_BASE + 0x47ff, + .end = DM646X_EMAC_BASE + SZ_16K - 1, .flags = IORESOURCE_MEM, }, { @@ -401,6 +401,21 @@ static struct platform_device dm646x_emac_device = { .resource = dm646x_emac_resources, }; +static struct resource dm646x_mdio_resources[] = { + { + .start = DM646X_EMAC_MDIO_BASE, + .end = DM646X_EMAC_MDIO_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device dm646x_mdio_device = { + .name = "davinci_mdio", + .id = 0, + .num_resources = ARRAY_SIZE(dm646x_mdio_resources), + .resource = dm646x_mdio_resources, +}; + /* * Device specific mux setup * @@ -897,7 +912,11 @@ static int __init dm646x_init_devices(void) if (!cpu_is_davinci_dm646x()) return 0; + platform_device_register(&dm646x_mdio_device); platform_device_register(&dm646x_emac_device); + clk_add_alias(NULL, dev_name(&dm646x_mdio_device.dev), + NULL, &dm646x_emac_device.dev); + return 0; } postcore_initcall(dm646x_init_devices); diff --git a/arch/arm/mach-davinci/include/mach/dm365.h b/arch/arm/mach-davinci/include/mach/dm365.h index ea5df3b..dbb5052 100644 --- a/arch/arm/mach-davinci/include/mach/dm365.h +++ b/arch/arm/mach-davinci/include/mach/dm365.h @@ -21,6 +21,7 @@ #include #define DM365_EMAC_BASE (0x01D07000) +#define DM365_EMAC_MDIO_BASE (DM365_EMAC_BASE + 0x4000) #define DM365_EMAC_CNTRL_OFFSET (0x0000) #define DM365_EMAC_CNTRL_MOD_OFFSET (0x3000) #define DM365_EMAC_CNTRL_RAM_OFFSET (0x1000) diff --git a/arch/arm/mach-davinci/include/mach/dm644x.h b/arch/arm/mach-davinci/include/mach/dm644x.h index 6fca568..5159117 100644 --- a/arch/arm/mach-davinci/include/mach/dm644x.h +++ b/arch/arm/mach-davinci/include/mach/dm644x.h @@ -28,6 +28,7 @@ #include #define DM644X_EMAC_BASE (0x01C80000) +#define DM644X_EMAC_MDIO_BASE (DM644X_EMAC_BASE + 0x4000) #define DM644X_EMAC_CNTRL_OFFSET (0x0000) #define DM644X_EMAC_CNTRL_MOD_OFFSET (0x1000) #define DM644X_EMAC_CNTRL_RAM_OFFSET (0x2000) diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h index 0a27ee9..1c4dca9 100644 --- a/arch/arm/mach-davinci/include/mach/dm646x.h +++ b/arch/arm/mach-davinci/include/mach/dm646x.h @@ -19,6 +19,7 @@ #include #define DM646X_EMAC_BASE (0x01C80000) +#define DM646X_EMAC_MDIO_BASE (DM646X_EMAC_BASE + 0x4000) #define DM646X_EMAC_CNTRL_OFFSET (0x0000) #define DM646X_EMAC_CNTRL_MOD_OFFSET (0x1000) #define DM646X_EMAC_CNTRL_RAM_OFFSET (0x2000) -- cgit v1.1 From 433cdb0ac4c4660e98412e441589a7a712010325 Mon Sep 17 00:00:00 2001 From: Cyril Chemparathy Date: Wed, 15 Sep 2010 10:11:23 -0400 Subject: omap: add mdio platform devices This patch adds mdio platform devices on SoCs that have the necessary hardware. Clock lookup entries (aliases) have also been added, so that the MDIO and EMAC drivers can independently enable/disable a shared underlying clock. Further, the EMAC MMR region has been split down into separate MDIO and EMAC regions. Signed-off-by: Cyril Chemparathy Acked-by: David S. Miller Acked-by: Tony Lindgren Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/board-am3517evm.c | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index 4d0f585..5dd1b73 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c @@ -18,6 +18,7 @@ #include #include +#include #include #include #include @@ -41,6 +42,27 @@ #define AM35XX_EVM_PHY_MASK (0xF) #define AM35XX_EVM_MDIO_FREQUENCY (1000000) +static struct mdio_platform_data am3517_evm_mdio_pdata = { + .bus_freq = AM35XX_EVM_MDIO_FREQUENCY, +}; + +static struct resource am3517_mdio_resources[] = { + { + .start = AM35XX_IPSS_EMAC_BASE + AM35XX_EMAC_MDIO_OFFSET, + .end = AM35XX_IPSS_EMAC_BASE + AM35XX_EMAC_MDIO_OFFSET + + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device am3517_mdio_device = { + .name = "davinci_mdio", + .id = 0, + .num_resources = ARRAY_SIZE(am3517_mdio_resources), + .resource = am3517_mdio_resources, + .dev.platform_data = &am3517_evm_mdio_pdata, +}; + static struct emac_platform_data am3517_evm_emac_pdata = { .phy_mask = AM35XX_EVM_PHY_MASK, .mdio_max_freq = AM35XX_EVM_MDIO_FREQUENCY, @@ -50,7 +72,7 @@ static struct emac_platform_data am3517_evm_emac_pdata = { static struct resource am3517_emac_resources[] = { { .start = AM35XX_IPSS_EMAC_BASE, - .end = AM35XX_IPSS_EMAC_BASE + 0x3FFFF, + .end = AM35XX_IPSS_EMAC_BASE + 0x2FFFF, .flags = IORESOURCE_MEM, }, { @@ -121,6 +143,9 @@ void am3517_evm_ethernet_init(struct emac_platform_data *pdata) pdata->interrupt_disable = am3517_disable_ethernet_int; am3517_emac_device.dev.platform_data = pdata; platform_device_register(&am3517_emac_device); + platform_device_register(&am3517_mdio_device); + clk_add_alias(NULL, dev_name(&am3517_mdio_device.dev), + NULL, &am3517_emac_device.dev); regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); regval = regval & (~(AM35XX_CPGMACSS_SW_RST)); -- cgit v1.1 From 782f2d782771484bb951be1c394ca2128ed7774e Mon Sep 17 00:00:00 2001 From: Cyril Chemparathy Date: Wed, 15 Sep 2010 10:11:25 -0400 Subject: davinci: cleanup mdio arch code and switch to phy_id This patch removes davinci architecture code that has now been rendered useless by the previous patches in the MDIO separation series. In addition, the earlier phy_mask definitions have been replaced with corresponding phy_id definitions. Signed-off-by: Cyril Chemparathy Tested-by: Michael Williamson Tested-by: Caglar Akyuz Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/board-da830-evm.c | 7 ++----- arch/arm/mach-davinci/board-da850-evm.c | 7 ++----- arch/arm/mach-davinci/board-dm365-evm.c | 7 ++----- arch/arm/mach-davinci/board-dm644x-evm.c | 8 ++------ arch/arm/mach-davinci/board-dm646x-evm.c | 7 ++----- arch/arm/mach-davinci/board-mityomapl138.c | 8 ++------ arch/arm/mach-davinci/board-neuros-osd2.c | 7 ++----- arch/arm/mach-davinci/board-sffsdr.c | 7 ++----- arch/arm/mach-davinci/devices-da8xx.c | 2 -- arch/arm/mach-davinci/dm365.c | 1 - arch/arm/mach-davinci/dm644x.c | 1 - arch/arm/mach-davinci/dm646x.c | 1 - arch/arm/mach-davinci/include/mach/dm365.h | 1 - arch/arm/mach-davinci/include/mach/dm644x.h | 1 - arch/arm/mach-davinci/include/mach/dm646x.h | 1 - 15 files changed, 16 insertions(+), 50 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c index ef1ab0b..1bb89d3 100644 --- a/arch/arm/mach-davinci/board-da830-evm.c +++ b/arch/arm/mach-davinci/board-da830-evm.c @@ -31,9 +31,7 @@ #include #include -#define DA830_EVM_PHY_MASK 0x0 -#define DA830_EVM_MDIO_FREQUENCY 2200000 /* PHY bus frequency */ - +#define DA830_EVM_PHY_ID "" /* * USB1 VBUS is controlled by GPIO1[15], over-current is reported on GPIO2[4]. */ @@ -558,9 +556,8 @@ static __init void da830_evm_init(void) da830_evm_usb_init(); - soc_info->emac_pdata->phy_mask = DA830_EVM_PHY_MASK; - soc_info->emac_pdata->mdio_max_freq = DA830_EVM_MDIO_FREQUENCY; soc_info->emac_pdata->rmii_en = 1; + soc_info->emac_pdata->phy_id = DA830_EVM_PHY_ID; ret = davinci_cfg_reg_list(da830_cpgmac_pins); if (ret) diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index ac2297c..5e435b0 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -38,9 +38,7 @@ #include #include -#define DA850_EVM_PHY_MASK 0x1 -#define DA850_EVM_MDIO_FREQUENCY 2200000 /* PHY bus frequency */ - +#define DA850_EVM_PHY_ID "0:00" #define DA850_LCD_PWR_PIN GPIO_TO_PIN(2, 8) #define DA850_LCD_BL_PIN GPIO_TO_PIN(2, 15) @@ -678,8 +676,7 @@ static int __init da850_evm_config_emac(void) /* Enable/Disable MII MDIO clock */ gpio_direction_output(DA850_MII_MDIO_CLKEN_PIN, rmii_en); - soc_info->emac_pdata->phy_mask = DA850_EVM_PHY_MASK; - soc_info->emac_pdata->mdio_max_freq = DA850_EVM_MDIO_FREQUENCY; + soc_info->emac_pdata->phy_id = DA850_EVM_PHY_ID; ret = da8xx_register_emac(); if (ret) diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c index bdea2da..a06b84c 100644 --- a/arch/arm/mach-davinci/board-dm365-evm.c +++ b/arch/arm/mach-davinci/board-dm365-evm.c @@ -54,9 +54,7 @@ static inline int have_tvp7002(void) return 0; } -#define DM365_EVM_PHY_MASK (0x2) -#define DM365_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ - +#define DM365_EVM_PHY_ID "0:01" /* * A MAX-II CPLD is used for various board control functions. */ @@ -535,8 +533,7 @@ fail: /* ... and ENET ... */ dm365evm_emac_configure(); - soc_info->emac_pdata->phy_mask = DM365_EVM_PHY_MASK; - soc_info->emac_pdata->mdio_max_freq = DM365_EVM_MDIO_FREQUENCY; + soc_info->emac_pdata->phy_id = DM365_EVM_PHY_ID; resets &= ~BIT(3); /* ... and AIC33 */ diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c index 65bb940..44a2f0a 100644 --- a/arch/arm/mach-davinci/board-dm644x-evm.c +++ b/arch/arm/mach-davinci/board-dm644x-evm.c @@ -39,9 +39,7 @@ #include #include -#define DM644X_EVM_PHY_MASK (0x2) -#define DM644X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ - +#define DM644X_EVM_PHY_ID "0:01" #define LXT971_PHY_ID (0x001378e2) #define LXT971_PHY_MASK (0xfffffff0) @@ -707,9 +705,7 @@ static __init void davinci_evm_init(void) davinci_serial_init(&uart_config); dm644x_init_asp(&dm644x_evm_snd_data); - soc_info->emac_pdata->phy_mask = DM644X_EVM_PHY_MASK; - soc_info->emac_pdata->mdio_max_freq = DM644X_EVM_MDIO_FREQUENCY; - + soc_info->emac_pdata->phy_id = DM644X_EVM_PHY_ID; /* Register the fixup for PHY on DaVinci */ phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK, davinci_phy_fixup); diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c index 5a29955..67669bb 100644 --- a/arch/arm/mach-davinci/board-dm646x-evm.c +++ b/arch/arm/mach-davinci/board-dm646x-evm.c @@ -729,9 +729,7 @@ static struct davinci_uart_config uart_config __initdata = { .enabled_uarts = (1 << 0), }; -#define DM646X_EVM_PHY_MASK (0x2) -#define DM646X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ - +#define DM646X_EVM_PHY_ID "0:01" /* * The following EDMA channels/slots are not being used by drivers (for * example: Timer, GPIO, UART events etc) on dm646x, hence they are being @@ -784,8 +782,7 @@ static __init void evm_init(void) if (HAS_ATA) davinci_init_ide(); - soc_info->emac_pdata->phy_mask = DM646X_EVM_PHY_MASK; - soc_info->emac_pdata->mdio_max_freq = DM646X_EVM_MDIO_FREQUENCY; + soc_info->emac_pdata->phy_id = DM646X_EVM_PHY_ID; } #define DM646X_EVM_REF_FREQ 27000000 diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c index 84d5aff5..6f12a18 100644 --- a/arch/arm/mach-davinci/board-mityomapl138.c +++ b/arch/arm/mach-davinci/board-mityomapl138.c @@ -24,9 +24,7 @@ #include #include -#define MITYOMAPL138_PHY_MASK 0x08 /* hardcoded for now */ -#define MITYOMAPL138_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ - +#define MITYOMAPL138_PHY_ID "0:03" static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = { .bus_freq = 100, /* kHz */ .bus_delay = 0, /* usec */ @@ -273,9 +271,7 @@ static void __init mityomapl138_config_emac(void) /* configure the CFGCHIP3 register for RMII or MII */ __raw_writel(val, cfg_chip3_base); - soc_info->emac_pdata->phy_mask = MITYOMAPL138_PHY_MASK; - pr_debug("setting phy_mask to %x\n", soc_info->emac_pdata->phy_mask); - soc_info->emac_pdata->mdio_max_freq = MITYOMAPL138_MDIO_FREQUENCY; + soc_info->emac_pdata->phy_id = MITYOMAPL138_PHY_ID; ret = da8xx_register_emac(); if (ret) diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c index 4c30e92..04a8d16 100644 --- a/arch/arm/mach-davinci/board-neuros-osd2.c +++ b/arch/arm/mach-davinci/board-neuros-osd2.c @@ -39,9 +39,7 @@ #include #include -#define NEUROS_OSD2_PHY_MASK 0x2 -#define NEUROS_OSD2_MDIO_FREQUENCY 2200000 /* PHY bus frequency */ - +#define NEUROS_OSD2_PHY_ID "0:01" #define LXT971_PHY_ID 0x001378e2 #define LXT971_PHY_MASK 0xfffffff0 @@ -252,8 +250,7 @@ static __init void davinci_ntosd2_init(void) davinci_serial_init(&uart_config); dm644x_init_asp(&dm644x_ntosd2_snd_data); - soc_info->emac_pdata->phy_mask = NEUROS_OSD2_PHY_MASK; - soc_info->emac_pdata->mdio_max_freq = NEUROS_OSD2_MDIO_FREQUENCY; + soc_info->emac_pdata->phy_id = NEUROS_OSD2_PHY_ID; davinci_setup_usb(1000, 8); /* diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c index 23e664a..ab4292d 100644 --- a/arch/arm/mach-davinci/board-sffsdr.c +++ b/arch/arm/mach-davinci/board-sffsdr.c @@ -42,9 +42,7 @@ #include #include -#define SFFSDR_PHY_MASK (0x2) -#define SFFSDR_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ - +#define SFFSDR_PHY_ID "0:01" static struct mtd_partition davinci_sffsdr_nandflash_partition[] = { /* U-Boot Environment: Block 0 * UBL: Block 1 @@ -143,8 +141,7 @@ static __init void davinci_sffsdr_init(void) ARRAY_SIZE(davinci_sffsdr_devices)); sffsdr_init_i2c(); davinci_serial_init(&uart_config); - soc_info->emac_pdata->phy_mask = SFFSDR_PHY_MASK; - soc_info->emac_pdata->mdio_max_freq = SFFSDR_MDIO_FREQUENCY; + soc_info->emac_pdata->phy_id = SFFSDR_PHY_ID; davinci_setup_usb(0, 0); /* We support only peripheral mode. */ /* mux VLYNQ pins */ diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c index 9039221..9eec630 100644 --- a/arch/arm/mach-davinci/devices-da8xx.c +++ b/arch/arm/mach-davinci/devices-da8xx.c @@ -42,7 +42,6 @@ #define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000 #define DA8XX_EMAC_MOD_REG_OFFSET 0x2000 #define DA8XX_EMAC_RAM_OFFSET 0x0000 -#define DA8XX_MDIO_REG_OFFSET 0x4000 #define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K void __iomem *da8xx_syscfg0_base; @@ -381,7 +380,6 @@ struct emac_platform_data da8xx_emac_pdata = { .ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET, .ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET, .ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET, - .mdio_reg_offset = DA8XX_MDIO_REG_OFFSET, .ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE, .version = EMAC_VERSION_2, }; diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index 71f0f9d..240f392 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -691,7 +691,6 @@ static struct emac_platform_data dm365_emac_pdata = { .ctrl_reg_offset = DM365_EMAC_CNTRL_OFFSET, .ctrl_mod_reg_offset = DM365_EMAC_CNTRL_MOD_OFFSET, .ctrl_ram_offset = DM365_EMAC_CNTRL_RAM_OFFSET, - .mdio_reg_offset = DM365_EMAC_MDIO_OFFSET, .ctrl_ram_size = DM365_EMAC_CNTRL_RAM_SIZE, .version = EMAC_VERSION_2, }; diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c index c103b2c..41b7a95 100644 --- a/arch/arm/mach-davinci/dm644x.c +++ b/arch/arm/mach-davinci/dm644x.c @@ -322,7 +322,6 @@ static struct emac_platform_data dm644x_emac_pdata = { .ctrl_reg_offset = DM644X_EMAC_CNTRL_OFFSET, .ctrl_mod_reg_offset = DM644X_EMAC_CNTRL_MOD_OFFSET, .ctrl_ram_offset = DM644X_EMAC_CNTRL_RAM_OFFSET, - .mdio_reg_offset = DM644X_EMAC_MDIO_OFFSET, .ctrl_ram_size = DM644X_EMAC_CNTRL_RAM_SIZE, .version = EMAC_VERSION_1, }; diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c index 8da886b..08db90f 100644 --- a/arch/arm/mach-davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c @@ -358,7 +358,6 @@ static struct emac_platform_data dm646x_emac_pdata = { .ctrl_reg_offset = DM646X_EMAC_CNTRL_OFFSET, .ctrl_mod_reg_offset = DM646X_EMAC_CNTRL_MOD_OFFSET, .ctrl_ram_offset = DM646X_EMAC_CNTRL_RAM_OFFSET, - .mdio_reg_offset = DM646X_EMAC_MDIO_OFFSET, .ctrl_ram_size = DM646X_EMAC_CNTRL_RAM_SIZE, .version = EMAC_VERSION_2, }; diff --git a/arch/arm/mach-davinci/include/mach/dm365.h b/arch/arm/mach-davinci/include/mach/dm365.h index dbb5052..2563bf4 100644 --- a/arch/arm/mach-davinci/include/mach/dm365.h +++ b/arch/arm/mach-davinci/include/mach/dm365.h @@ -25,7 +25,6 @@ #define DM365_EMAC_CNTRL_OFFSET (0x0000) #define DM365_EMAC_CNTRL_MOD_OFFSET (0x3000) #define DM365_EMAC_CNTRL_RAM_OFFSET (0x1000) -#define DM365_EMAC_MDIO_OFFSET (0x4000) #define DM365_EMAC_CNTRL_RAM_SIZE (0x2000) /* Base of key scan register bank */ diff --git a/arch/arm/mach-davinci/include/mach/dm644x.h b/arch/arm/mach-davinci/include/mach/dm644x.h index 5159117..5a1b26d4 100644 --- a/arch/arm/mach-davinci/include/mach/dm644x.h +++ b/arch/arm/mach-davinci/include/mach/dm644x.h @@ -32,7 +32,6 @@ #define DM644X_EMAC_CNTRL_OFFSET (0x0000) #define DM644X_EMAC_CNTRL_MOD_OFFSET (0x1000) #define DM644X_EMAC_CNTRL_RAM_OFFSET (0x2000) -#define DM644X_EMAC_MDIO_OFFSET (0x4000) #define DM644X_EMAC_CNTRL_RAM_SIZE (0x2000) #define DM644X_ASYNC_EMIF_CONTROL_BASE 0x01E00000 diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h index 1c4dca9..7a27f3f 100644 --- a/arch/arm/mach-davinci/include/mach/dm646x.h +++ b/arch/arm/mach-davinci/include/mach/dm646x.h @@ -23,7 +23,6 @@ #define DM646X_EMAC_CNTRL_OFFSET (0x0000) #define DM646X_EMAC_CNTRL_MOD_OFFSET (0x1000) #define DM646X_EMAC_CNTRL_RAM_OFFSET (0x2000) -#define DM646X_EMAC_MDIO_OFFSET (0x4000) #define DM646X_EMAC_CNTRL_RAM_SIZE (0x2000) #define DM646X_ASYNC_EMIF_CONTROL_BASE 0x20008000 -- cgit v1.1 From 3b2a40a0a05cdf4f00f100c55b463d86ae14c383 Mon Sep 17 00:00:00 2001 From: Cyril Chemparathy Date: Wed, 15 Sep 2010 10:11:26 -0400 Subject: omap: cleanup unused davinci mdio arch code This patch removes davinci architecture code that has now been rendered useless by the previous patches in the MDIO separation series. Signed-off-by: Cyril Chemparathy Acked-by: David S. Miller Acked-by: Tony Lindgren Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/board-am3517evm.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index 5dd1b73..5225df6 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c @@ -39,7 +39,6 @@ #include "mux.h" -#define AM35XX_EVM_PHY_MASK (0xF) #define AM35XX_EVM_MDIO_FREQUENCY (1000000) static struct mdio_platform_data am3517_evm_mdio_pdata = { @@ -64,8 +63,6 @@ static struct platform_device am3517_mdio_device = { }; static struct emac_platform_data am3517_evm_emac_pdata = { - .phy_mask = AM35XX_EVM_PHY_MASK, - .mdio_max_freq = AM35XX_EVM_MDIO_FREQUENCY, .rmii_en = 1, }; @@ -135,7 +132,6 @@ void am3517_evm_ethernet_init(struct emac_platform_data *pdata) pdata->ctrl_reg_offset = AM35XX_EMAC_CNTRL_OFFSET; pdata->ctrl_mod_reg_offset = AM35XX_EMAC_CNTRL_MOD_OFFSET; pdata->ctrl_ram_offset = AM35XX_EMAC_CNTRL_RAM_OFFSET; - pdata->mdio_reg_offset = AM35XX_EMAC_MDIO_OFFSET; pdata->ctrl_ram_size = AM35XX_EMAC_CNTRL_RAM_SIZE; pdata->version = EMAC_VERSION_2; pdata->hw_ram_addr = AM35XX_EMAC_HW_RAM_ADDR; -- cgit v1.1 From d45b1ed4e47d2f585d2acdf5b957bfc5ff465aab Mon Sep 17 00:00:00 2001 From: Cyril Chemparathy Date: Mon, 20 Sep 2010 12:26:41 -0400 Subject: davinci: add tnetv107x keypad platform device This patch adds a platform device definition for tnetv107x's keypad controller. Signed-off-by: Cyril Chemparathy Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/devices-tnetv107x.c | 30 ++++++++++++++++++++++++++ arch/arm/mach-davinci/include/mach/tnetv107x.h | 3 +++ 2 files changed, 33 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c index 2718a3a..086269f 100644 --- a/arch/arm/mach-davinci/devices-tnetv107x.c +++ b/arch/arm/mach-davinci/devices-tnetv107x.c @@ -33,6 +33,7 @@ #define TNETV107X_WDOG_BASE 0x08086700 #define TNETV107X_SDIO0_BASE 0x08088700 #define TNETV107X_SDIO1_BASE 0x08088800 +#define TNETV107X_KEYPAD_BASE 0x08088a00 #define TNETV107X_ASYNC_EMIF_CNTRL_BASE 0x08200000 #define TNETV107X_ASYNC_EMIF_DATA_CE0_BASE 0x30000000 #define TNETV107X_ASYNC_EMIF_DATA_CE1_BASE 0x40000000 @@ -298,6 +299,30 @@ static int __init nand_init(int chipsel, struct davinci_nand_pdata *data) return platform_device_register(pdev); } +static struct resource keypad_resources[] = { + { + .start = TNETV107X_KEYPAD_BASE, + .end = TNETV107X_KEYPAD_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_TNETV107X_KEYPAD, + .flags = IORESOURCE_IRQ, + .name = "press", + }, + { + .start = IRQ_TNETV107X_KEYPAD_FREE, + .flags = IORESOURCE_IRQ, + .name = "release", + }, +}; + +static struct platform_device keypad_device = { + .name = "tnetv107x-keypad", + .num_resources = ARRAY_SIZE(keypad_resources), + .resource = keypad_resources, +}; + void __init tnetv107x_devices_init(struct tnetv107x_device_info *info) { int i; @@ -317,4 +342,9 @@ void __init tnetv107x_devices_init(struct tnetv107x_device_info *info) for (i = 0; i < 4; i++) if (info->nand_config[i]) nand_init(i, info->nand_config[i]); + + if (info->keypad_config) { + keypad_device.dev.platform_data = info->keypad_config; + platform_device_register(&keypad_device); + } } diff --git a/arch/arm/mach-davinci/include/mach/tnetv107x.h b/arch/arm/mach-davinci/include/mach/tnetv107x.h index c720647..5a681d8 100644 --- a/arch/arm/mach-davinci/include/mach/tnetv107x.h +++ b/arch/arm/mach-davinci/include/mach/tnetv107x.h @@ -33,6 +33,8 @@ #ifndef __ASSEMBLY__ #include +#include + #include #include #include @@ -41,6 +43,7 @@ struct tnetv107x_device_info { struct davinci_uart_config *serial_config; struct davinci_mmc_config *mmc_config[2]; /* 2 controllers */ struct davinci_nand_pdata *nand_config[4]; /* 4 chipsels */ + struct matrix_keypad_platform_data *keypad_config; }; extern struct platform_device tnetv107x_wdt_device; -- cgit v1.1 From a1b4440314edca8e2016f2819d4655453e6aff44 Mon Sep 17 00:00:00 2001 From: Cyril Chemparathy Date: Mon, 20 Sep 2010 12:26:42 -0400 Subject: davinci: add keypad config for tnetv107x evm board This patch adds evm board specific keymap definitions and controller configuration data for on-chip keypad controller on tnetv107x silicon. Signed-off-by: Cyril Chemparathy Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/board-tnetv107x-evm.c | 56 +++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-davinci/board-tnetv107x-evm.c b/arch/arm/mach-davinci/board-tnetv107x-evm.c index fe2a9d9..5afa8fc 100644 --- a/arch/arm/mach-davinci/board-tnetv107x-evm.c +++ b/arch/arm/mach-davinci/board-tnetv107x-evm.c @@ -23,6 +23,9 @@ #include #include #include +#include +#include + #include #include @@ -141,10 +144,63 @@ static struct davinci_uart_config serial_config __initconst = { .enabled_uarts = BIT(1), }; +static const uint32_t keymap[] = { + KEY(0, 0, KEY_NUMERIC_1), + KEY(0, 1, KEY_NUMERIC_2), + KEY(0, 2, KEY_NUMERIC_3), + KEY(0, 3, KEY_FN_F1), + KEY(0, 4, KEY_MENU), + + KEY(1, 0, KEY_NUMERIC_4), + KEY(1, 1, KEY_NUMERIC_5), + KEY(1, 2, KEY_NUMERIC_6), + KEY(1, 3, KEY_UP), + KEY(1, 4, KEY_FN_F2), + + KEY(2, 0, KEY_NUMERIC_7), + KEY(2, 1, KEY_NUMERIC_8), + KEY(2, 2, KEY_NUMERIC_9), + KEY(2, 3, KEY_LEFT), + KEY(2, 4, KEY_ENTER), + + KEY(3, 0, KEY_NUMERIC_STAR), + KEY(3, 1, KEY_NUMERIC_0), + KEY(3, 2, KEY_NUMERIC_POUND), + KEY(3, 3, KEY_DOWN), + KEY(3, 4, KEY_RIGHT), + + KEY(4, 0, KEY_FN_F3), + KEY(4, 1, KEY_FN_F4), + KEY(4, 2, KEY_MUTE), + KEY(4, 3, KEY_HOME), + KEY(4, 4, KEY_BACK), + + KEY(5, 0, KEY_VOLUMEDOWN), + KEY(5, 1, KEY_VOLUMEUP), + KEY(5, 2, KEY_F1), + KEY(5, 3, KEY_F2), + KEY(5, 4, KEY_F3), +}; + +static const struct matrix_keymap_data keymap_data = { + .keymap = keymap, + .keymap_size = ARRAY_SIZE(keymap), +}; + +static struct matrix_keypad_platform_data keypad_config = { + .keymap_data = &keymap_data, + .num_row_gpios = 6, + .num_col_gpios = 5, + .debounce_ms = 0, /* minimum */ + .active_low = 0, /* pull up realization */ + .no_autorepeat = 0, +}; + static struct tnetv107x_device_info evm_device_info __initconst = { .serial_config = &serial_config, .mmc_config[1] = &mmc_config, /* controller 1 */ .nand_config[0] = &nand_config, /* chip select 0 */ + .keypad_config = &keypad_config, }; static __init void tnetv107x_evm_board_init(void) -- cgit v1.1 From 1f4640ae7c299ce87968cb3923c5f85254d68c37 Mon Sep 17 00:00:00 2001 From: Cyril Chemparathy Date: Mon, 20 Sep 2010 12:26:44 -0400 Subject: davinci: add tnetv107x touchscreen platform device This patch adds a platform device definition for tnetv107x's touchscreen controller. Signed-off-by: Cyril Chemparathy Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/devices-tnetv107x.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c index 086269f..c9a86d8 100644 --- a/arch/arm/mach-davinci/devices-tnetv107x.c +++ b/arch/arm/mach-davinci/devices-tnetv107x.c @@ -31,6 +31,7 @@ #define TNETV107X_TPTC0_BASE 0x01c10000 #define TNETV107X_TPTC1_BASE 0x01c10400 #define TNETV107X_WDOG_BASE 0x08086700 +#define TNETV107X_TSC_BASE 0x08088500 #define TNETV107X_SDIO0_BASE 0x08088700 #define TNETV107X_SDIO1_BASE 0x08088800 #define TNETV107X_KEYPAD_BASE 0x08088a00 @@ -323,12 +324,31 @@ static struct platform_device keypad_device = { .resource = keypad_resources, }; +static struct resource tsc_resources[] = { + { + .start = TNETV107X_TSC_BASE, + .end = TNETV107X_TSC_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_TNETV107X_TSC, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device tsc_device = { + .name = "tnetv107x-ts", + .num_resources = ARRAY_SIZE(tsc_resources), + .resource = tsc_resources, +}; + void __init tnetv107x_devices_init(struct tnetv107x_device_info *info) { int i; platform_device_register(&edma_device); platform_device_register(&tnetv107x_wdt_device); + platform_device_register(&tsc_device); if (info->serial_config) davinci_serial_init(info->serial_config); -- cgit v1.1 From 2a7dae04f3a5966ade5086ebd2e09f170fd0e085 Mon Sep 17 00:00:00 2001 From: Michael Williamson Date: Fri, 17 Sep 2010 09:56:06 -0400 Subject: davinci: MityDSP-L138/MityARM-1808 read MAC address from I2C Prom For the MityDSP-L138/MityARM-1808 SOMS, read the factory assigned MAC address from the onboard I2C EPROM and assign it to the emac device during platform initialization. Signed-off-by: Michael Williamson Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/board-mityomapl138.c | 62 ++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c index 6f12a18..65f7501 100644 --- a/arch/arm/mach-davinci/board-mityomapl138.c +++ b/arch/arm/mach-davinci/board-mityomapl138.c @@ -15,6 +15,8 @@ #include #include #include +#include +#include #include #include @@ -25,6 +27,65 @@ #include #define MITYOMAPL138_PHY_ID "0:03" + +#define FACTORY_CONFIG_MAGIC 0x012C0138 +#define FACTORY_CONFIG_VERSION 0x00010001 + +/* Data Held in On-Board I2C device */ +struct factory_config { + u32 magic; + u32 version; + u8 mac[6]; + u32 fpga_type; + u32 spare; + u32 serialnumber; + char partnum[32]; +}; + +static struct factory_config factory_config; + +static void read_factory_config(struct memory_accessor *a, void *context) +{ + int ret; + struct davinci_soc_info *soc_info = &davinci_soc_info; + + ret = a->read(a, (char *)&factory_config, 0, sizeof(factory_config)); + if (ret != sizeof(struct factory_config)) { + pr_warning("MityOMAPL138: Read Factory Config Failed: %d\n", + ret); + return; + } + + if (factory_config.magic != FACTORY_CONFIG_MAGIC) { + pr_warning("MityOMAPL138: Factory Config Magic Wrong (%X)\n", + factory_config.magic); + return; + } + + if (factory_config.version != FACTORY_CONFIG_VERSION) { + pr_warning("MityOMAPL138: Factory Config Version Wrong (%X)\n", + factory_config.version); + return; + } + + pr_info("MityOMAPL138: Found MAC = %pM\n", factory_config.mac); + pr_info("MityOMAPL138: Part Number = %s\n", factory_config.partnum); + if (is_valid_ether_addr(factory_config.mac)) + memcpy(soc_info->emac_pdata->mac_addr, + factory_config.mac, ETH_ALEN); + else + pr_warning("MityOMAPL138: Invalid MAC found " + "in factory config block\n"); +} + +static struct at24_platform_data mityomapl138_fd_chip = { + .byte_len = 256, + .page_size = 8, + .flags = AT24_FLAG_READONLY | AT24_FLAG_IRUGO, + .setup = read_factory_config, + .context = NULL, +}; + static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = { .bus_freq = 100, /* kHz */ .bus_delay = 0, /* usec */ @@ -151,6 +212,7 @@ static struct i2c_board_info __initdata mityomap_tps65023_info[] = { }, { I2C_BOARD_INFO("24c02", 0x50), + .platform_data = &mityomapl138_fd_chip, }, }; -- cgit v1.1 From 6c18c91b3a6db6169998b54df12c9d53e74999f3 Mon Sep 17 00:00:00 2001 From: Victor Rodriguez Date: Thu, 23 Sep 2010 11:28:40 -0500 Subject: davinci: Initial support for Omapl138-Hawkboard This patch adds initial support for the Hawkboard-L138 system It is under the machine name "omapl138_hawkboard". This system is based on the da850 davinci CPU architecture. Information on these system may be found at http://www.hawkboard.org. Basic support for the UART console is included in this patch. It's tested with latest Angstrom File Systems like ramdisk from http://alturl.com/imb45. Signed-off-by: Victor Rodriguez Signed-off-by: Kevin Hilman --- arch/arm/configs/da8xx_omapl_defconfig | 1 + arch/arm/mach-davinci/Kconfig | 8 ++++ arch/arm/mach-davinci/Makefile | 1 + arch/arm/mach-davinci/board-omapl138-hawk.c | 64 +++++++++++++++++++++++++ arch/arm/mach-davinci/include/mach/uncompress.h | 1 + 5 files changed, 75 insertions(+) create mode 100644 arch/arm/mach-davinci/board-omapl138-hawk.c (limited to 'arch') diff --git a/arch/arm/configs/da8xx_omapl_defconfig b/arch/arm/configs/da8xx_omapl_defconfig index f8a47ee..cdc40c4 100644 --- a/arch/arm/configs/da8xx_omapl_defconfig +++ b/arch/arm/configs/da8xx_omapl_defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_DAVINCI=y CONFIG_ARCH_DAVINCI_DA830=y CONFIG_ARCH_DAVINCI_DA850=y CONFIG_MACH_MITYOMAPL138=y +CONFIG_MACH_OMAPL138_HAWKBOARD=y CONFIG_DAVINCI_RESET_CLOCKS=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 9aca60c..b77b860 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -193,6 +193,14 @@ config MACH_MITYOMAPL138 System on Module. Information on this SoM may be found at http://www.mitydsp.com +config MACH_OMAPL138_HAWKBOARD + bool "TI AM1808 / OMAPL-138 Hawkboard platform" + depends on ARCH_DAVINCI_DA850 + help + Say Y here to select the TI AM1808 / OMAPL-138 Hawkboard platform . + Information of this board may be found at + http://www.hawkboard.org/ + config DAVINCI_MUX bool "DAVINCI multiplexing support" depends on ARCH_DAVINCI diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index a7a70d1..0b87a1c 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += board-da830-evm.o obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += board-da850-evm.o obj-$(CONFIG_MACH_TNETV107X) += board-tnetv107x-evm.o obj-$(CONFIG_MACH_MITYOMAPL138) += board-mityomapl138.o +obj-$(CONFIG_MACH_OMAPL138_HAWKBOARD) += board-omapl138-hawk.o # Power Management obj-$(CONFIG_CPU_FREQ) += cpufreq.o diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c new file mode 100644 index 0000000..c472dd8 --- /dev/null +++ b/arch/arm/mach-davinci/board-omapl138-hawk.c @@ -0,0 +1,64 @@ +/* + * Hawkboard.org based on TI's OMAP-L138 Platform + * + * Initial code: Syed Mohammed Khasim + * + * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of + * any kind, whether express or implied. + */ +#include +#include +#include +#include + +#include +#include + +#include +#include + +static struct davinci_uart_config omapl138_hawk_uart_config __initdata = { + .enabled_uarts = 0x7, +}; + +static __init void omapl138_hawk_init(void) +{ + int ret; + + davinci_serial_init(&omapl138_hawk_uart_config); + + ret = da8xx_register_watchdog(); + if (ret) + pr_warning("omapl138_hawk_init: " + "watchdog registration failed: %d\n", + ret); +} + +#ifdef CONFIG_SERIAL_8250_CONSOLE +static int __init omapl138_hawk_console_init(void) +{ + if (!machine_is_omapl138_hawkboard()) + return 0; + + return add_preferred_console("ttyS", 2, "115200"); +} +console_initcall(omapl138_hawk_console_init); +#endif + +static void __init omapl138_hawk_map_io(void) +{ + da850_init(); +} + +MACHINE_START(OMAPL138_HAWKBOARD, "AM18x/OMAP-L138 Hawkboard") + .phys_io = IO_PHYS, + .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, + .boot_params = (DA8XX_DDR_BASE + 0x100), + .map_io = omapl138_hawk_map_io, + .init_irq = cp_intc_init, + .timer = &davinci_timer, + .init_machine = omapl138_hawk_init, +MACHINE_END diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h index d370391..47723e8 100644 --- a/arch/arm/mach-davinci/include/mach/uncompress.h +++ b/arch/arm/mach-davinci/include/mach/uncompress.h @@ -89,6 +89,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id) DEBUG_LL_DA8XX(davinci_da830_evm, 2); DEBUG_LL_DA8XX(davinci_da850_evm, 2); DEBUG_LL_DA8XX(mityomapl138, 1); + DEBUG_LL_DA8XX(omapl138_hawkboard, 2); /* TNETV107x boards */ DEBUG_LL_TNETV107X(tnetv107x, 1); -- cgit v1.1 From f39f4898ac72fec92066f15aef0e7485013482ea Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Fri, 24 Sep 2010 10:23:18 -0600 Subject: OMAP: omap_device: Fix to support multiple hwmods for a single device Currently there is a bug in the existing omap_device core code when extracting the hwmod structures passed to omap_device_build_ss(). This bug gets exposed only when passing multiple hwmod structures to omap_device_build_ss() resulting in incorrect extraction from second hwmod structure. This fix uses the pointer to pointer to omap_hwmod structure (array of pointers to omap_hwmod structure) passed to omap_device_build_ss() to correctly extract the appropriate omap_hwmod structure. This patch has been created and tested on lo/master and mainline. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Paul Walmsley Acked-by: Benoit Cousson Acked-by: Kevin Hilman Cc: Charulatha V Cc: Shubhrajyoti D --- arch/arm/plat-omap/omap_device.c | 35 ++++++++++++++--------------------- 1 file changed, 14 insertions(+), 21 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c index ceba58a..533ad13 100644 --- a/arch/arm/plat-omap/omap_device.c +++ b/arch/arm/plat-omap/omap_device.c @@ -296,12 +296,11 @@ static void _add_optional_clock_alias(struct omap_device *od, */ int omap_device_count_resources(struct omap_device *od) { - struct omap_hwmod *oh; int c = 0; int i; - for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) - c += omap_hwmod_count_resources(oh); + for (i = 0; i < od->hwmods_cnt; i++) + c += omap_hwmod_count_resources(od->hwmods[i]); pr_debug("omap_device: %s: counted %d total resources across %d " "hwmods\n", od->pdev.name, c, od->hwmods_cnt); @@ -328,12 +327,11 @@ int omap_device_count_resources(struct omap_device *od) */ int omap_device_fill_resources(struct omap_device *od, struct resource *res) { - struct omap_hwmod *oh; int c = 0; int i, r; - for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) { - r = omap_hwmod_fill_resources(oh, res); + for (i = 0; i < od->hwmods_cnt; i++) { + r = omap_hwmod_fill_resources(od->hwmods[i], res); res += r; c += r; } @@ -607,7 +605,6 @@ int omap_device_shutdown(struct platform_device *pdev) { int ret, i; struct omap_device *od; - struct omap_hwmod *oh; od = _find_by_pdev(pdev); @@ -620,8 +617,8 @@ int omap_device_shutdown(struct platform_device *pdev) ret = _omap_device_deactivate(od, IGNORE_WAKEUP_LAT); - for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) - omap_hwmod_shutdown(oh); + for (i = 0; i < od->hwmods_cnt; i++) + omap_hwmod_shutdown(od->hwmods[i]); od->_state = OMAP_DEVICE_STATE_SHUTDOWN; @@ -733,11 +730,10 @@ void __iomem *omap_device_get_rt_va(struct omap_device *od) */ int omap_device_enable_hwmods(struct omap_device *od) { - struct omap_hwmod *oh; int i; - for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) - omap_hwmod_enable(oh); + for (i = 0; i < od->hwmods_cnt; i++) + omap_hwmod_enable(od->hwmods[i]); /* XXX pass along return value here? */ return 0; @@ -751,11 +747,10 @@ int omap_device_enable_hwmods(struct omap_device *od) */ int omap_device_idle_hwmods(struct omap_device *od) { - struct omap_hwmod *oh; int i; - for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) - omap_hwmod_idle(oh); + for (i = 0; i < od->hwmods_cnt; i++) + omap_hwmod_idle(od->hwmods[i]); /* XXX pass along return value here? */ return 0; @@ -770,11 +765,10 @@ int omap_device_idle_hwmods(struct omap_device *od) */ int omap_device_disable_clocks(struct omap_device *od) { - struct omap_hwmod *oh; int i; - for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) - omap_hwmod_disable_clocks(oh); + for (i = 0; i < od->hwmods_cnt; i++) + omap_hwmod_disable_clocks(od->hwmods[i]); /* XXX pass along return value here? */ return 0; @@ -789,11 +783,10 @@ int omap_device_disable_clocks(struct omap_device *od) */ int omap_device_enable_clocks(struct omap_device *od) { - struct omap_hwmod *oh; int i; - for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) - omap_hwmod_enable_clocks(oh); + for (i = 0; i < od->hwmods_cnt; i++) + omap_hwmod_enable_clocks(od->hwmods[i]); /* XXX pass along return value here? */ return 0; -- cgit v1.1 From ff173d45525701d65d394cb8687e71845bfb34dc Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Fri, 24 Sep 2010 10:23:18 -0600 Subject: OMAP4: PM: Declare idle modules as functional too The omap4_cm_wait_module_ready function would only check for the modules to be completely functional before declaring them ready to be accessed. There might also be instances where in the module is actually in idle (under h/w control) but should still be declared accessible, as the h/w control would make it functional when needed. Hence make omap4_cm_wait_module_ready return true in case the module is fully functional *or* in idle state. Fail only if the module is fully disabled or stuck intransition. The explaination from the TRM for the idlest bits on OMAP4 is as below for quick reference Module idle state: 0x0 func: Module is fully functional, including OCP 0x1 trans: Module is performing transition: wakeup, or sleep, or sleep abortion 0x2 idle: Module is in Idle mode (only OCP part). It is functional if using separate functional clock 0x3 disabled: Module is disabled and cannot be accessed Signed-off-by: Rajendra Nayak Signed-off-by: Partha Basak Signed-off-by: Benoit Cousson Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/cm4xxx.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/cm4xxx.c b/arch/arm/mach-omap2/cm4xxx.c index b101091..f8a660a 100644 --- a/arch/arm/mach-omap2/cm4xxx.c +++ b/arch/arm/mach-omap2/cm4xxx.c @@ -43,7 +43,6 @@ * using separate functional clock * 0x3 disabled: Module is disabled and cannot be accessed * - * TODO: Need to handle module accessible in idle state */ int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg) { @@ -52,9 +51,11 @@ int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg) if (!clkctrl_reg) return 0; - omap_test_timeout(((__raw_readl(clkctrl_reg) & - OMAP4430_IDLEST_MASK) == 0), - MAX_MODULE_READY_TIME, i); + omap_test_timeout(( + ((__raw_readl(clkctrl_reg) & OMAP4430_IDLEST_MASK) == 0) || + (((__raw_readl(clkctrl_reg) & OMAP4430_IDLEST_MASK) >> + OMAP4430_IDLEST_SHIFT) == 0x2)), + MAX_MODULE_READY_TIME, i); return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; } -- cgit v1.1 From 78f26e872f77b6312273216de1a8f836c6f2e143 Mon Sep 17 00:00:00 2001 From: Hema HK Date: Fri, 24 Sep 2010 10:23:19 -0600 Subject: OMAP: hwmod: Set autoidle after smartidle during _sysc_enable OMAP USBOTG module has a requirement to set the autoidle bit only after setting smartidle bit. Modified the _sys_enable api to set the smartidle first and then the autoidle bit. Setting this will not have any impact on the other modules. Signed-off-by: Hema HK Signed-off-by: Partha Basak Cc: Felipe Balbi Cc: Tony Lindgren Cc: Kevin Hilman Acked-by: Benoit Cousson Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/omap_hwmod.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index c3a5889..955861a 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -777,12 +777,6 @@ static void _enable_sysc(struct omap_hwmod *oh) _set_master_standbymode(oh, idlemode, &v); } - if (sf & SYSC_HAS_AUTOIDLE) { - idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ? - 0 : 1; - _set_module_autoidle(oh, idlemode, &v); - } - /* * XXX The clock framework should handle this, by * calling into this code. But this must wait until the @@ -797,6 +791,17 @@ static void _enable_sysc(struct omap_hwmod *oh) /* If slave is in SMARTIDLE, also enable wakeup */ if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE)) _enable_wakeup(oh); + + /* + * Set the autoidle bit only after setting the smartidle bit + * Setting this will not have any impact on the other modules. + */ + if (sf & SYSC_HAS_AUTOIDLE) { + idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ? + 0 : 1; + _set_module_autoidle(oh, idlemode, &v); + _write_sysconfig(v, oh); + } } /** -- cgit v1.1 From 2c8e992716b3adff52846e2280731b533db592ff Mon Sep 17 00:00:00 2001 From: Jarkko Nikula Date: Thu, 23 Sep 2010 19:11:53 +0300 Subject: omap: zoom2: Fix ASoC multi-component build breakage by removing dead code ASoC Multi-Component Support patch removes #if 0 in board-zoom2.c that was used to protect some uncompiling dead code. Remove that code as it seems to be here quite some time since commit 479f12c. Signed-off-by: Jarkko Nikula Cc: Vikram Pandita Cc: Tony Lindgren Tested-by: Misael Lopez Cruz Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- arch/arm/mach-omap2/board-zoom2.c | 12 ------------ 1 file changed, 12 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-zoom2.c b/arch/arm/mach-omap2/board-zoom2.c index efbcd8f..86d4515 100644 --- a/arch/arm/mach-omap2/board-zoom2.c +++ b/arch/arm/mach-omap2/board-zoom2.c @@ -41,10 +41,6 @@ void zoom2_set_hs_extmute(int mute) gpio_set_value(ZOOM2_HEADSET_EXTMUTE_GPIO, mute); } -static struct twl4030_madc_platform_data zoom2_madc_data = { - .irq_line = 1, -}; - static struct twl4030_codec_audio_data zoom2_audio_data = { .audio_mclk = 26000000, .ramp_delay_value = 3, /* 161 ms */ @@ -62,15 +58,7 @@ static struct twl4030_platform_data zoom2_twldata = { .irq_end = TWL4030_IRQ_END, /* platform_data for children goes here */ - .bci = &zoom2_bci_data, - .madc = &zoom2_madc_data, - .usb = &zoom2_usb_data, - .gpio = &zoom2_gpio_data, - .keypad = &zoom2_kp_twl4030_data, .codec = &zoom2_codec_data, - .vmmc1 = &zoom2_vmmc1, - .vmmc2 = &zoom2_vmmc2, - .vsim = &zoom2_vsim, }; static struct i2c_board_info __initdata zoom2_i2c_boardinfo[] = { -- cgit v1.1 From 4b285c3f3f0082f7fb765050f07a864474459bf0 Mon Sep 17 00:00:00 2001 From: Jarkko Nikula Date: Thu, 23 Sep 2010 19:11:54 +0300 Subject: omap: zoom: Move new code introduced by ASoC m-c to board-zoom-peripherals ASoC Multi-Component Support moves some code from sound/soc/omap/zoom2.c into arch/arm/mach-omap2/board-zoom2.c. However, that code should go to board-zoom-peripherals.c instead as there is common code and registration for zoom boards. Signed-off-by: Jarkko Nikula Cc: Vikram Pandita Cc: Lopez Cruz, Misael Cc: Jorge Eduardo Candelaria Cc: Tony Lindgren Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- arch/arm/mach-omap2/board-zoom-peripherals.c | 12 ++++++++ arch/arm/mach-omap2/board-zoom2.c | 44 ---------------------------- 2 files changed, 12 insertions(+), 44 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c index 6b39849..3c65304 100644 --- a/arch/arm/mach-omap2/board-zoom-peripherals.c +++ b/arch/arm/mach-omap2/board-zoom-peripherals.c @@ -24,6 +24,8 @@ #include #include +#include + #include "mux.h" #include "hsmmc.h" @@ -188,6 +190,11 @@ static int zoom_twl_gpio_setup(struct device *dev, return 0; } +/* EXTMUTE callback function */ +void zoom2_set_hs_extmute(int mute) +{ + gpio_set_value(ZOOM2_HEADSET_EXTMUTE_GPIO, mute); +} static int zoom_batt_table[] = { /* 0 C*/ @@ -257,6 +264,11 @@ static struct i2c_board_info __initdata zoom_i2c_boardinfo[] = { static int __init omap_i2c_init(void) { + if (machine_is_omap_zoom2()) { + zoom_audio_data.ramp_delay_value = 3; /* 161 ms */ + zoom_audio_data.hs_extmute = 1; + zoom_audio_data.set_hs_extmute = zoom2_set_hs_extmute; + } omap_register_i2c_bus(1, 2400, zoom_i2c_boardinfo, ARRAY_SIZE(zoom_i2c_boardinfo)); omap_register_i2c_bus(2, 400, NULL, 0); diff --git a/arch/arm/mach-omap2/board-zoom2.c b/arch/arm/mach-omap2/board-zoom2.c index 86d4515..00c8f835 100644 --- a/arch/arm/mach-omap2/board-zoom2.c +++ b/arch/arm/mach-omap2/board-zoom2.c @@ -35,49 +35,6 @@ static void __init omap_zoom2_init_irq(void) omap_gpio_init(); } -/* EXTMUTE callback function */ -void zoom2_set_hs_extmute(int mute) -{ - gpio_set_value(ZOOM2_HEADSET_EXTMUTE_GPIO, mute); -} - -static struct twl4030_codec_audio_data zoom2_audio_data = { - .audio_mclk = 26000000, - .ramp_delay_value = 3, /* 161 ms */ - .hs_extmute = 1, - .set_hs_extmute = zoom2_set_hs_extmute, -}; - -static struct twl4030_codec_data zoom2_codec_data = { - .audio_mclk = 26000000, - .audio = &zoom2_audio_data, -}; - -static struct twl4030_platform_data zoom2_twldata = { - .irq_base = TWL4030_IRQ_BASE, - .irq_end = TWL4030_IRQ_END, - - /* platform_data for children goes here */ - .codec = &zoom2_codec_data, -}; - -static struct i2c_board_info __initdata zoom2_i2c_boardinfo[] = { - { - I2C_BOARD_INFO("twl4030", 0x48), - .flags = I2C_CLIENT_WAKE, - .irq = INT_34XX_SYS_NIRQ, - .platform_data = &zoom2_twldata, - }, -}; - -static int __init omap3_zoom2_i2c_init(void) -{ - omap_register_i2c_bus(1, 2600, zoom2_i2c_boardinfo, - ARRAY_SIZE(zoom2_i2c_boardinfo)); - return 0; -} - - #ifdef CONFIG_OMAP_MUX static struct omap_board_mux board_mux[] __initdata = { /* WLAN IRQ - GPIO 162 */ @@ -144,7 +101,6 @@ static void __init omap_zoom2_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); zoom_peripherals_init(); - omap3_zoom2_i2c_init(); board_nand_init(zoom_nand_partitions, ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS); zoom_debugboard_init(); -- cgit v1.1 From 94ce7a6628ccaa71f0a5f26f6ff7dc7b0f0f65b7 Mon Sep 17 00:00:00 2001 From: Shubhrajyoti Datta Date: Thu, 23 Sep 2010 18:22:49 -0700 Subject: omap: 4430sdp board support for proximity sensor omap 4430sdp board support for the proximity sensor via GPIO keys. The proximity sensor is connected to GPIO and is registered as a GPIO key. - Making the default state of the sensor off at bootup - The init is called before platform_add_devices Signed-off-by: Shubhrajyoti D Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-4430sdp.c | 61 +++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index 5b6a48d..d2b9173 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include @@ -40,6 +41,8 @@ #define ETH_KS8851_IRQ 34 #define ETH_KS8851_POWER_ON 48 #define ETH_KS8851_QUART 138 +#define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO 184 +#define OMAP4_SFH7741_ENABLE_GPIO 188 static struct gpio_led sdp4430_gpio_leds[] = { { @@ -77,11 +80,47 @@ static struct gpio_led sdp4430_gpio_leds[] = { }; +static struct gpio_keys_button sdp4430_gpio_keys[] = { + { + .desc = "Proximity Sensor", + .type = EV_SW, + .code = SW_FRONT_PROXIMITY, + .gpio = OMAP4_SFH7741_SENSOR_OUTPUT_GPIO, + .active_low = 0, + } +}; + static struct gpio_led_platform_data sdp4430_led_data = { .leds = sdp4430_gpio_leds, .num_leds = ARRAY_SIZE(sdp4430_gpio_leds), }; +static int omap_prox_activate(struct device *dev) +{ + gpio_set_value(OMAP4_SFH7741_ENABLE_GPIO , 1); + return 0; +} + +static void omap_prox_deactivate(struct device *dev) +{ + gpio_set_value(OMAP4_SFH7741_ENABLE_GPIO , 0); +} + +static struct gpio_keys_platform_data sdp4430_gpio_keys_data = { + .buttons = sdp4430_gpio_keys, + .nbuttons = ARRAY_SIZE(sdp4430_gpio_keys), + .enable = omap_prox_activate, + .disable = omap_prox_deactivate, +}; + +static struct platform_device sdp4430_gpio_keys_device = { + .name = "gpio-keys", + .id = -1, + .dev = { + .platform_data = &sdp4430_gpio_keys_data, + }, +}; + static struct platform_device sdp4430_leds_gpio = { .name = "leds-gpio", .id = -1, @@ -161,6 +200,7 @@ static struct platform_device sdp4430_lcd_device = { static struct platform_device *sdp4430_devices[] __initdata = { &sdp4430_lcd_device, + &sdp4430_gpio_keys_device, &sdp4430_leds_gpio, }; @@ -432,11 +472,32 @@ static int __init omap4_i2c_init(void) ARRAY_SIZE(sdp4430_i2c_4_boardinfo)); return 0; } + +static void __init omap_sfh7741prox_init(void) +{ + int error; + + error = gpio_request(OMAP4_SFH7741_ENABLE_GPIO, "sfh7741"); + if (error < 0) { + pr_err("%s:failed to request GPIO %d, error %d\n", + __func__, OMAP4_SFH7741_ENABLE_GPIO, error); + return; + } + + error = gpio_direction_output(OMAP4_SFH7741_ENABLE_GPIO , 0); + if (error < 0) { + pr_err("%s: GPIO configuration failed: GPIO %d,error %d\n", + __func__, OMAP4_SFH7741_ENABLE_GPIO, error); + gpio_free(OMAP4_SFH7741_ENABLE_GPIO); + } +} + static void __init omap_4430sdp_init(void) { int status; omap4_i2c_init(); + omap_sfh7741prox_init(); platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices)); omap_serial_init(); omap4_twl6030_hsmmc_init(mmc); -- cgit v1.1 From 3da434acd4f7c7f5aeebd44fed42bf5ed9adfc44 Mon Sep 17 00:00:00 2001 From: Ricardo Salveti de Araujo Date: Thu, 23 Sep 2010 18:22:49 -0700 Subject: omap4: board-omap4panda: adding leds status1 and status2 At Pandaboard we have 2 status leds, so adding them with similar usage as we have for Beagleboard (heartbeat and mmc0). The patch basically adds the platform data required by leds-gpio driver. Signed-off-by: Ricardo Salveti de Araujo Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-omap4panda.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index c03d1d5..22a8fd3 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -40,6 +41,36 @@ #include "hsmmc.h" +static struct gpio_led gpio_leds[] = { + { + .name = "pandaboard::status1", + .default_trigger = "heartbeat", + .gpio = 7, + }, + { + .name = "pandaboard::status2", + .default_trigger = "mmc0", + .gpio = 8, + }, +}; + +static struct gpio_led_platform_data gpio_led_info = { + .leds = gpio_leds, + .num_leds = ARRAY_SIZE(gpio_leds), +}; + +static struct platform_device leds_gpio = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &gpio_led_info, + }, +}; + +static struct platform_device *panda_devices[] __initdata = { + &leds_gpio, +}; + static void __init omap4_panda_init_irq(void) { omap2_init_common_hw(NULL, NULL); @@ -277,6 +308,7 @@ static void __init omap4_panda_init(void) int status; omap4_panda_i2c_init(); + platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices)); omap_serial_init(); omap4_twl6030_hsmmc_init(mmc); /* OMAP4 Panda uses internal transceiver so register nop transceiver */ -- cgit v1.1 From 14477095abc661a9f195ca4733bb739c54794b32 Mon Sep 17 00:00:00 2001 From: Vasily Khoruzhick Date: Wed, 8 Sep 2010 12:39:46 +0300 Subject: ARM: h1940: Use gpiolib for latch access This patch adds gpiolib support for h1940 latch. With this patch it's possible to use leds-gpio and uda1380 drivers (they require gpiolib support for appropriate pins). And now it's possible to drop leds-h1940 driver. Signed-off-by: Vasily Khoruzhick Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2410/h1940-bluetooth.c | 13 +++-- arch/arm/mach-s3c2410/include/mach/h1940-latch.h | 57 +++++++-------------- arch/arm/mach-s3c2410/mach-h1940.c | 64 +++++++++++++++++++++--- arch/arm/plat-s3c24xx/Kconfig | 1 + 4 files changed, 87 insertions(+), 48 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-s3c2410/h1940-bluetooth.c b/arch/arm/mach-s3c2410/h1940-bluetooth.c index 8cdeb14..8aa2f19 100644 --- a/arch/arm/mach-s3c2410/h1940-bluetooth.c +++ b/arch/arm/mach-s3c2410/h1940-bluetooth.c @@ -30,7 +30,7 @@ static void h1940bt_enable(int on) { if (on) { /* Power on the chip */ - h1940_latch_control(0, H1940_LATCH_BLUETOOTH_POWER); + gpio_set_value(H1940_LATCH_BLUETOOTH_POWER, 1); /* Reset the chip */ mdelay(10); @@ -43,7 +43,7 @@ static void h1940bt_enable(int on) mdelay(10); gpio_set_value(S3C2410_GPH(1), 0); mdelay(10); - h1940_latch_control(H1940_LATCH_BLUETOOTH_POWER, 0); + gpio_set_value(H1940_LATCH_BLUETOOTH_POWER, 0); } } @@ -64,7 +64,14 @@ static int __devinit h1940bt_probe(struct platform_device *pdev) ret = gpio_request(S3C2410_GPH(1), dev_name(&pdev->dev)); if (ret) { - dev_err(&pdev->dev, "could not get GPH1\n");\ + dev_err(&pdev->dev, "could not get GPH1\n"); + return ret; + } + + ret = gpio_request(H1940_LATCH_BLUETOOTH_POWER, dev_name(&pdev->dev)); + if (ret) { + gpio_free(S3C2410_GPH(1)); + dev_err(&pdev->dev, "could not get BT_POWER\n"); return ret; } diff --git a/arch/arm/mach-s3c2410/include/mach/h1940-latch.h b/arch/arm/mach-s3c2410/include/mach/h1940-latch.h index d8a8327..73586f2 100644 --- a/arch/arm/mach-s3c2410/include/mach/h1940-latch.h +++ b/arch/arm/mach-s3c2410/include/mach/h1940-latch.h @@ -14,51 +14,30 @@ #ifndef __ASM_ARCH_H1940_LATCH_H #define __ASM_ARCH_H1940_LATCH_H +#include -#ifndef __ASSEMBLY__ -#define H1940_LATCH ((void __force __iomem *)0xF8000000) -#else -#define H1940_LATCH 0xF8000000 -#endif - -#define H1940_PA_LATCH (S3C2410_CS2) +#define H1940_LATCH_GPIO(x) (S3C_GPIO_END + (x)) /* SD layer latch */ -#define H1940_LATCH_SDQ1 (1<<16) -#define H1940_LATCH_LCD_P1 (1<<17) -#define H1940_LATCH_LCD_P2 (1<<18) -#define H1940_LATCH_LCD_P3 (1<<19) -#define H1940_LATCH_MAX1698_nSHUTDOWN (1<<20) /* LCD backlight */ -#define H1940_LATCH_LED_RED (1<<21) -#define H1940_LATCH_SDQ7 (1<<22) -#define H1940_LATCH_USB_DP (1<<23) +#define H1940_LATCH_SDQ1 H1940_LATCH_GPIO(0) +#define H1940_LATCH_LCD_P1 H1940_LATCH_GPIO(1) +#define H1940_LATCH_LCD_P2 H1940_LATCH_GPIO(2) +#define H1940_LATCH_LCD_P3 H1940_LATCH_GPIO(3) +#define H1940_LATCH_MAX1698_nSHUTDOWN H1940_LATCH_GPIO(4) +#define H1940_LATCH_LED_RED H1940_LATCH_GPIO(5) +#define H1940_LATCH_SDQ7 H1940_LATCH_GPIO(6) +#define H1940_LATCH_USB_DP H1940_LATCH_GPIO(7) /* CPU layer latch */ -#define H1940_LATCH_UDA_POWER (1<<24) -#define H1940_LATCH_AUDIO_POWER (1<<25) -#define H1940_LATCH_SM803_ENABLE (1<<26) -#define H1940_LATCH_LCD_P4 (1<<27) -#define H1940_LATCH_CPUQ5 (1<<28) /* untraced */ -#define H1940_LATCH_BLUETOOTH_POWER (1<<29) /* active high */ -#define H1940_LATCH_LED_GREEN (1<<30) -#define H1940_LATCH_LED_FLASH (1<<31) - -/* default settings */ - -#define H1940_LATCH_DEFAULT \ - H1940_LATCH_LCD_P4 | \ - H1940_LATCH_SM803_ENABLE | \ - H1940_LATCH_SDQ1 | \ - H1940_LATCH_LCD_P1 | \ - H1940_LATCH_LCD_P2 | \ - H1940_LATCH_LCD_P3 | \ - H1940_LATCH_MAX1698_nSHUTDOWN | \ - H1940_LATCH_CPUQ5 - -/* control functions */ - -extern void h1940_latch_control(unsigned int clear, unsigned int set); +#define H1940_LATCH_UDA_POWER H1940_LATCH_GPIO(8) +#define H1940_LATCH_AUDIO_POWER H1940_LATCH_GPIO(9) +#define H1940_LATCH_SM803_ENABLE H1940_LATCH_GPIO(10) +#define H1940_LATCH_LCD_P4 H1940_LATCH_GPIO(11) +#define H1940_LATCH_CPUQ5 H1940_LATCH_GPIO(12) +#define H1940_LATCH_BLUETOOTH_POWER H1940_LATCH_GPIO(13) +#define H1940_LATCH_LED_GREEN H1940_LATCH_GPIO(14) +#define H1940_LATCH_LED_FLASH H1940_LATCH_GPIO(15) #endif /* __ASM_ARCH_H1940_LATCH_H */ diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c index 3ba3bab..f0493bd 100644 --- a/arch/arm/mach-s3c2410/mach-h1940.c +++ b/arch/arm/mach-s3c2410/mach-h1940.c @@ -59,6 +59,12 @@ #include #include +#define H1940_LATCH ((void __force __iomem *)0xF8000000) + +#define H1940_PA_LATCH S3C2410_CS2 + +#define H1940_LATCH_BIT(x) (1 << ((x) + 16 - S3C_GPIO_END)) + static struct map_desc h1940_iodesc[] __initdata = { [0] = { .virtual = (unsigned long)H1940_LATCH, @@ -100,9 +106,16 @@ static struct s3c2410_uartcfg h1940_uartcfgs[] __initdata = { /* Board control latch control */ -static unsigned int latch_state = H1940_LATCH_DEFAULT; +static unsigned int latch_state = H1940_LATCH_BIT(H1940_LATCH_LCD_P4) | + H1940_LATCH_BIT(H1940_LATCH_SM803_ENABLE) | + H1940_LATCH_BIT(H1940_LATCH_SDQ1) | + H1940_LATCH_BIT(H1940_LATCH_LCD_P1) | + H1940_LATCH_BIT(H1940_LATCH_LCD_P2) | + H1940_LATCH_BIT(H1940_LATCH_LCD_P3) | + H1940_LATCH_BIT(H1940_LATCH_MAX1698_nSHUTDOWN) | + H1940_LATCH_BIT(H1940_LATCH_CPUQ5); -void h1940_latch_control(unsigned int clear, unsigned int set) +static void h1940_latch_control(unsigned int clear, unsigned int set) { unsigned long flags; @@ -116,7 +129,42 @@ void h1940_latch_control(unsigned int clear, unsigned int set) local_irq_restore(flags); } -EXPORT_SYMBOL_GPL(h1940_latch_control); +static inline int h1940_gpiolib_to_latch(int offset) +{ + return 1 << (offset + 16); +} + +static void h1940_gpiolib_latch_set(struct gpio_chip *chip, + unsigned offset, int value) +{ + int latch_bit = h1940_gpiolib_to_latch(offset); + + h1940_latch_control(value ? 0 : latch_bit, + value ? latch_bit : 0); +} + +static int h1940_gpiolib_latch_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + h1940_gpiolib_latch_set(chip, offset, value); + return 0; +} + +static int h1940_gpiolib_latch_get(struct gpio_chip *chip, + unsigned offset) +{ + return (latch_state >> (offset + 16)) & 1; +} + +struct gpio_chip h1940_latch_gpiochip = { + .base = H1940_LATCH_GPIO(0), + .owner = THIS_MODULE, + .label = "H1940_LATCH", + .ngpio = 16, + .direction_output = h1940_gpiolib_latch_output, + .set = h1940_gpiolib_latch_set, + .get = h1940_gpiolib_latch_get, +}; static void h1940_udc_pullup(enum s3c2410_udc_cmd_e cmd) { @@ -125,10 +173,10 @@ static void h1940_udc_pullup(enum s3c2410_udc_cmd_e cmd) switch (cmd) { case S3C2410_UDC_P_ENABLE : - h1940_latch_control(0, H1940_LATCH_USB_DP); + gpio_set_value(H1940_LATCH_USB_DP, 1); break; case S3C2410_UDC_P_DISABLE : - h1940_latch_control(H1940_LATCH_USB_DP, 0); + gpio_set_value(H1940_LATCH_USB_DP, 0); break; case S3C2410_UDC_P_RESET : break; @@ -303,6 +351,8 @@ static void __init h1940_map_io(void) memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024); #endif s3c_pm_init(); + + WARN_ON(gpiochip_add(&h1940_latch_gpiochip)); } /* H1940 and RX3715 need to reserve this for suspend */ @@ -342,9 +392,11 @@ static void __init h1940_init(void) gpio_request(S3C2410_GPC(0), "LCD power"); gpio_request(S3C2410_GPC(5), "LCD power"); gpio_request(S3C2410_GPC(6), "LCD power"); - gpio_direction_input(S3C2410_GPC(6)); + gpio_request(H1940_LATCH_USB_DP, "USB pullup"); + gpio_direction_output(H1940_LATCH_USB_DP, 0); + platform_add_devices(h1940_devices, ARRAY_SIZE(h1940_devices)); } diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig index 984bf66..5a27b1b 100644 --- a/arch/arm/plat-s3c24xx/Kconfig +++ b/arch/arm/plat-s3c24xx/Kconfig @@ -69,6 +69,7 @@ config S3C24XX_GPIO_EXTRA int default 128 if S3C24XX_GPIO_EXTRA128 default 64 if S3C24XX_GPIO_EXTRA64 + default 16 if ARCH_H1940 default 0 config S3C24XX_GPIO_EXTRA64 -- cgit v1.1 From 80eb4a6f89bbf8e8318e108701bad11451efb2df Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Sat, 11 Sep 2010 18:10:10 +0200 Subject: alpha: kill big kernel lock All uses of the BKL on alpha are totally bogus, nothing is really protected by this. Remove the remaining users so we don't have to mark alpha as 'depends on BKL'. Signed-off-by: Arnd Bergmann Cc: Richard Henderson Cc: Ivan Kokshaysky Cc: Matt Turner Cc: linux-alpha@vger.kernel.org --- arch/alpha/kernel/osf_sys.c | 5 ----- arch/alpha/kernel/traps.c | 3 --- 2 files changed, 8 deletions(-) (limited to 'arch') diff --git a/arch/alpha/kernel/osf_sys.c b/arch/alpha/kernel/osf_sys.c index 5d1e6d6..49225dd 100644 --- a/arch/alpha/kernel/osf_sys.c +++ b/arch/alpha/kernel/osf_sys.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include @@ -69,7 +68,6 @@ SYSCALL_DEFINE4(osf_set_program_attributes, unsigned long, text_start, { struct mm_struct *mm; - lock_kernel(); mm = current->mm; mm->end_code = bss_start + bss_len; mm->start_brk = bss_start + bss_len; @@ -78,7 +76,6 @@ SYSCALL_DEFINE4(osf_set_program_attributes, unsigned long, text_start, printk("set_program_attributes(%lx %lx %lx %lx)\n", text_start, text_len, bss_start, bss_len); #endif - unlock_kernel(); return 0; } @@ -517,7 +514,6 @@ SYSCALL_DEFINE2(osf_proplist_syscall, enum pl_code, code, long error; int __user *min_buf_size_ptr; - lock_kernel(); switch (code) { case PL_SET: if (get_user(error, &args->set.nbytes)) @@ -547,7 +543,6 @@ SYSCALL_DEFINE2(osf_proplist_syscall, enum pl_code, code, error = -EOPNOTSUPP; break; }; - unlock_kernel(); return error; } diff --git a/arch/alpha/kernel/traps.c b/arch/alpha/kernel/traps.c index b14f015..0414e02 100644 --- a/arch/alpha/kernel/traps.c +++ b/arch/alpha/kernel/traps.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include @@ -623,7 +622,6 @@ do_entUna(void * va, unsigned long opcode, unsigned long reg, return; } - lock_kernel(); printk("Bad unaligned kernel access at %016lx: %p %lx %lu\n", pc, va, opcode, reg); do_exit(SIGSEGV); @@ -646,7 +644,6 @@ got_exception: * Yikes! No one to forward the exception to. * Since the registers are in a weird format, dump them ourselves. */ - lock_kernel(); printk("%s(%d): unhandled unaligned exception\n", current->comm, task_pid_nr(current)); -- cgit v1.1 From 0890b5880df6a4989336add11f3a22122b26d9e1 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Sat, 11 Sep 2010 18:18:22 +0200 Subject: cris: autoconvert trivial BKL users All uses of the big kernel lock in the cris architecture are for ioctl and open functions of character device drivers, which can be trivially converted to a per-driver mutex. Most of these are probably unnecessary, so it may make sense to audit them and eventually remove the extra mutex introduced by this patch. Signed-off-by: Arnd Bergmann Cc: Mikael Starvik Cc: Jesper Nilsson Cc: linux-cris-kernel@axis.com --- arch/cris/arch-v10/drivers/ds1302.c | 7 ++++--- arch/cris/arch-v10/drivers/pcf8563.c | 6 +++--- arch/cris/arch-v10/drivers/sync_serial.c | 11 ++++++----- arch/cris/arch-v32/drivers/cryptocop.c | 4 ++-- arch/cris/arch-v32/drivers/mach-a3/gpio.c | 11 ++++++----- arch/cris/arch-v32/drivers/mach-fs/gpio.c | 11 ++++++----- arch/cris/arch-v32/drivers/pcf8563.c | 6 +++--- arch/cris/arch-v32/drivers/sync_serial.c | 11 ++++++----- 8 files changed, 36 insertions(+), 31 deletions(-) (limited to 'arch') diff --git a/arch/cris/arch-v10/drivers/ds1302.c b/arch/cris/arch-v10/drivers/ds1302.c index 8842756..4b92ad0 100644 --- a/arch/cris/arch-v10/drivers/ds1302.c +++ b/arch/cris/arch-v10/drivers/ds1302.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include #include @@ -34,6 +34,7 @@ #define RTC_MAJOR_NR 121 /* local major, change later */ +static DEFINE_MUTEX(ds1302_mutex); static const char ds1302_name[] = "ds1302"; /* The DS1302 might be connected to different bits on different products. @@ -357,9 +358,9 @@ static long rtc_unlocked_ioctl(struct file *file, unsigned int cmd, unsigned lon { int ret; - lock_kernel(); + mutex_lock(&ds1302_mutex); ret = rtc_ioctl(file, cmd, arg); - unlock_kernel(); + mutex_unlock(&ds1302_mutex); return ret; } diff --git a/arch/cris/arch-v10/drivers/pcf8563.c b/arch/cris/arch-v10/drivers/pcf8563.c index 7dcb1f8..2f1dded 100644 --- a/arch/cris/arch-v10/drivers/pcf8563.c +++ b/arch/cris/arch-v10/drivers/pcf8563.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include @@ -49,6 +48,7 @@ #define rtc_read(x) i2c_readreg(RTC_I2C_READ, x) #define rtc_write(x,y) i2c_writereg(RTC_I2C_WRITE, x, y) +static DEFINE_MUTEX(pcf8563_mutex); static DEFINE_MUTEX(rtc_lock); /* Protect state etc */ static const unsigned char days_in_month[] = @@ -343,9 +343,9 @@ static long pcf8563_unlocked_ioctl(struct file *filp, unsigned int cmd, unsigned { int ret; - lock_kernel(); + mutex_lock(&pcf8563_mutex); return pcf8563_ioctl(filp, cmd, arg); - unlock_kernel(); + mutex_unlock(&pcf8563_mutex); return ret; } diff --git a/arch/cris/arch-v10/drivers/sync_serial.c b/arch/cris/arch-v10/drivers/sync_serial.c index ee2dd43..3d9fa07 100644 --- a/arch/cris/arch-v10/drivers/sync_serial.c +++ b/arch/cris/arch-v10/drivers/sync_serial.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include #include @@ -149,6 +149,7 @@ struct sync_port { }; +static DEFINE_MUTEX(sync_serial_mutex); static int etrax_sync_serial_init(void); static void initialize_port(int portnbr); static inline int sync_data_avail(struct sync_port *port); @@ -445,7 +446,7 @@ static int sync_serial_open(struct inode *inode, struct file *file) int mode; int err = -EBUSY; - lock_kernel(); + mutex_lock(&sync_serial_mutex); DEBUG(printk(KERN_DEBUG "Open sync serial port %d\n", dev)); if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) { @@ -626,7 +627,7 @@ static int sync_serial_open(struct inode *inode, struct file *file) ret = 0; out: - unlock_kernel(); + mutex_unlock(&sync_serial_mutex); return ret; } @@ -961,9 +962,9 @@ static long sync_serial_ioctl(struct file *file, { long ret; - lock_kernel(); + mutex_lock(&sync_serial_mutex); ret = sync_serial_ioctl_unlocked(file, cmd, arg); - unlock_kernel(); + mutex_unlock(&sync_serial_mutex); return ret; } diff --git a/arch/cris/arch-v32/drivers/cryptocop.c b/arch/cris/arch-v32/drivers/cryptocop.c index b07646a..0973d5a 100644 --- a/arch/cris/arch-v32/drivers/cryptocop.c +++ b/arch/cris/arch-v32/drivers/cryptocop.c @@ -3139,9 +3139,9 @@ cryptocop_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) struct inode *inode = file->f_path.dentry->d_inode; long ret; - lock_kernel(); + mutex_lock(&cryptocop_mutex); ret = cryptocop_ioctl_unlocked(inode, filp, cmd, arg); - unlock_kernel(); + mutex_unlock(&cryptocop_mutex); return ret; } diff --git a/arch/cris/arch-v32/drivers/mach-a3/gpio.c b/arch/cris/arch-v32/drivers/mach-a3/gpio.c index 2dcd27a..50d1885 100644 --- a/arch/cris/arch-v32/drivers/mach-a3/gpio.c +++ b/arch/cris/arch-v32/drivers/mach-a3/gpio.c @@ -23,7 +23,7 @@ #include #include #include -#include +#include #include #include @@ -66,6 +66,7 @@ static int dp_cnt; #define DP(x) #endif +static DEFINE_MUTEX(gpio_mutex); static char gpio_name[] = "etrax gpio"; #ifdef CONFIG_ETRAX_VIRTUAL_GPIO @@ -391,7 +392,7 @@ static int gpio_open(struct inode *inode, struct file *filp) if (!priv) return -ENOMEM; - lock_kernel(); + mutex_lock(&gpio_mutex); memset(priv, 0, sizeof(*priv)); priv->minor = p; @@ -414,7 +415,7 @@ static int gpio_open(struct inode *inode, struct file *filp) spin_unlock_irq(&gpio_lock); } - unlock_kernel(); + mutex_unlock(&gpio_mutex); return 0; } @@ -667,9 +668,9 @@ static long gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { long ret; - lock_kernel(); + mutex_lock(&gpio_mutex); ret = gpio_ioctl_unlocked(file, cmd, arg); - unlock_kernel(); + mutex_unlock(&gpio_mutex); return ret; } diff --git a/arch/cris/arch-v32/drivers/mach-fs/gpio.c b/arch/cris/arch-v32/drivers/mach-fs/gpio.c index 5ec8a7d..de8dca0 100644 --- a/arch/cris/arch-v32/drivers/mach-fs/gpio.c +++ b/arch/cris/arch-v32/drivers/mach-fs/gpio.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include #include @@ -64,6 +64,7 @@ static int dp_cnt; #define DP(x) #endif +static DEFINE_MUTEX(gpio_mutex); static char gpio_name[] = "etrax gpio"; #if 0 @@ -429,7 +430,7 @@ gpio_open(struct inode *inode, struct file *filp) if (!priv) return -ENOMEM; - lock_kernel(); + mutex_lock(&gpio_mutex); memset(priv, 0, sizeof(*priv)); priv->minor = p; @@ -450,7 +451,7 @@ gpio_open(struct inode *inode, struct file *filp) alarmlist = priv; spin_unlock_irq(&alarm_lock); - unlock_kernel(); + mutex_unlock(&gpio_mutex); return 0; } @@ -708,9 +709,9 @@ static long gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { long ret; - lock_kernel(); + mutex_lock(&gpio_mutex); ret = gpio_ioctl_unlocked(file, cmd, arg); - unlock_kernel(); + mutex_unlock(&gpio_mutex); return ret; } diff --git a/arch/cris/arch-v32/drivers/pcf8563.c b/arch/cris/arch-v32/drivers/pcf8563.c index bef6eb5..bdcac9d 100644 --- a/arch/cris/arch-v32/drivers/pcf8563.c +++ b/arch/cris/arch-v32/drivers/pcf8563.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include #include @@ -45,6 +44,7 @@ #define rtc_read(x) i2c_readreg(RTC_I2C_READ, x) #define rtc_write(x,y) i2c_writereg(RTC_I2C_WRITE, x, y) +static DEFINE_MUTEX(pcf8563_mutex); static DEFINE_MUTEX(rtc_lock); /* Protect state etc */ static const unsigned char days_in_month[] = @@ -339,9 +339,9 @@ static long pcf8563_unlocked_ioctl(struct file *filp, unsigned int cmd, unsigned { int ret; - lock_kernel(); + mutex_lock(&pcf8563_mutex); return pcf8563_ioctl(filp, cmd, arg); - unlock_kernel(); + mutex_unlock(&pcf8563_mutex); return ret; } diff --git a/arch/cris/arch-v32/drivers/sync_serial.c b/arch/cris/arch-v32/drivers/sync_serial.c index ca248f3..a01ae9f 100644 --- a/arch/cris/arch-v32/drivers/sync_serial.c +++ b/arch/cris/arch-v32/drivers/sync_serial.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include #include @@ -145,6 +145,7 @@ typedef struct sync_port spinlock_t lock; } sync_port; +static DEFINE_MUTEX(sync_serial_mutex); static int etrax_sync_serial_init(void); static void initialize_port(int portnbr); static inline int sync_data_avail(struct sync_port *port); @@ -434,7 +435,7 @@ static int sync_serial_open(struct inode *inode, struct file *file) reg_dma_rw_cfg cfg = {.en = regk_dma_yes}; reg_dma_rw_intr_mask intr_mask = {.data = regk_dma_yes}; - lock_kernel(); + mutex_lock(&sync_serial_mutex); DEBUG(printk(KERN_DEBUG "Open sync serial port %d\n", dev)); if (dev < 0 || dev >= NBR_PORTS || !ports[dev].enabled) @@ -583,7 +584,7 @@ static int sync_serial_open(struct inode *inode, struct file *file) port->busy++; ret = 0; out: - unlock_kernel(); + mutex_unlock(&sync_serial_mutex); return ret; } @@ -966,9 +967,9 @@ static long sync_serial_ioctl(struct file *file, { long ret; - lock_kernel(); + mutex_lock(&sync_serial_mutex); ret = sync_serial_ioctl_unlocked(file, cmd, arg); - unlock_kernel(); + mutex_unlock(&sync_serial_mutex); return ret; } -- cgit v1.1 From 48cd65a6a020292e1ab5d0f5ba96571c858964e6 Mon Sep 17 00:00:00 2001 From: Vasily Khoruzhick Date: Mon, 27 Sep 2010 00:27:41 +0300 Subject: ARM: h1940: Implement mmc_power function This patch implements h1940-specific set_power callback for s3cmci driver, so card power can be disabled when card is not inserted or before suspend. Without this patch PDA consumes power in suspend when card is inserted. Signed-off-by: Vasily Khoruzhick Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2410/include/mach/h1940-latch.h | 2 +- arch/arm/mach-s3c2410/mach-h1940.c | 23 ++++++++++++++++++++--- 2 files changed, 21 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-s3c2410/include/mach/h1940-latch.h b/arch/arm/mach-s3c2410/include/mach/h1940-latch.h index 73586f2..ef7d8cf 100644 --- a/arch/arm/mach-s3c2410/include/mach/h1940-latch.h +++ b/arch/arm/mach-s3c2410/include/mach/h1940-latch.h @@ -35,7 +35,7 @@ #define H1940_LATCH_AUDIO_POWER H1940_LATCH_GPIO(9) #define H1940_LATCH_SM803_ENABLE H1940_LATCH_GPIO(10) #define H1940_LATCH_LCD_P4 H1940_LATCH_GPIO(11) -#define H1940_LATCH_CPUQ5 H1940_LATCH_GPIO(12) +#define H1940_LATCH_SD_POWER H1940_LATCH_GPIO(12) #define H1940_LATCH_BLUETOOTH_POWER H1940_LATCH_GPIO(13) #define H1940_LATCH_LED_GREEN H1940_LATCH_GPIO(14) #define H1940_LATCH_LED_FLASH H1940_LATCH_GPIO(15) diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c index f0493bd..cc8660e 100644 --- a/arch/arm/mach-s3c2410/mach-h1940.c +++ b/arch/arm/mach-s3c2410/mach-h1940.c @@ -112,8 +112,7 @@ static unsigned int latch_state = H1940_LATCH_BIT(H1940_LATCH_LCD_P4) | H1940_LATCH_BIT(H1940_LATCH_LCD_P1) | H1940_LATCH_BIT(H1940_LATCH_LCD_P2) | H1940_LATCH_BIT(H1940_LATCH_LCD_P3) | - H1940_LATCH_BIT(H1940_LATCH_MAX1698_nSHUTDOWN) | - H1940_LATCH_BIT(H1940_LATCH_CPUQ5); + H1940_LATCH_BIT(H1940_LATCH_MAX1698_nSHUTDOWN); static void h1940_latch_control(unsigned int clear, unsigned int set) { @@ -247,10 +246,25 @@ static struct platform_device h1940_device_bluetooth = { .id = -1, }; +static void h1940_set_mmc_power(unsigned char power_mode, unsigned short vdd) +{ + switch (power_mode) { + case MMC_POWER_OFF: + gpio_set_value(H1940_LATCH_SD_POWER, 0); + break; + case MMC_POWER_UP: + case MMC_POWER_ON: + gpio_set_value(H1940_LATCH_SD_POWER, 1); + break; + default: + break; + }; +} + static struct s3c24xx_mci_pdata h1940_mmc_cfg __initdata = { .gpio_detect = S3C2410_GPF(5), .gpio_wprotect = S3C2410_GPH(8), - .set_power = NULL, + .set_power = h1940_set_mmc_power, .ocr_avail = MMC_VDD_32_33, }; @@ -397,6 +411,9 @@ static void __init h1940_init(void) gpio_request(H1940_LATCH_USB_DP, "USB pullup"); gpio_direction_output(H1940_LATCH_USB_DP, 0); + gpio_request(H1940_LATCH_SD_POWER, "SD power"); + gpio_direction_output(H1940_LATCH_SD_POWER, 0); + platform_add_devices(h1940_devices, ARRAY_SIZE(h1940_devices)); } -- cgit v1.1 From ecab01d46c68370f347b2c1125cb90070813c799 Mon Sep 17 00:00:00 2001 From: Vasily Khoruzhick Date: Mon, 27 Sep 2010 00:17:48 +0300 Subject: ARM: rx1950: Add battery device This patch adds registration of appropriate device for s3c-adc-battery driver, so battery monitoring and charging are available on RX1950 PDA now. Signed-off-by: Vasily Khoruzhick Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2440/mach-rx1950.c | 160 ++++++++++++++++++++++++++++++++++++ 1 file changed, 160 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-s3c2440/mach-rx1950.c b/arch/arm/mach-s3c2440/mach-rx1950.c index 142d1f9..a4d8c15 100644 --- a/arch/arm/mach-s3c2440/mach-rx1950.c +++ b/arch/arm/mach-s3c2440/mach-rx1950.c @@ -25,8 +25,10 @@ #include #include #include +#include #include #include +#include #include #include @@ -127,6 +129,162 @@ static struct s3c2410fb_display rx1950_display = { }; +static int power_supply_init(struct device *dev) +{ + return gpio_request(S3C2410_GPF(2), "cable plugged"); +} + +static int rx1950_is_ac_online(void) +{ + return !gpio_get_value(S3C2410_GPF(2)); +} + +static void power_supply_exit(struct device *dev) +{ + gpio_free(S3C2410_GPF(2)); +} + +static char *rx1950_supplicants[] = { + "main-battery" +}; + +static struct pda_power_pdata power_supply_info = { + .init = power_supply_init, + .is_ac_online = rx1950_is_ac_online, + .exit = power_supply_exit, + .supplied_to = rx1950_supplicants, + .num_supplicants = ARRAY_SIZE(rx1950_supplicants), +}; + +static struct resource power_supply_resources[] = { + [0] = { + .name = "ac", + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE | + IORESOURCE_IRQ_HIGHEDGE, + .start = IRQ_EINT2, + .end = IRQ_EINT2, + }, +}; + +static struct platform_device power_supply = { + .name = "pda-power", + .id = -1, + .dev = { + .platform_data = + &power_supply_info, + }, + .resource = power_supply_resources, + .num_resources = ARRAY_SIZE(power_supply_resources), +}; + +static const struct s3c_adc_bat_thresh bat_lut_noac[] = { + { .volt = 4100, .cur = 156, .level = 100}, + { .volt = 4050, .cur = 156, .level = 95}, + { .volt = 4025, .cur = 141, .level = 90}, + { .volt = 3995, .cur = 144, .level = 85}, + { .volt = 3957, .cur = 162, .level = 80}, + { .volt = 3931, .cur = 147, .level = 75}, + { .volt = 3902, .cur = 147, .level = 70}, + { .volt = 3863, .cur = 153, .level = 65}, + { .volt = 3838, .cur = 150, .level = 60}, + { .volt = 3800, .cur = 153, .level = 55}, + { .volt = 3765, .cur = 153, .level = 50}, + { .volt = 3748, .cur = 172, .level = 45}, + { .volt = 3740, .cur = 153, .level = 40}, + { .volt = 3714, .cur = 175, .level = 35}, + { .volt = 3710, .cur = 156, .level = 30}, + { .volt = 3963, .cur = 156, .level = 25}, + { .volt = 3672, .cur = 178, .level = 20}, + { .volt = 3651, .cur = 178, .level = 15}, + { .volt = 3629, .cur = 178, .level = 10}, + { .volt = 3612, .cur = 162, .level = 5}, + { .volt = 3605, .cur = 162, .level = 0}, +}; + +static const struct s3c_adc_bat_thresh bat_lut_acin[] = { + { .volt = 4200, .cur = 0, .level = 100}, + { .volt = 4190, .cur = 0, .level = 99}, + { .volt = 4178, .cur = 0, .level = 95}, + { .volt = 4110, .cur = 0, .level = 70}, + { .volt = 4076, .cur = 0, .level = 65}, + { .volt = 4046, .cur = 0, .level = 60}, + { .volt = 4021, .cur = 0, .level = 55}, + { .volt = 3999, .cur = 0, .level = 50}, + { .volt = 3982, .cur = 0, .level = 45}, + { .volt = 3965, .cur = 0, .level = 40}, + { .volt = 3957, .cur = 0, .level = 35}, + { .volt = 3948, .cur = 0, .level = 30}, + { .volt = 3936, .cur = 0, .level = 25}, + { .volt = 3927, .cur = 0, .level = 20}, + { .volt = 3906, .cur = 0, .level = 15}, + { .volt = 3880, .cur = 0, .level = 10}, + { .volt = 3829, .cur = 0, .level = 5}, + { .volt = 3820, .cur = 0, .level = 0}, +}; + +int rx1950_bat_init(void) +{ + int ret; + + ret = gpio_request(S3C2410_GPJ(2), "rx1950-charger-enable-1"); + if (ret) + goto err_gpio1; + ret = gpio_request(S3C2410_GPJ(3), "rx1950-charger-enable-2"); + if (ret) + goto err_gpio2; + + return 0; + +err_gpio2: + gpio_free(S3C2410_GPJ(2)); +err_gpio1: + return ret; +} + +void rx1950_bat_exit(void) +{ + gpio_free(S3C2410_GPJ(2)); + gpio_free(S3C2410_GPJ(3)); +} + +void rx1950_enable_charger(void) +{ + gpio_direction_output(S3C2410_GPJ(2), 1); + gpio_direction_output(S3C2410_GPJ(3), 1); +} + +void rx1950_disable_charger(void) +{ + gpio_direction_output(S3C2410_GPJ(2), 0); + gpio_direction_output(S3C2410_GPJ(3), 0); +} + +static struct s3c_adc_bat_pdata rx1950_bat_cfg = { + .init = rx1950_bat_init, + .exit = rx1950_bat_exit, + .enable_charger = rx1950_enable_charger, + .disable_charger = rx1950_disable_charger, + .gpio_charge_finished = S3C2410_GPF(3), + .lut_noac = bat_lut_noac, + .lut_noac_cnt = ARRAY_SIZE(bat_lut_noac), + .lut_acin = bat_lut_acin, + .lut_acin_cnt = ARRAY_SIZE(bat_lut_acin), + .volt_channel = 0, + .current_channel = 1, + .volt_mult = 4235, + .current_mult = 2900, + .internal_impedance = 200, +}; + +static struct platform_device rx1950_battery = { + .name = "s3c-adc-battery", + .id = -1, + .dev = { + .parent = &s3c_device_adc.dev, + .platform_data = &rx1950_bat_cfg, + }, +}; + static struct s3c2410fb_mach_info rx1950_lcd_cfg = { .displays = &rx1950_display, .num_displays = 1, @@ -503,6 +661,8 @@ static struct platform_device *rx1950_devices[] __initdata = { &s3c_device_timer[1], &rx1950_backlight, &rx1950_device_gpiokeys, + &power_supply, + &rx1950_battery, }; static struct clk *rx1950_clocks[] __initdata = { -- cgit v1.1 From 9c1a47cf1e8978394399198b6b296c10f3a8dbfe Mon Sep 17 00:00:00 2001 From: Vasily Khoruzhick Date: Tue, 7 Sep 2010 17:32:25 +0300 Subject: ARM: rx1950: Add LEDs support Signed-off-by: Vasily Khoruzhick Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2440/mach-rx1950.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-s3c2440/mach-rx1950.c b/arch/arm/mach-s3c2440/mach-rx1950.c index a4d8c15..adfbb30 100644 --- a/arch/arm/mach-s3c2440/mach-rx1950.c +++ b/arch/arm/mach-s3c2440/mach-rx1950.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include @@ -259,6 +260,37 @@ void rx1950_disable_charger(void) gpio_direction_output(S3C2410_GPJ(3), 0); } +static struct gpio_led rx1950_leds_desc[] = { + { + .name = "Green", + .default_trigger = "main-battery-charging-or-full", + .gpio = S3C2410_GPA(6), + }, + { + .name = "Red", + .default_trigger = "main-battery-full", + .gpio = S3C2410_GPA(7), + }, + { + .name = "Blue", + .default_trigger = "rx1950-acx-mem", + .gpio = S3C2410_GPA(11), + }, +}; + +static struct gpio_led_platform_data rx1950_leds_pdata = { + .num_leds = ARRAY_SIZE(rx1950_leds_desc), + .leds = rx1950_leds_desc, +}; + +static struct platform_device rx1950_leds = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &rx1950_leds_pdata, + }, +}; + static struct s3c_adc_bat_pdata rx1950_bat_cfg = { .init = rx1950_bat_init, .exit = rx1950_bat_exit, @@ -663,6 +695,7 @@ static struct platform_device *rx1950_devices[] __initdata = { &rx1950_device_gpiokeys, &power_supply, &rx1950_battery, + &rx1950_leds, }; static struct clk *rx1950_clocks[] __initdata = { -- cgit v1.1 From 2cc857ffec1e7540155c5ab90e622e5acc28d136 Mon Sep 17 00:00:00 2001 From: Vasily Khoruzhick Date: Tue, 7 Sep 2010 17:32:26 +0300 Subject: ARM: rx1950: Add UDA1380 to i2c devices list Signed-off-by: Vasily Khoruzhick Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2440/mach-rx1950.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-s3c2440/mach-rx1950.c b/arch/arm/mach-s3c2440/mach-rx1950.c index adfbb30..6d676a7 100644 --- a/arch/arm/mach-s3c2440/mach-rx1950.c +++ b/arch/arm/mach-s3c2440/mach-rx1950.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include @@ -58,6 +59,8 @@ #include #include +#include + #define LCD_PWM_PERIOD 192960 #define LCD_PWM_DUTY 127353 @@ -671,11 +674,17 @@ static struct platform_device rx1950_device_gpiokeys = { .dev.platform_data = &rx1950_gpio_keys_data, }; -static struct s3c2410_platform_i2c rx1950_i2c_data = { - .flags = 0, - .slave_addr = 0x42, - .frequency = 400 * 1000, - .sda_delay = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON, +static struct uda1380_platform_data uda1380_info = { + .gpio_power = S3C2410_GPJ(0), + .gpio_reset = S3C2410_GPD(0), + .dac_clk = UDA1380_DAC_CLK_SYSCLK, +}; + +static struct i2c_board_info rx1950_i2c_devices[] = { + { + I2C_BOARD_INFO("uda1380", 0x1a), + .platform_data = &uda1380_info, + }, }; static struct platform_device *rx1950_devices[] __initdata = { @@ -683,6 +692,7 @@ static struct platform_device *rx1950_devices[] __initdata = { &s3c_device_wdt, &s3c_device_i2c0, &s3c_device_iis, + &s3c_device_pcm, &s3c_device_usbgadget, &s3c_device_rtc, &s3c_device_nand, @@ -731,7 +741,7 @@ static void __init rx1950_init_machine(void) s3c24xx_udc_set_platdata(&rx1950_udc_cfg); s3c24xx_ts_set_platdata(&rx1950_ts_cfg); s3c24xx_mci_set_platdata(&rx1950_mmc_cfg); - s3c_i2c0_set_platdata(&rx1950_i2c_data); + s3c_i2c0_set_platdata(NULL); s3c_nand_set_platdata(&rx1950_nand_info); /* Turn off suspend on both USB ports, and switch the @@ -762,6 +772,9 @@ static void __init rx1950_init_machine(void) WARN_ON(gpio_request(S3C2410_GPB(1), "LCD power")); platform_add_devices(rx1950_devices, ARRAY_SIZE(rx1950_devices)); + + i2c_register_board_info(0, rx1950_i2c_devices, + ARRAY_SIZE(rx1950_i2c_devices)); } /* H1940 and RX3715 need to reserve this for suspend */ -- cgit v1.1 From afc28bc0ec5ebe1b71108735e27283a19feb2e24 Mon Sep 17 00:00:00 2001 From: Anand Gadiyar Date: Thu, 16 Sep 2010 16:22:13 -0700 Subject: omap: usb: fix build warning Fix this and similar build warnings when building with omap_4430sdp_defconfig. CC arch/arm/mach-omap2/board-4430sdp.o In file included from arch/arm/mach-omap2/board-4430sdp.c:36: arch/arm/plat-omap/include/plat/usb.h:109: warning: return type defaults to 'int' Signed-off-by: Anand Gadiyar Acked-by: Felipe Balbi Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/include/plat/usb.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h index 2a9427c..6674562 100644 --- a/arch/arm/plat-omap/include/plat/usb.h +++ b/arch/arm/plat-omap/include/plat/usb.h @@ -105,7 +105,7 @@ static inline void omap1_usb_init(struct omap_usb_config *pdata) #if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP_OTG_MODULE) void omap2_usbfs_init(struct omap_usb_config *pdata); #else -static inline omap2_usbfs_init(struct omap_usb_config *pdata) +static inline void omap2_usbfs_init(struct omap_usb_config *pdata) { } #endif -- cgit v1.1 From 82a0c149b5beb4b91036b9687644db8a913e8fd1 Mon Sep 17 00:00:00 2001 From: Dmitry Kasatkin Date: Fri, 20 Aug 2010 13:44:46 +0000 Subject: omap: crypto: updates to enable omap aes Updates to enable omap aes Signed-off-by: Dmitry Kasatkin [tony@atomide.com: updated to use CONFIG_ARCH_OMAP2/3 instead of old 24XX/34XX] Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/clock2420_data.c | 2 +- arch/arm/mach-omap2/clock2430_data.c | 2 +- arch/arm/mach-omap2/clock3xxx_data.c | 2 +- arch/arm/mach-omap2/devices.c | 71 ++++++++++++++++++++++++++++++++++++ 4 files changed, 74 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c index 37d65d6..5f2066a 100644 --- a/arch/arm/mach-omap2/clock2420_data.c +++ b/arch/arm/mach-omap2/clock2420_data.c @@ -1838,7 +1838,7 @@ static struct omap_clk omap2420_clks[] = { CLK(NULL, "des_ick", &des_ick, CK_242X), CLK("omap-sham", "ick", &sha_ick, CK_242X), CLK("omap_rng", "ick", &rng_ick, CK_242X), - CLK(NULL, "aes_ick", &aes_ick, CK_242X), + CLK("omap-aes", "ick", &aes_ick, CK_242X), CLK(NULL, "pka_ick", &pka_ick, CK_242X), CLK(NULL, "usb_fck", &usb_fck, CK_242X), CLK("musb_hdrc", "fck", &osc_ck, CK_242X), diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c index b33118f..701a171 100644 --- a/arch/arm/mach-omap2/clock2430_data.c +++ b/arch/arm/mach-omap2/clock2430_data.c @@ -1926,7 +1926,7 @@ static struct omap_clk omap2430_clks[] = { CLK(NULL, "des_ick", &des_ick, CK_243X), CLK("omap-sham", "ick", &sha_ick, CK_243X), CLK("omap_rng", "ick", &rng_ick, CK_243X), - CLK(NULL, "aes_ick", &aes_ick, CK_243X), + CLK("omap-aes", "ick", &aes_ick, CK_243X), CLK(NULL, "pka_ick", &pka_ick, CK_243X), CLK(NULL, "usb_fck", &usb_fck, CK_243X), CLK("musb_hdrc", "ick", &usbhs_ick, CK_243X), diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index dfdce2d..c73906d 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -3288,7 +3288,7 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2 | CK_AM35XX), CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2 | CK_AM35XX), CLK(NULL, "icr_ick", &icr_ick, CK_343X), - CLK(NULL, "aes2_ick", &aes2_ick, CK_343X), + CLK("omap-aes", "ick", &aes2_ick, CK_343X), CLK("omap-sham", "ick", &sha12_ick, CK_343X), CLK(NULL, "des2_ick", &des2_ick, CK_343X), CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_3XXX), diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 2dbb265..dc49c07 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -498,6 +498,76 @@ static void omap_init_sham(void) static inline void omap_init_sham(void) { } #endif +#if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE) + +#ifdef CONFIG_ARCH_OMAP2 +static struct resource omap2_aes_resources[] = { + { + .start = OMAP24XX_SEC_AES_BASE, + .end = OMAP24XX_SEC_AES_BASE + 0x4C, + .flags = IORESOURCE_MEM, + }, + { + .start = OMAP24XX_DMA_AES_TX, + .flags = IORESOURCE_DMA, + }, + { + .start = OMAP24XX_DMA_AES_RX, + .flags = IORESOURCE_DMA, + } +}; +static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources); +#else +#define omap2_aes_resources NULL +#define omap2_aes_resources_sz 0 +#endif + +#ifdef CONFIG_ARCH_OMAP3 +static struct resource omap3_aes_resources[] = { + { + .start = OMAP34XX_SEC_AES_BASE, + .end = OMAP34XX_SEC_AES_BASE + 0x4C, + .flags = IORESOURCE_MEM, + }, + { + .start = OMAP34XX_DMA_AES2_TX, + .flags = IORESOURCE_DMA, + }, + { + .start = OMAP34XX_DMA_AES2_RX, + .flags = IORESOURCE_DMA, + } +}; +static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources); +#else +#define omap3_aes_resources NULL +#define omap3_aes_resources_sz 0 +#endif + +static struct platform_device aes_device = { + .name = "omap-aes", + .id = -1, +}; + +static void omap_init_aes(void) +{ + if (cpu_is_omap24xx()) { + aes_device.resource = omap2_aes_resources; + aes_device.num_resources = omap2_aes_resources_sz; + } else if (cpu_is_omap34xx()) { + aes_device.resource = omap3_aes_resources; + aes_device.num_resources = omap3_aes_resources_sz; + } else { + pr_err("%s: platform not supported\n", __func__); + return; + } + platform_device_register(&aes_device); +} + +#else +static inline void omap_init_aes(void) { } +#endif + /*-------------------------------------------------------------------------*/ #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) @@ -854,6 +924,7 @@ static int __init omap2_init_devices(void) omap_hdq_init(); omap_init_sti(); omap_init_sham(); + omap_init_aes(); omap_init_vout(); return 0; -- cgit v1.1 From 813f6c5850521fec8917f61813be59691b60fcdf Mon Sep 17 00:00:00 2001 From: "Subramaniam C.A" Date: Tue, 24 Aug 2010 12:02:28 -0500 Subject: omap: i2c: Avoid compilation error in case the header is included multiple times Added defines to avoid compilation error. Signed-off-by: Subramaniam C.A Acked-by: Felipe Balbi Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/include/plat/i2c.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm/plat-omap/include/plat/i2c.h b/arch/arm/plat-omap/include/plat/i2c.h index 87f6bf2..36a0bef 100644 --- a/arch/arm/plat-omap/include/plat/i2c.h +++ b/arch/arm/plat-omap/include/plat/i2c.h @@ -18,6 +18,8 @@ * 02110-1301 USA * */ +#ifndef __ASM__ARCH_OMAP_I2C_H +#define __ASM__ARCH_OMAP_I2C_H #include @@ -36,3 +38,5 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate, void __init omap1_i2c_mux_pins(int bus_id); void __init omap2_i2c_mux_pins(int bus_id); + +#endif /* __ASM__ARCH_OMAP_I2C_H */ -- cgit v1.1 From ce3f054bdd4e022fa0ee9d11a215ec32f1caa12d Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Tue, 31 Aug 2010 08:11:44 +0000 Subject: omap: McBSP: Do not enable SRG in slave mode McBSP SRG (Sample Rate Generator) and FSG (Frame Sync Generator) is only needed to be enabled, when McBSP is master. In McBSP slave mode, the SRG, and FSG can be kept disabled, which might save some power at the end in this configuration. Signed-off-by: Peter Ujfalusi Acked-by: Jarkko Nikula Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/mcbsp.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index e31496e..ecbfe39 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c @@ -878,7 +878,7 @@ EXPORT_SYMBOL(omap_mcbsp_free); void omap_mcbsp_start(unsigned int id, int tx, int rx) { struct omap_mcbsp *mcbsp; - int idle; + int enable_srg = 0; u16 w; if (!omap_mcbsp_check_valid_id(id)) { @@ -893,10 +893,13 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx) mcbsp->rx_word_length = (MCBSP_READ_CACHE(mcbsp, RCR1) >> 5) & 0x7; mcbsp->tx_word_length = (MCBSP_READ_CACHE(mcbsp, XCR1) >> 5) & 0x7; - idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) | - MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1); + /* Only enable SRG, if McBSP is master */ + w = MCBSP_READ_CACHE(mcbsp, PCR0); + if (w & (FSXM | FSRM | CLKXM | CLKRM)) + enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) | + MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1); - if (idle) { + if (enable_srg) { /* Start the sample generator */ w = MCBSP_READ_CACHE(mcbsp, SPCR2); MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6)); @@ -919,7 +922,7 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx) */ udelay(500); - if (idle) { + if (enable_srg) { /* Start frame sync */ w = MCBSP_READ_CACHE(mcbsp, SPCR2); MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7)); -- cgit v1.1 From 7193559af4243279790fd8dbfef82f8536d9c514 Mon Sep 17 00:00:00 2001 From: Jarkko Nikula Date: Tue, 31 Aug 2010 10:12:56 +0000 Subject: omap2: McBSP: Remove mux code for OMAP2420 McBSP2 and do cleanups This 'legacy' OMAP2420 McBSP2 muxing code is currently broken after recent conversion to new mux code. The omap_mcbsp_request calling this code is usually called after booting whereas the omap_mux_init_signal is __init marked so null pointer dereference would occur. Fix this by removing the muxing code and let the bootloader or board file to do it if necessary. Remove also omap2_mcbsp_ops as there is no use for it. Signed-off-by: Jarkko Nikula Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/mcbsp.c | 39 --------------------------------------- 1 file changed, 39 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index 467aae2..88b8790 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c @@ -23,29 +23,6 @@ #include #include -#include "mux.h" - -static void omap2_mcbsp2_mux_setup(void) -{ - omap_mux_init_signal("eac_ac_sclk.mcbsp2_clkx", OMAP_PULL_ENA); - omap_mux_init_signal("eac_ac_fs.mcbsp2_fsx", OMAP_PULL_ENA); - omap_mux_init_signal("eac_ac_din.mcbsp2_dr", OMAP_PULL_ENA); - omap_mux_init_signal("eac_ac_dout.mcbsp2_dx", OMAP_PULL_ENA); - omap_mux_init_gpio(117, OMAP_PULL_ENA); - /* - * TODO: Need to add MUX settings for OMAP 2430 SDP - */ -} - -static void omap2_mcbsp_request(unsigned int id) -{ - if (cpu_is_omap2420() && (id == OMAP_MCBSP2)) - omap2_mcbsp2_mux_setup(); -} - -static struct omap_mcbsp_ops omap2_mcbsp_ops = { - .request = omap2_mcbsp_request, -}; #ifdef CONFIG_ARCH_OMAP2420 static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = { @@ -55,7 +32,6 @@ static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, .rx_irq = INT_24XX_MCBSP1_IRQ_RX, .tx_irq = INT_24XX_MCBSP1_IRQ_TX, - .ops = &omap2_mcbsp_ops, }, { .phys_base = OMAP24XX_MCBSP2_BASE, @@ -63,7 +39,6 @@ static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, .rx_irq = INT_24XX_MCBSP2_IRQ_RX, .tx_irq = INT_24XX_MCBSP2_IRQ_TX, - .ops = &omap2_mcbsp_ops, }, }; #define OMAP2420_MCBSP_PDATA_SZ ARRAY_SIZE(omap2420_mcbsp_pdata) @@ -82,7 +57,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, .rx_irq = INT_24XX_MCBSP1_IRQ_RX, .tx_irq = INT_24XX_MCBSP1_IRQ_TX, - .ops = &omap2_mcbsp_ops, }, { .phys_base = OMAP24XX_MCBSP2_BASE, @@ -90,7 +64,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, .rx_irq = INT_24XX_MCBSP2_IRQ_RX, .tx_irq = INT_24XX_MCBSP2_IRQ_TX, - .ops = &omap2_mcbsp_ops, }, { .phys_base = OMAP2430_MCBSP3_BASE, @@ -98,7 +71,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX, .rx_irq = INT_24XX_MCBSP3_IRQ_RX, .tx_irq = INT_24XX_MCBSP3_IRQ_TX, - .ops = &omap2_mcbsp_ops, }, { .phys_base = OMAP2430_MCBSP4_BASE, @@ -106,7 +78,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX, .rx_irq = INT_24XX_MCBSP4_IRQ_RX, .tx_irq = INT_24XX_MCBSP4_IRQ_TX, - .ops = &omap2_mcbsp_ops, }, { .phys_base = OMAP2430_MCBSP5_BASE, @@ -114,7 +85,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX, .rx_irq = INT_24XX_MCBSP5_IRQ_RX, .tx_irq = INT_24XX_MCBSP5_IRQ_TX, - .ops = &omap2_mcbsp_ops, }, }; #define OMAP2430_MCBSP_PDATA_SZ ARRAY_SIZE(omap2430_mcbsp_pdata) @@ -133,7 +103,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, .rx_irq = INT_24XX_MCBSP1_IRQ_RX, .tx_irq = INT_24XX_MCBSP1_IRQ_TX, - .ops = &omap2_mcbsp_ops, .buffer_size = 0x80, /* The FIFO has 128 locations */ }, { @@ -143,7 +112,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, .rx_irq = INT_24XX_MCBSP2_IRQ_RX, .tx_irq = INT_24XX_MCBSP2_IRQ_TX, - .ops = &omap2_mcbsp_ops, .buffer_size = 0x500, /* The FIFO has 1024 + 256 locations */ }, { @@ -153,7 +121,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX, .rx_irq = INT_24XX_MCBSP3_IRQ_RX, .tx_irq = INT_24XX_MCBSP3_IRQ_TX, - .ops = &omap2_mcbsp_ops, .buffer_size = 0x80, /* The FIFO has 128 locations */ }, { @@ -162,7 +129,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX, .rx_irq = INT_24XX_MCBSP4_IRQ_RX, .tx_irq = INT_24XX_MCBSP4_IRQ_TX, - .ops = &omap2_mcbsp_ops, .buffer_size = 0x80, /* The FIFO has 128 locations */ }, { @@ -171,7 +137,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX, .rx_irq = INT_24XX_MCBSP5_IRQ_RX, .tx_irq = INT_24XX_MCBSP5_IRQ_TX, - .ops = &omap2_mcbsp_ops, .buffer_size = 0x80, /* The FIFO has 128 locations */ }, }; @@ -189,28 +154,24 @@ static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = { .dma_rx_sync = OMAP44XX_DMA_MCBSP1_RX, .dma_tx_sync = OMAP44XX_DMA_MCBSP1_TX, .tx_irq = OMAP44XX_IRQ_MCBSP1, - .ops = &omap2_mcbsp_ops, }, { .phys_base = OMAP44XX_MCBSP2_BASE, .dma_rx_sync = OMAP44XX_DMA_MCBSP2_RX, .dma_tx_sync = OMAP44XX_DMA_MCBSP2_TX, .tx_irq = OMAP44XX_IRQ_MCBSP2, - .ops = &omap2_mcbsp_ops, }, { .phys_base = OMAP44XX_MCBSP3_BASE, .dma_rx_sync = OMAP44XX_DMA_MCBSP3_RX, .dma_tx_sync = OMAP44XX_DMA_MCBSP3_TX, .tx_irq = OMAP44XX_IRQ_MCBSP3, - .ops = &omap2_mcbsp_ops, }, { .phys_base = OMAP44XX_MCBSP4_BASE, .dma_rx_sync = OMAP44XX_DMA_MCBSP4_RX, .dma_tx_sync = OMAP44XX_DMA_MCBSP4_TX, .tx_irq = OMAP44XX_IRQ_MCBSP4, - .ops = &omap2_mcbsp_ops, }, }; #define OMAP44XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap44xx_mcbsp_pdata) -- cgit v1.1 From 3a63833ec3002816a759a49ebda4e229c089114e Mon Sep 17 00:00:00 2001 From: Sukumar Ghorai Date: Wed, 15 Sep 2010 14:49:23 +0000 Subject: omap: mmc: extended to pass host capabilities from board file wires variable is renamed, extended and this single variable to be used to pass the platform capabilities, e.g DDR mode. Also removed the hardcoded value was using as bus-width. Signed-off-by: Sukumar Ghorai Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-2430sdp.c | 3 ++- arch/arm/mach-omap2/board-3430sdp.c | 5 +++-- arch/arm/mach-omap2/board-4430sdp.c | 4 ++-- arch/arm/mach-omap2/board-cm-t35.c | 5 +++-- arch/arm/mach-omap2/board-devkit8000.c | 3 ++- arch/arm/mach-omap2/board-igep0020.c | 5 +++-- arch/arm/mach-omap2/board-ldp.c | 3 ++- arch/arm/mach-omap2/board-n8x0.c | 2 +- arch/arm/mach-omap2/board-omap3beagle.c | 3 ++- arch/arm/mach-omap2/board-omap3evm.c | 3 ++- arch/arm/mach-omap2/board-omap3pandora.c | 7 ++++--- arch/arm/mach-omap2/board-omap3stalker.c | 3 ++- arch/arm/mach-omap2/board-omap3touchbook.c | 3 ++- arch/arm/mach-omap2/board-omap4panda.c | 2 +- arch/arm/mach-omap2/board-overo.c | 5 +++-- arch/arm/mach-omap2/board-rx51-peripherals.c | 5 +++-- arch/arm/mach-omap2/board-zoom-peripherals.c | 5 +++-- arch/arm/mach-omap2/devices.c | 16 +++++++++------- arch/arm/mach-omap2/hsmmc.c | 16 ++++++++++------ arch/arm/mach-omap2/hsmmc.h | 3 ++- arch/arm/plat-omap/include/plat/mmc.h | 7 +++---- 21 files changed, 64 insertions(+), 44 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c index 8538e41..fc178a0 100644 --- a/arch/arm/mach-omap2/board-2430sdp.c +++ b/arch/arm/mach-omap2/board-2430sdp.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -190,7 +191,7 @@ static int __init omap2430_i2c_init(void) static struct omap2_hsmmc_info mmc[] __initdata = { { .mmc = 1, - .wires = 4, + .caps = MMC_CAP_4_BIT_DATA, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, .ext_clock = 1, diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index 67b95b5f..3eb9839 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include @@ -353,12 +354,12 @@ static struct omap2_hsmmc_info mmc[] = { /* 8 bits (default) requires S6.3 == ON, * so the SIM card isn't used; else 4 bits. */ - .wires = 8, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, .gpio_wp = 4, }, { .mmc = 2, - .wires = 8, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, .gpio_wp = 7, }, {} /* Terminator */ diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index 9447644..e379bef 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -193,12 +193,12 @@ static struct omap_musb_board_data musb_board_data = { static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, - .wires = 8, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, .gpio_wp = -EINVAL, }, { .mmc = 2, - .wires = 8, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, .nonremovable = true, diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index e10bc10..b72009a 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include @@ -579,14 +580,14 @@ static struct twl4030_keypad_data cm_t35_kp_data = { static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, - .wires = 4, + .caps = MMC_CAP_4_BIT_DATA, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, }, { .mmc = 2, - .wires = 4, + .caps = MMC_CAP_4_BIT_DATA, .transceiver = 1, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c index a07086d..de5e2c2 100644 --- a/arch/arm/mach-omap2/board-devkit8000.c +++ b/arch/arm/mach-omap2/board-devkit8000.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include @@ -105,7 +106,7 @@ static struct omap_nand_platform_data devkit8000_nand_data = { static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, - .wires = 8, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, .gpio_wp = 29, }, {} /* Terminator */ diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index 175f043..f3f0280 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -20,6 +20,7 @@ #include #include +#include #include #include @@ -248,13 +249,13 @@ static struct regulator_init_data igep2_vmmc2 = { static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, - .wires = 4, + .caps = MMC_CAP_4_BIT_DATA, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, }, { .mmc = 2, - .wires = 4, + .caps = MMC_CAP_4_BIT_DATA, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, }, diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c index 00d9b13..58698e3 100644 --- a/arch/arm/mach-omap2/board-ldp.c +++ b/arch/arm/mach-omap2/board-ldp.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include @@ -362,7 +363,7 @@ static int __init omap_i2c_init(void) static struct omap2_hsmmc_info mmc[] __initdata = { { .mmc = 1, - .wires = 4, + .caps = MMC_CAP_4_BIT_DATA, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, }, diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c index 8fd2269..7a93bd5 100644 --- a/arch/arm/mach-omap2/board-n8x0.c +++ b/arch/arm/mach-omap2/board-n8x0.c @@ -488,7 +488,7 @@ static struct omap_mmc_platform_data mmc1_data = { .max_freq = 24000000, .dma_mask = 0xffffffff, .slots[0] = { - .wires = 4, + .caps = MMC_CAP_4_BIT_DATA, .set_power = n8x0_mmc_set_power, .set_bus_mode = n8x0_mmc_set_bus_mode, .get_cover_state = n8x0_mmc_get_cover_state, diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 87969c7..51493f5 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include @@ -166,7 +167,7 @@ static void __init beagle_display_init(void) static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, - .wires = 8, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, .gpio_wp = 29, }, {} /* Terminator */ diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index f76d9c0..523ba55 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -31,6 +31,7 @@ #include #include +#include #include #include @@ -370,7 +371,7 @@ static struct regulator_init_data omap3evm_vsim = { static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, - .wires = 4, + .caps = MMC_CAP_4_BIT_DATA, .gpio_cd = -EINVAL, .gpio_wp = 63, }, diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c index dd3af2b..2d2e6fc 100644 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ b/arch/arm/mach-omap2/board-omap3pandora.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include @@ -276,14 +277,14 @@ static void pandora_wl1251_init_card(struct mmc_card *card) static struct omap2_hsmmc_info omap3pandora_mmc[] = { { .mmc = 1, - .wires = 4, + .caps = MMC_CAP_4_BIT_DATA, .gpio_cd = -EINVAL, .gpio_wp = 126, .ext_clock = 0, }, { .mmc = 2, - .wires = 4, + .caps = MMC_CAP_4_BIT_DATA, .gpio_cd = -EINVAL, .gpio_wp = 127, .ext_clock = 1, @@ -291,7 +292,7 @@ static struct omap2_hsmmc_info omap3pandora_mmc[] = { }, { .mmc = 3, - .wires = 4, + .caps = MMC_CAP_4_BIT_DATA, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, .init_card = pandora_wl1251_init_card, diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c index bcd01d2..c1b881d 100644 --- a/arch/arm/mach-omap2/board-omap3stalker.c +++ b/arch/arm/mach-omap2/board-omap3stalker.c @@ -26,6 +26,7 @@ #include #include +#include #include #include @@ -275,7 +276,7 @@ static struct regulator_init_data omap3stalker_vsim = { static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, - .wires = 4, + .caps = MMC_CAP_4_BIT_DATA, .gpio_cd = -EINVAL, .gpio_wp = 23, }, diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c index 663c62d..9ab18fd 100644 --- a/arch/arm/mach-omap2/board-omap3touchbook.c +++ b/arch/arm/mach-omap2/board-omap3touchbook.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include @@ -108,7 +109,7 @@ static struct omap_nand_platform_data omap3touchbook_nand_data = { static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, - .wires = 8, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, .gpio_wp = 29, }, {} /* Terminator */ diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index 96f5bbb..0bb2353 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -56,7 +56,7 @@ static struct omap_musb_board_data musb_board_data = { static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, - .wires = 8, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, .gpio_wp = -EINVAL, }, {} /* Terminator */ diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index 4c48436..93441e5 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include @@ -303,13 +304,13 @@ static void __init overo_flash_init(void) static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, - .wires = 4, + .caps = MMC_CAP_4_BIT_DATA, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, }, { .mmc = 2, - .wires = 4, + .caps = MMC_CAP_4_BIT_DATA, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, .transceiver = true, diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index 9a5eb87..a3dbaa7 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -302,7 +302,7 @@ static struct omap2_hsmmc_info mmc[] __initdata = { { .name = "external", .mmc = 1, - .wires = 4, + .caps = MMC_CAP_4_BIT_DATA, .cover_only = true, .gpio_cd = 160, .gpio_wp = -EINVAL, @@ -311,7 +311,8 @@ static struct omap2_hsmmc_info mmc[] __initdata = { { .name = "internal", .mmc = 2, - .wires = 8, /* See also rx51_mmc2_remux */ + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, + /* See also rx51_mmc2_remux */ .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, .nonremovable = true, diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c index 6b39849..e5eac46 100644 --- a/arch/arm/mach-omap2/board-zoom-peripherals.c +++ b/arch/arm/mach-omap2/board-zoom-peripherals.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include @@ -155,14 +156,14 @@ static struct omap2_hsmmc_info mmc[] __initdata = { { .name = "external", .mmc = 1, - .wires = 4, + .caps = MMC_CAP_4_BIT_DATA, .gpio_wp = -EINVAL, .power_saving = true, }, { .name = "internal", .mmc = 2, - .wires = 8, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, .nonremovable = true, diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index dc49c07..9e5d51b 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -694,7 +694,7 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, omap_mux_init_signal("sdmmc_dat0", 0); omap_mux_init_signal("sdmmc_dat_dir0", 0); omap_mux_init_signal("sdmmc_cmd_dir", 0); - if (mmc_controller->slots[0].wires == 4) { + if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) { omap_mux_init_signal("sdmmc_dat1", 0); omap_mux_init_signal("sdmmc_dat2", 0); omap_mux_init_signal("sdmmc_dat3", 0); @@ -722,8 +722,8 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, OMAP_PIN_INPUT_PULLUP); omap_mux_init_signal("sdmmc1_dat0", OMAP_PIN_INPUT_PULLUP); - if (mmc_controller->slots[0].wires == 4 || - mmc_controller->slots[0].wires == 8) { + if (mmc_controller->slots[0].caps & + (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) { omap_mux_init_signal("sdmmc1_dat1", OMAP_PIN_INPUT_PULLUP); omap_mux_init_signal("sdmmc1_dat2", @@ -731,7 +731,8 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, omap_mux_init_signal("sdmmc1_dat3", OMAP_PIN_INPUT_PULLUP); } - if (mmc_controller->slots[0].wires == 8) { + if (mmc_controller->slots[0].caps & + MMC_CAP_8_BIT_DATA) { omap_mux_init_signal("sdmmc1_dat4", OMAP_PIN_INPUT_PULLUP); omap_mux_init_signal("sdmmc1_dat5", @@ -755,8 +756,8 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed * in the board-*.c files */ - if (mmc_controller->slots[0].wires == 4 || - mmc_controller->slots[0].wires == 8) { + if (mmc_controller->slots[0].caps & + (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) { omap_mux_init_signal("sdmmc2_dat1", OMAP_PIN_INPUT_PULLUP); omap_mux_init_signal("sdmmc2_dat2", @@ -764,7 +765,8 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, omap_mux_init_signal("sdmmc2_dat3", OMAP_PIN_INPUT_PULLUP); } - if (mmc_controller->slots[0].wires == 8) { + if (mmc_controller->slots[0].caps & + MMC_CAP_8_BIT_DATA) { omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4", OMAP_PIN_INPUT_PULLUP); omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5", diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c index c8f647b..87ce6ff 100644 --- a/arch/arm/mach-omap2/hsmmc.c +++ b/arch/arm/mach-omap2/hsmmc.c @@ -258,7 +258,7 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) "mmc%islot%i", c->mmc, 1); mmc->slots[0].name = hc->name; mmc->nr_slots = 1; - mmc->slots[0].wires = c->wires; + mmc->slots[0].caps = c->caps; mmc->slots[0].internal_clock = !c->ext_clock; mmc->dma_mask = 0xffffffff; @@ -316,16 +316,20 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) } /* Omap3630 HSMMC1 supports only 4-bit */ - if (cpu_is_omap3630() && c->wires > 4) { - c->wires = 4; - mmc->slots[0].wires = c->wires; + if (cpu_is_omap3630() && + (c->caps & MMC_CAP_8_BIT_DATA)) { + c->caps &= ~MMC_CAP_8_BIT_DATA; + c->caps |= MMC_CAP_4_BIT_DATA; + mmc->slots[0].caps = c->caps; } break; case 2: if (c->ext_clock) c->transceiver = 1; - if (c->transceiver && c->wires > 4) - c->wires = 4; + if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) { + c->caps &= ~MMC_CAP_8_BIT_DATA; + c->caps |= MMC_CAP_4_BIT_DATA; + } /* FALLTHROUGH */ case 3: if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { diff --git a/arch/arm/mach-omap2/hsmmc.h b/arch/arm/mach-omap2/hsmmc.h index 1fe6f01..281e972 100644 --- a/arch/arm/mach-omap2/hsmmc.h +++ b/arch/arm/mach-omap2/hsmmc.h @@ -10,7 +10,8 @@ struct mmc_card; struct omap2_hsmmc_info { u8 mmc; /* controller 1/2/3 */ - u8 wires; /* 1/4/8 wires */ + u32 caps; /* 4/8 wires and any additional host + * capabilities OR'd (ref. linux/mmc/host.h) */ bool transceiver; /* MMC-2 option */ bool ext_clock; /* use external pin for input clock */ bool cover_only; /* No card detect - just cover switch */ diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h index 9b89ec6..4f819fc 100644 --- a/arch/arm/plat-omap/include/plat/mmc.h +++ b/arch/arm/plat-omap/include/plat/mmc.h @@ -73,10 +73,9 @@ struct omap_mmc_platform_data { struct omap_mmc_slot_data { - /* 4 wire signaling is optional, and is used for SD/SDIO/HSMMC; - * 8 wire signaling is also optional, and is used with HSMMC - */ - u8 wires; + /* 4/8 wires and any additional host capabilities + * need to OR'd all capabilities (ref. linux/mmc/host.h) */ + u32 caps; /* * nomux means "standard" muxing is wrong on this board, and -- cgit v1.1 From 6e457bb05c348e196f67005876992ceb5eb0430a Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Wed, 22 Sep 2010 20:40:57 +0200 Subject: update OMAP Kconfig help texts for all supported SoC models update OMAP Kconfig help texts for all supported SoC models Signed-off-by: Lennert Buytenhek Signed-off-by: Tony Lindgren --- arch/arm/Kconfig | 2 +- arch/arm/plat-omap/Kconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 553b7cf..15b603c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -813,7 +813,7 @@ config ARCH_OMAP select GENERIC_CLOCKEVENTS select ARCH_HAS_HOLES_MEMORYMODEL help - Support for TI's OMAP platform (OMAP1 and OMAP2). + Support for TI's OMAP platform (OMAP1/2/3/4). config PLAT_SPEAR bool "ST SPEAr" diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index e39a417..d98c5c0 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig @@ -19,7 +19,7 @@ config ARCH_OMAP2PLUS bool "TI OMAP2/3/4" select COMMON_CLKDEV help - "Systems based on omap24xx, omap34xx or omap44xx" + "Systems based on OMAP2, OMAP3 or OMAP4" endchoice -- cgit v1.1 From 76cf52951ac57a31a453610e0ab5cae50b10502d Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Mon, 27 Sep 2010 14:02:54 -0600 Subject: OMAP4: clocks: Update clock tree for ES2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch updates the clock tree with all the changes in OMAP4430 ES2. clock nodes added -1- tie_low_clock_ck -2- abe_dpll_bypass_clk_mux_ck clock nodes deleted -1- dpll_sys_ref_clk -2- per_sgx_fclk -3- usbphyocp2scp_ick Signed-off-by: Rajendra Nayak Signed-off-by: Benoît Cousson [paul@pwsan.com: added comment re ES1 clocks to top of file] Signed-off-by: Paul Walmsley Cc: Kevin Hilman --- arch/arm/mach-omap2/clock44xx_data.c | 172 +++++++++++++++-------------------- 1 file changed, 74 insertions(+), 98 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index e10db7a..f39552b 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -17,6 +17,10 @@ * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. + * + * XXX Some of the ES1 clocks have been removed/changed; once support + * is added for discriminating clocks by ES level, these should be added back + * in. */ #include @@ -175,21 +179,27 @@ static struct clk sys_clkin_ck = { .recalc = &omap2_clksel_recalc, }; +static struct clk tie_low_clock_ck = { + .name = "tie_low_clock_ck", + .rate = 0, + .ops = &clkops_null, +}; + static struct clk utmi_phy_clkout_ck = { .name = "utmi_phy_clkout_ck", - .rate = 12000000, + .rate = 60000000, .ops = &clkops_null, }; static struct clk xclk60mhsp1_ck = { .name = "xclk60mhsp1_ck", - .rate = 12000000, + .rate = 60000000, .ops = &clkops_null, }; static struct clk xclk60mhsp2_ck = { .name = "xclk60mhsp2_ck", - .rate = 12000000, + .rate = 60000000, .ops = &clkops_null, }; @@ -201,39 +211,23 @@ static struct clk xclk60motg_ck = { /* Module clocks and DPLL outputs */ -static const struct clksel_rate div2_1to2_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_4430 }, - { .div = 2, .val = 1, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; - -static const struct clksel dpll_sys_ref_clk_div[] = { - { .parent = &sys_clkin_ck, .rates = div2_1to2_rates }, +static const struct clksel abe_dpll_bypass_clk_mux_sel[] = { + { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, + { .parent = &sys_32k_ck, .rates = div_1_1_rates }, { .parent = NULL }, }; -static struct clk dpll_sys_ref_clk = { - .name = "dpll_sys_ref_clk", +static struct clk abe_dpll_bypass_clk_mux_ck = { + .name = "abe_dpll_bypass_clk_mux_ck", .parent = &sys_clkin_ck, - .clksel = dpll_sys_ref_clk_div, - .clksel_reg = OMAP4430_CM_DPLL_SYS_REF_CLKSEL, - .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static const struct clksel abe_dpll_refclk_mux_sel[] = { - { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates }, - { .parent = &sys_32k_ck, .rates = div_1_1_rates }, - { .parent = NULL }, + .recalc = &followparent_recalc, }; static struct clk abe_dpll_refclk_mux_ck = { .name = "abe_dpll_refclk_mux_ck", - .parent = &dpll_sys_ref_clk, - .clksel = abe_dpll_refclk_mux_sel, + .parent = &sys_clkin_ck, + .clksel = abe_dpll_bypass_clk_mux_sel, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_ABE_PLL_REF_CLKSEL, .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, @@ -244,7 +238,7 @@ static struct clk abe_dpll_refclk_mux_ck = { /* DPLL_ABE */ static struct dpll_data dpll_abe_dd = { .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE, - .clk_bypass = &sys_clkin_ck, + .clk_bypass = &abe_dpll_bypass_clk_mux_ck, .clk_ref = &abe_dpll_refclk_mux_ck, .control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), @@ -310,6 +304,12 @@ static struct clk abe_clk = { .set_rate = &omap2_clksel_set_rate, }; +static const struct clksel_rate div2_1to2_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_4430 }, + { .div = 2, .val = 1, .flags = RATE_IN_4430 }, + { .div = 0 }, +}; + static const struct clksel aess_fclk_div[] = { { .parent = &abe_clk, .rates = div2_1to2_rates }, { .parent = NULL }, @@ -380,14 +380,14 @@ static struct clk dpll_abe_m3_ck = { }; static const struct clksel core_hsd_byp_clk_mux_sel[] = { - { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates }, + { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, { .parent = &dpll_abe_m3_ck, .rates = div_1_1_rates }, { .parent = NULL }, }; static struct clk core_hsd_byp_clk_mux_ck = { .name = "core_hsd_byp_clk_mux_ck", - .parent = &dpll_sys_ref_clk, + .parent = &sys_clkin_ck, .clksel = core_hsd_byp_clk_mux_sel, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_CORE, @@ -400,7 +400,7 @@ static struct clk core_hsd_byp_clk_mux_ck = { static struct dpll_data dpll_core_dd = { .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE, .clk_bypass = &core_hsd_byp_clk_mux_ck, - .clk_ref = &dpll_sys_ref_clk, + .clk_ref = &sys_clkin_ck, .control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_CORE, @@ -418,7 +418,7 @@ static struct dpll_data dpll_core_dd = { static struct clk dpll_core_ck = { .name = "dpll_core_ck", - .parent = &dpll_sys_ref_clk, + .parent = &sys_clkin_ck, .dpll_data = &dpll_core_dd, .init = &omap2_init_dpll_parent, .ops = &clkops_null, @@ -596,14 +596,14 @@ static struct clk dpll_core_m7_ck = { }; static const struct clksel iva_hsd_byp_clk_mux_sel[] = { - { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates }, + { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, { .parent = &div_iva_hs_clk, .rates = div_1_1_rates }, { .parent = NULL }, }; static struct clk iva_hsd_byp_clk_mux_ck = { .name = "iva_hsd_byp_clk_mux_ck", - .parent = &dpll_sys_ref_clk, + .parent = &sys_clkin_ck, .ops = &clkops_null, .recalc = &followparent_recalc, }; @@ -612,7 +612,7 @@ static struct clk iva_hsd_byp_clk_mux_ck = { static struct dpll_data dpll_iva_dd = { .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA, .clk_bypass = &iva_hsd_byp_clk_mux_ck, - .clk_ref = &dpll_sys_ref_clk, + .clk_ref = &sys_clkin_ck, .control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_IVA, @@ -630,7 +630,7 @@ static struct dpll_data dpll_iva_dd = { static struct clk dpll_iva_ck = { .name = "dpll_iva_ck", - .parent = &dpll_sys_ref_clk, + .parent = &sys_clkin_ck, .dpll_data = &dpll_iva_dd, .init = &omap2_init_dpll_parent, .ops = &clkops_omap3_noncore_dpll_ops, @@ -672,7 +672,7 @@ static struct clk dpll_iva_m5_ck = { static struct dpll_data dpll_mpu_dd = { .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU, .clk_bypass = &div_mpu_hs_clk, - .clk_ref = &dpll_sys_ref_clk, + .clk_ref = &sys_clkin_ck, .control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_MPU, @@ -690,7 +690,7 @@ static struct dpll_data dpll_mpu_dd = { static struct clk dpll_mpu_ck = { .name = "dpll_mpu_ck", - .parent = &dpll_sys_ref_clk, + .parent = &sys_clkin_ck, .dpll_data = &dpll_mpu_dd, .init = &omap2_init_dpll_parent, .ops = &clkops_omap3_noncore_dpll_ops, @@ -724,14 +724,14 @@ static struct clk per_hs_clk_div_ck = { }; static const struct clksel per_hsd_byp_clk_mux_sel[] = { - { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates }, + { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates }, { .parent = NULL }, }; static struct clk per_hsd_byp_clk_mux_ck = { .name = "per_hsd_byp_clk_mux_ck", - .parent = &dpll_sys_ref_clk, + .parent = &sys_clkin_ck, .clksel = per_hsd_byp_clk_mux_sel, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_PER, @@ -744,7 +744,7 @@ static struct clk per_hsd_byp_clk_mux_ck = { static struct dpll_data dpll_per_dd = { .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER, .clk_bypass = &per_hsd_byp_clk_mux_ck, - .clk_ref = &dpll_sys_ref_clk, + .clk_ref = &sys_clkin_ck, .control_reg = OMAP4430_CM_CLKMODE_DPLL_PER, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_PER, @@ -762,7 +762,7 @@ static struct dpll_data dpll_per_dd = { static struct clk dpll_per_ck = { .name = "dpll_per_ck", - .parent = &dpll_sys_ref_clk, + .parent = &sys_clkin_ck, .dpll_data = &dpll_per_dd, .init = &omap2_init_dpll_parent, .ops = &clkops_omap3_noncore_dpll_ops, @@ -858,8 +858,8 @@ static struct clk dpll_per_m7_ck = { /* DPLL_UNIPRO */ static struct dpll_data dpll_unipro_dd = { .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_UNIPRO, - .clk_bypass = &dpll_sys_ref_clk, - .clk_ref = &dpll_sys_ref_clk, + .clk_bypass = &sys_clkin_ck, + .clk_ref = &sys_clkin_ck, .control_reg = OMAP4430_CM_CLKMODE_DPLL_UNIPRO, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO, @@ -877,7 +877,7 @@ static struct dpll_data dpll_unipro_dd = { static struct clk dpll_unipro_ck = { .name = "dpll_unipro_ck", - .parent = &dpll_sys_ref_clk, + .parent = &sys_clkin_ck, .dpll_data = &dpll_unipro_dd, .init = &omap2_init_dpll_parent, .ops = &clkops_omap3_noncore_dpll_ops, @@ -914,7 +914,7 @@ static struct clk usb_hs_clk_div_ck = { static struct dpll_data dpll_usb_dd = { .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB, .clk_bypass = &usb_hs_clk_div_ck, - .clk_ref = &dpll_sys_ref_clk, + .clk_ref = &sys_clkin_ck, .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB, @@ -933,7 +933,7 @@ static struct dpll_data dpll_usb_dd = { static struct clk dpll_usb_ck = { .name = "dpll_usb_ck", - .parent = &dpll_sys_ref_clk, + .parent = &sys_clkin_ck, .dpll_data = &dpll_usb_dd, .init = &omap2_init_dpll_parent, .ops = &clkops_omap3_noncore_dpll_ops, @@ -1222,7 +1222,7 @@ static struct clk per_abe_24m_fclk = { static const struct clksel pmd_stm_clock_mux_sel[] = { { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates }, - { .parent = &dpll_per_m7_ck, .rates = div_1_2_rates }, + { .parent = &tie_low_clock_ck, .rates = div_1_2_rates }, { .parent = NULL }, }; @@ -1240,10 +1240,15 @@ static struct clk pmd_trace_clk_mux_ck = { .recalc = &followparent_recalc, }; +static const struct clksel syc_clk_div_div[] = { + { .parent = &sys_clkin_ck, .rates = div2_1to2_rates }, + { .parent = NULL }, +}; + static struct clk syc_clk_div_ck = { .name = "syc_clk_div_ck", .parent = &sys_clkin_ck, - .clksel = dpll_sys_ref_clk_div, + .clksel = syc_clk_div_div, .clksel_reg = OMAP4430_CM_ABE_DSS_SYS_CLKSEL, .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, .ops = &clkops_null, @@ -1407,26 +1412,9 @@ static struct clk fdif_fck = { .clkdm_name = "iss_clkdm", }; -static const struct clksel per_sgx_fclk_div[] = { - { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates }, - { .parent = NULL }, -}; - -static struct clk per_sgx_fclk = { - .name = "per_sgx_fclk", - .parent = &dpll_per_m2x2_ck, - .clksel = per_sgx_fclk_div, - .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_PER_192M_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - static const struct clksel sgx_clk_mux_sel[] = { { .parent = &dpll_core_m7_ck, .rates = div_1_0_rates }, - { .parent = &per_sgx_fclk, .rates = div_1_1_rates }, + { .parent = &dpll_per_m7_ck, .rates = div_1_1_rates }, { .parent = NULL }, }; @@ -1515,12 +1503,6 @@ static struct clk gpmc_ick = { .recalc = &followparent_recalc, }; -static const struct clksel dmt1_clk_mux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &sys_32k_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - /* * Merged dmt1_clk_mux into gptimer1 * gptimer1 renamed temporarily into gpt1 to match OMAP3 convention @@ -1528,7 +1510,7 @@ static const struct clksel dmt1_clk_mux_sel[] = { static struct clk gpt1_fck = { .name = "gpt1_fck", .parent = &sys_clkin_ck, - .clksel = dmt1_clk_mux_sel, + .clksel = abe_dpll_bypass_clk_mux_sel, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_MASK, @@ -1546,7 +1528,7 @@ static struct clk gpt1_fck = { static struct clk gpt10_fck = { .name = "gpt10_fck", .parent = &sys_clkin_ck, - .clksel = dmt1_clk_mux_sel, + .clksel = abe_dpll_bypass_clk_mux_sel, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_MASK, @@ -1564,7 +1546,7 @@ static struct clk gpt10_fck = { static struct clk gpt11_fck = { .name = "gpt11_fck", .parent = &sys_clkin_ck, - .clksel = dmt1_clk_mux_sel, + .clksel = abe_dpll_bypass_clk_mux_sel, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_MASK, @@ -1582,7 +1564,7 @@ static struct clk gpt11_fck = { static struct clk gpt2_fck = { .name = "gpt2_fck", .parent = &sys_clkin_ck, - .clksel = dmt1_clk_mux_sel, + .clksel = abe_dpll_bypass_clk_mux_sel, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_MASK, @@ -1600,7 +1582,7 @@ static struct clk gpt2_fck = { static struct clk gpt3_fck = { .name = "gpt3_fck", .parent = &sys_clkin_ck, - .clksel = dmt1_clk_mux_sel, + .clksel = abe_dpll_bypass_clk_mux_sel, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_MASK, @@ -1618,7 +1600,7 @@ static struct clk gpt3_fck = { static struct clk gpt4_fck = { .name = "gpt4_fck", .parent = &sys_clkin_ck, - .clksel = dmt1_clk_mux_sel, + .clksel = abe_dpll_bypass_clk_mux_sel, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_MASK, @@ -1714,7 +1696,7 @@ static struct clk gpt8_fck = { static struct clk gpt9_fck = { .name = "gpt9_fck", .parent = &sys_clkin_ck, - .clksel = dmt1_clk_mux_sel, + .clksel = abe_dpll_bypass_clk_mux_sel, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_MASK, @@ -1735,11 +1717,16 @@ static struct clk hdq1w_fck = { .recalc = &followparent_recalc, }; +static const struct clksel hsi_fclk_div[] = { + { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates }, + { .parent = NULL }, +}; + /* Merged hsi_fclk into hsi */ static struct clk hsi_ick = { .name = "hsi_ick", .parent = &dpll_per_m2x2_ck, - .clksel = per_sgx_fclk_div, + .clksel = hsi_fclk_div, .clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, .clksel_mask = OMAP4430_CLKSEL_24_25_MASK, .ops = &clkops_omap2_dflt, @@ -2315,21 +2302,11 @@ static struct clk usb_tll_ick = { .recalc = &followparent_recalc, }; -static struct clk usbphyocp2scp_ick = { - .name = "usbphyocp2scp_ick", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "l3_init_clkdm", - .parent = &l4_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk usim_fck = { - .name = "usim_fck", +static struct clk usim_ick = { + .name = "usim_ick", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL, .clkdm_name = "l4_wkup_clkdm", .parent = &sys_32k_ck, .recalc = &followparent_recalc, @@ -2483,11 +2460,12 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_443X), CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_443X), CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_443X), + CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck, CK_443X), CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_443X), CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_443X), CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_443X), CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_443X), - CLK(NULL, "dpll_sys_ref_clk", &dpll_sys_ref_clk, CK_443X), + CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck, CK_443X), CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X), CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X), CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X), @@ -2566,7 +2544,6 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "emif1_ick", &emif1_ick, CK_443X), CLK(NULL, "emif2_ick", &emif2_ick, CK_443X), CLK(NULL, "fdif_fck", &fdif_fck, CK_443X), - CLK(NULL, "per_sgx_fclk", &per_sgx_fclk, CK_443X), CLK(NULL, "gfx_fck", &gfx_fck, CK_443X), CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X), CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X), @@ -2637,8 +2614,7 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X), CLK("musb_hdrc", "ick", &usb_otg_ick, CK_443X), CLK(NULL, "usb_tll_ick", &usb_tll_ick, CK_443X), - CLK(NULL, "usbphyocp2scp_ick", &usbphyocp2scp_ick, CK_443X), - CLK(NULL, "usim_fck", &usim_fck, CK_443X), + CLK(NULL, "usim_ick", &usim_ick, CK_443X), CLK("omap_wdt", "fck", &wdt2_fck, CK_443X), CLK(NULL, "wdt3_fck", &wdt3_fck, CK_443X), CLK(NULL, "otg_60m_gfclk_ck", &otg_60m_gfclk_ck, CK_443X), -- cgit v1.1 From 0e43327191986e88efdc8717084aeb22db2cc8a9 Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Mon, 27 Sep 2010 14:02:54 -0600 Subject: OMAP4: clock: Fix clock names and align with hwmod names The OMAP4 hwmod data introduced the new naming convention for TI IPs (See patch OMAP4: hwmod: Add partial hwmod support for OMAP4430 ES1.0) The leaf clock names are using the same IP name and thus must be modified to match the clock populated in the hwmod data. - Fix some leaf clocks nodes that were using a _iclk instead of the _fclk prefix. - Fix some wrong interface clock name for master IPs connected to interconnect. Please not that due to the fact that nodes are sorted by name, the name change will introduce a quite ugly diff a little bit hard to follow. Timers clock con_id is still using the old gptX_fck name until the gptimer driver is updated to omap_device framework. Timers entries in hwmods DB are still disabled until the migration if timer to platform_driver + omap_hwmod. Signed-off-by: Benoit Cousson [paul@pwsan.com: manually resolved conflicts with Rajendra's clock patch] Signed-off-by: Paul Walmsley Cc: Rajendra Nayak --- arch/arm/mach-omap2/clock44xx_data.c | 665 ++++++++++++++++------------------- 1 file changed, 310 insertions(+), 355 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index f39552b..8296ae0 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -26,7 +26,6 @@ #include #include #include - #include #include @@ -914,6 +913,7 @@ static struct clk usb_hs_clk_div_ck = { static struct dpll_data dpll_usb_dd = { .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB, .clk_bypass = &usb_hs_clk_div_ck, + .flags = DPLL_J_TYPE | DPLL_NO_DCO_SEL, .clk_ref = &sys_clkin_ck, .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), @@ -927,7 +927,6 @@ static struct dpll_data dpll_usb_dd = { .max_multiplier = OMAP4430_MAX_DPLL_MULT, .max_divider = OMAP4430_MAX_DPLL_DIV, .min_divider = 1, - .flags = DPLL_J_TYPE | DPLL_NO_DCO_SEL }; @@ -1289,16 +1288,6 @@ static struct clk aess_fck = { .recalc = &followparent_recalc, }; -static struct clk cust_efuse_fck = { - .name = "cust_efuse_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_cefuse_clkdm", - .parent = &sys_clkin_ck, - .recalc = &followparent_recalc, -}; - static struct clk des3des_fck = { .name = "des3des_fck", .ops = &clkops_omap2_dflt, @@ -1349,6 +1338,16 @@ static struct clk dmic_fck = { .clkdm_name = "abe_clkdm", }; +static struct clk dsp_fck = { + .name = "dsp_fck", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL, + .clkdm_name = "tesla_clkdm", + .parent = &dpll_iva_m4_ck, + .recalc = &followparent_recalc, +}; + static struct clk dss_fck = { .name = "dss_fck", .ops = &clkops_omap2_dflt, @@ -1359,18 +1358,18 @@ static struct clk dss_fck = { .recalc = &followparent_recalc, }; -static struct clk ducati_ick = { - .name = "ducati_ick", +static struct clk efuse_ctrl_cust_fck = { + .name = "efuse_ctrl_cust_fck", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "ducati_clkdm", - .parent = &ducati_clk_mux_ck, + .enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "l4_cefuse_clkdm", + .parent = &sys_clkin_ck, .recalc = &followparent_recalc, }; -static struct clk emif1_ick = { - .name = "emif1_ick", +static struct clk emif1_fck = { + .name = "emif1_fck", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, @@ -1380,8 +1379,8 @@ static struct clk emif1_ick = { .recalc = &followparent_recalc, }; -static struct clk emif2_ick = { - .name = "emif2_ick", +static struct clk emif2_fck = { + .name = "emif2_fck", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, @@ -1412,25 +1411,14 @@ static struct clk fdif_fck = { .clkdm_name = "iss_clkdm", }; -static const struct clksel sgx_clk_mux_sel[] = { - { .parent = &dpll_core_m7_ck, .rates = div_1_0_rates }, - { .parent = &dpll_per_m7_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -/* Merged sgx_clk_mux into gfx */ -static struct clk gfx_fck = { - .name = "gfx_fck", - .parent = &dpll_core_m7_ck, - .clksel = sgx_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK, +static struct clk fpka_fck = { + .name = "fpka_fck", .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, + .enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l3_gfx_clkdm", + .clkdm_name = "l4_secure_clkdm", + .parent = &l4_div_ck, + .recalc = &followparent_recalc, }; static struct clk gpio1_ick = { @@ -1503,208 +1491,25 @@ static struct clk gpmc_ick = { .recalc = &followparent_recalc, }; -/* - * Merged dmt1_clk_mux into gptimer1 - * gptimer1 renamed temporarily into gpt1 to match OMAP3 convention - */ -static struct clk gpt1_fck = { - .name = "gpt1_fck", - .parent = &sys_clkin_ck, - .clksel = abe_dpll_bypass_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_wkup_clkdm", -}; - -/* - * Merged cm2_dm10_mux into gptimer10 - * gptimer10 renamed temporarily into gpt10 to match OMAP3 convention - */ -static struct clk gpt10_fck = { - .name = "gpt10_fck", - .parent = &sys_clkin_ck, - .clksel = abe_dpll_bypass_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", -}; - -/* - * Merged cm2_dm11_mux into gptimer11 - * gptimer11 renamed temporarily into gpt11 to match OMAP3 convention - */ -static struct clk gpt11_fck = { - .name = "gpt11_fck", - .parent = &sys_clkin_ck, - .clksel = abe_dpll_bypass_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", -}; - -/* - * Merged cm2_dm2_mux into gptimer2 - * gptimer2 renamed temporarily into gpt2 to match OMAP3 convention - */ -static struct clk gpt2_fck = { - .name = "gpt2_fck", - .parent = &sys_clkin_ck, - .clksel = abe_dpll_bypass_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", -}; - -/* - * Merged cm2_dm3_mux into gptimer3 - * gptimer3 renamed temporarily into gpt3 to match OMAP3 convention - */ -static struct clk gpt3_fck = { - .name = "gpt3_fck", - .parent = &sys_clkin_ck, - .clksel = abe_dpll_bypass_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", -}; - -/* - * Merged cm2_dm4_mux into gptimer4 - * gptimer4 renamed temporarily into gpt4 to match OMAP3 convention - */ -static struct clk gpt4_fck = { - .name = "gpt4_fck", - .parent = &sys_clkin_ck, - .clksel = abe_dpll_bypass_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", -}; - -static const struct clksel timer5_sync_mux_sel[] = { - { .parent = &syc_clk_div_ck, .rates = div_1_0_rates }, - { .parent = &sys_32k_ck, .rates = div_1_1_rates }, +static const struct clksel sgx_clk_mux_sel[] = { + { .parent = &dpll_core_m7_ck, .rates = div_1_0_rates }, + { .parent = &dpll_per_m7_ck, .rates = div_1_1_rates }, { .parent = NULL }, }; -/* - * Merged timer5_sync_mux into gptimer5 - * gptimer5 renamed temporarily into gpt5 to match OMAP3 convention - */ -static struct clk gpt5_fck = { - .name = "gpt5_fck", - .parent = &syc_clk_div_ck, - .clksel = timer5_sync_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", -}; - -/* - * Merged timer6_sync_mux into gptimer6 - * gptimer6 renamed temporarily into gpt6 to match OMAP3 convention - */ -static struct clk gpt6_fck = { - .name = "gpt6_fck", - .parent = &syc_clk_div_ck, - .clksel = timer5_sync_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", -}; - -/* - * Merged timer7_sync_mux into gptimer7 - * gptimer7 renamed temporarily into gpt7 to match OMAP3 convention - */ -static struct clk gpt7_fck = { - .name = "gpt7_fck", - .parent = &syc_clk_div_ck, - .clksel = timer5_sync_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", -}; - -/* - * Merged timer8_sync_mux into gptimer8 - * gptimer8 renamed temporarily into gpt8 to match OMAP3 convention - */ -static struct clk gpt8_fck = { - .name = "gpt8_fck", - .parent = &syc_clk_div_ck, - .clksel = timer5_sync_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", -}; - -/* - * Merged cm2_dm9_mux into gptimer9 - * gptimer9 renamed temporarily into gpt9 to match OMAP3 convention - */ -static struct clk gpt9_fck = { - .name = "gpt9_fck", - .parent = &sys_clkin_ck, - .clksel = abe_dpll_bypass_clk_mux_sel, +/* Merged sgx_clk_mux into gpu */ +static struct clk gpu_fck = { + .name = "gpu_fck", + .parent = &dpll_core_m7_ck, + .clksel = sgx_clk_mux_sel, .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_MASK, + .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK, .ops = &clkops_omap2_dflt, .recalc = &omap2_clksel_recalc, - .enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, + .enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_per_clkdm", + .clkdm_name = "l3_gfx_clkdm", }; static struct clk hdq1w_fck = { @@ -1723,8 +1528,8 @@ static const struct clksel hsi_fclk_div[] = { }; /* Merged hsi_fclk into hsi */ -static struct clk hsi_ick = { - .name = "hsi_ick", +static struct clk hsi_fck = { + .name = "hsi_fck", .parent = &dpll_per_m2x2_ck, .clksel = hsi_fclk_div, .clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, @@ -1778,6 +1583,16 @@ static struct clk i2c4_fck = { .recalc = &followparent_recalc, }; +static struct clk ipu_fck = { + .name = "ipu_fck", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL, + .clkdm_name = "ducati_clkdm", + .parent = &ducati_clk_mux_ck, + .recalc = &followparent_recalc, +}; + static struct clk iss_fck = { .name = "iss_fck", .ops = &clkops_omap2_dflt, @@ -1788,8 +1603,8 @@ static struct clk iss_fck = { .recalc = &followparent_recalc, }; -static struct clk ivahd_ick = { - .name = "ivahd_ick", +static struct clk iva_fck = { + .name = "iva_fck", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, @@ -1798,8 +1613,8 @@ static struct clk ivahd_ick = { .recalc = &followparent_recalc, }; -static struct clk keyboard_fck = { - .name = "keyboard_fck", +static struct clk kbd_fck = { + .name = "kbd_fck", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, @@ -1808,8 +1623,8 @@ static struct clk keyboard_fck = { .recalc = &followparent_recalc, }; -static struct clk l3_instr_interconnect_ick = { - .name = "l3_instr_interconnect_ick", +static struct clk l3_instr_ick = { + .name = "l3_instr_ick", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, @@ -1818,8 +1633,8 @@ static struct clk l3_instr_interconnect_ick = { .recalc = &followparent_recalc, }; -static struct clk l3_interconnect_3_ick = { - .name = "l3_interconnect_3_ick", +static struct clk l3_main_3_ick = { + .name = "l3_main_3_ick", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, @@ -1992,6 +1807,16 @@ static struct clk mcbsp4_fck = { .clkdm_name = "l4_per_clkdm", }; +static struct clk mcpdm_fck = { + .name = "mcpdm_fck", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "abe_clkdm", + .parent = &pad_clks_ck, + .recalc = &followparent_recalc, +}; + static struct clk mcspi1_fck = { .name = "mcspi1_fck", .ops = &clkops_omap2_dflt, @@ -2092,8 +1917,8 @@ static struct clk mmc5_fck = { .recalc = &followparent_recalc, }; -static struct clk ocp_wp1_ick = { - .name = "ocp_wp1_ick", +static struct clk ocp_wp_noc_ick = { + .name = "ocp_wp_noc_ick", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, @@ -2102,26 +1927,6 @@ static struct clk ocp_wp1_ick = { .recalc = &followparent_recalc, }; -static struct clk pdm_fck = { - .name = "pdm_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "abe_clkdm", - .parent = &pad_clks_ck, - .recalc = &followparent_recalc, -}; - -static struct clk pkaeip29_fck = { - .name = "pkaeip29_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l4_secure_clkdm", - .parent = &l4_div_ck, - .recalc = &followparent_recalc, -}; - static struct clk rng_ick = { .name = "rng_ick", .ops = &clkops_omap2_dflt, @@ -2132,8 +1937,8 @@ static struct clk rng_ick = { .recalc = &followparent_recalc, }; -static struct clk sha2md51_fck = { - .name = "sha2md51_fck", +static struct clk sha2md5_fck = { + .name = "sha2md5_fck", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, @@ -2142,8 +1947,8 @@ static struct clk sha2md51_fck = { .recalc = &followparent_recalc, }; -static struct clk sl2_ick = { - .name = "sl2_ick", +static struct clk sl2if_ick = { + .name = "sl2if_ick", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, @@ -2172,8 +1977,8 @@ static struct clk slimbus2_fck = { .recalc = &followparent_recalc, }; -static struct clk sr_core_fck = { - .name = "sr_core_fck", +static struct clk smartreflex_core_fck = { + .name = "smartreflex_core_fck", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, @@ -2182,8 +1987,8 @@ static struct clk sr_core_fck = { .recalc = &followparent_recalc, }; -static struct clk sr_iva_fck = { - .name = "sr_iva_fck", +static struct clk smartreflex_iva_fck = { + .name = "smartreflex_iva_fck", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, @@ -2192,8 +1997,8 @@ static struct clk sr_iva_fck = { .recalc = &followparent_recalc, }; -static struct clk sr_mpu_fck = { - .name = "sr_mpu_fck", +static struct clk smartreflex_mpu_fck = { + .name = "smartreflex_mpu_fck", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, @@ -2202,14 +2007,175 @@ static struct clk sr_mpu_fck = { .recalc = &followparent_recalc, }; -static struct clk tesla_ick = { - .name = "tesla_ick", +/* Merged dmt1_clk_mux into timer1 */ +static struct clk timer1_fck = { + .name = "timer1_fck", + .parent = &sys_clkin_ck, + .clksel = abe_dpll_bypass_clk_mux_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_MASK, .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "tesla_clkdm", - .parent = &dpll_iva_m4_ck, - .recalc = &followparent_recalc, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "l4_wkup_clkdm", +}; + +/* Merged cm2_dm10_mux into timer10 */ +static struct clk timer10_fck = { + .name = "timer10_fck", + .parent = &sys_clkin_ck, + .clksel = abe_dpll_bypass_clk_mux_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_MASK, + .ops = &clkops_omap2_dflt, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "l4_per_clkdm", +}; + +/* Merged cm2_dm11_mux into timer11 */ +static struct clk timer11_fck = { + .name = "timer11_fck", + .parent = &sys_clkin_ck, + .clksel = abe_dpll_bypass_clk_mux_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_MASK, + .ops = &clkops_omap2_dflt, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "l4_per_clkdm", +}; + +/* Merged cm2_dm2_mux into timer2 */ +static struct clk timer2_fck = { + .name = "timer2_fck", + .parent = &sys_clkin_ck, + .clksel = abe_dpll_bypass_clk_mux_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_MASK, + .ops = &clkops_omap2_dflt, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "l4_per_clkdm", +}; + +/* Merged cm2_dm3_mux into timer3 */ +static struct clk timer3_fck = { + .name = "timer3_fck", + .parent = &sys_clkin_ck, + .clksel = abe_dpll_bypass_clk_mux_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_MASK, + .ops = &clkops_omap2_dflt, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "l4_per_clkdm", +}; + +/* Merged cm2_dm4_mux into timer4 */ +static struct clk timer4_fck = { + .name = "timer4_fck", + .parent = &sys_clkin_ck, + .clksel = abe_dpll_bypass_clk_mux_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_MASK, + .ops = &clkops_omap2_dflt, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "l4_per_clkdm", +}; + +static const struct clksel timer5_sync_mux_sel[] = { + { .parent = &syc_clk_div_ck, .rates = div_1_0_rates }, + { .parent = &sys_32k_ck, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + +/* Merged timer5_sync_mux into timer5 */ +static struct clk timer5_fck = { + .name = "timer5_fck", + .parent = &syc_clk_div_ck, + .clksel = timer5_sync_mux_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_MASK, + .ops = &clkops_omap2_dflt, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "abe_clkdm", +}; + +/* Merged timer6_sync_mux into timer6 */ +static struct clk timer6_fck = { + .name = "timer6_fck", + .parent = &syc_clk_div_ck, + .clksel = timer5_sync_mux_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_MASK, + .ops = &clkops_omap2_dflt, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "abe_clkdm", +}; + +/* Merged timer7_sync_mux into timer7 */ +static struct clk timer7_fck = { + .name = "timer7_fck", + .parent = &syc_clk_div_ck, + .clksel = timer5_sync_mux_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_MASK, + .ops = &clkops_omap2_dflt, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "abe_clkdm", +}; + +/* Merged timer8_sync_mux into timer8 */ +static struct clk timer8_fck = { + .name = "timer8_fck", + .parent = &syc_clk_div_ck, + .clksel = timer5_sync_mux_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_MASK, + .ops = &clkops_omap2_dflt, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "abe_clkdm", +}; + +/* Merged cm2_dm9_mux into timer9 */ +static struct clk timer9_fck = { + .name = "timer9_fck", + .parent = &sys_clkin_ck, + .clksel = abe_dpll_bypass_clk_mux_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_MASK, + .ops = &clkops_omap2_dflt, + .recalc = &omap2_clksel_recalc, + .enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, + .enable_bit = OMAP4430_MODULEMODE_SWCTRL, + .clkdm_name = "l4_per_clkdm", }; static struct clk uart1_fck = { @@ -2252,18 +2218,18 @@ static struct clk uart4_fck = { .recalc = &followparent_recalc, }; -static struct clk unipro1_fck = { - .name = "unipro1_fck", +static struct clk usb_host_fs_fck = { + .name = "usb_host_fs_fck", .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL, + .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, .clkdm_name = "l3_init_clkdm", - .parent = &func_96m_fclk, + .parent = &func_48mc_fclk, .recalc = &followparent_recalc, }; -static struct clk usb_host_fck = { - .name = "usb_host_fck", +static struct clk usb_host_hs_fck = { + .name = "usb_host_hs_fck", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, @@ -2272,18 +2238,8 @@ static struct clk usb_host_fck = { .recalc = &followparent_recalc, }; -static struct clk usb_host_fs_fck = { - .name = "usb_host_fs_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_SWCTRL, - .clkdm_name = "l3_init_clkdm", - .parent = &func_48mc_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk usb_otg_ick = { - .name = "usb_otg_ick", +static struct clk usb_otg_hs_ick = { + .name = "usb_otg_hs_ick", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, @@ -2292,8 +2248,8 @@ static struct clk usb_otg_ick = { .recalc = &followparent_recalc, }; -static struct clk usb_tll_ick = { - .name = "usb_tll_ick", +static struct clk usb_tll_hs_ick = { + .name = "usb_tll_hs_ick", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, @@ -2302,8 +2258,8 @@ static struct clk usb_tll_ick = { .recalc = &followparent_recalc, }; -static struct clk usim_ick = { - .name = "usim_ick", +static struct clk usim_fck = { + .name = "usim_fck", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_HWCTRL, @@ -2312,8 +2268,8 @@ static struct clk usim_ick = { .recalc = &followparent_recalc, }; -static struct clk wdt2_fck = { - .name = "wdt2_fck", +static struct clk wd_timer2_fck = { + .name = "wd_timer2_fck", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, @@ -2322,8 +2278,8 @@ static struct clk wdt2_fck = { .recalc = &followparent_recalc, }; -static struct clk wdt3_fck = { - .name = "wdt3_fck", +static struct clk wd_timer3_fck = { + .name = "wd_timer3_fck", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL, .enable_bit = OMAP4430_MODULEMODE_SWCTRL, @@ -2535,16 +2491,16 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "aes1_fck", &aes1_fck, CK_443X), CLK(NULL, "aes2_fck", &aes2_fck, CK_443X), CLK(NULL, "aess_fck", &aess_fck, CK_443X), - CLK(NULL, "cust_efuse_fck", &cust_efuse_fck, CK_443X), CLK(NULL, "des3des_fck", &des3des_fck, CK_443X), CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), CLK(NULL, "dmic_fck", &dmic_fck, CK_443X), + CLK(NULL, "dsp_fck", &dsp_fck, CK_443X), CLK(NULL, "dss_fck", &dss_fck, CK_443X), - CLK(NULL, "ducati_ick", &ducati_ick, CK_443X), - CLK(NULL, "emif1_ick", &emif1_ick, CK_443X), - CLK(NULL, "emif2_ick", &emif2_ick, CK_443X), + CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X), + CLK(NULL, "emif1_fck", &emif1_fck, CK_443X), + CLK(NULL, "emif2_fck", &emif2_fck, CK_443X), CLK(NULL, "fdif_fck", &fdif_fck, CK_443X), - CLK(NULL, "gfx_fck", &gfx_fck, CK_443X), + CLK(NULL, "fpka_fck", &fpka_fck, CK_443X), CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X), CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X), CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X), @@ -2552,28 +2508,19 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X), CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X), CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X), - CLK(NULL, "gpt1_fck", &gpt1_fck, CK_443X), - CLK(NULL, "gpt10_fck", &gpt10_fck, CK_443X), - CLK(NULL, "gpt11_fck", &gpt11_fck, CK_443X), - CLK(NULL, "gpt2_fck", &gpt2_fck, CK_443X), - CLK(NULL, "gpt3_fck", &gpt3_fck, CK_443X), - CLK(NULL, "gpt4_fck", &gpt4_fck, CK_443X), - CLK(NULL, "gpt5_fck", &gpt5_fck, CK_443X), - CLK(NULL, "gpt6_fck", &gpt6_fck, CK_443X), - CLK(NULL, "gpt7_fck", &gpt7_fck, CK_443X), - CLK(NULL, "gpt8_fck", &gpt8_fck, CK_443X), - CLK(NULL, "gpt9_fck", &gpt9_fck, CK_443X), + CLK(NULL, "gpu_fck", &gpu_fck, CK_443X), CLK("omap2_hdq.0", "fck", &hdq1w_fck, CK_443X), - CLK(NULL, "hsi_ick", &hsi_ick, CK_443X), + CLK(NULL, "hsi_fck", &hsi_fck, CK_443X), CLK("i2c_omap.1", "fck", &i2c1_fck, CK_443X), CLK("i2c_omap.2", "fck", &i2c2_fck, CK_443X), CLK("i2c_omap.3", "fck", &i2c3_fck, CK_443X), CLK("i2c_omap.4", "fck", &i2c4_fck, CK_443X), + CLK(NULL, "ipu_fck", &ipu_fck, CK_443X), CLK(NULL, "iss_fck", &iss_fck, CK_443X), - CLK(NULL, "ivahd_ick", &ivahd_ick, CK_443X), - CLK(NULL, "keyboard_fck", &keyboard_fck, CK_443X), - CLK(NULL, "l3_instr_interconnect_ick", &l3_instr_interconnect_ick, CK_443X), - CLK(NULL, "l3_interconnect_3_ick", &l3_interconnect_3_ick, CK_443X), + CLK(NULL, "iva_fck", &iva_fck, CK_443X), + CLK(NULL, "kbd_fck", &kbd_fck, CK_443X), + CLK(NULL, "l3_instr_ick", &l3_instr_ick, CK_443X), + CLK(NULL, "l3_main_3_ick", &l3_main_3_ick, CK_443X), CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X), CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X), CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X), @@ -2584,6 +2531,7 @@ static struct omap_clk omap44xx_clks[] = { CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_443X), CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X), CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_443X), + CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_443X), CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_443X), CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_443X), CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_443X), @@ -2593,30 +2541,37 @@ static struct omap_clk omap44xx_clks[] = { CLK("mmci-omap-hs.2", "fck", &mmc3_fck, CK_443X), CLK("mmci-omap-hs.3", "fck", &mmc4_fck, CK_443X), CLK("mmci-omap-hs.4", "fck", &mmc5_fck, CK_443X), - CLK(NULL, "ocp_wp1_ick", &ocp_wp1_ick, CK_443X), - CLK(NULL, "pdm_fck", &pdm_fck, CK_443X), - CLK(NULL, "pkaeip29_fck", &pkaeip29_fck, CK_443X), + CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X), CLK("omap_rng", "ick", &rng_ick, CK_443X), - CLK(NULL, "sha2md51_fck", &sha2md51_fck, CK_443X), - CLK(NULL, "sl2_ick", &sl2_ick, CK_443X), + CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X), + CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X), CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X), CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X), - CLK(NULL, "sr_core_fck", &sr_core_fck, CK_443X), - CLK(NULL, "sr_iva_fck", &sr_iva_fck, CK_443X), - CLK(NULL, "sr_mpu_fck", &sr_mpu_fck, CK_443X), - CLK(NULL, "tesla_ick", &tesla_ick, CK_443X), + CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X), + CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X), + CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X), + CLK(NULL, "gpt1_fck", &timer1_fck, CK_443X), + CLK(NULL, "gpt10_fck", &timer10_fck, CK_443X), + CLK(NULL, "gpt11_fck", &timer11_fck, CK_443X), + CLK(NULL, "gpt2_fck", &timer2_fck, CK_443X), + CLK(NULL, "gpt3_fck", &timer3_fck, CK_443X), + CLK(NULL, "gpt4_fck", &timer4_fck, CK_443X), + CLK(NULL, "gpt5_fck", &timer5_fck, CK_443X), + CLK(NULL, "gpt6_fck", &timer6_fck, CK_443X), + CLK(NULL, "gpt7_fck", &timer7_fck, CK_443X), + CLK(NULL, "gpt8_fck", &timer8_fck, CK_443X), + CLK(NULL, "gpt9_fck", &timer9_fck, CK_443X), CLK(NULL, "uart1_fck", &uart1_fck, CK_443X), CLK(NULL, "uart2_fck", &uart2_fck, CK_443X), CLK(NULL, "uart3_fck", &uart3_fck, CK_443X), CLK(NULL, "uart4_fck", &uart4_fck, CK_443X), - CLK(NULL, "unipro1_fck", &unipro1_fck, CK_443X), - CLK(NULL, "usb_host_fck", &usb_host_fck, CK_443X), CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X), - CLK("musb_hdrc", "ick", &usb_otg_ick, CK_443X), - CLK(NULL, "usb_tll_ick", &usb_tll_ick, CK_443X), - CLK(NULL, "usim_ick", &usim_ick, CK_443X), - CLK("omap_wdt", "fck", &wdt2_fck, CK_443X), - CLK(NULL, "wdt3_fck", &wdt3_fck, CK_443X), + CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X), + CLK("musb_hdrc", "ick", &usb_otg_hs_ick, CK_443X), + CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X), + CLK(NULL, "usim_fck", &usim_fck, CK_443X), + CLK("omap_wdt", "fck", &wd_timer2_fck, CK_443X), + CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X), CLK(NULL, "otg_60m_gfclk_ck", &otg_60m_gfclk_ck, CK_443X), CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), @@ -2645,19 +2600,19 @@ static struct omap_clk omap44xx_clks[] = { CLK("i2c_omap.2", "ick", &dummy_ck, CK_443X), CLK("i2c_omap.3", "ick", &dummy_ck, CK_443X), CLK("i2c_omap.4", "ick", &dummy_ck, CK_443X), + CLK("mmci-omap-hs.0", "ick", &dummy_ck, CK_443X), + CLK("mmci-omap-hs.1", "ick", &dummy_ck, CK_443X), + CLK("mmci-omap-hs.2", "ick", &dummy_ck, CK_443X), + CLK("mmci-omap-hs.3", "ick", &dummy_ck, CK_443X), + CLK("mmci-omap-hs.4", "ick", &dummy_ck, CK_443X), CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X), CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X), CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X), CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X), - CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X), - CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X), - CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X), - CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X), - CLK("mmci-omap-hs.0", "ick", &dummy_ck, CK_443X), - CLK("mmci-omap-hs.1", "ick", &dummy_ck, CK_443X), - CLK("mmci-omap-hs.2", "ick", &dummy_ck, CK_443X), - CLK("mmci-omap-hs.3", "ick", &dummy_ck, CK_443X), - CLK("mmci-omap-hs.4", "ick", &dummy_ck, CK_443X), + CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X), + CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X), + CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X), + CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X), CLK(NULL, "uart1_ick", &dummy_ck, CK_443X), CLK(NULL, "uart2_ick", &dummy_ck, CK_443X), CLK(NULL, "uart3_ick", &dummy_ck, CK_443X), -- cgit v1.1 From 1c03f42f01d212a79f7cd6e91eb8d8c624a843ec Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Mon, 27 Sep 2010 14:02:55 -0600 Subject: OMAP4: clock: Add optional clock nodes OMAP4 IP optional clocks require explicit enable in module CTRLCLK register. In order to allow that we have to create artificial clock nodes that represent this clock inputs in the IP. Notes: - Temporary use OMAP3 names for GPIO optional clocks until the GPIO hwmod convertion is done. It will enforce the usage of OMAP4 names as the reference. - Temporary use OMAP3 names for TIMER main clock (gptX_fck) until TIMER hwmod convertion is done. During that convertion, the new name will have to be used. Signed-off-by: Benoit Cousson Signed-off-by: Paul Walmsley Cc: Kevin Hilman Cc: Rajendra Nayak --- arch/arm/mach-omap2/clock44xx_data.c | 477 ++++++++++++++++++++++++++++++----- 1 file changed, 417 insertions(+), 60 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 8296ae0..b94f21a 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -1288,6 +1288,16 @@ static struct clk aess_fck = { .recalc = &followparent_recalc, }; +static struct clk bandgap_fclk = { + .name = "bandgap_fclk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, + .clkdm_name = "l4_wkup_clkdm", + .parent = &sys_32k_ck, + .recalc = &followparent_recalc, +}; + static struct clk des3des_fck = { .name = "des3des_fck", .ops = &clkops_omap2_dflt, @@ -1348,6 +1358,46 @@ static struct clk dsp_fck = { .recalc = &followparent_recalc, }; +static struct clk dss_sys_clk = { + .name = "dss_sys_clk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT, + .clkdm_name = "l3_dss_clkdm", + .parent = &syc_clk_div_ck, + .recalc = &followparent_recalc, +}; + +static struct clk dss_tv_clk = { + .name = "dss_tv_clk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, + .clkdm_name = "l3_dss_clkdm", + .parent = &extalt_clkin_ck, + .recalc = &followparent_recalc, +}; + +static struct clk dss_dss_clk = { + .name = "dss_dss_clk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT, + .clkdm_name = "l3_dss_clkdm", + .parent = &dpll_per_m5_ck, + .recalc = &followparent_recalc, +}; + +static struct clk dss_48mhz_clk = { + .name = "dss_48mhz_clk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT, + .clkdm_name = "l3_dss_clkdm", + .parent = &func_48mc_fclk, + .recalc = &followparent_recalc, +}; + static struct clk dss_fck = { .name = "dss_fck", .ops = &clkops_omap2_dflt, @@ -1421,6 +1471,16 @@ static struct clk fpka_fck = { .recalc = &followparent_recalc, }; +static struct clk gpio1_dbclk = { + .name = "gpio1_dbclk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, + .clkdm_name = "l4_wkup_clkdm", + .parent = &sys_32k_ck, + .recalc = &followparent_recalc, +}; + static struct clk gpio1_ick = { .name = "gpio1_ick", .ops = &clkops_omap2_dflt, @@ -1431,6 +1491,16 @@ static struct clk gpio1_ick = { .recalc = &followparent_recalc, }; +static struct clk gpio2_dbclk = { + .name = "gpio2_dbclk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, + .clkdm_name = "l4_per_clkdm", + .parent = &sys_32k_ck, + .recalc = &followparent_recalc, +}; + static struct clk gpio2_ick = { .name = "gpio2_ick", .ops = &clkops_omap2_dflt, @@ -1441,6 +1511,16 @@ static struct clk gpio2_ick = { .recalc = &followparent_recalc, }; +static struct clk gpio3_dbclk = { + .name = "gpio3_dbclk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, + .clkdm_name = "l4_per_clkdm", + .parent = &sys_32k_ck, + .recalc = &followparent_recalc, +}; + static struct clk gpio3_ick = { .name = "gpio3_ick", .ops = &clkops_omap2_dflt, @@ -1451,6 +1531,16 @@ static struct clk gpio3_ick = { .recalc = &followparent_recalc, }; +static struct clk gpio4_dbclk = { + .name = "gpio4_dbclk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, + .clkdm_name = "l4_per_clkdm", + .parent = &sys_32k_ck, + .recalc = &followparent_recalc, +}; + static struct clk gpio4_ick = { .name = "gpio4_ick", .ops = &clkops_omap2_dflt, @@ -1461,6 +1551,16 @@ static struct clk gpio4_ick = { .recalc = &followparent_recalc, }; +static struct clk gpio5_dbclk = { + .name = "gpio5_dbclk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, + .clkdm_name = "l4_per_clkdm", + .parent = &sys_32k_ck, + .recalc = &followparent_recalc, +}; + static struct clk gpio5_ick = { .name = "gpio5_ick", .ops = &clkops_omap2_dflt, @@ -1471,6 +1571,16 @@ static struct clk gpio5_ick = { .recalc = &followparent_recalc, }; +static struct clk gpio6_dbclk = { + .name = "gpio6_dbclk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, + .clkdm_name = "l4_per_clkdm", + .parent = &sys_32k_ck, + .recalc = &followparent_recalc, +}; + static struct clk gpio6_ick = { .name = "gpio6_ick", .ops = &clkops_omap2_dflt, @@ -1593,6 +1703,16 @@ static struct clk ipu_fck = { .recalc = &followparent_recalc, }; +static struct clk iss_ctrlclk = { + .name = "iss_ctrlclk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT, + .clkdm_name = "iss_clkdm", + .parent = &func_96m_fclk, + .recalc = &followparent_recalc, +}; + static struct clk iss_fck = { .name = "iss_fck", .ops = &clkops_omap2_dflt, @@ -1917,6 +2037,26 @@ static struct clk mmc5_fck = { .recalc = &followparent_recalc, }; +static struct clk ocp2scp_usb_phy_clk32k = { + .name = "ocp2scp_usb_phy_clk32k", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_CLK32K_SHIFT, + .clkdm_name = "l3_init_clkdm", + .parent = &sys_32k_ck, + .recalc = &followparent_recalc, +}; + +static struct clk ocp2scp_usb_phy_phy_48m = { + .name = "ocp2scp_usb_phy_phy_48m", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, + .clkdm_name = "l3_init_clkdm", + .parent = &func_48m_fclk, + .recalc = &followparent_recalc, +}; + static struct clk ocp_wp_noc_ick = { .name = "ocp_wp_noc_ick", .ops = &clkops_omap2_dflt, @@ -1957,6 +2097,46 @@ static struct clk sl2if_ick = { .recalc = &followparent_recalc, }; +static struct clk slimbus1_fclk_1 = { + .name = "slimbus1_fclk_1", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_FCLK1_SHIFT, + .clkdm_name = "abe_clkdm", + .parent = &func_24m_clk, + .recalc = &followparent_recalc, +}; + +static struct clk slimbus1_fclk_0 = { + .name = "slimbus1_fclk_0", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_FCLK0_SHIFT, + .clkdm_name = "abe_clkdm", + .parent = &abe_24m_fclk, + .recalc = &followparent_recalc, +}; + +static struct clk slimbus1_fclk_2 = { + .name = "slimbus1_fclk_2", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_FCLK2_SHIFT, + .clkdm_name = "abe_clkdm", + .parent = &pad_clks_ck, + .recalc = &followparent_recalc, +}; + +static struct clk slimbus1_slimbus_clk = { + .name = "slimbus1_slimbus_clk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, + .clkdm_name = "abe_clkdm", + .parent = &slimbus_clk, + .recalc = &followparent_recalc, +}; + static struct clk slimbus1_fck = { .name = "slimbus1_fck", .ops = &clkops_omap2_dflt, @@ -1967,6 +2147,36 @@ static struct clk slimbus1_fck = { .recalc = &followparent_recalc, }; +static struct clk slimbus2_fclk_1 = { + .name = "slimbus2_fclk_1", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, + .clkdm_name = "l4_per_clkdm", + .parent = &per_abe_24m_fclk, + .recalc = &followparent_recalc, +}; + +static struct clk slimbus2_fclk_0 = { + .name = "slimbus2_fclk_0", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT, + .clkdm_name = "l4_per_clkdm", + .parent = &func_24mc_fclk, + .recalc = &followparent_recalc, +}; + +static struct clk slimbus2_slimbus_clk = { + .name = "slimbus2_slimbus_clk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, + .clkdm_name = "l4_per_clkdm", + .parent = &pad_slimbus_core_clks_ck, + .recalc = &followparent_recalc, +}; + static struct clk slimbus2_fck = { .name = "slimbus2_fck", .ops = &clkops_omap2_dflt, @@ -2228,6 +2438,120 @@ static struct clk usb_host_fs_fck = { .recalc = &followparent_recalc, }; +static struct clk usb_host_hs_utmi_p3_clk = { + .name = "usb_host_hs_utmi_p3_clk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT, + .clkdm_name = "l3_init_clkdm", + .parent = &init_60m_fclk, + .recalc = &followparent_recalc, +}; + +static struct clk usb_host_hs_hsic60m_p1_clk = { + .name = "usb_host_hs_hsic60m_p1_clk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT, + .clkdm_name = "l3_init_clkdm", + .parent = &init_60m_fclk, + .recalc = &followparent_recalc, +}; + +static struct clk usb_host_hs_hsic60m_p2_clk = { + .name = "usb_host_hs_hsic60m_p2_clk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT, + .clkdm_name = "l3_init_clkdm", + .parent = &init_60m_fclk, + .recalc = &followparent_recalc, +}; + +static const struct clksel utmi_p1_gfclk_sel[] = { + { .parent = &init_60m_fclk, .rates = div_1_0_rates }, + { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + +static struct clk utmi_p1_gfclk = { + .name = "utmi_p1_gfclk", + .parent = &init_60m_fclk, + .clksel = utmi_p1_gfclk_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_UTMI_P1_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk usb_host_hs_utmi_p1_clk = { + .name = "usb_host_hs_utmi_p1_clk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT, + .clkdm_name = "l3_init_clkdm", + .parent = &utmi_p1_gfclk, + .recalc = &followparent_recalc, +}; + +static const struct clksel utmi_p2_gfclk_sel[] = { + { .parent = &init_60m_fclk, .rates = div_1_0_rates }, + { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + +static struct clk utmi_p2_gfclk = { + .name = "utmi_p2_gfclk", + .parent = &init_60m_fclk, + .clksel = utmi_p2_gfclk_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_UTMI_P2_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk usb_host_hs_utmi_p2_clk = { + .name = "usb_host_hs_utmi_p2_clk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT, + .clkdm_name = "l3_init_clkdm", + .parent = &utmi_p2_gfclk, + .recalc = &followparent_recalc, +}; + +static struct clk usb_host_hs_hsic480m_p1_clk = { + .name = "usb_host_hs_hsic480m_p1_clk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT, + .clkdm_name = "l3_init_clkdm", + .parent = &dpll_usb_m2_ck, + .recalc = &followparent_recalc, +}; + +static struct clk usb_host_hs_hsic480m_p2_clk = { + .name = "usb_host_hs_hsic480m_p2_clk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT, + .clkdm_name = "l3_init_clkdm", + .parent = &dpll_usb_m2_ck, + .recalc = &followparent_recalc, +}; + +static struct clk usb_host_hs_func48mclk = { + .name = "usb_host_hs_func48mclk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT, + .clkdm_name = "l3_init_clkdm", + .parent = &func_48mc_fclk, + .recalc = &followparent_recalc, +}; + static struct clk usb_host_hs_fck = { .name = "usb_host_hs_fck", .ops = &clkops_omap2_dflt, @@ -2238,6 +2562,33 @@ static struct clk usb_host_hs_fck = { .recalc = &followparent_recalc, }; +static const struct clksel otg_60m_gfclk_sel[] = { + { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates }, + { .parent = &xclk60motg_ck, .rates = div_1_1_rates }, + { .parent = NULL }, +}; + +static struct clk otg_60m_gfclk = { + .name = "otg_60m_gfclk", + .parent = &utmi_phy_clkout_ck, + .clksel = otg_60m_gfclk_sel, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_60M_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk usb_otg_hs_xclk = { + .name = "usb_otg_hs_xclk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_XCLK_SHIFT, + .clkdm_name = "l3_init_clkdm", + .parent = &otg_60m_gfclk, + .recalc = &followparent_recalc, +}; + static struct clk usb_otg_hs_ick = { .name = "usb_otg_hs_ick", .ops = &clkops_omap2_dflt, @@ -2248,6 +2599,36 @@ static struct clk usb_otg_hs_ick = { .recalc = &followparent_recalc, }; +static struct clk usb_tll_hs_usb_ch2_clk = { + .name = "usb_tll_hs_usb_ch2_clk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT, + .clkdm_name = "l3_init_clkdm", + .parent = &init_60m_fclk, + .recalc = &followparent_recalc, +}; + +static struct clk usb_tll_hs_usb_ch0_clk = { + .name = "usb_tll_hs_usb_ch0_clk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT, + .clkdm_name = "l3_init_clkdm", + .parent = &init_60m_fclk, + .recalc = &followparent_recalc, +}; + +static struct clk usb_tll_hs_usb_ch1_clk = { + .name = "usb_tll_hs_usb_ch1_clk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT, + .clkdm_name = "l3_init_clkdm", + .parent = &init_60m_fclk, + .recalc = &followparent_recalc, +}; + static struct clk usb_tll_hs_ick = { .name = "usb_tll_hs_ick", .ops = &clkops_omap2_dflt, @@ -2289,23 +2670,6 @@ static struct clk wd_timer3_fck = { }; /* Remaining optional clocks */ -static const struct clksel otg_60m_gfclk_sel[] = { - { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates }, - { .parent = &xclk60motg_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk otg_60m_gfclk_ck = { - .name = "otg_60m_gfclk_ck", - .parent = &utmi_phy_clkout_ck, - .clksel = otg_60m_gfclk_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_60M_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - static const struct clksel stm_clk_div_div[] = { { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates }, { .parent = NULL }, @@ -2363,40 +2727,6 @@ static struct clk usim_fclk = { .set_rate = &omap2_clksel_set_rate, }; -static const struct clksel utmi_p1_gfclk_sel[] = { - { .parent = &init_60m_fclk, .rates = div_1_0_rates }, - { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk utmi_p1_gfclk_ck = { - .name = "utmi_p1_gfclk_ck", - .parent = &init_60m_fclk, - .clksel = utmi_p1_gfclk_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_UTMI_P1_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel utmi_p2_gfclk_sel[] = { - { .parent = &init_60m_fclk, .rates = div_1_0_rates }, - { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates }, - { .parent = NULL }, -}; - -static struct clk utmi_p2_gfclk_ck = { - .name = "utmi_p2_gfclk_ck", - .parent = &init_60m_fclk, - .clksel = utmi_p2_gfclk_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_UTMI_P2_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - /* * clkdev */ @@ -2491,21 +2821,32 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "aes1_fck", &aes1_fck, CK_443X), CLK(NULL, "aes2_fck", &aes2_fck, CK_443X), CLK(NULL, "aess_fck", &aess_fck, CK_443X), + CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X), CLK(NULL, "des3des_fck", &des3des_fck, CK_443X), CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), CLK(NULL, "dmic_fck", &dmic_fck, CK_443X), CLK(NULL, "dsp_fck", &dsp_fck, CK_443X), + CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X), + CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X), + CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X), + CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X), CLK(NULL, "dss_fck", &dss_fck, CK_443X), CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X), CLK(NULL, "emif1_fck", &emif1_fck, CK_443X), CLK(NULL, "emif2_fck", &emif2_fck, CK_443X), CLK(NULL, "fdif_fck", &fdif_fck, CK_443X), CLK(NULL, "fpka_fck", &fpka_fck, CK_443X), + CLK(NULL, "gpio1_dbck", &gpio1_dbclk, CK_443X), CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X), + CLK(NULL, "gpio2_dbck", &gpio2_dbclk, CK_443X), CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X), + CLK(NULL, "gpio3_dbck", &gpio3_dbclk, CK_443X), CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X), + CLK(NULL, "gpio4_dbck", &gpio4_dbclk, CK_443X), CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X), + CLK(NULL, "gpio5_dbck", &gpio5_dbclk, CK_443X), CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X), + CLK(NULL, "gpio6_dbck", &gpio6_dbclk, CK_443X), CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X), CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X), CLK(NULL, "gpu_fck", &gpu_fck, CK_443X), @@ -2516,6 +2857,7 @@ static struct omap_clk omap44xx_clks[] = { CLK("i2c_omap.3", "fck", &i2c3_fck, CK_443X), CLK("i2c_omap.4", "fck", &i2c4_fck, CK_443X), CLK(NULL, "ipu_fck", &ipu_fck, CK_443X), + CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X), CLK(NULL, "iss_fck", &iss_fck, CK_443X), CLK(NULL, "iva_fck", &iva_fck, CK_443X), CLK(NULL, "kbd_fck", &kbd_fck, CK_443X), @@ -2541,11 +2883,20 @@ static struct omap_clk omap44xx_clks[] = { CLK("mmci-omap-hs.2", "fck", &mmc3_fck, CK_443X), CLK("mmci-omap-hs.3", "fck", &mmc4_fck, CK_443X), CLK("mmci-omap-hs.4", "fck", &mmc5_fck, CK_443X), + CLK(NULL, "ocp2scp_usb_phy_clk32k", &ocp2scp_usb_phy_clk32k, CK_443X), + CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X), CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X), CLK("omap_rng", "ick", &rng_ick, CK_443X), CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X), CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X), + CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X), + CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X), + CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_443X), + CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_443X), CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X), + CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_443X), + CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X), + CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X), CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X), CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X), CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X), @@ -2566,24 +2917,30 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "uart3_fck", &uart3_fck, CK_443X), CLK(NULL, "uart4_fck", &uart4_fck, CK_443X), CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X), + CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X), + CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X), + CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X), + CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X), + CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X), + CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X), + CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_443X), + CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_443X), + CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X), + CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X), CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X), + CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X), + CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X), CLK("musb_hdrc", "ick", &usb_otg_hs_ick, CK_443X), + CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X), + CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X), + CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X), CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X), CLK(NULL, "usim_fck", &usim_fck, CK_443X), CLK("omap_wdt", "fck", &wd_timer2_fck, CK_443X), CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X), - CLK(NULL, "otg_60m_gfclk_ck", &otg_60m_gfclk_ck, CK_443X), CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), - CLK(NULL, "utmi_p1_gfclk_ck", &utmi_p1_gfclk_ck, CK_443X), - CLK(NULL, "utmi_p2_gfclk_ck", &utmi_p2_gfclk_ck, CK_443X), - CLK(NULL, "gpio1_dbck", &dummy_ck, CK_443X), - CLK(NULL, "gpio2_dbck", &dummy_ck, CK_443X), - CLK(NULL, "gpio3_dbck", &dummy_ck, CK_443X), - CLK(NULL, "gpio4_dbck", &dummy_ck, CK_443X), - CLK(NULL, "gpio5_dbck", &dummy_ck, CK_443X), - CLK(NULL, "gpio6_dbck", &dummy_ck, CK_443X), CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X), CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X), CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X), -- cgit v1.1 From 568997cf375f3e3db28d6962cde66958b57dd6ac Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Mon, 27 Sep 2010 14:02:55 -0600 Subject: OMAP4: CM & PRM: Update PRCM register bitshifts and masks for ES2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch updates the PRM and CM register bitshifts and masks for OMAP4430 ES2.0. Replace as well the BITFIELD macro with the shift operator in order to be consistent with the previous OMAP2 & 3 format. Sort the register list in comments in order to have a consistent register order and avoid futur change during code generation. Signed-off-by: Rajendra Nayak Signed-off-by: Benoît Cousson Signed-off-by: Paul Walmsley Cc: Kevin Hilman --- arch/arm/mach-omap2/cm-regbits-44xx.h | 1287 ++++++++++++++++--------------- arch/arm/mach-omap2/prm-regbits-44xx.h | 1314 +++++++++++++++++--------------- 2 files changed, 1385 insertions(+), 1216 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/cm-regbits-44xx.h b/arch/arm/mach-omap2/cm-regbits-44xx.h index ac8458e..0b72be4 100644 --- a/arch/arm/mach-omap2/cm-regbits-44xx.h +++ b/arch/arm/mach-omap2/cm-regbits-44xx.h @@ -1,8 +1,8 @@ /* * OMAP44xx Clock Management register bits * - * Copyright (C) 2009 Texas Instruments, Inc. - * Copyright (C) 2009 Nokia Corporation + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * Copyright (C) 2009-2010 Nokia Corporation * * Paul Walmsley (paul@pwsan.com) * Rajendra Nayak (rnayak@ti.com) @@ -25,453 +25,459 @@ #include "cm.h" -/* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ +/* + * Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, + * CM_TESLA_DYNAMICDEP + */ #define OMAP4430_ABE_DYNDEP_SHIFT 3 -#define OMAP4430_ABE_DYNDEP_MASK BITFIELD(3, 3) +#define OMAP4430_ABE_DYNDEP_MASK (1 << 3) /* - * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, - * CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, - * CM_TESLA_STATICDEP + * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP, + * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, + * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP */ #define OMAP4430_ABE_STATDEP_SHIFT 3 -#define OMAP4430_ABE_STATDEP_MASK BITFIELD(3, 3) +#define OMAP4430_ABE_STATDEP_MASK (1 << 3) -/* Used by CM_L4CFG_DYNAMICDEP */ +/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ #define OMAP4430_ALWONCORE_DYNDEP_SHIFT 16 -#define OMAP4430_ALWONCORE_DYNDEP_MASK BITFIELD(16, 16) +#define OMAP4430_ALWONCORE_DYNDEP_MASK (1 << 16) /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ #define OMAP4430_ALWONCORE_STATDEP_SHIFT 16 -#define OMAP4430_ALWONCORE_STATDEP_MASK BITFIELD(16, 16) +#define OMAP4430_ALWONCORE_STATDEP_MASK (1 << 16) /* - * Used by CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB, - * CM_AUTOIDLE_DPLL_CORE_RESTORE, CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, - * CM_AUTOIDLE_DPLL_DDRPHY, CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU + * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, + * CM_AUTOIDLE_DPLL_CORE_RESTORE, CM_AUTOIDLE_DPLL_DDRPHY, + * CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER, + * CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB */ #define OMAP4430_AUTO_DPLL_MODE_SHIFT 0 -#define OMAP4430_AUTO_DPLL_MODE_MASK BITFIELD(0, 2) +#define OMAP4430_AUTO_DPLL_MODE_MASK (0x7 << 0) -/* Used by CM_L4CFG_DYNAMICDEP */ +/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ #define OMAP4430_CEFUSE_DYNDEP_SHIFT 17 -#define OMAP4430_CEFUSE_DYNDEP_MASK BITFIELD(17, 17) +#define OMAP4430_CEFUSE_DYNDEP_MASK (1 << 17) /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ #define OMAP4430_CEFUSE_STATDEP_SHIFT 17 -#define OMAP4430_CEFUSE_STATDEP_MASK BITFIELD(17, 17) +#define OMAP4430_CEFUSE_STATDEP_MASK (1 << 17) /* Used by CM1_ABE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT 13 -#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK BITFIELD(13, 13) +#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK (1 << 13) /* Used by CM1_ABE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT 12 -#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK BITFIELD(12, 12) +#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK (1 << 12) /* Used by CM_WKUP_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK BITFIELD(9, 9) +#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK (1 << 9) /* Used by CM1_ABE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT 11 -#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK BITFIELD(11, 11) +#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK (1 << 11) /* Used by CM1_ABE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK BITFIELD(8, 8) +#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK (1 << 8) /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT 11 -#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK BITFIELD(11, 11) +#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK (1 << 11) /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT 12 -#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK BITFIELD(12, 12) +#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK (1 << 12) /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT 13 -#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK BITFIELD(13, 13) +#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK (1 << 13) /* Used by CM_CAM_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK BITFIELD(9, 9) +#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK (1 << 9) + +/* Used by CM_ALWON_CLKSTCTRL */ +#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_SHIFT 12 +#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_MASK (1 << 12) /* Used by CM_EMU_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK BITFIELD(9, 9) +#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK (1 << 9) /* Used by CM_CEFUSE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK BITFIELD(9, 9) +#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9) /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_DLL_CLK_MASK BITFIELD(9, 9) +#define OMAP4430_CLKACTIVITY_DLL_CLK_MASK (1 << 9) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK BITFIELD(9, 9) +#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK (1 << 9) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK BITFIELD(10, 10) +#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK (1 << 10) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT 11 -#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK BITFIELD(11, 11) +#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK (1 << 11) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT 12 -#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK BITFIELD(12, 12) +#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK (1 << 12) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT 13 -#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK BITFIELD(13, 13) +#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK (1 << 13) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT 14 -#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK BITFIELD(14, 14) +#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK (1 << 14) /* Used by CM_DSS_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK BITFIELD(10, 10) +#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK (1 << 10) /* Used by CM_DSS_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK BITFIELD(9, 9) +#define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK (1 << 9) /* Used by CM_DUCATI_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK BITFIELD(8, 8) - -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_EMAC_50MHZ_CLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_EMAC_50MHZ_CLK_MASK BITFIELD(10, 10) +#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK (1 << 8) /* Used by CM_EMU_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK BITFIELD(8, 8) +#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK (1 << 8) /* Used by CM_CAM_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK BITFIELD(10, 10) +#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK (1 << 10) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT 15 -#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK BITFIELD(15, 15) +#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK (1 << 15) /* Used by CM1_ABE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK BITFIELD(10, 10) +#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK (1 << 10) /* Used by CM_DSS_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT 11 -#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK BITFIELD(11, 11) +#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK (1 << 11) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20 -#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK BITFIELD(20, 20) +#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK (1 << 20) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26 -#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK BITFIELD(26, 26) +#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK (1 << 26) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21 -#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK BITFIELD(21, 21) +#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK (1 << 21) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27 -#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK BITFIELD(27, 27) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_INIT_32K_GFCLK_SHIFT 31 -#define OMAP4430_CLKACTIVITY_INIT_32K_GFCLK_MASK BITFIELD(31, 31) +#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK (1 << 27) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT 13 -#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK BITFIELD(13, 13) +#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK (1 << 13) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT 12 -#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK BITFIELD(12, 12) +#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK (1 << 12) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT 28 -#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK BITFIELD(28, 28) +#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK (1 << 28) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT 29 -#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK BITFIELD(29, 29) +#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK (1 << 29) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT 11 -#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK BITFIELD(11, 11) +#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK (1 << 11) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT 16 -#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK BITFIELD(16, 16) +#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK (1 << 16) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT 17 -#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK BITFIELD(17, 17) +#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK (1 << 17) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT 18 -#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK BITFIELD(18, 18) +#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK (1 << 18) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT 19 -#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK BITFIELD(19, 19) +#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK (1 << 19) /* Used by CM_CAM_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK BITFIELD(8, 8) +#define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK (1 << 8) /* Used by CM_IVAHD_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK BITFIELD(8, 8) +#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK (1 << 8) -/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ -#define OMAP4430_CLKACTIVITY_L3INIT_DPLL_ALWON_CLK_SHIFT 14 -#define OMAP4430_CLKACTIVITY_L3INIT_DPLL_ALWON_CLK_MASK BITFIELD(14, 14) +/* Used by CM_D2D_CLKSTCTRL */ +#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT 10 +#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK (1 << 10) /* Used by CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK BITFIELD(8, 8) +#define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK (1 << 8) /* Used by CM_L3_2_CLKSTCTRL, CM_L3_2_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK BITFIELD(8, 8) +#define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK (1 << 8) /* Used by CM_D2D_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK BITFIELD(8, 8) +#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK (1 << 8) /* Used by CM_SDMA_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK BITFIELD(8, 8) +#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK (1 << 8) /* Used by CM_DSS_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK BITFIELD(8, 8) +#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK (1 << 8) /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK BITFIELD(8, 8) +#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK (1 << 8) /* Used by CM_GFX_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK BITFIELD(8, 8) +#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK (1 << 8) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK BITFIELD(8, 8) +#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK (1 << 8) /* Used by CM_L3INSTR_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK BITFIELD(8, 8) +#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK (1 << 8) /* Used by CM_L4SEC_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK BITFIELD(8, 8) +#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK (1 << 8) /* Used by CM_ALWON_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK BITFIELD(8, 8) +#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK (1 << 8) /* Used by CM_CEFUSE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK BITFIELD(8, 8) +#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8) /* Used by CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK BITFIELD(8, 8) +#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK (1 << 8) /* Used by CM_D2D_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK BITFIELD(9, 9) +#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK (1 << 9) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK BITFIELD(9, 9) +#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK (1 << 9) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK BITFIELD(8, 8) +#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK (1 << 8) /* Used by CM_L4SEC_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK BITFIELD(9, 9) +#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK (1 << 9) /* Used by CM_WKUP_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT 12 -#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK BITFIELD(12, 12) +#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK (1 << 12) /* Used by CM_MPU_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK BITFIELD(8, 8) +#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK (1 << 8) /* Used by CM1_ABE_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK BITFIELD(9, 9) +#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK (1 << 9) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT 16 -#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK BITFIELD(16, 16) +#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK (1 << 16) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17 -#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK BITFIELD(17, 17) +#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK (1 << 17) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18 -#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK BITFIELD(18, 18) +#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 18) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19 -#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK BITFIELD(19, 19) +#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 19) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT 25 -#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK BITFIELD(25, 25) - -/* Used by CM_EMU_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_PER_DPLL_EMU_CLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_PER_DPLL_EMU_CLK_MASK BITFIELD(10, 10) +#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK (1 << 25) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT 20 -#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK BITFIELD(20, 20) +#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK (1 << 20) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT 21 -#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK BITFIELD(21, 21) +#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK (1 << 21) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT 22 -#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK BITFIELD(22, 22) +#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK (1 << 22) /* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT 24 -#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK BITFIELD(24, 24) +#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK (1 << 24) /* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK BITFIELD(10, 10) +#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK (1 << 10) /* Used by CM_GFX_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK BITFIELD(9, 9) +#define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK (1 << 9) /* Used by CM_ALWON_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT 11 -#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK BITFIELD(11, 11) +#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK (1 << 11) /* Used by CM_ALWON_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK BITFIELD(10, 10) +#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK (1 << 10) /* Used by CM_ALWON_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK BITFIELD(9, 9) +#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK (1 << 9) /* Used by CM_WKUP_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_SYS_CLK_MASK BITFIELD(8, 8) +#define OMAP4430_CLKACTIVITY_SYS_CLK_MASK (1 << 8) /* Used by CM_TESLA_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK BITFIELD(8, 8) +#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK (1 << 8) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22 -#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK BITFIELD(22, 22) +#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK (1 << 22) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23 -#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK BITFIELD(23, 23) +#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK (1 << 23) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24 -#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK BITFIELD(24, 24) +#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK (1 << 24) + +/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ +#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT 10 +#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK (1 << 10) + +/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ +#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT 14 +#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 14) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15 -#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK BITFIELD(15, 15) +#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 15) /* Used by CM_WKUP_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK BITFIELD(10, 10) +#define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK (1 << 10) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30 -#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK BITFIELD(30, 30) +#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK (1 << 30) /* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25 -#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK BITFIELD(25, 25) +#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK (1 << 25) /* Used by CM_WKUP_CLKSTCTRL */ #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT 11 -#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK BITFIELD(11, 11) +#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK (1 << 11) /* - * Used by CM_WKUP_TIMER1_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL, + * Used by CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, + * CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, + * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MMC6_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL, * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL, * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL, * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, - * CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MMC6_CLKCTRL, - * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, - * CM1_ABE_TIMER8_CLKCTRL + * CM_WKUP_TIMER1_CLKCTRL */ #define OMAP4430_CLKSEL_SHIFT 24 -#define OMAP4430_CLKSEL_MASK BITFIELD(24, 24) +#define OMAP4430_CLKSEL_MASK (1 << 24) /* * Renamed from CLKSEL Used by CM_ABE_DSS_SYS_CLKSEL, CM_ABE_PLL_REF_CLKSEL, - * CM_DPLL_SYS_REF_CLKSEL, CM_L4_WKUP_CLKSEL, CM_CLKSEL_DUCATI_ISS_ROOT, - * CM_CLKSEL_USB_60MHZ + * CM_L4_WKUP_CLKSEL, CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ */ #define OMAP4430_CLKSEL_0_0_SHIFT 0 -#define OMAP4430_CLKSEL_0_0_MASK BITFIELD(0, 0) +#define OMAP4430_CLKSEL_0_0_MASK (1 << 0) /* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */ #define OMAP4430_CLKSEL_0_1_SHIFT 0 -#define OMAP4430_CLKSEL_0_1_MASK BITFIELD(0, 1) +#define OMAP4430_CLKSEL_0_1_MASK (0x3 << 0) /* Renamed from CLKSEL Used by CM_L3INIT_HSI_CLKCTRL */ #define OMAP4430_CLKSEL_24_25_SHIFT 24 -#define OMAP4430_CLKSEL_24_25_MASK BITFIELD(24, 25) +#define OMAP4430_CLKSEL_24_25_MASK (0x3 << 24) /* Used by CM_L3INIT_USB_OTG_CLKCTRL */ #define OMAP4430_CLKSEL_60M_SHIFT 24 -#define OMAP4430_CLKSEL_60M_MASK BITFIELD(24, 24) +#define OMAP4430_CLKSEL_60M_MASK (1 << 24) /* Used by CM1_ABE_AESS_CLKCTRL */ #define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24 -#define OMAP4430_CLKSEL_AESS_FCLK_MASK BITFIELD(24, 24) +#define OMAP4430_CLKSEL_AESS_FCLK_MASK (1 << 24) -/* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */ +/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */ #define OMAP4430_CLKSEL_CORE_SHIFT 0 -#define OMAP4430_CLKSEL_CORE_MASK BITFIELD(0, 0) +#define OMAP4430_CLKSEL_CORE_MASK (1 << 0) -/* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */ +/* + * Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2_RESTORE, + * CM_SHADOW_FREQ_CONFIG2 + */ #define OMAP4430_CLKSEL_CORE_1_1_SHIFT 1 -#define OMAP4430_CLKSEL_CORE_1_1_MASK BITFIELD(1, 1) +#define OMAP4430_CLKSEL_CORE_1_1_MASK (1 << 1) /* Used by CM_WKUP_USIM_CLKCTRL */ #define OMAP4430_CLKSEL_DIV_SHIFT 24 -#define OMAP4430_CLKSEL_DIV_MASK BITFIELD(24, 24) +#define OMAP4430_CLKSEL_DIV_MASK (1 << 24) /* Used by CM_CAM_FDIF_CLKCTRL */ #define OMAP4430_CLKSEL_FCLK_SHIFT 24 -#define OMAP4430_CLKSEL_FCLK_MASK BITFIELD(24, 25) +#define OMAP4430_CLKSEL_FCLK_MASK (0x3 << 24) /* Used by CM_L4PER_MCBSP4_CLKCTRL */ #define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT 25 -#define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK BITFIELD(25, 25) +#define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK (1 << 25) /* * Renamed from CLKSEL_INTERNAL_SOURCE Used by CM1_ABE_DMIC_CLKCTRL, @@ -479,836 +485,869 @@ * CM1_ABE_MCBSP3_CLKCTRL */ #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT 26 -#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK BITFIELD(26, 27) +#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK (0x3 << 26) -/* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */ +/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */ #define OMAP4430_CLKSEL_L3_SHIFT 4 -#define OMAP4430_CLKSEL_L3_MASK BITFIELD(4, 4) +#define OMAP4430_CLKSEL_L3_MASK (1 << 4) -/* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */ +/* + * Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2_RESTORE, + * CM_SHADOW_FREQ_CONFIG2 + */ #define OMAP4430_CLKSEL_L3_SHADOW_SHIFT 2 -#define OMAP4430_CLKSEL_L3_SHADOW_MASK BITFIELD(2, 2) +#define OMAP4430_CLKSEL_L3_SHADOW_MASK (1 << 2) -/* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */ +/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */ #define OMAP4430_CLKSEL_L4_SHIFT 8 -#define OMAP4430_CLKSEL_L4_MASK BITFIELD(8, 8) +#define OMAP4430_CLKSEL_L4_MASK (1 << 8) /* Used by CM_CLKSEL_ABE */ #define OMAP4430_CLKSEL_OPP_SHIFT 0 -#define OMAP4430_CLKSEL_OPP_MASK BITFIELD(0, 1) - -/* Used by CM_GFX_GFX_CLKCTRL */ -#define OMAP4430_CLKSEL_PER_192M_SHIFT 25 -#define OMAP4430_CLKSEL_PER_192M_MASK BITFIELD(25, 26) +#define OMAP4430_CLKSEL_OPP_MASK (0x3 << 0) /* Used by CM_EMU_DEBUGSS_CLKCTRL */ #define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT 27 -#define OMAP4430_CLKSEL_PMD_STM_CLK_MASK BITFIELD(27, 29) +#define OMAP4430_CLKSEL_PMD_STM_CLK_MASK (0x7 << 27) /* Used by CM_EMU_DEBUGSS_CLKCTRL */ #define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT 24 -#define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK BITFIELD(24, 26) +#define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK (0x7 << 24) /* Used by CM_GFX_GFX_CLKCTRL */ #define OMAP4430_CLKSEL_SGX_FCLK_SHIFT 24 -#define OMAP4430_CLKSEL_SGX_FCLK_MASK BITFIELD(24, 24) +#define OMAP4430_CLKSEL_SGX_FCLK_MASK (1 << 24) /* * Used by CM1_ABE_DMIC_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, * CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL */ #define OMAP4430_CLKSEL_SOURCE_SHIFT 24 -#define OMAP4430_CLKSEL_SOURCE_MASK BITFIELD(24, 25) +#define OMAP4430_CLKSEL_SOURCE_MASK (0x3 << 24) /* Renamed from CLKSEL_SOURCE Used by CM_L4PER_MCBSP4_CLKCTRL */ #define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT 24 -#define OMAP4430_CLKSEL_SOURCE_24_24_MASK BITFIELD(24, 24) +#define OMAP4430_CLKSEL_SOURCE_24_24_MASK (1 << 24) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ #define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24 -#define OMAP4430_CLKSEL_UTMI_P1_MASK BITFIELD(24, 24) +#define OMAP4430_CLKSEL_UTMI_P1_MASK (1 << 24) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ #define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25 -#define OMAP4430_CLKSEL_UTMI_P2_MASK BITFIELD(25, 25) +#define OMAP4430_CLKSEL_UTMI_P2_MASK (1 << 25) /* - * Used by CM_WKUP_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_D2D_CLKSTCTRL, - * CM_DUCATI_CLKSTCTRL, CM_L3INSTR_CLKSTCTRL, CM_L3_1_CLKSTCTRL, - * CM_L3_2_CLKSTCTRL, CM_L4CFG_CLKSTCTRL, CM_MEMIF_CLKSTCTRL, - * CM_SDMA_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_L4PER_CLKSTCTRL, CM_L4SEC_CLKSTCTRL, - * CM_L3INIT_CLKSTCTRL, CM_CAM_CLKSTCTRL, CM_CEFUSE_CLKSTCTRL, - * CM_L3INIT_CLKSTCTRL_RESTORE, CM_L3_1_CLKSTCTRL_RESTORE, - * CM_L3_2_CLKSTCTRL_RESTORE, CM_L4CFG_CLKSTCTRL_RESTORE, - * CM_L4PER_CLKSTCTRL_RESTORE, CM_MEMIF_CLKSTCTRL_RESTORE, CM_ALWON_CLKSTCTRL, - * CM_IVAHD_CLKSTCTRL, CM_DSS_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_TESLA_CLKSTCTRL, - * CM1_ABE_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE + * Used by CM1_ABE_CLKSTCTRL, CM_ALWON_CLKSTCTRL, CM_CAM_CLKSTCTRL, + * CM_CEFUSE_CLKSTCTRL, CM_D2D_CLKSTCTRL, CM_DSS_CLKSTCTRL, + * CM_DUCATI_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_IVAHD_CLKSTCTRL, + * CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE, CM_L3INSTR_CLKSTCTRL, + * CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE, CM_L3_2_CLKSTCTRL, + * CM_L3_2_CLKSTCTRL_RESTORE, CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE, + * CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE, CM_L4SEC_CLKSTCTRL, + * CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE, CM_MPU_CLKSTCTRL, + * CM_MPU_CLKSTCTRL_RESTORE, CM_SDMA_CLKSTCTRL, CM_TESLA_CLKSTCTRL, + * CM_WKUP_CLKSTCTRL */ #define OMAP4430_CLKTRCTRL_SHIFT 0 -#define OMAP4430_CLKTRCTRL_MASK BITFIELD(0, 1) +#define OMAP4430_CLKTRCTRL_MASK (0x3 << 0) /* Used by CM_EMU_OVERRIDE_DPLL_CORE */ #define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT 0 -#define OMAP4430_CORE_DPLL_EMU_DIV_MASK BITFIELD(0, 6) +#define OMAP4430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0) /* Used by CM_EMU_OVERRIDE_DPLL_CORE */ #define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT 8 -#define OMAP4430_CORE_DPLL_EMU_MULT_MASK BITFIELD(8, 18) +#define OMAP4430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8) + +/* Used by REVISION_CM1, REVISION_CM2 */ +#define OMAP4430_CUSTOM_SHIFT 6 +#define OMAP4430_CUSTOM_MASK (0x3 << 6) -/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ +/* + * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, + * CM_L4CFG_DYNAMICDEP_RESTORE + */ #define OMAP4430_D2D_DYNDEP_SHIFT 18 -#define OMAP4430_D2D_DYNDEP_MASK BITFIELD(18, 18) +#define OMAP4430_D2D_DYNDEP_MASK (1 << 18) /* Used by CM_MPU_STATICDEP */ #define OMAP4430_D2D_STATDEP_SHIFT 18 -#define OMAP4430_D2D_STATDEP_MASK BITFIELD(18, 18) +#define OMAP4430_D2D_STATDEP_MASK (1 << 18) /* - * Used by CM_SSC_DELTAMSTEP_DPLL_PER, CM_SSC_DELTAMSTEP_DPLL_UNIPRO, - * CM_SSC_DELTAMSTEP_DPLL_USB, CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE, - * CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE, - * CM_SSC_DELTAMSTEP_DPLL_DDRPHY, CM_SSC_DELTAMSTEP_DPLL_IVA, - * CM_SSC_DELTAMSTEP_DPLL_MPU + * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE, + * CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE, CM_SSC_DELTAMSTEP_DPLL_DDRPHY, + * CM_SSC_DELTAMSTEP_DPLL_IVA, CM_SSC_DELTAMSTEP_DPLL_MPU, + * CM_SSC_DELTAMSTEP_DPLL_PER, CM_SSC_DELTAMSTEP_DPLL_UNIPRO, + * CM_SSC_DELTAMSTEP_DPLL_USB */ #define OMAP4430_DELTAMSTEP_SHIFT 0 -#define OMAP4430_DELTAMSTEP_MASK BITFIELD(0, 19) +#define OMAP4430_DELTAMSTEP_MASK (0xfffff << 0) -/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ +/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ #define OMAP4430_DLL_OVERRIDE_SHIFT 2 -#define OMAP4430_DLL_OVERRIDE_MASK BITFIELD(2, 2) +#define OMAP4430_DLL_OVERRIDE_MASK (1 << 2) /* Renamed from DLL_OVERRIDE Used by CM_DLL_CTRL */ #define OMAP4430_DLL_OVERRIDE_0_0_SHIFT 0 -#define OMAP4430_DLL_OVERRIDE_0_0_MASK BITFIELD(0, 0) +#define OMAP4430_DLL_OVERRIDE_0_0_MASK (1 << 0) -/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ +/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ #define OMAP4430_DLL_RESET_SHIFT 3 -#define OMAP4430_DLL_RESET_MASK BITFIELD(3, 3) +#define OMAP4430_DLL_RESET_MASK (1 << 3) /* - * Used by CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO, CM_CLKSEL_DPLL_USB, - * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, - * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU + * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, + * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, + * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO, + * CM_CLKSEL_DPLL_USB */ #define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23 -#define OMAP4430_DPLL_BYP_CLKSEL_MASK BITFIELD(23, 23) +#define OMAP4430_DPLL_BYP_CLKSEL_MASK (1 << 23) /* Used by CM_CLKDCOLDO_DPLL_USB */ #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8 -#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK BITFIELD(8, 8) +#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8) -/* Used by CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_CORE */ +/* Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_CORE_RESTORE */ #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20 -#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK BITFIELD(20, 20) +#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20) /* - * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE, - * CM_DIV_M3_DPLL_CORE + * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, + * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER */ #define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT 0 -#define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK BITFIELD(0, 4) +#define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK (0x1f << 0) /* - * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE, - * CM_DIV_M3_DPLL_CORE + * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, + * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER */ #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT 5 -#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK BITFIELD(5, 5) +#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK (1 << 5) /* - * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE, - * CM_DIV_M3_DPLL_CORE + * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, + * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER */ #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8 -#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK BITFIELD(8, 8) +#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK (1 << 8) -/* Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, CM_DIV_M2_DPLL_ABE */ +/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */ #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT 10 -#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK BITFIELD(10, 10) +#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10) /* - * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, - * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, - * CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU + * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, + * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU, + * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */ #define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0 -#define OMAP4430_DPLL_CLKOUT_DIV_MASK BITFIELD(0, 4) +#define OMAP4430_DPLL_CLKOUT_DIV_MASK (0x1f << 0) /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_USB */ #define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT 0 -#define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK BITFIELD(0, 6) +#define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0) /* - * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, - * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, - * CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU + * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, + * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU, + * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */ #define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT 5 -#define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK BITFIELD(5, 5) +#define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5) /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_USB */ #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT 7 -#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK BITFIELD(7, 7) +#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK (1 << 7) /* - * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB, CM_DIV_M2_DPLL_CORE_RESTORE, - * CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, - * CM_DIV_M2_DPLL_MPU + * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, + * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU, + * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB */ #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT 8 -#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK BITFIELD(8, 8) +#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) -/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ +/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ #define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT 8 -#define OMAP4430_DPLL_CORE_DPLL_EN_MASK BITFIELD(8, 10) +#define OMAP4430_DPLL_CORE_DPLL_EN_MASK (0x7 << 8) -/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ +/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ #define OMAP4430_DPLL_CORE_M2_DIV_SHIFT 11 -#define OMAP4430_DPLL_CORE_M2_DIV_MASK BITFIELD(11, 15) +#define OMAP4430_DPLL_CORE_M2_DIV_MASK (0x1f << 11) -/* Used by CM_SHADOW_FREQ_CONFIG2 */ +/* Used by CM_SHADOW_FREQ_CONFIG2, CM_SHADOW_FREQ_CONFIG2_RESTORE */ #define OMAP4430_DPLL_CORE_M5_DIV_SHIFT 3 -#define OMAP4430_DPLL_CORE_M5_DIV_MASK BITFIELD(3, 7) - -/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ -#define OMAP4430_DPLL_CORE_SYS_REF_CLKSEL_SHIFT 1 -#define OMAP4430_DPLL_CORE_SYS_REF_CLKSEL_MASK BITFIELD(1, 1) +#define OMAP4430_DPLL_CORE_M5_DIV_MASK (0x1f << 3) /* - * Used by CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO, - * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, - * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU + * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, + * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, + * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO */ #define OMAP4430_DPLL_DIV_SHIFT 0 -#define OMAP4430_DPLL_DIV_MASK BITFIELD(0, 6) +#define OMAP4430_DPLL_DIV_MASK (0x7f << 0) /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_USB */ #define OMAP4430_DPLL_DIV_0_7_SHIFT 0 -#define OMAP4430_DPLL_DIV_0_7_MASK BITFIELD(0, 7) +#define OMAP4430_DPLL_DIV_0_7_MASK (0xff << 0) /* - * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_USB, - * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, - * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU + * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, + * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, + * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER */ #define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT 8 -#define OMAP4430_DPLL_DRIFTGUARD_EN_MASK BITFIELD(8, 8) +#define OMAP4430_DPLL_DRIFTGUARD_EN_MASK (1 << 8) /* Renamed from DPLL_DRIFTGUARD_EN Used by CM_CLKMODE_DPLL_UNIPRO */ #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT 3 -#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK BITFIELD(3, 3) +#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK (1 << 3) /* - * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB, - * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, - * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU + * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, + * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, + * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, + * CM_CLKMODE_DPLL_USB */ #define OMAP4430_DPLL_EN_SHIFT 0 -#define OMAP4430_DPLL_EN_MASK BITFIELD(0, 2) +#define OMAP4430_DPLL_EN_MASK (0x7 << 0) /* - * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, - * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, - * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU + * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, + * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, + * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO */ #define OMAP4430_DPLL_LPMODE_EN_SHIFT 10 -#define OMAP4430_DPLL_LPMODE_EN_MASK BITFIELD(10, 10) +#define OMAP4430_DPLL_LPMODE_EN_MASK (1 << 10) /* - * Used by CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO, - * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, - * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU + * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, + * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, + * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO */ #define OMAP4430_DPLL_MULT_SHIFT 8 -#define OMAP4430_DPLL_MULT_MASK BITFIELD(8, 18) +#define OMAP4430_DPLL_MULT_MASK (0x7ff << 8) /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_USB */ #define OMAP4430_DPLL_MULT_USB_SHIFT 8 -#define OMAP4430_DPLL_MULT_USB_MASK BITFIELD(8, 19) +#define OMAP4430_DPLL_MULT_USB_MASK (0xfff << 8) /* - * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, - * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, - * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU + * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, + * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, + * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO */ #define OMAP4430_DPLL_REGM4XEN_SHIFT 11 -#define OMAP4430_DPLL_REGM4XEN_MASK BITFIELD(11, 11) +#define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11) /* Used by CM_CLKSEL_DPLL_USB */ #define OMAP4430_DPLL_SD_DIV_SHIFT 24 -#define OMAP4430_DPLL_SD_DIV_MASK BITFIELD(24, 31) +#define OMAP4430_DPLL_SD_DIV_MASK (0xff << 24) /* - * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB, - * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, - * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU + * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, + * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, + * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, + * CM_CLKMODE_DPLL_USB */ #define OMAP4430_DPLL_SSC_ACK_SHIFT 13 -#define OMAP4430_DPLL_SSC_ACK_MASK BITFIELD(13, 13) +#define OMAP4430_DPLL_SSC_ACK_MASK (1 << 13) /* - * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB, - * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, - * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU + * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, + * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, + * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, + * CM_CLKMODE_DPLL_USB */ #define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT 14 -#define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK BITFIELD(14, 14) +#define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) /* - * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB, - * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, - * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU + * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, + * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, + * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, + * CM_CLKMODE_DPLL_USB */ #define OMAP4430_DPLL_SSC_EN_SHIFT 12 -#define OMAP4430_DPLL_SSC_EN_MASK BITFIELD(12, 12) +#define OMAP4430_DPLL_SSC_EN_MASK (1 << 12) -/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ +/* + * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, + * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, CM_L4PER_DYNAMICDEP_RESTORE + */ #define OMAP4430_DSS_DYNDEP_SHIFT 8 -#define OMAP4430_DSS_DYNDEP_MASK BITFIELD(8, 8) +#define OMAP4430_DSS_DYNDEP_MASK (1 << 8) /* - * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, - * CM_MPU_STATICDEP + * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, + * CM_SDMA_STATICDEP_RESTORE */ #define OMAP4430_DSS_STATDEP_SHIFT 8 -#define OMAP4430_DSS_STATDEP_MASK BITFIELD(8, 8) +#define OMAP4430_DSS_STATDEP_MASK (1 << 8) -/* Used by CM_L3_2_DYNAMICDEP */ +/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */ #define OMAP4430_DUCATI_DYNDEP_SHIFT 0 -#define OMAP4430_DUCATI_DYNDEP_MASK BITFIELD(0, 0) +#define OMAP4430_DUCATI_DYNDEP_MASK (1 << 0) -/* Used by CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP */ +/* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE */ #define OMAP4430_DUCATI_STATDEP_SHIFT 0 -#define OMAP4430_DUCATI_STATDEP_MASK BITFIELD(0, 0) +#define OMAP4430_DUCATI_STATDEP_MASK (1 << 0) -/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ +/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ #define OMAP4430_FREQ_UPDATE_SHIFT 0 -#define OMAP4430_FREQ_UPDATE_MASK BITFIELD(0, 0) +#define OMAP4430_FREQ_UPDATE_MASK (1 << 0) + +/* Used by REVISION_CM1, REVISION_CM2 */ +#define OMAP4430_FUNC_SHIFT 16 +#define OMAP4430_FUNC_MASK (0xfff << 16) -/* Used by CM_L3_2_DYNAMICDEP */ +/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */ #define OMAP4430_GFX_DYNDEP_SHIFT 10 -#define OMAP4430_GFX_DYNDEP_MASK BITFIELD(10, 10) +#define OMAP4430_GFX_DYNDEP_MASK (1 << 10) /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ #define OMAP4430_GFX_STATDEP_SHIFT 10 -#define OMAP4430_GFX_STATDEP_MASK BITFIELD(10, 10) +#define OMAP4430_GFX_STATDEP_MASK (1 << 10) -/* Used by CM_SHADOW_FREQ_CONFIG2 */ +/* Used by CM_SHADOW_FREQ_CONFIG2, CM_SHADOW_FREQ_CONFIG2_RESTORE */ #define OMAP4430_GPMC_FREQ_UPDATE_SHIFT 0 -#define OMAP4430_GPMC_FREQ_UPDATE_MASK BITFIELD(0, 0) +#define OMAP4430_GPMC_FREQ_UPDATE_MASK (1 << 0) /* - * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, - * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA + * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, + * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT 0 -#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK BITFIELD(0, 4) +#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0) /* - * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, - * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA + * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, + * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5 -#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK BITFIELD(5, 5) +#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5) /* - * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, - * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA + * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, + * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8 -#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK BITFIELD(8, 8) +#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8) /* - * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, - * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA + * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, + * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12 -#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK BITFIELD(12, 12) +#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12) /* - * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, - * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA + * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, + * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT 0 -#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK BITFIELD(0, 4) +#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0) /* - * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, - * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA + * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, + * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5 -#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK BITFIELD(5, 5) +#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5) /* - * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, - * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA + * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, + * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8 -#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK BITFIELD(8, 8) +#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8) /* - * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, - * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA + * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, + * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12 -#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK BITFIELD(12, 12) +#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12) /* - * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, - * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY + * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE, + * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT 0 -#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK BITFIELD(0, 4) +#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0) /* - * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, - * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY + * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE, + * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5 -#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK BITFIELD(5, 5) +#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5) /* - * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, - * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY + * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE, + * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8 -#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK BITFIELD(8, 8) +#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8) /* - * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, - * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY + * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE, + * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12 -#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK BITFIELD(12, 12) +#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12) /* - * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, - * CM_DIV_M7_DPLL_CORE + * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE, + * CM_DIV_M7_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT 0 -#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK BITFIELD(0, 4) +#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK (0x1f << 0) /* - * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, - * CM_DIV_M7_DPLL_CORE + * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE, + * CM_DIV_M7_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT 5 -#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK BITFIELD(5, 5) +#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK (1 << 5) /* - * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, - * CM_DIV_M7_DPLL_CORE + * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE, + * CM_DIV_M7_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT 8 -#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK BITFIELD(8, 8) +#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK (1 << 8) /* - * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, - * CM_DIV_M7_DPLL_CORE + * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE, + * CM_DIV_M7_DPLL_PER */ #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT 12 -#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK BITFIELD(12, 12) - -/* - * Used by PRM_PRM_PROFILING_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, - * CM_WKUP_KEYBOARD_CLKCTRL, CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, - * CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, - * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, - * CM_WKUP_WDT2_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, - * CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, - * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL, - * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, - * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, - * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, - * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL, - * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL, - * CM_MEMIF_EMIF_H2_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, CM_GFX_GFX_CLKCTRL, - * CM_L4PER_ADC_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL, - * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL, - * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL, - * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL, - * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, - * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, - * CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, - * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, - * CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, - * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, - * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, - * CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, - * CM_L4PER_MSPROHG_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, - * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, - * CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, - * CM_L4SEC_DES3DES_CLKCTRL, CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, - * CM_L4SEC_SHA2MD51_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, +#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK (1 << 12) + +/* + * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, + * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, + * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, + * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, + * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL, + * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, + * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, + * CM_CM1_PROFILING_CLKCTRL, CM_CM1_PROFILING_CLKCTRL_RESTORE, + * CM_CM2_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL_RESTORE, + * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, + * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, + * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, + * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL, - * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL, - * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_CAM_FDIF_CLKCTRL, - * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, - * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, - * CM_L3INSTR_L3_3_CLKCTRL_RESTORE, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE, - * CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE, CM_L4PER_GPIO2_CLKCTRL_RESTORE, - * CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE, - * CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE, - * CM_ALWON_MDMINTC_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, - * CM_ALWON_SR_MPU_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, CM_IVAHD_SL2_CLKCTRL, - * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_CM2_PROFILING_CLKCTRL, - * CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL, - * CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, - * CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL, - * CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, CM1_ABE_TIMER5_CLKCTRL, - * CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, - * CM1_ABE_WDT3_CLKCTRL, CM_CM1_PROFILING_CLKCTRL + * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_HOST_FS_CLKCTRL, + * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, + * CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, CM_L3INIT_XHPI_CLKCTRL, + * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL_RESTORE, + * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE, + * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE, + * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL, + * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL, + * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL, + * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL, + * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL, + * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, + * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE, + * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE, + * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE, + * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE, + * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE, + * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, + * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, + * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, + * CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, + * CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, + * CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, + * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL, + * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, + * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, + * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, + * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL, + * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL, + * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL, + * CM_MEMIF_EMIF_H2_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, + * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL, + * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, + * CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, + * CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL */ #define OMAP4430_IDLEST_SHIFT 16 -#define OMAP4430_IDLEST_MASK BITFIELD(16, 17) +#define OMAP4430_IDLEST_MASK (0x3 << 16) -/* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ +/* + * Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, + * CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE + */ #define OMAP4430_ISS_DYNDEP_SHIFT 9 -#define OMAP4430_ISS_DYNDEP_MASK BITFIELD(9, 9) +#define OMAP4430_ISS_DYNDEP_MASK (1 << 9) /* - * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, - * CM_MPU_STATICDEP, CM_TESLA_STATICDEP + * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, + * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP */ #define OMAP4430_ISS_STATDEP_SHIFT 9 -#define OMAP4430_ISS_STATDEP_MASK BITFIELD(9, 9) +#define OMAP4430_ISS_STATDEP_MASK (1 << 9) -/* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ +/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_TESLA_DYNAMICDEP */ #define OMAP4430_IVAHD_DYNDEP_SHIFT 2 -#define OMAP4430_IVAHD_DYNDEP_MASK BITFIELD(2, 2) +#define OMAP4430_IVAHD_DYNDEP_MASK (1 << 2) /* - * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, - * CM_GFX_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP, - * CM_SDMA_STATICDEP_RESTORE, CM_DSS_STATICDEP, CM_MPU_STATICDEP, - * CM_TESLA_STATICDEP + * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, + * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, + * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, + * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP */ #define OMAP4430_IVAHD_STATDEP_SHIFT 2 -#define OMAP4430_IVAHD_STATDEP_MASK BITFIELD(2, 2) +#define OMAP4430_IVAHD_STATDEP_MASK (1 << 2) -/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ +/* + * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, + * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, CM_L4PER_DYNAMICDEP_RESTORE + */ #define OMAP4430_L3INIT_DYNDEP_SHIFT 7 -#define OMAP4430_L3INIT_DYNDEP_MASK BITFIELD(7, 7) +#define OMAP4430_L3INIT_DYNDEP_MASK (1 << 7) /* - * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, - * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, CM_TESLA_STATICDEP + * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP, + * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, + * CM_TESLA_STATICDEP */ #define OMAP4430_L3INIT_STATDEP_SHIFT 7 -#define OMAP4430_L3INIT_STATDEP_MASK BITFIELD(7, 7) +#define OMAP4430_L3INIT_STATDEP_MASK (1 << 7) /* - * Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, - * CM_DSS_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP + * Used by CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_2_DYNAMICDEP, + * CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, + * CM_L4CFG_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ #define OMAP4430_L3_1_DYNDEP_SHIFT 5 -#define OMAP4430_L3_1_DYNDEP_MASK BITFIELD(5, 5) +#define OMAP4430_L3_1_DYNDEP_MASK (1 << 5) /* - * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, - * CM_GFX_STATICDEP, CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP, - * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP, - * CM_MPU_STATICDEP, CM_TESLA_STATICDEP + * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, + * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, + * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, + * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP */ #define OMAP4430_L3_1_STATDEP_SHIFT 5 -#define OMAP4430_L3_1_STATDEP_MASK BITFIELD(5, 5) +#define OMAP4430_L3_1_STATDEP_MASK (1 << 5) /* - * Used by CM_EMU_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP, - * CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_SDMA_DYNAMICDEP, - * CM_GFX_DYNAMICDEP, CM_L4SEC_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, - * CM_CAM_DYNAMICDEP, CM_IVAHD_DYNAMICDEP + * Used by CM_CAM_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, + * CM_DUCATI_DYNAMICDEP, CM_EMU_DYNAMICDEP, CM_GFX_DYNAMICDEP, + * CM_IVAHD_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_1_DYNAMICDEP, + * CM_L3_1_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, + * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP */ #define OMAP4430_L3_2_DYNDEP_SHIFT 6 -#define OMAP4430_L3_2_DYNDEP_MASK BITFIELD(6, 6) +#define OMAP4430_L3_2_DYNDEP_MASK (1 << 6) /* - * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, - * CM_GFX_STATICDEP, CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP, - * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP, - * CM_MPU_STATICDEP, CM_TESLA_STATICDEP + * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, + * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, + * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, + * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP */ #define OMAP4430_L3_2_STATDEP_SHIFT 6 -#define OMAP4430_L3_2_STATDEP_MASK BITFIELD(6, 6) +#define OMAP4430_L3_2_STATDEP_MASK (1 << 6) -/* Used by CM_L3_1_DYNAMICDEP */ +/* Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE */ #define OMAP4430_L4CFG_DYNDEP_SHIFT 12 -#define OMAP4430_L4CFG_DYNDEP_MASK BITFIELD(12, 12) +#define OMAP4430_L4CFG_DYNDEP_MASK (1 << 12) /* - * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, - * CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, - * CM_TESLA_STATICDEP + * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP, + * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, + * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP */ #define OMAP4430_L4CFG_STATDEP_SHIFT 12 -#define OMAP4430_L4CFG_STATDEP_MASK BITFIELD(12, 12) +#define OMAP4430_L4CFG_STATDEP_MASK (1 << 12) -/* Used by CM_L3_2_DYNAMICDEP */ +/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */ #define OMAP4430_L4PER_DYNDEP_SHIFT 13 -#define OMAP4430_L4PER_DYNDEP_MASK BITFIELD(13, 13) +#define OMAP4430_L4PER_DYNDEP_MASK (1 << 13) /* - * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, - * CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, - * CM_MPU_STATICDEP, CM_TESLA_STATICDEP + * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP, + * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, + * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP */ #define OMAP4430_L4PER_STATDEP_SHIFT 13 -#define OMAP4430_L4PER_STATDEP_MASK BITFIELD(13, 13) +#define OMAP4430_L4PER_STATDEP_MASK (1 << 13) -/* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ +/* + * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, + * CM_L4PER_DYNAMICDEP_RESTORE + */ #define OMAP4430_L4SEC_DYNDEP_SHIFT 14 -#define OMAP4430_L4SEC_DYNDEP_MASK BITFIELD(14, 14) +#define OMAP4430_L4SEC_DYNDEP_MASK (1 << 14) /* - * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_L3INIT_STATICDEP, - * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP + * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, + * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE */ #define OMAP4430_L4SEC_STATDEP_SHIFT 14 -#define OMAP4430_L4SEC_STATDEP_MASK BITFIELD(14, 14) +#define OMAP4430_L4SEC_STATDEP_MASK (1 << 14) -/* Used by CM_L4CFG_DYNAMICDEP */ +/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ #define OMAP4430_L4WKUP_DYNDEP_SHIFT 15 -#define OMAP4430_L4WKUP_DYNDEP_MASK BITFIELD(15, 15) +#define OMAP4430_L4WKUP_DYNDEP_MASK (1 << 15) /* - * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_L3INIT_STATICDEP, - * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, CM_TESLA_STATICDEP + * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, + * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP */ #define OMAP4430_L4WKUP_STATDEP_SHIFT 15 -#define OMAP4430_L4WKUP_STATDEP_MASK BITFIELD(15, 15) +#define OMAP4430_L4WKUP_STATDEP_MASK (1 << 15) /* - * Used by CM_D2D_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, - * CM_MPU_DYNAMICDEP + * Used by CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, CM_L3_1_DYNAMICDEP, + * CM_L3_1_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, + * CM_L4CFG_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP */ #define OMAP4430_MEMIF_DYNDEP_SHIFT 4 -#define OMAP4430_MEMIF_DYNDEP_MASK BITFIELD(4, 4) +#define OMAP4430_MEMIF_DYNDEP_MASK (1 << 4) /* - * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, - * CM_GFX_STATICDEP, CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP, - * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP, - * CM_MPU_STATICDEP, CM_TESLA_STATICDEP + * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, + * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, + * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, + * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP */ #define OMAP4430_MEMIF_STATDEP_SHIFT 4 -#define OMAP4430_MEMIF_STATDEP_MASK BITFIELD(4, 4) +#define OMAP4430_MEMIF_STATDEP_MASK (1 << 4) /* - * Used by CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO, - * CM_SSC_MODFREQDIV_DPLL_USB, CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, - * CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, - * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA, - * CM_SSC_MODFREQDIV_DPLL_MPU + * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, + * CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, CM_SSC_MODFREQDIV_DPLL_DDRPHY, + * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU, + * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO, + * CM_SSC_MODFREQDIV_DPLL_USB */ #define OMAP4430_MODFREQDIV_EXPONENT_SHIFT 8 -#define OMAP4430_MODFREQDIV_EXPONENT_MASK BITFIELD(8, 10) +#define OMAP4430_MODFREQDIV_EXPONENT_MASK (0x7 << 8) /* - * Used by CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO, - * CM_SSC_MODFREQDIV_DPLL_USB, CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, - * CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, - * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA, - * CM_SSC_MODFREQDIV_DPLL_MPU + * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, + * CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, CM_SSC_MODFREQDIV_DPLL_DDRPHY, + * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU, + * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO, + * CM_SSC_MODFREQDIV_DPLL_USB */ #define OMAP4430_MODFREQDIV_MANTISSA_SHIFT 0 -#define OMAP4430_MODFREQDIV_MANTISSA_MASK BITFIELD(0, 6) - -/* - * Used by PRM_PRM_PROFILING_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, - * CM_WKUP_KEYBOARD_CLKCTRL, CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, - * CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, - * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, - * CM_WKUP_WDT2_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, - * CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, - * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL, - * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, - * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, - * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, - * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL, - * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL, - * CM_MEMIF_EMIF_H2_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, CM_GFX_GFX_CLKCTRL, - * CM_L4PER_ADC_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL, - * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL, - * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL, - * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL, - * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, - * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, - * CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, - * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, - * CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, - * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, - * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, - * CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, - * CM_L4PER_MSPROHG_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, - * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, - * CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, - * CM_L4SEC_DES3DES_CLKCTRL, CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, - * CM_L4SEC_SHA2MD51_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, +#define OMAP4430_MODFREQDIV_MANTISSA_MASK (0x7f << 0) + +/* + * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, + * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, + * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, + * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, + * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL, + * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, + * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, + * CM_CM1_PROFILING_CLKCTRL, CM_CM1_PROFILING_CLKCTRL_RESTORE, + * CM_CM2_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL_RESTORE, + * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, + * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, + * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, + * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL, - * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL, - * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_CAM_FDIF_CLKCTRL, - * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, - * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, - * CM_L3INSTR_L3_3_CLKCTRL_RESTORE, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE, - * CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE, CM_L4PER_GPIO2_CLKCTRL_RESTORE, - * CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE, - * CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE, - * CM_ALWON_MDMINTC_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, - * CM_ALWON_SR_MPU_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, CM_IVAHD_SL2_CLKCTRL, - * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_CM2_PROFILING_CLKCTRL, - * CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL, - * CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, - * CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL, - * CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, CM1_ABE_TIMER5_CLKCTRL, - * CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, - * CM1_ABE_WDT3_CLKCTRL, CM_CM1_PROFILING_CLKCTRL + * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_HOST_FS_CLKCTRL, + * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, + * CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, CM_L3INIT_XHPI_CLKCTRL, + * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL_RESTORE, + * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE, + * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE, + * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL, + * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL, + * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL, + * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL, + * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL, + * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, + * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE, + * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE, + * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE, + * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE, + * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE, + * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, + * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, + * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, + * CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, + * CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, + * CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, + * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL, + * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, + * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, + * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, + * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL, + * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL, + * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL, + * CM_MEMIF_EMIF_H2_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, + * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL, + * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, + * CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, + * CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL */ #define OMAP4430_MODULEMODE_SHIFT 0 -#define OMAP4430_MODULEMODE_MASK BITFIELD(0, 1) +#define OMAP4430_MODULEMODE_MASK (0x3 << 0) /* Used by CM_DSS_DSS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT 9 -#define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK BITFIELD(9, 9) +#define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK (1 << 9) /* Used by CM_WKUP_BANDGAP_CLKCTRL */ #define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT 8 -#define OMAP4430_OPTFCLKEN_BGAP_32K_MASK BITFIELD(8, 8) +#define OMAP4430_OPTFCLKEN_BGAP_32K_MASK (1 << 8) -/* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */ -#define OMAP4430_OPTFCLKEN_CLK32K_SHIFT 9 -#define OMAP4430_OPTFCLKEN_CLK32K_MASK BITFIELD(9, 9) +/* Used by CM_ALWON_USBPHY_CLKCTRL */ +#define OMAP4430_OPTFCLKEN_CLK32K_SHIFT 8 +#define OMAP4430_OPTFCLKEN_CLK32K_MASK (1 << 8) /* Used by CM_CAM_ISS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_CTRLCLK_MASK BITFIELD(8, 8) +#define OMAP4430_OPTFCLKEN_CTRLCLK_MASK (1 << 8) /* - * Used by CM_WKUP_GPIO1_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL, - * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, - * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE, - * CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE, - * CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE + * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE, + * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE, + * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE, + * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE, + * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE, CM_WKUP_GPIO1_CLKCTRL */ #define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_DBCLK_MASK BITFIELD(8, 8) +#define OMAP4430_OPTFCLKEN_DBCLK_MASK (1 << 8) /* Used by CM_MEMIF_DLL_CLKCTRL, CM_MEMIF_DLL_H_CLKCTRL */ #define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_DLL_CLK_MASK BITFIELD(8, 8) +#define OMAP4430_OPTFCLKEN_DLL_CLK_MASK (1 << 8) /* Used by CM_DSS_DSS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_DSSCLK_MASK BITFIELD(8, 8) +#define OMAP4430_OPTFCLKEN_DSSCLK_MASK (1 << 8) + +/* Used by CM_WKUP_USIM_CLKCTRL */ +#define OMAP4430_OPTFCLKEN_FCLK_SHIFT 8 +#define OMAP4430_OPTFCLKEN_FCLK_MASK (1 << 8) /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_FCLK0_SHIFT 8 -#define OMAP4430_OPTFCLKEN_FCLK0_MASK BITFIELD(8, 8) +#define OMAP4430_OPTFCLKEN_FCLK0_MASK (1 << 8) /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_FCLK1_SHIFT 9 -#define OMAP4430_OPTFCLKEN_FCLK1_MASK BITFIELD(9, 9) +#define OMAP4430_OPTFCLKEN_FCLK1_MASK (1 << 9) /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10 -#define OMAP4430_OPTFCLKEN_FCLK2_MASK BITFIELD(10, 10) +#define OMAP4430_OPTFCLKEN_FCLK2_MASK (1 << 10) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ #define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15 -#define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK BITFIELD(15, 15) +#define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK (1 << 15) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13 -#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK BITFIELD(13, 13) +#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK (1 << 13) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14 -#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK BITFIELD(14, 14) +#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK (1 << 14) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11 -#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK BITFIELD(11, 11) +#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK (1 << 11) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12 -#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK BITFIELD(12, 12) +#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK (1 << 12) /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK BITFIELD(8, 8) +#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK (1 << 8) /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT 9 -#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK BITFIELD(9, 9) +#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK (1 << 9) /* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */ #define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT 8 -#define OMAP4430_OPTFCLKEN_PHY_48M_MASK BITFIELD(8, 8) +#define OMAP4430_OPTFCLKEN_PHY_48M_MASK (1 << 8) /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT 10 -#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK BITFIELD(10, 10) +#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK (1 << 10) /* Renamed from OPTFCLKEN_SLIMBUS_CLK Used by CM1_ABE_SLIMBUS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT 11 -#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK BITFIELD(11, 11) +#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK (1 << 11) /* Used by CM_DSS_DSS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT 10 -#define OMAP4430_OPTFCLKEN_SYS_CLK_MASK BITFIELD(10, 10) +#define OMAP4430_OPTFCLKEN_SYS_CLK_MASK (1 << 10) /* Used by CM_DSS_DSS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT 11 -#define OMAP4430_OPTFCLKEN_TV_CLK_MASK BITFIELD(11, 11) +#define OMAP4430_OPTFCLKEN_TV_CLK_MASK (1 << 11) /* Used by CM_L3INIT_UNIPRO1_CLKCTRL */ #define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK BITFIELD(8, 8) +#define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK (1 << 8) /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK BITFIELD(8, 8) +#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK (1 << 8) /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9 -#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK BITFIELD(9, 9) +#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK (1 << 9) /* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10 -#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK BITFIELD(10, 10) +#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK (1 << 10) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK BITFIELD(8, 8) +#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK (1 << 8) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9 -#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK BITFIELD(9, 9) +#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK (1 << 9) /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10 -#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK BITFIELD(10, 10) +#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK (1 << 10) /* Used by CM_L3INIT_USB_OTG_CLKCTRL */ #define OMAP4430_OPTFCLKEN_XCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_XCLK_MASK BITFIELD(8, 8) +#define OMAP4430_OPTFCLKEN_XCLK_MASK (1 << 8) -/* Used by CM_EMU_OVERRIDE_DPLL_PER, CM_EMU_OVERRIDE_DPLL_CORE */ +/* Used by CM_EMU_OVERRIDE_DPLL_CORE */ #define OMAP4430_OVERRIDE_ENABLE_SHIFT 19 -#define OMAP4430_OVERRIDE_ENABLE_MASK BITFIELD(19, 19) +#define OMAP4430_OVERRIDE_ENABLE_MASK (1 << 19) /* Used by CM_CLKSEL_ABE */ #define OMAP4430_PAD_CLKS_GATE_SHIFT 8 -#define OMAP4430_PAD_CLKS_GATE_MASK BITFIELD(8, 8) +#define OMAP4430_PAD_CLKS_GATE_MASK (1 << 8) /* Used by CM_CORE_DVFS_CURRENT, CM_IVA_DVFS_CURRENT */ #define OMAP4430_PERF_CURRENT_SHIFT 0 -#define OMAP4430_PERF_CURRENT_MASK BITFIELD(0, 7) +#define OMAP4430_PERF_CURRENT_MASK (0xff << 0) /* * Used by CM_CORE_DVFS_PERF1, CM_CORE_DVFS_PERF2, CM_CORE_DVFS_PERF3, @@ -1316,159 +1355,173 @@ * CM_IVA_DVFS_PERF_TESLA */ #define OMAP4430_PERF_REQ_SHIFT 0 -#define OMAP4430_PERF_REQ_MASK BITFIELD(0, 7) - -/* Used by CM_EMU_OVERRIDE_DPLL_PER */ -#define OMAP4430_PER_DPLL_EMU_DIV_SHIFT 0 -#define OMAP4430_PER_DPLL_EMU_DIV_MASK BITFIELD(0, 6) - -/* Used by CM_EMU_OVERRIDE_DPLL_PER */ -#define OMAP4430_PER_DPLL_EMU_MULT_SHIFT 8 -#define OMAP4430_PER_DPLL_EMU_MULT_MASK BITFIELD(8, 18) +#define OMAP4430_PERF_REQ_MASK (0xff << 0) /* Used by CM_RESTORE_ST */ #define OMAP4430_PHASE1_COMPLETED_SHIFT 0 -#define OMAP4430_PHASE1_COMPLETED_MASK BITFIELD(0, 0) +#define OMAP4430_PHASE1_COMPLETED_MASK (1 << 0) /* Used by CM_RESTORE_ST */ #define OMAP4430_PHASE2A_COMPLETED_SHIFT 1 -#define OMAP4430_PHASE2A_COMPLETED_MASK BITFIELD(1, 1) +#define OMAP4430_PHASE2A_COMPLETED_MASK (1 << 1) /* Used by CM_RESTORE_ST */ #define OMAP4430_PHASE2B_COMPLETED_SHIFT 2 -#define OMAP4430_PHASE2B_COMPLETED_MASK BITFIELD(2, 2) +#define OMAP4430_PHASE2B_COMPLETED_MASK (1 << 2) /* Used by CM_EMU_DEBUGSS_CLKCTRL */ #define OMAP4430_PMD_STM_MUX_CTRL_SHIFT 20 -#define OMAP4430_PMD_STM_MUX_CTRL_MASK BITFIELD(20, 21) +#define OMAP4430_PMD_STM_MUX_CTRL_MASK (0x3 << 20) /* Used by CM_EMU_DEBUGSS_CLKCTRL */ #define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22 -#define OMAP4430_PMD_TRACE_MUX_CTRL_MASK BITFIELD(22, 23) +#define OMAP4430_PMD_TRACE_MUX_CTRL_MASK (0x3 << 22) -/* Used by CM_DYN_DEP_PRESCAL */ +/* Used by CM_DYN_DEP_PRESCAL, CM_DYN_DEP_PRESCAL_RESTORE */ #define OMAP4430_PRESCAL_SHIFT 0 -#define OMAP4430_PRESCAL_MASK BITFIELD(0, 5) +#define OMAP4430_PRESCAL_MASK (0x3f << 0) -/* Used by REVISION_CM2, REVISION_CM1 */ -#define OMAP4430_REV_SHIFT 0 -#define OMAP4430_REV_MASK BITFIELD(0, 7) +/* Used by REVISION_CM1, REVISION_CM2 */ +#define OMAP4430_R_RTL_SHIFT 11 +#define OMAP4430_R_RTL_MASK (0x1f << 11) /* - * Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, - * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE + * Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, + * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ #define OMAP4430_SAR_MODE_SHIFT 4 -#define OMAP4430_SAR_MODE_MASK BITFIELD(4, 4) +#define OMAP4430_SAR_MODE_MASK (1 << 4) /* Used by CM_SCALE_FCLK */ #define OMAP4430_SCALE_FCLK_SHIFT 0 -#define OMAP4430_SCALE_FCLK_MASK BITFIELD(0, 0) +#define OMAP4430_SCALE_FCLK_MASK (1 << 0) + +/* Used by REVISION_CM1, REVISION_CM2 */ +#define OMAP4430_SCHEME_SHIFT 30 +#define OMAP4430_SCHEME_MASK (0x3 << 30) -/* Used by CM_L4CFG_DYNAMICDEP */ +/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ #define OMAP4430_SDMA_DYNDEP_SHIFT 11 -#define OMAP4430_SDMA_DYNDEP_MASK BITFIELD(11, 11) +#define OMAP4430_SDMA_DYNDEP_MASK (1 << 11) /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ #define OMAP4430_SDMA_STATDEP_SHIFT 11 -#define OMAP4430_SDMA_STATDEP_MASK BITFIELD(11, 11) +#define OMAP4430_SDMA_STATDEP_MASK (1 << 11) /* Used by CM_CLKSEL_ABE */ #define OMAP4430_SLIMBUS_CLK_GATE_SHIFT 10 -#define OMAP4430_SLIMBUS_CLK_GATE_MASK BITFIELD(10, 10) +#define OMAP4430_SLIMBUS_CLK_GATE_MASK (1 << 10) /* - * Used by CM_EMU_DEBUGSS_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, - * CM_DUCATI_DUCATI_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, CM_GFX_GFX_CLKCTRL, - * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, + * Used by CM1_ABE_AESS_CLKCTRL, CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, + * CM_D2D_SAD2D_CLKCTRL, CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, + * CM_DUCATI_DUCATI_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, + * CM_IVAHD_IVAHD_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, - * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL, - * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_CAM_FDIF_CLKCTRL, - * CM_CAM_ISS_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, - * CM_IVAHD_IVAHD_CLKCTRL, CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, - * CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL + * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, + * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL, + * CM_L3INIT_XHPI_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL, + * CM_SDMA_SDMA_CLKCTRL, CM_TESLA_TESLA_CLKCTRL */ #define OMAP4430_STBYST_SHIFT 18 -#define OMAP4430_STBYST_MASK BITFIELD(18, 18) +#define OMAP4430_STBYST_MASK (1 << 18) /* - * Used by CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB, - * CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY, - * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU + * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY, + * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, + * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB */ #define OMAP4430_ST_DPLL_CLK_SHIFT 0 -#define OMAP4430_ST_DPLL_CLK_MASK BITFIELD(0, 0) +#define OMAP4430_ST_DPLL_CLK_MASK (1 << 0) /* Used by CM_CLKDCOLDO_DPLL_USB */ #define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT 9 -#define OMAP4430_ST_DPLL_CLKDCOLDO_MASK BITFIELD(9, 9) +#define OMAP4430_ST_DPLL_CLKDCOLDO_MASK (1 << 9) /* - * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB, CM_DIV_M2_DPLL_CORE_RESTORE, - * CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, - * CM_DIV_M2_DPLL_MPU + * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, + * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU, + * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB */ #define OMAP4430_ST_DPLL_CLKOUT_SHIFT 9 -#define OMAP4430_ST_DPLL_CLKOUT_MASK BITFIELD(9, 9) +#define OMAP4430_ST_DPLL_CLKOUT_MASK (1 << 9) /* - * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE, - * CM_DIV_M3_DPLL_CORE + * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, + * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER */ #define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT 9 -#define OMAP4430_ST_DPLL_CLKOUTHIF_MASK BITFIELD(9, 9) +#define OMAP4430_ST_DPLL_CLKOUTHIF_MASK (1 << 9) -/* Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, CM_DIV_M2_DPLL_ABE */ +/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */ #define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT 11 -#define OMAP4430_ST_DPLL_CLKOUTX2_MASK BITFIELD(11, 11) +#define OMAP4430_ST_DPLL_CLKOUTX2_MASK (1 << 11) /* - * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, - * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA + * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, + * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER */ #define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT 9 -#define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK BITFIELD(9, 9) +#define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9) /* - * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, - * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA + * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, + * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER */ #define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT 9 -#define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK BITFIELD(9, 9) +#define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9) /* - * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, - * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY + * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE, + * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ #define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT 9 -#define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK BITFIELD(9, 9) +#define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9) /* - * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, - * CM_DIV_M7_DPLL_CORE + * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE, + * CM_DIV_M7_DPLL_PER */ #define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT 9 -#define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK BITFIELD(9, 9) +#define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK (1 << 9) + +/* + * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY, + * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, + * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB + */ +#define OMAP4430_ST_MN_BYPASS_SHIFT 8 +#define OMAP4430_ST_MN_BYPASS_MASK (1 << 8) /* Used by CM_SYS_CLKSEL */ #define OMAP4430_SYS_CLKSEL_SHIFT 0 -#define OMAP4430_SYS_CLKSEL_MASK BITFIELD(0, 2) +#define OMAP4430_SYS_CLKSEL_MASK (0x7 << 0) -/* Used by CM_L4CFG_DYNAMICDEP */ +/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ #define OMAP4430_TESLA_DYNDEP_SHIFT 1 -#define OMAP4430_TESLA_DYNDEP_MASK BITFIELD(1, 1) +#define OMAP4430_TESLA_DYNDEP_MASK (1 << 1) /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ #define OMAP4430_TESLA_STATDEP_SHIFT 1 -#define OMAP4430_TESLA_STATDEP_MASK BITFIELD(1, 1) +#define OMAP4430_TESLA_STATDEP_MASK (1 << 1) /* - * Used by CM_EMU_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP, - * CM_L3_1_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, - * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP + * Used by CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, CM_DUCATI_DYNAMICDEP, + * CM_EMU_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE, + * CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, + * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, + * CM_L4PER_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ #define OMAP4430_WINDOWSIZE_SHIFT 24 -#define OMAP4430_WINDOWSIZE_MASK BITFIELD(24, 27) +#define OMAP4430_WINDOWSIZE_MASK (0xf << 24) + +/* Used by REVISION_CM1, REVISION_CM2 */ +#define OMAP4430_X_MAJOR_SHIFT 8 +#define OMAP4430_X_MAJOR_MASK (0x7 << 8) + +/* Used by REVISION_CM1, REVISION_CM2 */ +#define OMAP4430_Y_MINOR_SHIFT 0 +#define OMAP4430_Y_MINOR_MASK (0x3f << 0) #endif diff --git a/arch/arm/mach-omap2/prm-regbits-44xx.h b/arch/arm/mach-omap2/prm-regbits-44xx.h index 597be4a..25b19b6 100644 --- a/arch/arm/mach-omap2/prm-regbits-44xx.h +++ b/arch/arm/mach-omap2/prm-regbits-44xx.h @@ -1,8 +1,8 @@ /* * OMAP44xx Power Management register bits * - * Copyright (C) 2009 Texas Instruments, Inc. - * Copyright (C) 2009 Nokia Corporation + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * Copyright (C) 2009-2010 Nokia Corporation * * Paul Walmsley (paul@pwsan.com) * Rajendra Nayak (rnayak@ti.com) @@ -30,587 +30,611 @@ * PRM_LDO_SRAM_MPU_SETUP */ #define OMAP4430_ABBOFF_ACT_EXPORT_SHIFT 1 -#define OMAP4430_ABBOFF_ACT_EXPORT_MASK BITFIELD(1, 1) +#define OMAP4430_ABBOFF_ACT_EXPORT_MASK (1 << 1) /* * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, * PRM_LDO_SRAM_MPU_SETUP */ #define OMAP4430_ABBOFF_SLEEP_EXPORT_SHIFT 2 -#define OMAP4430_ABBOFF_SLEEP_EXPORT_MASK BITFIELD(2, 2) +#define OMAP4430_ABBOFF_SLEEP_EXPORT_MASK (1 << 2) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_ABB_IVA_DONE_EN_SHIFT 31 -#define OMAP4430_ABB_IVA_DONE_EN_MASK BITFIELD(31, 31) +#define OMAP4430_ABB_IVA_DONE_EN_MASK (1 << 31) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_ABB_IVA_DONE_ST_SHIFT 31 -#define OMAP4430_ABB_IVA_DONE_ST_MASK BITFIELD(31, 31) +#define OMAP4430_ABB_IVA_DONE_ST_MASK (1 << 31) /* Used by PRM_IRQENABLE_MPU_2 */ #define OMAP4430_ABB_MPU_DONE_EN_SHIFT 7 -#define OMAP4430_ABB_MPU_DONE_EN_MASK BITFIELD(7, 7) +#define OMAP4430_ABB_MPU_DONE_EN_MASK (1 << 7) /* Used by PRM_IRQSTATUS_MPU_2 */ #define OMAP4430_ABB_MPU_DONE_ST_SHIFT 7 -#define OMAP4430_ABB_MPU_DONE_ST_MASK BITFIELD(7, 7) +#define OMAP4430_ABB_MPU_DONE_ST_MASK (1 << 7) /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ #define OMAP4430_ACTIVE_FBB_SEL_SHIFT 2 -#define OMAP4430_ACTIVE_FBB_SEL_MASK BITFIELD(2, 2) +#define OMAP4430_ACTIVE_FBB_SEL_MASK (1 << 2) /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ #define OMAP4430_ACTIVE_RBB_SEL_SHIFT 1 -#define OMAP4430_ACTIVE_RBB_SEL_MASK BITFIELD(1, 1) +#define OMAP4430_ACTIVE_RBB_SEL_MASK (1 << 1) /* Used by PM_ABE_PWRSTCTRL */ #define OMAP4430_AESSMEM_ONSTATE_SHIFT 16 -#define OMAP4430_AESSMEM_ONSTATE_MASK BITFIELD(16, 17) +#define OMAP4430_AESSMEM_ONSTATE_MASK (0x3 << 16) /* Used by PM_ABE_PWRSTCTRL */ #define OMAP4430_AESSMEM_RETSTATE_SHIFT 8 -#define OMAP4430_AESSMEM_RETSTATE_MASK BITFIELD(8, 8) +#define OMAP4430_AESSMEM_RETSTATE_MASK (1 << 8) /* Used by PM_ABE_PWRSTST */ #define OMAP4430_AESSMEM_STATEST_SHIFT 4 -#define OMAP4430_AESSMEM_STATEST_MASK BITFIELD(4, 5) +#define OMAP4430_AESSMEM_STATEST_MASK (0x3 << 4) /* * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, * PRM_LDO_SRAM_MPU_SETUP */ #define OMAP4430_AIPOFF_SHIFT 8 -#define OMAP4430_AIPOFF_MASK BITFIELD(8, 8) +#define OMAP4430_AIPOFF_MASK (1 << 8) /* Used by PRM_VOLTCTRL */ #define OMAP4430_AUTO_CTRL_VDD_CORE_L_SHIFT 0 -#define OMAP4430_AUTO_CTRL_VDD_CORE_L_MASK BITFIELD(0, 1) +#define OMAP4430_AUTO_CTRL_VDD_CORE_L_MASK (0x3 << 0) /* Used by PRM_VOLTCTRL */ #define OMAP4430_AUTO_CTRL_VDD_IVA_L_SHIFT 4 -#define OMAP4430_AUTO_CTRL_VDD_IVA_L_MASK BITFIELD(4, 5) +#define OMAP4430_AUTO_CTRL_VDD_IVA_L_MASK (0x3 << 4) /* Used by PRM_VOLTCTRL */ #define OMAP4430_AUTO_CTRL_VDD_MPU_L_SHIFT 2 -#define OMAP4430_AUTO_CTRL_VDD_MPU_L_MASK BITFIELD(2, 3) +#define OMAP4430_AUTO_CTRL_VDD_MPU_L_MASK (0x3 << 2) + +/* Used by PRM_VC_ERRST */ +#define OMAP4430_BYPS_RA_ERR_SHIFT 25 +#define OMAP4430_BYPS_RA_ERR_MASK (1 << 25) + +/* Used by PRM_VC_ERRST */ +#define OMAP4430_BYPS_SA_ERR_SHIFT 24 +#define OMAP4430_BYPS_SA_ERR_MASK (1 << 24) + +/* Used by PRM_VC_ERRST */ +#define OMAP4430_BYPS_TIMEOUT_ERR_SHIFT 26 +#define OMAP4430_BYPS_TIMEOUT_ERR_MASK (1 << 26) + +/* Used by PRM_RSTST */ +#define OMAP4430_C2C_RST_SHIFT 10 +#define OMAP4430_C2C_RST_MASK (1 << 10) /* Used by PM_CAM_PWRSTCTRL */ #define OMAP4430_CAM_MEM_ONSTATE_SHIFT 16 -#define OMAP4430_CAM_MEM_ONSTATE_MASK BITFIELD(16, 17) +#define OMAP4430_CAM_MEM_ONSTATE_MASK (0x3 << 16) /* Used by PM_CAM_PWRSTST */ #define OMAP4430_CAM_MEM_STATEST_SHIFT 4 -#define OMAP4430_CAM_MEM_STATEST_MASK BITFIELD(4, 5) +#define OMAP4430_CAM_MEM_STATEST_MASK (0x3 << 4) /* Used by PRM_CLKREQCTRL */ #define OMAP4430_CLKREQ_COND_SHIFT 0 -#define OMAP4430_CLKREQ_COND_MASK BITFIELD(0, 2) +#define OMAP4430_CLKREQ_COND_MASK (0x7 << 0) /* Used by PRM_VC_VAL_SMPS_RA_CMD */ #define OMAP4430_CMDRA_VDD_CORE_L_SHIFT 0 -#define OMAP4430_CMDRA_VDD_CORE_L_MASK BITFIELD(0, 7) +#define OMAP4430_CMDRA_VDD_CORE_L_MASK (0xff << 0) /* Used by PRM_VC_VAL_SMPS_RA_CMD */ #define OMAP4430_CMDRA_VDD_IVA_L_SHIFT 8 -#define OMAP4430_CMDRA_VDD_IVA_L_MASK BITFIELD(8, 15) +#define OMAP4430_CMDRA_VDD_IVA_L_MASK (0xff << 8) /* Used by PRM_VC_VAL_SMPS_RA_CMD */ #define OMAP4430_CMDRA_VDD_MPU_L_SHIFT 16 -#define OMAP4430_CMDRA_VDD_MPU_L_MASK BITFIELD(16, 23) +#define OMAP4430_CMDRA_VDD_MPU_L_MASK (0xff << 16) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_CMD_VDD_CORE_L_SHIFT 4 -#define OMAP4430_CMD_VDD_CORE_L_MASK BITFIELD(4, 4) +#define OMAP4430_CMD_VDD_CORE_L_MASK (1 << 4) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_CMD_VDD_IVA_L_SHIFT 12 -#define OMAP4430_CMD_VDD_IVA_L_MASK BITFIELD(12, 12) +#define OMAP4430_CMD_VDD_IVA_L_MASK (1 << 12) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_CMD_VDD_MPU_L_SHIFT 17 -#define OMAP4430_CMD_VDD_MPU_L_MASK BITFIELD(17, 17) +#define OMAP4430_CMD_VDD_MPU_L_MASK (1 << 17) /* Used by PM_CORE_PWRSTCTRL */ #define OMAP4430_CORE_OCMRAM_ONSTATE_SHIFT 18 -#define OMAP4430_CORE_OCMRAM_ONSTATE_MASK BITFIELD(18, 19) +#define OMAP4430_CORE_OCMRAM_ONSTATE_MASK (0x3 << 18) /* Used by PM_CORE_PWRSTCTRL */ #define OMAP4430_CORE_OCMRAM_RETSTATE_SHIFT 9 -#define OMAP4430_CORE_OCMRAM_RETSTATE_MASK BITFIELD(9, 9) +#define OMAP4430_CORE_OCMRAM_RETSTATE_MASK (1 << 9) /* Used by PM_CORE_PWRSTST */ #define OMAP4430_CORE_OCMRAM_STATEST_SHIFT 6 -#define OMAP4430_CORE_OCMRAM_STATEST_MASK BITFIELD(6, 7) +#define OMAP4430_CORE_OCMRAM_STATEST_MASK (0x3 << 6) /* Used by PM_CORE_PWRSTCTRL */ #define OMAP4430_CORE_OTHER_BANK_ONSTATE_SHIFT 16 -#define OMAP4430_CORE_OTHER_BANK_ONSTATE_MASK BITFIELD(16, 17) +#define OMAP4430_CORE_OTHER_BANK_ONSTATE_MASK (0x3 << 16) /* Used by PM_CORE_PWRSTCTRL */ #define OMAP4430_CORE_OTHER_BANK_RETSTATE_SHIFT 8 -#define OMAP4430_CORE_OTHER_BANK_RETSTATE_MASK BITFIELD(8, 8) +#define OMAP4430_CORE_OTHER_BANK_RETSTATE_MASK (1 << 8) /* Used by PM_CORE_PWRSTST */ #define OMAP4430_CORE_OTHER_BANK_STATEST_SHIFT 4 -#define OMAP4430_CORE_OTHER_BANK_STATEST_MASK BITFIELD(4, 5) +#define OMAP4430_CORE_OTHER_BANK_STATEST_MASK (0x3 << 4) + +/* Used by REVISION_PRM */ +#define OMAP4430_CUSTOM_SHIFT 6 +#define OMAP4430_CUSTOM_MASK (0x3 << 6) /* Used by PRM_VC_VAL_BYPASS */ #define OMAP4430_DATA_SHIFT 16 -#define OMAP4430_DATA_MASK BITFIELD(16, 23) +#define OMAP4430_DATA_MASK (0xff << 16) /* Used by PRM_DEVICE_OFF_CTRL */ #define OMAP4430_DEVICE_OFF_ENABLE_SHIFT 0 -#define OMAP4430_DEVICE_OFF_ENABLE_MASK BITFIELD(0, 0) +#define OMAP4430_DEVICE_OFF_ENABLE_MASK (1 << 0) /* Used by PRM_VC_CFG_I2C_MODE */ #define OMAP4430_DFILTEREN_SHIFT 6 -#define OMAP4430_DFILTEREN_MASK BITFIELD(6, 6) +#define OMAP4430_DFILTEREN_MASK (1 << 6) -/* Used by PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */ +/* + * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, + * PRM_LDO_SRAM_MPU_SETUP, PRM_SRAM_WKUP_SETUP + */ +#define OMAP4430_DISABLE_RTA_EXPORT_SHIFT 0 +#define OMAP4430_DISABLE_RTA_EXPORT_MASK (1 << 0) + +/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */ #define OMAP4430_DPLL_ABE_RECAL_EN_SHIFT 4 -#define OMAP4430_DPLL_ABE_RECAL_EN_MASK BITFIELD(4, 4) +#define OMAP4430_DPLL_ABE_RECAL_EN_MASK (1 << 4) -/* Used by PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */ +/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */ #define OMAP4430_DPLL_ABE_RECAL_ST_SHIFT 4 -#define OMAP4430_DPLL_ABE_RECAL_ST_MASK BITFIELD(4, 4) +#define OMAP4430_DPLL_ABE_RECAL_ST_MASK (1 << 4) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_DPLL_CORE_RECAL_EN_SHIFT 0 -#define OMAP4430_DPLL_CORE_RECAL_EN_MASK BITFIELD(0, 0) +#define OMAP4430_DPLL_CORE_RECAL_EN_MASK (1 << 0) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_DPLL_CORE_RECAL_ST_SHIFT 0 -#define OMAP4430_DPLL_CORE_RECAL_ST_MASK BITFIELD(0, 0) +#define OMAP4430_DPLL_CORE_RECAL_ST_MASK (1 << 0) /* Used by PRM_IRQENABLE_MPU */ #define OMAP4430_DPLL_DDRPHY_RECAL_EN_SHIFT 6 -#define OMAP4430_DPLL_DDRPHY_RECAL_EN_MASK BITFIELD(6, 6) +#define OMAP4430_DPLL_DDRPHY_RECAL_EN_MASK (1 << 6) /* Used by PRM_IRQSTATUS_MPU */ #define OMAP4430_DPLL_DDRPHY_RECAL_ST_SHIFT 6 -#define OMAP4430_DPLL_DDRPHY_RECAL_ST_MASK BITFIELD(6, 6) +#define OMAP4430_DPLL_DDRPHY_RECAL_ST_MASK (1 << 6) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */ #define OMAP4430_DPLL_IVA_RECAL_EN_SHIFT 2 -#define OMAP4430_DPLL_IVA_RECAL_EN_MASK BITFIELD(2, 2) +#define OMAP4430_DPLL_IVA_RECAL_EN_MASK (1 << 2) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */ #define OMAP4430_DPLL_IVA_RECAL_ST_SHIFT 2 -#define OMAP4430_DPLL_IVA_RECAL_ST_MASK BITFIELD(2, 2) +#define OMAP4430_DPLL_IVA_RECAL_ST_MASK (1 << 2) /* Used by PRM_IRQENABLE_MPU */ #define OMAP4430_DPLL_MPU_RECAL_EN_SHIFT 1 -#define OMAP4430_DPLL_MPU_RECAL_EN_MASK BITFIELD(1, 1) +#define OMAP4430_DPLL_MPU_RECAL_EN_MASK (1 << 1) /* Used by PRM_IRQSTATUS_MPU */ #define OMAP4430_DPLL_MPU_RECAL_ST_SHIFT 1 -#define OMAP4430_DPLL_MPU_RECAL_ST_MASK BITFIELD(1, 1) +#define OMAP4430_DPLL_MPU_RECAL_ST_MASK (1 << 1) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_DPLL_PER_RECAL_EN_SHIFT 3 -#define OMAP4430_DPLL_PER_RECAL_EN_MASK BITFIELD(3, 3) +#define OMAP4430_DPLL_PER_RECAL_EN_MASK (1 << 3) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_DPLL_PER_RECAL_ST_SHIFT 3 -#define OMAP4430_DPLL_PER_RECAL_ST_MASK BITFIELD(3, 3) +#define OMAP4430_DPLL_PER_RECAL_ST_MASK (1 << 3) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_DPLL_UNIPRO_RECAL_EN_SHIFT 7 -#define OMAP4430_DPLL_UNIPRO_RECAL_EN_MASK BITFIELD(7, 7) +#define OMAP4430_DPLL_UNIPRO_RECAL_EN_MASK (1 << 7) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_DPLL_UNIPRO_RECAL_ST_SHIFT 7 -#define OMAP4430_DPLL_UNIPRO_RECAL_ST_MASK BITFIELD(7, 7) - -/* Used by PRM_IRQENABLE_MPU */ -#define OMAP4430_DPLL_USB_RECAL_EN_SHIFT 5 -#define OMAP4430_DPLL_USB_RECAL_EN_MASK BITFIELD(5, 5) - -/* Used by PRM_IRQSTATUS_MPU */ -#define OMAP4430_DPLL_USB_RECAL_ST_SHIFT 5 -#define OMAP4430_DPLL_USB_RECAL_ST_MASK BITFIELD(5, 5) +#define OMAP4430_DPLL_UNIPRO_RECAL_ST_MASK (1 << 7) /* Used by PM_DSS_PWRSTCTRL */ #define OMAP4430_DSS_MEM_ONSTATE_SHIFT 16 -#define OMAP4430_DSS_MEM_ONSTATE_MASK BITFIELD(16, 17) +#define OMAP4430_DSS_MEM_ONSTATE_MASK (0x3 << 16) /* Used by PM_DSS_PWRSTCTRL */ #define OMAP4430_DSS_MEM_RETSTATE_SHIFT 8 -#define OMAP4430_DSS_MEM_RETSTATE_MASK BITFIELD(8, 8) +#define OMAP4430_DSS_MEM_RETSTATE_MASK (1 << 8) /* Used by PM_DSS_PWRSTST */ #define OMAP4430_DSS_MEM_STATEST_SHIFT 4 -#define OMAP4430_DSS_MEM_STATEST_MASK BITFIELD(4, 5) +#define OMAP4430_DSS_MEM_STATEST_MASK (0x3 << 4) /* Used by PM_CORE_PWRSTCTRL */ #define OMAP4430_DUCATI_L2RAM_ONSTATE_SHIFT 20 -#define OMAP4430_DUCATI_L2RAM_ONSTATE_MASK BITFIELD(20, 21) +#define OMAP4430_DUCATI_L2RAM_ONSTATE_MASK (0x3 << 20) /* Used by PM_CORE_PWRSTCTRL */ #define OMAP4430_DUCATI_L2RAM_RETSTATE_SHIFT 10 -#define OMAP4430_DUCATI_L2RAM_RETSTATE_MASK BITFIELD(10, 10) +#define OMAP4430_DUCATI_L2RAM_RETSTATE_MASK (1 << 10) /* Used by PM_CORE_PWRSTST */ #define OMAP4430_DUCATI_L2RAM_STATEST_SHIFT 8 -#define OMAP4430_DUCATI_L2RAM_STATEST_MASK BITFIELD(8, 9) +#define OMAP4430_DUCATI_L2RAM_STATEST_MASK (0x3 << 8) /* Used by PM_CORE_PWRSTCTRL */ #define OMAP4430_DUCATI_UNICACHE_ONSTATE_SHIFT 22 -#define OMAP4430_DUCATI_UNICACHE_ONSTATE_MASK BITFIELD(22, 23) +#define OMAP4430_DUCATI_UNICACHE_ONSTATE_MASK (0x3 << 22) /* Used by PM_CORE_PWRSTCTRL */ #define OMAP4430_DUCATI_UNICACHE_RETSTATE_SHIFT 11 -#define OMAP4430_DUCATI_UNICACHE_RETSTATE_MASK BITFIELD(11, 11) +#define OMAP4430_DUCATI_UNICACHE_RETSTATE_MASK (1 << 11) /* Used by PM_CORE_PWRSTST */ #define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT 10 -#define OMAP4430_DUCATI_UNICACHE_STATEST_MASK BITFIELD(10, 11) +#define OMAP4430_DUCATI_UNICACHE_STATEST_MASK (0x3 << 10) /* Used by RM_MPU_RSTST */ #define OMAP4430_EMULATION_RST_SHIFT 0 -#define OMAP4430_EMULATION_RST_MASK BITFIELD(0, 0) +#define OMAP4430_EMULATION_RST_MASK (1 << 0) /* Used by RM_DUCATI_RSTST */ #define OMAP4430_EMULATION_RST1ST_SHIFT 3 -#define OMAP4430_EMULATION_RST1ST_MASK BITFIELD(3, 3) +#define OMAP4430_EMULATION_RST1ST_MASK (1 << 3) /* Used by RM_DUCATI_RSTST */ #define OMAP4430_EMULATION_RST2ST_SHIFT 4 -#define OMAP4430_EMULATION_RST2ST_MASK BITFIELD(4, 4) +#define OMAP4430_EMULATION_RST2ST_MASK (1 << 4) /* Used by RM_IVAHD_RSTST */ #define OMAP4430_EMULATION_SEQ1_RST1ST_SHIFT 3 -#define OMAP4430_EMULATION_SEQ1_RST1ST_MASK BITFIELD(3, 3) +#define OMAP4430_EMULATION_SEQ1_RST1ST_MASK (1 << 3) /* Used by RM_IVAHD_RSTST */ #define OMAP4430_EMULATION_SEQ2_RST2ST_SHIFT 4 -#define OMAP4430_EMULATION_SEQ2_RST2ST_MASK BITFIELD(4, 4) +#define OMAP4430_EMULATION_SEQ2_RST2ST_MASK (1 << 4) /* Used by PM_EMU_PWRSTCTRL */ #define OMAP4430_EMU_BANK_ONSTATE_SHIFT 16 -#define OMAP4430_EMU_BANK_ONSTATE_MASK BITFIELD(16, 17) +#define OMAP4430_EMU_BANK_ONSTATE_MASK (0x3 << 16) /* Used by PM_EMU_PWRSTST */ #define OMAP4430_EMU_BANK_STATEST_SHIFT 4 -#define OMAP4430_EMU_BANK_STATEST_MASK BITFIELD(4, 5) - -/* - * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, - * PRM_LDO_SRAM_MPU_SETUP, PRM_SRAM_WKUP_SETUP - */ -#define OMAP4430_ENABLE_RTA_EXPORT_SHIFT 0 -#define OMAP4430_ENABLE_RTA_EXPORT_MASK BITFIELD(0, 0) +#define OMAP4430_EMU_BANK_STATEST_MASK (0x3 << 4) /* * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, * PRM_LDO_SRAM_MPU_SETUP */ -#define OMAP4430_ENFUNC1_SHIFT 3 -#define OMAP4430_ENFUNC1_MASK BITFIELD(3, 3) +#define OMAP4430_ENFUNC1_EXPORT_SHIFT 3 +#define OMAP4430_ENFUNC1_EXPORT_MASK (1 << 3) /* * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, * PRM_LDO_SRAM_MPU_SETUP */ -#define OMAP4430_ENFUNC3_SHIFT 5 -#define OMAP4430_ENFUNC3_MASK BITFIELD(5, 5) +#define OMAP4430_ENFUNC3_EXPORT_SHIFT 5 +#define OMAP4430_ENFUNC3_EXPORT_MASK (1 << 5) /* * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, * PRM_LDO_SRAM_MPU_SETUP */ #define OMAP4430_ENFUNC4_SHIFT 6 -#define OMAP4430_ENFUNC4_MASK BITFIELD(6, 6) +#define OMAP4430_ENFUNC4_MASK (1 << 6) /* * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, * PRM_LDO_SRAM_MPU_SETUP */ #define OMAP4430_ENFUNC5_SHIFT 7 -#define OMAP4430_ENFUNC5_MASK BITFIELD(7, 7) +#define OMAP4430_ENFUNC5_MASK (1 << 7) /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ #define OMAP4430_ERRORGAIN_SHIFT 16 -#define OMAP4430_ERRORGAIN_MASK BITFIELD(16, 23) +#define OMAP4430_ERRORGAIN_MASK (0xff << 16) /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ #define OMAP4430_ERROROFFSET_SHIFT 24 -#define OMAP4430_ERROROFFSET_MASK BITFIELD(24, 31) +#define OMAP4430_ERROROFFSET_MASK (0xff << 24) /* Used by PRM_RSTST */ #define OMAP4430_EXTERNAL_WARM_RST_SHIFT 5 -#define OMAP4430_EXTERNAL_WARM_RST_MASK BITFIELD(5, 5) +#define OMAP4430_EXTERNAL_WARM_RST_MASK (1 << 5) /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ #define OMAP4430_FORCEUPDATE_SHIFT 1 -#define OMAP4430_FORCEUPDATE_MASK BITFIELD(1, 1) +#define OMAP4430_FORCEUPDATE_MASK (1 << 1) /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */ #define OMAP4430_FORCEUPDATEWAIT_SHIFT 8 -#define OMAP4430_FORCEUPDATEWAIT_MASK BITFIELD(8, 31) +#define OMAP4430_FORCEUPDATEWAIT_MASK (0xffffff << 8) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_TESLA */ #define OMAP4430_FORCEWKUP_EN_SHIFT 10 -#define OMAP4430_FORCEWKUP_EN_MASK BITFIELD(10, 10) +#define OMAP4430_FORCEWKUP_EN_MASK (1 << 10) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_TESLA */ #define OMAP4430_FORCEWKUP_ST_SHIFT 10 -#define OMAP4430_FORCEWKUP_ST_MASK BITFIELD(10, 10) +#define OMAP4430_FORCEWKUP_ST_MASK (1 << 10) + +/* Used by REVISION_PRM */ +#define OMAP4430_FUNC_SHIFT 16 +#define OMAP4430_FUNC_MASK (0xfff << 16) /* Used by PM_GFX_PWRSTCTRL */ #define OMAP4430_GFX_MEM_ONSTATE_SHIFT 16 -#define OMAP4430_GFX_MEM_ONSTATE_MASK BITFIELD(16, 17) +#define OMAP4430_GFX_MEM_ONSTATE_MASK (0x3 << 16) /* Used by PM_GFX_PWRSTST */ #define OMAP4430_GFX_MEM_STATEST_SHIFT 4 -#define OMAP4430_GFX_MEM_STATEST_MASK BITFIELD(4, 5) +#define OMAP4430_GFX_MEM_STATEST_MASK (0x3 << 4) /* Used by PRM_RSTST */ #define OMAP4430_GLOBAL_COLD_RST_SHIFT 0 -#define OMAP4430_GLOBAL_COLD_RST_MASK BITFIELD(0, 0) +#define OMAP4430_GLOBAL_COLD_RST_MASK (1 << 0) /* Used by PRM_RSTST */ #define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT 1 -#define OMAP4430_GLOBAL_WARM_SW_RST_MASK BITFIELD(1, 1) +#define OMAP4430_GLOBAL_WARM_SW_RST_MASK (1 << 1) /* Used by PRM_IO_PMCTRL */ #define OMAP4430_GLOBAL_WUEN_SHIFT 16 -#define OMAP4430_GLOBAL_WUEN_MASK BITFIELD(16, 16) +#define OMAP4430_GLOBAL_WUEN_MASK (1 << 16) /* Used by PRM_VC_CFG_I2C_MODE */ #define OMAP4430_HSMCODE_SHIFT 0 -#define OMAP4430_HSMCODE_MASK BITFIELD(0, 2) +#define OMAP4430_HSMCODE_MASK (0x7 << 0) /* Used by PRM_VC_CFG_I2C_MODE */ #define OMAP4430_HSMODEEN_SHIFT 3 -#define OMAP4430_HSMODEEN_MASK BITFIELD(3, 3) +#define OMAP4430_HSMODEEN_MASK (1 << 3) /* Used by PRM_VC_CFG_I2C_CLK */ #define OMAP4430_HSSCLH_SHIFT 16 -#define OMAP4430_HSSCLH_MASK BITFIELD(16, 23) +#define OMAP4430_HSSCLH_MASK (0xff << 16) /* Used by PRM_VC_CFG_I2C_CLK */ #define OMAP4430_HSSCLL_SHIFT 24 -#define OMAP4430_HSSCLL_MASK BITFIELD(24, 31) +#define OMAP4430_HSSCLL_MASK (0xff << 24) /* Used by PM_IVAHD_PWRSTCTRL */ #define OMAP4430_HWA_MEM_ONSTATE_SHIFT 16 -#define OMAP4430_HWA_MEM_ONSTATE_MASK BITFIELD(16, 17) +#define OMAP4430_HWA_MEM_ONSTATE_MASK (0x3 << 16) /* Used by PM_IVAHD_PWRSTCTRL */ #define OMAP4430_HWA_MEM_RETSTATE_SHIFT 8 -#define OMAP4430_HWA_MEM_RETSTATE_MASK BITFIELD(8, 8) +#define OMAP4430_HWA_MEM_RETSTATE_MASK (1 << 8) /* Used by PM_IVAHD_PWRSTST */ #define OMAP4430_HWA_MEM_STATEST_SHIFT 4 -#define OMAP4430_HWA_MEM_STATEST_MASK BITFIELD(4, 5) +#define OMAP4430_HWA_MEM_STATEST_MASK (0x3 << 4) /* Used by RM_MPU_RSTST */ #define OMAP4430_ICECRUSHER_MPU_RST_SHIFT 1 -#define OMAP4430_ICECRUSHER_MPU_RST_MASK BITFIELD(1, 1) +#define OMAP4430_ICECRUSHER_MPU_RST_MASK (1 << 1) /* Used by RM_DUCATI_RSTST */ #define OMAP4430_ICECRUSHER_RST1ST_SHIFT 5 -#define OMAP4430_ICECRUSHER_RST1ST_MASK BITFIELD(5, 5) +#define OMAP4430_ICECRUSHER_RST1ST_MASK (1 << 5) /* Used by RM_DUCATI_RSTST */ #define OMAP4430_ICECRUSHER_RST2ST_SHIFT 6 -#define OMAP4430_ICECRUSHER_RST2ST_MASK BITFIELD(6, 6) +#define OMAP4430_ICECRUSHER_RST2ST_MASK (1 << 6) /* Used by RM_IVAHD_RSTST */ #define OMAP4430_ICECRUSHER_SEQ1_RST1ST_SHIFT 5 -#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_MASK BITFIELD(5, 5) +#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_MASK (1 << 5) /* Used by RM_IVAHD_RSTST */ #define OMAP4430_ICECRUSHER_SEQ2_RST2ST_SHIFT 6 -#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_MASK BITFIELD(6, 6) +#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_MASK (1 << 6) /* Used by PRM_RSTST */ #define OMAP4430_ICEPICK_RST_SHIFT 9 -#define OMAP4430_ICEPICK_RST_MASK BITFIELD(9, 9) +#define OMAP4430_ICEPICK_RST_MASK (1 << 9) /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ #define OMAP4430_INITVDD_SHIFT 2 -#define OMAP4430_INITVDD_MASK BITFIELD(2, 2) +#define OMAP4430_INITVDD_MASK (1 << 2) /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ #define OMAP4430_INITVOLTAGE_SHIFT 8 -#define OMAP4430_INITVOLTAGE_MASK BITFIELD(8, 15) +#define OMAP4430_INITVOLTAGE_MASK (0xff << 8) /* - * Used by PM_EMU_PWRSTST, PM_CORE_PWRSTST, PM_CAM_PWRSTST, PM_L3INIT_PWRSTST, - * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST, - * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST + * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST, + * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST, + * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST */ #define OMAP4430_INTRANSITION_SHIFT 20 -#define OMAP4430_INTRANSITION_MASK BITFIELD(20, 20) +#define OMAP4430_INTRANSITION_MASK (1 << 20) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_IO_EN_SHIFT 9 -#define OMAP4430_IO_EN_MASK BITFIELD(9, 9) +#define OMAP4430_IO_EN_MASK (1 << 9) /* Used by PRM_IO_PMCTRL */ #define OMAP4430_IO_ON_STATUS_SHIFT 5 -#define OMAP4430_IO_ON_STATUS_MASK BITFIELD(5, 5) +#define OMAP4430_IO_ON_STATUS_MASK (1 << 5) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_IO_ST_SHIFT 9 -#define OMAP4430_IO_ST_MASK BITFIELD(9, 9) +#define OMAP4430_IO_ST_MASK (1 << 9) /* Used by PRM_IO_PMCTRL */ #define OMAP4430_ISOCLK_OVERRIDE_SHIFT 0 -#define OMAP4430_ISOCLK_OVERRIDE_MASK BITFIELD(0, 0) +#define OMAP4430_ISOCLK_OVERRIDE_MASK (1 << 0) /* Used by PRM_IO_PMCTRL */ #define OMAP4430_ISOCLK_STATUS_SHIFT 1 -#define OMAP4430_ISOCLK_STATUS_MASK BITFIELD(1, 1) +#define OMAP4430_ISOCLK_STATUS_MASK (1 << 1) /* Used by PRM_IO_PMCTRL */ #define OMAP4430_ISOOVR_EXTEND_SHIFT 4 -#define OMAP4430_ISOOVR_EXTEND_MASK BITFIELD(4, 4) +#define OMAP4430_ISOOVR_EXTEND_MASK (1 << 4) /* Used by PRM_IO_COUNT */ #define OMAP4430_ISO_2_ON_TIME_SHIFT 0 -#define OMAP4430_ISO_2_ON_TIME_MASK BITFIELD(0, 7) +#define OMAP4430_ISO_2_ON_TIME_MASK (0xff << 0) /* Used by PM_L3INIT_PWRSTCTRL */ #define OMAP4430_L3INIT_BANK1_ONSTATE_SHIFT 16 -#define OMAP4430_L3INIT_BANK1_ONSTATE_MASK BITFIELD(16, 17) +#define OMAP4430_L3INIT_BANK1_ONSTATE_MASK (0x3 << 16) /* Used by PM_L3INIT_PWRSTCTRL */ #define OMAP4430_L3INIT_BANK1_RETSTATE_SHIFT 8 -#define OMAP4430_L3INIT_BANK1_RETSTATE_MASK BITFIELD(8, 8) +#define OMAP4430_L3INIT_BANK1_RETSTATE_MASK (1 << 8) /* Used by PM_L3INIT_PWRSTST */ #define OMAP4430_L3INIT_BANK1_STATEST_SHIFT 4 -#define OMAP4430_L3INIT_BANK1_STATEST_MASK BITFIELD(4, 5) +#define OMAP4430_L3INIT_BANK1_STATEST_MASK (0x3 << 4) + +/* + * Used by PM_ABE_PWRSTST, PM_CORE_PWRSTST, PM_IVAHD_PWRSTST, + * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST + */ +#define OMAP4430_LASTPOWERSTATEENTERED_SHIFT 24 +#define OMAP4430_LASTPOWERSTATEENTERED_MASK (0x3 << 24) /* - * Used by PM_CORE_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_ABE_PWRSTCTRL, - * PM_MPU_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_TESLA_PWRSTCTRL, - * PM_IVAHD_PWRSTCTRL + * Used by PM_ABE_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, + * PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, + * PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL */ #define OMAP4430_LOGICRETSTATE_SHIFT 2 -#define OMAP4430_LOGICRETSTATE_MASK BITFIELD(2, 2) +#define OMAP4430_LOGICRETSTATE_MASK (1 << 2) /* - * Used by PM_EMU_PWRSTST, PM_CORE_PWRSTST, PM_CAM_PWRSTST, PM_L3INIT_PWRSTST, - * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST, - * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST + * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST, + * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST, + * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST */ #define OMAP4430_LOGICSTATEST_SHIFT 2 -#define OMAP4430_LOGICSTATEST_MASK BITFIELD(2, 2) +#define OMAP4430_LOGICSTATEST_MASK (1 << 2) /* - * Used by RM_WKUP_GPIO1_CONTEXT, RM_WKUP_KEYBOARD_CONTEXT, - * RM_WKUP_L4WKUP_CONTEXT, RM_WKUP_RTC_CONTEXT, RM_WKUP_SARRAM_CONTEXT, - * RM_WKUP_SYNCTIMER_CONTEXT, RM_WKUP_TIMER12_CONTEXT, RM_WKUP_TIMER1_CONTEXT, - * RM_WKUP_USIM_CONTEXT, RM_WKUP_WDT1_CONTEXT, RM_WKUP_WDT2_CONTEXT, - * RM_EMU_DEBUGSS_CONTEXT, RM_D2D_SAD2D_CONTEXT, RM_D2D_SAD2D_FW_CONTEXT, - * RM_DUCATI_DUCATI_CONTEXT, RM_L3INSTR_L3_3_CONTEXT, - * RM_L3INSTR_L3_INSTR_CONTEXT, RM_L3INSTR_OCP_WP1_CONTEXT, - * RM_L3_1_L3_1_CONTEXT, RM_L3_2_L3_2_CONTEXT, RM_L3_2_OCMC_RAM_CONTEXT, - * RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_SAR_ROM_CONTEXT, RM_MEMIF_DLL_CONTEXT, - * RM_MEMIF_DLL_H_CONTEXT, RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_FW_CONTEXT, - * RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT, RM_L3INIT_CCPTX_CONTEXT, - * RM_L3INIT_EMAC_CONTEXT, RM_L3INIT_P1500_CONTEXT, RM_L3INIT_PCIESS_CONTEXT, - * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT, - * RM_L3INIT_USBPHYOCP2SCP_CONTEXT, RM_L3INIT_XHPI_CONTEXT, - * RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT, + * Used by RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT, * RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT, * RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT, RM_ABE_TIMER5_CONTEXT, * RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT, - * RM_ABE_WDT3_CONTEXT, RM_GFX_GFX_CONTEXT, RM_MPU_MPU_CONTEXT, - * RM_CEFUSE_CEFUSE_CONTEXT, RM_ALWON_MDMINTC_CONTEXT, - * RM_ALWON_SR_CORE_CONTEXT, RM_ALWON_SR_IVA_CONTEXT, RM_ALWON_SR_MPU_CONTEXT, - * RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT, RM_L4PER_ADC_CONTEXT, - * RM_L4PER_DMTIMER10_CONTEXT, RM_L4PER_DMTIMER11_CONTEXT, - * RM_L4PER_DMTIMER2_CONTEXT, RM_L4PER_DMTIMER3_CONTEXT, - * RM_L4PER_DMTIMER4_CONTEXT, RM_L4PER_DMTIMER9_CONTEXT, RM_L4PER_ELM_CONTEXT, - * RM_L4PER_HDQ1W_CONTEXT, RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, - * RM_L4PER_I2C2_CONTEXT, RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT, - * RM_L4PER_I2C5_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCASP2_CONTEXT, - * RM_L4PER_MCASP3_CONTEXT, RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MCSPI1_CONTEXT, - * RM_L4PER_MCSPI2_CONTEXT, RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT, - * RM_L4PER_MGATE_CONTEXT, RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT, - * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_MSPROHG_CONTEXT, - * RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT, - * RM_TESLA_TESLA_CONTEXT, RM_IVAHD_IVAHD_CONTEXT, RM_IVAHD_SL2_CONTEXT + * RM_ABE_WDT3_CONTEXT, RM_ALWON_MDMINTC_CONTEXT, RM_ALWON_SR_CORE_CONTEXT, + * RM_ALWON_SR_IVA_CONTEXT, RM_ALWON_SR_MPU_CONTEXT, RM_CAM_FDIF_CONTEXT, + * RM_CAM_ISS_CONTEXT, RM_CEFUSE_CEFUSE_CONTEXT, RM_D2D_SAD2D_CONTEXT, + * RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT, + * RM_DUCATI_DUCATI_CONTEXT, RM_EMU_DEBUGSS_CONTEXT, RM_GFX_GFX_CONTEXT, + * RM_IVAHD_IVAHD_CONTEXT, RM_IVAHD_SL2_CONTEXT, RM_L3INIT_CCPTX_CONTEXT, + * RM_L3INIT_EMAC_CONTEXT, RM_L3INIT_P1500_CONTEXT, RM_L3INIT_PCIESS_CONTEXT, + * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT, + * RM_L3INIT_USBPHYOCP2SCP_CONTEXT, RM_L3INIT_XHPI_CONTEXT, + * RM_L3INSTR_L3_3_CONTEXT, RM_L3INSTR_L3_INSTR_CONTEXT, + * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_L3_2_CONTEXT, + * RM_L3_2_OCMC_RAM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_SAR_ROM_CONTEXT, + * RM_L4PER_ADC_CONTEXT, RM_L4PER_DMTIMER10_CONTEXT, + * RM_L4PER_DMTIMER11_CONTEXT, RM_L4PER_DMTIMER2_CONTEXT, + * RM_L4PER_DMTIMER3_CONTEXT, RM_L4PER_DMTIMER4_CONTEXT, + * RM_L4PER_DMTIMER9_CONTEXT, RM_L4PER_ELM_CONTEXT, RM_L4PER_HDQ1W_CONTEXT, + * RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, RM_L4PER_I2C2_CONTEXT, + * RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT, RM_L4PER_I2C5_CONTEXT, + * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCASP2_CONTEXT, RM_L4PER_MCASP3_CONTEXT, + * RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MCSPI1_CONTEXT, RM_L4PER_MCSPI2_CONTEXT, + * RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT, RM_L4PER_MGATE_CONTEXT, + * RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT, RM_L4PER_MMCSD5_CONTEXT, + * RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, + * RM_L4SEC_PKAEIP29_CONTEXT, RM_MEMIF_DLL_CONTEXT, RM_MEMIF_DLL_H_CONTEXT, + * RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT, + * RM_MEMIF_EMIF_FW_CONTEXT, RM_MPU_MPU_CONTEXT, RM_TESLA_TESLA_CONTEXT, + * RM_WKUP_GPIO1_CONTEXT, RM_WKUP_KEYBOARD_CONTEXT, RM_WKUP_L4WKUP_CONTEXT, + * RM_WKUP_RTC_CONTEXT, RM_WKUP_SARRAM_CONTEXT, RM_WKUP_SYNCTIMER_CONTEXT, + * RM_WKUP_TIMER12_CONTEXT, RM_WKUP_TIMER1_CONTEXT, RM_WKUP_USIM_CONTEXT, + * RM_WKUP_WDT1_CONTEXT, RM_WKUP_WDT2_CONTEXT */ #define OMAP4430_LOSTCONTEXT_DFF_SHIFT 0 -#define OMAP4430_LOSTCONTEXT_DFF_MASK BITFIELD(0, 0) +#define OMAP4430_LOSTCONTEXT_DFF_MASK (1 << 0) /* * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_D2D_SAD2D_CONTEXT, - * RM_D2D_SAD2D_FW_CONTEXT, RM_DUCATI_DUCATI_CONTEXT, RM_L3INSTR_L3_3_CONTEXT, + * RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DSS_CONTEXT, RM_DUCATI_DUCATI_CONTEXT, + * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT, + * RM_L3INIT_MMC6_CONTEXT, RM_L3INIT_USB_HOST_CONTEXT, + * RM_L3INIT_USB_HOST_FS_CONTEXT, RM_L3INIT_USB_OTG_CONTEXT, + * RM_L3INIT_USB_TLL_CONTEXT, RM_L3INSTR_L3_3_CONTEXT, * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_GPMC_CONTEXT, * RM_L3_2_L3_2_CONTEXT, RM_L4CFG_HW_SEM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT, - * RM_L4CFG_MAILBOX_CONTEXT, RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, - * RM_MEMIF_EMIF_2_CONTEXT, RM_MEMIF_EMIF_FW_CONTEXT, RM_MEMIF_EMIF_H1_CONTEXT, - * RM_MEMIF_EMIF_H2_CONTEXT, RM_SDMA_SDMA_CONTEXT, RM_L3INIT_HSI_CONTEXT, - * RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT, RM_L3INIT_MMC6_CONTEXT, - * RM_L3INIT_USB_HOST_CONTEXT, RM_L3INIT_USB_HOST_FS_CONTEXT, - * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_USB_TLL_CONTEXT, RM_DSS_DSS_CONTEXT, - * RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT, RM_L4PER_GPIO4_CONTEXT, - * RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT, RM_L4PER_I2C1_CONTEXT, - * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT, RM_L4PER_UART2_CONTEXT, - * RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, RM_L4SEC_AES1_CONTEXT, - * RM_L4SEC_AES2_CONTEXT, RM_L4SEC_CRYPTODMA_CONTEXT, RM_L4SEC_DES3DES_CONTEXT, - * RM_L4SEC_RNG_CONTEXT, RM_L4SEC_SHA2MD51_CONTEXT, RM_TESLA_TESLA_CONTEXT + * RM_L4CFG_MAILBOX_CONTEXT, RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT, + * RM_L4PER_GPIO4_CONTEXT, RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT, + * RM_L4PER_I2C1_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT, + * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, + * RM_L4SEC_AES1_CONTEXT, RM_L4SEC_AES2_CONTEXT, RM_L4SEC_CRYPTODMA_CONTEXT, + * RM_L4SEC_DES3DES_CONTEXT, RM_L4SEC_RNG_CONTEXT, RM_L4SEC_SHA2MD51_CONTEXT, + * RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT, + * RM_MEMIF_EMIF_FW_CONTEXT, RM_MEMIF_EMIF_H1_CONTEXT, + * RM_MEMIF_EMIF_H2_CONTEXT, RM_SDMA_SDMA_CONTEXT, RM_TESLA_TESLA_CONTEXT */ #define OMAP4430_LOSTCONTEXT_RFF_SHIFT 1 -#define OMAP4430_LOSTCONTEXT_RFF_MASK BITFIELD(1, 1) +#define OMAP4430_LOSTCONTEXT_RFF_MASK (1 << 1) /* Used by RM_ABE_AESS_CONTEXT */ #define OMAP4430_LOSTMEM_AESSMEM_SHIFT 8 -#define OMAP4430_LOSTMEM_AESSMEM_MASK BITFIELD(8, 8) +#define OMAP4430_LOSTMEM_AESSMEM_MASK (1 << 8) /* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */ #define OMAP4430_LOSTMEM_CAM_MEM_SHIFT 8 -#define OMAP4430_LOSTMEM_CAM_MEM_MASK BITFIELD(8, 8) +#define OMAP4430_LOSTMEM_CAM_MEM_MASK (1 << 8) /* Used by RM_L3INSTR_OCP_WP1_CONTEXT */ #define OMAP4430_LOSTMEM_CORE_NRET_BANK_SHIFT 8 -#define OMAP4430_LOSTMEM_CORE_NRET_BANK_MASK BITFIELD(8, 8) +#define OMAP4430_LOSTMEM_CORE_NRET_BANK_MASK (1 << 8) /* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_MEMIF_DMM_CONTEXT */ #define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_SHIFT 9 -#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_MASK BITFIELD(9, 9) +#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_MASK (1 << 9) /* Used by RM_L3_2_OCMC_RAM_CONTEXT */ #define OMAP4430_LOSTMEM_CORE_OCMRAM_SHIFT 8 -#define OMAP4430_LOSTMEM_CORE_OCMRAM_MASK BITFIELD(8, 8) +#define OMAP4430_LOSTMEM_CORE_OCMRAM_MASK (1 << 8) /* * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_MEMIF_DMM_CONTEXT, * RM_SDMA_SDMA_CONTEXT */ #define OMAP4430_LOSTMEM_CORE_OTHER_BANK_SHIFT 8 -#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_MASK BITFIELD(8, 8) +#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_MASK (1 << 8) /* Used by RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT */ #define OMAP4430_LOSTMEM_DSS_MEM_SHIFT 8 -#define OMAP4430_LOSTMEM_DSS_MEM_MASK BITFIELD(8, 8) +#define OMAP4430_LOSTMEM_DSS_MEM_MASK (1 << 8) /* Used by RM_DUCATI_DUCATI_CONTEXT */ #define OMAP4430_LOSTMEM_DUCATI_L2RAM_SHIFT 9 -#define OMAP4430_LOSTMEM_DUCATI_L2RAM_MASK BITFIELD(9, 9) +#define OMAP4430_LOSTMEM_DUCATI_L2RAM_MASK (1 << 9) /* Used by RM_DUCATI_DUCATI_CONTEXT */ #define OMAP4430_LOSTMEM_DUCATI_UNICACHE_SHIFT 8 -#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_MASK BITFIELD(8, 8) +#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_MASK (1 << 8) /* Used by RM_EMU_DEBUGSS_CONTEXT */ #define OMAP4430_LOSTMEM_EMU_BANK_SHIFT 8 -#define OMAP4430_LOSTMEM_EMU_BANK_MASK BITFIELD(8, 8) +#define OMAP4430_LOSTMEM_EMU_BANK_MASK (1 << 8) /* Used by RM_GFX_GFX_CONTEXT */ #define OMAP4430_LOSTMEM_GFX_MEM_SHIFT 8 -#define OMAP4430_LOSTMEM_GFX_MEM_MASK BITFIELD(8, 8) +#define OMAP4430_LOSTMEM_GFX_MEM_MASK (1 << 8) /* Used by RM_IVAHD_IVAHD_CONTEXT */ #define OMAP4430_LOSTMEM_HWA_MEM_SHIFT 10 -#define OMAP4430_LOSTMEM_HWA_MEM_MASK BITFIELD(10, 10) +#define OMAP4430_LOSTMEM_HWA_MEM_MASK (1 << 10) /* * Used by RM_L3INIT_CCPTX_CONTEXT, RM_L3INIT_EMAC_CONTEXT, @@ -620,19 +644,19 @@ * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_XHPI_CONTEXT */ #define OMAP4430_LOSTMEM_L3INIT_BANK1_SHIFT 8 -#define OMAP4430_LOSTMEM_L3INIT_BANK1_MASK BITFIELD(8, 8) +#define OMAP4430_LOSTMEM_L3INIT_BANK1_MASK (1 << 8) /* Used by RM_MPU_MPU_CONTEXT */ #define OMAP4430_LOSTMEM_MPU_L1_SHIFT 8 -#define OMAP4430_LOSTMEM_MPU_L1_MASK BITFIELD(8, 8) +#define OMAP4430_LOSTMEM_MPU_L1_MASK (1 << 8) /* Used by RM_MPU_MPU_CONTEXT */ #define OMAP4430_LOSTMEM_MPU_L2_SHIFT 9 -#define OMAP4430_LOSTMEM_MPU_L2_MASK BITFIELD(9, 9) +#define OMAP4430_LOSTMEM_MPU_L2_MASK (1 << 9) /* Used by RM_MPU_MPU_CONTEXT */ #define OMAP4430_LOSTMEM_MPU_RAM_SHIFT 10 -#define OMAP4430_LOSTMEM_MPU_RAM_MASK BITFIELD(10, 10) +#define OMAP4430_LOSTMEM_MPU_RAM_MASK (1 << 10) /* * Used by RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, @@ -640,14 +664,14 @@ * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT */ #define OMAP4430_LOSTMEM_NONRETAINED_BANK_SHIFT 8 -#define OMAP4430_LOSTMEM_NONRETAINED_BANK_MASK BITFIELD(8, 8) +#define OMAP4430_LOSTMEM_NONRETAINED_BANK_MASK (1 << 8) /* * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, * RM_ABE_MCBSP3_CONTEXT, RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT */ #define OMAP4430_LOSTMEM_PERIHPMEM_SHIFT 8 -#define OMAP4430_LOSTMEM_PERIHPMEM_MASK BITFIELD(8, 8) +#define OMAP4430_LOSTMEM_PERIHPMEM_MASK (1 << 8) /* * Used by RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_UART1_CONTEXT, @@ -655,245 +679,237 @@ * RM_L4SEC_CRYPTODMA_CONTEXT */ #define OMAP4430_LOSTMEM_RETAINED_BANK_SHIFT 8 -#define OMAP4430_LOSTMEM_RETAINED_BANK_MASK BITFIELD(8, 8) +#define OMAP4430_LOSTMEM_RETAINED_BANK_MASK (1 << 8) /* Used by RM_IVAHD_SL2_CONTEXT */ #define OMAP4430_LOSTMEM_SL2_MEM_SHIFT 8 -#define OMAP4430_LOSTMEM_SL2_MEM_MASK BITFIELD(8, 8) +#define OMAP4430_LOSTMEM_SL2_MEM_MASK (1 << 8) /* Used by RM_IVAHD_IVAHD_CONTEXT */ #define OMAP4430_LOSTMEM_TCM1_MEM_SHIFT 8 -#define OMAP4430_LOSTMEM_TCM1_MEM_MASK BITFIELD(8, 8) +#define OMAP4430_LOSTMEM_TCM1_MEM_MASK (1 << 8) /* Used by RM_IVAHD_IVAHD_CONTEXT */ #define OMAP4430_LOSTMEM_TCM2_MEM_SHIFT 9 -#define OMAP4430_LOSTMEM_TCM2_MEM_MASK BITFIELD(9, 9) +#define OMAP4430_LOSTMEM_TCM2_MEM_MASK (1 << 9) /* Used by RM_TESLA_TESLA_CONTEXT */ #define OMAP4430_LOSTMEM_TESLA_EDMA_SHIFT 10 -#define OMAP4430_LOSTMEM_TESLA_EDMA_MASK BITFIELD(10, 10) +#define OMAP4430_LOSTMEM_TESLA_EDMA_MASK (1 << 10) /* Used by RM_TESLA_TESLA_CONTEXT */ #define OMAP4430_LOSTMEM_TESLA_L1_SHIFT 8 -#define OMAP4430_LOSTMEM_TESLA_L1_MASK BITFIELD(8, 8) +#define OMAP4430_LOSTMEM_TESLA_L1_MASK (1 << 8) /* Used by RM_TESLA_TESLA_CONTEXT */ #define OMAP4430_LOSTMEM_TESLA_L2_SHIFT 9 -#define OMAP4430_LOSTMEM_TESLA_L2_MASK BITFIELD(9, 9) +#define OMAP4430_LOSTMEM_TESLA_L2_MASK (1 << 9) /* Used by RM_WKUP_SARRAM_CONTEXT */ #define OMAP4430_LOSTMEM_WKUP_BANK_SHIFT 8 -#define OMAP4430_LOSTMEM_WKUP_BANK_MASK BITFIELD(8, 8) +#define OMAP4430_LOSTMEM_WKUP_BANK_MASK (1 << 8) /* - * Used by PM_CORE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, - * PM_ABE_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, - * PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_TESLA_PWRSTCTRL, PM_IVAHD_PWRSTCTRL + * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, + * PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_IVAHD_PWRSTCTRL, + * PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL */ #define OMAP4430_LOWPOWERSTATECHANGE_SHIFT 4 -#define OMAP4430_LOWPOWERSTATECHANGE_MASK BITFIELD(4, 4) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP4430_MEMORYCHANGE_SHIFT 3 -#define OMAP4430_MEMORYCHANGE_MASK BITFIELD(3, 3) +#define OMAP4430_LOWPOWERSTATECHANGE_MASK (1 << 4) /* Used by PRM_MODEM_IF_CTRL */ #define OMAP4430_MODEM_READY_SHIFT 1 -#define OMAP4430_MODEM_READY_MASK BITFIELD(1, 1) +#define OMAP4430_MODEM_READY_MASK (1 << 1) /* Used by PRM_MODEM_IF_CTRL */ #define OMAP4430_MODEM_SHUTDOWN_IRQ_SHIFT 9 -#define OMAP4430_MODEM_SHUTDOWN_IRQ_MASK BITFIELD(9, 9) +#define OMAP4430_MODEM_SHUTDOWN_IRQ_MASK (1 << 9) /* Used by PRM_MODEM_IF_CTRL */ #define OMAP4430_MODEM_SLEEP_ST_SHIFT 16 -#define OMAP4430_MODEM_SLEEP_ST_MASK BITFIELD(16, 16) +#define OMAP4430_MODEM_SLEEP_ST_MASK (1 << 16) /* Used by PRM_MODEM_IF_CTRL */ #define OMAP4430_MODEM_WAKE_IRQ_SHIFT 8 -#define OMAP4430_MODEM_WAKE_IRQ_MASK BITFIELD(8, 8) +#define OMAP4430_MODEM_WAKE_IRQ_MASK (1 << 8) /* Used by PM_MPU_PWRSTCTRL */ #define OMAP4430_MPU_L1_ONSTATE_SHIFT 16 -#define OMAP4430_MPU_L1_ONSTATE_MASK BITFIELD(16, 17) +#define OMAP4430_MPU_L1_ONSTATE_MASK (0x3 << 16) /* Used by PM_MPU_PWRSTCTRL */ #define OMAP4430_MPU_L1_RETSTATE_SHIFT 8 -#define OMAP4430_MPU_L1_RETSTATE_MASK BITFIELD(8, 8) +#define OMAP4430_MPU_L1_RETSTATE_MASK (1 << 8) /* Used by PM_MPU_PWRSTST */ #define OMAP4430_MPU_L1_STATEST_SHIFT 4 -#define OMAP4430_MPU_L1_STATEST_MASK BITFIELD(4, 5) +#define OMAP4430_MPU_L1_STATEST_MASK (0x3 << 4) /* Used by PM_MPU_PWRSTCTRL */ #define OMAP4430_MPU_L2_ONSTATE_SHIFT 18 -#define OMAP4430_MPU_L2_ONSTATE_MASK BITFIELD(18, 19) +#define OMAP4430_MPU_L2_ONSTATE_MASK (0x3 << 18) /* Used by PM_MPU_PWRSTCTRL */ #define OMAP4430_MPU_L2_RETSTATE_SHIFT 9 -#define OMAP4430_MPU_L2_RETSTATE_MASK BITFIELD(9, 9) +#define OMAP4430_MPU_L2_RETSTATE_MASK (1 << 9) /* Used by PM_MPU_PWRSTST */ #define OMAP4430_MPU_L2_STATEST_SHIFT 6 -#define OMAP4430_MPU_L2_STATEST_MASK BITFIELD(6, 7) +#define OMAP4430_MPU_L2_STATEST_MASK (0x3 << 6) /* Used by PM_MPU_PWRSTCTRL */ #define OMAP4430_MPU_RAM_ONSTATE_SHIFT 20 -#define OMAP4430_MPU_RAM_ONSTATE_MASK BITFIELD(20, 21) +#define OMAP4430_MPU_RAM_ONSTATE_MASK (0x3 << 20) /* Used by PM_MPU_PWRSTCTRL */ #define OMAP4430_MPU_RAM_RETSTATE_SHIFT 10 -#define OMAP4430_MPU_RAM_RETSTATE_MASK BITFIELD(10, 10) +#define OMAP4430_MPU_RAM_RETSTATE_MASK (1 << 10) /* Used by PM_MPU_PWRSTST */ #define OMAP4430_MPU_RAM_STATEST_SHIFT 8 -#define OMAP4430_MPU_RAM_STATEST_MASK BITFIELD(8, 9) +#define OMAP4430_MPU_RAM_STATEST_MASK (0x3 << 8) /* Used by PRM_RSTST */ #define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT 2 -#define OMAP4430_MPU_SECURITY_VIOL_RST_MASK BITFIELD(2, 2) +#define OMAP4430_MPU_SECURITY_VIOL_RST_MASK (1 << 2) /* Used by PRM_RSTST */ #define OMAP4430_MPU_WDT_RST_SHIFT 3 -#define OMAP4430_MPU_WDT_RST_MASK BITFIELD(3, 3) +#define OMAP4430_MPU_WDT_RST_MASK (1 << 3) /* Used by PM_L4PER_PWRSTCTRL */ #define OMAP4430_NONRETAINED_BANK_ONSTATE_SHIFT 18 -#define OMAP4430_NONRETAINED_BANK_ONSTATE_MASK BITFIELD(18, 19) +#define OMAP4430_NONRETAINED_BANK_ONSTATE_MASK (0x3 << 18) /* Used by PM_L4PER_PWRSTCTRL */ #define OMAP4430_NONRETAINED_BANK_RETSTATE_SHIFT 9 -#define OMAP4430_NONRETAINED_BANK_RETSTATE_MASK BITFIELD(9, 9) +#define OMAP4430_NONRETAINED_BANK_RETSTATE_MASK (1 << 9) /* Used by PM_L4PER_PWRSTST */ #define OMAP4430_NONRETAINED_BANK_STATEST_SHIFT 6 -#define OMAP4430_NONRETAINED_BANK_STATEST_MASK BITFIELD(6, 7) +#define OMAP4430_NONRETAINED_BANK_STATEST_MASK (0x3 << 6) /* Used by PM_CORE_PWRSTCTRL */ #define OMAP4430_OCP_NRET_BANK_ONSTATE_SHIFT 24 -#define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK BITFIELD(24, 25) +#define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK (0x3 << 24) /* Used by PM_CORE_PWRSTCTRL */ #define OMAP4430_OCP_NRET_BANK_RETSTATE_SHIFT 12 -#define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK BITFIELD(12, 12) +#define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK (1 << 12) /* Used by PM_CORE_PWRSTST */ #define OMAP4430_OCP_NRET_BANK_STATEST_SHIFT 12 -#define OMAP4430_OCP_NRET_BANK_STATEST_MASK BITFIELD(12, 13) +#define OMAP4430_OCP_NRET_BANK_STATEST_MASK (0x3 << 12) /* * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, * PRM_VC_VAL_CMD_VDD_MPU_L */ #define OMAP4430_OFF_SHIFT 0 -#define OMAP4430_OFF_MASK BITFIELD(0, 7) - -/* Used by PRM_LDO_BANDGAP_CTRL */ -#define OMAP4430_OFF_ENABLE_SHIFT 0 -#define OMAP4430_OFF_ENABLE_MASK BITFIELD(0, 0) +#define OMAP4430_OFF_MASK (0xff << 0) /* * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, * PRM_VC_VAL_CMD_VDD_MPU_L */ #define OMAP4430_ON_SHIFT 24 -#define OMAP4430_ON_MASK BITFIELD(24, 31) +#define OMAP4430_ON_MASK (0xff << 24) /* * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, * PRM_VC_VAL_CMD_VDD_MPU_L */ #define OMAP4430_ONLP_SHIFT 16 -#define OMAP4430_ONLP_MASK BITFIELD(16, 23) +#define OMAP4430_ONLP_MASK (0xff << 16) /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ #define OMAP4430_OPP_CHANGE_SHIFT 2 -#define OMAP4430_OPP_CHANGE_MASK BITFIELD(2, 2) +#define OMAP4430_OPP_CHANGE_MASK (1 << 2) /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ #define OMAP4430_OPP_SEL_SHIFT 0 -#define OMAP4430_OPP_SEL_MASK BITFIELD(0, 1) +#define OMAP4430_OPP_SEL_MASK (0x3 << 0) /* Used by PRM_SRAM_COUNT */ #define OMAP4430_PCHARGECNT_VALUE_SHIFT 0 -#define OMAP4430_PCHARGECNT_VALUE_MASK BITFIELD(0, 5) +#define OMAP4430_PCHARGECNT_VALUE_MASK (0x3f << 0) /* Used by PRM_PSCON_COUNT */ #define OMAP4430_PCHARGE_TIME_SHIFT 0 -#define OMAP4430_PCHARGE_TIME_MASK BITFIELD(0, 7) +#define OMAP4430_PCHARGE_TIME_MASK (0xff << 0) /* Used by PM_ABE_PWRSTCTRL */ #define OMAP4430_PERIPHMEM_ONSTATE_SHIFT 20 -#define OMAP4430_PERIPHMEM_ONSTATE_MASK BITFIELD(20, 21) +#define OMAP4430_PERIPHMEM_ONSTATE_MASK (0x3 << 20) /* Used by PM_ABE_PWRSTCTRL */ #define OMAP4430_PERIPHMEM_RETSTATE_SHIFT 10 -#define OMAP4430_PERIPHMEM_RETSTATE_MASK BITFIELD(10, 10) +#define OMAP4430_PERIPHMEM_RETSTATE_MASK (1 << 10) /* Used by PM_ABE_PWRSTST */ #define OMAP4430_PERIPHMEM_STATEST_SHIFT 8 -#define OMAP4430_PERIPHMEM_STATEST_MASK BITFIELD(8, 9) +#define OMAP4430_PERIPHMEM_STATEST_MASK (0x3 << 8) /* Used by PRM_PHASE1_CNDP */ #define OMAP4430_PHASE1_CNDP_SHIFT 0 -#define OMAP4430_PHASE1_CNDP_MASK BITFIELD(0, 31) +#define OMAP4430_PHASE1_CNDP_MASK (0xffffffff << 0) /* Used by PRM_PHASE2A_CNDP */ #define OMAP4430_PHASE2A_CNDP_SHIFT 0 -#define OMAP4430_PHASE2A_CNDP_MASK BITFIELD(0, 31) +#define OMAP4430_PHASE2A_CNDP_MASK (0xffffffff << 0) /* Used by PRM_PHASE2B_CNDP */ #define OMAP4430_PHASE2B_CNDP_SHIFT 0 -#define OMAP4430_PHASE2B_CNDP_MASK BITFIELD(0, 31) +#define OMAP4430_PHASE2B_CNDP_MASK (0xffffffff << 0) /* Used by PRM_PSCON_COUNT */ #define OMAP4430_PONOUT_2_PGOODIN_TIME_SHIFT 8 -#define OMAP4430_PONOUT_2_PGOODIN_TIME_MASK BITFIELD(8, 15) +#define OMAP4430_PONOUT_2_PGOODIN_TIME_MASK (0xff << 8) /* - * Used by PM_EMU_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_CAM_PWRSTCTRL, - * PM_L3INIT_PWRSTCTRL, PM_ABE_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, - * PM_CEFUSE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, - * PM_TESLA_PWRSTCTRL, PM_IVAHD_PWRSTCTRL + * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, + * PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_EMU_PWRSTCTRL, PM_GFX_PWRSTCTRL, + * PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, + * PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL */ #define OMAP4430_POWERSTATE_SHIFT 0 -#define OMAP4430_POWERSTATE_MASK BITFIELD(0, 1) +#define OMAP4430_POWERSTATE_MASK (0x3 << 0) /* - * Used by PM_EMU_PWRSTST, PM_CORE_PWRSTST, PM_CAM_PWRSTST, PM_L3INIT_PWRSTST, - * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST, - * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST + * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST, + * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST, + * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST */ #define OMAP4430_POWERSTATEST_SHIFT 0 -#define OMAP4430_POWERSTATEST_MASK BITFIELD(0, 1) +#define OMAP4430_POWERSTATEST_MASK (0x3 << 0) /* Used by PRM_PWRREQCTRL */ #define OMAP4430_PWRREQ_COND_SHIFT 0 -#define OMAP4430_PWRREQ_COND_MASK BITFIELD(0, 1) +#define OMAP4430_PWRREQ_COND_MASK (0x3 << 0) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_RACEN_VDD_CORE_L_SHIFT 3 -#define OMAP4430_RACEN_VDD_CORE_L_MASK BITFIELD(3, 3) +#define OMAP4430_RACEN_VDD_CORE_L_MASK (1 << 3) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_RACEN_VDD_IVA_L_SHIFT 11 -#define OMAP4430_RACEN_VDD_IVA_L_MASK BITFIELD(11, 11) +#define OMAP4430_RACEN_VDD_IVA_L_MASK (1 << 11) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_RACEN_VDD_MPU_L_SHIFT 20 -#define OMAP4430_RACEN_VDD_MPU_L_MASK BITFIELD(20, 20) +#define OMAP4430_RACEN_VDD_MPU_L_MASK (1 << 20) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_RAC_VDD_CORE_L_SHIFT 2 -#define OMAP4430_RAC_VDD_CORE_L_MASK BITFIELD(2, 2) +#define OMAP4430_RAC_VDD_CORE_L_MASK (1 << 2) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_RAC_VDD_IVA_L_SHIFT 10 -#define OMAP4430_RAC_VDD_IVA_L_MASK BITFIELD(10, 10) +#define OMAP4430_RAC_VDD_IVA_L_MASK (1 << 10) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_RAC_VDD_MPU_L_SHIFT 19 -#define OMAP4430_RAC_VDD_MPU_L_MASK BITFIELD(19, 19) +#define OMAP4430_RAC_VDD_MPU_L_MASK (1 << 19) /* * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, @@ -901,7 +917,7 @@ * PRM_VOLTSETUP_MPU_RET_SLEEP */ #define OMAP4430_RAMP_DOWN_COUNT_SHIFT 16 -#define OMAP4430_RAMP_DOWN_COUNT_MASK BITFIELD(16, 21) +#define OMAP4430_RAMP_DOWN_COUNT_MASK (0x3f << 16) /* * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, @@ -909,7 +925,7 @@ * PRM_VOLTSETUP_MPU_RET_SLEEP */ #define OMAP4430_RAMP_DOWN_PRESCAL_SHIFT 24 -#define OMAP4430_RAMP_DOWN_PRESCAL_MASK BITFIELD(24, 25) +#define OMAP4430_RAMP_DOWN_PRESCAL_MASK (0x3 << 24) /* * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, @@ -917,7 +933,7 @@ * PRM_VOLTSETUP_MPU_RET_SLEEP */ #define OMAP4430_RAMP_UP_COUNT_SHIFT 0 -#define OMAP4430_RAMP_UP_COUNT_MASK BITFIELD(0, 5) +#define OMAP4430_RAMP_UP_COUNT_MASK (0x3f << 0) /* * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, @@ -925,1281 +941,1381 @@ * PRM_VOLTSETUP_MPU_RET_SLEEP */ #define OMAP4430_RAMP_UP_PRESCAL_SHIFT 8 -#define OMAP4430_RAMP_UP_PRESCAL_MASK BITFIELD(8, 9) +#define OMAP4430_RAMP_UP_PRESCAL_MASK (0x3 << 8) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_RAV_VDD_CORE_L_SHIFT 1 -#define OMAP4430_RAV_VDD_CORE_L_MASK BITFIELD(1, 1) +#define OMAP4430_RAV_VDD_CORE_L_MASK (1 << 1) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_RAV_VDD_IVA_L_SHIFT 9 -#define OMAP4430_RAV_VDD_IVA_L_MASK BITFIELD(9, 9) +#define OMAP4430_RAV_VDD_IVA_L_MASK (1 << 9) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_RAV_VDD_MPU_L_SHIFT 18 -#define OMAP4430_RAV_VDD_MPU_L_MASK BITFIELD(18, 18) +#define OMAP4430_RAV_VDD_MPU_L_MASK (1 << 18) /* Used by PRM_VC_VAL_BYPASS */ #define OMAP4430_REGADDR_SHIFT 8 -#define OMAP4430_REGADDR_MASK BITFIELD(8, 15) +#define OMAP4430_REGADDR_MASK (0xff << 8) /* * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, * PRM_VC_VAL_CMD_VDD_MPU_L */ #define OMAP4430_RET_SHIFT 8 -#define OMAP4430_RET_MASK BITFIELD(8, 15) +#define OMAP4430_RET_MASK (0xff << 8) /* Used by PM_L4PER_PWRSTCTRL */ #define OMAP4430_RETAINED_BANK_ONSTATE_SHIFT 16 -#define OMAP4430_RETAINED_BANK_ONSTATE_MASK BITFIELD(16, 17) +#define OMAP4430_RETAINED_BANK_ONSTATE_MASK (0x3 << 16) /* Used by PM_L4PER_PWRSTCTRL */ #define OMAP4430_RETAINED_BANK_RETSTATE_SHIFT 8 -#define OMAP4430_RETAINED_BANK_RETSTATE_MASK BITFIELD(8, 8) +#define OMAP4430_RETAINED_BANK_RETSTATE_MASK (1 << 8) /* Used by PM_L4PER_PWRSTST */ #define OMAP4430_RETAINED_BANK_STATEST_SHIFT 4 -#define OMAP4430_RETAINED_BANK_STATEST_MASK BITFIELD(4, 5) +#define OMAP4430_RETAINED_BANK_STATEST_MASK (0x3 << 4) /* * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, * PRM_LDO_SRAM_MPU_CTRL */ #define OMAP4430_RETMODE_ENABLE_SHIFT 0 -#define OMAP4430_RETMODE_ENABLE_MASK BITFIELD(0, 0) +#define OMAP4430_RETMODE_ENABLE_MASK (1 << 0) -/* Used by REVISION_PRM */ -#define OMAP4430_REV_SHIFT 0 -#define OMAP4430_REV_MASK BITFIELD(0, 7) - -/* Used by RM_DUCATI_RSTCTRL, RM_TESLA_RSTCTRL, RM_IVAHD_RSTCTRL */ +/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */ #define OMAP4430_RST1_SHIFT 0 -#define OMAP4430_RST1_MASK BITFIELD(0, 0) +#define OMAP4430_RST1_MASK (1 << 0) -/* Used by RM_DUCATI_RSTST, RM_TESLA_RSTST, RM_IVAHD_RSTST */ +/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */ #define OMAP4430_RST1ST_SHIFT 0 -#define OMAP4430_RST1ST_MASK BITFIELD(0, 0) +#define OMAP4430_RST1ST_MASK (1 << 0) -/* Used by RM_DUCATI_RSTCTRL, RM_TESLA_RSTCTRL, RM_IVAHD_RSTCTRL */ +/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */ #define OMAP4430_RST2_SHIFT 1 -#define OMAP4430_RST2_MASK BITFIELD(1, 1) +#define OMAP4430_RST2_MASK (1 << 1) -/* Used by RM_DUCATI_RSTST, RM_TESLA_RSTST, RM_IVAHD_RSTST */ +/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */ #define OMAP4430_RST2ST_SHIFT 1 -#define OMAP4430_RST2ST_MASK BITFIELD(1, 1) +#define OMAP4430_RST2ST_MASK (1 << 1) /* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL */ #define OMAP4430_RST3_SHIFT 2 -#define OMAP4430_RST3_MASK BITFIELD(2, 2) +#define OMAP4430_RST3_MASK (1 << 2) /* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST */ #define OMAP4430_RST3ST_SHIFT 2 -#define OMAP4430_RST3ST_MASK BITFIELD(2, 2) +#define OMAP4430_RST3ST_MASK (1 << 2) /* Used by PRM_RSTTIME */ #define OMAP4430_RSTTIME1_SHIFT 0 -#define OMAP4430_RSTTIME1_MASK BITFIELD(0, 9) +#define OMAP4430_RSTTIME1_MASK (0x3ff << 0) /* Used by PRM_RSTTIME */ #define OMAP4430_RSTTIME2_SHIFT 10 -#define OMAP4430_RSTTIME2_MASK BITFIELD(10, 14) +#define OMAP4430_RSTTIME2_MASK (0x1f << 10) /* Used by PRM_RSTCTRL */ #define OMAP4430_RST_GLOBAL_COLD_SW_SHIFT 1 -#define OMAP4430_RST_GLOBAL_COLD_SW_MASK BITFIELD(1, 1) +#define OMAP4430_RST_GLOBAL_COLD_SW_MASK (1 << 1) /* Used by PRM_RSTCTRL */ #define OMAP4430_RST_GLOBAL_WARM_SW_SHIFT 0 -#define OMAP4430_RST_GLOBAL_WARM_SW_MASK BITFIELD(0, 0) +#define OMAP4430_RST_GLOBAL_WARM_SW_MASK (1 << 0) + +/* Used by REVISION_PRM */ +#define OMAP4430_R_RTL_SHIFT 11 +#define OMAP4430_R_RTL_MASK (0x1f << 11) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_SA_VDD_CORE_L_SHIFT 0 -#define OMAP4430_SA_VDD_CORE_L_MASK BITFIELD(0, 0) +#define OMAP4430_SA_VDD_CORE_L_MASK (1 << 0) /* Renamed from SA_VDD_CORE_L Used by PRM_VC_SMPS_SA */ #define OMAP4430_SA_VDD_CORE_L_0_6_SHIFT 0 -#define OMAP4430_SA_VDD_CORE_L_0_6_MASK BITFIELD(0, 6) +#define OMAP4430_SA_VDD_CORE_L_0_6_MASK (0x7f << 0) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_SA_VDD_IVA_L_SHIFT 8 -#define OMAP4430_SA_VDD_IVA_L_MASK BITFIELD(8, 8) +#define OMAP4430_SA_VDD_IVA_L_MASK (1 << 8) /* Renamed from SA_VDD_IVA_L Used by PRM_VC_SMPS_SA */ #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT 8 -#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK BITFIELD(8, 14) +#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK (0x7f << 8) /* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_SA_VDD_MPU_L_SHIFT 16 -#define OMAP4430_SA_VDD_MPU_L_MASK BITFIELD(16, 16) +#define OMAP4430_SA_VDD_MPU_L_MASK (1 << 16) /* Renamed from SA_VDD_MPU_L Used by PRM_VC_SMPS_SA */ #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT 16 -#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK BITFIELD(16, 22) +#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK (0x7f << 16) + +/* Used by REVISION_PRM */ +#define OMAP4430_SCHEME_SHIFT 30 +#define OMAP4430_SCHEME_MASK (0x3 << 30) /* Used by PRM_VC_CFG_I2C_CLK */ #define OMAP4430_SCLH_SHIFT 0 -#define OMAP4430_SCLH_MASK BITFIELD(0, 7) +#define OMAP4430_SCLH_MASK (0xff << 0) /* Used by PRM_VC_CFG_I2C_CLK */ #define OMAP4430_SCLL_SHIFT 8 -#define OMAP4430_SCLL_MASK BITFIELD(8, 15) +#define OMAP4430_SCLL_MASK (0xff << 8) /* Used by PRM_RSTST */ #define OMAP4430_SECURE_WDT_RST_SHIFT 4 -#define OMAP4430_SECURE_WDT_RST_MASK BITFIELD(4, 4) +#define OMAP4430_SECURE_WDT_RST_MASK (1 << 4) /* Used by PM_IVAHD_PWRSTCTRL */ #define OMAP4430_SL2_MEM_ONSTATE_SHIFT 18 -#define OMAP4430_SL2_MEM_ONSTATE_MASK BITFIELD(18, 19) +#define OMAP4430_SL2_MEM_ONSTATE_MASK (0x3 << 18) /* Used by PM_IVAHD_PWRSTCTRL */ #define OMAP4430_SL2_MEM_RETSTATE_SHIFT 9 -#define OMAP4430_SL2_MEM_RETSTATE_MASK BITFIELD(9, 9) +#define OMAP4430_SL2_MEM_RETSTATE_MASK (1 << 9) /* Used by PM_IVAHD_PWRSTST */ #define OMAP4430_SL2_MEM_STATEST_SHIFT 6 -#define OMAP4430_SL2_MEM_STATEST_MASK BITFIELD(6, 7) +#define OMAP4430_SL2_MEM_STATEST_MASK (0x3 << 6) /* Used by PRM_VC_VAL_BYPASS */ #define OMAP4430_SLAVEADDR_SHIFT 0 -#define OMAP4430_SLAVEADDR_MASK BITFIELD(0, 6) +#define OMAP4430_SLAVEADDR_MASK (0x7f << 0) /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ #define OMAP4430_SLEEP_RBB_SEL_SHIFT 3 -#define OMAP4430_SLEEP_RBB_SEL_MASK BITFIELD(3, 3) +#define OMAP4430_SLEEP_RBB_SEL_MASK (1 << 3) /* Used by PRM_SRAM_COUNT */ #define OMAP4430_SLPCNT_VALUE_SHIFT 16 -#define OMAP4430_SLPCNT_VALUE_MASK BITFIELD(16, 23) +#define OMAP4430_SLPCNT_VALUE_MASK (0xff << 16) /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ #define OMAP4430_SMPSWAITTIMEMAX_SHIFT 8 -#define OMAP4430_SMPSWAITTIMEMAX_MASK BITFIELD(8, 23) +#define OMAP4430_SMPSWAITTIMEMAX_MASK (0xffff << 8) /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ #define OMAP4430_SMPSWAITTIMEMIN_SHIFT 8 -#define OMAP4430_SMPSWAITTIMEMIN_MASK BITFIELD(8, 23) +#define OMAP4430_SMPSWAITTIMEMIN_MASK (0xffff << 8) + +/* Used by PRM_VC_ERRST */ +#define OMAP4430_SMPS_RA_ERR_CORE_SHIFT 1 +#define OMAP4430_SMPS_RA_ERR_CORE_MASK (1 << 1) + +/* Used by PRM_VC_ERRST */ +#define OMAP4430_SMPS_RA_ERR_IVA_SHIFT 9 +#define OMAP4430_SMPS_RA_ERR_IVA_MASK (1 << 9) + +/* Used by PRM_VC_ERRST */ +#define OMAP4430_SMPS_RA_ERR_MPU_SHIFT 17 +#define OMAP4430_SMPS_RA_ERR_MPU_MASK (1 << 17) + +/* Used by PRM_VC_ERRST */ +#define OMAP4430_SMPS_SA_ERR_CORE_SHIFT 0 +#define OMAP4430_SMPS_SA_ERR_CORE_MASK (1 << 0) + +/* Used by PRM_VC_ERRST */ +#define OMAP4430_SMPS_SA_ERR_IVA_SHIFT 8 +#define OMAP4430_SMPS_SA_ERR_IVA_MASK (1 << 8) + +/* Used by PRM_VC_ERRST */ +#define OMAP4430_SMPS_SA_ERR_MPU_SHIFT 16 +#define OMAP4430_SMPS_SA_ERR_MPU_MASK (1 << 16) + +/* Used by PRM_VC_ERRST */ +#define OMAP4430_SMPS_TIMEOUT_ERR_CORE_SHIFT 2 +#define OMAP4430_SMPS_TIMEOUT_ERR_CORE_MASK (1 << 2) + +/* Used by PRM_VC_ERRST */ +#define OMAP4430_SMPS_TIMEOUT_ERR_IVA_SHIFT 10 +#define OMAP4430_SMPS_TIMEOUT_ERR_IVA_MASK (1 << 10) + +/* Used by PRM_VC_ERRST */ +#define OMAP4430_SMPS_TIMEOUT_ERR_MPU_SHIFT 18 +#define OMAP4430_SMPS_TIMEOUT_ERR_MPU_MASK (1 << 18) /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ #define OMAP4430_SR2EN_SHIFT 0 -#define OMAP4430_SR2EN_MASK BITFIELD(0, 0) +#define OMAP4430_SR2EN_MASK (1 << 0) /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ #define OMAP4430_SR2_IN_TRANSITION_SHIFT 6 -#define OMAP4430_SR2_IN_TRANSITION_MASK BITFIELD(6, 6) +#define OMAP4430_SR2_IN_TRANSITION_MASK (1 << 6) /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ #define OMAP4430_SR2_STATUS_SHIFT 3 -#define OMAP4430_SR2_STATUS_MASK BITFIELD(3, 4) +#define OMAP4430_SR2_STATUS_MASK (0x3 << 3) /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ #define OMAP4430_SR2_WTCNT_VALUE_SHIFT 8 -#define OMAP4430_SR2_WTCNT_VALUE_MASK BITFIELD(8, 15) +#define OMAP4430_SR2_WTCNT_VALUE_MASK (0xff << 8) /* * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, * PRM_LDO_SRAM_MPU_CTRL */ #define OMAP4430_SRAMLDO_STATUS_SHIFT 8 -#define OMAP4430_SRAMLDO_STATUS_MASK BITFIELD(8, 8) +#define OMAP4430_SRAMLDO_STATUS_MASK (1 << 8) /* * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, * PRM_LDO_SRAM_MPU_CTRL */ #define OMAP4430_SRAM_IN_TRANSITION_SHIFT 9 -#define OMAP4430_SRAM_IN_TRANSITION_MASK BITFIELD(9, 9) +#define OMAP4430_SRAM_IN_TRANSITION_MASK (1 << 9) /* Used by PRM_VC_CFG_I2C_MODE */ #define OMAP4430_SRMODEEN_SHIFT 4 -#define OMAP4430_SRMODEEN_MASK BITFIELD(4, 4) +#define OMAP4430_SRMODEEN_MASK (1 << 4) /* Used by PRM_VOLTSETUP_WARMRESET */ #define OMAP4430_STABLE_COUNT_SHIFT 0 -#define OMAP4430_STABLE_COUNT_MASK BITFIELD(0, 5) +#define OMAP4430_STABLE_COUNT_MASK (0x3f << 0) /* Used by PRM_VOLTSETUP_WARMRESET */ #define OMAP4430_STABLE_PRESCAL_SHIFT 8 -#define OMAP4430_STABLE_PRESCAL_MASK BITFIELD(8, 9) +#define OMAP4430_STABLE_PRESCAL_MASK (0x3 << 8) + +/* Used by PRM_LDO_BANDGAP_SETUP */ +#define OMAP4430_STARTUP_COUNT_SHIFT 0 +#define OMAP4430_STARTUP_COUNT_MASK (0xff << 0) + +/* Renamed from STARTUP_COUNT Used by PRM_SRAM_COUNT */ +#define OMAP4430_STARTUP_COUNT_24_31_SHIFT 24 +#define OMAP4430_STARTUP_COUNT_24_31_MASK (0xff << 24) /* Used by PM_IVAHD_PWRSTCTRL */ #define OMAP4430_TCM1_MEM_ONSTATE_SHIFT 20 -#define OMAP4430_TCM1_MEM_ONSTATE_MASK BITFIELD(20, 21) +#define OMAP4430_TCM1_MEM_ONSTATE_MASK (0x3 << 20) /* Used by PM_IVAHD_PWRSTCTRL */ #define OMAP4430_TCM1_MEM_RETSTATE_SHIFT 10 -#define OMAP4430_TCM1_MEM_RETSTATE_MASK BITFIELD(10, 10) +#define OMAP4430_TCM1_MEM_RETSTATE_MASK (1 << 10) /* Used by PM_IVAHD_PWRSTST */ #define OMAP4430_TCM1_MEM_STATEST_SHIFT 8 -#define OMAP4430_TCM1_MEM_STATEST_MASK BITFIELD(8, 9) +#define OMAP4430_TCM1_MEM_STATEST_MASK (0x3 << 8) /* Used by PM_IVAHD_PWRSTCTRL */ #define OMAP4430_TCM2_MEM_ONSTATE_SHIFT 22 -#define OMAP4430_TCM2_MEM_ONSTATE_MASK BITFIELD(22, 23) +#define OMAP4430_TCM2_MEM_ONSTATE_MASK (0x3 << 22) /* Used by PM_IVAHD_PWRSTCTRL */ #define OMAP4430_TCM2_MEM_RETSTATE_SHIFT 11 -#define OMAP4430_TCM2_MEM_RETSTATE_MASK BITFIELD(11, 11) +#define OMAP4430_TCM2_MEM_RETSTATE_MASK (1 << 11) /* Used by PM_IVAHD_PWRSTST */ #define OMAP4430_TCM2_MEM_STATEST_SHIFT 10 -#define OMAP4430_TCM2_MEM_STATEST_MASK BITFIELD(10, 11) +#define OMAP4430_TCM2_MEM_STATEST_MASK (0x3 << 10) /* Used by RM_TESLA_RSTST */ #define OMAP4430_TESLASS_EMU_RSTST_SHIFT 2 -#define OMAP4430_TESLASS_EMU_RSTST_MASK BITFIELD(2, 2) +#define OMAP4430_TESLASS_EMU_RSTST_MASK (1 << 2) /* Used by RM_TESLA_RSTST */ #define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_SHIFT 3 -#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_MASK BITFIELD(3, 3) +#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_MASK (1 << 3) /* Used by PM_TESLA_PWRSTCTRL */ #define OMAP4430_TESLA_EDMA_ONSTATE_SHIFT 20 -#define OMAP4430_TESLA_EDMA_ONSTATE_MASK BITFIELD(20, 21) +#define OMAP4430_TESLA_EDMA_ONSTATE_MASK (0x3 << 20) /* Used by PM_TESLA_PWRSTCTRL */ #define OMAP4430_TESLA_EDMA_RETSTATE_SHIFT 10 -#define OMAP4430_TESLA_EDMA_RETSTATE_MASK BITFIELD(10, 10) +#define OMAP4430_TESLA_EDMA_RETSTATE_MASK (1 << 10) /* Used by PM_TESLA_PWRSTST */ #define OMAP4430_TESLA_EDMA_STATEST_SHIFT 8 -#define OMAP4430_TESLA_EDMA_STATEST_MASK BITFIELD(8, 9) +#define OMAP4430_TESLA_EDMA_STATEST_MASK (0x3 << 8) /* Used by PM_TESLA_PWRSTCTRL */ #define OMAP4430_TESLA_L1_ONSTATE_SHIFT 16 -#define OMAP4430_TESLA_L1_ONSTATE_MASK BITFIELD(16, 17) +#define OMAP4430_TESLA_L1_ONSTATE_MASK (0x3 << 16) /* Used by PM_TESLA_PWRSTCTRL */ #define OMAP4430_TESLA_L1_RETSTATE_SHIFT 8 -#define OMAP4430_TESLA_L1_RETSTATE_MASK BITFIELD(8, 8) +#define OMAP4430_TESLA_L1_RETSTATE_MASK (1 << 8) /* Used by PM_TESLA_PWRSTST */ #define OMAP4430_TESLA_L1_STATEST_SHIFT 4 -#define OMAP4430_TESLA_L1_STATEST_MASK BITFIELD(4, 5) +#define OMAP4430_TESLA_L1_STATEST_MASK (0x3 << 4) /* Used by PM_TESLA_PWRSTCTRL */ #define OMAP4430_TESLA_L2_ONSTATE_SHIFT 18 -#define OMAP4430_TESLA_L2_ONSTATE_MASK BITFIELD(18, 19) +#define OMAP4430_TESLA_L2_ONSTATE_MASK (0x3 << 18) /* Used by PM_TESLA_PWRSTCTRL */ #define OMAP4430_TESLA_L2_RETSTATE_SHIFT 9 -#define OMAP4430_TESLA_L2_RETSTATE_MASK BITFIELD(9, 9) +#define OMAP4430_TESLA_L2_RETSTATE_MASK (1 << 9) /* Used by PM_TESLA_PWRSTST */ #define OMAP4430_TESLA_L2_STATEST_SHIFT 6 -#define OMAP4430_TESLA_L2_STATEST_MASK BITFIELD(6, 7) +#define OMAP4430_TESLA_L2_STATEST_MASK (0x3 << 6) /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ #define OMAP4430_TIMEOUT_SHIFT 0 -#define OMAP4430_TIMEOUT_MASK BITFIELD(0, 15) +#define OMAP4430_TIMEOUT_MASK (0xffff << 0) /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ #define OMAP4430_TIMEOUTEN_SHIFT 3 -#define OMAP4430_TIMEOUTEN_MASK BITFIELD(3, 3) +#define OMAP4430_TIMEOUTEN_MASK (1 << 3) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_TRANSITION_EN_SHIFT 8 -#define OMAP4430_TRANSITION_EN_MASK BITFIELD(8, 8) +#define OMAP4430_TRANSITION_EN_MASK (1 << 8) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_TRANSITION_ST_SHIFT 8 -#define OMAP4430_TRANSITION_ST_MASK BITFIELD(8, 8) +#define OMAP4430_TRANSITION_ST_MASK (1 << 8) /* Used by PRM_VC_VAL_BYPASS */ #define OMAP4430_VALID_SHIFT 24 -#define OMAP4430_VALID_MASK BITFIELD(24, 24) +#define OMAP4430_VALID_MASK (1 << 24) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VC_BYPASSACK_EN_SHIFT 14 -#define OMAP4430_VC_BYPASSACK_EN_MASK BITFIELD(14, 14) +#define OMAP4430_VC_BYPASSACK_EN_MASK (1 << 14) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VC_BYPASSACK_ST_SHIFT 14 -#define OMAP4430_VC_BYPASSACK_ST_MASK BITFIELD(14, 14) +#define OMAP4430_VC_BYPASSACK_ST_MASK (1 << 14) + +/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ +#define OMAP4430_VC_CORE_VPACK_EN_SHIFT 22 +#define OMAP4430_VC_CORE_VPACK_EN_MASK (1 << 22) + +/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ +#define OMAP4430_VC_CORE_VPACK_ST_SHIFT 22 +#define OMAP4430_VC_CORE_VPACK_ST_MASK (1 << 22) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VC_IVA_VPACK_EN_SHIFT 30 -#define OMAP4430_VC_IVA_VPACK_EN_MASK BITFIELD(30, 30) +#define OMAP4430_VC_IVA_VPACK_EN_MASK (1 << 30) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VC_IVA_VPACK_ST_SHIFT 30 -#define OMAP4430_VC_IVA_VPACK_ST_MASK BITFIELD(30, 30) +#define OMAP4430_VC_IVA_VPACK_ST_MASK (1 << 30) /* Used by PRM_IRQENABLE_MPU_2 */ #define OMAP4430_VC_MPU_VPACK_EN_SHIFT 6 -#define OMAP4430_VC_MPU_VPACK_EN_MASK BITFIELD(6, 6) +#define OMAP4430_VC_MPU_VPACK_EN_MASK (1 << 6) /* Used by PRM_IRQSTATUS_MPU_2 */ #define OMAP4430_VC_MPU_VPACK_ST_SHIFT 6 -#define OMAP4430_VC_MPU_VPACK_ST_MASK BITFIELD(6, 6) +#define OMAP4430_VC_MPU_VPACK_ST_MASK (1 << 6) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VC_RAERR_EN_SHIFT 12 -#define OMAP4430_VC_RAERR_EN_MASK BITFIELD(12, 12) +#define OMAP4430_VC_RAERR_EN_MASK (1 << 12) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VC_RAERR_ST_SHIFT 12 -#define OMAP4430_VC_RAERR_ST_MASK BITFIELD(12, 12) +#define OMAP4430_VC_RAERR_ST_MASK (1 << 12) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VC_SAERR_EN_SHIFT 11 -#define OMAP4430_VC_SAERR_EN_MASK BITFIELD(11, 11) +#define OMAP4430_VC_SAERR_EN_MASK (1 << 11) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VC_SAERR_ST_SHIFT 11 -#define OMAP4430_VC_SAERR_ST_MASK BITFIELD(11, 11) +#define OMAP4430_VC_SAERR_ST_MASK (1 << 11) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VC_TOERR_EN_SHIFT 13 -#define OMAP4430_VC_TOERR_EN_MASK BITFIELD(13, 13) +#define OMAP4430_VC_TOERR_EN_MASK (1 << 13) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VC_TOERR_ST_SHIFT 13 -#define OMAP4430_VC_TOERR_ST_MASK BITFIELD(13, 13) +#define OMAP4430_VC_TOERR_ST_MASK (1 << 13) /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ #define OMAP4430_VDDMAX_SHIFT 24 -#define OMAP4430_VDDMAX_MASK BITFIELD(24, 31) +#define OMAP4430_VDDMAX_MASK (0xff << 24) /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ #define OMAP4430_VDDMIN_SHIFT 16 -#define OMAP4430_VDDMIN_MASK BITFIELD(16, 23) +#define OMAP4430_VDDMIN_MASK (0xff << 16) /* Used by PRM_VOLTCTRL */ #define OMAP4430_VDD_CORE_I2C_DISABLE_SHIFT 12 -#define OMAP4430_VDD_CORE_I2C_DISABLE_MASK BITFIELD(12, 12) +#define OMAP4430_VDD_CORE_I2C_DISABLE_MASK (1 << 12) /* Used by PRM_RSTST */ #define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT 8 -#define OMAP4430_VDD_CORE_VOLT_MGR_RST_MASK BITFIELD(8, 8) +#define OMAP4430_VDD_CORE_VOLT_MGR_RST_MASK (1 << 8) /* Used by PRM_VOLTCTRL */ #define OMAP4430_VDD_IVA_I2C_DISABLE_SHIFT 14 -#define OMAP4430_VDD_IVA_I2C_DISABLE_MASK BITFIELD(14, 14) +#define OMAP4430_VDD_IVA_I2C_DISABLE_MASK (1 << 14) /* Used by PRM_VOLTCTRL */ #define OMAP4430_VDD_IVA_PRESENCE_SHIFT 9 -#define OMAP4430_VDD_IVA_PRESENCE_MASK BITFIELD(9, 9) +#define OMAP4430_VDD_IVA_PRESENCE_MASK (1 << 9) /* Used by PRM_RSTST */ #define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT 7 -#define OMAP4430_VDD_IVA_VOLT_MGR_RST_MASK BITFIELD(7, 7) +#define OMAP4430_VDD_IVA_VOLT_MGR_RST_MASK (1 << 7) /* Used by PRM_VOLTCTRL */ #define OMAP4430_VDD_MPU_I2C_DISABLE_SHIFT 13 -#define OMAP4430_VDD_MPU_I2C_DISABLE_MASK BITFIELD(13, 13) +#define OMAP4430_VDD_MPU_I2C_DISABLE_MASK (1 << 13) /* Used by PRM_VOLTCTRL */ #define OMAP4430_VDD_MPU_PRESENCE_SHIFT 8 -#define OMAP4430_VDD_MPU_PRESENCE_MASK BITFIELD(8, 8) +#define OMAP4430_VDD_MPU_PRESENCE_MASK (1 << 8) /* Used by PRM_RSTST */ #define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT 6 -#define OMAP4430_VDD_MPU_VOLT_MGR_RST_MASK BITFIELD(6, 6) +#define OMAP4430_VDD_MPU_VOLT_MGR_RST_MASK (1 << 6) + +/* Used by PRM_VC_ERRST */ +#define OMAP4430_VFSM_RA_ERR_CORE_SHIFT 4 +#define OMAP4430_VFSM_RA_ERR_CORE_MASK (1 << 4) + +/* Used by PRM_VC_ERRST */ +#define OMAP4430_VFSM_RA_ERR_IVA_SHIFT 12 +#define OMAP4430_VFSM_RA_ERR_IVA_MASK (1 << 12) + +/* Used by PRM_VC_ERRST */ +#define OMAP4430_VFSM_RA_ERR_MPU_SHIFT 20 +#define OMAP4430_VFSM_RA_ERR_MPU_MASK (1 << 20) + +/* Used by PRM_VC_ERRST */ +#define OMAP4430_VFSM_SA_ERR_CORE_SHIFT 3 +#define OMAP4430_VFSM_SA_ERR_CORE_MASK (1 << 3) + +/* Used by PRM_VC_ERRST */ +#define OMAP4430_VFSM_SA_ERR_IVA_SHIFT 11 +#define OMAP4430_VFSM_SA_ERR_IVA_MASK (1 << 11) + +/* Used by PRM_VC_ERRST */ +#define OMAP4430_VFSM_SA_ERR_MPU_SHIFT 19 +#define OMAP4430_VFSM_SA_ERR_MPU_MASK (1 << 19) + +/* Used by PRM_VC_ERRST */ +#define OMAP4430_VFSM_TIMEOUT_ERR_CORE_SHIFT 5 +#define OMAP4430_VFSM_TIMEOUT_ERR_CORE_MASK (1 << 5) + +/* Used by PRM_VC_ERRST */ +#define OMAP4430_VFSM_TIMEOUT_ERR_IVA_SHIFT 13 +#define OMAP4430_VFSM_TIMEOUT_ERR_IVA_MASK (1 << 13) + +/* Used by PRM_VC_ERRST */ +#define OMAP4430_VFSM_TIMEOUT_ERR_MPU_SHIFT 21 +#define OMAP4430_VFSM_TIMEOUT_ERR_MPU_MASK (1 << 21) /* Used by PRM_VC_VAL_SMPS_RA_VOL */ #define OMAP4430_VOLRA_VDD_CORE_L_SHIFT 0 -#define OMAP4430_VOLRA_VDD_CORE_L_MASK BITFIELD(0, 7) +#define OMAP4430_VOLRA_VDD_CORE_L_MASK (0xff << 0) /* Used by PRM_VC_VAL_SMPS_RA_VOL */ #define OMAP4430_VOLRA_VDD_IVA_L_SHIFT 8 -#define OMAP4430_VOLRA_VDD_IVA_L_MASK BITFIELD(8, 15) +#define OMAP4430_VOLRA_VDD_IVA_L_MASK (0xff << 8) /* Used by PRM_VC_VAL_SMPS_RA_VOL */ #define OMAP4430_VOLRA_VDD_MPU_L_SHIFT 16 -#define OMAP4430_VOLRA_VDD_MPU_L_MASK BITFIELD(16, 23) +#define OMAP4430_VOLRA_VDD_MPU_L_MASK (0xff << 16) /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ #define OMAP4430_VPENABLE_SHIFT 0 -#define OMAP4430_VPENABLE_MASK BITFIELD(0, 0) +#define OMAP4430_VPENABLE_MASK (1 << 0) /* Used by PRM_VP_CORE_STATUS, PRM_VP_IVA_STATUS, PRM_VP_MPU_STATUS */ #define OMAP4430_VPINIDLE_SHIFT 0 -#define OMAP4430_VPINIDLE_MASK BITFIELD(0, 0) +#define OMAP4430_VPINIDLE_MASK (1 << 0) /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */ #define OMAP4430_VPVOLTAGE_SHIFT 0 -#define OMAP4430_VPVOLTAGE_MASK BITFIELD(0, 7) +#define OMAP4430_VPVOLTAGE_MASK (0xff << 0) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_CORE_EQVALUE_EN_SHIFT 20 -#define OMAP4430_VP_CORE_EQVALUE_EN_MASK BITFIELD(20, 20) +#define OMAP4430_VP_CORE_EQVALUE_EN_MASK (1 << 20) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_CORE_EQVALUE_ST_SHIFT 20 -#define OMAP4430_VP_CORE_EQVALUE_ST_MASK BITFIELD(20, 20) +#define OMAP4430_VP_CORE_EQVALUE_ST_MASK (1 << 20) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_CORE_MAXVDD_EN_SHIFT 18 -#define OMAP4430_VP_CORE_MAXVDD_EN_MASK BITFIELD(18, 18) +#define OMAP4430_VP_CORE_MAXVDD_EN_MASK (1 << 18) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_CORE_MAXVDD_ST_SHIFT 18 -#define OMAP4430_VP_CORE_MAXVDD_ST_MASK BITFIELD(18, 18) +#define OMAP4430_VP_CORE_MAXVDD_ST_MASK (1 << 18) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_CORE_MINVDD_EN_SHIFT 17 -#define OMAP4430_VP_CORE_MINVDD_EN_MASK BITFIELD(17, 17) +#define OMAP4430_VP_CORE_MINVDD_EN_MASK (1 << 17) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_CORE_MINVDD_ST_SHIFT 17 -#define OMAP4430_VP_CORE_MINVDD_ST_MASK BITFIELD(17, 17) +#define OMAP4430_VP_CORE_MINVDD_ST_MASK (1 << 17) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_CORE_NOSMPSACK_EN_SHIFT 19 -#define OMAP4430_VP_CORE_NOSMPSACK_EN_MASK BITFIELD(19, 19) +#define OMAP4430_VP_CORE_NOSMPSACK_EN_MASK (1 << 19) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_CORE_NOSMPSACK_ST_SHIFT 19 -#define OMAP4430_VP_CORE_NOSMPSACK_ST_MASK BITFIELD(19, 19) +#define OMAP4430_VP_CORE_NOSMPSACK_ST_MASK (1 << 19) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_SHIFT 16 -#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_MASK BITFIELD(16, 16) +#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_MASK (1 << 16) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_SHIFT 16 -#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_MASK BITFIELD(16, 16) +#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_MASK (1 << 16) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_CORE_TRANXDONE_EN_SHIFT 21 -#define OMAP4430_VP_CORE_TRANXDONE_EN_MASK BITFIELD(21, 21) +#define OMAP4430_VP_CORE_TRANXDONE_EN_MASK (1 << 21) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_CORE_TRANXDONE_ST_SHIFT 21 -#define OMAP4430_VP_CORE_TRANXDONE_ST_MASK BITFIELD(21, 21) +#define OMAP4430_VP_CORE_TRANXDONE_ST_MASK (1 << 21) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_IVA_EQVALUE_EN_SHIFT 28 -#define OMAP4430_VP_IVA_EQVALUE_EN_MASK BITFIELD(28, 28) +#define OMAP4430_VP_IVA_EQVALUE_EN_MASK (1 << 28) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_IVA_EQVALUE_ST_SHIFT 28 -#define OMAP4430_VP_IVA_EQVALUE_ST_MASK BITFIELD(28, 28) +#define OMAP4430_VP_IVA_EQVALUE_ST_MASK (1 << 28) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_IVA_MAXVDD_EN_SHIFT 26 -#define OMAP4430_VP_IVA_MAXVDD_EN_MASK BITFIELD(26, 26) +#define OMAP4430_VP_IVA_MAXVDD_EN_MASK (1 << 26) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_IVA_MAXVDD_ST_SHIFT 26 -#define OMAP4430_VP_IVA_MAXVDD_ST_MASK BITFIELD(26, 26) +#define OMAP4430_VP_IVA_MAXVDD_ST_MASK (1 << 26) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_IVA_MINVDD_EN_SHIFT 25 -#define OMAP4430_VP_IVA_MINVDD_EN_MASK BITFIELD(25, 25) +#define OMAP4430_VP_IVA_MINVDD_EN_MASK (1 << 25) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_IVA_MINVDD_ST_SHIFT 25 -#define OMAP4430_VP_IVA_MINVDD_ST_MASK BITFIELD(25, 25) +#define OMAP4430_VP_IVA_MINVDD_ST_MASK (1 << 25) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_IVA_NOSMPSACK_EN_SHIFT 27 -#define OMAP4430_VP_IVA_NOSMPSACK_EN_MASK BITFIELD(27, 27) +#define OMAP4430_VP_IVA_NOSMPSACK_EN_MASK (1 << 27) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_IVA_NOSMPSACK_ST_SHIFT 27 -#define OMAP4430_VP_IVA_NOSMPSACK_ST_MASK BITFIELD(27, 27) +#define OMAP4430_VP_IVA_NOSMPSACK_ST_MASK (1 << 27) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_SHIFT 24 -#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_MASK BITFIELD(24, 24) +#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_MASK (1 << 24) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_SHIFT 24 -#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_MASK BITFIELD(24, 24) +#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_MASK (1 << 24) /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ #define OMAP4430_VP_IVA_TRANXDONE_EN_SHIFT 29 -#define OMAP4430_VP_IVA_TRANXDONE_EN_MASK BITFIELD(29, 29) +#define OMAP4430_VP_IVA_TRANXDONE_EN_MASK (1 << 29) /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ #define OMAP4430_VP_IVA_TRANXDONE_ST_SHIFT 29 -#define OMAP4430_VP_IVA_TRANXDONE_ST_MASK BITFIELD(29, 29) +#define OMAP4430_VP_IVA_TRANXDONE_ST_MASK (1 << 29) /* Used by PRM_IRQENABLE_MPU_2 */ #define OMAP4430_VP_MPU_EQVALUE_EN_SHIFT 4 -#define OMAP4430_VP_MPU_EQVALUE_EN_MASK BITFIELD(4, 4) +#define OMAP4430_VP_MPU_EQVALUE_EN_MASK (1 << 4) /* Used by PRM_IRQSTATUS_MPU_2 */ #define OMAP4430_VP_MPU_EQVALUE_ST_SHIFT 4 -#define OMAP4430_VP_MPU_EQVALUE_ST_MASK BITFIELD(4, 4) +#define OMAP4430_VP_MPU_EQVALUE_ST_MASK (1 << 4) /* Used by PRM_IRQENABLE_MPU_2 */ #define OMAP4430_VP_MPU_MAXVDD_EN_SHIFT 2 -#define OMAP4430_VP_MPU_MAXVDD_EN_MASK BITFIELD(2, 2) +#define OMAP4430_VP_MPU_MAXVDD_EN_MASK (1 << 2) /* Used by PRM_IRQSTATUS_MPU_2 */ #define OMAP4430_VP_MPU_MAXVDD_ST_SHIFT 2 -#define OMAP4430_VP_MPU_MAXVDD_ST_MASK BITFIELD(2, 2) +#define OMAP4430_VP_MPU_MAXVDD_ST_MASK (1 << 2) /* Used by PRM_IRQENABLE_MPU_2 */ #define OMAP4430_VP_MPU_MINVDD_EN_SHIFT 1 -#define OMAP4430_VP_MPU_MINVDD_EN_MASK BITFIELD(1, 1) +#define OMAP4430_VP_MPU_MINVDD_EN_MASK (1 << 1) /* Used by PRM_IRQSTATUS_MPU_2 */ #define OMAP4430_VP_MPU_MINVDD_ST_SHIFT 1 -#define OMAP4430_VP_MPU_MINVDD_ST_MASK BITFIELD(1, 1) +#define OMAP4430_VP_MPU_MINVDD_ST_MASK (1 << 1) /* Used by PRM_IRQENABLE_MPU_2 */ #define OMAP4430_VP_MPU_NOSMPSACK_EN_SHIFT 3 -#define OMAP4430_VP_MPU_NOSMPSACK_EN_MASK BITFIELD(3, 3) +#define OMAP4430_VP_MPU_NOSMPSACK_EN_MASK (1 << 3) /* Used by PRM_IRQSTATUS_MPU_2 */ #define OMAP4430_VP_MPU_NOSMPSACK_ST_SHIFT 3 -#define OMAP4430_VP_MPU_NOSMPSACK_ST_MASK BITFIELD(3, 3) +#define OMAP4430_VP_MPU_NOSMPSACK_ST_MASK (1 << 3) /* Used by PRM_IRQENABLE_MPU_2 */ #define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_SHIFT 0 -#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_MASK BITFIELD(0, 0) +#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_MASK (1 << 0) /* Used by PRM_IRQSTATUS_MPU_2 */ #define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_SHIFT 0 -#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_MASK BITFIELD(0, 0) +#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_MASK (1 << 0) /* Used by PRM_IRQENABLE_MPU_2 */ #define OMAP4430_VP_MPU_TRANXDONE_EN_SHIFT 5 -#define OMAP4430_VP_MPU_TRANXDONE_EN_MASK BITFIELD(5, 5) +#define OMAP4430_VP_MPU_TRANXDONE_EN_MASK (1 << 5) /* Used by PRM_IRQSTATUS_MPU_2 */ #define OMAP4430_VP_MPU_TRANXDONE_ST_SHIFT 5 -#define OMAP4430_VP_MPU_TRANXDONE_ST_MASK BITFIELD(5, 5) +#define OMAP4430_VP_MPU_TRANXDONE_ST_MASK (1 << 5) /* Used by PRM_SRAM_COUNT */ #define OMAP4430_VSETUPCNT_VALUE_SHIFT 8 -#define OMAP4430_VSETUPCNT_VALUE_MASK BITFIELD(8, 15) +#define OMAP4430_VSETUPCNT_VALUE_MASK (0xff << 8) /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ #define OMAP4430_VSTEPMAX_SHIFT 0 -#define OMAP4430_VSTEPMAX_MASK BITFIELD(0, 7) +#define OMAP4430_VSTEPMAX_MASK (0xff << 0) /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ #define OMAP4430_VSTEPMIN_SHIFT 0 -#define OMAP4430_VSTEPMIN_MASK BITFIELD(0, 7) +#define OMAP4430_VSTEPMIN_MASK (0xff << 0) /* Used by PRM_MODEM_IF_CTRL */ #define OMAP4430_WAKE_MODEM_SHIFT 0 -#define OMAP4430_WAKE_MODEM_MASK BITFIELD(0, 0) +#define OMAP4430_WAKE_MODEM_MASK (1 << 0) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DISPC_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_DISPC_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_DISPC_DUCATI_MASK (1 << 1) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DISPC_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DISPC_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_DISPC_MPU_MASK (1 << 0) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DISPC_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_DISPC_SDMA_MASK BITFIELD(3, 3) +#define OMAP4430_WKUPDEP_DISPC_SDMA_MASK (1 << 3) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DISPC_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_DISPC_TESLA_MASK BITFIELD(2, 2) +#define OMAP4430_WKUPDEP_DISPC_TESLA_MASK (1 << 2) /* Used by PM_ABE_DMIC_WKDEP */ #define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_MASK BITFIELD(7, 7) +#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_MASK (1 << 7) /* Used by PM_ABE_DMIC_WKDEP */ #define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_MASK BITFIELD(6, 6) +#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_MASK (1 << 6) /* Used by PM_ABE_DMIC_WKDEP */ #define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_MASK (1 << 0) /* Used by PM_ABE_DMIC_WKDEP */ #define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_MASK BITFIELD(2, 2) +#define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_MASK (1 << 2) /* Used by PM_L4PER_DMTIMER10_WKDEP */ #define OMAP4430_WKUPDEP_DMTIMER10_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DMTIMER10_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_DMTIMER10_MPU_MASK (1 << 0) /* Used by PM_L4PER_DMTIMER11_WKDEP */ #define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_MASK (1 << 1) /* Used by PM_L4PER_DMTIMER11_WKDEP */ #define OMAP4430_WKUPDEP_DMTIMER11_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DMTIMER11_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_DMTIMER11_MPU_MASK (1 << 0) /* Used by PM_L4PER_DMTIMER2_WKDEP */ #define OMAP4430_WKUPDEP_DMTIMER2_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DMTIMER2_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_DMTIMER2_MPU_MASK (1 << 0) /* Used by PM_L4PER_DMTIMER3_WKDEP */ #define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_MASK (1 << 1) /* Used by PM_L4PER_DMTIMER3_WKDEP */ #define OMAP4430_WKUPDEP_DMTIMER3_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DMTIMER3_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_DMTIMER3_MPU_MASK (1 << 0) /* Used by PM_L4PER_DMTIMER4_WKDEP */ #define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_MASK (1 << 1) /* Used by PM_L4PER_DMTIMER4_WKDEP */ #define OMAP4430_WKUPDEP_DMTIMER4_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DMTIMER4_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_DMTIMER4_MPU_MASK (1 << 0) /* Used by PM_L4PER_DMTIMER9_WKDEP */ #define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_MASK (1 << 1) /* Used by PM_L4PER_DMTIMER9_WKDEP */ #define OMAP4430_WKUPDEP_DMTIMER9_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DMTIMER9_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_DMTIMER9_MPU_MASK (1 << 0) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DSI1_DUCATI_SHIFT 5 -#define OMAP4430_WKUPDEP_DSI1_DUCATI_MASK BITFIELD(5, 5) +#define OMAP4430_WKUPDEP_DSI1_DUCATI_MASK (1 << 5) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DSI1_MPU_SHIFT 4 -#define OMAP4430_WKUPDEP_DSI1_MPU_MASK BITFIELD(4, 4) +#define OMAP4430_WKUPDEP_DSI1_MPU_MASK (1 << 4) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DSI1_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_DSI1_SDMA_MASK BITFIELD(7, 7) +#define OMAP4430_WKUPDEP_DSI1_SDMA_MASK (1 << 7) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DSI1_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_DSI1_TESLA_MASK BITFIELD(6, 6) +#define OMAP4430_WKUPDEP_DSI1_TESLA_MASK (1 << 6) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DSI2_DUCATI_SHIFT 9 -#define OMAP4430_WKUPDEP_DSI2_DUCATI_MASK BITFIELD(9, 9) +#define OMAP4430_WKUPDEP_DSI2_DUCATI_MASK (1 << 9) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DSI2_MPU_SHIFT 8 -#define OMAP4430_WKUPDEP_DSI2_MPU_MASK BITFIELD(8, 8) +#define OMAP4430_WKUPDEP_DSI2_MPU_MASK (1 << 8) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DSI2_SDMA_SHIFT 11 -#define OMAP4430_WKUPDEP_DSI2_SDMA_MASK BITFIELD(11, 11) +#define OMAP4430_WKUPDEP_DSI2_SDMA_MASK (1 << 11) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_DSI2_TESLA_SHIFT 10 -#define OMAP4430_WKUPDEP_DSI2_TESLA_MASK BITFIELD(10, 10) +#define OMAP4430_WKUPDEP_DSI2_TESLA_MASK (1 << 10) /* Used by PM_WKUP_GPIO1_WKDEP */ #define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_MASK (1 << 1) /* Used by PM_WKUP_GPIO1_WKDEP */ #define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_MASK (1 << 0) /* Used by PM_WKUP_GPIO1_WKDEP */ #define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_MASK BITFIELD(6, 6) +#define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_MASK (1 << 6) /* Used by PM_L4PER_GPIO2_WKDEP */ #define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_MASK (1 << 1) /* Used by PM_L4PER_GPIO2_WKDEP */ #define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_MASK (1 << 0) /* Used by PM_L4PER_GPIO2_WKDEP */ #define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_MASK BITFIELD(6, 6) +#define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_MASK (1 << 6) /* Used by PM_L4PER_GPIO3_WKDEP */ #define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_MASK (1 << 0) /* Used by PM_L4PER_GPIO3_WKDEP */ #define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_MASK BITFIELD(6, 6) +#define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_MASK (1 << 6) /* Used by PM_L4PER_GPIO4_WKDEP */ #define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_MASK (1 << 0) /* Used by PM_L4PER_GPIO4_WKDEP */ #define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_MASK BITFIELD(6, 6) +#define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_MASK (1 << 6) /* Used by PM_L4PER_GPIO5_WKDEP */ #define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_MASK (1 << 0) /* Used by PM_L4PER_GPIO5_WKDEP */ #define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_MASK BITFIELD(6, 6) +#define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_MASK (1 << 6) /* Used by PM_L4PER_GPIO6_WKDEP */ #define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_MASK (1 << 0) /* Used by PM_L4PER_GPIO6_WKDEP */ #define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_MASK BITFIELD(6, 6) +#define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_MASK (1 << 6) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_HDMIDMA_SDMA_SHIFT 19 -#define OMAP4430_WKUPDEP_HDMIDMA_SDMA_MASK BITFIELD(19, 19) +#define OMAP4430_WKUPDEP_HDMIDMA_SDMA_MASK (1 << 19) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_SHIFT 13 -#define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_MASK BITFIELD(13, 13) +#define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_MASK (1 << 13) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_HDMIIRQ_MPU_SHIFT 12 -#define OMAP4430_WKUPDEP_HDMIIRQ_MPU_MASK BITFIELD(12, 12) +#define OMAP4430_WKUPDEP_HDMIIRQ_MPU_MASK (1 << 12) /* Used by PM_DSS_DSS_WKDEP */ #define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_SHIFT 14 -#define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_MASK BITFIELD(14, 14) +#define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_MASK (1 << 14) /* Used by PM_L4PER_HECC1_WKDEP */ #define OMAP4430_WKUPDEP_HECC1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_HECC1_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_HECC1_MPU_MASK (1 << 0) /* Used by PM_L4PER_HECC2_WKDEP */ #define OMAP4430_WKUPDEP_HECC2_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_HECC2_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_HECC2_MPU_MASK (1 << 0) /* Used by PM_L3INIT_HSI_WKDEP */ #define OMAP4430_WKUPDEP_HSI_DSP_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_HSI_DSP_TESLA_MASK BITFIELD(6, 6) +#define OMAP4430_WKUPDEP_HSI_DSP_TESLA_MASK (1 << 6) /* Used by PM_L3INIT_HSI_WKDEP */ #define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_MASK (1 << 1) /* Used by PM_L3INIT_HSI_WKDEP */ #define OMAP4430_WKUPDEP_HSI_MCU_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_HSI_MCU_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_HSI_MCU_MPU_MASK (1 << 0) /* Used by PM_L4PER_I2C1_WKDEP */ #define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_MASK BITFIELD(7, 7) +#define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_MASK (1 << 7) /* Used by PM_L4PER_I2C1_WKDEP */ #define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_MASK (1 << 1) /* Used by PM_L4PER_I2C1_WKDEP */ #define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_MASK (1 << 0) /* Used by PM_L4PER_I2C2_WKDEP */ #define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_MASK BITFIELD(7, 7) +#define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_MASK (1 << 7) /* Used by PM_L4PER_I2C2_WKDEP */ #define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_MASK (1 << 1) /* Used by PM_L4PER_I2C2_WKDEP */ #define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_MASK (1 << 0) /* Used by PM_L4PER_I2C3_WKDEP */ #define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_MASK BITFIELD(7, 7) +#define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_MASK (1 << 7) /* Used by PM_L4PER_I2C3_WKDEP */ #define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_MASK (1 << 1) /* Used by PM_L4PER_I2C3_WKDEP */ #define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_MASK (1 << 0) /* Used by PM_L4PER_I2C4_WKDEP */ #define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_MASK BITFIELD(7, 7) +#define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_MASK (1 << 7) /* Used by PM_L4PER_I2C4_WKDEP */ #define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_MASK (1 << 1) /* Used by PM_L4PER_I2C4_WKDEP */ #define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_MASK (1 << 0) /* Used by PM_L4PER_I2C5_WKDEP */ #define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_MASK BITFIELD(7, 7) +#define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_MASK (1 << 7) /* Used by PM_L4PER_I2C5_WKDEP */ #define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_MASK (1 << 0) /* Used by PM_WKUP_KEYBOARD_WKDEP */ #define OMAP4430_WKUPDEP_KEYBOARD_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_KEYBOARD_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_KEYBOARD_MPU_MASK (1 << 0) /* Used by PM_ABE_MCASP_WKDEP */ #define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_MASK BITFIELD(7, 7) +#define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_MASK (1 << 7) /* Used by PM_ABE_MCASP_WKDEP */ #define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_MASK BITFIELD(6, 6) +#define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_MASK (1 << 6) /* Used by PM_ABE_MCASP_WKDEP */ #define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_MASK (1 << 0) /* Used by PM_ABE_MCASP_WKDEP */ #define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_MASK BITFIELD(2, 2) +#define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_MASK (1 << 2) /* Used by PM_L4PER_MCASP2_WKDEP */ #define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_MASK BITFIELD(7, 7) +#define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_MASK (1 << 7) /* Used by PM_L4PER_MCASP2_WKDEP */ #define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_MASK BITFIELD(6, 6) +#define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_MASK (1 << 6) /* Used by PM_L4PER_MCASP2_WKDEP */ #define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_MASK (1 << 0) /* Used by PM_L4PER_MCASP2_WKDEP */ #define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_MASK BITFIELD(2, 2) +#define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_MASK (1 << 2) /* Used by PM_L4PER_MCASP3_WKDEP */ #define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_MASK BITFIELD(7, 7) +#define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_MASK (1 << 7) /* Used by PM_L4PER_MCASP3_WKDEP */ #define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_MASK BITFIELD(6, 6) +#define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_MASK (1 << 6) /* Used by PM_L4PER_MCASP3_WKDEP */ #define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_MASK (1 << 0) /* Used by PM_L4PER_MCASP3_WKDEP */ #define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_MASK BITFIELD(2, 2) +#define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_MASK (1 << 2) /* Used by PM_ABE_MCBSP1_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCBSP1_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_MCBSP1_MPU_MASK (1 << 0) /* Used by PM_ABE_MCBSP1_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP1_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCBSP1_SDMA_MASK BITFIELD(3, 3) +#define OMAP4430_WKUPDEP_MCBSP1_SDMA_MASK (1 << 3) /* Used by PM_ABE_MCBSP1_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP1_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCBSP1_TESLA_MASK BITFIELD(2, 2) +#define OMAP4430_WKUPDEP_MCBSP1_TESLA_MASK (1 << 2) /* Used by PM_ABE_MCBSP2_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP2_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCBSP2_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_MCBSP2_MPU_MASK (1 << 0) /* Used by PM_ABE_MCBSP2_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP2_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCBSP2_SDMA_MASK BITFIELD(3, 3) +#define OMAP4430_WKUPDEP_MCBSP2_SDMA_MASK (1 << 3) /* Used by PM_ABE_MCBSP2_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP2_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCBSP2_TESLA_MASK BITFIELD(2, 2) +#define OMAP4430_WKUPDEP_MCBSP2_TESLA_MASK (1 << 2) /* Used by PM_ABE_MCBSP3_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP3_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCBSP3_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_MCBSP3_MPU_MASK (1 << 0) /* Used by PM_ABE_MCBSP3_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP3_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCBSP3_SDMA_MASK BITFIELD(3, 3) +#define OMAP4430_WKUPDEP_MCBSP3_SDMA_MASK (1 << 3) /* Used by PM_ABE_MCBSP3_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP3_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCBSP3_TESLA_MASK BITFIELD(2, 2) +#define OMAP4430_WKUPDEP_MCBSP3_TESLA_MASK (1 << 2) /* Used by PM_L4PER_MCBSP4_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP4_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCBSP4_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_MCBSP4_MPU_MASK (1 << 0) /* Used by PM_L4PER_MCBSP4_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP4_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCBSP4_SDMA_MASK BITFIELD(3, 3) +#define OMAP4430_WKUPDEP_MCBSP4_SDMA_MASK (1 << 3) /* Used by PM_L4PER_MCBSP4_WKDEP */ #define OMAP4430_WKUPDEP_MCBSP4_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCBSP4_TESLA_MASK BITFIELD(2, 2) +#define OMAP4430_WKUPDEP_MCBSP4_TESLA_MASK (1 << 2) /* Used by PM_L4PER_MCSPI1_WKDEP */ #define OMAP4430_WKUPDEP_MCSPI1_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MCSPI1_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_MCSPI1_DUCATI_MASK (1 << 1) /* Used by PM_L4PER_MCSPI1_WKDEP */ #define OMAP4430_WKUPDEP_MCSPI1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCSPI1_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_MCSPI1_MPU_MASK (1 << 0) /* Used by PM_L4PER_MCSPI1_WKDEP */ #define OMAP4430_WKUPDEP_MCSPI1_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCSPI1_SDMA_MASK BITFIELD(3, 3) +#define OMAP4430_WKUPDEP_MCSPI1_SDMA_MASK (1 << 3) /* Used by PM_L4PER_MCSPI1_WKDEP */ #define OMAP4430_WKUPDEP_MCSPI1_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCSPI1_TESLA_MASK BITFIELD(2, 2) +#define OMAP4430_WKUPDEP_MCSPI1_TESLA_MASK (1 << 2) /* Used by PM_L4PER_MCSPI2_WKDEP */ #define OMAP4430_WKUPDEP_MCSPI2_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MCSPI2_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_MCSPI2_DUCATI_MASK (1 << 1) /* Used by PM_L4PER_MCSPI2_WKDEP */ #define OMAP4430_WKUPDEP_MCSPI2_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCSPI2_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_MCSPI2_MPU_MASK (1 << 0) /* Used by PM_L4PER_MCSPI2_WKDEP */ #define OMAP4430_WKUPDEP_MCSPI2_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCSPI2_SDMA_MASK BITFIELD(3, 3) +#define OMAP4430_WKUPDEP_MCSPI2_SDMA_MASK (1 << 3) /* Used by PM_L4PER_MCSPI3_WKDEP */ #define OMAP4430_WKUPDEP_MCSPI3_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCSPI3_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_MCSPI3_MPU_MASK (1 << 0) /* Used by PM_L4PER_MCSPI3_WKDEP */ #define OMAP4430_WKUPDEP_MCSPI3_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCSPI3_SDMA_MASK BITFIELD(3, 3) +#define OMAP4430_WKUPDEP_MCSPI3_SDMA_MASK (1 << 3) /* Used by PM_L4PER_MCSPI4_WKDEP */ #define OMAP4430_WKUPDEP_MCSPI4_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCSPI4_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_MCSPI4_MPU_MASK (1 << 0) /* Used by PM_L4PER_MCSPI4_WKDEP */ #define OMAP4430_WKUPDEP_MCSPI4_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCSPI4_SDMA_MASK BITFIELD(3, 3) +#define OMAP4430_WKUPDEP_MCSPI4_SDMA_MASK (1 << 3) /* Used by PM_L3INIT_MMC1_WKDEP */ #define OMAP4430_WKUPDEP_MMC1_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MMC1_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_MMC1_DUCATI_MASK (1 << 1) /* Used by PM_L3INIT_MMC1_WKDEP */ #define OMAP4430_WKUPDEP_MMC1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MMC1_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_MMC1_MPU_MASK (1 << 0) /* Used by PM_L3INIT_MMC1_WKDEP */ #define OMAP4430_WKUPDEP_MMC1_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MMC1_SDMA_MASK BITFIELD(3, 3) +#define OMAP4430_WKUPDEP_MMC1_SDMA_MASK (1 << 3) /* Used by PM_L3INIT_MMC1_WKDEP */ #define OMAP4430_WKUPDEP_MMC1_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MMC1_TESLA_MASK BITFIELD(2, 2) +#define OMAP4430_WKUPDEP_MMC1_TESLA_MASK (1 << 2) /* Used by PM_L3INIT_MMC2_WKDEP */ #define OMAP4430_WKUPDEP_MMC2_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MMC2_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_MMC2_DUCATI_MASK (1 << 1) /* Used by PM_L3INIT_MMC2_WKDEP */ #define OMAP4430_WKUPDEP_MMC2_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MMC2_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_MMC2_MPU_MASK (1 << 0) /* Used by PM_L3INIT_MMC2_WKDEP */ #define OMAP4430_WKUPDEP_MMC2_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MMC2_SDMA_MASK BITFIELD(3, 3) +#define OMAP4430_WKUPDEP_MMC2_SDMA_MASK (1 << 3) /* Used by PM_L3INIT_MMC2_WKDEP */ #define OMAP4430_WKUPDEP_MMC2_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MMC2_TESLA_MASK BITFIELD(2, 2) +#define OMAP4430_WKUPDEP_MMC2_TESLA_MASK (1 << 2) /* Used by PM_L3INIT_MMC6_WKDEP */ #define OMAP4430_WKUPDEP_MMC6_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MMC6_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_MMC6_DUCATI_MASK (1 << 1) /* Used by PM_L3INIT_MMC6_WKDEP */ #define OMAP4430_WKUPDEP_MMC6_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MMC6_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_MMC6_MPU_MASK (1 << 0) /* Used by PM_L3INIT_MMC6_WKDEP */ #define OMAP4430_WKUPDEP_MMC6_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MMC6_TESLA_MASK BITFIELD(2, 2) +#define OMAP4430_WKUPDEP_MMC6_TESLA_MASK (1 << 2) /* Used by PM_L4PER_MMCSD3_WKDEP */ #define OMAP4430_WKUPDEP_MMCSD3_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MMCSD3_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_MMCSD3_DUCATI_MASK (1 << 1) /* Used by PM_L4PER_MMCSD3_WKDEP */ #define OMAP4430_WKUPDEP_MMCSD3_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MMCSD3_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_MMCSD3_MPU_MASK (1 << 0) /* Used by PM_L4PER_MMCSD3_WKDEP */ #define OMAP4430_WKUPDEP_MMCSD3_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MMCSD3_SDMA_MASK BITFIELD(3, 3) +#define OMAP4430_WKUPDEP_MMCSD3_SDMA_MASK (1 << 3) /* Used by PM_L4PER_MMCSD4_WKDEP */ #define OMAP4430_WKUPDEP_MMCSD4_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MMCSD4_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_MMCSD4_DUCATI_MASK (1 << 1) /* Used by PM_L4PER_MMCSD4_WKDEP */ #define OMAP4430_WKUPDEP_MMCSD4_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MMCSD4_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_MMCSD4_MPU_MASK (1 << 0) /* Used by PM_L4PER_MMCSD4_WKDEP */ #define OMAP4430_WKUPDEP_MMCSD4_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MMCSD4_SDMA_MASK BITFIELD(3, 3) +#define OMAP4430_WKUPDEP_MMCSD4_SDMA_MASK (1 << 3) /* Used by PM_L4PER_MMCSD5_WKDEP */ #define OMAP4430_WKUPDEP_MMCSD5_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MMCSD5_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_MMCSD5_DUCATI_MASK (1 << 1) /* Used by PM_L4PER_MMCSD5_WKDEP */ #define OMAP4430_WKUPDEP_MMCSD5_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MMCSD5_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_MMCSD5_MPU_MASK (1 << 0) /* Used by PM_L4PER_MMCSD5_WKDEP */ #define OMAP4430_WKUPDEP_MMCSD5_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MMCSD5_SDMA_MASK BITFIELD(3, 3) +#define OMAP4430_WKUPDEP_MMCSD5_SDMA_MASK (1 << 3) /* Used by PM_L3INIT_PCIESS_WKDEP */ #define OMAP4430_WKUPDEP_PCIESS_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_PCIESS_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_PCIESS_MPU_MASK (1 << 0) /* Used by PM_L3INIT_PCIESS_WKDEP */ #define OMAP4430_WKUPDEP_PCIESS_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_PCIESS_TESLA_MASK BITFIELD(2, 2) +#define OMAP4430_WKUPDEP_PCIESS_TESLA_MASK (1 << 2) /* Used by PM_ABE_PDM_WKDEP */ #define OMAP4430_WKUPDEP_PDM_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_PDM_DMA_SDMA_MASK BITFIELD(7, 7) +#define OMAP4430_WKUPDEP_PDM_DMA_SDMA_MASK (1 << 7) /* Used by PM_ABE_PDM_WKDEP */ #define OMAP4430_WKUPDEP_PDM_DMA_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_PDM_DMA_TESLA_MASK BITFIELD(6, 6) +#define OMAP4430_WKUPDEP_PDM_DMA_TESLA_MASK (1 << 6) /* Used by PM_ABE_PDM_WKDEP */ #define OMAP4430_WKUPDEP_PDM_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_PDM_IRQ_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_PDM_IRQ_MPU_MASK (1 << 0) /* Used by PM_ABE_PDM_WKDEP */ #define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_MASK BITFIELD(2, 2) +#define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_MASK (1 << 2) /* Used by PM_WKUP_RTC_WKDEP */ #define OMAP4430_WKUPDEP_RTC_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_RTC_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_RTC_MPU_MASK (1 << 0) /* Used by PM_L3INIT_SATA_WKDEP */ #define OMAP4430_WKUPDEP_SATA_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_SATA_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_SATA_MPU_MASK (1 << 0) /* Used by PM_L3INIT_SATA_WKDEP */ #define OMAP4430_WKUPDEP_SATA_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_SATA_TESLA_MASK BITFIELD(2, 2) +#define OMAP4430_WKUPDEP_SATA_TESLA_MASK (1 << 2) /* Used by PM_ABE_SLIMBUS_WKDEP */ #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK BITFIELD(7, 7) +#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK (1 << 7) /* Used by PM_ABE_SLIMBUS_WKDEP */ #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_MASK BITFIELD(6, 6) +#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_MASK (1 << 6) /* Used by PM_ABE_SLIMBUS_WKDEP */ #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK (1 << 0) /* Used by PM_ABE_SLIMBUS_WKDEP */ #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_MASK BITFIELD(2, 2) +#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_MASK (1 << 2) /* Used by PM_L4PER_SLIMBUS2_WKDEP */ #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_MASK BITFIELD(7, 7) +#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_MASK (1 << 7) /* Used by PM_L4PER_SLIMBUS2_WKDEP */ #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_MASK BITFIELD(6, 6) +#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_MASK (1 << 6) /* Used by PM_L4PER_SLIMBUS2_WKDEP */ #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_MASK (1 << 0) /* Used by PM_L4PER_SLIMBUS2_WKDEP */ #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_MASK BITFIELD(2, 2) +#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_MASK (1 << 2) /* Used by PM_ALWON_SR_CORE_WKDEP */ #define OMAP4430_WKUPDEP_SR_CORE_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_SR_CORE_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_SR_CORE_DUCATI_MASK (1 << 1) /* Used by PM_ALWON_SR_CORE_WKDEP */ #define OMAP4430_WKUPDEP_SR_CORE_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_SR_CORE_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_SR_CORE_MPU_MASK (1 << 0) /* Used by PM_ALWON_SR_IVA_WKDEP */ #define OMAP4430_WKUPDEP_SR_IVA_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_SR_IVA_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_SR_IVA_DUCATI_MASK (1 << 1) /* Used by PM_ALWON_SR_IVA_WKDEP */ #define OMAP4430_WKUPDEP_SR_IVA_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_SR_IVA_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_SR_IVA_MPU_MASK (1 << 0) /* Used by PM_ALWON_SR_MPU_WKDEP */ #define OMAP4430_WKUPDEP_SR_MPU_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_SR_MPU_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_SR_MPU_MPU_MASK (1 << 0) /* Used by PM_WKUP_TIMER12_WKDEP */ #define OMAP4430_WKUPDEP_TIMER12_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_TIMER12_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_TIMER12_MPU_MASK (1 << 0) /* Used by PM_WKUP_TIMER1_WKDEP */ #define OMAP4430_WKUPDEP_TIMER1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_TIMER1_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_TIMER1_MPU_MASK (1 << 0) /* Used by PM_ABE_TIMER5_WKDEP */ #define OMAP4430_WKUPDEP_TIMER5_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_TIMER5_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_TIMER5_MPU_MASK (1 << 0) /* Used by PM_ABE_TIMER5_WKDEP */ #define OMAP4430_WKUPDEP_TIMER5_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_TIMER5_TESLA_MASK BITFIELD(2, 2) +#define OMAP4430_WKUPDEP_TIMER5_TESLA_MASK (1 << 2) /* Used by PM_ABE_TIMER6_WKDEP */ #define OMAP4430_WKUPDEP_TIMER6_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_TIMER6_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_TIMER6_MPU_MASK (1 << 0) /* Used by PM_ABE_TIMER6_WKDEP */ #define OMAP4430_WKUPDEP_TIMER6_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_TIMER6_TESLA_MASK BITFIELD(2, 2) +#define OMAP4430_WKUPDEP_TIMER6_TESLA_MASK (1 << 2) /* Used by PM_ABE_TIMER7_WKDEP */ #define OMAP4430_WKUPDEP_TIMER7_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_TIMER7_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_TIMER7_MPU_MASK (1 << 0) /* Used by PM_ABE_TIMER7_WKDEP */ #define OMAP4430_WKUPDEP_TIMER7_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_TIMER7_TESLA_MASK BITFIELD(2, 2) +#define OMAP4430_WKUPDEP_TIMER7_TESLA_MASK (1 << 2) /* Used by PM_ABE_TIMER8_WKDEP */ #define OMAP4430_WKUPDEP_TIMER8_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_TIMER8_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_TIMER8_MPU_MASK (1 << 0) /* Used by PM_ABE_TIMER8_WKDEP */ #define OMAP4430_WKUPDEP_TIMER8_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_TIMER8_TESLA_MASK BITFIELD(2, 2) +#define OMAP4430_WKUPDEP_TIMER8_TESLA_MASK (1 << 2) /* Used by PM_L4PER_UART1_WKDEP */ #define OMAP4430_WKUPDEP_UART1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_UART1_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_UART1_MPU_MASK (1 << 0) /* Used by PM_L4PER_UART1_WKDEP */ #define OMAP4430_WKUPDEP_UART1_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_UART1_SDMA_MASK BITFIELD(3, 3) +#define OMAP4430_WKUPDEP_UART1_SDMA_MASK (1 << 3) /* Used by PM_L4PER_UART2_WKDEP */ #define OMAP4430_WKUPDEP_UART2_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_UART2_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_UART2_MPU_MASK (1 << 0) /* Used by PM_L4PER_UART2_WKDEP */ #define OMAP4430_WKUPDEP_UART2_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_UART2_SDMA_MASK BITFIELD(3, 3) +#define OMAP4430_WKUPDEP_UART2_SDMA_MASK (1 << 3) /* Used by PM_L4PER_UART3_WKDEP */ #define OMAP4430_WKUPDEP_UART3_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_UART3_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_UART3_DUCATI_MASK (1 << 1) /* Used by PM_L4PER_UART3_WKDEP */ #define OMAP4430_WKUPDEP_UART3_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_UART3_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_UART3_MPU_MASK (1 << 0) /* Used by PM_L4PER_UART3_WKDEP */ #define OMAP4430_WKUPDEP_UART3_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_UART3_SDMA_MASK BITFIELD(3, 3) +#define OMAP4430_WKUPDEP_UART3_SDMA_MASK (1 << 3) /* Used by PM_L4PER_UART3_WKDEP */ #define OMAP4430_WKUPDEP_UART3_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_UART3_TESLA_MASK BITFIELD(2, 2) +#define OMAP4430_WKUPDEP_UART3_TESLA_MASK (1 << 2) /* Used by PM_L4PER_UART4_WKDEP */ #define OMAP4430_WKUPDEP_UART4_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_UART4_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_UART4_MPU_MASK (1 << 0) /* Used by PM_L4PER_UART4_WKDEP */ #define OMAP4430_WKUPDEP_UART4_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_UART4_SDMA_MASK BITFIELD(3, 3) +#define OMAP4430_WKUPDEP_UART4_SDMA_MASK (1 << 3) /* Used by PM_L3INIT_UNIPRO1_WKDEP */ #define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_MASK (1 << 1) /* Used by PM_L3INIT_UNIPRO1_WKDEP */ #define OMAP4430_WKUPDEP_UNIPRO1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_UNIPRO1_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_UNIPRO1_MPU_MASK (1 << 0) /* Used by PM_L3INIT_USB_HOST_WKDEP */ #define OMAP4430_WKUPDEP_USB_HOST_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_USB_HOST_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_USB_HOST_DUCATI_MASK (1 << 1) /* Used by PM_L3INIT_USB_HOST_FS_WKDEP */ #define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_MASK (1 << 1) /* Used by PM_L3INIT_USB_HOST_FS_WKDEP */ #define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_MASK (1 << 0) /* Used by PM_L3INIT_USB_HOST_WKDEP */ #define OMAP4430_WKUPDEP_USB_HOST_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_USB_HOST_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_USB_HOST_MPU_MASK (1 << 0) /* Used by PM_L3INIT_USB_OTG_WKDEP */ #define OMAP4430_WKUPDEP_USB_OTG_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_USB_OTG_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_USB_OTG_DUCATI_MASK (1 << 1) /* Used by PM_L3INIT_USB_OTG_WKDEP */ #define OMAP4430_WKUPDEP_USB_OTG_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_USB_OTG_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_USB_OTG_MPU_MASK (1 << 0) /* Used by PM_L3INIT_USB_TLL_WKDEP */ #define OMAP4430_WKUPDEP_USB_TLL_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_USB_TLL_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_USB_TLL_DUCATI_MASK (1 << 1) /* Used by PM_L3INIT_USB_TLL_WKDEP */ #define OMAP4430_WKUPDEP_USB_TLL_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_USB_TLL_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_USB_TLL_MPU_MASK (1 << 0) /* Used by PM_WKUP_USIM_WKDEP */ #define OMAP4430_WKUPDEP_USIM_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_USIM_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_USIM_MPU_MASK (1 << 0) /* Used by PM_WKUP_USIM_WKDEP */ #define OMAP4430_WKUPDEP_USIM_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_USIM_SDMA_MASK BITFIELD(3, 3) +#define OMAP4430_WKUPDEP_USIM_SDMA_MASK (1 << 3) /* Used by PM_WKUP_WDT2_WKDEP */ #define OMAP4430_WKUPDEP_WDT2_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_WDT2_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_WDT2_DUCATI_MASK (1 << 1) /* Used by PM_WKUP_WDT2_WKDEP */ #define OMAP4430_WKUPDEP_WDT2_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_WDT2_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_WDT2_MPU_MASK (1 << 0) /* Used by PM_ABE_WDT3_WKDEP */ #define OMAP4430_WKUPDEP_WDT3_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_WDT3_MPU_MASK BITFIELD(0, 0) +#define OMAP4430_WKUPDEP_WDT3_MPU_MASK (1 << 0) /* Used by PM_L3INIT_HSI_WKDEP */ #define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_SHIFT 8 -#define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_MASK BITFIELD(8, 8) +#define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_MASK (1 << 8) /* Used by PM_L3INIT_XHPI_WKDEP */ #define OMAP4430_WKUPDEP_XHPI_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_XHPI_DUCATI_MASK BITFIELD(1, 1) +#define OMAP4430_WKUPDEP_XHPI_DUCATI_MASK (1 << 1) /* Used by PRM_IO_PMCTRL */ #define OMAP4430_WUCLK_CTRL_SHIFT 8 -#define OMAP4430_WUCLK_CTRL_MASK BITFIELD(8, 8) +#define OMAP4430_WUCLK_CTRL_MASK (1 << 8) /* Used by PRM_IO_PMCTRL */ #define OMAP4430_WUCLK_STATUS_SHIFT 9 -#define OMAP4430_WUCLK_STATUS_MASK BITFIELD(9, 9) +#define OMAP4430_WUCLK_STATUS_MASK (1 << 9) + +/* Used by REVISION_PRM */ +#define OMAP4430_X_MAJOR_SHIFT 8 +#define OMAP4430_X_MAJOR_MASK (0x7 << 8) + +/* Used by REVISION_PRM */ +#define OMAP4430_Y_MINOR_SHIFT 0 +#define OMAP4430_Y_MINOR_MASK (0x3f << 0) #endif -- cgit v1.1 From fdd4f409981e5581e03d4259f2b4923b3158f2cf Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Mon, 27 Sep 2010 14:02:56 -0600 Subject: OMAP4: PM: Define additional registers for ES2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 4430 ES2 has a few new registers added and a few modified from ES1. This patch adds all the register changes in PRM and CM for OMAP4430 ES2. Signed-off-by: Rajendra Nayak Signed-off-by: Benoît Cousson Signed-off-by: Paul Walmsley Cc: Kevin Hilman --- arch/arm/mach-omap2/cm44xx.h | 90 ++++++++++++++++++++++++++++++++++++++++++- arch/arm/mach-omap2/prm44xx.h | 14 ++++--- 2 files changed, 96 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/cm44xx.h b/arch/arm/mach-omap2/cm44xx.h index 336d948..3c35a87 100644 --- a/arch/arm/mach-omap2/cm44xx.h +++ b/arch/arm/mach-omap2/cm44xx.h @@ -195,6 +195,42 @@ #define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088 #define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0088) +/* CM1.RESTORE_CM1 register offsets */ +#define OMAP4_CM_CLKSEL_CORE_RESTORE_OFFSET 0x0000 +#define OMAP4430_CM_CLKSEL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0000) +#define OMAP4_CM_DIV_M2_DPLL_CORE_RESTORE_OFFSET 0x0004 +#define OMAP4430_CM_DIV_M2_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0004) +#define OMAP4_CM_DIV_M3_DPLL_CORE_RESTORE_OFFSET 0x0008 +#define OMAP4430_CM_DIV_M3_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0008) +#define OMAP4_CM_DIV_M4_DPLL_CORE_RESTORE_OFFSET 0x000c +#define OMAP4430_CM_DIV_M4_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x000c) +#define OMAP4_CM_DIV_M5_DPLL_CORE_RESTORE_OFFSET 0x0010 +#define OMAP4430_CM_DIV_M5_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0010) +#define OMAP4_CM_DIV_M6_DPLL_CORE_RESTORE_OFFSET 0x0014 +#define OMAP4430_CM_DIV_M6_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0014) +#define OMAP4_CM_DIV_M7_DPLL_CORE_RESTORE_OFFSET 0x0018 +#define OMAP4430_CM_DIV_M7_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0018) +#define OMAP4_CM_CLKSEL_DPLL_CORE_RESTORE_OFFSET 0x001c +#define OMAP4430_CM_CLKSEL_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x001c) +#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE_OFFSET 0x0020 +#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0020) +#define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE_OFFSET 0x0024 +#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0024) +#define OMAP4_CM_CLKMODE_DPLL_CORE_RESTORE_OFFSET 0x0028 +#define OMAP4430_CM_CLKMODE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0028) +#define OMAP4_CM_SHADOW_FREQ_CONFIG2_RESTORE_OFFSET 0x002c +#define OMAP4430_CM_SHADOW_FREQ_CONFIG2_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x002c) +#define OMAP4_CM_SHADOW_FREQ_CONFIG1_RESTORE_OFFSET 0x0030 +#define OMAP4430_CM_SHADOW_FREQ_CONFIG1_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0030) +#define OMAP4_CM_AUTOIDLE_DPLL_CORE_RESTORE_OFFSET 0x0034 +#define OMAP4430_CM_AUTOIDLE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0034) +#define OMAP4_CM_MPU_CLKSTCTRL_RESTORE_OFFSET 0x0038 +#define OMAP4430_CM_MPU_CLKSTCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0038) +#define OMAP4_CM_CM1_PROFILING_CLKCTRL_RESTORE_OFFSET 0x003c +#define OMAP4430_CM_CM1_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x003c) +#define OMAP4_CM_DYN_DEP_PRESCAL_RESTORE_OFFSET 0x0040 +#define OMAP4430_CM_DYN_DEP_PRESCAL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0040) + /* CM2 */ /* CM2.OCP_SOCKET_CM2 register offsets */ @@ -252,8 +288,6 @@ #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0068) #define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x006c #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x006c) -#define OMAP4_CM_EMU_OVERRIDE_DPLL_PER_OFFSET 0x0070 -#define OMAP4430_CM_EMU_OVERRIDE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0070) #define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET 0x0080 #define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0080) #define OMAP4_CM_IDLEST_DPLL_USB_OFFSET 0x0084 @@ -296,6 +330,8 @@ #define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0030) #define OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET 0x0038 #define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0038) +#define OMAP4_CM_ALWON_USBPHY_CLKCTRL_OFFSET 0x0040 +#define OMAP4430_CM_ALWON_USBPHY_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0040) /* CM2.CORE_CM2 register offsets */ #define OMAP4_CM_L3_1_CLKSTCTRL_OFFSET 0x0000 @@ -578,4 +614,54 @@ #define OMAP4430_CM_CEFUSE_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0000) #define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020 #define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0020) + +/* CM2.RESTORE_CM2 register offsets */ +#define OMAP4_CM_L3_1_CLKSTCTRL_RESTORE_OFFSET 0x0000 +#define OMAP4430_CM_L3_1_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0000) +#define OMAP4_CM_L3_2_CLKSTCTRL_RESTORE_OFFSET 0x0004 +#define OMAP4430_CM_L3_2_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0004) +#define OMAP4_CM_L4CFG_CLKSTCTRL_RESTORE_OFFSET 0x0008 +#define OMAP4430_CM_L4CFG_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0008) +#define OMAP4_CM_MEMIF_CLKSTCTRL_RESTORE_OFFSET 0x000c +#define OMAP4430_CM_MEMIF_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x000c) +#define OMAP4_CM_L4PER_CLKSTCTRL_RESTORE_OFFSET 0x0010 +#define OMAP4430_CM_L4PER_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0010) +#define OMAP4_CM_L3INIT_CLKSTCTRL_RESTORE_OFFSET 0x0014 +#define OMAP4430_CM_L3INIT_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0014) +#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_RESTORE_OFFSET 0x0018 +#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0018) +#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE_OFFSET 0x001c +#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x001c) +#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE_OFFSET 0x0020 +#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0020) +#define OMAP4_CM_CM2_PROFILING_CLKCTRL_RESTORE_OFFSET 0x0024 +#define OMAP4430_CM_CM2_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0024) +#define OMAP4_CM_D2D_STATICDEP_RESTORE_OFFSET 0x0028 +#define OMAP4430_CM_D2D_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0028) +#define OMAP4_CM_L3_1_DYNAMICDEP_RESTORE_OFFSET 0x002c +#define OMAP4430_CM_L3_1_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x002c) +#define OMAP4_CM_L3_2_DYNAMICDEP_RESTORE_OFFSET 0x0030 +#define OMAP4430_CM_L3_2_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0030) +#define OMAP4_CM_D2D_DYNAMICDEP_RESTORE_OFFSET 0x0034 +#define OMAP4430_CM_D2D_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0034) +#define OMAP4_CM_L4CFG_DYNAMICDEP_RESTORE_OFFSET 0x0038 +#define OMAP4430_CM_L4CFG_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0038) +#define OMAP4_CM_L4PER_DYNAMICDEP_RESTORE_OFFSET 0x003c +#define OMAP4430_CM_L4PER_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x003c) +#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_RESTORE_OFFSET 0x0040 +#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0040) +#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_RESTORE_OFFSET 0x0044 +#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0044) +#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_RESTORE_OFFSET 0x0048 +#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0048) +#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_RESTORE_OFFSET 0x004c +#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x004c) +#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_RESTORE_OFFSET 0x0050 +#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0050) +#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE_OFFSET 0x0054 +#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0054) +#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE_OFFSET 0x0058 +#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0058) +#define OMAP4_CM_SDMA_STATICDEP_RESTORE_OFFSET 0x005c +#define OMAP4430_CM_SDMA_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x005c) #endif diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h index fe8ef26..59839db 100644 --- a/arch/arm/mach-omap2/prm44xx.h +++ b/arch/arm/mach-omap2/prm44xx.h @@ -44,14 +44,12 @@ #define OMAP4430_PRM_IRQSTATUS_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0030) #define OMAP4_PRM_IRQENABLE_TESLA_OFFSET 0x0038 #define OMAP4430_PRM_IRQENABLE_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0038) -#define OMAP4_PRM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040 -#define OMAP4430_PRM_PRM_PROFILING_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0040) +#define OMAP4_CM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040 +#define OMAP4430_CM_PRM_PROFILING_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0040) /* PRM.CKGEN_PRM register offsets */ #define OMAP4_CM_ABE_DSS_SYS_CLKSEL_OFFSET 0x0000 #define OMAP4430_CM_ABE_DSS_SYS_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0000) -#define OMAP4_CM_DPLL_SYS_REF_CLKSEL_OFFSET 0x0004 -#define OMAP4430_CM_DPLL_SYS_REF_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0004) #define OMAP4_CM_L4_WKUP_CLKSEL_OFFSET 0x0008 #define OMAP4430_CM_L4_WKUP_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0008) #define OMAP4_CM_ABE_PLL_REF_CLKSEL_OFFSET 0x000c @@ -686,8 +684,8 @@ #define OMAP4430_PRM_LDO_ABB_IVA_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d8) #define OMAP4_PRM_LDO_ABB_IVA_CTRL_OFFSET 0x00dc #define OMAP4430_PRM_LDO_ABB_IVA_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00dc) -#define OMAP4_PRM_LDO_BANDGAP_CTRL_OFFSET 0x00e0 -#define OMAP4430_PRM_LDO_BANDGAP_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e0) +#define OMAP4_PRM_LDO_BANDGAP_SETUP_OFFSET 0x00e0 +#define OMAP4430_PRM_LDO_BANDGAP_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e0) #define OMAP4_PRM_DEVICE_OFF_CTRL_OFFSET 0x00e4 #define OMAP4430_PRM_DEVICE_OFF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e4) #define OMAP4_PRM_PHASE1_CNDP_OFFSET 0x00e8 @@ -698,6 +696,8 @@ #define OMAP4430_PRM_PHASE2B_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f0) #define OMAP4_PRM_MODEM_IF_CTRL_OFFSET 0x00f4 #define OMAP4430_PRM_MODEM_IF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f4) +#define OMAP4_PRM_VC_ERRST_OFFSET 0x00f8 +#define OMAP4430_PRM_VC_ERRST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f8) /* * PRCM_MPU @@ -715,6 +715,8 @@ /* PRCM_MPU.DEVICE_PRM register offsets */ #define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000 #define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0000) +#define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004 +#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0004) /* PRCM_MPU.CPU0 register offsets */ #define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000 -- cgit v1.1 From bb722f33e233c980159f0ac5560d530eb5dfdd0f Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Mon, 27 Sep 2010 14:02:56 -0600 Subject: OMAP4: powerdomain: Update DSS logic state for ES2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit DSS on ES2 supports only OSWR, hence remove the support for CSWR from the powerdomain framework. Signed-off-by: Rajendra Nayak Signed-off-by: Benoît Cousson Signed-off-by: Paul Walmsley Cc: Kevin Hilman --- arch/arm/mach-omap2/powerdomains44xx.h | 2 +- arch/arm/plat-omap/include/plat/powerdomain.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/powerdomains44xx.h b/arch/arm/mach-omap2/powerdomains44xx.h index c721951..9c01b55 100644 --- a/arch/arm/mach-omap2/powerdomains44xx.h +++ b/arch/arm/mach-omap2/powerdomains44xx.h @@ -98,7 +98,7 @@ static struct powerdomain dss_44xx_pwrdm = { .prcm_offs = OMAP4430_PRM_DSS_MOD, .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), .pwrsts = PWRSTS_OFF_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, + .pwrsts_logic_ret = PWRSTS_OFF, .banks = 1, .pwrsts_mem_ret = { [0] = PWRDM_POWER_OFF, /* dss_mem */ diff --git a/arch/arm/plat-omap/include/plat/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h index fb6ec74..3ea7220 100644 --- a/arch/arm/plat-omap/include/plat/powerdomain.h +++ b/arch/arm/plat-omap/include/plat/powerdomain.h @@ -32,6 +32,7 @@ /* Powerdomain allowable state bitfields */ #define PWRSTS_ON (1 << PWRDM_POWER_ON) +#define PWRSTS_OFF (1 << PWRDM_POWER_OFF) #define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \ (1 << PWRDM_POWER_ON)) -- cgit v1.1 From 0edc9e858222ca8fd685756f0d7e546633c39ff0 Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Mon, 27 Sep 2010 14:02:56 -0600 Subject: OMAP4: clocks: Fix ES2 clock issues Fix a few OMAP4430 clock tree problems after the recent manual merge of the various ES2 clock patches: - usim optional clock and its parent had the same name, rename the parent usim_fclk -> usim_ck - OPTFCLKEN_CLK32K is not handled anymore by the USBPHYOCP2SCP module in ES2 Create a new clock that belongs to CM_ALWON_USBPHY_CLKCTRL register This patch depends on some of the PRCM macro updates from Rajendra. Signed-off-by: Benoit Cousson [paul@pwsan.com: tweaked patch description] Signed-off-by: Paul Walmsley Cc: Rajendra Nayak --- arch/arm/mach-omap2/clock44xx_data.c | 88 ++++++++++++++++++++++-------------- 1 file changed, 55 insertions(+), 33 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index b94f21a..67fac44 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -2037,23 +2037,23 @@ static struct clk mmc5_fck = { .recalc = &followparent_recalc, }; -static struct clk ocp2scp_usb_phy_clk32k = { - .name = "ocp2scp_usb_phy_clk32k", +static struct clk ocp2scp_usb_phy_phy_48m = { + .name = "ocp2scp_usb_phy_phy_48m", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_CLK32K_SHIFT, + .enable_bit = OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, .clkdm_name = "l3_init_clkdm", - .parent = &sys_32k_ck, + .parent = &func_48m_fclk, .recalc = &followparent_recalc, }; -static struct clk ocp2scp_usb_phy_phy_48m = { - .name = "ocp2scp_usb_phy_phy_48m", +static struct clk ocp2scp_usb_phy_ick = { + .name = "ocp2scp_usb_phy_ick", .ops = &clkops_omap2_dflt, .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, - .enable_bit = OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, + .enable_bit = OMAP4430_MODULEMODE_HWCTRL, .clkdm_name = "l3_init_clkdm", - .parent = &func_48m_fclk, + .parent = &l4_div_ck, .recalc = &followparent_recalc, }; @@ -2599,6 +2599,16 @@ static struct clk usb_otg_hs_ick = { .recalc = &followparent_recalc, }; +static struct clk usb_phy_cm_clk32k = { + .name = "usb_phy_cm_clk32k", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_ALWON_USBPHY_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_CLK32K_SHIFT, + .clkdm_name = "l4_ao_clkdm", + .parent = &sys_32k_ck, + .recalc = &followparent_recalc, +}; + static struct clk usb_tll_hs_usb_ch2_clk = { .name = "usb_tll_hs_usb_ch2_clk", .ops = &clkops_omap2_dflt, @@ -2639,6 +2649,39 @@ static struct clk usb_tll_hs_ick = { .recalc = &followparent_recalc, }; +static const struct clksel_rate div2_14to18_rates[] = { + { .div = 14, .val = 0, .flags = RATE_IN_4430 }, + { .div = 18, .val = 1, .flags = RATE_IN_4430 }, + { .div = 0 }, +}; + +static const struct clksel usim_fclk_div[] = { + { .parent = &dpll_per_m4_ck, .rates = div2_14to18_rates }, + { .parent = NULL }, +}; + +static struct clk usim_ck = { + .name = "usim_ck", + .parent = &dpll_per_m4_ck, + .clksel = usim_fclk_div, + .clksel_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, + .clksel_mask = OMAP4430_CLKSEL_DIV_MASK, + .ops = &clkops_null, + .recalc = &omap2_clksel_recalc, + .round_rate = &omap2_clksel_round_rate, + .set_rate = &omap2_clksel_set_rate, +}; + +static struct clk usim_fclk = { + .name = "usim_fclk", + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, + .enable_bit = OMAP4430_OPTFCLKEN_FCLK_SHIFT, + .clkdm_name = "l4_wkup_clkdm", + .parent = &usim_ck, + .recalc = &followparent_recalc, +}; + static struct clk usim_fck = { .name = "usim_fck", .ops = &clkops_omap2_dflt, @@ -2704,29 +2747,6 @@ static struct clk trace_clk_div_ck = { .set_rate = &omap2_clksel_set_rate, }; -static const struct clksel_rate div2_14to18_rates[] = { - { .div = 14, .val = 0, .flags = RATE_IN_4430 }, - { .div = 18, .val = 1, .flags = RATE_IN_4430 }, - { .div = 0 }, -}; - -static const struct clksel usim_fclk_div[] = { - { .parent = &dpll_per_m4_ck, .rates = div2_14to18_rates }, - { .parent = NULL }, -}; - -static struct clk usim_fclk = { - .name = "usim_fclk", - .parent = &dpll_per_m4_ck, - .clksel = usim_fclk_div, - .clksel_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, - .clksel_mask = OMAP4430_CLKSEL_DIV_MASK, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - /* * clkdev */ @@ -2883,8 +2903,8 @@ static struct omap_clk omap44xx_clks[] = { CLK("mmci-omap-hs.2", "fck", &mmc3_fck, CK_443X), CLK("mmci-omap-hs.3", "fck", &mmc4_fck, CK_443X), CLK("mmci-omap-hs.4", "fck", &mmc5_fck, CK_443X), - CLK(NULL, "ocp2scp_usb_phy_clk32k", &ocp2scp_usb_phy_clk32k, CK_443X), CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X), + CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X), CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X), CLK("omap_rng", "ick", &rng_ick, CK_443X), CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X), @@ -2931,16 +2951,18 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X), CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X), CLK("musb_hdrc", "ick", &usb_otg_hs_ick, CK_443X), + CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_443X), CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X), CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X), CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X), CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X), + CLK(NULL, "usim_ck", &usim_ck, CK_443X), + CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), CLK(NULL, "usim_fck", &usim_fck, CK_443X), CLK("omap_wdt", "fck", &wd_timer2_fck, CK_443X), CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X), CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), - CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X), CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X), CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X), -- cgit v1.1 From 0c3492467c99f3d0d83a48012ee6e672b016759c Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Mon, 27 Sep 2010 14:02:57 -0600 Subject: omap4: control: Add ctrl_pad_base to omap_globals On omap4 control module is divided in four IP blocks. - CTRL_MODULE_CORE 0x4a002000 - CTRL_MODULE_PAD_CORE 0x4a100000 - CTRL_MODULE_WKUP 0x4a30c000 - CTRL_MODULE_PAD_WKUP 0x4a31e000 Addressing all the modules with single base address is not possible considering 16 bit offsets. The mux code manages the pad core and pad wakeup related base address inside the mux framework. For other usage only control core and control pad bases are necessary. So this patch maps only needed pad control base address which is used by device drivers and infrastructure code The main control core base is still kept same in this patch to keep git-bisect working. This will be fixed in the relevant patch in this series. Signed-off-by: Benoit Cousson Signed-off-by: Santosh Shilimkar Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/control.c | 7 +++++++ arch/arm/plat-omap/common.c | 3 ++- arch/arm/plat-omap/include/plat/common.h | 1 + 3 files changed, 10 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index a8d20ee..99c0eb6 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -25,6 +25,7 @@ #include "sdrc.h" static void __iomem *omap2_ctrl_base; +static void __iomem *omap4_ctrl_pad_base; #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) struct omap3_scratchpad { @@ -145,6 +146,12 @@ void __init omap2_set_globals_control(struct omap_globals *omap2_globals) omap2_ctrl_base = ioremap(omap2_globals->ctrl, SZ_4K); WARN_ON(!omap2_ctrl_base); } + + /* Static mapping, never released */ + if (omap2_globals->ctrl_pad) { + omap4_ctrl_pad_base = ioremap(omap2_globals->ctrl_pad, SZ_4K); + WARN_ON(!omap4_ctrl_pad_base); + } } void __iomem *omap_ctrl_base_get(void) diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c index 3008e71..480718b 100644 --- a/arch/arm/plat-omap/common.c +++ b/arch/arm/plat-omap/common.c @@ -336,7 +336,8 @@ void __init omap3_map_io(void) static struct omap_globals omap4_globals = { .class = OMAP443X_CLASS, .tap = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE), - .ctrl = OMAP443X_CTRL_BASE, + .ctrl = OMAP443X_CTRL_BASE, /* FIXME: Move this to control core */ + .ctrl_pad = OMAP443X_CTRL_BASE, .prm = OMAP4430_PRM_BASE, .cm = OMAP4430_CM_BASE, .cm2 = OMAP4430_CM2_BASE, diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h index 9776b41..7cd0180 100644 --- a/arch/arm/plat-omap/include/plat/common.h +++ b/arch/arm/plat-omap/include/plat/common.h @@ -47,6 +47,7 @@ struct omap_globals { unsigned long sdrc; /* SDRAM Controller */ unsigned long sms; /* SDRAM Memory Scheduler */ unsigned long ctrl; /* System Control Module */ + unsigned long ctrl_pad; /* PAD Control Module */ unsigned long prm; /* Power and Reset Management */ unsigned long cm; /* Clock Management */ unsigned long cm2; -- cgit v1.1 From 70ba71a25e02ef7b8796723c8615955620e465ff Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Mon, 27 Sep 2010 14:02:57 -0600 Subject: omap4: control: Add accessor api's for pad control module On OMAP4 control pad are not addressable from control core base. So the common omap_ctrl_read/write APIs breaks Hence export separate APIs to manage the omap4 pad control registers. This APIs will work only for OMAP4 Signed-off-by: Santosh Shilimkar Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/control.c | 18 ++++++++++++++++++ arch/arm/plat-omap/include/plat/control.h | 4 ++++ 2 files changed, 22 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index 99c0eb6..8b3c469 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -138,6 +138,7 @@ static struct omap3_control_regs control_context; #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ #define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg)) +#define OMAP4_CTRL_PAD_REGADDR(reg) (omap4_ctrl_pad_base + (reg)) void __init omap2_set_globals_control(struct omap_globals *omap2_globals) { @@ -189,6 +190,23 @@ void omap_ctrl_writel(u32 val, u16 offset) __raw_writel(val, OMAP_CTRL_REGADDR(offset)); } +/* + * On OMAP4 control pad are not addressable from control + * core base. So the common omap_ctrl_read/write APIs breaks + * Hence export separate APIs to manage the omap4 pad control + * registers. This APIs will work only for OMAP4 + */ + +u32 omap4_ctrl_pad_readl(u16 offset) +{ + return __raw_readl(OMAP4_CTRL_PAD_REGADDR(offset)); +} + +void omap4_ctrl_pad_writel(u32 val, u16 offset) +{ + __raw_writel(val, OMAP4_CTRL_PAD_REGADDR(offset)); +} + #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) /* * Clears the scratchpad contents in case of cold boot- diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/plat-omap/include/plat/control.h index 131bf40..2916b7e 100644 --- a/arch/arm/plat-omap/include/plat/control.h +++ b/arch/arm/plat-omap/include/plat/control.h @@ -354,9 +354,11 @@ extern void __iomem *omap_ctrl_base_get(void); extern u8 omap_ctrl_readb(u16 offset); extern u16 omap_ctrl_readw(u16 offset); extern u32 omap_ctrl_readl(u16 offset); +extern u32 omap4_ctrl_pad_readl(u16 offset); extern void omap_ctrl_writeb(u8 val, u16 offset); extern void omap_ctrl_writew(u16 val, u16 offset); extern void omap_ctrl_writel(u32 val, u16 offset); +extern void omap4_ctrl_pad_writel(u32 val, u16 offset); extern void omap3_save_scratchpad_contents(void); extern void omap3_clear_scratchpad_contents(void); @@ -371,9 +373,11 @@ extern void omap3_control_restore_context(void); #define omap_ctrl_readb(x) 0 #define omap_ctrl_readw(x) 0 #define omap_ctrl_readl(x) 0 +#define omap4_ctrl_pad_readl(x) 0 #define omap_ctrl_writeb(x, y) WARN_ON(1) #define omap_ctrl_writew(x, y) WARN_ON(1) #define omap_ctrl_writel(x, y) WARN_ON(1) +#define omap4_ctrl_pad_writel(x, y) WARN_ON(1) #endif #endif /* __ASSEMBLY__ */ -- cgit v1.1 From 802edcb7a9227ad98e902ad4406c4b99ddf18c13 Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Mon, 27 Sep 2010 14:02:58 -0600 Subject: omap4: control: Add the register definition headers On OMAP4, control module is divided into 4 separate IPs - OMAP44XX_CTRL_MODULE_CORE - OMAP44XX_CTRL_MODULE_PAD_CORE - OMAP44XX_CTRL_MODULE_WKUP - OMAP44XX_CTRL_MODULE_PAD_WKUP This patch adds all the omap4 control module register data and includes them in the common control.h The register data is autogenerated from the codebase thanks to Benoit Cousson efforts Signed-off-by: Benoit Cousson Signed-off-by: Santosh Shilimkar Signed-off-by: Paul Walmsley --- .../include/mach/ctrl_module_core_44xx.h | 391 ++++++ .../include/mach/ctrl_module_pad_core_44xx.h | 1409 ++++++++++++++++++++ .../include/mach/ctrl_module_pad_wkup_44xx.h | 236 ++++ .../include/mach/ctrl_module_wkup_44xx.h | 92 ++ arch/arm/plat-omap/include/plat/control.h | 4 + 5 files changed, 2132 insertions(+) create mode 100644 arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h create mode 100644 arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h create mode 100644 arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h create mode 100644 arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h (limited to 'arch') diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h new file mode 100644 index 0000000..2f7ac70 --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h @@ -0,0 +1,391 @@ +/* + * OMAP44xx CTRL_MODULE_CORE registers and bitfields + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * + * Benoit Cousson (b-cousson@ti.com) + * Santosh Shilimkar (santosh.shilimkar@ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H +#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H + + +/* Base address */ +#define OMAP4_CTRL_MODULE_CORE 0x4a002000 + +/* Registers offset */ +#define OMAP4_CTRL_MODULE_CORE_IP_REVISION 0x0000 +#define OMAP4_CTRL_MODULE_CORE_IP_HWINFO 0x0004 +#define OMAP4_CTRL_MODULE_CORE_IP_SYSCONFIG 0x0010 +#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_0 0x0200 +#define OMAP4_CTRL_MODULE_CORE_ID_CODE 0x0204 +#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_1 0x0208 +#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_2 0x020c +#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_3 0x0210 +#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_0 0x0214 +#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1 0x0218 +#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_USB_CONF 0x021c +#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_VDD_WKUP 0x0228 +#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_BGAP 0x0260 +#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_0 0x0264 +#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_1 0x0268 +#define OMAP4_CTRL_MODULE_CORE_STATUS 0x02c4 +#define OMAP4_CTRL_MODULE_CORE_DEV_CONF 0x0300 +#define OMAP4_CTRL_MODULE_CORE_LDOVBB_IVA_VOLTAGE_CTRL 0x0314 +#define OMAP4_CTRL_MODULE_CORE_LDOVBB_MPU_VOLTAGE_CTRL 0x0318 +#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_IVA_VOLTAGE_CTRL 0x0320 +#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_MPU_VOLTAGE_CTRL 0x0324 +#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_CORE_VOLTAGE_CTRL 0x0328 +#define OMAP4_CTRL_MODULE_CORE_TEMP_SENSOR 0x032c +#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_0 0x0330 +#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_1 0x0334 +#define OMAP4_CTRL_MODULE_CORE_USBOTGHS_CONTROL 0x033c +#define OMAP4_CTRL_MODULE_CORE_DSS_CONTROL 0x0340 +#define OMAP4_CTRL_MODULE_CORE_HWOBS_CONTROL 0x0350 +#define OMAP4_CTRL_MODULE_CORE_DEBOBS_FINAL_MUX_SEL 0x0400 +#define OMAP4_CTRL_MODULE_CORE_DEBOBS_MMR_MPU 0x0408 +#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL0 0x042c +#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL1 0x0430 +#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL2 0x0434 +#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL3 0x0438 +#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL0 0x0440 +#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL1 0x0444 +#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL2 0x0448 +#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_FREQLOCK_SEL 0x044c +#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_TINITZ_SEL 0x0450 +#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_PHASELOCK_SEL 0x0454 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_0 0x0480 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_1 0x0484 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_2 0x0488 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_3 0x048c +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_4 0x0490 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_5 0x0494 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_6 0x0498 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_7 0x049c +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_8 0x04a0 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_9 0x04a4 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_10 0x04a8 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_11 0x04ac +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_12 0x04b0 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_13 0x04b4 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_14 0x04b8 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_15 0x04bc +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_16 0x04c0 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_17 0x04c4 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_18 0x04c8 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_19 0x04cc +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_20 0x04d0 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_21 0x04d4 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_22 0x04d8 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_23 0x04dc +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_24 0x04e0 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_25 0x04e4 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_26 0x04e8 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_27 0x04ec +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_28 0x04f0 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_29 0x04f4 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_30 0x04f8 +#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_31 0x04fc + +/* Registers shifts and masks */ + +/* IP_REVISION */ +#define OMAP4_IP_REV_SCHEME_SHIFT 30 +#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30) +#define OMAP4_IP_REV_FUNC_SHIFT 16 +#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16) +#define OMAP4_IP_REV_RTL_SHIFT 11 +#define OMAP4_IP_REV_RTL_MASK (0x1f << 11) +#define OMAP4_IP_REV_MAJOR_SHIFT 8 +#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8) +#define OMAP4_IP_REV_CUSTOM_SHIFT 6 +#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6) +#define OMAP4_IP_REV_MINOR_SHIFT 0 +#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0) + +/* IP_HWINFO */ +#define OMAP4_IP_HWINFO_SHIFT 0 +#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0) + +/* IP_SYSCONFIG */ +#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2 +#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2) + +/* STD_FUSE_DIE_ID_0 */ +#define OMAP4_STD_FUSE_DIE_ID_0_SHIFT 0 +#define OMAP4_STD_FUSE_DIE_ID_0_MASK (0xffffffff << 0) + +/* ID_CODE */ +#define OMAP4_STD_FUSE_IDCODE_SHIFT 0 +#define OMAP4_STD_FUSE_IDCODE_MASK (0xffffffff << 0) + +/* STD_FUSE_DIE_ID_1 */ +#define OMAP4_STD_FUSE_DIE_ID_1_SHIFT 0 +#define OMAP4_STD_FUSE_DIE_ID_1_MASK (0xffffffff << 0) + +/* STD_FUSE_DIE_ID_2 */ +#define OMAP4_STD_FUSE_DIE_ID_2_SHIFT 0 +#define OMAP4_STD_FUSE_DIE_ID_2_MASK (0xffffffff << 0) + +/* STD_FUSE_DIE_ID_3 */ +#define OMAP4_STD_FUSE_DIE_ID_3_SHIFT 0 +#define OMAP4_STD_FUSE_DIE_ID_3_MASK (0xffffffff << 0) + +/* STD_FUSE_PROD_ID_0 */ +#define OMAP4_STD_FUSE_PROD_ID_0_SHIFT 0 +#define OMAP4_STD_FUSE_PROD_ID_0_MASK (0xffffffff << 0) + +/* STD_FUSE_PROD_ID_1 */ +#define OMAP4_STD_FUSE_PROD_ID_1_SHIFT 0 +#define OMAP4_STD_FUSE_PROD_ID_1_MASK (0xffffffff << 0) + +/* STD_FUSE_USB_CONF */ +#define OMAP4_USB_PROD_ID_SHIFT 16 +#define OMAP4_USB_PROD_ID_MASK (0xffff << 16) +#define OMAP4_USB_VENDOR_ID_SHIFT 0 +#define OMAP4_USB_VENDOR_ID_MASK (0xffff << 0) + +/* STD_FUSE_OPP_VDD_WKUP */ +#define OMAP4_STD_FUSE_OPP_VDD_WKUP_SHIFT 0 +#define OMAP4_STD_FUSE_OPP_VDD_WKUP_MASK (0xffffffff << 0) + +/* STD_FUSE_OPP_BGAP */ +#define OMAP4_STD_FUSE_OPP_BGAP_SHIFT 0 +#define OMAP4_STD_FUSE_OPP_BGAP_MASK (0xffffffff << 0) + +/* STD_FUSE_OPP_DPLL_0 */ +#define OMAP4_STD_FUSE_OPP_DPLL_0_SHIFT 0 +#define OMAP4_STD_FUSE_OPP_DPLL_0_MASK (0xffffffff << 0) + +/* STD_FUSE_OPP_DPLL_1 */ +#define OMAP4_STD_FUSE_OPP_DPLL_1_SHIFT 0 +#define OMAP4_STD_FUSE_OPP_DPLL_1_MASK (0xffffffff << 0) + +/* STATUS */ +#define OMAP4_ATTILA_CONF_SHIFT 11 +#define OMAP4_ATTILA_CONF_MASK (0x3 << 11) +#define OMAP4_DEVICE_TYPE_SHIFT 8 +#define OMAP4_DEVICE_TYPE_MASK (0x7 << 8) +#define OMAP4_SYS_BOOT_SHIFT 0 +#define OMAP4_SYS_BOOT_MASK (0xff << 0) + +/* DEV_CONF */ +#define OMAP4_DEV_CONF_SHIFT 1 +#define OMAP4_DEV_CONF_MASK (0x7fffffff << 1) +#define OMAP4_USBPHY_PD_SHIFT 0 +#define OMAP4_USBPHY_PD_MASK (1 << 0) + +/* LDOVBB_IVA_VOLTAGE_CTRL */ +#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_SHIFT 26 +#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_MASK (1 << 26) +#define OMAP4_LDOVBBIVA_RBB_VSET_IN_SHIFT 21 +#define OMAP4_LDOVBBIVA_RBB_VSET_IN_MASK (0x1f << 21) +#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_SHIFT 16 +#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_MASK (0x1f << 16) +#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_SHIFT 10 +#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_MASK (1 << 10) +#define OMAP4_LDOVBBIVA_FBB_VSET_IN_SHIFT 5 +#define OMAP4_LDOVBBIVA_FBB_VSET_IN_MASK (0x1f << 5) +#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_SHIFT 0 +#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_MASK (0x1f << 0) + +/* LDOVBB_MPU_VOLTAGE_CTRL */ +#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_SHIFT 26 +#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_MASK (1 << 26) +#define OMAP4_LDOVBBMPU_RBB_VSET_IN_SHIFT 21 +#define OMAP4_LDOVBBMPU_RBB_VSET_IN_MASK (0x1f << 21) +#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_SHIFT 16 +#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_MASK (0x1f << 16) +#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_SHIFT 10 +#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_MASK (1 << 10) +#define OMAP4_LDOVBBMPU_FBB_VSET_IN_SHIFT 5 +#define OMAP4_LDOVBBMPU_FBB_VSET_IN_MASK (0x1f << 5) +#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_SHIFT 0 +#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_MASK (0x1f << 0) + +/* LDOSRAM_IVA_VOLTAGE_CTRL */ +#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_SHIFT 26 +#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_MASK (1 << 26) +#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_SHIFT 21 +#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_MASK (0x1f << 21) +#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_SHIFT 16 +#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_MASK (0x1f << 16) +#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_SHIFT 10 +#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_MASK (1 << 10) +#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_SHIFT 5 +#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_MASK (0x1f << 5) +#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_SHIFT 0 +#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_MASK (0x1f << 0) + +/* LDOSRAM_MPU_VOLTAGE_CTRL */ +#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_SHIFT 26 +#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_MASK (1 << 26) +#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_SHIFT 21 +#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_MASK (0x1f << 21) +#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_SHIFT 16 +#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_MASK (0x1f << 16) +#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_SHIFT 10 +#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_MASK (1 << 10) +#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_SHIFT 5 +#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_MASK (0x1f << 5) +#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_SHIFT 0 +#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_MASK (0x1f << 0) + +/* LDOSRAM_CORE_VOLTAGE_CTRL */ +#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_SHIFT 26 +#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_MASK (1 << 26) +#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_SHIFT 21 +#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_MASK (0x1f << 21) +#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_SHIFT 16 +#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_MASK (0x1f << 16) +#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_SHIFT 10 +#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_MASK (1 << 10) +#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_SHIFT 5 +#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_MASK (0x1f << 5) +#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_SHIFT 0 +#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_MASK (0x1f << 0) + +/* TEMP_SENSOR */ +#define OMAP4_BGAP_TEMPSOFF_SHIFT 12 +#define OMAP4_BGAP_TEMPSOFF_MASK (1 << 12) +#define OMAP4_BGAP_TSHUT_SHIFT 11 +#define OMAP4_BGAP_TSHUT_MASK (1 << 11) +#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_SHIFT 10 +#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_MASK (1 << 10) +#define OMAP4_BGAP_TEMP_SENSOR_SOC_SHIFT 9 +#define OMAP4_BGAP_TEMP_SENSOR_SOC_MASK (1 << 9) +#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_SHIFT 8 +#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_MASK (1 << 8) +#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_SHIFT 0 +#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_MASK (0xff << 0) + +/* DPLL_NWELL_TRIM_0 */ +#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_SHIFT 29 +#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_MASK (1 << 29) +#define OMAP4_DPLL_ABE_NWELL_TRIM_SHIFT 24 +#define OMAP4_DPLL_ABE_NWELL_TRIM_MASK (0x1f << 24) +#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_SHIFT 23 +#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_MASK (1 << 23) +#define OMAP4_DPLL_PER_NWELL_TRIM_SHIFT 18 +#define OMAP4_DPLL_PER_NWELL_TRIM_MASK (0x1f << 18) +#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_SHIFT 17 +#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_MASK (1 << 17) +#define OMAP4_DPLL_CORE_NWELL_TRIM_SHIFT 12 +#define OMAP4_DPLL_CORE_NWELL_TRIM_MASK (0x1f << 12) +#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_SHIFT 11 +#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_MASK (1 << 11) +#define OMAP4_DPLL_IVA_NWELL_TRIM_SHIFT 6 +#define OMAP4_DPLL_IVA_NWELL_TRIM_MASK (0x1f << 6) +#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_SHIFT 5 +#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_MASK (1 << 5) +#define OMAP4_DPLL_MPU_NWELL_TRIM_SHIFT 0 +#define OMAP4_DPLL_MPU_NWELL_TRIM_MASK (0x1f << 0) + +/* DPLL_NWELL_TRIM_1 */ +#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_SHIFT 29 +#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_MASK (1 << 29) +#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_SHIFT 24 +#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MASK (0x1f << 24) +#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_SHIFT 23 +#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_MASK (1 << 23) +#define OMAP4_DPLL_USB_NWELL_TRIM_SHIFT 18 +#define OMAP4_DPLL_USB_NWELL_TRIM_MASK (0x1f << 18) +#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_SHIFT 17 +#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_MASK (1 << 17) +#define OMAP4_DPLL_HDMI_NWELL_TRIM_SHIFT 12 +#define OMAP4_DPLL_HDMI_NWELL_TRIM_MASK (0x1f << 12) +#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_SHIFT 11 +#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_MASK (1 << 11) +#define OMAP4_DPLL_DSI2_NWELL_TRIM_SHIFT 6 +#define OMAP4_DPLL_DSI2_NWELL_TRIM_MASK (0x1f << 6) +#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_SHIFT 5 +#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_MASK (1 << 5) +#define OMAP4_DPLL_DSI1_NWELL_TRIM_SHIFT 0 +#define OMAP4_DPLL_DSI1_NWELL_TRIM_MASK (0x1f << 0) + +/* USBOTGHS_CONTROL */ +#define OMAP4_DISCHRGVBUS_SHIFT 8 +#define OMAP4_DISCHRGVBUS_MASK (1 << 8) +#define OMAP4_CHRGVBUS_SHIFT 7 +#define OMAP4_CHRGVBUS_MASK (1 << 7) +#define OMAP4_DRVVBUS_SHIFT 6 +#define OMAP4_DRVVBUS_MASK (1 << 6) +#define OMAP4_IDPULLUP_SHIFT 5 +#define OMAP4_IDPULLUP_MASK (1 << 5) +#define OMAP4_IDDIG_SHIFT 4 +#define OMAP4_IDDIG_MASK (1 << 4) +#define OMAP4_SESSEND_SHIFT 3 +#define OMAP4_SESSEND_MASK (1 << 3) +#define OMAP4_VBUSVALID_SHIFT 2 +#define OMAP4_VBUSVALID_MASK (1 << 2) +#define OMAP4_BVALID_SHIFT 1 +#define OMAP4_BVALID_MASK (1 << 1) +#define OMAP4_AVALID_SHIFT 0 +#define OMAP4_AVALID_MASK (1 << 0) + +/* DSS_CONTROL */ +#define OMAP4_DSS_MUX6_SELECT_SHIFT 0 +#define OMAP4_DSS_MUX6_SELECT_MASK (1 << 0) + +/* HWOBS_CONTROL */ +#define OMAP4_HWOBS_CLKDIV_SEL_SHIFT 3 +#define OMAP4_HWOBS_CLKDIV_SEL_MASK (0x1f << 3) +#define OMAP4_HWOBS_ALL_ZERO_MODE_SHIFT 2 +#define OMAP4_HWOBS_ALL_ZERO_MODE_MASK (1 << 2) +#define OMAP4_HWOBS_ALL_ONE_MODE_SHIFT 1 +#define OMAP4_HWOBS_ALL_ONE_MODE_MASK (1 << 1) +#define OMAP4_HWOBS_MACRO_ENABLE_SHIFT 0 +#define OMAP4_HWOBS_MACRO_ENABLE_MASK (1 << 0) + +/* DEBOBS_FINAL_MUX_SEL */ +#define OMAP4_SELECT_SHIFT 0 +#define OMAP4_SELECT_MASK (0xffffffff << 0) + +/* DEBOBS_MMR_MPU */ +#define OMAP4_SELECT_DEBOBS_MMR_MPU_SHIFT 0 +#define OMAP4_SELECT_DEBOBS_MMR_MPU_MASK (0xf << 0) + +/* CONF_SDMA_REQ_SEL0 */ +#define OMAP4_MULT_SHIFT 0 +#define OMAP4_MULT_MASK (0x7f << 0) + +/* CONF_CLK_SEL0 */ +#define OMAP4_MULT_CONF_CLK_SEL0_SHIFT 0 +#define OMAP4_MULT_CONF_CLK_SEL0_MASK (0x7 << 0) + +/* CONF_CLK_SEL1 */ +#define OMAP4_MULT_CONF_CLK_SEL1_SHIFT 0 +#define OMAP4_MULT_CONF_CLK_SEL1_MASK (0x7 << 0) + +/* CONF_CLK_SEL2 */ +#define OMAP4_MULT_CONF_CLK_SEL2_SHIFT 0 +#define OMAP4_MULT_CONF_CLK_SEL2_MASK (0x7 << 0) + +/* CONF_DPLL_FREQLOCK_SEL */ +#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_SHIFT 0 +#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_MASK (0x7 << 0) + +/* CONF_DPLL_TINITZ_SEL */ +#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_SHIFT 0 +#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_MASK (0x7 << 0) + +/* CONF_DPLL_PHASELOCK_SEL */ +#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_SHIFT 0 +#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_MASK (0x7 << 0) + +/* CONF_DEBUG_SEL_TST_0 */ +#define OMAP4_MODE_SHIFT 0 +#define OMAP4_MODE_MASK (0xf << 0) + +#endif diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h new file mode 100644 index 0000000..c88420d --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h @@ -0,0 +1,1409 @@ +/* + * OMAP44xx CTRL_MODULE_PAD_CORE registers and bitfields + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * + * Benoit Cousson (b-cousson@ti.com) + * Santosh Shilimkar (santosh.shilimkar@ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H +#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H + + +/* Base address */ +#define OMAP4_CTRL_MODULE_PAD_CORE 0x4a100000 + +/* Registers offset */ +#define OMAP4_CTRL_MODULE_PAD_CORE_IP_REVISION 0x0000 +#define OMAP4_CTRL_MODULE_PAD_CORE_IP_HWINFO 0x0004 +#define OMAP4_CTRL_MODULE_PAD_CORE_IP_SYSCONFIG 0x0010 +#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_0 0x01d8 +#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_1 0x01dc +#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_2 0x01e0 +#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_3 0x01e4 +#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_4 0x01e8 +#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_5 0x01ec +#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_6 0x01f0 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_GLOBAL 0x05a0 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_MODE 0x05a4 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_0 0x05a8 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_1 0x05ac +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_0 0x05b0 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_1 0x05b4 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_0 0x05b8 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_1 0x05bc +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_2 0x05c0 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USBB_HSIC 0x05c4 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SLIMBUS 0x05c8 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE 0x0600 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_0 0x0604 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX 0x0608 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_AVDAC 0x060c +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDMI_TX_PHY 0x0610 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC2 0x0614 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY 0x0618 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP 0x061c +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB2PHYCORE 0x0620 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1 0x0624 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1 0x0628 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HSI 0x062c +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB 0x0630 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDQ 0x0634 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_0 0x0638 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_1 0x063c +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_2 0x0640 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_3 0x0644 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_0 0x0648 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_1 0x064c +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_2 0x0650 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_3 0x0654 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_BUS_HOLD 0x0658 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_C2C 0x065c +#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_RW 0x0660 +#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R 0x0664 +#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R_C0 0x0668 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_1 0x0700 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_2 0x0704 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_3 0x0708 +#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_4 0x070c + +/* Registers shifts and masks */ + +/* IP_REVISION */ +#define OMAP4_IP_REV_SCHEME_SHIFT 30 +#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30) +#define OMAP4_IP_REV_FUNC_SHIFT 16 +#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16) +#define OMAP4_IP_REV_RTL_SHIFT 11 +#define OMAP4_IP_REV_RTL_MASK (0x1f << 11) +#define OMAP4_IP_REV_MAJOR_SHIFT 8 +#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8) +#define OMAP4_IP_REV_CUSTOM_SHIFT 6 +#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6) +#define OMAP4_IP_REV_MINOR_SHIFT 0 +#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0) + +/* IP_HWINFO */ +#define OMAP4_IP_HWINFO_SHIFT 0 +#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0) + +/* IP_SYSCONFIG */ +#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2 +#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2) + +/* PADCONF_WAKEUPEVENT_0 */ +#define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_SHIFT 31 +#define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 31) +#define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_SHIFT 30 +#define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_MASK (1 << 30) +#define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_SHIFT 29 +#define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_MASK (1 << 29) +#define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_SHIFT 28 +#define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_MASK (1 << 28) +#define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_SHIFT 27 +#define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_MASK (1 << 27) +#define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_SHIFT 26 +#define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_MASK (1 << 26) +#define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_SHIFT 25 +#define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_MASK (1 << 25) +#define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_SHIFT 24 +#define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_MASK (1 << 24) +#define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_SHIFT 23 +#define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_MASK (1 << 23) +#define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_SHIFT 22 +#define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_MASK (1 << 22) +#define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_SHIFT 21 +#define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_MASK (1 << 21) +#define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_SHIFT 20 +#define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_MASK (1 << 20) +#define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_SHIFT 19 +#define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_MASK (1 << 19) +#define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_SHIFT 18 +#define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_MASK (1 << 18) +#define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_SHIFT 17 +#define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_MASK (1 << 17) +#define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_SHIFT 16 +#define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_MASK (1 << 16) +#define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_SHIFT 15 +#define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_MASK (1 << 15) +#define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_SHIFT 14 +#define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_MASK (1 << 14) +#define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_SHIFT 13 +#define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_MASK (1 << 13) +#define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_SHIFT 12 +#define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_MASK (1 << 12) +#define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_SHIFT 11 +#define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_MASK (1 << 11) +#define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_SHIFT 10 +#define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_MASK (1 << 10) +#define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_SHIFT 9 +#define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_MASK (1 << 9) +#define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_SHIFT 8 +#define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_MASK (1 << 8) +#define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_SHIFT 7 +#define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_MASK (1 << 7) +#define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_SHIFT 6 +#define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_MASK (1 << 6) +#define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_SHIFT 5 +#define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_MASK (1 << 5) +#define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_SHIFT 4 +#define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_MASK (1 << 4) +#define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_SHIFT 3 +#define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_MASK (1 << 3) +#define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_SHIFT 2 +#define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_MASK (1 << 2) +#define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_SHIFT 1 +#define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_MASK (1 << 1) +#define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_SHIFT 0 +#define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_MASK (1 << 0) + +/* PADCONF_WAKEUPEVENT_1 */ +#define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 31 +#define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 31) +#define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_SHIFT 30 +#define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_MASK (1 << 30) +#define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_SHIFT 29 +#define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_MASK (1 << 29) +#define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_SHIFT 28 +#define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_MASK (1 << 28) +#define OMAP4_CSI22_DY0_DUPLICATEWAKEUPEVENT_SHIFT 27 +#define OMAP4_CSI22_DY0_DUPLICATEWAKEUPEVENT_MASK (1 << 27) +#define OMAP4_CSI22_DX0_DUPLICATEWAKEUPEVENT_SHIFT 26 +#define OMAP4_CSI22_DX0_DUPLICATEWAKEUPEVENT_MASK (1 << 26) +#define OMAP4_CSI21_DY4_DUPLICATEWAKEUPEVENT_SHIFT 25 +#define OMAP4_CSI21_DY4_DUPLICATEWAKEUPEVENT_MASK (1 << 25) +#define OMAP4_CSI21_DX4_DUPLICATEWAKEUPEVENT_SHIFT 24 +#define OMAP4_CSI21_DX4_DUPLICATEWAKEUPEVENT_MASK (1 << 24) +#define OMAP4_CSI21_DY3_DUPLICATEWAKEUPEVENT_SHIFT 23 +#define OMAP4_CSI21_DY3_DUPLICATEWAKEUPEVENT_MASK (1 << 23) +#define OMAP4_CSI21_DX3_DUPLICATEWAKEUPEVENT_SHIFT 22 +#define OMAP4_CSI21_DX3_DUPLICATEWAKEUPEVENT_MASK (1 << 22) +#define OMAP4_CSI21_DY2_DUPLICATEWAKEUPEVENT_SHIFT 21 +#define OMAP4_CSI21_DY2_DUPLICATEWAKEUPEVENT_MASK (1 << 21) +#define OMAP4_CSI21_DX2_DUPLICATEWAKEUPEVENT_SHIFT 20 +#define OMAP4_CSI21_DX2_DUPLICATEWAKEUPEVENT_MASK (1 << 20) +#define OMAP4_CSI21_DY1_DUPLICATEWAKEUPEVENT_SHIFT 19 +#define OMAP4_CSI21_DY1_DUPLICATEWAKEUPEVENT_MASK (1 << 19) +#define OMAP4_CSI21_DX1_DUPLICATEWAKEUPEVENT_SHIFT 18 +#define OMAP4_CSI21_DX1_DUPLICATEWAKEUPEVENT_MASK (1 << 18) +#define OMAP4_CSI21_DY0_DUPLICATEWAKEUPEVENT_SHIFT 17 +#define OMAP4_CSI21_DY0_DUPLICATEWAKEUPEVENT_MASK (1 << 17) +#define OMAP4_CSI21_DX0_DUPLICATEWAKEUPEVENT_SHIFT 16 +#define OMAP4_CSI21_DX0_DUPLICATEWAKEUPEVENT_MASK (1 << 16) +#define OMAP4_HDMI_DDC_SDA_DUPLICATEWAKEUPEVENT_SHIFT 15 +#define OMAP4_HDMI_DDC_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 15) +#define OMAP4_HDMI_DDC_SCL_DUPLICATEWAKEUPEVENT_SHIFT 14 +#define OMAP4_HDMI_DDC_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 14) +#define OMAP4_HDMI_CEC_DUPLICATEWAKEUPEVENT_SHIFT 13 +#define OMAP4_HDMI_CEC_DUPLICATEWAKEUPEVENT_MASK (1 << 13) +#define OMAP4_HDMI_HPD_DUPLICATEWAKEUPEVENT_SHIFT 12 +#define OMAP4_HDMI_HPD_DUPLICATEWAKEUPEVENT_MASK (1 << 12) +#define OMAP4_C2C_DATA15_DUPLICATEWAKEUPEVENT_SHIFT 11 +#define OMAP4_C2C_DATA15_DUPLICATEWAKEUPEVENT_MASK (1 << 11) +#define OMAP4_C2C_DATA14_DUPLICATEWAKEUPEVENT_SHIFT 10 +#define OMAP4_C2C_DATA14_DUPLICATEWAKEUPEVENT_MASK (1 << 10) +#define OMAP4_C2C_DATA13_DUPLICATEWAKEUPEVENT_SHIFT 9 +#define OMAP4_C2C_DATA13_DUPLICATEWAKEUPEVENT_MASK (1 << 9) +#define OMAP4_C2C_DATA12_DUPLICATEWAKEUPEVENT_SHIFT 8 +#define OMAP4_C2C_DATA12_DUPLICATEWAKEUPEVENT_MASK (1 << 8) +#define OMAP4_C2C_DATA11_DUPLICATEWAKEUPEVENT_SHIFT 7 +#define OMAP4_C2C_DATA11_DUPLICATEWAKEUPEVENT_MASK (1 << 7) +#define OMAP4_GPMC_WAIT1_DUPLICATEWAKEUPEVENT_SHIFT 6 +#define OMAP4_GPMC_WAIT1_DUPLICATEWAKEUPEVENT_MASK (1 << 6) +#define OMAP4_GPMC_WAIT0_DUPLICATEWAKEUPEVENT_SHIFT 5 +#define OMAP4_GPMC_WAIT0_DUPLICATEWAKEUPEVENT_MASK (1 << 5) +#define OMAP4_GPMC_NBE1_DUPLICATEWAKEUPEVENT_SHIFT 4 +#define OMAP4_GPMC_NBE1_DUPLICATEWAKEUPEVENT_MASK (1 << 4) +#define OMAP4_GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT_SHIFT 3 +#define OMAP4_GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT_MASK (1 << 3) +#define OMAP4_GPMC_NWE_DUPLICATEWAKEUPEVENT_SHIFT 2 +#define OMAP4_GPMC_NWE_DUPLICATEWAKEUPEVENT_MASK (1 << 2) +#define OMAP4_GPMC_NOE_DUPLICATEWAKEUPEVENT_SHIFT 1 +#define OMAP4_GPMC_NOE_DUPLICATEWAKEUPEVENT_MASK (1 << 1) +#define OMAP4_GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT_SHIFT 0 +#define OMAP4_GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT_MASK (1 << 0) + +/* PADCONF_WAKEUPEVENT_2 */ +#define OMAP4_ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT_SHIFT 31 +#define OMAP4_ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT_MASK (1 << 31) +#define OMAP4_ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT_SHIFT 30 +#define OMAP4_ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT_MASK (1 << 30) +#define OMAP4_ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT_SHIFT 29 +#define OMAP4_ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT_MASK (1 << 29) +#define OMAP4_ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT_SHIFT 28 +#define OMAP4_ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT_MASK (1 << 28) +#define OMAP4_ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT_SHIFT 27 +#define OMAP4_ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT_MASK (1 << 27) +#define OMAP4_SDMMC1_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 26 +#define OMAP4_SDMMC1_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 26) +#define OMAP4_SDMMC1_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 25 +#define OMAP4_SDMMC1_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 25) +#define OMAP4_SDMMC1_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 24 +#define OMAP4_SDMMC1_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 24) +#define OMAP4_SDMMC1_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 23 +#define OMAP4_SDMMC1_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 23) +#define OMAP4_SDMMC1_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 22 +#define OMAP4_SDMMC1_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 22) +#define OMAP4_SDMMC1_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 21 +#define OMAP4_SDMMC1_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 21) +#define OMAP4_SDMMC1_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 20 +#define OMAP4_SDMMC1_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 20) +#define OMAP4_SDMMC1_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 19 +#define OMAP4_SDMMC1_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 19) +#define OMAP4_SDMMC1_CMD_DUPLICATEWAKEUPEVENT_SHIFT 18 +#define OMAP4_SDMMC1_CMD_DUPLICATEWAKEUPEVENT_MASK (1 << 18) +#define OMAP4_SDMMC1_CLK_DUPLICATEWAKEUPEVENT_SHIFT 17 +#define OMAP4_SDMMC1_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 17) +#define OMAP4_USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT_SHIFT 16 +#define OMAP4_USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT_MASK (1 << 16) +#define OMAP4_USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT_SHIFT 15 +#define OMAP4_USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT_MASK (1 << 15) +#define OMAP4_USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 14 +#define OMAP4_USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 14) +#define OMAP4_USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT_SHIFT 13 +#define OMAP4_USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 13) +#define OMAP4_USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 12 +#define OMAP4_USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 12) +#define OMAP4_USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 11 +#define OMAP4_USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 11) +#define OMAP4_USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 10 +#define OMAP4_USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 10) +#define OMAP4_USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 9 +#define OMAP4_USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 9) +#define OMAP4_USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 8 +#define OMAP4_USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 8) +#define OMAP4_USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 7 +#define OMAP4_USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 7) +#define OMAP4_USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 6 +#define OMAP4_USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 6) +#define OMAP4_USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 5 +#define OMAP4_USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 5) +#define OMAP4_USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_SHIFT 4 +#define OMAP4_USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_MASK (1 << 4) +#define OMAP4_USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_SHIFT 3 +#define OMAP4_USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_MASK (1 << 3) +#define OMAP4_USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT_SHIFT 2 +#define OMAP4_USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT_MASK (1 << 2) +#define OMAP4_USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_SHIFT 1 +#define OMAP4_USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 1) +#define OMAP4_CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT_SHIFT 0 +#define OMAP4_CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT_MASK (1 << 0) + +/* PADCONF_WAKEUPEVENT_3 */ +#define OMAP4_MCSPI1_CS3_DUPLICATEWAKEUPEVENT_SHIFT 31 +#define OMAP4_MCSPI1_CS3_DUPLICATEWAKEUPEVENT_MASK (1 << 31) +#define OMAP4_MCSPI1_CS2_DUPLICATEWAKEUPEVENT_SHIFT 30 +#define OMAP4_MCSPI1_CS2_DUPLICATEWAKEUPEVENT_MASK (1 << 30) +#define OMAP4_MCSPI1_CS1_DUPLICATEWAKEUPEVENT_SHIFT 29 +#define OMAP4_MCSPI1_CS1_DUPLICATEWAKEUPEVENT_MASK (1 << 29) +#define OMAP4_MCSPI1_CS0_DUPLICATEWAKEUPEVENT_SHIFT 28 +#define OMAP4_MCSPI1_CS0_DUPLICATEWAKEUPEVENT_MASK (1 << 28) +#define OMAP4_MCSPI1_SIMO_DUPLICATEWAKEUPEVENT_SHIFT 27 +#define OMAP4_MCSPI1_SIMO_DUPLICATEWAKEUPEVENT_MASK (1 << 27) +#define OMAP4_MCSPI1_SOMI_DUPLICATEWAKEUPEVENT_SHIFT 26 +#define OMAP4_MCSPI1_SOMI_DUPLICATEWAKEUPEVENT_MASK (1 << 26) +#define OMAP4_MCSPI1_CLK_DUPLICATEWAKEUPEVENT_SHIFT 25 +#define OMAP4_MCSPI1_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 25) +#define OMAP4_I2C4_SDA_DUPLICATEWAKEUPEVENT_SHIFT 24 +#define OMAP4_I2C4_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 24) +#define OMAP4_I2C4_SCL_DUPLICATEWAKEUPEVENT_SHIFT 23 +#define OMAP4_I2C4_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 23) +#define OMAP4_I2C3_SDA_DUPLICATEWAKEUPEVENT_SHIFT 22 +#define OMAP4_I2C3_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 22) +#define OMAP4_I2C3_SCL_DUPLICATEWAKEUPEVENT_SHIFT 21 +#define OMAP4_I2C3_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 21) +#define OMAP4_I2C2_SDA_DUPLICATEWAKEUPEVENT_SHIFT 20 +#define OMAP4_I2C2_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 20) +#define OMAP4_I2C2_SCL_DUPLICATEWAKEUPEVENT_SHIFT 19 +#define OMAP4_I2C2_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 19) +#define OMAP4_I2C1_SDA_DUPLICATEWAKEUPEVENT_SHIFT 18 +#define OMAP4_I2C1_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 18) +#define OMAP4_I2C1_SCL_DUPLICATEWAKEUPEVENT_SHIFT 17 +#define OMAP4_I2C1_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 17) +#define OMAP4_HDQ_SIO_DUPLICATEWAKEUPEVENT_SHIFT 16 +#define OMAP4_HDQ_SIO_DUPLICATEWAKEUPEVENT_MASK (1 << 16) +#define OMAP4_UART2_TX_DUPLICATEWAKEUPEVENT_SHIFT 15 +#define OMAP4_UART2_TX_DUPLICATEWAKEUPEVENT_MASK (1 << 15) +#define OMAP4_UART2_RX_DUPLICATEWAKEUPEVENT_SHIFT 14 +#define OMAP4_UART2_RX_DUPLICATEWAKEUPEVENT_MASK (1 << 14) +#define OMAP4_UART2_RTS_DUPLICATEWAKEUPEVENT_SHIFT 13 +#define OMAP4_UART2_RTS_DUPLICATEWAKEUPEVENT_MASK (1 << 13) +#define OMAP4_UART2_CTS_DUPLICATEWAKEUPEVENT_SHIFT 12 +#define OMAP4_UART2_CTS_DUPLICATEWAKEUPEVENT_MASK (1 << 12) +#define OMAP4_ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT_SHIFT 11 +#define OMAP4_ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT_MASK (1 << 11) +#define OMAP4_ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT_SHIFT 10 +#define OMAP4_ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT_MASK (1 << 10) +#define OMAP4_ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT_SHIFT 9 +#define OMAP4_ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT_MASK (1 << 9) +#define OMAP4_ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT_SHIFT 8 +#define OMAP4_ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT_MASK (1 << 8) +#define OMAP4_ABE_CLKS_DUPLICATEWAKEUPEVENT_SHIFT 7 +#define OMAP4_ABE_CLKS_DUPLICATEWAKEUPEVENT_MASK (1 << 7) +#define OMAP4_ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT_SHIFT 6 +#define OMAP4_ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 6) +#define OMAP4_ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT_SHIFT 5 +#define OMAP4_ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT_MASK (1 << 5) +#define OMAP4_ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT_SHIFT 4 +#define OMAP4_ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 4) +#define OMAP4_ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT_SHIFT 3 +#define OMAP4_ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 3) +#define OMAP4_ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT_SHIFT 2 +#define OMAP4_ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT_MASK (1 << 2) +#define OMAP4_ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT_SHIFT 1 +#define OMAP4_ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT_MASK (1 << 1) +#define OMAP4_ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT_SHIFT 0 +#define OMAP4_ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT_MASK (1 << 0) + +/* PADCONF_WAKEUPEVENT_4 */ +#define OMAP4_UNIPRO_TY0_DUPLICATEWAKEUPEVENT_SHIFT 31 +#define OMAP4_UNIPRO_TY0_DUPLICATEWAKEUPEVENT_MASK (1 << 31) +#define OMAP4_UNIPRO_TX0_DUPLICATEWAKEUPEVENT_SHIFT 30 +#define OMAP4_UNIPRO_TX0_DUPLICATEWAKEUPEVENT_MASK (1 << 30) +#define OMAP4_USBB2_HSIC_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 29 +#define OMAP4_USBB2_HSIC_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 29) +#define OMAP4_USBB2_HSIC_DATA_DUPLICATEWAKEUPEVENT_SHIFT 28 +#define OMAP4_USBB2_HSIC_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 28) +#define OMAP4_USBB2_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 27 +#define OMAP4_USBB2_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 27) +#define OMAP4_USBB2_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 26 +#define OMAP4_USBB2_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 26) +#define OMAP4_USBB2_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 25 +#define OMAP4_USBB2_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 25) +#define OMAP4_USBB2_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 24 +#define OMAP4_USBB2_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 24) +#define OMAP4_USBB2_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 23 +#define OMAP4_USBB2_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 23) +#define OMAP4_USBB2_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 22 +#define OMAP4_USBB2_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 22) +#define OMAP4_USBB2_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 21 +#define OMAP4_USBB2_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 21) +#define OMAP4_USBB2_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 20 +#define OMAP4_USBB2_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 20) +#define OMAP4_USBB2_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_SHIFT 19 +#define OMAP4_USBB2_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_MASK (1 << 19) +#define OMAP4_USBB2_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_SHIFT 18 +#define OMAP4_USBB2_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_MASK (1 << 18) +#define OMAP4_USBB2_ULPITLL_STP_DUPLICATEWAKEUPEVENT_SHIFT 17 +#define OMAP4_USBB2_ULPITLL_STP_DUPLICATEWAKEUPEVENT_MASK (1 << 17) +#define OMAP4_USBB2_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_SHIFT 16 +#define OMAP4_USBB2_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 16) +#define OMAP4_UART4_TX_DUPLICATEWAKEUPEVENT_SHIFT 15 +#define OMAP4_UART4_TX_DUPLICATEWAKEUPEVENT_MASK (1 << 15) +#define OMAP4_UART4_RX_DUPLICATEWAKEUPEVENT_SHIFT 14 +#define OMAP4_UART4_RX_DUPLICATEWAKEUPEVENT_MASK (1 << 14) +#define OMAP4_MCSPI4_CS0_DUPLICATEWAKEUPEVENT_SHIFT 13 +#define OMAP4_MCSPI4_CS0_DUPLICATEWAKEUPEVENT_MASK (1 << 13) +#define OMAP4_MCSPI4_SOMI_DUPLICATEWAKEUPEVENT_SHIFT 12 +#define OMAP4_MCSPI4_SOMI_DUPLICATEWAKEUPEVENT_MASK (1 << 12) +#define OMAP4_MCSPI4_SIMO_DUPLICATEWAKEUPEVENT_SHIFT 11 +#define OMAP4_MCSPI4_SIMO_DUPLICATEWAKEUPEVENT_MASK (1 << 11) +#define OMAP4_MCSPI4_CLK_DUPLICATEWAKEUPEVENT_SHIFT 10 +#define OMAP4_MCSPI4_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 10) +#define OMAP4_SDMMC5_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 9 +#define OMAP4_SDMMC5_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 9) +#define OMAP4_SDMMC5_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 8 +#define OMAP4_SDMMC5_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 8) +#define OMAP4_SDMMC5_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 7 +#define OMAP4_SDMMC5_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 7) +#define OMAP4_SDMMC5_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 6 +#define OMAP4_SDMMC5_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 6) +#define OMAP4_SDMMC5_CMD_DUPLICATEWAKEUPEVENT_SHIFT 5 +#define OMAP4_SDMMC5_CMD_DUPLICATEWAKEUPEVENT_MASK (1 << 5) +#define OMAP4_SDMMC5_CLK_DUPLICATEWAKEUPEVENT_SHIFT 4 +#define OMAP4_SDMMC5_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 4) +#define OMAP4_UART3_TX_IRTX_DUPLICATEWAKEUPEVENT_SHIFT 3 +#define OMAP4_UART3_TX_IRTX_DUPLICATEWAKEUPEVENT_MASK (1 << 3) +#define OMAP4_UART3_RX_IRRX_DUPLICATEWAKEUPEVENT_SHIFT 2 +#define OMAP4_UART3_RX_IRRX_DUPLICATEWAKEUPEVENT_MASK (1 << 2) +#define OMAP4_UART3_RTS_SD_DUPLICATEWAKEUPEVENT_SHIFT 1 +#define OMAP4_UART3_RTS_SD_DUPLICATEWAKEUPEVENT_MASK (1 << 1) +#define OMAP4_UART3_CTS_RCTX_DUPLICATEWAKEUPEVENT_SHIFT 0 +#define OMAP4_UART3_CTS_RCTX_DUPLICATEWAKEUPEVENT_MASK (1 << 0) + +/* PADCONF_WAKEUPEVENT_5 */ +#define OMAP4_DPM_EMU11_DUPLICATEWAKEUPEVENT_SHIFT 31 +#define OMAP4_DPM_EMU11_DUPLICATEWAKEUPEVENT_MASK (1 << 31) +#define OMAP4_DPM_EMU10_DUPLICATEWAKEUPEVENT_SHIFT 30 +#define OMAP4_DPM_EMU10_DUPLICATEWAKEUPEVENT_MASK (1 << 30) +#define OMAP4_DPM_EMU9_DUPLICATEWAKEUPEVENT_SHIFT 29 +#define OMAP4_DPM_EMU9_DUPLICATEWAKEUPEVENT_MASK (1 << 29) +#define OMAP4_DPM_EMU8_DUPLICATEWAKEUPEVENT_SHIFT 28 +#define OMAP4_DPM_EMU8_DUPLICATEWAKEUPEVENT_MASK (1 << 28) +#define OMAP4_DPM_EMU7_DUPLICATEWAKEUPEVENT_SHIFT 27 +#define OMAP4_DPM_EMU7_DUPLICATEWAKEUPEVENT_MASK (1 << 27) +#define OMAP4_DPM_EMU6_DUPLICATEWAKEUPEVENT_SHIFT 26 +#define OMAP4_DPM_EMU6_DUPLICATEWAKEUPEVENT_MASK (1 << 26) +#define OMAP4_DPM_EMU5_DUPLICATEWAKEUPEVENT_SHIFT 25 +#define OMAP4_DPM_EMU5_DUPLICATEWAKEUPEVENT_MASK (1 << 25) +#define OMAP4_DPM_EMU4_DUPLICATEWAKEUPEVENT_SHIFT 24 +#define OMAP4_DPM_EMU4_DUPLICATEWAKEUPEVENT_MASK (1 << 24) +#define OMAP4_DPM_EMU3_DUPLICATEWAKEUPEVENT_SHIFT 23 +#define OMAP4_DPM_EMU3_DUPLICATEWAKEUPEVENT_MASK (1 << 23) +#define OMAP4_DPM_EMU2_DUPLICATEWAKEUPEVENT_SHIFT 22 +#define OMAP4_DPM_EMU2_DUPLICATEWAKEUPEVENT_MASK (1 << 22) +#define OMAP4_DPM_EMU1_DUPLICATEWAKEUPEVENT_SHIFT 21 +#define OMAP4_DPM_EMU1_DUPLICATEWAKEUPEVENT_MASK (1 << 21) +#define OMAP4_DPM_EMU0_DUPLICATEWAKEUPEVENT_SHIFT 20 +#define OMAP4_DPM_EMU0_DUPLICATEWAKEUPEVENT_MASK (1 << 20) +#define OMAP4_SYS_BOOT5_DUPLICATEWAKEUPEVENT_SHIFT 19 +#define OMAP4_SYS_BOOT5_DUPLICATEWAKEUPEVENT_MASK (1 << 19) +#define OMAP4_SYS_BOOT4_DUPLICATEWAKEUPEVENT_SHIFT 18 +#define OMAP4_SYS_BOOT4_DUPLICATEWAKEUPEVENT_MASK (1 << 18) +#define OMAP4_SYS_BOOT3_DUPLICATEWAKEUPEVENT_SHIFT 17 +#define OMAP4_SYS_BOOT3_DUPLICATEWAKEUPEVENT_MASK (1 << 17) +#define OMAP4_SYS_BOOT2_DUPLICATEWAKEUPEVENT_SHIFT 16 +#define OMAP4_SYS_BOOT2_DUPLICATEWAKEUPEVENT_MASK (1 << 16) +#define OMAP4_SYS_BOOT1_DUPLICATEWAKEUPEVENT_SHIFT 15 +#define OMAP4_SYS_BOOT1_DUPLICATEWAKEUPEVENT_MASK (1 << 15) +#define OMAP4_SYS_BOOT0_DUPLICATEWAKEUPEVENT_SHIFT 14 +#define OMAP4_SYS_BOOT0_DUPLICATEWAKEUPEVENT_MASK (1 << 14) +#define OMAP4_SYS_NIRQ2_DUPLICATEWAKEUPEVENT_SHIFT 13 +#define OMAP4_SYS_NIRQ2_DUPLICATEWAKEUPEVENT_MASK (1 << 13) +#define OMAP4_SYS_NIRQ1_DUPLICATEWAKEUPEVENT_SHIFT 12 +#define OMAP4_SYS_NIRQ1_DUPLICATEWAKEUPEVENT_MASK (1 << 12) +#define OMAP4_FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT_SHIFT 11 +#define OMAP4_FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 11) +#define OMAP4_FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT_SHIFT 10 +#define OMAP4_FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 10) +#define OMAP4_UNIPRO_RY2_DUPLICATEWAKEUPEVENT_SHIFT 9 +#define OMAP4_UNIPRO_RY2_DUPLICATEWAKEUPEVENT_MASK (1 << 9) +#define OMAP4_UNIPRO_RX2_DUPLICATEWAKEUPEVENT_SHIFT 8 +#define OMAP4_UNIPRO_RX2_DUPLICATEWAKEUPEVENT_MASK (1 << 8) +#define OMAP4_UNIPRO_RY1_DUPLICATEWAKEUPEVENT_SHIFT 7 +#define OMAP4_UNIPRO_RY1_DUPLICATEWAKEUPEVENT_MASK (1 << 7) +#define OMAP4_UNIPRO_RX1_DUPLICATEWAKEUPEVENT_SHIFT 6 +#define OMAP4_UNIPRO_RX1_DUPLICATEWAKEUPEVENT_MASK (1 << 6) +#define OMAP4_UNIPRO_RY0_DUPLICATEWAKEUPEVENT_SHIFT 5 +#define OMAP4_UNIPRO_RY0_DUPLICATEWAKEUPEVENT_MASK (1 << 5) +#define OMAP4_UNIPRO_RX0_DUPLICATEWAKEUPEVENT_SHIFT 4 +#define OMAP4_UNIPRO_RX0_DUPLICATEWAKEUPEVENT_MASK (1 << 4) +#define OMAP4_UNIPRO_TY2_DUPLICATEWAKEUPEVENT_SHIFT 3 +#define OMAP4_UNIPRO_TY2_DUPLICATEWAKEUPEVENT_MASK (1 << 3) +#define OMAP4_UNIPRO_TX2_DUPLICATEWAKEUPEVENT_SHIFT 2 +#define OMAP4_UNIPRO_TX2_DUPLICATEWAKEUPEVENT_MASK (1 << 2) +#define OMAP4_UNIPRO_TY1_DUPLICATEWAKEUPEVENT_SHIFT 1 +#define OMAP4_UNIPRO_TY1_DUPLICATEWAKEUPEVENT_MASK (1 << 1) +#define OMAP4_UNIPRO_TX1_DUPLICATEWAKEUPEVENT_SHIFT 0 +#define OMAP4_UNIPRO_TX1_DUPLICATEWAKEUPEVENT_MASK (1 << 0) + +/* PADCONF_WAKEUPEVENT_6 */ +#define OMAP4_DPM_EMU19_DUPLICATEWAKEUPEVENT_SHIFT 7 +#define OMAP4_DPM_EMU19_DUPLICATEWAKEUPEVENT_MASK (1 << 7) +#define OMAP4_DPM_EMU18_DUPLICATEWAKEUPEVENT_SHIFT 6 +#define OMAP4_DPM_EMU18_DUPLICATEWAKEUPEVENT_MASK (1 << 6) +#define OMAP4_DPM_EMU17_DUPLICATEWAKEUPEVENT_SHIFT 5 +#define OMAP4_DPM_EMU17_DUPLICATEWAKEUPEVENT_MASK (1 << 5) +#define OMAP4_DPM_EMU16_DUPLICATEWAKEUPEVENT_SHIFT 4 +#define OMAP4_DPM_EMU16_DUPLICATEWAKEUPEVENT_MASK (1 << 4) +#define OMAP4_DPM_EMU15_DUPLICATEWAKEUPEVENT_SHIFT 3 +#define OMAP4_DPM_EMU15_DUPLICATEWAKEUPEVENT_MASK (1 << 3) +#define OMAP4_DPM_EMU14_DUPLICATEWAKEUPEVENT_SHIFT 2 +#define OMAP4_DPM_EMU14_DUPLICATEWAKEUPEVENT_MASK (1 << 2) +#define OMAP4_DPM_EMU13_DUPLICATEWAKEUPEVENT_SHIFT 1 +#define OMAP4_DPM_EMU13_DUPLICATEWAKEUPEVENT_MASK (1 << 1) +#define OMAP4_DPM_EMU12_DUPLICATEWAKEUPEVENT_SHIFT 0 +#define OMAP4_DPM_EMU12_DUPLICATEWAKEUPEVENT_MASK (1 << 0) + +/* CONTROL_PADCONF_GLOBAL */ +#define OMAP4_FORCE_OFFMODE_EN_SHIFT 31 +#define OMAP4_FORCE_OFFMODE_EN_MASK (1 << 31) + +/* CONTROL_PADCONF_MODE */ +#define OMAP4_VDDS_DV_BANK0_SHIFT 31 +#define OMAP4_VDDS_DV_BANK0_MASK (1 << 31) +#define OMAP4_VDDS_DV_BANK1_SHIFT 30 +#define OMAP4_VDDS_DV_BANK1_MASK (1 << 30) +#define OMAP4_VDDS_DV_BANK3_SHIFT 29 +#define OMAP4_VDDS_DV_BANK3_MASK (1 << 29) +#define OMAP4_VDDS_DV_BANK4_SHIFT 28 +#define OMAP4_VDDS_DV_BANK4_MASK (1 << 28) +#define OMAP4_VDDS_DV_BANK5_SHIFT 27 +#define OMAP4_VDDS_DV_BANK5_MASK (1 << 27) +#define OMAP4_VDDS_DV_BANK6_SHIFT 26 +#define OMAP4_VDDS_DV_BANK6_MASK (1 << 26) +#define OMAP4_VDDS_DV_C2C_SHIFT 25 +#define OMAP4_VDDS_DV_C2C_MASK (1 << 25) +#define OMAP4_VDDS_DV_CAM_SHIFT 24 +#define OMAP4_VDDS_DV_CAM_MASK (1 << 24) +#define OMAP4_VDDS_DV_GPMC_SHIFT 23 +#define OMAP4_VDDS_DV_GPMC_MASK (1 << 23) +#define OMAP4_VDDS_DV_SDMMC2_SHIFT 22 +#define OMAP4_VDDS_DV_SDMMC2_MASK (1 << 22) + +/* CONTROL_SMART1IO_PADCONF_0 */ +#define OMAP4_ABE_DR0_SC_SHIFT 30 +#define OMAP4_ABE_DR0_SC_MASK (0x3 << 30) +#define OMAP4_CAM_DR0_SC_SHIFT 28 +#define OMAP4_CAM_DR0_SC_MASK (0x3 << 28) +#define OMAP4_FREF_DR2_SC_SHIFT 26 +#define OMAP4_FREF_DR2_SC_MASK (0x3 << 26) +#define OMAP4_FREF_DR3_SC_SHIFT 24 +#define OMAP4_FREF_DR3_SC_MASK (0x3 << 24) +#define OMAP4_GPIO_DR8_SC_SHIFT 22 +#define OMAP4_GPIO_DR8_SC_MASK (0x3 << 22) +#define OMAP4_GPIO_DR9_SC_SHIFT 20 +#define OMAP4_GPIO_DR9_SC_MASK (0x3 << 20) +#define OMAP4_GPMC_DR2_SC_SHIFT 18 +#define OMAP4_GPMC_DR2_SC_MASK (0x3 << 18) +#define OMAP4_GPMC_DR3_SC_SHIFT 16 +#define OMAP4_GPMC_DR3_SC_MASK (0x3 << 16) +#define OMAP4_GPMC_DR6_SC_SHIFT 14 +#define OMAP4_GPMC_DR6_SC_MASK (0x3 << 14) +#define OMAP4_HDMI_DR0_SC_SHIFT 12 +#define OMAP4_HDMI_DR0_SC_MASK (0x3 << 12) +#define OMAP4_MCSPI1_DR0_SC_SHIFT 10 +#define OMAP4_MCSPI1_DR0_SC_MASK (0x3 << 10) +#define OMAP4_UART1_DR0_SC_SHIFT 8 +#define OMAP4_UART1_DR0_SC_MASK (0x3 << 8) +#define OMAP4_UART3_DR0_SC_SHIFT 6 +#define OMAP4_UART3_DR0_SC_MASK (0x3 << 6) +#define OMAP4_UART3_DR1_SC_SHIFT 4 +#define OMAP4_UART3_DR1_SC_MASK (0x3 << 4) +#define OMAP4_UNIPRO_DR0_SC_SHIFT 2 +#define OMAP4_UNIPRO_DR0_SC_MASK (0x3 << 2) +#define OMAP4_UNIPRO_DR1_SC_SHIFT 0 +#define OMAP4_UNIPRO_DR1_SC_MASK (0x3 << 0) + +/* CONTROL_SMART1IO_PADCONF_1 */ +#define OMAP4_ABE_DR0_LB_SHIFT 30 +#define OMAP4_ABE_DR0_LB_MASK (0x3 << 30) +#define OMAP4_CAM_DR0_LB_SHIFT 28 +#define OMAP4_CAM_DR0_LB_MASK (0x3 << 28) +#define OMAP4_FREF_DR2_LB_SHIFT 26 +#define OMAP4_FREF_DR2_LB_MASK (0x3 << 26) +#define OMAP4_FREF_DR3_LB_SHIFT 24 +#define OMAP4_FREF_DR3_LB_MASK (0x3 << 24) +#define OMAP4_GPIO_DR8_LB_SHIFT 22 +#define OMAP4_GPIO_DR8_LB_MASK (0x3 << 22) +#define OMAP4_GPIO_DR9_LB_SHIFT 20 +#define OMAP4_GPIO_DR9_LB_MASK (0x3 << 20) +#define OMAP4_GPMC_DR2_LB_SHIFT 18 +#define OMAP4_GPMC_DR2_LB_MASK (0x3 << 18) +#define OMAP4_GPMC_DR3_LB_SHIFT 16 +#define OMAP4_GPMC_DR3_LB_MASK (0x3 << 16) +#define OMAP4_GPMC_DR6_LB_SHIFT 14 +#define OMAP4_GPMC_DR6_LB_MASK (0x3 << 14) +#define OMAP4_HDMI_DR0_LB_SHIFT 12 +#define OMAP4_HDMI_DR0_LB_MASK (0x3 << 12) +#define OMAP4_MCSPI1_DR0_LB_SHIFT 10 +#define OMAP4_MCSPI1_DR0_LB_MASK (0x3 << 10) +#define OMAP4_UART1_DR0_LB_SHIFT 8 +#define OMAP4_UART1_DR0_LB_MASK (0x3 << 8) +#define OMAP4_UART3_DR0_LB_SHIFT 6 +#define OMAP4_UART3_DR0_LB_MASK (0x3 << 6) +#define OMAP4_UART3_DR1_LB_SHIFT 4 +#define OMAP4_UART3_DR1_LB_MASK (0x3 << 4) +#define OMAP4_UNIPRO_DR0_LB_SHIFT 2 +#define OMAP4_UNIPRO_DR0_LB_MASK (0x3 << 2) +#define OMAP4_UNIPRO_DR1_LB_SHIFT 0 +#define OMAP4_UNIPRO_DR1_LB_MASK (0x3 << 0) + +/* CONTROL_SMART2IO_PADCONF_0 */ +#define OMAP4_C2C_DR0_LB_SHIFT 31 +#define OMAP4_C2C_DR0_LB_MASK (1 << 31) +#define OMAP4_DPM_DR1_LB_SHIFT 30 +#define OMAP4_DPM_DR1_LB_MASK (1 << 30) +#define OMAP4_DPM_DR2_LB_SHIFT 29 +#define OMAP4_DPM_DR2_LB_MASK (1 << 29) +#define OMAP4_DPM_DR3_LB_SHIFT 28 +#define OMAP4_DPM_DR3_LB_MASK (1 << 28) +#define OMAP4_GPIO_DR0_LB_SHIFT 27 +#define OMAP4_GPIO_DR0_LB_MASK (1 << 27) +#define OMAP4_GPIO_DR1_LB_SHIFT 26 +#define OMAP4_GPIO_DR1_LB_MASK (1 << 26) +#define OMAP4_GPIO_DR10_LB_SHIFT 25 +#define OMAP4_GPIO_DR10_LB_MASK (1 << 25) +#define OMAP4_GPIO_DR2_LB_SHIFT 24 +#define OMAP4_GPIO_DR2_LB_MASK (1 << 24) +#define OMAP4_GPMC_DR0_LB_SHIFT 23 +#define OMAP4_GPMC_DR0_LB_MASK (1 << 23) +#define OMAP4_GPMC_DR1_LB_SHIFT 22 +#define OMAP4_GPMC_DR1_LB_MASK (1 << 22) +#define OMAP4_GPMC_DR4_LB_SHIFT 21 +#define OMAP4_GPMC_DR4_LB_MASK (1 << 21) +#define OMAP4_GPMC_DR5_LB_SHIFT 20 +#define OMAP4_GPMC_DR5_LB_MASK (1 << 20) +#define OMAP4_GPMC_DR7_LB_SHIFT 19 +#define OMAP4_GPMC_DR7_LB_MASK (1 << 19) +#define OMAP4_HSI2_DR0_LB_SHIFT 18 +#define OMAP4_HSI2_DR0_LB_MASK (1 << 18) +#define OMAP4_HSI2_DR1_LB_SHIFT 17 +#define OMAP4_HSI2_DR1_LB_MASK (1 << 17) +#define OMAP4_HSI2_DR2_LB_SHIFT 16 +#define OMAP4_HSI2_DR2_LB_MASK (1 << 16) +#define OMAP4_KPD_DR0_LB_SHIFT 15 +#define OMAP4_KPD_DR0_LB_MASK (1 << 15) +#define OMAP4_KPD_DR1_LB_SHIFT 14 +#define OMAP4_KPD_DR1_LB_MASK (1 << 14) +#define OMAP4_PDM_DR0_LB_SHIFT 13 +#define OMAP4_PDM_DR0_LB_MASK (1 << 13) +#define OMAP4_SDMMC2_DR0_LB_SHIFT 12 +#define OMAP4_SDMMC2_DR0_LB_MASK (1 << 12) +#define OMAP4_SDMMC3_DR0_LB_SHIFT 11 +#define OMAP4_SDMMC3_DR0_LB_MASK (1 << 11) +#define OMAP4_SDMMC4_DR0_LB_SHIFT 10 +#define OMAP4_SDMMC4_DR0_LB_MASK (1 << 10) +#define OMAP4_SDMMC4_DR1_LB_SHIFT 9 +#define OMAP4_SDMMC4_DR1_LB_MASK (1 << 9) +#define OMAP4_SPI3_DR0_LB_SHIFT 8 +#define OMAP4_SPI3_DR0_LB_MASK (1 << 8) +#define OMAP4_SPI3_DR1_LB_SHIFT 7 +#define OMAP4_SPI3_DR1_LB_MASK (1 << 7) +#define OMAP4_UART3_DR2_LB_SHIFT 6 +#define OMAP4_UART3_DR2_LB_MASK (1 << 6) +#define OMAP4_UART3_DR3_LB_SHIFT 5 +#define OMAP4_UART3_DR3_LB_MASK (1 << 5) +#define OMAP4_UART3_DR4_LB_SHIFT 4 +#define OMAP4_UART3_DR4_LB_MASK (1 << 4) +#define OMAP4_UART3_DR5_LB_SHIFT 3 +#define OMAP4_UART3_DR5_LB_MASK (1 << 3) +#define OMAP4_USBA0_DR1_LB_SHIFT 2 +#define OMAP4_USBA0_DR1_LB_MASK (1 << 2) +#define OMAP4_USBA_DR2_LB_SHIFT 1 +#define OMAP4_USBA_DR2_LB_MASK (1 << 1) + +/* CONTROL_SMART2IO_PADCONF_1 */ +#define OMAP4_USBB1_DR0_LB_SHIFT 31 +#define OMAP4_USBB1_DR0_LB_MASK (1 << 31) +#define OMAP4_USBB2_DR0_LB_SHIFT 30 +#define OMAP4_USBB2_DR0_LB_MASK (1 << 30) +#define OMAP4_USBA0_DR0_LB_SHIFT 29 +#define OMAP4_USBA0_DR0_LB_MASK (1 << 29) + +/* CONTROL_SMART3IO_PADCONF_0 */ +#define OMAP4_DMIC_DR0_MB_SHIFT 30 +#define OMAP4_DMIC_DR0_MB_MASK (0x3 << 30) +#define OMAP4_GPIO_DR3_MB_SHIFT 28 +#define OMAP4_GPIO_DR3_MB_MASK (0x3 << 28) +#define OMAP4_GPIO_DR4_MB_SHIFT 26 +#define OMAP4_GPIO_DR4_MB_MASK (0x3 << 26) +#define OMAP4_GPIO_DR5_MB_SHIFT 24 +#define OMAP4_GPIO_DR5_MB_MASK (0x3 << 24) +#define OMAP4_GPIO_DR6_MB_SHIFT 22 +#define OMAP4_GPIO_DR6_MB_MASK (0x3 << 22) +#define OMAP4_HSI_DR1_MB_SHIFT 20 +#define OMAP4_HSI_DR1_MB_MASK (0x3 << 20) +#define OMAP4_HSI_DR2_MB_SHIFT 18 +#define OMAP4_HSI_DR2_MB_MASK (0x3 << 18) +#define OMAP4_HSI_DR3_MB_SHIFT 16 +#define OMAP4_HSI_DR3_MB_MASK (0x3 << 16) +#define OMAP4_MCBSP2_DR0_MB_SHIFT 14 +#define OMAP4_MCBSP2_DR0_MB_MASK (0x3 << 14) +#define OMAP4_MCSPI4_DR0_MB_SHIFT 12 +#define OMAP4_MCSPI4_DR0_MB_MASK (0x3 << 12) +#define OMAP4_MCSPI4_DR1_MB_SHIFT 10 +#define OMAP4_MCSPI4_DR1_MB_MASK (0x3 << 10) +#define OMAP4_SDMMC3_DR0_MB_SHIFT 8 +#define OMAP4_SDMMC3_DR0_MB_MASK (0x3 << 8) +#define OMAP4_SPI2_DR0_MB_SHIFT 0 +#define OMAP4_SPI2_DR0_MB_MASK (0x3 << 0) + +/* CONTROL_SMART3IO_PADCONF_1 */ +#define OMAP4_SPI2_DR1_MB_SHIFT 30 +#define OMAP4_SPI2_DR1_MB_MASK (0x3 << 30) +#define OMAP4_SPI2_DR2_MB_SHIFT 28 +#define OMAP4_SPI2_DR2_MB_MASK (0x3 << 28) +#define OMAP4_UART2_DR0_MB_SHIFT 26 +#define OMAP4_UART2_DR0_MB_MASK (0x3 << 26) +#define OMAP4_UART2_DR1_MB_SHIFT 24 +#define OMAP4_UART2_DR1_MB_MASK (0x3 << 24) +#define OMAP4_UART4_DR0_MB_SHIFT 22 +#define OMAP4_UART4_DR0_MB_MASK (0x3 << 22) +#define OMAP4_HSI_DR0_MB_SHIFT 20 +#define OMAP4_HSI_DR0_MB_MASK (0x3 << 20) + +/* CONTROL_SMART3IO_PADCONF_2 */ +#define OMAP4_DMIC_DR0_LB_SHIFT 31 +#define OMAP4_DMIC_DR0_LB_MASK (1 << 31) +#define OMAP4_GPIO_DR3_LB_SHIFT 30 +#define OMAP4_GPIO_DR3_LB_MASK (1 << 30) +#define OMAP4_GPIO_DR4_LB_SHIFT 29 +#define OMAP4_GPIO_DR4_LB_MASK (1 << 29) +#define OMAP4_GPIO_DR5_LB_SHIFT 28 +#define OMAP4_GPIO_DR5_LB_MASK (1 << 28) +#define OMAP4_GPIO_DR6_LB_SHIFT 27 +#define OMAP4_GPIO_DR6_LB_MASK (1 << 27) +#define OMAP4_HSI_DR1_LB_SHIFT 26 +#define OMAP4_HSI_DR1_LB_MASK (1 << 26) +#define OMAP4_HSI_DR2_LB_SHIFT 25 +#define OMAP4_HSI_DR2_LB_MASK (1 << 25) +#define OMAP4_HSI_DR3_LB_SHIFT 24 +#define OMAP4_HSI_DR3_LB_MASK (1 << 24) +#define OMAP4_MCBSP2_DR0_LB_SHIFT 23 +#define OMAP4_MCBSP2_DR0_LB_MASK (1 << 23) +#define OMAP4_MCSPI4_DR0_LB_SHIFT 22 +#define OMAP4_MCSPI4_DR0_LB_MASK (1 << 22) +#define OMAP4_MCSPI4_DR1_LB_SHIFT 21 +#define OMAP4_MCSPI4_DR1_LB_MASK (1 << 21) +#define OMAP4_SLIMBUS2_DR0_LB_SHIFT 18 +#define OMAP4_SLIMBUS2_DR0_LB_MASK (1 << 18) +#define OMAP4_SPI2_DR0_LB_SHIFT 16 +#define OMAP4_SPI2_DR0_LB_MASK (1 << 16) +#define OMAP4_SPI2_DR1_LB_SHIFT 15 +#define OMAP4_SPI2_DR1_LB_MASK (1 << 15) +#define OMAP4_SPI2_DR2_LB_SHIFT 14 +#define OMAP4_SPI2_DR2_LB_MASK (1 << 14) +#define OMAP4_UART2_DR0_LB_SHIFT 13 +#define OMAP4_UART2_DR0_LB_MASK (1 << 13) +#define OMAP4_UART2_DR1_LB_SHIFT 12 +#define OMAP4_UART2_DR1_LB_MASK (1 << 12) +#define OMAP4_UART4_DR0_LB_SHIFT 11 +#define OMAP4_UART4_DR0_LB_MASK (1 << 11) +#define OMAP4_HSI_DR0_LB_SHIFT 10 +#define OMAP4_HSI_DR0_LB_MASK (1 << 10) + +/* CONTROL_USBB_HSIC */ +#define OMAP4_USBB2_DR1_SR_SHIFT 30 +#define OMAP4_USBB2_DR1_SR_MASK (0x3 << 30) +#define OMAP4_USBB2_DR1_I_SHIFT 27 +#define OMAP4_USBB2_DR1_I_MASK (0x7 << 27) +#define OMAP4_USBB1_DR1_SR_SHIFT 25 +#define OMAP4_USBB1_DR1_SR_MASK (0x3 << 25) +#define OMAP4_USBB1_DR1_I_SHIFT 22 +#define OMAP4_USBB1_DR1_I_MASK (0x7 << 22) +#define OMAP4_USBB1_HSIC_DATA_WD_SHIFT 20 +#define OMAP4_USBB1_HSIC_DATA_WD_MASK (0x3 << 20) +#define OMAP4_USBB1_HSIC_STROBE_WD_SHIFT 18 +#define OMAP4_USBB1_HSIC_STROBE_WD_MASK (0x3 << 18) +#define OMAP4_USBB2_HSIC_DATA_WD_SHIFT 16 +#define OMAP4_USBB2_HSIC_DATA_WD_MASK (0x3 << 16) +#define OMAP4_USBB2_HSIC_STROBE_WD_SHIFT 14 +#define OMAP4_USBB2_HSIC_STROBE_WD_MASK (0x3 << 14) +#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_ENABLE_SHIFT 13 +#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_ENABLE_MASK (1 << 13) +#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_SHIFT 11 +#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_MASK (0x3 << 11) +#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_ENABLE_SHIFT 10 +#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_ENABLE_MASK (1 << 10) +#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_SHIFT 8 +#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_MASK (0x3 << 8) +#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_ENABLE_SHIFT 7 +#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_ENABLE_MASK (1 << 7) +#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_SHIFT 5 +#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_MASK (0x3 << 5) +#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_ENABLE_SHIFT 4 +#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_ENABLE_MASK (1 << 4) +#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_SHIFT 2 +#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_MASK (0x3 << 2) + +/* CONTROL_SLIMBUS */ +#define OMAP4_SLIMBUS1_DR0_MB_SHIFT 30 +#define OMAP4_SLIMBUS1_DR0_MB_MASK (0x3 << 30) +#define OMAP4_SLIMBUS1_DR1_MB_SHIFT 28 +#define OMAP4_SLIMBUS1_DR1_MB_MASK (0x3 << 28) +#define OMAP4_SLIMBUS2_DR0_MB_SHIFT 26 +#define OMAP4_SLIMBUS2_DR0_MB_MASK (0x3 << 26) +#define OMAP4_SLIMBUS2_DR1_MB_SHIFT 24 +#define OMAP4_SLIMBUS2_DR1_MB_MASK (0x3 << 24) +#define OMAP4_SLIMBUS2_DR2_MB_SHIFT 22 +#define OMAP4_SLIMBUS2_DR2_MB_MASK (0x3 << 22) +#define OMAP4_SLIMBUS2_DR3_MB_SHIFT 20 +#define OMAP4_SLIMBUS2_DR3_MB_MASK (0x3 << 20) +#define OMAP4_SLIMBUS1_DR0_LB_SHIFT 19 +#define OMAP4_SLIMBUS1_DR0_LB_MASK (1 << 19) +#define OMAP4_SLIMBUS2_DR1_LB_SHIFT 18 +#define OMAP4_SLIMBUS2_DR1_LB_MASK (1 << 18) + +/* CONTROL_PBIASLITE */ +#define OMAP4_USIM_PBIASLITE_HIZ_MODE_SHIFT 31 +#define OMAP4_USIM_PBIASLITE_HIZ_MODE_MASK (1 << 31) +#define OMAP4_USIM_PBIASLITE_SUPPLY_HI_OUT_SHIFT 30 +#define OMAP4_USIM_PBIASLITE_SUPPLY_HI_OUT_MASK (1 << 30) +#define OMAP4_USIM_PBIASLITE_VMODE_ERROR_SHIFT 29 +#define OMAP4_USIM_PBIASLITE_VMODE_ERROR_MASK (1 << 29) +#define OMAP4_USIM_PBIASLITE_PWRDNZ_SHIFT 28 +#define OMAP4_USIM_PBIASLITE_PWRDNZ_MASK (1 << 28) +#define OMAP4_USIM_PBIASLITE_VMODE_SHIFT 27 +#define OMAP4_USIM_PBIASLITE_VMODE_MASK (1 << 27) +#define OMAP4_MMC1_PWRDNZ_SHIFT 26 +#define OMAP4_MMC1_PWRDNZ_MASK (1 << 26) +#define OMAP4_MMC1_PBIASLITE_HIZ_MODE_SHIFT 25 +#define OMAP4_MMC1_PBIASLITE_HIZ_MODE_MASK (1 << 25) +#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT_SHIFT 24 +#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT_MASK (1 << 24) +#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_SHIFT 23 +#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK (1 << 23) +#define OMAP4_MMC1_PBIASLITE_PWRDNZ_SHIFT 22 +#define OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK (1 << 22) +#define OMAP4_MMC1_PBIASLITE_VMODE_SHIFT 21 +#define OMAP4_MMC1_PBIASLITE_VMODE_MASK (1 << 21) +#define OMAP4_USBC1_ICUSB_PWRDNZ_SHIFT 20 +#define OMAP4_USBC1_ICUSB_PWRDNZ_MASK (1 << 20) + +/* CONTROL_I2C_0 */ +#define OMAP4_I2C4_SDA_GLFENB_SHIFT 31 +#define OMAP4_I2C4_SDA_GLFENB_MASK (1 << 31) +#define OMAP4_I2C4_SDA_LOAD_BITS_SHIFT 29 +#define OMAP4_I2C4_SDA_LOAD_BITS_MASK (0x3 << 29) +#define OMAP4_I2C4_SDA_PULLUPRESX_SHIFT 28 +#define OMAP4_I2C4_SDA_PULLUPRESX_MASK (1 << 28) +#define OMAP4_I2C3_SDA_GLFENB_SHIFT 27 +#define OMAP4_I2C3_SDA_GLFENB_MASK (1 << 27) +#define OMAP4_I2C3_SDA_LOAD_BITS_SHIFT 25 +#define OMAP4_I2C3_SDA_LOAD_BITS_MASK (0x3 << 25) +#define OMAP4_I2C3_SDA_PULLUPRESX_SHIFT 24 +#define OMAP4_I2C3_SDA_PULLUPRESX_MASK (1 << 24) +#define OMAP4_I2C2_SDA_GLFENB_SHIFT 23 +#define OMAP4_I2C2_SDA_GLFENB_MASK (1 << 23) +#define OMAP4_I2C2_SDA_LOAD_BITS_SHIFT 21 +#define OMAP4_I2C2_SDA_LOAD_BITS_MASK (0x3 << 21) +#define OMAP4_I2C2_SDA_PULLUPRESX_SHIFT 20 +#define OMAP4_I2C2_SDA_PULLUPRESX_MASK (1 << 20) +#define OMAP4_I2C1_SDA_GLFENB_SHIFT 19 +#define OMAP4_I2C1_SDA_GLFENB_MASK (1 << 19) +#define OMAP4_I2C1_SDA_LOAD_BITS_SHIFT 17 +#define OMAP4_I2C1_SDA_LOAD_BITS_MASK (0x3 << 17) +#define OMAP4_I2C1_SDA_PULLUPRESX_SHIFT 16 +#define OMAP4_I2C1_SDA_PULLUPRESX_MASK (1 << 16) +#define OMAP4_I2C4_SCL_GLFENB_SHIFT 15 +#define OMAP4_I2C4_SCL_GLFENB_MASK (1 << 15) +#define OMAP4_I2C4_SCL_LOAD_BITS_SHIFT 13 +#define OMAP4_I2C4_SCL_LOAD_BITS_MASK (0x3 << 13) +#define OMAP4_I2C4_SCL_PULLUPRESX_SHIFT 12 +#define OMAP4_I2C4_SCL_PULLUPRESX_MASK (1 << 12) +#define OMAP4_I2C3_SCL_GLFENB_SHIFT 11 +#define OMAP4_I2C3_SCL_GLFENB_MASK (1 << 11) +#define OMAP4_I2C3_SCL_LOAD_BITS_SHIFT 9 +#define OMAP4_I2C3_SCL_LOAD_BITS_MASK (0x3 << 9) +#define OMAP4_I2C3_SCL_PULLUPRESX_SHIFT 8 +#define OMAP4_I2C3_SCL_PULLUPRESX_MASK (1 << 8) +#define OMAP4_I2C2_SCL_GLFENB_SHIFT 7 +#define OMAP4_I2C2_SCL_GLFENB_MASK (1 << 7) +#define OMAP4_I2C2_SCL_LOAD_BITS_SHIFT 5 +#define OMAP4_I2C2_SCL_LOAD_BITS_MASK (0x3 << 5) +#define OMAP4_I2C2_SCL_PULLUPRESX_SHIFT 4 +#define OMAP4_I2C2_SCL_PULLUPRESX_MASK (1 << 4) +#define OMAP4_I2C1_SCL_GLFENB_SHIFT 3 +#define OMAP4_I2C1_SCL_GLFENB_MASK (1 << 3) +#define OMAP4_I2C1_SCL_LOAD_BITS_SHIFT 1 +#define OMAP4_I2C1_SCL_LOAD_BITS_MASK (0x3 << 1) +#define OMAP4_I2C1_SCL_PULLUPRESX_SHIFT 0 +#define OMAP4_I2C1_SCL_PULLUPRESX_MASK (1 << 0) + +/* CONTROL_CAMERA_RX */ +#define OMAP4_CAMERARX_UNIPRO_CTRLCLKEN_SHIFT 31 +#define OMAP4_CAMERARX_UNIPRO_CTRLCLKEN_MASK (1 << 31) +#define OMAP4_CAMERARX_CSI22_LANEENABLE_SHIFT 29 +#define OMAP4_CAMERARX_CSI22_LANEENABLE_MASK (0x3 << 29) +#define OMAP4_CAMERARX_CSI21_LANEENABLE_SHIFT 24 +#define OMAP4_CAMERARX_CSI21_LANEENABLE_MASK (0x1f << 24) +#define OMAP4_CAMERARX_UNIPRO_CAMMODE_SHIFT 22 +#define OMAP4_CAMERARX_UNIPRO_CAMMODE_MASK (0x3 << 22) +#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_SHIFT 21 +#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_MASK (1 << 21) +#define OMAP4_CAMERARX_CSI22_CAMMODE_SHIFT 19 +#define OMAP4_CAMERARX_CSI22_CAMMODE_MASK (0x3 << 19) +#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_SHIFT 18 +#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_MASK (1 << 18) +#define OMAP4_CAMERARX_CSI21_CAMMODE_SHIFT 16 +#define OMAP4_CAMERARX_CSI21_CAMMODE_MASK (0x3 << 16) + +/* CONTROL_AVDAC */ +#define OMAP4_AVDAC_ACEN_SHIFT 31 +#define OMAP4_AVDAC_ACEN_MASK (1 << 31) +#define OMAP4_AVDAC_TVOUTBYPASS_SHIFT 30 +#define OMAP4_AVDAC_TVOUTBYPASS_MASK (1 << 30) +#define OMAP4_AVDAC_INPUTINV_SHIFT 29 +#define OMAP4_AVDAC_INPUTINV_MASK (1 << 29) +#define OMAP4_AVDAC_CTL_SHIFT 13 +#define OMAP4_AVDAC_CTL_MASK (0xffff << 13) +#define OMAP4_AVDAC_CTL_WR_ACK_SHIFT 12 +#define OMAP4_AVDAC_CTL_WR_ACK_MASK (1 << 12) + +/* CONTROL_HDMI_TX_PHY */ +#define OMAP4_HDMITXPHY_PADORDER_SHIFT 31 +#define OMAP4_HDMITXPHY_PADORDER_MASK (1 << 31) +#define OMAP4_HDMITXPHY_TXVALID_SHIFT 30 +#define OMAP4_HDMITXPHY_TXVALID_MASK (1 << 30) +#define OMAP4_HDMITXPHY_ENBYPASSCLK_SHIFT 29 +#define OMAP4_HDMITXPHY_ENBYPASSCLK_MASK (1 << 29) +#define OMAP4_HDMITXPHY_PD_PULLUPDET_SHIFT 28 +#define OMAP4_HDMITXPHY_PD_PULLUPDET_MASK (1 << 28) + +/* CONTROL_MMC2 */ +#define OMAP4_MMC2_FEEDBACK_CLK_SEL_SHIFT 31 +#define OMAP4_MMC2_FEEDBACK_CLK_SEL_MASK (1 << 31) + +/* CONTROL_DSIPHY */ +#define OMAP4_DSI2_LANEENABLE_SHIFT 29 +#define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29) +#define OMAP4_DSI1_LANEENABLE_SHIFT 24 +#define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24) +#define OMAP4_DSI1_PIPD_SHIFT 19 +#define OMAP4_DSI1_PIPD_MASK (0x1f << 19) +#define OMAP4_DSI2_PIPD_SHIFT 14 +#define OMAP4_DSI2_PIPD_MASK (0x1f << 14) + +/* CONTROL_MCBSPLP */ +#define OMAP4_ALBCTRLRX_FSX_SHIFT 31 +#define OMAP4_ALBCTRLRX_FSX_MASK (1 << 31) +#define OMAP4_ALBCTRLRX_CLKX_SHIFT 30 +#define OMAP4_ALBCTRLRX_CLKX_MASK (1 << 30) +#define OMAP4_ABE_MCBSP1_DR_EN_SHIFT 29 +#define OMAP4_ABE_MCBSP1_DR_EN_MASK (1 << 29) + +/* CONTROL_USB2PHYCORE */ +#define OMAP4_USB2PHY_AUTORESUME_EN_SHIFT 31 +#define OMAP4_USB2PHY_AUTORESUME_EN_MASK (1 << 31) +#define OMAP4_USB2PHY_DISCHGDET_SHIFT 30 +#define OMAP4_USB2PHY_DISCHGDET_MASK (1 << 30) +#define OMAP4_USB2PHY_GPIOMODE_SHIFT 29 +#define OMAP4_USB2PHY_GPIOMODE_MASK (1 << 29) +#define OMAP4_USB2PHY_CHG_DET_EXT_CTL_SHIFT 28 +#define OMAP4_USB2PHY_CHG_DET_EXT_CTL_MASK (1 << 28) +#define OMAP4_USB2PHY_RDM_PD_CHGDET_EN_SHIFT 27 +#define OMAP4_USB2PHY_RDM_PD_CHGDET_EN_MASK (1 << 27) +#define OMAP4_USB2PHY_RDP_PU_CHGDET_EN_SHIFT 26 +#define OMAP4_USB2PHY_RDP_PU_CHGDET_EN_MASK (1 << 26) +#define OMAP4_USB2PHY_CHG_VSRC_EN_SHIFT 25 +#define OMAP4_USB2PHY_CHG_VSRC_EN_MASK (1 << 25) +#define OMAP4_USB2PHY_CHG_ISINK_EN_SHIFT 24 +#define OMAP4_USB2PHY_CHG_ISINK_EN_MASK (1 << 24) +#define OMAP4_USB2PHY_CHG_DET_STATUS_SHIFT 21 +#define OMAP4_USB2PHY_CHG_DET_STATUS_MASK (0x7 << 21) +#define OMAP4_USB2PHY_CHG_DET_DM_COMP_SHIFT 20 +#define OMAP4_USB2PHY_CHG_DET_DM_COMP_MASK (1 << 20) +#define OMAP4_USB2PHY_CHG_DET_DP_COMP_SHIFT 19 +#define OMAP4_USB2PHY_CHG_DET_DP_COMP_MASK (1 << 19) +#define OMAP4_USB2PHY_DATADET_SHIFT 18 +#define OMAP4_USB2PHY_DATADET_MASK (1 << 18) +#define OMAP4_USB2PHY_SINKONDP_SHIFT 17 +#define OMAP4_USB2PHY_SINKONDP_MASK (1 << 17) +#define OMAP4_USB2PHY_SRCONDM_SHIFT 16 +#define OMAP4_USB2PHY_SRCONDM_MASK (1 << 16) +#define OMAP4_USB2PHY_RESTARTCHGDET_SHIFT 15 +#define OMAP4_USB2PHY_RESTARTCHGDET_MASK (1 << 15) +#define OMAP4_USB2PHY_CHGDETDONE_SHIFT 14 +#define OMAP4_USB2PHY_CHGDETDONE_MASK (1 << 14) +#define OMAP4_USB2PHY_CHGDETECTED_SHIFT 13 +#define OMAP4_USB2PHY_CHGDETECTED_MASK (1 << 13) +#define OMAP4_USB2PHY_MCPCPUEN_SHIFT 12 +#define OMAP4_USB2PHY_MCPCPUEN_MASK (1 << 12) +#define OMAP4_USB2PHY_MCPCMODEEN_SHIFT 11 +#define OMAP4_USB2PHY_MCPCMODEEN_MASK (1 << 11) +#define OMAP4_USB2PHY_RESETDONEMCLK_SHIFT 10 +#define OMAP4_USB2PHY_RESETDONEMCLK_MASK (1 << 10) +#define OMAP4_USB2PHY_UTMIRESETDONE_SHIFT 9 +#define OMAP4_USB2PHY_UTMIRESETDONE_MASK (1 << 9) +#define OMAP4_USB2PHY_TXBITSTUFFENABLE_SHIFT 8 +#define OMAP4_USB2PHY_TXBITSTUFFENABLE_MASK (1 << 8) +#define OMAP4_USB2PHY_DATAPOLARITYN_SHIFT 7 +#define OMAP4_USB2PHY_DATAPOLARITYN_MASK (1 << 7) +#define OMAP4_USBDPLL_FREQLOCK_SHIFT 6 +#define OMAP4_USBDPLL_FREQLOCK_MASK (1 << 6) +#define OMAP4_USB2PHY_RESETDONETCLK_SHIFT 5 +#define OMAP4_USB2PHY_RESETDONETCLK_MASK (1 << 5) + +/* CONTROL_I2C_1 */ +#define OMAP4_HDMI_DDC_SDA_GLFENB_SHIFT 31 +#define OMAP4_HDMI_DDC_SDA_GLFENB_MASK (1 << 31) +#define OMAP4_HDMI_DDC_SDA_LOAD_BITS_SHIFT 29 +#define OMAP4_HDMI_DDC_SDA_LOAD_BITS_MASK (0x3 << 29) +#define OMAP4_HDMI_DDC_SDA_PULLUPRESX_SHIFT 28 +#define OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK (1 << 28) +#define OMAP4_HDMI_DDC_SCL_GLFENB_SHIFT 27 +#define OMAP4_HDMI_DDC_SCL_GLFENB_MASK (1 << 27) +#define OMAP4_HDMI_DDC_SCL_LOAD_BITS_SHIFT 25 +#define OMAP4_HDMI_DDC_SCL_LOAD_BITS_MASK (0x3 << 25) +#define OMAP4_HDMI_DDC_SCL_PULLUPRESX_SHIFT 24 +#define OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK (1 << 24) +#define OMAP4_HDMI_DDC_SDA_HSMODE_SHIFT 23 +#define OMAP4_HDMI_DDC_SDA_HSMODE_MASK (1 << 23) +#define OMAP4_HDMI_DDC_SDA_NMODE_SHIFT 22 +#define OMAP4_HDMI_DDC_SDA_NMODE_MASK (1 << 22) +#define OMAP4_HDMI_DDC_SCL_HSMODE_SHIFT 21 +#define OMAP4_HDMI_DDC_SCL_HSMODE_MASK (1 << 21) +#define OMAP4_HDMI_DDC_SCL_NMODE_SHIFT 20 +#define OMAP4_HDMI_DDC_SCL_NMODE_MASK (1 << 20) + +/* CONTROL_MMC1 */ +#define OMAP4_SDMMC1_PUSTRENGTH_GRP0_SHIFT 31 +#define OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK (1 << 31) +#define OMAP4_SDMMC1_PUSTRENGTH_GRP1_SHIFT 30 +#define OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK (1 << 30) +#define OMAP4_SDMMC1_PUSTRENGTH_GRP2_SHIFT 29 +#define OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK (1 << 29) +#define OMAP4_SDMMC1_PUSTRENGTH_GRP3_SHIFT 28 +#define OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK (1 << 28) +#define OMAP4_SDMMC1_DR0_SPEEDCTRL_SHIFT 27 +#define OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK (1 << 27) +#define OMAP4_SDMMC1_DR1_SPEEDCTRL_SHIFT 26 +#define OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK (1 << 26) +#define OMAP4_SDMMC1_DR2_SPEEDCTRL_SHIFT 25 +#define OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK (1 << 25) +#define OMAP4_USBC1_DR0_SPEEDCTRL_SHIFT 24 +#define OMAP4_USBC1_DR0_SPEEDCTRL_MASK (1 << 24) +#define OMAP4_USB_FD_CDEN_SHIFT 23 +#define OMAP4_USB_FD_CDEN_MASK (1 << 23) +#define OMAP4_USBC1_ICUSB_DP_PDDIS_SHIFT 22 +#define OMAP4_USBC1_ICUSB_DP_PDDIS_MASK (1 << 22) +#define OMAP4_USBC1_ICUSB_DM_PDDIS_SHIFT 21 +#define OMAP4_USBC1_ICUSB_DM_PDDIS_MASK (1 << 21) + +/* CONTROL_HSI */ +#define OMAP4_HSI1_CALLOOP_SEL_SHIFT 31 +#define OMAP4_HSI1_CALLOOP_SEL_MASK (1 << 31) +#define OMAP4_HSI1_CALMUX_SEL_SHIFT 30 +#define OMAP4_HSI1_CALMUX_SEL_MASK (1 << 30) +#define OMAP4_HSI2_CALLOOP_SEL_SHIFT 29 +#define OMAP4_HSI2_CALLOOP_SEL_MASK (1 << 29) +#define OMAP4_HSI2_CALMUX_SEL_SHIFT 28 +#define OMAP4_HSI2_CALMUX_SEL_MASK (1 << 28) + +/* CONTROL_USB */ +#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN_SHIFT 31 +#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN_MASK (1 << 31) +#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN_SHIFT 30 +#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN_MASK (1 << 30) + +/* CONTROL_HDQ */ +#define OMAP4_HDQ_SIO_PWRDNZ_SHIFT 31 +#define OMAP4_HDQ_SIO_PWRDNZ_MASK (1 << 31) + +/* CONTROL_LPDDR2IO1_0 */ +#define OMAP4_LPDDR2IO1_GR4_SR_SHIFT 30 +#define OMAP4_LPDDR2IO1_GR4_SR_MASK (0x3 << 30) +#define OMAP4_LPDDR2IO1_GR4_I_SHIFT 27 +#define OMAP4_LPDDR2IO1_GR4_I_MASK (0x7 << 27) +#define OMAP4_LPDDR2IO1_GR4_WD_SHIFT 25 +#define OMAP4_LPDDR2IO1_GR4_WD_MASK (0x3 << 25) +#define OMAP4_LPDDR2IO1_GR3_SR_SHIFT 22 +#define OMAP4_LPDDR2IO1_GR3_SR_MASK (0x3 << 22) +#define OMAP4_LPDDR2IO1_GR3_I_SHIFT 19 +#define OMAP4_LPDDR2IO1_GR3_I_MASK (0x7 << 19) +#define OMAP4_LPDDR2IO1_GR3_WD_SHIFT 17 +#define OMAP4_LPDDR2IO1_GR3_WD_MASK (0x3 << 17) +#define OMAP4_LPDDR2IO1_GR2_SR_SHIFT 14 +#define OMAP4_LPDDR2IO1_GR2_SR_MASK (0x3 << 14) +#define OMAP4_LPDDR2IO1_GR2_I_SHIFT 11 +#define OMAP4_LPDDR2IO1_GR2_I_MASK (0x7 << 11) +#define OMAP4_LPDDR2IO1_GR2_WD_SHIFT 9 +#define OMAP4_LPDDR2IO1_GR2_WD_MASK (0x3 << 9) +#define OMAP4_LPDDR2IO1_GR1_SR_SHIFT 6 +#define OMAP4_LPDDR2IO1_GR1_SR_MASK (0x3 << 6) +#define OMAP4_LPDDR2IO1_GR1_I_SHIFT 3 +#define OMAP4_LPDDR2IO1_GR1_I_MASK (0x7 << 3) +#define OMAP4_LPDDR2IO1_GR1_WD_SHIFT 1 +#define OMAP4_LPDDR2IO1_GR1_WD_MASK (0x3 << 1) + +/* CONTROL_LPDDR2IO1_1 */ +#define OMAP4_LPDDR2IO1_GR8_SR_SHIFT 30 +#define OMAP4_LPDDR2IO1_GR8_SR_MASK (0x3 << 30) +#define OMAP4_LPDDR2IO1_GR8_I_SHIFT 27 +#define OMAP4_LPDDR2IO1_GR8_I_MASK (0x7 << 27) +#define OMAP4_LPDDR2IO1_GR8_WD_SHIFT 25 +#define OMAP4_LPDDR2IO1_GR8_WD_MASK (0x3 << 25) +#define OMAP4_LPDDR2IO1_GR7_SR_SHIFT 22 +#define OMAP4_LPDDR2IO1_GR7_SR_MASK (0x3 << 22) +#define OMAP4_LPDDR2IO1_GR7_I_SHIFT 19 +#define OMAP4_LPDDR2IO1_GR7_I_MASK (0x7 << 19) +#define OMAP4_LPDDR2IO1_GR7_WD_SHIFT 17 +#define OMAP4_LPDDR2IO1_GR7_WD_MASK (0x3 << 17) +#define OMAP4_LPDDR2IO1_GR6_SR_SHIFT 14 +#define OMAP4_LPDDR2IO1_GR6_SR_MASK (0x3 << 14) +#define OMAP4_LPDDR2IO1_GR6_I_SHIFT 11 +#define OMAP4_LPDDR2IO1_GR6_I_MASK (0x7 << 11) +#define OMAP4_LPDDR2IO1_GR6_WD_SHIFT 9 +#define OMAP4_LPDDR2IO1_GR6_WD_MASK (0x3 << 9) +#define OMAP4_LPDDR2IO1_GR5_SR_SHIFT 6 +#define OMAP4_LPDDR2IO1_GR5_SR_MASK (0x3 << 6) +#define OMAP4_LPDDR2IO1_GR5_I_SHIFT 3 +#define OMAP4_LPDDR2IO1_GR5_I_MASK (0x7 << 3) +#define OMAP4_LPDDR2IO1_GR5_WD_SHIFT 1 +#define OMAP4_LPDDR2IO1_GR5_WD_MASK (0x3 << 1) + +/* CONTROL_LPDDR2IO1_2 */ +#define OMAP4_LPDDR2IO1_GR11_SR_SHIFT 30 +#define OMAP4_LPDDR2IO1_GR11_SR_MASK (0x3 << 30) +#define OMAP4_LPDDR2IO1_GR11_I_SHIFT 27 +#define OMAP4_LPDDR2IO1_GR11_I_MASK (0x7 << 27) +#define OMAP4_LPDDR2IO1_GR11_WD_SHIFT 25 +#define OMAP4_LPDDR2IO1_GR11_WD_MASK (0x3 << 25) +#define OMAP4_LPDDR2IO1_GR10_SR_SHIFT 22 +#define OMAP4_LPDDR2IO1_GR10_SR_MASK (0x3 << 22) +#define OMAP4_LPDDR2IO1_GR10_I_SHIFT 19 +#define OMAP4_LPDDR2IO1_GR10_I_MASK (0x7 << 19) +#define OMAP4_LPDDR2IO1_GR10_WD_SHIFT 17 +#define OMAP4_LPDDR2IO1_GR10_WD_MASK (0x3 << 17) +#define OMAP4_LPDDR2IO1_GR9_SR_SHIFT 14 +#define OMAP4_LPDDR2IO1_GR9_SR_MASK (0x3 << 14) +#define OMAP4_LPDDR2IO1_GR9_I_SHIFT 11 +#define OMAP4_LPDDR2IO1_GR9_I_MASK (0x7 << 11) +#define OMAP4_LPDDR2IO1_GR9_WD_SHIFT 9 +#define OMAP4_LPDDR2IO1_GR9_WD_MASK (0x3 << 9) + +/* CONTROL_LPDDR2IO1_3 */ +#define OMAP4_LPDDR21_VREF_CA_CCAP0_SHIFT 31 +#define OMAP4_LPDDR21_VREF_CA_CCAP0_MASK (1 << 31) +#define OMAP4_LPDDR21_VREF_CA_CCAP1_SHIFT 30 +#define OMAP4_LPDDR21_VREF_CA_CCAP1_MASK (1 << 30) +#define OMAP4_LPDDR21_VREF_CA_INT_CCAP0_SHIFT 29 +#define OMAP4_LPDDR21_VREF_CA_INT_CCAP0_MASK (1 << 29) +#define OMAP4_LPDDR21_VREF_CA_INT_CCAP1_SHIFT 28 +#define OMAP4_LPDDR21_VREF_CA_INT_CCAP1_MASK (1 << 28) +#define OMAP4_LPDDR21_VREF_CA_INT_TAP0_SHIFT 27 +#define OMAP4_LPDDR21_VREF_CA_INT_TAP0_MASK (1 << 27) +#define OMAP4_LPDDR21_VREF_CA_INT_TAP1_SHIFT 26 +#define OMAP4_LPDDR21_VREF_CA_INT_TAP1_MASK (1 << 26) +#define OMAP4_LPDDR21_VREF_CA_TAP0_SHIFT 25 +#define OMAP4_LPDDR21_VREF_CA_TAP0_MASK (1 << 25) +#define OMAP4_LPDDR21_VREF_CA_TAP1_SHIFT 24 +#define OMAP4_LPDDR21_VREF_CA_TAP1_MASK (1 << 24) +#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP0_SHIFT 23 +#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP0_MASK (1 << 23) +#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP1_SHIFT 22 +#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP1_MASK (1 << 22) +#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP0_SHIFT 21 +#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP0_MASK (1 << 21) +#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP1_SHIFT 20 +#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP1_MASK (1 << 20) +#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP0_SHIFT 19 +#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP0_MASK (1 << 19) +#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP1_SHIFT 18 +#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP1_MASK (1 << 18) +#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP0_SHIFT 17 +#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP0_MASK (1 << 17) +#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP1_SHIFT 16 +#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP1_MASK (1 << 16) +#define OMAP4_LPDDR21_VREF_DQ_CCAP0_SHIFT 15 +#define OMAP4_LPDDR21_VREF_DQ_CCAP0_MASK (1 << 15) +#define OMAP4_LPDDR21_VREF_DQ_CCAP1_SHIFT 14 +#define OMAP4_LPDDR21_VREF_DQ_CCAP1_MASK (1 << 14) +#define OMAP4_LPDDR21_VREF_DQ_TAP0_SHIFT 13 +#define OMAP4_LPDDR21_VREF_DQ_TAP0_MASK (1 << 13) +#define OMAP4_LPDDR21_VREF_DQ_TAP1_SHIFT 12 +#define OMAP4_LPDDR21_VREF_DQ_TAP1_MASK (1 << 12) + +/* CONTROL_LPDDR2IO2_0 */ +#define OMAP4_LPDDR2IO2_GR4_SR_SHIFT 30 +#define OMAP4_LPDDR2IO2_GR4_SR_MASK (0x3 << 30) +#define OMAP4_LPDDR2IO2_GR4_I_SHIFT 27 +#define OMAP4_LPDDR2IO2_GR4_I_MASK (0x7 << 27) +#define OMAP4_LPDDR2IO2_GR4_WD_SHIFT 25 +#define OMAP4_LPDDR2IO2_GR4_WD_MASK (0x3 << 25) +#define OMAP4_LPDDR2IO2_GR3_SR_SHIFT 22 +#define OMAP4_LPDDR2IO2_GR3_SR_MASK (0x3 << 22) +#define OMAP4_LPDDR2IO2_GR3_I_SHIFT 19 +#define OMAP4_LPDDR2IO2_GR3_I_MASK (0x7 << 19) +#define OMAP4_LPDDR2IO2_GR3_WD_SHIFT 17 +#define OMAP4_LPDDR2IO2_GR3_WD_MASK (0x3 << 17) +#define OMAP4_LPDDR2IO2_GR2_SR_SHIFT 14 +#define OMAP4_LPDDR2IO2_GR2_SR_MASK (0x3 << 14) +#define OMAP4_LPDDR2IO2_GR2_I_SHIFT 11 +#define OMAP4_LPDDR2IO2_GR2_I_MASK (0x7 << 11) +#define OMAP4_LPDDR2IO2_GR2_WD_SHIFT 9 +#define OMAP4_LPDDR2IO2_GR2_WD_MASK (0x3 << 9) +#define OMAP4_LPDDR2IO2_GR1_SR_SHIFT 6 +#define OMAP4_LPDDR2IO2_GR1_SR_MASK (0x3 << 6) +#define OMAP4_LPDDR2IO2_GR1_I_SHIFT 3 +#define OMAP4_LPDDR2IO2_GR1_I_MASK (0x7 << 3) +#define OMAP4_LPDDR2IO2_GR1_WD_SHIFT 1 +#define OMAP4_LPDDR2IO2_GR1_WD_MASK (0x3 << 1) + +/* CONTROL_LPDDR2IO2_1 */ +#define OMAP4_LPDDR2IO2_GR8_SR_SHIFT 30 +#define OMAP4_LPDDR2IO2_GR8_SR_MASK (0x3 << 30) +#define OMAP4_LPDDR2IO2_GR8_I_SHIFT 27 +#define OMAP4_LPDDR2IO2_GR8_I_MASK (0x7 << 27) +#define OMAP4_LPDDR2IO2_GR8_WD_SHIFT 25 +#define OMAP4_LPDDR2IO2_GR8_WD_MASK (0x3 << 25) +#define OMAP4_LPDDR2IO2_GR7_SR_SHIFT 22 +#define OMAP4_LPDDR2IO2_GR7_SR_MASK (0x3 << 22) +#define OMAP4_LPDDR2IO2_GR7_I_SHIFT 19 +#define OMAP4_LPDDR2IO2_GR7_I_MASK (0x7 << 19) +#define OMAP4_LPDDR2IO2_GR7_WD_SHIFT 17 +#define OMAP4_LPDDR2IO2_GR7_WD_MASK (0x3 << 17) +#define OMAP4_LPDDR2IO2_GR6_SR_SHIFT 14 +#define OMAP4_LPDDR2IO2_GR6_SR_MASK (0x3 << 14) +#define OMAP4_LPDDR2IO2_GR6_I_SHIFT 11 +#define OMAP4_LPDDR2IO2_GR6_I_MASK (0x7 << 11) +#define OMAP4_LPDDR2IO2_GR6_WD_SHIFT 9 +#define OMAP4_LPDDR2IO2_GR6_WD_MASK (0x3 << 9) +#define OMAP4_LPDDR2IO2_GR5_SR_SHIFT 6 +#define OMAP4_LPDDR2IO2_GR5_SR_MASK (0x3 << 6) +#define OMAP4_LPDDR2IO2_GR5_I_SHIFT 3 +#define OMAP4_LPDDR2IO2_GR5_I_MASK (0x7 << 3) +#define OMAP4_LPDDR2IO2_GR5_WD_SHIFT 1 +#define OMAP4_LPDDR2IO2_GR5_WD_MASK (0x3 << 1) + +/* CONTROL_LPDDR2IO2_2 */ +#define OMAP4_LPDDR2IO2_GR11_SR_SHIFT 30 +#define OMAP4_LPDDR2IO2_GR11_SR_MASK (0x3 << 30) +#define OMAP4_LPDDR2IO2_GR11_I_SHIFT 27 +#define OMAP4_LPDDR2IO2_GR11_I_MASK (0x7 << 27) +#define OMAP4_LPDDR2IO2_GR11_WD_SHIFT 25 +#define OMAP4_LPDDR2IO2_GR11_WD_MASK (0x3 << 25) +#define OMAP4_LPDDR2IO2_GR10_SR_SHIFT 22 +#define OMAP4_LPDDR2IO2_GR10_SR_MASK (0x3 << 22) +#define OMAP4_LPDDR2IO2_GR10_I_SHIFT 19 +#define OMAP4_LPDDR2IO2_GR10_I_MASK (0x7 << 19) +#define OMAP4_LPDDR2IO2_GR10_WD_SHIFT 17 +#define OMAP4_LPDDR2IO2_GR10_WD_MASK (0x3 << 17) +#define OMAP4_LPDDR2IO2_GR9_SR_SHIFT 14 +#define OMAP4_LPDDR2IO2_GR9_SR_MASK (0x3 << 14) +#define OMAP4_LPDDR2IO2_GR9_I_SHIFT 11 +#define OMAP4_LPDDR2IO2_GR9_I_MASK (0x7 << 11) +#define OMAP4_LPDDR2IO2_GR9_WD_SHIFT 9 +#define OMAP4_LPDDR2IO2_GR9_WD_MASK (0x3 << 9) + +/* CONTROL_LPDDR2IO2_3 */ +#define OMAP4_LPDDR22_VREF_CA_CCAP0_SHIFT 31 +#define OMAP4_LPDDR22_VREF_CA_CCAP0_MASK (1 << 31) +#define OMAP4_LPDDR22_VREF_CA_CCAP1_SHIFT 30 +#define OMAP4_LPDDR22_VREF_CA_CCAP1_MASK (1 << 30) +#define OMAP4_LPDDR22_VREF_CA_INT_CCAP0_SHIFT 29 +#define OMAP4_LPDDR22_VREF_CA_INT_CCAP0_MASK (1 << 29) +#define OMAP4_LPDDR22_VREF_CA_INT_CCAP1_SHIFT 28 +#define OMAP4_LPDDR22_VREF_CA_INT_CCAP1_MASK (1 << 28) +#define OMAP4_LPDDR22_VREF_CA_INT_TAP0_SHIFT 27 +#define OMAP4_LPDDR22_VREF_CA_INT_TAP0_MASK (1 << 27) +#define OMAP4_LPDDR22_VREF_CA_INT_TAP1_SHIFT 26 +#define OMAP4_LPDDR22_VREF_CA_INT_TAP1_MASK (1 << 26) +#define OMAP4_LPDDR22_VREF_CA_TAP0_SHIFT 25 +#define OMAP4_LPDDR22_VREF_CA_TAP0_MASK (1 << 25) +#define OMAP4_LPDDR22_VREF_CA_TAP1_SHIFT 24 +#define OMAP4_LPDDR22_VREF_CA_TAP1_MASK (1 << 24) +#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP0_SHIFT 23 +#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP0_MASK (1 << 23) +#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP1_SHIFT 22 +#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP1_MASK (1 << 22) +#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP0_SHIFT 21 +#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP0_MASK (1 << 21) +#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP1_SHIFT 20 +#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP1_MASK (1 << 20) +#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP0_SHIFT 19 +#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP0_MASK (1 << 19) +#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP1_SHIFT 18 +#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP1_MASK (1 << 18) +#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP0_SHIFT 17 +#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP0_MASK (1 << 17) +#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP1_SHIFT 16 +#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP1_MASK (1 << 16) +#define OMAP4_LPDDR22_VREF_DQ_CCAP0_SHIFT 15 +#define OMAP4_LPDDR22_VREF_DQ_CCAP0_MASK (1 << 15) +#define OMAP4_LPDDR22_VREF_DQ_CCAP1_SHIFT 14 +#define OMAP4_LPDDR22_VREF_DQ_CCAP1_MASK (1 << 14) +#define OMAP4_LPDDR22_VREF_DQ_TAP0_SHIFT 13 +#define OMAP4_LPDDR22_VREF_DQ_TAP0_MASK (1 << 13) +#define OMAP4_LPDDR22_VREF_DQ_TAP1_SHIFT 12 +#define OMAP4_LPDDR22_VREF_DQ_TAP1_MASK (1 << 12) + +/* CONTROL_BUS_HOLD */ +#define OMAP4_ABE_DMIC_DIN3_EN_SHIFT 31 +#define OMAP4_ABE_DMIC_DIN3_EN_MASK (1 << 31) +#define OMAP4_MCSPI1_CS3_EN_SHIFT 30 +#define OMAP4_MCSPI1_CS3_EN_MASK (1 << 30) + +/* CONTROL_C2C */ +#define OMAP4_MIRROR_MODE_EN_SHIFT 31 +#define OMAP4_MIRROR_MODE_EN_MASK (1 << 31) +#define OMAP4_C2C_SPARE_SHIFT 24 +#define OMAP4_C2C_SPARE_MASK (0x7f << 24) + +/* CORE_CONTROL_SPARE_RW */ +#define OMAP4_CORE_CONTROL_SPARE_RW_SHIFT 0 +#define OMAP4_CORE_CONTROL_SPARE_RW_MASK (0xffffffff << 0) + +/* CORE_CONTROL_SPARE_R */ +#define OMAP4_CORE_CONTROL_SPARE_R_SHIFT 0 +#define OMAP4_CORE_CONTROL_SPARE_R_MASK (0xffffffff << 0) + +/* CORE_CONTROL_SPARE_R_C0 */ +#define OMAP4_CORE_CONTROL_SPARE_R_C0_SHIFT 31 +#define OMAP4_CORE_CONTROL_SPARE_R_C0_MASK (1 << 31) +#define OMAP4_CORE_CONTROL_SPARE_R_C1_SHIFT 30 +#define OMAP4_CORE_CONTROL_SPARE_R_C1_MASK (1 << 30) +#define OMAP4_CORE_CONTROL_SPARE_R_C2_SHIFT 29 +#define OMAP4_CORE_CONTROL_SPARE_R_C2_MASK (1 << 29) +#define OMAP4_CORE_CONTROL_SPARE_R_C3_SHIFT 28 +#define OMAP4_CORE_CONTROL_SPARE_R_C3_MASK (1 << 28) +#define OMAP4_CORE_CONTROL_SPARE_R_C4_SHIFT 27 +#define OMAP4_CORE_CONTROL_SPARE_R_C4_MASK (1 << 27) +#define OMAP4_CORE_CONTROL_SPARE_R_C5_SHIFT 26 +#define OMAP4_CORE_CONTROL_SPARE_R_C5_MASK (1 << 26) +#define OMAP4_CORE_CONTROL_SPARE_R_C6_SHIFT 25 +#define OMAP4_CORE_CONTROL_SPARE_R_C6_MASK (1 << 25) +#define OMAP4_CORE_CONTROL_SPARE_R_C7_SHIFT 24 +#define OMAP4_CORE_CONTROL_SPARE_R_C7_MASK (1 << 24) + +/* CONTROL_EFUSE_1 */ +#define OMAP4_AVDAC_TRIM_BYTE3_SHIFT 24 +#define OMAP4_AVDAC_TRIM_BYTE3_MASK (0x7f << 24) +#define OMAP4_AVDAC_TRIM_BYTE2_SHIFT 16 +#define OMAP4_AVDAC_TRIM_BYTE2_MASK (0xff << 16) +#define OMAP4_AVDAC_TRIM_BYTE1_SHIFT 8 +#define OMAP4_AVDAC_TRIM_BYTE1_MASK (0xff << 8) +#define OMAP4_AVDAC_TRIM_BYTE0_SHIFT 0 +#define OMAP4_AVDAC_TRIM_BYTE0_MASK (0xff << 0) + +/* CONTROL_EFUSE_2 */ +#define OMAP4_EFUSE_SMART2TEST_P0_SHIFT 31 +#define OMAP4_EFUSE_SMART2TEST_P0_MASK (1 << 31) +#define OMAP4_EFUSE_SMART2TEST_P1_SHIFT 30 +#define OMAP4_EFUSE_SMART2TEST_P1_MASK (1 << 30) +#define OMAP4_EFUSE_SMART2TEST_P2_SHIFT 29 +#define OMAP4_EFUSE_SMART2TEST_P2_MASK (1 << 29) +#define OMAP4_EFUSE_SMART2TEST_P3_SHIFT 28 +#define OMAP4_EFUSE_SMART2TEST_P3_MASK (1 << 28) +#define OMAP4_EFUSE_SMART2TEST_N0_SHIFT 27 +#define OMAP4_EFUSE_SMART2TEST_N0_MASK (1 << 27) +#define OMAP4_EFUSE_SMART2TEST_N1_SHIFT 26 +#define OMAP4_EFUSE_SMART2TEST_N1_MASK (1 << 26) +#define OMAP4_EFUSE_SMART2TEST_N2_SHIFT 25 +#define OMAP4_EFUSE_SMART2TEST_N2_MASK (1 << 25) +#define OMAP4_EFUSE_SMART2TEST_N3_SHIFT 24 +#define OMAP4_EFUSE_SMART2TEST_N3_MASK (1 << 24) +#define OMAP4_LPDDR2_PTV_N1_SHIFT 23 +#define OMAP4_LPDDR2_PTV_N1_MASK (1 << 23) +#define OMAP4_LPDDR2_PTV_N2_SHIFT 22 +#define OMAP4_LPDDR2_PTV_N2_MASK (1 << 22) +#define OMAP4_LPDDR2_PTV_N3_SHIFT 21 +#define OMAP4_LPDDR2_PTV_N3_MASK (1 << 21) +#define OMAP4_LPDDR2_PTV_N4_SHIFT 20 +#define OMAP4_LPDDR2_PTV_N4_MASK (1 << 20) +#define OMAP4_LPDDR2_PTV_N5_SHIFT 19 +#define OMAP4_LPDDR2_PTV_N5_MASK (1 << 19) +#define OMAP4_LPDDR2_PTV_P1_SHIFT 18 +#define OMAP4_LPDDR2_PTV_P1_MASK (1 << 18) +#define OMAP4_LPDDR2_PTV_P2_SHIFT 17 +#define OMAP4_LPDDR2_PTV_P2_MASK (1 << 17) +#define OMAP4_LPDDR2_PTV_P3_SHIFT 16 +#define OMAP4_LPDDR2_PTV_P3_MASK (1 << 16) +#define OMAP4_LPDDR2_PTV_P4_SHIFT 15 +#define OMAP4_LPDDR2_PTV_P4_MASK (1 << 15) +#define OMAP4_LPDDR2_PTV_P5_SHIFT 14 +#define OMAP4_LPDDR2_PTV_P5_MASK (1 << 14) + +/* CONTROL_EFUSE_3 */ +#define OMAP4_STD_FUSE_SPARE_1_SHIFT 24 +#define OMAP4_STD_FUSE_SPARE_1_MASK (0xff << 24) +#define OMAP4_STD_FUSE_SPARE_2_SHIFT 16 +#define OMAP4_STD_FUSE_SPARE_2_MASK (0xff << 16) +#define OMAP4_STD_FUSE_SPARE_3_SHIFT 8 +#define OMAP4_STD_FUSE_SPARE_3_MASK (0xff << 8) +#define OMAP4_STD_FUSE_SPARE_4_SHIFT 0 +#define OMAP4_STD_FUSE_SPARE_4_MASK (0xff << 0) + +/* CONTROL_EFUSE_4 */ +#define OMAP4_STD_FUSE_SPARE_5_SHIFT 24 +#define OMAP4_STD_FUSE_SPARE_5_MASK (0xff << 24) +#define OMAP4_STD_FUSE_SPARE_6_SHIFT 16 +#define OMAP4_STD_FUSE_SPARE_6_MASK (0xff << 16) +#define OMAP4_STD_FUSE_SPARE_7_SHIFT 8 +#define OMAP4_STD_FUSE_SPARE_7_MASK (0xff << 8) +#define OMAP4_STD_FUSE_SPARE_8_SHIFT 0 +#define OMAP4_STD_FUSE_SPARE_8_MASK (0xff << 0) + +#endif diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h new file mode 100644 index 0000000..17c9b37 --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h @@ -0,0 +1,236 @@ +/* + * OMAP44xx CTRL_MODULE_PAD_WKUP registers and bitfields + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * + * Benoit Cousson (b-cousson@ti.com) + * Santosh Shilimkar (santosh.shilimkar@ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H +#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H + + +/* Base address */ +#define OMAP4_CTRL_MODULE_PAD_WKUP 0x4a31e000 + +/* Registers offset */ +#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_REVISION 0x0000 +#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_HWINFO 0x0004 +#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_SYSCONFIG 0x0010 +#define OMAP4_CTRL_MODULE_PAD_WKUP_PADCONF_WAKEUPEVENT_0 0x007c +#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_0 0x05a0 +#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_1 0x05a4 +#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_PADCONF_MODE 0x05a8 +#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_XTAL_OSCILLATOR 0x05ac +#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_USIMIO 0x0600 +#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2 0x0604 +#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_JTAG 0x0608 +#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SYS 0x060c +#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_RW 0x0614 +#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R 0x0618 +#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R_C0 0x061c + +/* Registers shifts and masks */ + +/* IP_REVISION */ +#define OMAP4_IP_REV_SCHEME_SHIFT 30 +#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30) +#define OMAP4_IP_REV_FUNC_SHIFT 16 +#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16) +#define OMAP4_IP_REV_RTL_SHIFT 11 +#define OMAP4_IP_REV_RTL_MASK (0x1f << 11) +#define OMAP4_IP_REV_MAJOR_SHIFT 8 +#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8) +#define OMAP4_IP_REV_CUSTOM_SHIFT 6 +#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6) +#define OMAP4_IP_REV_MINOR_SHIFT 0 +#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0) + +/* IP_HWINFO */ +#define OMAP4_IP_HWINFO_SHIFT 0 +#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0) + +/* IP_SYSCONFIG */ +#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2 +#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2) + +/* PADCONF_WAKEUPEVENT_0 */ +#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_SHIFT 24 +#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_MASK (1 << 24) +#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_SHIFT 23 +#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_MASK (1 << 23) +#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_SHIFT 22 +#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_MASK (1 << 22) +#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_SHIFT 21 +#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_MASK (1 << 21) +#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_SHIFT 20 +#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_MASK (1 << 20) +#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_SHIFT 19 +#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_MASK (1 << 19) +#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_SHIFT 18 +#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_MASK (1 << 18) +#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_SHIFT 17 +#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_MASK (1 << 17) +#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_SHIFT 16 +#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 16) +#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_SHIFT 15 +#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 15) +#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_SHIFT 14 +#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_MASK (1 << 14) +#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_SHIFT 13 +#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_MASK (1 << 13) +#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_SHIFT 12 +#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 12) +#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_SHIFT 11 +#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 11) +#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_SHIFT 10 +#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 10) +#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_SHIFT 9 +#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 9) +#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_SHIFT 8 +#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 8) +#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_SHIFT 7 +#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_MASK (1 << 7) +#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_SHIFT 6 +#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 6) +#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_SHIFT 5 +#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 5) +#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_SHIFT 4 +#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_MASK (1 << 4) +#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_SHIFT 3 +#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_MASK (1 << 3) +#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_SHIFT 2 +#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_MASK (1 << 2) +#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_SHIFT 1 +#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 1) +#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_SHIFT 0 +#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_MASK (1 << 0) + +/* CONTROL_SMART1NOPMIO_PADCONF_0 */ +#define OMAP4_FREF_DR0_SC_SHIFT 30 +#define OMAP4_FREF_DR0_SC_MASK (0x3 << 30) +#define OMAP4_FREF_DR1_SC_SHIFT 28 +#define OMAP4_FREF_DR1_SC_MASK (0x3 << 28) +#define OMAP4_FREF_DR4_SC_SHIFT 26 +#define OMAP4_FREF_DR4_SC_MASK (0x3 << 26) +#define OMAP4_FREF_DR5_SC_SHIFT 24 +#define OMAP4_FREF_DR5_SC_MASK (0x3 << 24) +#define OMAP4_FREF_DR6_SC_SHIFT 22 +#define OMAP4_FREF_DR6_SC_MASK (0x3 << 22) +#define OMAP4_FREF_DR7_SC_SHIFT 20 +#define OMAP4_FREF_DR7_SC_MASK (0x3 << 20) +#define OMAP4_GPIO_DR7_SC_SHIFT 18 +#define OMAP4_GPIO_DR7_SC_MASK (0x3 << 18) +#define OMAP4_DPM_DR0_SC_SHIFT 14 +#define OMAP4_DPM_DR0_SC_MASK (0x3 << 14) +#define OMAP4_SIM_DR0_SC_SHIFT 12 +#define OMAP4_SIM_DR0_SC_MASK (0x3 << 12) + +/* CONTROL_SMART1NOPMIO_PADCONF_1 */ +#define OMAP4_FREF_DR0_LB_SHIFT 30 +#define OMAP4_FREF_DR0_LB_MASK (0x3 << 30) +#define OMAP4_FREF_DR1_LB_SHIFT 28 +#define OMAP4_FREF_DR1_LB_MASK (0x3 << 28) +#define OMAP4_FREF_DR4_LB_SHIFT 26 +#define OMAP4_FREF_DR4_LB_MASK (0x3 << 26) +#define OMAP4_FREF_DR5_LB_SHIFT 24 +#define OMAP4_FREF_DR5_LB_MASK (0x3 << 24) +#define OMAP4_FREF_DR6_LB_SHIFT 22 +#define OMAP4_FREF_DR6_LB_MASK (0x3 << 22) +#define OMAP4_FREF_DR7_LB_SHIFT 20 +#define OMAP4_FREF_DR7_LB_MASK (0x3 << 20) +#define OMAP4_GPIO_DR7_LB_SHIFT 18 +#define OMAP4_GPIO_DR7_LB_MASK (0x3 << 18) +#define OMAP4_DPM_DR0_LB_SHIFT 14 +#define OMAP4_DPM_DR0_LB_MASK (0x3 << 14) +#define OMAP4_SIM_DR0_LB_SHIFT 12 +#define OMAP4_SIM_DR0_LB_MASK (0x3 << 12) + +/* CONTROL_PADCONF_MODE */ +#define OMAP4_VDDS_DV_FREF_SHIFT 31 +#define OMAP4_VDDS_DV_FREF_MASK (1 << 31) +#define OMAP4_VDDS_DV_BANK2_SHIFT 30 +#define OMAP4_VDDS_DV_BANK2_MASK (1 << 30) + +/* CONTROL_XTAL_OSCILLATOR */ +#define OMAP4_OSCILLATOR_BOOST_SHIFT 31 +#define OMAP4_OSCILLATOR_BOOST_MASK (1 << 31) +#define OMAP4_OSCILLATOR_OS_OUT_SHIFT 30 +#define OMAP4_OSCILLATOR_OS_OUT_MASK (1 << 30) + +/* CONTROL_USIMIO */ +#define OMAP4_PAD_USIM_CLK_LOW_SHIFT 31 +#define OMAP4_PAD_USIM_CLK_LOW_MASK (1 << 31) +#define OMAP4_PAD_USIM_RST_LOW_SHIFT 29 +#define OMAP4_PAD_USIM_RST_LOW_MASK (1 << 29) +#define OMAP4_USIM_PWRDNZ_SHIFT 28 +#define OMAP4_USIM_PWRDNZ_MASK (1 << 28) + +/* CONTROL_I2C_2 */ +#define OMAP4_SR_SDA_GLFENB_SHIFT 31 +#define OMAP4_SR_SDA_GLFENB_MASK (1 << 31) +#define OMAP4_SR_SDA_LOAD_BITS_SHIFT 29 +#define OMAP4_SR_SDA_LOAD_BITS_MASK (0x3 << 29) +#define OMAP4_SR_SDA_PULLUPRESX_SHIFT 28 +#define OMAP4_SR_SDA_PULLUPRESX_MASK (1 << 28) +#define OMAP4_SR_SCL_GLFENB_SHIFT 27 +#define OMAP4_SR_SCL_GLFENB_MASK (1 << 27) +#define OMAP4_SR_SCL_LOAD_BITS_SHIFT 25 +#define OMAP4_SR_SCL_LOAD_BITS_MASK (0x3 << 25) +#define OMAP4_SR_SCL_PULLUPRESX_SHIFT 24 +#define OMAP4_SR_SCL_PULLUPRESX_MASK (1 << 24) + +/* CONTROL_JTAG */ +#define OMAP4_JTAG_NTRST_EN_SHIFT 31 +#define OMAP4_JTAG_NTRST_EN_MASK (1 << 31) +#define OMAP4_JTAG_TCK_EN_SHIFT 30 +#define OMAP4_JTAG_TCK_EN_MASK (1 << 30) +#define OMAP4_JTAG_RTCK_EN_SHIFT 29 +#define OMAP4_JTAG_RTCK_EN_MASK (1 << 29) +#define OMAP4_JTAG_TDI_EN_SHIFT 28 +#define OMAP4_JTAG_TDI_EN_MASK (1 << 28) +#define OMAP4_JTAG_TDO_EN_SHIFT 27 +#define OMAP4_JTAG_TDO_EN_MASK (1 << 27) + +/* CONTROL_SYS */ +#define OMAP4_SYS_NRESWARM_PIPU_SHIFT 31 +#define OMAP4_SYS_NRESWARM_PIPU_MASK (1 << 31) + +/* WKUP_CONTROL_SPARE_RW */ +#define OMAP4_WKUP_CONTROL_SPARE_RW_SHIFT 0 +#define OMAP4_WKUP_CONTROL_SPARE_RW_MASK (0xffffffff << 0) + +/* WKUP_CONTROL_SPARE_R */ +#define OMAP4_WKUP_CONTROL_SPARE_R_SHIFT 0 +#define OMAP4_WKUP_CONTROL_SPARE_R_MASK (0xffffffff << 0) + +/* WKUP_CONTROL_SPARE_R_C0 */ +#define OMAP4_WKUP_CONTROL_SPARE_R_C0_SHIFT 31 +#define OMAP4_WKUP_CONTROL_SPARE_R_C0_MASK (1 << 31) +#define OMAP4_WKUP_CONTROL_SPARE_R_C1_SHIFT 30 +#define OMAP4_WKUP_CONTROL_SPARE_R_C1_MASK (1 << 30) +#define OMAP4_WKUP_CONTROL_SPARE_R_C2_SHIFT 29 +#define OMAP4_WKUP_CONTROL_SPARE_R_C2_MASK (1 << 29) +#define OMAP4_WKUP_CONTROL_SPARE_R_C3_SHIFT 28 +#define OMAP4_WKUP_CONTROL_SPARE_R_C3_MASK (1 << 28) +#define OMAP4_WKUP_CONTROL_SPARE_R_C4_SHIFT 27 +#define OMAP4_WKUP_CONTROL_SPARE_R_C4_MASK (1 << 27) +#define OMAP4_WKUP_CONTROL_SPARE_R_C5_SHIFT 26 +#define OMAP4_WKUP_CONTROL_SPARE_R_C5_MASK (1 << 26) +#define OMAP4_WKUP_CONTROL_SPARE_R_C6_SHIFT 25 +#define OMAP4_WKUP_CONTROL_SPARE_R_C6_MASK (1 << 25) +#define OMAP4_WKUP_CONTROL_SPARE_R_C7_SHIFT 24 +#define OMAP4_WKUP_CONTROL_SPARE_R_C7_MASK (1 << 24) + +#endif diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h new file mode 100644 index 0000000..a0af9ba --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h @@ -0,0 +1,92 @@ +/* + * OMAP44xx CTRL_MODULE_WKUP registers and bitfields + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * + * Benoit Cousson (b-cousson@ti.com) + * Santosh Shilimkar (santosh.shilimkar@ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_WKUP_44XX_H +#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_WKUP_44XX_H + + +/* Base address */ +#define OMAP4_CTRL_MODULE_WKUP 0x4a30c000 + +/* Registers offset */ +#define OMAP4_CTRL_MODULE_WKUP_IP_REVISION 0x0000 +#define OMAP4_CTRL_MODULE_WKUP_IP_HWINFO 0x0004 +#define OMAP4_CTRL_MODULE_WKUP_IP_SYSCONFIG 0x0010 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_0 0x0460 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_1 0x0464 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_2 0x0468 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_3 0x046c +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_4 0x0470 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_5 0x0474 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_6 0x0478 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_7 0x047c +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_8 0x0480 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_9 0x0484 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_10 0x0488 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_11 0x048c +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_12 0x0490 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_13 0x0494 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_14 0x0498 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_15 0x049c +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_16 0x04a0 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_17 0x04a4 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_18 0x04a8 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_19 0x04ac +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_20 0x04b0 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_21 0x04b4 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_22 0x04b8 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_23 0x04bc +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_24 0x04c0 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_25 0x04c4 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_26 0x04c8 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_27 0x04cc +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_28 0x04d0 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_29 0x04d4 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_30 0x04d8 +#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_31 0x04dc + +/* Registers shifts and masks */ + +/* IP_REVISION */ +#define OMAP4_IP_REV_SCHEME_SHIFT 30 +#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30) +#define OMAP4_IP_REV_FUNC_SHIFT 16 +#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16) +#define OMAP4_IP_REV_RTL_SHIFT 11 +#define OMAP4_IP_REV_RTL_MASK (0x1f << 11) +#define OMAP4_IP_REV_MAJOR_SHIFT 8 +#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8) +#define OMAP4_IP_REV_CUSTOM_SHIFT 6 +#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6) +#define OMAP4_IP_REV_MINOR_SHIFT 0 +#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0) + +/* IP_HWINFO */ +#define OMAP4_IP_HWINFO_SHIFT 0 +#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0) + +/* IP_SYSCONFIG */ +#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2 +#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2) + +/* CONF_DEBUG_SEL_TST_0 */ +#define OMAP4_WKUP_MODE_SHIFT 0 +#define OMAP4_WKUP_MODE_MASK (1 << 0) + +#endif diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/plat-omap/include/plat/control.h index 2916b7e..f571af7 100644 --- a/arch/arm/plat-omap/include/plat/control.h +++ b/arch/arm/plat-omap/include/plat/control.h @@ -17,6 +17,10 @@ #define __ASM_ARCH_CONTROL_H #include +#include +#include +#include +#include #ifndef __ASSEMBLY__ #define OMAP242X_CTRL_REGADDR(reg) \ -- cgit v1.1 From dcf5ef3f42fbc0c62043b4c466d679fca32f1b9f Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Mon, 27 Sep 2010 14:02:58 -0600 Subject: omap4: control: Fix the control module register accesses This patch has multiple fixes together. To ensure that git bisect work across commits, all changes are clubbed together 1. Move the common control base address to control core 2. Remove the manually coeded defines and use the ones from headers. 3. Fix the the status register define in id.c for OMAP4 4. Fix all the register define in hsmmc.c 5. Use the control pad accessor API for omap4 hsmmc register accesses Signed-off-by: Benoit Cousson Signed-off-by: Santosh Shilimkar Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/hsmmc.c | 67 +++++++++++++++++-------------- arch/arm/mach-omap2/id.c | 2 +- arch/arm/plat-omap/common.c | 2 +- arch/arm/plat-omap/include/plat/control.h | 23 ----------- 4 files changed, 38 insertions(+), 56 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c index c8f647b..87bdb7b 100644 --- a/arch/arm/mach-omap2/hsmmc.c +++ b/arch/arm/mach-omap2/hsmmc.c @@ -135,10 +135,11 @@ static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot, * * FIXME handle VMMC1A as needed ... */ - reg = omap_ctrl_readl(control_pbias_offset); - reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ | OMAP4_MMC1_PWRDNZ | - OMAP4_USBC1_ICUSB_PWRDNZ); - omap_ctrl_writel(reg, control_pbias_offset); + reg = omap4_ctrl_pad_readl(control_pbias_offset); + reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK | + OMAP4_MMC1_PWRDNZ_MASK | + OMAP4_USBC1_ICUSB_PWRDNZ_MASK); + omap4_ctrl_pad_writel(reg, control_pbias_offset); } static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot, @@ -147,30 +148,33 @@ static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot, u32 reg; if (power_on) { - reg = omap_ctrl_readl(control_pbias_offset); - reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ; + reg = omap4_ctrl_pad_readl(control_pbias_offset); + reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK; if ((1 << vdd) <= MMC_VDD_165_195) - reg &= ~OMAP4_MMC1_PBIASLITE_VMODE; + reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK; else - reg |= OMAP4_MMC1_PBIASLITE_VMODE; - reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ | OMAP4_MMC1_PWRDNZ | - OMAP4_USBC1_ICUSB_PWRDNZ); - omap_ctrl_writel(reg, control_pbias_offset); + reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK; + reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK | + OMAP4_MMC1_PWRDNZ_MASK | + OMAP4_USBC1_ICUSB_PWRDNZ_MASK); + omap4_ctrl_pad_writel(reg, control_pbias_offset); /* 4 microsec delay for comparator to generate an error*/ udelay(4); - reg = omap_ctrl_readl(control_pbias_offset); - if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR) { + reg = omap4_ctrl_pad_readl(control_pbias_offset); + if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) { pr_err("Pbias Voltage is not same as LDO\n"); /* Caution : On VMODE_ERROR Power Down MMC IO */ - reg &= ~(OMAP4_MMC1_PWRDNZ | OMAP4_USBC1_ICUSB_PWRDNZ); - omap_ctrl_writel(reg, control_pbias_offset); + reg &= ~(OMAP4_MMC1_PWRDNZ_MASK | + OMAP4_USBC1_ICUSB_PWRDNZ_MASK); + omap4_ctrl_pad_writel(reg, control_pbias_offset); } } else { - reg = omap_ctrl_readl(control_pbias_offset); - reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ | - OMAP4_MMC1_PBIASLITE_VMODE | OMAP4_MMC1_PWRDNZ | - OMAP4_USBC1_ICUSB_PWRDNZ); - omap_ctrl_writel(reg, control_pbias_offset); + reg = omap4_ctrl_pad_readl(control_pbias_offset); + reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK | + OMAP4_MMC1_PWRDNZ_MASK | + OMAP4_MMC1_PBIASLITE_VMODE_MASK | + OMAP4_USBC1_ICUSB_PWRDNZ_MASK); + omap4_ctrl_pad_writel(reg, control_pbias_offset); } } @@ -218,17 +222,18 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1; } } else { - control_pbias_offset = OMAP44XX_CONTROL_PBIAS_LITE; - control_mmc1 = OMAP44XX_CONTROL_MMC1; - reg = omap_ctrl_readl(control_mmc1); - reg |= (OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP0 | - OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP1); - reg &= ~(OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP2 | - OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP3); - reg |= (OMAP4_CONTROL_SDMMC1_DR0_SPEEDCTRL | - OMAP4_CONTROL_SDMMC1_DR1_SPEEDCTRL | - OMAP4_CONTROL_SDMMC1_DR2_SPEEDCTRL); - omap_ctrl_writel(reg, control_mmc1); + control_pbias_offset = + OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE; + control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1; + reg = omap4_ctrl_pad_readl(control_mmc1); + reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK | + OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK); + reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK | + OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK); + reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK| + OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK | + OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK); + omap4_ctrl_pad_writel(reg, control_mmc1); } for (c = controllers; c->mmc; c++) { diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 9a879f9..4808bc9 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -60,7 +60,7 @@ int omap_type(void) } else if (cpu_is_omap34xx()) { val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); } else if (cpu_is_omap44xx()) { - val = omap_ctrl_readl(OMAP44XX_CONTROL_STATUS); + val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS); } else { pr_err("Cannot detect omap type!\n"); goto out; diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c index 480718b..7d668b3 100644 --- a/arch/arm/plat-omap/common.c +++ b/arch/arm/plat-omap/common.c @@ -336,7 +336,7 @@ void __init omap3_map_io(void) static struct omap_globals omap4_globals = { .class = OMAP443X_CLASS, .tap = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE), - .ctrl = OMAP443X_CTRL_BASE, /* FIXME: Move this to control core */ + .ctrl = OMAP443X_SCM_BASE, .ctrl_pad = OMAP443X_CTRL_BASE, .prm = OMAP4430_PRM_BASE, .cm = OMAP4430_CM_BASE, diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/plat-omap/include/plat/control.h index f571af7..19c9b2a 100644 --- a/arch/arm/plat-omap/include/plat/control.h +++ b/arch/arm/plat-omap/include/plat/control.h @@ -208,12 +208,6 @@ #define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250 #define OMAP3_PADCONF_SAD2D_IDLEACK 0x254 -/* 44xx control status register offset */ -#define OMAP44XX_CONTROL_STATUS 0x2c4 - -/* 44xx-only CONTROL_GENERAL register offsets */ -#define OMAP44XX_CONTROL_MMC1 0x628 -#define OMAP44XX_CONTROL_PBIAS_LITE 0x600 /* * REVISIT: This list of registers is not comprehensive - there are more * that should be added. @@ -259,23 +253,6 @@ #define OMAP2_PBIASLITEPWRDNZ0 (1 << 1) #define OMAP2_PBIASLITEVMODE0 (1 << 0) -/* CONTROL_PBIAS_LITE bits for OMAP4 */ -#define OMAP4_MMC1_PWRDNZ (1 << 26) -#define OMAP4_MMC1_PBIASLITE_HIZ_MODE (1 << 25) -#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT (1 << 24) -#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR (1 << 23) -#define OMAP4_MMC1_PBIASLITE_PWRDNZ (1 << 22) -#define OMAP4_MMC1_PBIASLITE_VMODE (1 << 21) -#define OMAP4_USBC1_ICUSB_PWRDNZ (1 << 20) - -#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP0 (1 << 31) -#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP1 (1 << 30) -#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP2 (1 << 29) -#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP3 (1 << 28) -#define OMAP4_CONTROL_SDMMC1_DR0_SPEEDCTRL (1 << 27) -#define OMAP4_CONTROL_SDMMC1_DR1_SPEEDCTRL (1 << 26) -#define OMAP4_CONTROL_SDMMC1_DR2_SPEEDCTRL (1 << 25) - /* CONTROL_PROG_IO1 bits */ #define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20) -- cgit v1.1 From a3fed9bc181666df6ecfe9ce34a29d48803f2310 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Mon, 27 Sep 2010 14:02:59 -0600 Subject: omap3: Prevent SDRC deadlock when L3 is changing frequency When changing the L3 clock frequency, the CPU is executing from internal RAM and the SDRC clock is disabled. During this time accesses made to external DDR are stalled. If the ARM subsystem attempts to access the DDR while the SDRC clock is disabled this will stall the CPU until the access to the SDRC timeouts. A timeout on the SDRC should never occur. Once a timeout occurs all the following accesses will be aborted and the DDR is no longer accessible. Although the code being executed in the internal RAM does not directly access the DDR, it was found that the branch prediction logic in the CPU may cause the CPU to prefetch code from a DDR location while the SDRC clock is disabled. This was causing an SDRC timeout which resulted in a system hang. This patch fixes this problem by ensuring the branch prediction logic is disabled while changing the L3 clock frequency. The branch prediction logic is disabled by clearing the Z-bit in the ARM CTRL register. Disabling the branch prediction logic does not have any noticable impact on the execution time of this code section. The hardware observability signals were used to monitor the sdrc idle time with and without this patch when operating at different CPU frequencies (150MHz, 500MHz and 600MHz) and the total sdrc idle time when changing frequenct was in the range of 9-11us. This was measured on an omap3430 SDP running the omapzoom p-android-omap-2.6.29 branch. Signed-off-by: Jon Hunter Signed-off-by: Paul Walmsley Cc: Santosh Shilimkar Cc: Richard Woodruff Cc: Tony Lindgren --- arch/arm/mach-omap2/sram34xx.S | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S index de99ba2..3637274 100644 --- a/arch/arm/mach-omap2/sram34xx.S +++ b/arch/arm/mach-omap2/sram34xx.S @@ -129,8 +129,11 @@ ENTRY(omap3_sram_configure_core_dpll) ldr r4, [sp, #80] str r4, omap_sdrc_mr_1_val skip_cs1_params: + mrc p15, 0, r8, c1, c0, 0 @ read ctrl register + bic r10, r8, #0x800 @ clear Z-bit, disable branch prediction + mcr p15, 0, r10, c1, c0, 0 @ write ctrl register dsb @ flush buffered writes to interconnect - + isb @ prevent speculative exec past here cmp r3, #1 @ if increasing SDRC clk rate, bleq configure_sdrc @ program the SDRC regs early (for RFR) cmp r1, #SDRC_UNLOCK_DLL @ set the intended DLL state @@ -148,6 +151,7 @@ skip_cs1_params: beq return_to_sdram @ return to SDRAM code, otherwise, bl configure_sdrc @ reprogram SDRC regs now return_to_sdram: + mcr p15, 0, r8, c1, c0, 0 @ restore ctrl register isb @ prevent speculative exec past here mov r0, #0 @ return value ldmfd sp!, {r1-r12, pc} @ restore regs and return -- cgit v1.1 From d04b620e6e6e72a95b7b88ccb7b002cb8f6b8113 Mon Sep 17 00:00:00 2001 From: Igor Grinberg Date: Tue, 21 Sep 2010 16:03:09 +0000 Subject: omap3: Introduce CompuLab CM-T3517 module Add basic suppot, enable uart and led. Signed-off-by: Igor Grinberg Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/Kconfig | 7 ++ arch/arm/mach-omap2/Makefile | 1 + arch/arm/mach-omap2/board-cm-t3517.c | 109 +++++++++++++++++++++++++++ arch/arm/plat-omap/include/plat/uncompress.h | 1 + 4 files changed, 118 insertions(+) create mode 100644 arch/arm/mach-omap2/board-cm-t3517.c (limited to 'arch') diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index bb85f24..9ceb72b 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -216,6 +216,13 @@ config MACH_CM_T35 select OMAP_PACKAGE_CUS select OMAP_MUX +config MACH_CM_T3517 + bool "CompuLab CM-T3517 module" + depends on ARCH_OMAP3 + default y + select OMAP_PACKAGE_CBB + select OMAP_MUX + config MACH_IGEP0020 bool "IGEP v2 board" depends on ARCH_OMAP3 diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index e599ae2..9d1a360 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -151,6 +151,7 @@ obj-$(CONFIG_MACH_OMAP_3630SDP) += board-3630sdp.o \ hsmmc.o obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o \ hsmmc.o +obj-$(CONFIG_MACH_CM_T3517) += board-cm-t3517.o obj-$(CONFIG_MACH_IGEP0020) += board-igep0020.o \ hsmmc.o obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK) += board-omap3touchbook.o \ diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c new file mode 100644 index 0000000..507d2d5 --- /dev/null +++ b/arch/arm/mach-omap2/board-cm-t3517.c @@ -0,0 +1,109 @@ +/* + * linux/arch/arm/mach-omap2/board-cm-t3517.c + * + * Support for the CompuLab CM-T3517 modules + * + * Copyright (C) 2010 CompuLab, Ltd. + * Author: Igor Grinberg + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include "mux.h" + +#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) +static struct gpio_led cm_t3517_leds[] = { + [0] = { + .gpio = 186, + .name = "cm-t3517:green", + .default_trigger = "heartbeat", + .active_low = 0, + }, +}; + +static struct gpio_led_platform_data cm_t3517_led_pdata = { + .num_leds = ARRAY_SIZE(cm_t3517_leds), + .leds = cm_t3517_leds, +}; + +static struct platform_device cm_t3517_led_device = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &cm_t3517_led_pdata, + }, +}; + +static void __init cm_t3517_init_leds(void) +{ + platform_device_register(&cm_t3517_led_device); +} +#else +static inline void cm_t3517_init_leds(void) {} +#endif + + +static struct omap_board_config_kernel cm_t3517_config[] __initdata = { +}; + +static void __init cm_t3517_init_irq(void) +{ + omap_board_config = cm_t3517_config; + omap_board_config_size = ARRAY_SIZE(cm_t3517_config); + + omap2_init_common_hw(NULL, NULL); + omap_init_irq(); + omap_gpio_init(); +} + +static struct omap_board_mux board_mux[] __initdata = { + /* GPIO186 - Green LED */ + OMAP3_MUX(SYS_CLKOUT2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), + + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; + +static void __init cm_t3517_init(void) +{ + omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); + omap_serial_init(); + cm_t3517_init_leds(); +} + +MACHINE_START(CM_T3517, "Compulab CM-T3517") + .phys_io = 0x48000000, + .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, + .boot_params = 0x80000100, + .map_io = omap3_map_io, + .reserve = omap_reserve, + .init_irq = cm_t3517_init_irq, + .init_machine = cm_t3517_init, + .timer = &omap_timer, +MACHINE_END diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h index 57dffa7..ab60b35 100644 --- a/arch/arm/plat-omap/include/plat/uncompress.h +++ b/arch/arm/plat-omap/include/plat/uncompress.h @@ -142,6 +142,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id) /* omap3 based boards using UART3 */ DEBUG_LL_OMAP3(3, cm_t35); + DEBUG_LL_OMAP3(3, cm_t3517); DEBUG_LL_OMAP3(3, igep0020); DEBUG_LL_OMAP3(3, nokia_rx51); DEBUG_LL_OMAP3(3, omap3517evm); -- cgit v1.1 From 46893a56aad011764003703b06303515ea670c57 Mon Sep 17 00:00:00 2001 From: Igor Grinberg Date: Tue, 21 Sep 2010 16:03:10 +0000 Subject: omap3: cm-t3517: add support for v3020 rtc add support for v3020 rtc. Signed-off-by: Igor Grinberg Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-cm-t3517.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c index 507d2d5..2b41c6d 100644 --- a/arch/arm/mach-omap2/board-cm-t3517.c +++ b/arch/arm/mach-omap2/board-cm-t3517.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include @@ -69,6 +70,35 @@ static void __init cm_t3517_init_leds(void) static inline void cm_t3517_init_leds(void) {} #endif +#if defined(CONFIG_RTC_DRV_V3020) || defined(CONFIG_RTC_DRV_V3020_MODULE) +#define RTC_IO_GPIO (153) +#define RTC_WR_GPIO (154) +#define RTC_RD_GPIO (160) +#define RTC_CS_GPIO (163) + +struct v3020_platform_data cm_t3517_v3020_pdata = { + .use_gpio = 1, + .gpio_cs = RTC_CS_GPIO, + .gpio_wr = RTC_WR_GPIO, + .gpio_rd = RTC_RD_GPIO, + .gpio_io = RTC_IO_GPIO, +}; + +static struct platform_device cm_t3517_rtc_device = { + .name = "v3020", + .id = -1, + .dev = { + .platform_data = &cm_t3517_v3020_pdata, + } +}; + +static void __init cm_t3517_init_rtc(void) +{ + platform_device_register(&cm_t3517_rtc_device); +} +#else +static inline void cm_t3517_init_rtc(void) {} +#endif static struct omap_board_config_kernel cm_t3517_config[] __initdata = { }; @@ -86,6 +116,11 @@ static void __init cm_t3517_init_irq(void) static struct omap_board_mux board_mux[] __initdata = { /* GPIO186 - Green LED */ OMAP3_MUX(SYS_CLKOUT2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), + /* RTC GPIOs: IO, WR#, RD#, CS# */ + OMAP3_MUX(MCBSP4_DR, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), + OMAP3_MUX(MCBSP4_DX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), + OMAP3_MUX(MCBSP_CLKS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), + OMAP3_MUX(UART3_CTS_RCTX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), { .reg_offset = OMAP_MUX_TERMINATOR }, }; @@ -95,6 +130,7 @@ static void __init cm_t3517_init(void) omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); omap_serial_init(); cm_t3517_init_leds(); + cm_t3517_init_rtc(); } MACHINE_START(CM_T3517, "Compulab CM-T3517") -- cgit v1.1 From 525d75b31bc97354870b5991d57b2607d7b88602 Mon Sep 17 00:00:00 2001 From: Igor Grinberg Date: Tue, 21 Sep 2010 16:03:11 +0000 Subject: omap3: cm-t3517: add support for usb host add support for hsusb host ports 1, 2 and on-module usb hub. Signed-off-by: Igor Grinberg Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-cm-t3517.c | 50 ++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c index 2b41c6d..2c7082d 100644 --- a/arch/arm/mach-omap2/board-cm-t3517.c +++ b/arch/arm/mach-omap2/board-cm-t3517.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -36,6 +37,7 @@ #include #include #include +#include #include "mux.h" @@ -100,6 +102,47 @@ static void __init cm_t3517_init_rtc(void) static inline void cm_t3517_init_rtc(void) {} #endif +#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE) +#define HSUSB1_RESET_GPIO (146) +#define HSUSB2_RESET_GPIO (147) +#define USB_HUB_RESET_GPIO (152) + +static struct ehci_hcd_omap_platform_data cm_t3517_ehci_pdata __initdata = { + .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, + .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, + .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, + + .phy_reset = true, + .reset_gpio_port[0] = HSUSB1_RESET_GPIO, + .reset_gpio_port[1] = HSUSB2_RESET_GPIO, + .reset_gpio_port[2] = -EINVAL, +}; + +static int cm_t3517_init_usbh(void) +{ + int err; + + err = gpio_request(USB_HUB_RESET_GPIO, "usb hub rst"); + if (err) { + pr_err("CM-T3517: usb hub rst gpio request failed: %d\n", err); + } else { + gpio_direction_output(USB_HUB_RESET_GPIO, 0); + udelay(10); + gpio_set_value(USB_HUB_RESET_GPIO, 1); + msleep(1); + } + + usb_ehci_init(&cm_t3517_ehci_pdata); + + return 0; +} +#else +static inline int cm_t3517_init_usbh(void) +{ + return 0; +} +#endif + static struct omap_board_config_kernel cm_t3517_config[] __initdata = { }; @@ -121,6 +164,12 @@ static struct omap_board_mux board_mux[] __initdata = { OMAP3_MUX(MCBSP4_DX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), OMAP3_MUX(MCBSP_CLKS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), OMAP3_MUX(UART3_CTS_RCTX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), + /* HSUSB1 RESET */ + OMAP3_MUX(UART2_TX, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), + /* HSUSB2 RESET */ + OMAP3_MUX(UART2_RX, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), + /* CM-T3517 USB HUB nRESET */ + OMAP3_MUX(MCBSP4_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), { .reg_offset = OMAP_MUX_TERMINATOR }, }; @@ -131,6 +180,7 @@ static void __init cm_t3517_init(void) omap_serial_init(); cm_t3517_init_leds(); cm_t3517_init_rtc(); + cm_t3517_init_usbh(); } MACHINE_START(CM_T3517, "Compulab CM-T3517") -- cgit v1.1 From ec34fccd3a8ed4997c38797b49e37535ad387401 Mon Sep 17 00:00:00 2001 From: Igor Grinberg Date: Tue, 21 Sep 2010 16:03:12 +0000 Subject: omap3: cm-t3517: add support for NAND flash add support for NAND flash. Signed-off-by: Igor Grinberg Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-cm-t3517.c | 54 ++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c index 2c7082d..4c26cf5 100644 --- a/arch/arm/mach-omap2/board-cm-t3517.c +++ b/arch/arm/mach-omap2/board-cm-t3517.c @@ -29,6 +29,9 @@ #include #include #include +#include +#include +#include #include #include @@ -38,6 +41,8 @@ #include #include #include +#include +#include #include "mux.h" @@ -143,6 +148,54 @@ static inline int cm_t3517_init_usbh(void) } #endif +#if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE) +#define NAND_BLOCK_SIZE SZ_128K + +static struct mtd_partition cm_t3517_nand_partitions[] = { + { + .name = "xloader", + .offset = 0, /* Offset = 0x00000 */ + .size = 4 * NAND_BLOCK_SIZE, + .mask_flags = MTD_WRITEABLE + }, + { + .name = "uboot", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ + .size = 15 * NAND_BLOCK_SIZE, + }, + { + .name = "uboot environment", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */ + .size = 2 * NAND_BLOCK_SIZE, + }, + { + .name = "linux", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */ + .size = 32 * NAND_BLOCK_SIZE, + }, + { + .name = "rootfs", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x680000 */ + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct omap_nand_platform_data cm_t3517_nand_data = { + .parts = cm_t3517_nand_partitions, + .nr_parts = ARRAY_SIZE(cm_t3517_nand_partitions), + .dma_channel = -1, /* disable DMA in OMAP NAND driver */ + .cs = 0, +}; + +static void __init cm_t3517_init_nand(void) +{ + if (gpmc_nand_init(&cm_t3517_nand_data) < 0) + pr_err("CM-T3517: NAND initialization failed\n"); +} +#else +static inline void cm_t3517_init_nand(void) {} +#endif + static struct omap_board_config_kernel cm_t3517_config[] __initdata = { }; @@ -179,6 +232,7 @@ static void __init cm_t3517_init(void) omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); omap_serial_init(); cm_t3517_init_leds(); + cm_t3517_init_nand(); cm_t3517_init_rtc(); cm_t3517_init_usbh(); } -- cgit v1.1 From b6a26b4b87d7b030a546e7bdaf390ffc58323f36 Mon Sep 17 00:00:00 2001 From: Igor Grinberg Date: Tue, 21 Sep 2010 16:03:13 +0000 Subject: omap3: cm-t3517: add support for TI HECC add support for TI HECC. Signed-off-by: Igor Grinberg Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-cm-t3517.c | 45 ++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c index 4c26cf5..1115b8a 100644 --- a/arch/arm/mach-omap2/board-cm-t3517.c +++ b/arch/arm/mach-omap2/board-cm-t3517.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include @@ -44,6 +45,8 @@ #include #include +#include + #include "mux.h" #if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) @@ -77,6 +80,47 @@ static void __init cm_t3517_init_leds(void) static inline void cm_t3517_init_leds(void) {} #endif +#if defined(CONFIG_CAN_TI_HECC) || defined(CONFIG_CAN_TI_HECC_MODULE) +static struct resource cm_t3517_hecc_resources[] = { + { + .start = AM35XX_IPSS_HECC_BASE, + .end = AM35XX_IPSS_HECC_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = INT_35XX_HECC0_IRQ, + .end = INT_35XX_HECC0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct ti_hecc_platform_data cm_t3517_hecc_pdata = { + .scc_hecc_offset = AM35XX_HECC_SCC_HECC_OFFSET, + .scc_ram_offset = AM35XX_HECC_SCC_RAM_OFFSET, + .hecc_ram_offset = AM35XX_HECC_RAM_OFFSET, + .mbx_offset = AM35XX_HECC_MBOX_OFFSET, + .int_line = AM35XX_HECC_INT_LINE, + .version = AM35XX_HECC_VERSION, +}; + +static struct platform_device cm_t3517_hecc_device = { + .name = "ti_hecc", + .id = 1, + .num_resources = ARRAY_SIZE(cm_t3517_hecc_resources), + .resource = cm_t3517_hecc_resources, + .dev = { + .platform_data = &cm_t3517_hecc_pdata, + }, +}; + +static void cm_t3517_init_hecc(void) +{ + platform_device_register(&cm_t3517_hecc_device); +} +#else +static inline void cm_t3517_init_hecc(void) {} +#endif + #if defined(CONFIG_RTC_DRV_V3020) || defined(CONFIG_RTC_DRV_V3020_MODULE) #define RTC_IO_GPIO (153) #define RTC_WR_GPIO (154) @@ -235,6 +279,7 @@ static void __init cm_t3517_init(void) cm_t3517_init_nand(); cm_t3517_init_rtc(); cm_t3517_init_usbh(); + cm_t3517_init_hecc(); } MACHINE_START(CM_T3517, "Compulab CM-T3517") -- cgit v1.1 From b45b501c31ce496dbb2b96a8d606642261fa8d8b Mon Sep 17 00:00:00 2001 From: matt mooney Date: Mon, 27 Sep 2010 19:04:32 -0700 Subject: arm: remove cast from void* Unnecessary cast from void* in assignment. Signed-off-by: matt mooney Acked-by: Hiroshi DOYU Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/mailbox.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c index 42dbfa4..40ddeca 100644 --- a/arch/arm/mach-omap2/mailbox.c +++ b/arch/arm/mach-omap2/mailbox.c @@ -181,7 +181,7 @@ static int omap2_mbox_fifo_full(struct omap_mbox *mbox) static void omap2_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_type_t irq) { - struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv; + struct omap_mbox2_priv *p = mbox->priv; u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit; l = mbox_read_reg(p->irqenable); @@ -192,7 +192,7 @@ static void omap2_mbox_enable_irq(struct omap_mbox *mbox, static void omap2_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_type_t irq) { - struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv; + struct omap_mbox2_priv *p = mbox->priv; u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit; l = mbox_read_reg(p->irqdisable); l &= ~bit; @@ -202,7 +202,7 @@ static void omap2_mbox_disable_irq(struct omap_mbox *mbox, static void omap2_mbox_ack_irq(struct omap_mbox *mbox, omap_mbox_type_t irq) { - struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv; + struct omap_mbox2_priv *p = mbox->priv; u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit; mbox_write_reg(bit, p->irqstatus); @@ -214,7 +214,7 @@ static void omap2_mbox_ack_irq(struct omap_mbox *mbox, static int omap2_mbox_is_irq(struct omap_mbox *mbox, omap_mbox_type_t irq) { - struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv; + struct omap_mbox2_priv *p = mbox->priv; u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit; u32 enable = mbox_read_reg(p->irqenable); u32 status = mbox_read_reg(p->irqstatus); -- cgit v1.1 From d40f3f15d31e93fce3960d90caaa5a40b52494e8 Mon Sep 17 00:00:00 2001 From: Tim Nordell Date: Mon, 27 Sep 2010 16:05:47 +0000 Subject: ARM: OMAP3LOGIC: Adding LogicPD OMAP3 board support Adding support for LogicPD's OMAP 3530 LV SOM and OMAP 35x Torpedo board. Signed-off-by: Tim Nordell Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/Kconfig | 20 ++++ arch/arm/mach-omap2/Makefile | 4 + arch/arm/mach-omap2/board-omap3logic.c | 143 +++++++++++++++++++++++++++ arch/arm/plat-omap/include/plat/uncompress.h | 2 + 4 files changed, 169 insertions(+) create mode 100644 arch/arm/mach-omap2/board-omap3logic.c (limited to 'arch') diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 9ceb72b..1c4b237 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -137,6 +137,26 @@ config MACH_OMAP_LDP default y select OMAP_PACKAGE_CBB +config MACH_OMAP3530_LV_SOM + bool "OMAP3 Logic 3530 LV SOM board" + depends on ARCH_OMAP3 + select OMAP_PACKAGE_CBB + default y + help + Support for the LogicPD OMAP3530 SOM Development kit + for full description please see the products webpage at + http://www.logicpd.com/products/development-kits/texas-instruments-zoom%E2%84%A2-omap35x-development-kit + +config MACH_OMAP3_TORPEDO + bool "OMAP3 Logic 35x Torpedo board" + depends on ARCH_OMAP3 + select OMAP_PACKAGE_CBB + default y + help + Support for the LogicPD OMAP35x Torpedo Development kit + for full description please see the products webpage at + http://www.logicpd.com/products/development-kits/zoom-omap35x-torpedo-development-kit + config MACH_OVERO bool "Gumstix Overo board" depends on ARCH_OMAP3 diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 9d1a360..1c525a8 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -120,6 +120,10 @@ obj-$(CONFIG_MACH_DEVKIT8000) += board-devkit8000.o \ obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o \ board-flash.o \ hsmmc.o +obj-$(CONFIG_MACH_OMAP3530_LV_SOM) += board-omap3logic.o \ + hsmmc.o +obj-$(CONFIG_MACH_OMAP3_TORPEDO) += board-omap3logic.o \ + hsmmc.o obj-$(CONFIG_MACH_OVERO) += board-overo.o \ hsmmc.o obj-$(CONFIG_MACH_OMAP3EVM) += board-omap3evm.o \ diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c new file mode 100644 index 0000000..ac3b0f7 --- /dev/null +++ b/arch/arm/mach-omap2/board-omap3logic.c @@ -0,0 +1,143 @@ +/* + * linux/arch/arm/mach-omap2/board-omap3logic.c + * + * Copyright (C) 2010 Li-Pro.Net + * Stephan Linz + * + * Copyright (C) 2010 Logic Product Development, Inc. + * Peter Barada + * + * Modified from Beagle, EVM, and RX51 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include +#include +#include +#include + +#include "mux.h" + +#include +#include +#include +#include +#include +#include +#include + +#define OMAP3LOGIC_SMSC911X_CS 1 + +#define OMAP3530_LV_SOM_MMC_GPIO_CD 110 +#define OMAP3530_LV_SOM_MMC_GPIO_WP 126 +#define OMAP3530_LV_SOM_SMSC911X_GPIO_IRQ 152 + +#define OMAP3_TORPEDO_MMC_GPIO_CD 127 +#define OMAP3_TORPEDO_SMSC911X_GPIO_IRQ 129 + +static struct regulator_consumer_supply omap3logic_vmmc1_supply = { + .supply = "vmmc", +}; + +/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ +static struct regulator_init_data omap3logic_vmmc1 = { + .constraints = { + .name = "VMMC1", + .min_uV = 1850000, + .max_uV = 3150000, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &omap3logic_vmmc1_supply, +}; + +static struct twl4030_gpio_platform_data omap3logic_gpio_data = { + .gpio_base = OMAP_MAX_GPIO_LINES, + .irq_base = TWL4030_GPIO_IRQ_BASE, + .irq_end = TWL4030_GPIO_IRQ_END, + .use_leds = true, + .pullups = BIT(1), + .pulldowns = BIT(2) | BIT(6) | BIT(7) | BIT(8) + | BIT(13) | BIT(15) | BIT(16) | BIT(17), +}; + +static struct twl4030_platform_data omap3logic_twldata = { + .irq_base = TWL4030_IRQ_BASE, + .irq_end = TWL4030_IRQ_END, + + /* platform_data for children goes here */ + .gpio = &omap3logic_gpio_data, +}; + +static struct i2c_board_info __initdata omap3logic_i2c_boardinfo[] = { + { + I2C_BOARD_INFO("twl4030", 0x48), + .flags = I2C_CLIENT_WAKE, + .irq = INT_34XX_SYS_NIRQ, + .platform_data = &omap3logic_twldata, + }, +}; + +static int __init omap3logic_i2c_init(void) +{ + omap_register_i2c_bus(1, 2600, omap3logic_i2c_boardinfo, + ARRAY_SIZE(omap3logic_i2c_boardinfo)); + return 0; +} + +static void __init omap3logic_init_irq(void) +{ + omap2_init_common_hw(NULL, NULL); + omap_init_irq(); + omap_gpio_init(); +} + +static void __init omap3logic_init(void) +{ + omap3logic_i2c_init(); + omap_serial_init(); + + /* Ensure SDRC pins are mux'd for self-refresh */ + omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); + omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); +} + +MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board") + .phys_io = 0x48000000, + .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, + .boot_params = 0x80000100, + .map_io = omap3_map_io, + .init_irq = omap3logic_init_irq, + .init_machine = omap3logic_init, + .timer = &omap_timer, +MACHINE_END + +MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board") + .phys_io = 0x48000000, + .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, + .boot_params = 0x80000100, + .map_io = omap3_map_io, + .init_irq = omap3logic_init_irq, + .init_machine = omap3logic_init, + .timer = &omap_timer, +MACHINE_END diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h index ab60b35..2769395 100644 --- a/arch/arm/plat-omap/include/plat/uncompress.h +++ b/arch/arm/plat-omap/include/plat/uncompress.h @@ -139,6 +139,8 @@ static inline void __arch_decomp_setup(unsigned long arch_id) DEBUG_LL_OMAP2(1, omap3evm); DEBUG_LL_OMAP3(1, omap_3430sdp); DEBUG_LL_OMAP3(1, omap_3630sdp); + DEBUG_LL_OMAP3(1, omap3530_lv_som); + DEBUG_LL_OMAP3(1, omap3_torpedo); /* omap3 based boards using UART3 */ DEBUG_LL_OMAP3(3, cm_t35); -- cgit v1.1 From 8430281b0a909048cc0e38756b11ae309bb783cd Mon Sep 17 00:00:00 2001 From: Tim Nordell Date: Mon, 27 Sep 2010 16:05:48 +0000 Subject: ARM: OMAP3LOGIC: Adding SDMMC support Add low-level initialization for hsmmc controller for LogicPD's OMAP 3530 LV SOM and OMAP 35x Torpedo board. Signed-off-by: Tim Nordell [tony@atomide.com: updated for the recent mmc platform init changes] Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-omap3logic.c | 39 +++++++++++++++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c index ac3b0f7..8b60360 100644 --- a/arch/arm/mach-omap2/board-omap3logic.c +++ b/arch/arm/mach-omap2/board-omap3logic.c @@ -26,6 +26,7 @@ #include #include +#include #include #include @@ -33,6 +34,7 @@ #include #include "mux.h" +#include "hsmmc.h" #include #include @@ -87,6 +89,7 @@ static struct twl4030_platform_data omap3logic_twldata = { /* platform_data for children goes here */ .gpio = &omap3logic_gpio_data, + .vmmc1 = &omap3logic_vmmc1, }; static struct i2c_board_info __initdata omap3logic_i2c_boardinfo[] = { @@ -105,6 +108,40 @@ static int __init omap3logic_i2c_init(void) return 0; } +static struct omap2_hsmmc_info __initdata board_mmc_info[] = { + { + .name = "external", + .mmc = 1, + .caps = MMC_CAP_4_BIT_DATA, + .gpio_cd = -EINVAL, + .gpio_wp = -EINVAL, + }, + {} /* Terminator */ +}; + +static void __init board_mmc_init(void) +{ + if (machine_is_omap3530_lv_som()) { + /* OMAP3530 LV SOM board */ + board_mmc_info[0].gpio_cd = OMAP3530_LV_SOM_MMC_GPIO_CD; + board_mmc_info[0].gpio_wp = OMAP3530_LV_SOM_MMC_GPIO_WP; + omap_mux_init_signal("gpio_110", OMAP_PIN_OUTPUT); + omap_mux_init_signal("gpio_126", OMAP_PIN_OUTPUT); + } else if (machine_is_omap3_torpedo()) { + /* OMAP3 Torpedo board */ + board_mmc_info[0].gpio_cd = OMAP3_TORPEDO_MMC_GPIO_CD; + omap_mux_init_signal("gpio_127", OMAP_PIN_OUTPUT); + } else { + /* unsupported board */ + printk(KERN_ERR "%s(): unknown machine type\n", __func__); + return; + } + + omap2_hsmmc_init(board_mmc_info); + /* link regulators to MMC adapters */ + omap3logic_vmmc1_supply.dev = board_mmc_info[0].dev; +} + static void __init omap3logic_init_irq(void) { omap2_init_common_hw(NULL, NULL); @@ -116,7 +153,7 @@ static void __init omap3logic_init(void) { omap3logic_i2c_init(); omap_serial_init(); - + board_mmc_init(); /* Ensure SDRC pins are mux'd for self-refresh */ omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); -- cgit v1.1 From cdd280b9958d71ccbaf7c00c0d63dab0a48c1db0 Mon Sep 17 00:00:00 2001 From: Tim Nordell Date: Mon, 27 Sep 2010 16:05:49 +0000 Subject: ARM: OMAP3LOGIC: Add generic smsc911x support when connected to GPMC Introduce of a generic way to setup smsc911x based Ethernet controller connected to GPMC similar to gpmc-smc91x but without timing setup. Signed-off-by: Tim Nordell Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/Makefile | 3 + arch/arm/mach-omap2/gpmc-smsc911x.c | 113 ++++++++++++++++++++++++ arch/arm/plat-omap/include/plat/gpmc-smsc911x.h | 35 ++++++++ 3 files changed, 151 insertions(+) create mode 100644 arch/arm/mach-omap2/gpmc-smsc911x.c create mode 100644 arch/arm/plat-omap/include/plat/gpmc-smsc911x.h (limited to 'arch') diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 1c525a8..9edacb0 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -184,3 +184,6 @@ obj-y += $(nand-m) $(nand-y) smc91x-$(CONFIG_SMC91X) := gpmc-smc91x.o obj-y += $(smc91x-m) $(smc91x-y) + +smsc911x-$(CONFIG_SMSC911X) := gpmc-smsc911x.o +obj-y += $(smsc911x-m) $(smsc911x-y) diff --git a/arch/arm/mach-omap2/gpmc-smsc911x.c b/arch/arm/mach-omap2/gpmc-smsc911x.c new file mode 100644 index 0000000..703f150 --- /dev/null +++ b/arch/arm/mach-omap2/gpmc-smsc911x.c @@ -0,0 +1,113 @@ +/* + * linux/arch/arm/mach-omap2/gpmc-smsc911x.c + * + * Copyright (C) 2009 Li-Pro.Net + * Stephan Linz + * + * Modified from linux/arch/arm/mach-omap2/gpmc-smc91x.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +static struct omap_smsc911x_platform_data *gpmc_cfg; + +static struct resource gpmc_smsc911x_resources[] = { + [0] = { + .flags = IORESOURCE_MEM, + }, + [1] = { + .flags = IORESOURCE_IRQ, + }, +}; + +static struct smsc911x_platform_config gpmc_smsc911x_config = { + .phy_interface = PHY_INTERFACE_MODE_MII, + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, + .flags = SMSC911X_USE_16BIT, +}; + +static struct platform_device gpmc_smsc911x_device = { + .name = "smsc911x", + .id = -1, + .num_resources = ARRAY_SIZE(gpmc_smsc911x_resources), + .resource = gpmc_smsc911x_resources, + .dev = { + .platform_data = &gpmc_smsc911x_config, + }, +}; + +/* + * Initialize smsc911x device connected to the GPMC. Note that we + * assume that pin multiplexing is done in the board-*.c file, + * or in the bootloader. + */ +void __init gpmc_smsc911x_init(struct omap_smsc911x_platform_data *board_data) +{ + unsigned long cs_mem_base; + int ret; + + gpmc_cfg = board_data; + + if (gpmc_cs_request(gpmc_cfg->cs, SZ_16M, &cs_mem_base) < 0) { + printk(KERN_ERR "Failed to request GPMC mem for smsc911x\n"); + return; + } + + gpmc_smsc911x_resources[0].start = cs_mem_base + 0x0; + gpmc_smsc911x_resources[0].end = cs_mem_base + 0xff; + + if (gpio_request(gpmc_cfg->gpio_irq, "smsc911x irq") < 0) { + printk(KERN_ERR "Failed to request GPIO%d for smsc911x IRQ\n", + gpmc_cfg->gpio_irq); + goto free1; + } + + gpio_direction_input(gpmc_cfg->gpio_irq); + gpmc_smsc911x_resources[1].start = gpio_to_irq(gpmc_cfg->gpio_irq); + gpmc_smsc911x_resources[1].flags |= + (gpmc_cfg->flags & IRQF_TRIGGER_MASK); + + if (gpio_is_valid(gpmc_cfg->gpio_reset)) { + ret = gpio_request(gpmc_cfg->gpio_reset, "smsc911x reset"); + if (ret) { + printk(KERN_ERR "Failed to request GPIO%d for smsc911x reset\n", + gpmc_cfg->gpio_reset); + goto free2; + } + + gpio_direction_output(gpmc_cfg->gpio_reset, 1); + gpio_set_value(gpmc_cfg->gpio_reset, 0); + msleep(100); + gpio_set_value(gpmc_cfg->gpio_reset, 1); + } + + if (platform_device_register(&gpmc_smsc911x_device) < 0) { + printk(KERN_ERR "Unable to register smsc911x device\n"); + gpio_free(gpmc_cfg->gpio_reset); + goto free2; + } + + return; + +free2: + gpio_free(gpmc_cfg->gpio_irq); +free1: + gpmc_cs_free(gpmc_cfg->cs); + + printk(KERN_ERR "Could not initialize smsc911x\n"); +} diff --git a/arch/arm/plat-omap/include/plat/gpmc-smsc911x.h b/arch/arm/plat-omap/include/plat/gpmc-smsc911x.h new file mode 100644 index 0000000..872de0bf --- /dev/null +++ b/arch/arm/plat-omap/include/plat/gpmc-smsc911x.h @@ -0,0 +1,35 @@ +/* + * arch/arm/plat-omap/include/plat/gpmc-smsc911x.h + * + * Copyright (C) 2009 Li-Pro.Net + * Stephan Linz + * + * Modified from arch/arm/plat-omap/include/plat/gpmc-smc91x.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_OMAP_GPMC_SMSC911X_H__ + +struct omap_smsc911x_platform_data { + int cs; + int gpio_irq; + int gpio_reset; + u32 flags; +}; + +#if defined(CONFIG_SMSC911X) || \ + defined(CONFIG_SMSC911X_MODULE) + +extern void gpmc_smsc911x_init(struct omap_smsc911x_platform_data *d); + +#else + +static inline void gpmc_smsc911x_init(struct omap_smsc911x_platform_data *d) +{ +} + +#endif +#endif -- cgit v1.1 From 26428b5c4f675434d52c8dc09c4c8d5e6198a6ac Mon Sep 17 00:00:00 2001 From: Tim Nordell Date: Mon, 27 Sep 2010 16:05:50 +0000 Subject: ARM: OMAP3LOGIC: Added SMSC Ethernet board support Enable SMSC911x Ethernet driver for LogicPD's OMAP 3530 LV SOM and OMAP 35x Torpedo board. Signed-off-by: Tim Nordell Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-omap3logic.c | 65 ++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c index 8b60360..4c045cf 100644 --- a/arch/arm/mach-omap2/board-omap3logic.c +++ b/arch/arm/mach-omap2/board-omap3logic.c @@ -39,6 +39,7 @@ #include #include #include +#include #include #include #include @@ -142,6 +143,58 @@ static void __init board_mmc_init(void) omap3logic_vmmc1_supply.dev = board_mmc_info[0].dev; } +static struct omap_smsc911x_platform_data __initdata board_smsc911x_data = { + .cs = OMAP3LOGIC_SMSC911X_CS, + .gpio_irq = -EINVAL, + .gpio_reset = -EINVAL, + .flags = IORESOURCE_IRQ_LOWLEVEL, +}; + +/* TODO/FIXME (comment by Peter Barada, LogicPD): + * Fix the PBIAS voltage for Torpedo MMC1 pins that + * are used for other needs (IRQs, etc). */ +static void omap3torpedo_fix_pbias_voltage(void) +{ + u16 control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE; + u32 reg; + + if (machine_is_omap3_torpedo()) + { + /* Set the bias for the pin */ + reg = omap_ctrl_readl(control_pbias_offset); + + reg &= ~OMAP343X_PBIASLITEPWRDNZ1; + omap_ctrl_writel(reg, control_pbias_offset); + + /* 100ms delay required for PBIAS configuration */ + msleep(100); + + reg |= OMAP343X_PBIASLITEVMODE1; + reg |= OMAP343X_PBIASLITEPWRDNZ1; + omap_ctrl_writel(reg | 0x300, control_pbias_offset); + } +} + +static inline void __init board_smsc911x_init(void) +{ + if (machine_is_omap3530_lv_som()) { + /* OMAP3530 LV SOM board */ + board_smsc911x_data.gpio_irq = + OMAP3530_LV_SOM_SMSC911X_GPIO_IRQ; + omap_mux_init_signal("gpio_152", OMAP_PIN_INPUT); + } else if (machine_is_omap3_torpedo()) { + /* OMAP3 Torpedo board */ + board_smsc911x_data.gpio_irq = OMAP3_TORPEDO_SMSC911X_GPIO_IRQ; + omap_mux_init_signal("gpio_129", OMAP_PIN_INPUT); + } else { + /* unsupported board */ + printk(KERN_ERR "%s(): unknown machine type\n", __func__); + return; + } + + gpmc_smsc911x_init(&board_smsc911x_data); +} + static void __init omap3logic_init_irq(void) { omap2_init_common_hw(NULL, NULL); @@ -149,11 +202,23 @@ static void __init omap3logic_init_irq(void) omap_gpio_init(); } +#ifdef CONFIG_OMAP_MUX +static struct omap_board_mux board_mux[] __initdata = { + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; +#else +#define board_mux NULL +#endif + static void __init omap3logic_init(void) { + omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); + omap3torpedo_fix_pbias_voltage(); omap3logic_i2c_init(); omap_serial_init(); board_mmc_init(); + board_smsc911x_init(); + /* Ensure SDRC pins are mux'd for self-refresh */ omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); -- cgit v1.1 From ecfdd76d2ffe76687385294619f6576aa4338c4e Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Tue, 28 Sep 2010 19:07:29 +0000 Subject: OMAP2+: defconfig: modularize bluetooth, audio and WLAN In working towards a smaller default kernel, only devices used for early boot should be built in. Toward that end, build the following as modules by default: - bluetooth - audio: ALSA, ASoC - WLAN Uncompressed kernel size comparison: Before: text data bss dec hex filename 6557576 465088 5616024 12638688 c0d9e0 vmlinux After: text data bss dec hex filename 5616572 436448 5610800 11663820 b1f9cc vmlinux Signed-off-by: Kevin Hilman Signed-off-by: Tony Lindgren --- arch/arm/configs/omap2plus_defconfig | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) (limited to 'arch') diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index 9ca8df0..cb5f7f9 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -91,23 +91,23 @@ CONFIG_IP_PNP_RARP=y # CONFIG_INET_LRO is not set # CONFIG_IPV6 is not set CONFIG_NETFILTER=y -CONFIG_BT=y -CONFIG_BT_L2CAP=y -CONFIG_BT_SCO=y +CONFIG_BT=m +CONFIG_BT_L2CAP=m +CONFIG_BT_SCO=m CONFIG_BT_RFCOMM=y CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_BNEP=y +CONFIG_BT_BNEP=m CONFIG_BT_BNEP_MC_FILTER=y CONFIG_BT_BNEP_PROTO_FILTER=y -CONFIG_BT_HIDP=y -CONFIG_BT_HCIUART=y +CONFIG_BT_HIDP=m +CONFIG_BT_HCIUART=m CONFIG_BT_HCIUART_H4=y CONFIG_BT_HCIUART_BCSP=y CONFIG_BT_HCIUART_LL=y -CONFIG_BT_HCIBCM203X=y -CONFIG_BT_HCIBPA10X=y -CONFIG_CFG80211=y -CONFIG_MAC80211=y +CONFIG_BT_HCIBCM203X=m +CONFIG_BT_HCIBPA10X=m +CONFIG_CFG80211=m +CONFIG_MAC80211=m CONFIG_MAC80211_RC_PID=y CONFIG_MAC80211_RC_DEFAULT_PID=y CONFIG_MAC80211_LEDS=y @@ -143,9 +143,9 @@ CONFIG_SMC91X=y CONFIG_SMSC911X=y CONFIG_KS8851=y CONFIG_KS8851_MLL=y -CONFIG_LIBERTAS=y -CONFIG_LIBERTAS_USB=y -CONFIG_LIBERTAS_SDIO=y +CONFIG_LIBERTAS=m +CONFIG_LIBERTAS_USB=m +CONFIG_LIBERTAS_SDIO=m CONFIG_LIBERTAS_DEBUG=y CONFIG_USB_USBNET=y CONFIG_USB_ALI_M5632=y @@ -207,8 +207,8 @@ CONFIG_FONTS=y CONFIG_FONT_8x8=y CONFIG_FONT_8x16=y CONFIG_LOGO=y -CONFIG_SOUND=y -CONFIG_SND=y +CONFIG_SOUND=m +CONFIG_SND=m CONFIG_SND_MIXER_OSS=y CONFIG_SND_PCM_OSS=y CONFIG_SND_VERBOSE_PRINTK=y -- cgit v1.1 From 7ad0e386d46e9edff64705ab25337ad9130baf63 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Tue, 28 Sep 2010 19:07:28 +0000 Subject: OMAP2+: defconfig: disable CPUfreq Disable CPUfreq since 1) is not yet supported in mainline, and 2) the current driver fails to suspend properly Signed-off-by: Kevin Hilman Signed-off-by: Tony Lindgren --- arch/arm/configs/omap2plus_defconfig | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index cb5f7f9..7deec89 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -65,10 +65,6 @@ CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_CMDLINE="root=/dev/mmcblk0p2 rootwait console=ttyS2,115200" CONFIG_KEXEC=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_STAT_DETAILS=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y CONFIG_FPE_NWFPE=y CONFIG_VFP=y CONFIG_NEON=y -- cgit v1.1 From 6b667f880ff5b273f9c1ec1076ffc2c9baf97a96 Mon Sep 17 00:00:00 2001 From: "Varadarajan, Charulatha" Date: Thu, 23 Sep 2010 20:02:38 +0530 Subject: OMAP3: hwmod data: Add watchdog timer Add watchdog timer hwmod data for OMAP3 chip Signed-off-by: Charulatha V Acked-by: Cousson, Benoit Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 66 ++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 5d8eb58..5bfe9c9 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -21,6 +21,7 @@ #include "omap_hwmod_common_data.h" #include "prm-regbits-34xx.h" +#include "cm-regbits-34xx.h" /* * OMAP3xxx hardware module integration data @@ -36,6 +37,7 @@ static struct omap_hwmod omap3xxx_iva_hwmod; static struct omap_hwmod omap3xxx_l3_main_hwmod; static struct omap_hwmod omap3xxx_l4_core_hwmod; static struct omap_hwmod omap3xxx_l4_per_hwmod; +static struct omap_hwmod omap3xxx_wd_timer2_hwmod; /* L3 -> L4_CORE interface */ static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { @@ -197,6 +199,69 @@ static struct omap_hwmod omap3xxx_iva_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) }; +/* l4_wkup -> wd_timer2 */ +static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = { + { + .pa_start = 0x48314000, + .pa_end = 0x4831407f, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { + .master = &omap3xxx_l4_wkup_hwmod, + .slave = &omap3xxx_wd_timer2_hwmod, + .clk = "wdt2_ick", + .addr = omap3xxx_wd_timer2_addrs, + .addr_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* + * 'wd_timer' class + * 32-bit watchdog upward counter that generates a pulse on the reset pin on + * overflow condition + */ + +static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = { + .name = "wd_timer", + .sysc = &omap3xxx_wd_timer_sysc, +}; + +/* wd_timer2 */ +static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = { + &omap3xxx_l4_wkup__wd_timer2, +}; + +static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { + .name = "wd_timer2", + .class = &omap3xxx_wd_timer_hwmod_class, + .main_clk = "wdt2_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_WDT2_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT, + }, + }, + .slaves = omap3xxx_wd_timer2_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { &omap3xxx_l3_main_hwmod, &omap3xxx_l4_core_hwmod, @@ -204,6 +269,7 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { &omap3xxx_l4_wkup_hwmod, &omap3xxx_mpu_hwmod, &omap3xxx_iva_hwmod, + &omap3xxx_wd_timer2_hwmod, NULL, }; -- cgit v1.1 From a714b9cfabcc385540a493733bd4958d37e982d3 Mon Sep 17 00:00:00 2001 From: "Varadarajan, Charulatha" Date: Thu, 23 Sep 2010 20:02:39 +0530 Subject: OMAP2420: hwmod data: Add watchdog timer Add watchdog timer hwmod data for OMAP2420 chip Signed-off-by: Charulatha V Acked-by: Cousson, Benoit Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/omap_hwmod_2420_data.c | 64 ++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index 3cc768e..66678d9 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -19,6 +19,7 @@ #include "omap_hwmod_common_data.h" #include "prm-regbits-24xx.h" +#include "cm-regbits-24xx.h" /* * OMAP2420 hardware module integration data @@ -33,6 +34,7 @@ static struct omap_hwmod omap2420_mpu_hwmod; static struct omap_hwmod omap2420_iva_hwmod; static struct omap_hwmod omap2420_l3_main_hwmod; static struct omap_hwmod omap2420_l4_core_hwmod; +static struct omap_hwmod omap2420_wd_timer2_hwmod; /* L3 -> L4_CORE interface */ static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = { @@ -165,12 +167,74 @@ static struct omap_hwmod omap2420_iva_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) }; +/* l4_wkup -> wd_timer2 */ +static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = { + { + .pa_start = 0x48022000, + .pa_end = 0x4802207f, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = { + .master = &omap2420_l4_wkup_hwmod, + .slave = &omap2420_wd_timer2_hwmod, + .clk = "mpu_wdt_ick", + .addr = omap2420_wd_timer2_addrs, + .addr_cnt = ARRAY_SIZE(omap2420_wd_timer2_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* + * 'wd_timer' class + * 32-bit watchdog upward counter that generates a pulse on the reset pin on + * overflow condition + */ + +static struct omap_hwmod_class_sysconfig omap2420_wd_timer_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2420_wd_timer_hwmod_class = { + .name = "wd_timer", + .sysc = &omap2420_wd_timer_sysc, +}; + +/* wd_timer2 */ +static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = { + &omap2420_l4_wkup__wd_timer2, +}; + +static struct omap_hwmod omap2420_wd_timer2_hwmod = { + .name = "wd_timer2", + .class = &omap2420_wd_timer_hwmod_class, + .main_clk = "mpu_wdt_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, + }, + }, + .slaves = omap2420_wd_timer2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_wd_timer2_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), +}; + static __initdata struct omap_hwmod *omap2420_hwmods[] = { &omap2420_l3_main_hwmod, &omap2420_l4_core_hwmod, &omap2420_l4_wkup_hwmod, &omap2420_mpu_hwmod, &omap2420_iva_hwmod, + &omap2420_wd_timer2_hwmod, NULL, }; -- cgit v1.1 From 165e2161525d66a76ed2b870dedabb4c1c4714b0 Mon Sep 17 00:00:00 2001 From: "Varadarajan, Charulatha" Date: Thu, 23 Sep 2010 20:02:40 +0530 Subject: OMAP2430: hwmod data: Add watchdog timer Add watchdog timer hwmod data for OMAP2430 chip Signed-off-by: Charulatha V Acked-by: Cousson, Benoit Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/omap_hwmod_2430_data.c | 64 ++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 4526628..7ec927a 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -19,6 +19,7 @@ #include "omap_hwmod_common_data.h" #include "prm-regbits-24xx.h" +#include "cm-regbits-24xx.h" /* * OMAP2430 hardware module integration data @@ -33,6 +34,7 @@ static struct omap_hwmod omap2430_mpu_hwmod; static struct omap_hwmod omap2430_iva_hwmod; static struct omap_hwmod omap2430_l3_main_hwmod; static struct omap_hwmod omap2430_l4_core_hwmod; +static struct omap_hwmod omap2430_wd_timer2_hwmod; /* L3 -> L4_CORE interface */ static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = { @@ -165,12 +167,74 @@ static struct omap_hwmod omap2430_iva_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) }; +/* l4_wkup -> wd_timer2 */ +static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = { + { + .pa_start = 0x49016000, + .pa_end = 0x4901607f, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = { + .master = &omap2430_l4_wkup_hwmod, + .slave = &omap2430_wd_timer2_hwmod, + .clk = "mpu_wdt_ick", + .addr = omap2430_wd_timer2_addrs, + .addr_cnt = ARRAY_SIZE(omap2430_wd_timer2_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* + * 'wd_timer' class + * 32-bit watchdog upward counter that generates a pulse on the reset pin on + * overflow condition + */ + +static struct omap_hwmod_class_sysconfig omap2430_wd_timer_sysc = { + .rev_offs = 0x0, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2430_wd_timer_hwmod_class = { + .name = "wd_timer", + .sysc = &omap2430_wd_timer_sysc, +}; + +/* wd_timer2 */ +static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = { + &omap2430_l4_wkup__wd_timer2, +}; + +static struct omap_hwmod omap2430_wd_timer2_hwmod = { + .name = "wd_timer2", + .class = &omap2430_wd_timer_hwmod_class, + .main_clk = "mpu_wdt_fck", + .prcm = { + .omap2 = { + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT, + .module_offs = WKUP_MOD, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, + }, + }, + .slaves = omap2430_wd_timer2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_wd_timer2_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + static __initdata struct omap_hwmod *omap2430_hwmods[] = { &omap2430_l3_main_hwmod, &omap2430_l4_core_hwmod, &omap2430_l4_wkup_hwmod, &omap2430_mpu_hwmod, &omap2430_iva_hwmod, + &omap2430_wd_timer2_hwmod, NULL, }; -- cgit v1.1 From 92b18d1cf1335a468d4014c4fdb1eb720e77526f Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Thu, 23 Sep 2010 20:02:41 +0530 Subject: OMAP4: hwmod data: Add watchdog timer Add watchdog timer hwmod data for OMAP4 chip Note: wd_timer3 in enabled in the hwmod list but it is not yet supported by the watchdog driver. Signed-off-by: Benoit Cousson Signed-off-by: Charulatha V Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 133 +++++++++++++++++++++++++++++ 1 file changed, 133 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index e20b0ee..9523b4c 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -452,6 +452,136 @@ static struct omap_hwmod omap44xx_mpu_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; +/* + * 'wd_timer' class + * 32-bit watchdog upward counter that generates a pulse on the reset pin on + * overflow condition + */ + +static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE | + SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = { + .name = "wd_timer", + .sysc = &omap44xx_wd_timer_sysc, +}; + +/* wd_timer2 */ +static struct omap_hwmod omap44xx_wd_timer2_hwmod; +static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = { + { .irq = 80 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = { + { + .pa_start = 0x4a314000, + .pa_end = 0x4a31407f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_wkup -> wd_timer2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = { + .master = &omap44xx_l4_wkup_hwmod, + .slave = &omap44xx_wd_timer2_hwmod, + .clk = "l4_wkup_clk_mux_ck", + .addr = omap44xx_wd_timer2_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer2_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* wd_timer2 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = { + &omap44xx_l4_wkup__wd_timer2, +}; + +static struct omap_hwmod omap44xx_wd_timer2_hwmod = { + .name = "wd_timer2", + .class = &omap44xx_wd_timer_hwmod_class, + .mpu_irqs = omap44xx_wd_timer2_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer2_irqs), + .main_clk = "wd_timer2_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL, + }, + }, + .slaves = omap44xx_wd_timer2_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* wd_timer3 */ +static struct omap_hwmod omap44xx_wd_timer3_hwmod; +static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = { + { .irq = 36 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { + { + .pa_start = 0x40130000, + .pa_end = 0x4013007f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_abe -> wd_timer3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_wd_timer3_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_wd_timer3_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_addrs), + .user = OCP_USER_MPU, +}; + +/* l4_abe -> wd_timer3 (dma) */ +static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = { + { + .pa_start = 0x49030000, + .pa_end = 0x4903007f, + .flags = ADDR_TYPE_RT + }, +}; + +static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { + .master = &omap44xx_l4_abe_hwmod, + .slave = &omap44xx_wd_timer3_hwmod, + .clk = "ocp_abe_iclk", + .addr = omap44xx_wd_timer3_dma_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs), + .user = OCP_USER_SDMA, +}; + +/* wd_timer3 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = { + &omap44xx_l4_abe__wd_timer3, + &omap44xx_l4_abe__wd_timer3_dma, +}; + +static struct omap_hwmod omap44xx_wd_timer3_hwmod = { + .name = "wd_timer3", + .class = &omap44xx_wd_timer_hwmod_class, + .mpu_irqs = omap44xx_wd_timer3_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer3_irqs), + .main_clk = "wd_timer3_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL, + }, + }, + .slaves = omap44xx_wd_timer3_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + static __initdata struct omap_hwmod *omap44xx_hwmods[] = { /* dmm class */ &omap44xx_dmm_hwmod, @@ -472,6 +602,9 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = { /* mpu class */ &omap44xx_mpu_hwmod, + /* wd_timer class */ + &omap44xx_wd_timer2_hwmod, + &omap44xx_wd_timer3_hwmod, NULL, }; -- cgit v1.1 From f2ce62312650211f6cf665cd6dc519c334c4071e Mon Sep 17 00:00:00 2001 From: "Varadarajan, Charulatha" Date: Thu, 23 Sep 2010 20:02:42 +0530 Subject: OMAP: WDT: Split OMAP1 and OMAP2PLUS device registration This patch splits omap_init_wdt() into separate omap_init_wdt() functions under mach-omap1 and mach-omap2 and set them up with subsys_initcall. Also it uses omap_device_build() API instead of platform_device_register() for watchdog timer device registration for OMAP2plus chips. For OMAP2plus chips, the device specific data defined in centralized hwmod database will be used. Signed-off-by: Charulatha V Acked-by: Cousson, Benoit Signed-off-by: Kevin Hilman --- arch/arm/mach-omap1/devices.c | 27 +++++++++++++++++++++++++++ arch/arm/mach-omap2/devices.c | 39 +++++++++++++++++++++++++++++++++++++++ arch/arm/plat-omap/devices.c | 41 ----------------------------------------- 3 files changed, 66 insertions(+), 41 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c index aa07256..a919366 100644 --- a/arch/arm/mach-omap1/devices.c +++ b/arch/arm/mach-omap1/devices.c @@ -232,3 +232,30 @@ static int __init omap1_init_devices(void) } arch_initcall(omap1_init_devices); +#if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE) + +static struct resource wdt_resources[] = { + { + .start = 0xfffeb000, + .end = 0xfffeb07F, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device omap_wdt_device = { + .name = "omap_wdt", + .id = -1, + .num_resources = ARRAY_SIZE(wdt_resources), + .resource = wdt_resources, +}; + +static int __init omap_init_wdt(void) +{ + if (!cpu_is_omap16xx()) + return; + + platform_device_register(&omap_wdt_device); + return 0; +} +subsys_initcall(omap_init_wdt); +#endif diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 9e5d51b..8e2f0aa 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include @@ -28,6 +29,8 @@ #include #include #include +#include +#include #include "mux.h" @@ -932,3 +935,39 @@ static int __init omap2_init_devices(void) return 0; } arch_initcall(omap2_init_devices); + +#if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE) +struct omap_device_pm_latency omap_wdt_latency[] = { + [0] = { + .deactivate_func = omap_device_idle_hwmods, + .activate_func = omap_device_enable_hwmods, + .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, + }, +}; + +static int __init omap_init_wdt(void) +{ + int id = -1; + struct omap_device *od; + struct omap_hwmod *oh; + char *oh_name = "wd_timer2"; + char *dev_name = "omap_wdt"; + + if (!cpu_class_is_omap2()) + return 0; + + oh = omap_hwmod_lookup(oh_name); + if (!oh) { + pr_err("Could not look up wd_timer%d hwmod\n", id); + return -EINVAL; + } + + od = omap_device_build(dev_name, id, oh, NULL, 0, + omap_wdt_latency, + ARRAY_SIZE(omap_wdt_latency), 0); + WARN(IS_ERR(od), "Cant build omap_device for %s:%s.\n", + dev_name, oh->name); + return 0; +} +subsys_initcall(omap_init_wdt); +#endif diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c index d1920be..8e88e0e 100644 --- a/arch/arm/plat-omap/devices.c +++ b/arch/arm/plat-omap/devices.c @@ -232,46 +232,6 @@ static void omap_init_uwire(void) static inline void omap_init_uwire(void) {} #endif -/*-------------------------------------------------------------------------*/ - -#if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE) - -static struct resource wdt_resources[] = { - { - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device omap_wdt_device = { - .name = "omap_wdt", - .id = -1, - .num_resources = ARRAY_SIZE(wdt_resources), - .resource = wdt_resources, -}; - -static void omap_init_wdt(void) -{ - if (cpu_is_omap16xx()) - wdt_resources[0].start = 0xfffeb000; - else if (cpu_is_omap2420()) - wdt_resources[0].start = 0x48022000; /* WDT2 */ - else if (cpu_is_omap2430()) - wdt_resources[0].start = 0x49016000; /* WDT2 */ - else if (cpu_is_omap343x()) - wdt_resources[0].start = 0x48314000; /* WDT2 */ - else if (cpu_is_omap44xx()) - wdt_resources[0].start = 0x4a314000; - else - return; - - wdt_resources[0].end = wdt_resources[0].start + 0x4f; - - (void) platform_device_register(&omap_wdt_device); -} -#else -static inline void omap_init_wdt(void) {} -#endif - /* * This gets called after board-specific INIT_MACHINE, and initializes most * on-chip peripherals accessible on this board (except for few like USB): @@ -300,7 +260,6 @@ static int __init omap_init_devices(void) omap_init_rng(); omap_init_mcpdm(); omap_init_uwire(); - omap_init_wdt(); return 0; } arch_initcall(omap_init_devices); -- cgit v1.1 From db12ba53fe8b2d79c06bfe00589b3e98fd50cb4c Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Mon, 27 Sep 2010 20:19:19 +0530 Subject: OMAP4: UART: Add uart1-4 hwmods data for omap4 Add uart1-4 hwmod data into omap4_hwmod data file. Signed-off-by: Benoit Cousson Signed-off-by: Govindraj.R Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 235 +++++++++++++++++++++++++++++ 1 file changed, 235 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index e20b0ee..afcbd48 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -452,6 +452,235 @@ static struct omap_hwmod omap44xx_mpu_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; +/* + * 'uart' class + * universal asynchronous receiver/transmitter (uart) + */ + +static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = { + .rev_offs = 0x0050, + .sysc_offs = 0x0054, + .syss_offs = 0x0058, + .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap44xx_uart_hwmod_class = { + .name = "uart", + .sysc = &omap44xx_uart_sysc, +}; + +/* uart1 */ +static struct omap_hwmod omap44xx_uart1_hwmod; +static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = { + { .irq = 72 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = { + { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START }, + { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = { + { + .pa_start = 0x4806a000, + .pa_end = 0x4806a0ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> uart1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_uart1_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_uart1_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_uart1_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* uart1 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = { + &omap44xx_l4_per__uart1, +}; + +static struct omap_hwmod omap44xx_uart1_hwmod = { + .name = "uart1", + .class = &omap44xx_uart_hwmod_class, + .mpu_irqs = omap44xx_uart1_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart1_irqs), + .sdma_reqs = omap44xx_uart1_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart1_sdma_reqs), + .main_clk = "uart1_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL, + }, + }, + .slaves = omap44xx_uart1_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_uart1_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* uart2 */ +static struct omap_hwmod omap44xx_uart2_hwmod; +static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = { + { .irq = 73 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = { + { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START }, + { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = { + { + .pa_start = 0x4806c000, + .pa_end = 0x4806c0ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> uart2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_uart2_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_uart2_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_uart2_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* uart2 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = { + &omap44xx_l4_per__uart2, +}; + +static struct omap_hwmod omap44xx_uart2_hwmod = { + .name = "uart2", + .class = &omap44xx_uart_hwmod_class, + .mpu_irqs = omap44xx_uart2_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart2_irqs), + .sdma_reqs = omap44xx_uart2_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart2_sdma_reqs), + .main_clk = "uart2_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL, + }, + }, + .slaves = omap44xx_uart2_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_uart2_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* uart3 */ +static struct omap_hwmod omap44xx_uart3_hwmod; +static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = { + { .irq = 74 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = { + { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START }, + { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = { + { + .pa_start = 0x48020000, + .pa_end = 0x480200ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> uart3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_uart3_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_uart3_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_uart3_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* uart3 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = { + &omap44xx_l4_per__uart3, +}; + +static struct omap_hwmod omap44xx_uart3_hwmod = { + .name = "uart3", + .class = &omap44xx_uart_hwmod_class, + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), + .mpu_irqs = omap44xx_uart3_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart3_irqs), + .sdma_reqs = omap44xx_uart3_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart3_sdma_reqs), + .main_clk = "uart3_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL, + }, + }, + .slaves = omap44xx_uart3_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_uart3_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* uart4 */ +static struct omap_hwmod omap44xx_uart4_hwmod; +static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = { + { .irq = 70 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = { + { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START }, + { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = { + { + .pa_start = 0x4806e000, + .pa_end = 0x4806e0ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> uart4 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_uart4_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_uart4_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_uart4_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* uart4 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = { + &omap44xx_l4_per__uart4, +}; + +static struct omap_hwmod omap44xx_uart4_hwmod = { + .name = "uart4", + .class = &omap44xx_uart_hwmod_class, + .mpu_irqs = omap44xx_uart4_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart4_irqs), + .sdma_reqs = omap44xx_uart4_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart4_sdma_reqs), + .main_clk = "uart4_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL, + }, + }, + .slaves = omap44xx_uart4_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_uart4_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + static __initdata struct omap_hwmod *omap44xx_hwmods[] = { /* dmm class */ &omap44xx_dmm_hwmod, @@ -472,6 +701,12 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = { /* mpu class */ &omap44xx_mpu_hwmod, + + /* uart class */ + &omap44xx_uart1_hwmod, + &omap44xx_uart2_hwmod, + &omap44xx_uart3_hwmod, + &omap44xx_uart4_hwmod, NULL, }; -- cgit v1.1 From 046465b76a41a32a8d56e691b167fb9ba7729970 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Mon, 27 Sep 2010 20:19:30 +0530 Subject: OMAP2/3: UART: add omap_hwmod data for UARTs 1-4 This patch adds omap_hwmod data for UARTs on OMAP2 and OMAP3 platforms. UART4 support for 3630 and OMAP2 hwmod data added by Govindraj R. Signed-off-by: Govindraj.R Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/omap_hwmod_2420_data.c | 193 ++++++++++++++++++++++ arch/arm/mach-omap2/omap_hwmod_2430_data.c | 193 ++++++++++++++++++++++ arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 253 ++++++++++++++++++++++++++++- arch/arm/mach-omap2/prcm-common.h | 3 + arch/arm/plat-omap/include/plat/dma.h | 2 + arch/arm/plat-omap/include/plat/irqs.h | 2 + 6 files changed, 644 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index 3cc768e..ba145f7 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -15,6 +15,7 @@ #include #include #include +#include #include "omap_hwmod_common_data.h" @@ -71,6 +72,9 @@ static struct omap_hwmod omap2420_l3_main_hwmod = { }; static struct omap_hwmod omap2420_l4_wkup_hwmod; +static struct omap_hwmod omap2420_uart1_hwmod; +static struct omap_hwmod omap2420_uart2_hwmod; +static struct omap_hwmod omap2420_uart3_hwmod; /* L4_CORE -> L4_WKUP interface */ static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = { @@ -79,6 +83,60 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* L4 CORE -> UART1 interface */ +static struct omap_hwmod_addr_space omap2420_uart1_addr_space[] = { + { + .pa_start = OMAP2_UART1_BASE, + .pa_end = OMAP2_UART1_BASE + SZ_8K - 1, + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_uart1_hwmod, + .clk = "uart1_ick", + .addr = omap2420_uart1_addr_space, + .addr_cnt = ARRAY_SIZE(omap2420_uart1_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> UART2 interface */ +static struct omap_hwmod_addr_space omap2420_uart2_addr_space[] = { + { + .pa_start = OMAP2_UART2_BASE, + .pa_end = OMAP2_UART2_BASE + SZ_1K - 1, + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_uart2_hwmod, + .clk = "uart2_ick", + .addr = omap2420_uart2_addr_space, + .addr_cnt = ARRAY_SIZE(omap2420_uart2_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 PER -> UART3 interface */ +static struct omap_hwmod_addr_space omap2420_uart3_addr_space[] = { + { + .pa_start = OMAP2_UART3_BASE, + .pa_end = OMAP2_UART3_BASE + SZ_1K - 1, + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_uart3_hwmod, + .clk = "uart3_ick", + .addr = omap2420_uart3_addr_space, + .addr_cnt = ARRAY_SIZE(omap2420_uart3_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* Slave interfaces on the L4_CORE interconnect */ static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = { &omap2420_l3_main__l4_core, @@ -87,6 +145,9 @@ static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = { /* Master interfaces on the L4_CORE interconnect */ static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = { &omap2420_l4_core__l4_wkup, + &omap2_l4_core__uart1, + &omap2_l4_core__uart2, + &omap2_l4_core__uart3, }; /* L4 CORE */ @@ -165,12 +226,144 @@ static struct omap_hwmod omap2420_iva_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) }; +/* UART */ + +static struct omap_hwmod_class_sysconfig uart_sysc = { + .rev_offs = 0x50, + .sysc_offs = 0x54, + .syss_offs = 0x58, + .sysc_flags = (SYSC_HAS_SIDLEMODE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class uart_class = { + .name = "uart", + .sysc = &uart_sysc, +}; + +/* UART1 */ + +static struct omap_hwmod_irq_info uart1_mpu_irqs[] = { + { .irq = INT_24XX_UART1_IRQ, }, +}; + +static struct omap_hwmod_dma_info uart1_sdma_reqs[] = { + { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, }, + { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, }, +}; + +static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = { + &omap2_l4_core__uart1, +}; + +static struct omap_hwmod omap2420_uart1_hwmod = { + .name = "uart1", + .mpu_irqs = uart1_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), + .sdma_reqs = uart1_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs), + .main_clk = "uart1_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_UART1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, + }, + }, + .slaves = omap2420_uart1_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_uart1_slaves), + .class = &uart_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), +}; + +/* UART2 */ + +static struct omap_hwmod_irq_info uart2_mpu_irqs[] = { + { .irq = INT_24XX_UART2_IRQ, }, +}; + +static struct omap_hwmod_dma_info uart2_sdma_reqs[] = { + { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, }, + { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, }, +}; + +static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = { + &omap2_l4_core__uart2, +}; + +static struct omap_hwmod omap2420_uart2_hwmod = { + .name = "uart2", + .mpu_irqs = uart2_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), + .sdma_reqs = uart2_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs), + .main_clk = "uart2_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_UART2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, + }, + }, + .slaves = omap2420_uart2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_uart2_slaves), + .class = &uart_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), +}; + +/* UART3 */ + +static struct omap_hwmod_irq_info uart3_mpu_irqs[] = { + { .irq = INT_24XX_UART3_IRQ, }, +}; + +static struct omap_hwmod_dma_info uart3_sdma_reqs[] = { + { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, }, + { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, }, +}; + +static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = { + &omap2_l4_core__uart3, +}; + +static struct omap_hwmod omap2420_uart3_hwmod = { + .name = "uart3", + .mpu_irqs = uart3_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), + .sdma_reqs = uart3_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs), + .main_clk = "uart3_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 2, + .module_bit = OMAP24XX_EN_UART3_SHIFT, + .idlest_reg_id = 2, + .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, + }, + }, + .slaves = omap2420_uart3_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_uart3_slaves), + .class = &uart_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), +}; + static __initdata struct omap_hwmod *omap2420_hwmods[] = { &omap2420_l3_main_hwmod, &omap2420_l4_core_hwmod, &omap2420_l4_wkup_hwmod, &omap2420_mpu_hwmod, &omap2420_iva_hwmod, + &omap2420_uart1_hwmod, + &omap2420_uart2_hwmod, + &omap2420_uart3_hwmod, NULL, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 4526628..d21073d 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -15,6 +15,7 @@ #include #include #include +#include #include "omap_hwmod_common_data.h" @@ -71,6 +72,9 @@ static struct omap_hwmod omap2430_l3_main_hwmod = { }; static struct omap_hwmod omap2430_l4_wkup_hwmod; +static struct omap_hwmod omap2430_uart1_hwmod; +static struct omap_hwmod omap2430_uart2_hwmod; +static struct omap_hwmod omap2430_uart3_hwmod; /* L4_CORE -> L4_WKUP interface */ static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = { @@ -79,6 +83,60 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* L4 CORE -> UART1 interface */ +static struct omap_hwmod_addr_space omap2430_uart1_addr_space[] = { + { + .pa_start = OMAP2_UART1_BASE, + .pa_end = OMAP2_UART1_BASE + SZ_8K - 1, + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_uart1_hwmod, + .clk = "uart1_ick", + .addr = omap2430_uart1_addr_space, + .addr_cnt = ARRAY_SIZE(omap2430_uart1_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> UART2 interface */ +static struct omap_hwmod_addr_space omap2430_uart2_addr_space[] = { + { + .pa_start = OMAP2_UART2_BASE, + .pa_end = OMAP2_UART2_BASE + SZ_1K - 1, + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_uart2_hwmod, + .clk = "uart2_ick", + .addr = omap2430_uart2_addr_space, + .addr_cnt = ARRAY_SIZE(omap2430_uart2_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 PER -> UART3 interface */ +static struct omap_hwmod_addr_space omap2430_uart3_addr_space[] = { + { + .pa_start = OMAP2_UART3_BASE, + .pa_end = OMAP2_UART3_BASE + SZ_1K - 1, + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_uart3_hwmod, + .clk = "uart3_ick", + .addr = omap2430_uart3_addr_space, + .addr_cnt = ARRAY_SIZE(omap2430_uart3_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* Slave interfaces on the L4_CORE interconnect */ static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = { &omap2430_l3_main__l4_core, @@ -104,6 +162,9 @@ static struct omap_hwmod omap2430_l4_core_hwmod = { /* Slave interfaces on the L4_WKUP interconnect */ static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = { &omap2430_l4_core__l4_wkup, + &omap2_l4_core__uart1, + &omap2_l4_core__uart2, + &omap2_l4_core__uart3, }; /* Master interfaces on the L4_WKUP interconnect */ @@ -165,12 +226,144 @@ static struct omap_hwmod omap2430_iva_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) }; +/* UART */ + +static struct omap_hwmod_class_sysconfig uart_sysc = { + .rev_offs = 0x50, + .sysc_offs = 0x54, + .syss_offs = 0x58, + .sysc_flags = (SYSC_HAS_SIDLEMODE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class uart_class = { + .name = "uart", + .sysc = &uart_sysc, +}; + +/* UART1 */ + +static struct omap_hwmod_irq_info uart1_mpu_irqs[] = { + { .irq = INT_24XX_UART1_IRQ, }, +}; + +static struct omap_hwmod_dma_info uart1_sdma_reqs[] = { + { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, }, + { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, }, +}; + +static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = { + &omap2_l4_core__uart1, +}; + +static struct omap_hwmod omap2430_uart1_hwmod = { + .name = "uart1", + .mpu_irqs = uart1_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), + .sdma_reqs = uart1_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs), + .main_clk = "uart1_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_UART1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, + }, + }, + .slaves = omap2430_uart1_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_uart1_slaves), + .class = &uart_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + +/* UART2 */ + +static struct omap_hwmod_irq_info uart2_mpu_irqs[] = { + { .irq = INT_24XX_UART2_IRQ, }, +}; + +static struct omap_hwmod_dma_info uart2_sdma_reqs[] = { + { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, }, + { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, }, +}; + +static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = { + &omap2_l4_core__uart2, +}; + +static struct omap_hwmod omap2430_uart2_hwmod = { + .name = "uart2", + .mpu_irqs = uart2_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), + .sdma_reqs = uart2_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs), + .main_clk = "uart2_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP24XX_EN_UART2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, + }, + }, + .slaves = omap2430_uart2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_uart2_slaves), + .class = &uart_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + +/* UART3 */ + +static struct omap_hwmod_irq_info uart3_mpu_irqs[] = { + { .irq = INT_24XX_UART3_IRQ, }, +}; + +static struct omap_hwmod_dma_info uart3_sdma_reqs[] = { + { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, }, + { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, }, +}; + +static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = { + &omap2_l4_core__uart3, +}; + +static struct omap_hwmod omap2430_uart3_hwmod = { + .name = "uart3", + .mpu_irqs = uart3_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), + .sdma_reqs = uart3_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs), + .main_clk = "uart3_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 2, + .module_bit = OMAP24XX_EN_UART3_SHIFT, + .idlest_reg_id = 2, + .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, + }, + }, + .slaves = omap2430_uart3_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_uart3_slaves), + .class = &uart_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + static __initdata struct omap_hwmod *omap2430_hwmods[] = { &omap2430_l3_main_hwmod, &omap2430_l4_core_hwmod, &omap2430_l4_wkup_hwmod, &omap2430_mpu_hwmod, &omap2430_iva_hwmod, + &omap2430_uart1_hwmod, + &omap2430_uart2_hwmod, + &omap2430_uart3_hwmod, NULL, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 5d8eb58..5c9cb25 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -17,6 +17,7 @@ #include #include #include +#include #include "omap_hwmod_common_data.h" @@ -82,6 +83,10 @@ static struct omap_hwmod omap3xxx_l3_main_hwmod = { }; static struct omap_hwmod omap3xxx_l4_wkup_hwmod; +static struct omap_hwmod omap3xxx_uart1_hwmod; +static struct omap_hwmod omap3xxx_uart2_hwmod; +static struct omap_hwmod omap3xxx_uart3_hwmod; +static struct omap_hwmod omap3xxx_uart4_hwmod; /* L4_CORE -> L4_WKUP interface */ static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { @@ -90,6 +95,78 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* L4 CORE -> UART1 interface */ +static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = { + { + .pa_start = OMAP3_UART1_BASE, + .pa_end = OMAP3_UART1_BASE + SZ_8K - 1, + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_uart1_hwmod, + .clk = "uart1_ick", + .addr = omap3xxx_uart1_addr_space, + .addr_cnt = ARRAY_SIZE(omap3xxx_uart1_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> UART2 interface */ +static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = { + { + .pa_start = OMAP3_UART2_BASE, + .pa_end = OMAP3_UART2_BASE + SZ_1K - 1, + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_uart2_hwmod, + .clk = "uart2_ick", + .addr = omap3xxx_uart2_addr_space, + .addr_cnt = ARRAY_SIZE(omap3xxx_uart2_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 PER -> UART3 interface */ +static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = { + { + .pa_start = OMAP3_UART3_BASE, + .pa_end = OMAP3_UART3_BASE + SZ_1K - 1, + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_uart3_hwmod, + .clk = "uart3_ick", + .addr = omap3xxx_uart3_addr_space, + .addr_cnt = ARRAY_SIZE(omap3xxx_uart3_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 PER -> UART4 interface */ +static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = { + { + .pa_start = OMAP3_UART4_BASE, + .pa_end = OMAP3_UART4_BASE + SZ_1K - 1, + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_uart4_hwmod, + .clk = "uart4_ick", + .addr = omap3xxx_uart4_addr_space, + .addr_cnt = ARRAY_SIZE(omap3xxx_uart4_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* Slave interfaces on the L4_CORE interconnect */ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = { &omap3xxx_l3_main__l4_core, @@ -98,6 +175,8 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = { /* Master interfaces on the L4_CORE interconnect */ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = { &omap3xxx_l4_core__l4_wkup, + &omap3_l4_core__uart1, + &omap3_l4_core__uart2, }; /* L4 CORE */ @@ -119,6 +198,8 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = { /* Master interfaces on the L4_PER interconnect */ static struct omap_hwmod_ocp_if *omap3xxx_l4_per_masters[] = { + &omap3_l4_per__uart3, + &omap3_l4_per__uart4, }; /* L4 PER */ @@ -197,6 +278,172 @@ static struct omap_hwmod omap3xxx_iva_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) }; +/* UART common */ + +static struct omap_hwmod_class_sysconfig uart_sysc = { + .rev_offs = 0x50, + .sysc_offs = 0x54, + .syss_offs = 0x58, + .sysc_flags = (SYSC_HAS_SIDLEMODE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class uart_class = { + .name = "uart", + .sysc = &uart_sysc, +}; + +/* UART1 */ + +static struct omap_hwmod_irq_info uart1_mpu_irqs[] = { + { .irq = INT_24XX_UART1_IRQ, }, +}; + +static struct omap_hwmod_dma_info uart1_sdma_reqs[] = { + { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, }, + { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = { + &omap3_l4_core__uart1, +}; + +static struct omap_hwmod omap3xxx_uart1_hwmod = { + .name = "uart1", + .mpu_irqs = uart1_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), + .sdma_reqs = uart1_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs), + .main_clk = "uart1_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_UART1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT, + }, + }, + .slaves = omap3xxx_uart1_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves), + .class = &uart_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* UART2 */ + +static struct omap_hwmod_irq_info uart2_mpu_irqs[] = { + { .irq = INT_24XX_UART2_IRQ, }, +}; + +static struct omap_hwmod_dma_info uart2_sdma_reqs[] = { + { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, }, + { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = { + &omap3_l4_core__uart2, +}; + +static struct omap_hwmod omap3xxx_uart2_hwmod = { + .name = "uart2", + .mpu_irqs = uart2_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), + .sdma_reqs = uart2_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs), + .main_clk = "uart2_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_UART2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT, + }, + }, + .slaves = omap3xxx_uart2_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves), + .class = &uart_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* UART3 */ + +static struct omap_hwmod_irq_info uart3_mpu_irqs[] = { + { .irq = INT_24XX_UART3_IRQ, }, +}; + +static struct omap_hwmod_dma_info uart3_sdma_reqs[] = { + { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, }, + { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = { + &omap3_l4_per__uart3, +}; + +static struct omap_hwmod omap3xxx_uart3_hwmod = { + .name = "uart3", + .mpu_irqs = uart3_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), + .sdma_reqs = uart3_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs), + .main_clk = "uart3_fck", + .prcm = { + .omap2 = { + .module_offs = OMAP3430_PER_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_UART3_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT, + }, + }, + .slaves = omap3xxx_uart3_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves), + .class = &uart_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* UART4 */ + +static struct omap_hwmod_irq_info uart4_mpu_irqs[] = { + { .irq = INT_36XX_UART4_IRQ, }, +}; + +static struct omap_hwmod_dma_info uart4_sdma_reqs[] = { + { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, }, + { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = { + &omap3_l4_per__uart4, +}; + +static struct omap_hwmod omap3xxx_uart4_hwmod = { + .name = "uart4", + .mpu_irqs = uart4_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(uart4_mpu_irqs), + .sdma_reqs = uart4_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(uart4_sdma_reqs), + .main_clk = "uart4_fck", + .prcm = { + .omap2 = { + .module_offs = OMAP3430_PER_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3630_EN_UART4_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT, + }, + }, + .slaves = omap3xxx_uart4_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves), + .class = &uart_class, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), +}; + static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { &omap3xxx_l3_main_hwmod, &omap3xxx_l4_core_hwmod, @@ -204,6 +451,10 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { &omap3xxx_l4_wkup_hwmod, &omap3xxx_mpu_hwmod, &omap3xxx_iva_hwmod, + &omap3xxx_uart1_hwmod, + &omap3xxx_uart2_hwmod, + &omap3xxx_uart3_hwmod, + &omap3xxx_uart4_hwmod, NULL, }; @@ -211,5 +462,3 @@ int __init omap3xxx_hwmod_init(void) { return omap_hwmod_init(omap3xxx_hwmods); } - - diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h index 995b7ed..86edcf9 100644 --- a/arch/arm/mach-omap2/prcm-common.h +++ b/arch/arm/mach-omap2/prcm-common.h @@ -382,6 +382,9 @@ #define OMAP3430_EN_MPU_SHIFT 1 /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */ + +#define OMAP3630_EN_UART4_MASK (1 << 18) +#define OMAP3630_EN_UART4_SHIFT 18 #define OMAP3430_EN_GPIO6_MASK (1 << 17) #define OMAP3430_EN_GPIO6_SHIFT 17 #define OMAP3430_EN_GPIO5_MASK (1 << 16) diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h index af3a039..098f154 100644 --- a/arch/arm/plat-omap/include/plat/dma.h +++ b/arch/arm/plat-omap/include/plat/dma.h @@ -319,6 +319,8 @@ #define OMAP34XX_DMA_USIM_TX 79 /* S_DMA_78 */ #define OMAP34XX_DMA_USIM_RX 80 /* S_DMA_79 */ +#define OMAP36XX_DMA_UART4_TX 81 /* S_DMA_80 */ +#define OMAP36XX_DMA_UART4_RX 82 /* S_DMA_81 */ /*----------------------------------------------------------------------------*/ #define OMAP1_DMA_TOUT_IRQ (1 << 0) diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h index c01d9f0..65e20a6 100644 --- a/arch/arm/plat-omap/include/plat/irqs.h +++ b/arch/arm/plat-omap/include/plat/irqs.h @@ -345,6 +345,8 @@ #define INT_34XX_MMC3_IRQ 94 #define INT_34XX_GPT12_IRQ 95 +#define INT_36XX_UART4_IRQ 80 + #define INT_35XX_HECC0_IRQ 24 #define INT_35XX_HECC1_IRQ 28 #define INT_35XX_EMAC_C0_RXTHRESH_IRQ 67 -- cgit v1.1 From 6f251e9db1093c187addc309b5f2f7fe3efd2995 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Mon, 27 Sep 2010 20:19:38 +0530 Subject: OMAP: UART: omap_device conversions, remove implicit 8520 assumptions Major rework of OMAP UART init for omap_device conversion as well as use with either 8250 driver or new omap-serial driver. In preparation for a new omap-serial driver, remove 8250 assumptions and dependencies from the serial core. Convert UART core and PM support to use omap_device layer. Also add support for both console on 8250 or omap-serial driver. omap_device conversion: - Convert clock API calls to omap_device calls - Remove all static platform_data setup and configuration. This is all done by the omap_device build phase. Signed-off-by: Govindraj.R Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/serial.c | 529 +++++++++++++++++++++---------------------- 1 file changed, 260 insertions(+), 269 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index 566e991..e6c4027 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -19,19 +19,29 @@ */ #include #include -#include #include #include #include #include +#include +#include +#include + +#ifdef CONFIG_SERIAL_OMAP +#include +#endif #include #include #include #include +#include +#include +#include #include "prm.h" #include "pm.h" +#include "cm.h" #include "prm-regbits-34xx.h" #define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52 @@ -48,6 +58,8 @@ */ #define DEFAULT_TIMEOUT 0 +#define MAX_UART_HWMOD_NAME_LEN 16 + struct omap_uart_state { int num; int can_sleep; @@ -58,14 +70,21 @@ struct omap_uart_state { void __iomem *wk_en; u32 wk_mask; u32 padconf; + u32 dma_enabled; struct clk *ick; struct clk *fck; int clocked; - struct plat_serial8250_port *p; + int irq; + int regshift; + int irqflags; + void __iomem *membase; + resource_size_t mapbase; + struct list_head node; - struct platform_device pdev; + struct omap_hwmod *oh; + struct platform_device *pdev; u32 errata; #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) @@ -83,75 +102,33 @@ struct omap_uart_state { }; static LIST_HEAD(uart_list); +static u8 num_uarts; -static struct plat_serial8250_port serial_platform_data0[] = { - { - .irq = 72, - .flags = UPF_BOOT_AUTOCONF, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = OMAP24XX_BASE_BAUD * 16, - }, { - .flags = 0 - } -}; - -static struct plat_serial8250_port serial_platform_data1[] = { - { - .irq = 73, - .flags = UPF_BOOT_AUTOCONF, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = OMAP24XX_BASE_BAUD * 16, - }, { - .flags = 0 - } -}; - -static struct plat_serial8250_port serial_platform_data2[] = { - { - .irq = 74, - .flags = UPF_BOOT_AUTOCONF, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = OMAP24XX_BASE_BAUD * 16, - }, { - .flags = 0 - } -}; - -static struct plat_serial8250_port serial_platform_data3[] = { - { - .irq = 70, - .flags = UPF_BOOT_AUTOCONF, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = OMAP24XX_BASE_BAUD * 16, - }, { - .flags = 0 - } -}; void __init omap2_set_globals_uart(struct omap_globals *omap2_globals) { - serial_platform_data0[0].mapbase = omap2_globals->uart1_phys; - serial_platform_data1[0].mapbase = omap2_globals->uart2_phys; - serial_platform_data2[0].mapbase = omap2_globals->uart3_phys; - serial_platform_data3[0].mapbase = omap2_globals->uart4_phys; } +static struct omap_device_pm_latency omap_uart_latency[] = { + { + .deactivate_func = omap_device_idle_hwmods, + .activate_func = omap_device_enable_hwmods, + .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, + }, +}; + static inline unsigned int __serial_read_reg(struct uart_port *up, - int offset) + int offset) { offset <<= up->regshift; return (unsigned int)__raw_readb(up->membase + offset); } -static inline unsigned int serial_read_reg(struct plat_serial8250_port *up, +static inline unsigned int serial_read_reg(struct omap_uart_state *uart, int offset) { - offset <<= up->regshift; - return (unsigned int)__raw_readb(up->membase + offset); + offset <<= uart->regshift; + return (unsigned int)__raw_readb(uart->membase + offset); } static inline void __serial_write_reg(struct uart_port *up, int offset, @@ -161,11 +138,11 @@ static inline void __serial_write_reg(struct uart_port *up, int offset, __raw_writeb(value, up->membase + offset); } -static inline void serial_write_reg(struct plat_serial8250_port *p, int offset, +static inline void serial_write_reg(struct omap_uart_state *uart, int offset, int value) { - offset <<= p->regshift; - __raw_writeb(value, p->membase + offset); + offset <<= uart->regshift; + __raw_writeb(value, uart->membase + offset); } /* @@ -173,14 +150,12 @@ static inline void serial_write_reg(struct plat_serial8250_port *p, int offset, * properly. Note that the TX watermark initialization may not be needed * once the 8250.c watermark handling code is merged. */ + static inline void __init omap_uart_reset(struct omap_uart_state *uart) { - struct plat_serial8250_port *p = uart->p; - - serial_write_reg(p, UART_OMAP_MDR1, 0x07); - serial_write_reg(p, UART_OMAP_SCR, 0x08); - serial_write_reg(p, UART_OMAP_MDR1, 0x00); - serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0)); + serial_write_reg(uart, UART_OMAP_MDR1, 0x07); + serial_write_reg(uart, UART_OMAP_SCR, 0x08); + serial_write_reg(uart, UART_OMAP_MDR1, 0x00); } #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) @@ -197,24 +172,23 @@ static inline void __init omap_uart_reset(struct omap_uart_state *uart) static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val, u8 fcr_val) { - struct plat_serial8250_port *p = uart->p; u8 timeout = 255; - serial_write_reg(p, UART_OMAP_MDR1, mdr1_val); + serial_write_reg(uart, UART_OMAP_MDR1, mdr1_val); udelay(2); - serial_write_reg(p, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT | + serial_write_reg(uart, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR); /* * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and * TX_FIFO_E bit is 1. */ - while (UART_LSR_THRE != (serial_read_reg(p, UART_LSR) & + while (UART_LSR_THRE != (serial_read_reg(uart, UART_LSR) & (UART_LSR_THRE | UART_LSR_DR))) { timeout--; if (!timeout) { /* Should *never* happen. we warn and carry on */ - dev_crit(&uart->pdev.dev, "Errata i202: timedout %x\n", - serial_read_reg(p, UART_LSR)); + dev_crit(&uart->pdev->dev, "Errata i202: timedout %x\n", + serial_read_reg(uart, UART_LSR)); break; } udelay(1); @@ -224,23 +198,22 @@ static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val, static void omap_uart_save_context(struct omap_uart_state *uart) { u16 lcr = 0; - struct plat_serial8250_port *p = uart->p; if (!enable_off_mode) return; - lcr = serial_read_reg(p, UART_LCR); - serial_write_reg(p, UART_LCR, 0xBF); - uart->dll = serial_read_reg(p, UART_DLL); - uart->dlh = serial_read_reg(p, UART_DLM); - serial_write_reg(p, UART_LCR, lcr); - uart->ier = serial_read_reg(p, UART_IER); - uart->sysc = serial_read_reg(p, UART_OMAP_SYSC); - uart->scr = serial_read_reg(p, UART_OMAP_SCR); - uart->wer = serial_read_reg(p, UART_OMAP_WER); - serial_write_reg(p, UART_LCR, 0x80); - uart->mcr = serial_read_reg(p, UART_MCR); - serial_write_reg(p, UART_LCR, lcr); + lcr = serial_read_reg(uart, UART_LCR); + serial_write_reg(uart, UART_LCR, 0xBF); + uart->dll = serial_read_reg(uart, UART_DLL); + uart->dlh = serial_read_reg(uart, UART_DLM); + serial_write_reg(uart, UART_LCR, lcr); + uart->ier = serial_read_reg(uart, UART_IER); + uart->sysc = serial_read_reg(uart, UART_OMAP_SYSC); + uart->scr = serial_read_reg(uart, UART_OMAP_SCR); + uart->wer = serial_read_reg(uart, UART_OMAP_WER); + serial_write_reg(uart, UART_LCR, 0x80); + uart->mcr = serial_read_reg(uart, UART_MCR); + serial_write_reg(uart, UART_LCR, lcr); uart->context_valid = 1; } @@ -248,7 +221,6 @@ static void omap_uart_save_context(struct omap_uart_state *uart) static void omap_uart_restore_context(struct omap_uart_state *uart) { u16 efr = 0; - struct plat_serial8250_port *p = uart->p; if (!enable_off_mode) return; @@ -261,29 +233,30 @@ static void omap_uart_restore_context(struct omap_uart_state *uart) if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS) omap_uart_mdr1_errataset(uart, 0x07, 0xA0); else - serial_write_reg(p, UART_OMAP_MDR1, 0x7); - serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ - efr = serial_read_reg(p, UART_EFR); - serial_write_reg(p, UART_EFR, UART_EFR_ECB); - serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */ - serial_write_reg(p, UART_IER, 0x0); - serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ - serial_write_reg(p, UART_DLL, uart->dll); - serial_write_reg(p, UART_DLM, uart->dlh); - serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */ - serial_write_reg(p, UART_IER, uart->ier); - serial_write_reg(p, UART_LCR, 0x80); - serial_write_reg(p, UART_MCR, uart->mcr); - serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ - serial_write_reg(p, UART_EFR, efr); - serial_write_reg(p, UART_LCR, UART_LCR_WLEN8); - serial_write_reg(p, UART_OMAP_SCR, uart->scr); - serial_write_reg(p, UART_OMAP_WER, uart->wer); - serial_write_reg(p, UART_OMAP_SYSC, uart->sysc); + serial_write_reg(uart, UART_OMAP_MDR1, 0x7); + serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */ + efr = serial_read_reg(uart, UART_EFR); + serial_write_reg(uart, UART_EFR, UART_EFR_ECB); + serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */ + serial_write_reg(uart, UART_IER, 0x0); + serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */ + serial_write_reg(uart, UART_DLL, uart->dll); + serial_write_reg(uart, UART_DLM, uart->dlh); + serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */ + serial_write_reg(uart, UART_IER, uart->ier); + serial_write_reg(uart, UART_LCR, 0x80); + serial_write_reg(uart, UART_MCR, uart->mcr); + serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */ + serial_write_reg(uart, UART_EFR, efr); + serial_write_reg(uart, UART_LCR, UART_LCR_WLEN8); + serial_write_reg(uart, UART_OMAP_SCR, uart->scr); + serial_write_reg(uart, UART_OMAP_WER, uart->wer); + serial_write_reg(uart, UART_OMAP_SYSC, uart->sysc); if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS) omap_uart_mdr1_errataset(uart, 0x00, 0xA1); else - serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */ + /* UART 16x mode */ + serial_write_reg(uart, UART_OMAP_MDR1, 0x00); } #else static inline void omap_uart_save_context(struct omap_uart_state *uart) {} @@ -295,8 +268,7 @@ static inline void omap_uart_enable_clocks(struct omap_uart_state *uart) if (uart->clocked) return; - clk_enable(uart->ick); - clk_enable(uart->fck); + omap_device_enable(uart->pdev); uart->clocked = 1; omap_uart_restore_context(uart); } @@ -310,8 +282,7 @@ static inline void omap_uart_disable_clocks(struct omap_uart_state *uart) omap_uart_save_context(uart); uart->clocked = 0; - clk_disable(uart->ick); - clk_disable(uart->fck); + omap_device_idle(uart->pdev); } static void omap_uart_enable_wakeup(struct omap_uart_state *uart) @@ -349,18 +320,24 @@ static void omap_uart_disable_wakeup(struct omap_uart_state *uart) } static void omap_uart_smart_idle_enable(struct omap_uart_state *uart, - int enable) + int enable) { - struct plat_serial8250_port *p = uart->p; - u16 sysc; + u8 idlemode; - sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7; - if (enable) - sysc |= 0x2 << 3; - else - sysc |= 0x1 << 3; + if (enable) { + /** + * Errata 2.15: [UART]:Cannot Acknowledge Idle Requests + * in Smartidle Mode When Configured for DMA Operations. + */ + if (uart->dma_enabled) + idlemode = HWMOD_IDLEMODE_FORCE; + else + idlemode = HWMOD_IDLEMODE_SMART; + } else { + idlemode = HWMOD_IDLEMODE_NO; + } - serial_write_reg(p, UART_OMAP_SYSC, sysc); + omap_hwmod_set_slave_idlemode(uart->oh, idlemode); } static void omap_uart_block_sleep(struct omap_uart_state *uart) @@ -377,7 +354,7 @@ static void omap_uart_block_sleep(struct omap_uart_state *uart) static void omap_uart_allow_sleep(struct omap_uart_state *uart) { - if (device_may_wakeup(&uart->pdev.dev)) + if (device_may_wakeup(&uart->pdev->dev)) omap_uart_enable_wakeup(uart); else omap_uart_disable_wakeup(uart); @@ -472,6 +449,7 @@ int omap_uart_can_sleep(void) * UART will not idle or sleep for its timeout period. * **/ +/* static int first_interrupt; */ static irqreturn_t omap_uart_interrupt(int irq, void *dev_id) { struct omap_uart_state *uart = dev_id; @@ -483,7 +461,6 @@ static irqreturn_t omap_uart_interrupt(int irq, void *dev_id) static void omap_uart_idle_init(struct omap_uart_state *uart) { - struct plat_serial8250_port *p = uart->p; int ret; uart->can_sleep = 0; @@ -546,9 +523,9 @@ static void omap_uart_idle_init(struct omap_uart_state *uart) uart->padconf = 0; } - p->irqflags |= IRQF_SHARED; - ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED, - "serial idle", (void *)uart); + uart->irqflags |= IRQF_SHARED; + ret = request_threaded_irq(uart->irq, NULL, omap_uart_interrupt, + IRQF_SHARED, "serial idle", (void *)uart); WARN_ON(ret); } @@ -559,10 +536,13 @@ void omap_uart_enable_irqs(int enable) list_for_each_entry(uart, &uart_list, node) { if (enable) - ret = request_irq(uart->p->irq, omap_uart_interrupt, - IRQF_SHARED, "serial idle", (void *)uart); + ret = request_threaded_irq(uart->irq, NULL, + omap_uart_interrupt, + IRQF_SHARED, + "serial idle", + (void *)uart); else - free_irq(uart->p->irq, (void *)uart); + free_irq(uart->irq, (void *)uart); } } @@ -570,10 +550,9 @@ static ssize_t sleep_timeout_show(struct device *dev, struct device_attribute *attr, char *buf) { - struct platform_device *pdev = container_of(dev, - struct platform_device, dev); - struct omap_uart_state *uart = container_of(pdev, - struct omap_uart_state, pdev); + struct platform_device *pdev = to_platform_device(dev); + struct omap_device *odev = to_omap_device(pdev); + struct omap_uart_state *uart = odev->hwmods[0]->dev_attr; return sprintf(buf, "%u\n", uart->timeout / HZ); } @@ -582,10 +561,9 @@ static ssize_t sleep_timeout_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) { - struct platform_device *pdev = container_of(dev, - struct platform_device, dev); - struct omap_uart_state *uart = container_of(pdev, - struct omap_uart_state, pdev); + struct platform_device *pdev = to_platform_device(dev); + struct omap_device *odev = to_omap_device(pdev); + struct omap_uart_state *uart = odev->hwmods[0]->dev_attr; unsigned int value; if (sscanf(buf, "%u", &value) != 1) { @@ -608,48 +586,11 @@ static DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, #define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr)) #else static inline void omap_uart_idle_init(struct omap_uart_state *uart) {} +static void omap_uart_block_sleep(struct omap_uart_state *uart) {} #define DEV_CREATE_FILE(dev, attr) #endif /* CONFIG_PM */ -static struct omap_uart_state omap_uart[] = { - { - .pdev = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = serial_platform_data0, - }, - }, - }, { - .pdev = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM1, - .dev = { - .platform_data = serial_platform_data1, - }, - }, - }, { - .pdev = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM2, - .dev = { - .platform_data = serial_platform_data2, - }, - }, - }, -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) - { - .pdev = { - .name = "serial8250", - .id = 3, - .dev = { - .platform_data = serial_platform_data3, - }, - }, - }, -#endif -}; - +#ifndef CONFIG_SERIAL_OMAP /* * Override the default 8250 read handler: mem_serial_in() * Empty RX fifo read causes an abort on omap3630 and omap4 @@ -682,71 +623,44 @@ static void serial_out_override(struct uart_port *up, int offset, int value) } __serial_write_reg(up, offset, value); } +#endif + void __init omap_serial_early_init(void) { - int i, nr_ports; - char name[16]; + int i = 0; - if (!(cpu_is_omap3630() || cpu_is_omap4430())) - nr_ports = 3; - else - nr_ports = ARRAY_SIZE(omap_uart); + do { + char oh_name[MAX_UART_HWMOD_NAME_LEN]; + struct omap_hwmod *oh; + struct omap_uart_state *uart; - /* - * Make sure the serial ports are muxed on at this point. - * You have to mux them off in device drivers later on - * if not needed. - */ + snprintf(oh_name, MAX_UART_HWMOD_NAME_LEN, + "uart%d", i + 1); + oh = omap_hwmod_lookup(oh_name); + if (!oh) + break; + + uart = kzalloc(sizeof(struct omap_uart_state), GFP_KERNEL); + if (WARN_ON(!uart)) + return; - for (i = 0; i < nr_ports; i++) { - struct omap_uart_state *uart = &omap_uart[i]; - struct platform_device *pdev = &uart->pdev; - struct device *dev = &pdev->dev; - struct plat_serial8250_port *p = dev->platform_data; + uart->oh = oh; + uart->num = i++; + list_add_tail(&uart->node, &uart_list); + num_uarts++; - /* Don't map zero-based physical address */ - if (p->mapbase == 0) { - dev_warn(dev, "no physical address for uart#%d," - " so skipping early_init...\n", i); - continue; - } /* - * Module 4KB + L4 interconnect 4KB - * Static mapping, never released + * NOTE: omap_hwmod_init() has not yet been called, + * so no hwmod functions will work yet. */ - p->membase = ioremap(p->mapbase, SZ_8K); - if (!p->membase) { - dev_err(dev, "ioremap failed for uart%i\n", i + 1); - continue; - } - - sprintf(name, "uart%d_ick", i + 1); - uart->ick = clk_get(NULL, name); - if (IS_ERR(uart->ick)) { - dev_err(dev, "Could not get uart%d_ick\n", i + 1); - uart->ick = NULL; - } - sprintf(name, "uart%d_fck", i+1); - uart->fck = clk_get(NULL, name); - if (IS_ERR(uart->fck)) { - dev_err(dev, "Could not get uart%d_fck\n", i + 1); - uart->fck = NULL; - } - - /* FIXME: Remove this once the clkdev is ready */ - if (!cpu_is_omap44xx()) { - if (!uart->ick || !uart->fck) - continue; - } - - uart->num = i; - p->private_data = uart; - uart->p = p; - - if (cpu_is_omap44xx()) - p->irq += 32; - } + /* + * During UART early init, device need to be probed + * to determine SoC specific init before omap_device + * is ready. Therefore, don't allow idle here + */ + uart->oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET; + } while (1); } /** @@ -763,53 +677,135 @@ void __init omap_serial_early_init(void) void __init omap_serial_init_port(int port) { struct omap_uart_state *uart; - struct platform_device *pdev; - struct device *dev; - - BUG_ON(port < 0); - BUG_ON(port >= ARRAY_SIZE(omap_uart)); - - uart = &omap_uart[port]; - pdev = &uart->pdev; - dev = &pdev->dev; + struct omap_hwmod *oh; + struct omap_device *od; + void *pdata = NULL; + u32 pdata_size = 0; + char *name; +#ifndef CONFIG_SERIAL_OMAP + struct plat_serial8250_port ports[2] = { + {}, + {.flags = 0}, + }; + struct plat_serial8250_port *p = &ports[0]; +#else + struct omap_uart_port_info omap_up; +#endif - /* Don't proceed if there's no clocks available */ - if (unlikely(!uart->ick || !uart->fck)) { - WARN(1, "%s: can't init uart%d, no clocks available\n", - kobject_name(&dev->kobj), port); + if (WARN_ON(port < 0)) + return; + if (WARN_ON(port >= num_uarts)) return; - } - - omap_uart_enable_clocks(uart); - - omap_uart_reset(uart); - omap_uart_idle_init(uart); - list_add_tail(&uart->node, &uart_list); + list_for_each_entry(uart, &uart_list, node) + if (port == uart->num) + break; - if (WARN_ON(platform_device_register(pdev))) - return; + oh = uart->oh; + uart->dma_enabled = 0; +#ifndef CONFIG_SERIAL_OMAP + name = "serial8250"; - if ((cpu_is_omap34xx() && uart->padconf) || - (uart->wk_en && uart->wk_mask)) { - device_init_wakeup(dev, true); - DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout); - } + /* + * !! 8250 driver does not use standard IORESOURCE* It + * has it's own custom pdata that can be taken from + * the hwmod resource data. But, this needs to be + * done after the build. + * + * ?? does it have to be done before the register ?? + * YES, because platform_device_data_add() copies + * pdata, it does not use a pointer. + */ + p->flags = UPF_BOOT_AUTOCONF; + p->iotype = UPIO_MEM; + p->regshift = 2; + p->uartclk = OMAP24XX_BASE_BAUD * 16; + p->irq = oh->mpu_irqs[0].irq; + p->mapbase = oh->slaves[0]->addr->pa_start; + p->membase = omap_hwmod_get_mpu_rt_va(oh); + p->irqflags = IRQF_SHARED; + p->private_data = uart; /* * omap44xx: Never read empty UART fifo * omap3xxx: Never read empty UART fifo on UARTs * with IP rev >=0x52 */ + uart->regshift = p->regshift; + uart->membase = p->membase; if (cpu_is_omap44xx()) uart->errata |= UART_ERRATA_FIFO_FULL_ABORT; - else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF) + else if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF) >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV) uart->errata |= UART_ERRATA_FIFO_FULL_ABORT; if (uart->errata & UART_ERRATA_FIFO_FULL_ABORT) { - uart->p->serial_in = serial_in_override; - uart->p->serial_out = serial_out_override; + p->serial_in = serial_in_override; + p->serial_out = serial_out_override; + } + + pdata = &ports[0]; + pdata_size = 2 * sizeof(struct plat_serial8250_port); +#else + + name = DRIVER_NAME; + + omap_up.dma_enabled = uart->dma_enabled; + omap_up.uartclk = OMAP24XX_BASE_BAUD * 16; + omap_up.mapbase = oh->slaves[0]->addr->pa_start; + omap_up.membase = omap_hwmod_get_mpu_rt_va(oh); + omap_up.irqflags = IRQF_SHARED; + omap_up.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; + + pdata = &omap_up; + pdata_size = sizeof(struct omap_uart_port_info); +#endif + + if (WARN_ON(!oh)) + return; + + od = omap_device_build(name, uart->num, oh, pdata, pdata_size, + omap_uart_latency, + ARRAY_SIZE(omap_uart_latency), false); + WARN(IS_ERR(od), "Could not build omap_device for %s: %s.\n", + name, oh->name); + + uart->irq = oh->mpu_irqs[0].irq; + uart->regshift = 2; + uart->mapbase = oh->slaves[0]->addr->pa_start; + uart->membase = omap_hwmod_get_mpu_rt_va(oh); + uart->pdev = &od->pdev; + + oh->dev_attr = uart; + + /* + * Because of early UART probing, UART did not get idled + * on init. Now that omap_device is ready, ensure full idle + * before doing omap_device_enable(). + */ + omap_hwmod_idle(uart->oh); + + omap_device_enable(uart->pdev); + omap_uart_idle_init(uart); + omap_uart_reset(uart); + omap_hwmod_enable_wakeup(uart->oh); + omap_device_idle(uart->pdev); + + /* + * Need to block sleep long enough for interrupt driven + * driver to start. Console driver is in polling mode + * so device needs to be kept enabled while polling driver + * is in use. + */ + if (uart->timeout) + uart->timeout = (30 * HZ); + omap_uart_block_sleep(uart); + uart->timeout = DEFAULT_TIMEOUT; + + if ((cpu_is_omap34xx() && uart->padconf) || + (uart->wk_en && uart->wk_mask)) { + device_init_wakeup(&od->pdev.dev, true); + DEV_CREATE_FILE(&od->pdev.dev, &dev_attr_sleep_timeout); } /* Enable the MDR1 errata for OMAP3 */ @@ -826,13 +822,8 @@ void __init omap_serial_init_port(int port) */ void __init omap_serial_init(void) { - int i, nr_ports; - - if (!(cpu_is_omap3630() || cpu_is_omap4430())) - nr_ports = 3; - else - nr_ports = ARRAY_SIZE(omap_uart); + struct omap_uart_state *uart; - for (i = 0; i < nr_ports; i++) - omap_serial_init_port(i); + list_for_each_entry(uart, &uart_list, node) + omap_serial_init_port(uart->num); } -- cgit v1.1 From c04ede382a64020f19e9aa23a85493a09af945d3 Mon Sep 17 00:00:00 2001 From: "Govindraj.R" Date: Mon, 27 Sep 2010 20:19:46 +0530 Subject: OMAP2: UART: remove set_uart_globals Remove set_uart_globals function as this will not be needed as physical address for uarts will be taken from hwmod data file. Signed-off-by: Govindraj.R Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/serial.c | 5 ----- arch/arm/plat-omap/common.c | 16 ---------------- arch/arm/plat-omap/include/plat/common.h | 1 - 3 files changed, 22 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index e6c4027..6ffbc92 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -104,11 +104,6 @@ struct omap_uart_state { static LIST_HEAD(uart_list); static u8 num_uarts; - -void __init omap2_set_globals_uart(struct omap_globals *omap2_globals) -{ -} - static struct omap_device_pm_latency omap_uart_latency[] = { { .deactivate_func = omap_device_idle_hwmods, diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c index 7d668b3..947de3f 100644 --- a/arch/arm/plat-omap/common.c +++ b/arch/arm/plat-omap/common.c @@ -257,7 +257,6 @@ static void __init __omap2_set_globals(struct omap_globals *omap2_globals) omap2_set_globals_sdrc(omap2_globals); omap2_set_globals_control(omap2_globals); omap2_set_globals_prcm(omap2_globals); - omap2_set_globals_uart(omap2_globals); } #endif @@ -272,9 +271,6 @@ static struct omap_globals omap242x_globals = { .ctrl = OMAP2420_CTRL_BASE, .prm = OMAP2420_PRM_BASE, .cm = OMAP2420_CM_BASE, - .uart1_phys = OMAP2_UART1_BASE, - .uart2_phys = OMAP2_UART2_BASE, - .uart3_phys = OMAP2_UART3_BASE, }; void __init omap2_set_globals_242x(void) @@ -293,9 +289,6 @@ static struct omap_globals omap243x_globals = { .ctrl = OMAP243X_CTRL_BASE, .prm = OMAP2430_PRM_BASE, .cm = OMAP2430_CM_BASE, - .uart1_phys = OMAP2_UART1_BASE, - .uart2_phys = OMAP2_UART2_BASE, - .uart3_phys = OMAP2_UART3_BASE, }; void __init omap2_set_globals_243x(void) @@ -314,10 +307,6 @@ static struct omap_globals omap3_globals = { .ctrl = OMAP343X_CTRL_BASE, .prm = OMAP3430_PRM_BASE, .cm = OMAP3430_CM_BASE, - .uart1_phys = OMAP3_UART1_BASE, - .uart2_phys = OMAP3_UART2_BASE, - .uart3_phys = OMAP3_UART3_BASE, - .uart4_phys = OMAP3_UART4_BASE, /* Only on 3630 */ }; void __init omap2_set_globals_3xxx(void) @@ -341,10 +330,6 @@ static struct omap_globals omap4_globals = { .prm = OMAP4430_PRM_BASE, .cm = OMAP4430_CM_BASE, .cm2 = OMAP4430_CM2_BASE, - .uart1_phys = OMAP4_UART1_BASE, - .uart2_phys = OMAP4_UART2_BASE, - .uart3_phys = OMAP4_UART3_BASE, - .uart4_phys = OMAP4_UART4_BASE, }; void __init omap2_set_globals_443x(void) @@ -352,7 +337,6 @@ void __init omap2_set_globals_443x(void) omap2_set_globals_tap(&omap4_globals); omap2_set_globals_control(&omap4_globals); omap2_set_globals_prcm(&omap4_globals); - omap2_set_globals_uart(&omap4_globals); } #endif diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h index 2d8f98d..a9d69a0 100644 --- a/arch/arm/plat-omap/include/plat/common.h +++ b/arch/arm/plat-omap/include/plat/common.h @@ -67,7 +67,6 @@ void omap2_set_globals_tap(struct omap_globals *); void omap2_set_globals_sdrc(struct omap_globals *); void omap2_set_globals_control(struct omap_globals *); void omap2_set_globals_prcm(struct omap_globals *); -void omap2_set_globals_uart(struct omap_globals *); void omap3_map_io(void); -- cgit v1.1 From 3244fcd227526a2f21018a280c7af0a9219c6ff4 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Mon, 27 Sep 2010 20:19:53 +0530 Subject: OMAP: UART: don't do automatic bus-level suspend/resume Since the omap_device for UART is currently managed inside the idle path itself, don't let the bus-level code suspend/resume the UART. To prevent this, pm_runtime_get() is used when preparing for suspend and pm_runtime_put() is used when finished with suspend. Signed-off-by: Govindraj.R Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/serial.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index 6ffbc92..ff83e91 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -26,6 +26,7 @@ #include #include #include +#include #ifdef CONFIG_SERIAL_OMAP #include @@ -530,14 +531,17 @@ void omap_uart_enable_irqs(int enable) struct omap_uart_state *uart; list_for_each_entry(uart, &uart_list, node) { - if (enable) + if (enable) { + pm_runtime_put_sync(&uart->pdev->dev); ret = request_threaded_irq(uart->irq, NULL, omap_uart_interrupt, IRQF_SHARED, "serial idle", (void *)uart); - else + } else { + pm_runtime_get_noresume(&uart->pdev->dev); free_irq(uart->irq, (void *)uart); + } } } -- cgit v1.1 From 8da37d9dc52befa8b55bdc20eef2a4aaf20e0c8d Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Mon, 27 Sep 2010 20:20:06 +0530 Subject: OMAP: UART: use non-locking versions of hwmod enable/idle functions Since the UART enable/idle is done during the idle path (with interrupts disabled), use the non-locking versions of the hwmod enable/idle functions. Signed-off-by: Govindraj.R Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/serial.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index ff83e91..72b5c98 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -105,10 +105,29 @@ struct omap_uart_state { static LIST_HEAD(uart_list); static u8 num_uarts; +/* + * Since these idle/enable hooks are used in the idle path itself + * which has interrupts disabled, use the non-locking versions of + * the hwmod enable/disable functions. + */ +static int uart_idle_hwmod(struct omap_device *od) +{ + _omap_hwmod_idle(od->hwmods[0]); + + return 0; +} + +static int uart_enable_hwmod(struct omap_device *od) +{ + _omap_hwmod_enable(od->hwmods[0]); + + return 0; +} + static struct omap_device_pm_latency omap_uart_latency[] = { { - .deactivate_func = omap_device_idle_hwmods, - .activate_func = omap_device_enable_hwmods, + .deactivate_func = uart_idle_hwmod, + .activate_func = uart_enable_hwmod, .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, }, }; -- cgit v1.1 From a0edcdbe5295b7912e92ff88dd8f46646710735b Mon Sep 17 00:00:00 2001 From: "Govindraj.R" Date: Mon, 27 Sep 2010 20:20:17 +0530 Subject: OMAP clock: Add uart4_ick/fck definitions for 3630 This is only valid for omap 36xx family of chips. Signed-off-by: Sergio Aguirre Signed-off-by: Govindraj.R Acked-by: Paul Walmsley Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/clock3xxx_data.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index c73906d..ba01ec0 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -2465,6 +2465,16 @@ static struct clk uart3_fck = { .recalc = &followparent_recalc, }; +static struct clk uart4_fck = { + .name = "uart4_fck", + .ops = &clkops_omap2_dflt_wait, + .parent = &per_48m_fck, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), + .enable_bit = OMAP3630_EN_UART4_SHIFT, + .clkdm_name = "per_clkdm", + .recalc = &followparent_recalc, +}; + static struct clk gpt2_fck = { .name = "gpt2_fck", .ops = &clkops_omap2_dflt_wait, @@ -2715,6 +2725,16 @@ static struct clk uart3_ick = { .recalc = &followparent_recalc, }; +static struct clk uart4_ick = { + .name = "uart4_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &per_l4_ick, + .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), + .enable_bit = OMAP3630_EN_UART4_SHIFT, + .clkdm_name = "per_clkdm", + .recalc = &followparent_recalc, +}; + static struct clk gpt9_ick = { .name = "gpt9_ick", .ops = &clkops_omap2_dflt_wait, @@ -3349,6 +3369,7 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "per_96m_fck", &per_96m_fck, CK_3XXX), CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX), CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX), + CLK(NULL, "uart4_fck", &uart4_fck, CK_36XX), CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX), CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX), CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX), @@ -3372,6 +3393,7 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "gpio2_ick", &gpio2_ick, CK_3XXX), CLK(NULL, "wdt3_ick", &wdt3_ick, CK_3XXX), CLK(NULL, "uart3_ick", &uart3_ick, CK_3XXX), + CLK(NULL, "uart4_ick", &uart4_ick, CK_36XX), CLK(NULL, "gpt9_ick", &gpt9_ick, CK_3XXX), CLK(NULL, "gpt8_ick", &gpt8_ick, CK_3XXX), CLK(NULL, "gpt7_ick", &gpt7_ick, CK_3XXX), -- cgit v1.1 From e586368904b737b4888927e4c869a25966e5cd05 Mon Sep 17 00:00:00 2001 From: "Govindraj.R" Date: Mon, 27 Sep 2010 20:20:25 +0530 Subject: OMAP3: PRCM: Consider UART4 for 3630 chip in prcm_setup_regs To standarize among other uarts (1 to 3), we shall now: - Enable uart4 autodile bit. - Enable uart4 wakeup in PER. - Allow uart4 to wakeup the MPU. Signed-off-by: Sergio Aguirre Signed-off-by: Govindraj.R Acked-by: Paul Walmsley Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/cm-regbits-34xx.h | 2 ++ arch/arm/mach-omap2/pm34xx.c | 15 +++++++++++++-- arch/arm/mach-omap2/prcm-common.h | 2 ++ arch/arm/mach-omap2/prm-regbits-34xx.h | 1 + 4 files changed, 18 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h index fe82b79..4f959a7 100644 --- a/arch/arm/mach-omap2/cm-regbits-34xx.h +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h @@ -649,6 +649,8 @@ #define OMAP3430_ST_MCBSP2_MASK (1 << 0) /* CM_AUTOIDLE_PER */ +#define OMAP3630_AUTO_UART4_MASK (1 << 18) +#define OMAP3630_AUTO_UART4_SHIFT 18 #define OMAP3430_AUTO_GPIO6_MASK (1 << 17) #define OMAP3430_AUTO_GPIO6_SHIFT 17 #define OMAP3430_AUTO_GPIO5_MASK (1 << 16) diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index d2b940c..043faaa 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -676,6 +676,14 @@ static void __init omap3_d2d_idle(void) static void __init prcm_setup_regs(void) { + u32 omap3630_auto_uart4_mask = cpu_is_omap3630() ? + OMAP3630_AUTO_UART4_MASK : 0; + u32 omap3630_en_uart4_mask = cpu_is_omap3630() ? + OMAP3630_EN_UART4_MASK : 0; + u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ? + OMAP3630_GRPSEL_UART4_MASK : 0; + + /* XXX Reset all wkdeps. This should be done when initializing * powerdomains */ prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP); @@ -762,6 +770,7 @@ static void __init prcm_setup_regs(void) CM_AUTOIDLE); cm_write_mod_reg( + omap3630_auto_uart4_mask | OMAP3430_AUTO_GPIO6_MASK | OMAP3430_AUTO_GPIO5_MASK | OMAP3430_AUTO_GPIO4_MASK | @@ -838,14 +847,16 @@ static void __init prcm_setup_regs(void) OMAP3430_DSS_MOD, PM_WKEN); /* Enable wakeups in PER */ - prm_write_mod_reg(OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK | + prm_write_mod_reg(omap3630_en_uart4_mask | + OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK | OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK | OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK | OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK | OMAP3430_EN_MCBSP4_MASK, OMAP3430_PER_MOD, PM_WKEN); /* and allow them to wake up MPU */ - prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2_MASK | + prm_write_mod_reg(omap3630_grpsel_uart4_mask | + OMAP3430_GRPSEL_GPIO2_MASK | OMAP3430_GRPSEL_GPIO3_MASK | OMAP3430_GRPSEL_GPIO4_MASK | OMAP3430_GRPSEL_GPIO5_MASK | diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h index 86edcf9..298a22a 100644 --- a/arch/arm/mach-omap2/prcm-common.h +++ b/arch/arm/mach-omap2/prcm-common.h @@ -425,6 +425,8 @@ #define OMAP3430_EN_MCBSP2_SHIFT 0 /* CM_IDLEST_PER, PM_WKST_PER shared bits */ +#define OMAP3630_ST_UART4_SHIFT 18 +#define OMAP3630_ST_UART4_MASK (1 << 18) #define OMAP3430_ST_GPIO6_SHIFT 17 #define OMAP3430_ST_GPIO6_MASK (1 << 17) #define OMAP3430_ST_GPIO5_SHIFT 16 diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h index 7fd6023..9e63cb7 100644 --- a/arch/arm/mach-omap2/prm-regbits-34xx.h +++ b/arch/arm/mach-omap2/prm-regbits-34xx.h @@ -122,6 +122,7 @@ #define OMAP3430_MEMRETSTATE_MASK (1 << 8) /* PM_MPUGRPSEL_PER, PM_IVA2GRPSEL_PER shared bits */ +#define OMAP3630_GRPSEL_UART4_MASK (1 << 18) #define OMAP3430_GRPSEL_GPIO6_MASK (1 << 17) #define OMAP3430_GRPSEL_GPIO5_MASK (1 << 16) #define OMAP3430_GRPSEL_GPIO4_MASK (1 << 15) -- cgit v1.1 From cd4f1faee029593fc10039aeb592dc2986d55f61 Mon Sep 17 00:00:00 2001 From: "Govindraj.R" Date: Mon, 27 Sep 2010 20:20:32 +0530 Subject: OMAP3: PM: Add prepare idle and resume idle call for uart4 Add prepare idle and resume idle call for uart4 used by 3630. Signed-off-by: Govindraj.R Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/pm34xx.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 043faaa..60baffa 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -388,6 +388,7 @@ void omap_sram_idle(void) /* PER */ if (per_next_state < PWRDM_POWER_ON) { omap_uart_prepare_idle(2); + omap_uart_prepare_idle(3); omap2_gpio_prepare_for_idle(per_next_state); if (per_next_state == PWRDM_POWER_OFF) omap3_per_save_context(); @@ -459,6 +460,7 @@ void omap_sram_idle(void) if (per_prev_state == PWRDM_POWER_OFF) omap3_per_restore_context(); omap_uart_resume_idle(2); + omap_uart_resume_idle(3); } /* Disable IO-PAD and IO-CHAIN wakeup */ -- cgit v1.1 From 52663aea10c3ce175b636ff3ed5a6d78fdbeec02 Mon Sep 17 00:00:00 2001 From: "Govindraj.R" Date: Mon, 27 Sep 2010 20:20:41 +0530 Subject: OMAP3: serial: Fix uart4 handling for 3630 This patch makes the following: - Adds missing wakeup padding register handling. - Fixes a hardcode to use PER module ONLY on UART3. Signed-off-by: Sergio Aguirre Signed-off-by: Govindraj.R Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/serial.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index 72b5c98..0bcc9df 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -487,7 +487,7 @@ static void omap_uart_idle_init(struct omap_uart_state *uart) omap_uart_smart_idle_enable(uart, 0); if (cpu_is_omap34xx()) { - u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD; + u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD; u32 wk_mask = 0; u32 padconf = 0; @@ -506,6 +506,10 @@ static void omap_uart_idle_init(struct omap_uart_state *uart) wk_mask = OMAP3430_ST_UART3_MASK; padconf = 0x19e; break; + case 3: + wk_mask = OMAP3630_ST_UART4_MASK; + padconf = 0x0d2; + break; } uart->wk_mask = wk_mask; uart->padconf = padconf; -- cgit v1.1 From b612633b5928077441b979471869753bfa93d41a Mon Sep 17 00:00:00 2001 From: "Govindraj.R" Date: Mon, 27 Sep 2010 20:20:49 +0530 Subject: serial: Add OMAP high-speed UART driver This patch adds driver support for OMAP2/3/4 high speed UART. The driver is made separate from 8250 driver as we cannot over load 8250 driver with omap platform specific configuration for features like DMA, it makes easier to implement features like DMA and hardware flow control and software flow control configuration with this driver as required for the omap-platform. This patch involves only the core driver and its dependent. Cc: Tony Lindgren Signed-off-by: Govindraj.R Acked-by: Alan Cox Acked-by: Greg Kroah-Hartman Signed-off-by: Kevin Hilman --- arch/arm/plat-omap/include/plat/omap-serial.h | 129 ++++++++++++++++++++++++++ 1 file changed, 129 insertions(+) create mode 100644 arch/arm/plat-omap/include/plat/omap-serial.h (limited to 'arch') diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h new file mode 100644 index 0000000..0d6f076 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/omap-serial.h @@ -0,0 +1,129 @@ +/* + * Driver for OMAP-UART controller. + * Based on drivers/serial/8250.c + * + * Copyright (C) 2010 Texas Instruments. + * + * Authors: + * Govindraj R + * Thara Gopinath + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __OMAP_SERIAL_H__ +#define __OMAP_SERIAL_H__ + +#include +#include + +#include +#include + +#define DRIVER_NAME "omap-hsuart" + +/* + * Use tty device name as ttyO, [O -> OMAP] + * in bootargs we specify as console=ttyO0 if uart1 + * is used as console uart. + */ +#define OMAP_SERIAL_NAME "ttyO" + +#define OMAP_MDR1_DISABLE 0x07 +#define OMAP_MDR1_MODE13X 0x03 +#define OMAP_MDR1_MODE16X 0x00 +#define OMAP_MODE13X_SPEED 230400 + +/* + * LCR = 0XBF: Switch to Configuration Mode B. + * In configuration mode b allow access + * to EFR,DLL,DLH. + * Reference OMAP TRM Chapter 17 + * Section: 1.4.3 Mode Selection + */ +#define OMAP_UART_LCR_CONF_MDB 0XBF + +/* WER = 0x7F + * Enable module level wakeup in WER reg + */ +#define OMAP_UART_WER_MOD_WKUP 0X7F + +/* Enable XON/XOFF flow control on output */ +#define OMAP_UART_SW_TX 0x04 + +/* Enable XON/XOFF flow control on input */ +#define OMAP_UART_SW_RX 0x04 + +#define OMAP_UART_SYSC_RESET 0X07 +#define OMAP_UART_TCR_TRIG 0X0F +#define OMAP_UART_SW_CLR 0XF0 +#define OMAP_UART_FIFO_CLR 0X06 + +#define OMAP_UART_DMA_CH_FREE -1 + +#define RX_TIMEOUT (3 * HZ) +#define OMAP_MAX_HSUART_PORTS 4 + +#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA + +struct omap_uart_port_info { + bool dma_enabled; /* To specify DMA Mode */ + unsigned int uartclk; /* UART clock rate */ + void __iomem *membase; /* ioremap cookie or NULL */ + resource_size_t mapbase; /* resource base */ + unsigned long irqflags; /* request_irq flags */ + upf_t flags; /* UPF_* flags */ +}; + +struct uart_omap_dma { + u8 uart_dma_tx; + u8 uart_dma_rx; + int rx_dma_channel; + int tx_dma_channel; + dma_addr_t rx_buf_dma_phys; + dma_addr_t tx_buf_dma_phys; + unsigned int uart_base; + /* + * Buffer for rx dma.It is not required for tx because the buffer + * comes from port structure. + */ + unsigned char *rx_buf; + unsigned int prev_rx_dma_pos; + int tx_buf_size; + int tx_dma_used; + int rx_dma_used; + spinlock_t tx_lock; + spinlock_t rx_lock; + /* timer to poll activity on rx dma */ + struct timer_list rx_timer; + int rx_buf_size; + int rx_timeout; +}; + +struct uart_omap_port { + struct uart_port port; + struct uart_omap_dma uart_dma; + struct platform_device *pdev; + + unsigned char ier; + unsigned char lcr; + unsigned char mcr; + unsigned char fcr; + unsigned char efr; + + int use_dma; + /* + * Some bits in registers are cleared on a read, so they must + * be saved whenever the register is read but the bits will not + * be immediately processed. + */ + unsigned int lsr_break_flag; + unsigned char msr_saved_flags; + char name[20]; + unsigned long port_activity; +}; + +#endif /* __OMAP_SERIAL_H__ */ -- cgit v1.1 From 12a75da296d43784c960a2beaca002a08d06cf15 Mon Sep 17 00:00:00 2001 From: "Govindraj.R" Date: Mon, 27 Sep 2010 20:20:57 +0530 Subject: OMAP: SERIAL: Enable omap-serial driver in Kconfig Enable omap-serial driver in /mach-omap2/Kconfig and move 8250 driver selection for zoom boards. With omap-serial driver addition all omap-uarts can be handled with omap-serial driver. With addition of omap-serial driver console parameter needs be changed in bootargs from ttyS* should be replaced with ttyO* [O --> OMAP not ZERO] For example: ttyS0[UART1 on 3430SDP] changes to ttyO0. But with some boards that do not use omap-uart as console uart. we need to handle them with 8250 driver. Ex: ZOOM2/3. For zoom2/3 board we need to use 8250 serial driver and console parameter will remain ttyS0 which basically uses a Quad uart placed on the debug board connected through a gpio line. Signed-off-by: Govindraj.R Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/Kconfig | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 1c4b237..91dd215 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -11,9 +11,8 @@ config ARCH_OMAP2PLUS_TYPICAL select PM_RUNTIME select VFP select NEON if ARCH_OMAP3 || ARCH_OMAP4 - select SERIAL_8250 - select SERIAL_CORE_CONSOLE - select SERIAL_8250_CONSOLE + select SERIAL_OMAP + select SERIAL_OMAP_CONSOLE select I2C select I2C_OMAP select MFD @@ -222,12 +221,18 @@ config MACH_OMAP_ZOOM2 depends on ARCH_OMAP3 default y select OMAP_PACKAGE_CBB + select SERIAL_8250 + select SERIAL_CORE_CONSOLE + select SERIAL_8250_CONSOLE config MACH_OMAP_ZOOM3 bool "OMAP3630 Zoom3 board" depends on ARCH_OMAP3 default y select OMAP_PACKAGE_CBP + select SERIAL_8250 + select SERIAL_CORE_CONSOLE + select SERIAL_8250_CONSOLE config MACH_CM_T35 bool "CompuLab CM-T35 module" -- cgit v1.1 From 257f23d87f9309fee41d468575404b9371bf4c7d Mon Sep 17 00:00:00 2001 From: "Govindraj.R" Date: Mon, 27 Sep 2010 20:21:05 +0530 Subject: OMAP3: SERIAL: Initialize all omap-uarts for zoom boards Initialize all omap-uarts for zoom boards. Now zoom_peripheral_init will initialise all uarts for 3630. 3630sdp_board_init call zoom_peripheral_init so we can now remove serial_init from 3630sdp board init as zoom_peripheral_init now will do that the same. Signed-off-by: Anand Gadiyar Signed-off-by: Govindraj.R Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/board-3630sdp.c | 1 - arch/arm/mach-omap2/board-zoom-peripherals.c | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c index b359c3f..d510451 100644 --- a/arch/arm/mach-omap2/board-3630sdp.c +++ b/arch/arm/mach-omap2/board-3630sdp.c @@ -208,7 +208,6 @@ static struct flash_partitions sdp_flash_partitions[] = { static void __init omap_sdp_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBP); - omap_serial_init(); zoom_peripherals_init(); board_smc91x_init(); board_flash_init(sdp_flash_partitions, chip_sel_sdp); diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c index e5eac46..35066b3 100644 --- a/arch/arm/mach-omap2/board-zoom-peripherals.c +++ b/arch/arm/mach-omap2/board-zoom-peripherals.c @@ -283,4 +283,5 @@ void __init zoom_peripherals_init(void) omap_i2c_init(); usb_musb_init(&musb_board_data); enable_board_wakeup_source(); + omap_serial_init(); } -- cgit v1.1 From 4c62c595c2a23fb36a0b901b550115370047a137 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Fri, 17 Sep 2010 09:25:10 +0000 Subject: sh: fix a kfree address in clkdev code kfree() in clkdev_drop() function should actually be called with an address of a struct clk_lookup_alloc object, and not struct clk_lookup, as presently done. This just happens to work, because "struct clk_lookup cl" is the first member in struct clk_lookup_alloc. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Paul Mundt --- arch/sh/kernel/clkdev.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/sh/kernel/clkdev.c b/arch/sh/kernel/clkdev.c index befc255..1f800ef 100644 --- a/arch/sh/kernel/clkdev.c +++ b/arch/sh/kernel/clkdev.c @@ -161,9 +161,11 @@ EXPORT_SYMBOL(clk_add_alias); */ void clkdev_drop(struct clk_lookup *cl) { + struct clk_lookup_alloc *cla = container_of(cl, struct clk_lookup_alloc, cl); + mutex_lock(&clocks_mutex); list_del(&cl->node); mutex_unlock(&clocks_mutex); - kfree(cl); + kfree(cla); } EXPORT_SYMBOL(clkdev_drop); -- cgit v1.1 From 68a1aed7039e5a94a8e60e23fdf676738c36086a Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Fri, 24 Sep 2010 09:05:38 +0000 Subject: sh: boot kernel with SR.BL set Update the SH kernel to keep SR.BL set until the VBR register has been initialized. Useful to allow boot of the kernel even though exceptions are pending. Without this patch there is a window of time when exceptions such as NMI are enabled but no exception handlers are installed. This patch modifies both the zImage loader and the actual kernel to boot with BL=1, but the zImage loader is modfied in such a way that the init_sr value is unchanged to not break the zImage loader provided by kexec. Tested on sh7724 Ecovec and on the SH4AL-DSP core included in sh7372. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- arch/sh/boot/compressed/head_32.S | 4 +++- arch/sh/kernel/head_32.S | 2 +- arch/sh/kernel/traps_32.c | 3 +++ 3 files changed, 7 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/sh/boot/compressed/head_32.S b/arch/sh/boot/compressed/head_32.S index 200c1d4..3e15032 100644 --- a/arch/sh/boot/compressed/head_32.S +++ b/arch/sh/boot/compressed/head_32.S @@ -91,7 +91,9 @@ bss_start_addr: end_addr: .long _end init_sr: - .long 0x400000F0 /* Privileged mode, Bank=0, Block=0, IMASK=0xF */ + .long 0x500000F0 /* Privileged mode, Bank=0, Block=1, IMASK=0xF */ +kexec_magic: + .long 0x400000F0 /* magic used by kexec to parse zImage format */ init_stack_addr: .long stack_start decompress_kernel_addr: diff --git a/arch/sh/kernel/head_32.S b/arch/sh/kernel/head_32.S index 6e35f01..7db2489 100644 --- a/arch/sh/kernel/head_32.S +++ b/arch/sh/kernel/head_32.S @@ -330,7 +330,7 @@ ENTRY(_stext) #if defined(CONFIG_CPU_SH2) 1: .long 0x000000F0 ! IMASK=0xF #else -1: .long 0x400080F0 ! MD=1, RB=0, BL=0, FD=1, IMASK=0xF +1: .long 0x500080F0 ! MD=1, RB=0, BL=1, FD=1, IMASK=0xF #endif ENTRY(stack_start) 2: .long init_thread_union+THREAD_SIZE diff --git a/arch/sh/kernel/traps_32.c b/arch/sh/kernel/traps_32.c index c3d86fa..f561352 100644 --- a/arch/sh/kernel/traps_32.c +++ b/arch/sh/kernel/traps_32.c @@ -802,6 +802,9 @@ void __cpuinit per_cpu_trap_init(void) : /* no output */ : "r" (&vbr_base) : "memory"); + + /* disable exception blocking now when the vbr has been setup */ + clear_bl_bit(); } void *set_exception_table_vec(unsigned int vec, void *handler) -- cgit v1.1 From b365a85c68161ea5db5476eb8845a91ceb1777ea Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Wed, 29 Sep 2010 10:41:05 +0200 Subject: x86, UV: Use allocated buffer in tlb_uv.c:tunables_read() The original code didn't check that the value returned from snprintf() was less than the size of the buffer. Although it didn't cause a runtime bug in this case, it makes the static checkers complain. Andrew Morton suggested a dynamically sized buffer would be cleaner. Suggested-by: Andrew Morton Signed-off-by: Dan Carpenter Cc: Cliff Wickman Cc: Jack Steiner Cc: Robin Holt LKML-Reference: <20100929083118.GA6376@bicker> Signed-off-by: Ingo Molnar --- arch/x86/kernel/tlb_uv.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/x86/kernel/tlb_uv.c b/arch/x86/kernel/tlb_uv.c index 312ef02..33e77e4 100644 --- a/arch/x86/kernel/tlb_uv.c +++ b/arch/x86/kernel/tlb_uv.c @@ -1001,10 +1001,10 @@ static int uv_ptc_seq_show(struct seq_file *file, void *data) static ssize_t tunables_read(struct file *file, char __user *userbuf, size_t count, loff_t *ppos) { - char buf[300]; + char *buf; int ret; - ret = snprintf(buf, 300, "%s %s %s\n%d %d %d %d %d %d %d %d %d\n", + buf = kasprintf(GFP_KERNEL, "%s %s %s\n%d %d %d %d %d %d %d %d %d\n", "max_bau_concurrent plugged_delay plugsb4reset", "timeoutsb4reset ipi_reset_limit complete_threshold", "congested_response_us congested_reps congested_period", @@ -1012,7 +1012,12 @@ static ssize_t tunables_read(struct file *file, char __user *userbuf, timeoutsb4reset, ipi_reset_limit, complete_threshold, congested_response_us, congested_reps, congested_period); - return simple_read_from_buffer(userbuf, count, ppos, buf, ret); + if (!buf) + return -ENOMEM; + + ret = simple_read_from_buffer(userbuf, count, ppos, buf, strlen(buf)); + kfree(buf); + return ret; } /* -- cgit v1.1 From 205d231bfbd26bb10400518586d2a9f1b62858ee Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Thu, 30 Sep 2010 13:46:14 -0700 Subject: ASoC: Remove -dai suffix from i.MX SSI driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit While it is a generic serial port in practice the i.MX SSI is only supported in Linux as an audio port (the i.MX has dedicated SPI controllers and so on). This means we don't need to disambiguate against other uses of the hardware and so can drop the -dai suffix from the driver name which fixes merge issues with the i.MX tree in -next. Signed-off-by: Mark Brown Acked-by: Uwe Kleine-König Acked-by: Liam Girdwood --- arch/arm/mach-mx3/clock-imx31.c | 4 ++-- arch/arm/mach-mx3/clock-imx35.c | 4 ++-- arch/arm/mach-mx3/devices.c | 4 ++-- arch/arm/plat-mxc/audmux-v2.c | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-mx3/clock-imx31.c b/arch/arm/mach-mx3/clock-imx31.c index 9b52a67..9a9eb6d 100644 --- a/arch/arm/mach-mx3/clock-imx31.c +++ b/arch/arm/mach-mx3/clock-imx31.c @@ -558,8 +558,8 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk) _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk) _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk) - _REGISTER_CLOCK("imx-ssi-dai.0", NULL, ssi1_clk) - _REGISTER_CLOCK("imx-ssi-dai.1", NULL, ssi2_clk) + _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) + _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) _REGISTER_CLOCK(NULL, "firi", firi_clk) _REGISTER_CLOCK(NULL, "ata", ata_clk) _REGISTER_CLOCK(NULL, "rtic", rtic_clk) diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c index f29c3e9..d3af0fd 100644 --- a/arch/arm/mach-mx3/clock-imx35.c +++ b/arch/arm/mach-mx3/clock-imx35.c @@ -464,8 +464,8 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK(NULL, "sdma", sdma_clk) _REGISTER_CLOCK(NULL, "spba", spba_clk) _REGISTER_CLOCK(NULL, "spdif", spdif_clk) - _REGISTER_CLOCK("imx-ssi-dai.0", NULL, ssi1_clk) - _REGISTER_CLOCK("imx-ssi-dai.1", NULL, ssi2_clk) + _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) + _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c index 90eccba..a4fd1a2 100644 --- a/arch/arm/mach-mx3/devices.c +++ b/arch/arm/mach-mx3/devices.c @@ -327,14 +327,14 @@ static struct resource imx_ssi_resources1[] = { }; struct platform_device imx_ssi_device0 = { - .name = "imx-ssi-dai", + .name = "imx-ssi", .id = 0, .num_resources = ARRAY_SIZE(imx_ssi_resources0), .resource = imx_ssi_resources0, }; struct platform_device imx_ssi_device1 = { - .name = "imx-ssi-dai", + .name = "imx-ssi", .id = 1, .num_resources = ARRAY_SIZE(imx_ssi_resources1), .resource = imx_ssi_resources1, diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c index 910374d..f9e7cdb 100644 --- a/arch/arm/plat-mxc/audmux-v2.c +++ b/arch/arm/plat-mxc/audmux-v2.c @@ -45,9 +45,9 @@ static const char *audmux_port_string(int port) { switch (port) { case MX31_AUDMUX_PORT1_SSI0: - return "imx-ssi-dai.0"; + return "imx-ssi.0"; case MX31_AUDMUX_PORT2_SSI1: - return "imx-ssi-dai.1"; + return "imx-ssi.1"; case MX31_AUDMUX_PORT3_SSI_PINS_3: return "SSI3"; case MX31_AUDMUX_PORT4_SSI_PINS_4: -- cgit v1.1 From 5924ad0d86fbc05bfb0c90afa15e20ccb7155549 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 1 Oct 2010 23:49:56 +0900 Subject: sh: Update SH-X3 subtype for clkdev lookups. Rewrite the SH-X3 proto CPU clock framework for clkdev. Signed-off-by: Paul Mundt --- arch/sh/Kconfig | 2 +- arch/sh/include/cpu-sh4/cpu/freq.h | 4 +- arch/sh/kernel/cpu/sh4a/clock-shx3.c | 225 ++++++++++++++++++++++------------- 3 files changed, 146 insertions(+), 85 deletions(-) (limited to 'arch') diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 2284215..e46b61d 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -570,7 +570,7 @@ config SH_CLK_CPG config SH_CLK_CPG_LEGACY depends on SH_CLK_CPG def_bool y if !CPU_SUBTYPE_SH7785 && !ARCH_SHMOBILE && \ - !CPU_SUBTYPE_SH7786 && !CPU_SUBTYPE_SH7757 + !CPU_SHX3 && !CPU_SUBTYPE_SH7757 config SH_CLK_MD int "CPU Mode Pin Setting" diff --git a/arch/sh/include/cpu-sh4/cpu/freq.h b/arch/sh/include/cpu-sh4/cpu/freq.h index e1e9096..cffd25e 100644 --- a/arch/sh/include/cpu-sh4/cpu/freq.h +++ b/arch/sh/include/cpu-sh4/cpu/freq.h @@ -56,7 +56,9 @@ #define FRQCR1 0xffc40004 #define FRQMR1 0xffc40014 #elif defined(CONFIG_CPU_SUBTYPE_SHX3) -#define FRQCR 0xffc00014 +#define FRQCR0 0xffc00000 +#define FRQCR1 0xffc00004 +#define FRQMR1 0xffc00014 #else #define FRQCR 0xffc00000 #define FRQCR_PSTBY 0x0200 diff --git a/arch/sh/kernel/cpu/sh4a/clock-shx3.c b/arch/sh/kernel/cpu/sh4a/clock-shx3.c index 236a628..4f70df6 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-shx3.c +++ b/arch/sh/kernel/cpu/sh4a/clock-shx3.c @@ -5,7 +5,7 @@ * * Copyright (C) 2006-2007 Renesas Technology Corp. * Copyright (C) 2006-2007 Renesas Solutions Corp. - * Copyright (C) 2006-2007 Paul Mundt + * Copyright (C) 2006-2010 Paul Mundt * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -18,120 +18,179 @@ #include #include -static int ifc_divisors[] = { 1, 2, 4 ,6 }; -static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 18, 24, 32, 36, 48 }; -static int pfc_divisors[] = { 1, 1, 1, 1, 1, 1, 1, 18, 24, 32, 36, 48 }; -static int cfc_divisors[] = { 1, 1, 4, 6 }; - -#define IFC_POS 28 -#define IFC_MSK 0x0003 -#define BFC_MSK 0x000f -#define PFC_MSK 0x000f -#define CFC_MSK 0x0003 -#define BFC_POS 16 -#define PFC_POS 0 -#define CFC_POS 20 - -static void master_clk_init(struct clk *clk) -{ - clk->rate *= pfc_divisors[(__raw_readl(FRQCR) >> PFC_POS) & PFC_MSK]; -} - -static struct clk_ops shx3_master_clk_ops = { - .init = master_clk_init, +/* + * Default rate for the root input clock, reset this with clk_set_rate() + * from the platform code. + */ +static struct clk extal_clk = { + .rate = 16666666, }; -static unsigned long module_clk_recalc(struct clk *clk) +static unsigned long pll_recalc(struct clk *clk) { - int idx = ((__raw_readl(FRQCR) >> PFC_POS) & PFC_MSK); - return clk->parent->rate / pfc_divisors[idx]; + /* PLL1 has a fixed x72 multiplier. */ + return clk->parent->rate * 72; } -static struct clk_ops shx3_module_clk_ops = { - .recalc = module_clk_recalc, +static struct clk_ops pll_clk_ops = { + .recalc = pll_recalc, }; -static unsigned long bus_clk_recalc(struct clk *clk) -{ - int idx = ((__raw_readl(FRQCR) >> BFC_POS) & BFC_MSK); - return clk->parent->rate / bfc_divisors[idx]; -} +static struct clk pll_clk = { + .ops = &pll_clk_ops, + .parent = &extal_clk, + .flags = CLK_ENABLE_ON_INIT, +}; -static struct clk_ops shx3_bus_clk_ops = { - .recalc = bus_clk_recalc, +static struct clk *clks[] = { + &extal_clk, + &pll_clk, }; -static unsigned long cpu_clk_recalc(struct clk *clk) -{ - int idx = ((__raw_readl(FRQCR) >> IFC_POS) & IFC_MSK); - return clk->parent->rate / ifc_divisors[idx]; -} +static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18, + 24, 32, 36, 48 }; -static struct clk_ops shx3_cpu_clk_ops = { - .recalc = cpu_clk_recalc, +static struct clk_div_mult_table div4_div_mult_table = { + .divisors = div2, + .nr_divisors = ARRAY_SIZE(div2), }; -static struct clk_ops *shx3_clk_ops[] = { - &shx3_master_clk_ops, - &shx3_module_clk_ops, - &shx3_bus_clk_ops, - &shx3_cpu_clk_ops, +static struct clk_div4_table div4_table = { + .div_mult_table = &div4_div_mult_table, }; -void __init arch_init_clk_ops(struct clk_ops **ops, int idx) -{ - if (idx < ARRAY_SIZE(shx3_clk_ops)) - *ops = shx3_clk_ops[idx]; -} +enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_SHA, DIV4_P, DIV4_NR }; -static unsigned long shyway_clk_recalc(struct clk *clk) -{ - int idx = ((__raw_readl(FRQCR) >> CFC_POS) & CFC_MSK); - return clk->parent->rate / cfc_divisors[idx]; -} +#define DIV4(_bit, _mask, _flags) \ + SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags) -static struct clk_ops shx3_shyway_clk_ops = { - .recalc = shyway_clk_recalc, +struct clk div4_clks[DIV4_NR] = { + [DIV4_P] = DIV4(0, 0x0f80, 0), + [DIV4_SHA] = DIV4(4, 0x0ff0, 0), + [DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT), + [DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT), + [DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT), + [DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT), }; -static struct clk shx3_shyway_clk = { - .flags = CLK_ENABLE_ON_INIT, - .ops = &shx3_shyway_clk_ops, -}; - -/* - * Additional SHx3-specific on-chip clocks that aren't already part of the - * clock framework - */ -static struct clk *shx3_onchip_clocks[] = { - &shx3_shyway_clk, +#define MSTPCR0 0xffc00030 +#define MSTPCR1 0xffc00034 + +enum { MSTP027, MSTP026, MSTP025, MSTP024, + MSTP009, MSTP008, MSTP003, MSTP002, + MSTP001, MSTP000, MSTP119, MSTP105, + MSTP104, MSTP_NR }; + +static struct clk mstp_clks[MSTP_NR] = { + /* MSTPCR0 */ + [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0), + [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), + [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), + [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), + [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0), + [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0), + [MSTP003] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 3, 0), + [MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0), + [MSTP001] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 1, 0), + [MSTP000] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 0, 0), + + /* MSTPCR1 */ + [MSTP119] = SH_CLK_MSTP32(NULL, MSTPCR1, 19, 0), + [MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0), + [MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0), }; #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } static struct clk_lookup lookups[] = { /* main clocks */ - CLKDEV_CON_ID("shyway_clk", &shx3_shyway_clk), + CLKDEV_CON_ID("extal", &extal_clk), + CLKDEV_CON_ID("pll_clk", &pll_clk), + + /* DIV4 clocks */ + CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), + CLKDEV_CON_ID("shywaya_clk", &div4_clks[DIV4_SHA]), + CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]), + CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), + CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), + CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), + + /* MSTP32 clocks */ + { + /* SCIF3 */ + .dev_id = "sh-sci.3", + .con_id = "sci_fck", + .clk = &mstp_clks[MSTP027], + }, { + /* SCIF2 */ + .dev_id = "sh-sci.2", + .con_id = "sci_fck", + .clk = &mstp_clks[MSTP026], + }, { + /* SCIF1 */ + .dev_id = "sh-sci.1", + .con_id = "sci_fck", + .clk = &mstp_clks[MSTP025], + }, { + /* SCIF0 */ + .dev_id = "sh-sci.0", + .con_id = "sci_fck", + .clk = &mstp_clks[MSTP024], + }, + CLKDEV_CON_ID("h8ex_fck", &mstp_clks[MSTP003]), + CLKDEV_CON_ID("csm_fck", &mstp_clks[MSTP002]), + CLKDEV_CON_ID("fe1_fck", &mstp_clks[MSTP001]), + CLKDEV_CON_ID("fe0_fck", &mstp_clks[MSTP000]), + { + /* TMU0 */ + .dev_id = "sh_tmu.0", + .con_id = "tmu_fck", + .clk = &mstp_clks[MSTP008], + }, { + /* TMU1 */ + .dev_id = "sh_tmu.1", + .con_id = "tmu_fck", + .clk = &mstp_clks[MSTP008], + }, { + /* TMU2 */ + .dev_id = "sh_tmu.2", + .con_id = "tmu_fck", + .clk = &mstp_clks[MSTP008], + }, { + /* TMU3 */ + .dev_id = "sh_tmu.3", + .con_id = "tmu_fck", + .clk = &mstp_clks[MSTP009], + }, { + /* TMU4 */ + .dev_id = "sh_tmu.4", + .con_id = "tmu_fck", + .clk = &mstp_clks[MSTP009], + }, { + /* TMU5 */ + .dev_id = "sh_tmu.5", + .con_id = "tmu_fck", + .clk = &mstp_clks[MSTP009], + }, + CLKDEV_CON_ID("hudi_fck", &mstp_clks[MSTP119]), + CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]), + CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]), }; int __init arch_clk_init(void) { - struct clk *clk; int i, ret = 0; - cpg_clk_init(); - - clk = clk_get(NULL, "master_clk"); - for (i = 0; i < ARRAY_SIZE(shx3_onchip_clocks); i++) { - struct clk *clkp = shx3_onchip_clocks[i]; - - clkp->parent = clk; - ret |= clk_register(clkp); - } - - clk_put(clk); + for (i = 0; i < ARRAY_SIZE(clks); i++) + ret |= clk_register(clks[i]); + for (i = 0; i < ARRAY_SIZE(lookups); i++) + clkdev_add(&lookups[i]); - clkdev_add_table(lookups, ARRAY_SIZE(lookups)); + if (!ret) + ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks), + &div4_table); + if (!ret) + ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR); return ret; } -- cgit v1.1 From e15f6870a2f2a29abcdb910b80f9629bcf7f5566 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Sat, 2 Oct 2010 00:43:43 +0900 Subject: sh: Support userimask for all SH-X3 interrupt controllers. This shuffles some of the shared bits out of the 7786 code and in to a shared SH-X3 support file. Presently just for userimask, but also a good place for the IRQ balancing wrappers. Signed-off-by: Paul Mundt --- arch/sh/kernel/cpu/sh4a/Makefile | 4 ++-- arch/sh/kernel/cpu/sh4a/intc-shx3.c | 34 ++++++++++++++++++++++++++++++++++ arch/sh/kernel/cpu/sh4a/setup-sh7786.c | 16 ---------------- 3 files changed, 36 insertions(+), 18 deletions(-) create mode 100644 arch/sh/kernel/cpu/sh4a/intc-shx3.c (limited to 'arch') diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile index b144e8a..f2d6542 100644 --- a/arch/sh/kernel/cpu/sh4a/Makefile +++ b/arch/sh/kernel/cpu/sh4a/Makefile @@ -8,13 +8,13 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7763) += setup-sh7763.o obj-$(CONFIG_CPU_SUBTYPE_SH7770) += setup-sh7770.o obj-$(CONFIG_CPU_SUBTYPE_SH7780) += setup-sh7780.o obj-$(CONFIG_CPU_SUBTYPE_SH7785) += setup-sh7785.o -obj-$(CONFIG_CPU_SUBTYPE_SH7786) += setup-sh7786.o +obj-$(CONFIG_CPU_SUBTYPE_SH7786) += setup-sh7786.o intc-shx3.o obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o obj-$(CONFIG_CPU_SUBTYPE_SH7723) += setup-sh7723.o obj-$(CONFIG_CPU_SUBTYPE_SH7724) += setup-sh7724.o obj-$(CONFIG_CPU_SUBTYPE_SH7366) += setup-sh7366.o -obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o +obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o intc-shx3.o # SMP setup smp-$(CONFIG_CPU_SHX3) := smp-shx3.o diff --git a/arch/sh/kernel/cpu/sh4a/intc-shx3.c b/arch/sh/kernel/cpu/sh4a/intc-shx3.c new file mode 100644 index 0000000..78c9714 --- /dev/null +++ b/arch/sh/kernel/cpu/sh4a/intc-shx3.c @@ -0,0 +1,34 @@ +/* + * Shared support for SH-X3 interrupt controllers. + * + * Copyright (C) 2009 - 2010 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include + +#define INTACK 0xfe4100b8 +#define INTACKCLR 0xfe4100bc +#define INTC_USERIMASK 0xfe411000 + +#ifdef CONFIG_INTC_BALANCING +unsigned int irq_lookup(unsigned int irq) +{ + return __raw_readl(INTACK) & 1 ? irq : NO_IRQ_IGNORE; +} + +void irq_finish(unsigned int irq) +{ + __raw_writel(irq2evt(irq), INTACKCLR); +} +#endif + +static int __init shx3_irq_setup(void) +{ + return register_intc_userimask(INTC_USERIMASK); +} +arch_initcall(shx3_irq_setup); diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c index 8797723..bbc0a97 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c @@ -756,8 +756,6 @@ static struct intc_vect vectors[] __initdata = { #define INTDISTCR0 0xfe4100b0 #define INTDISTCR1 0xfe4100b4 -#define INTACK 0xfe4100b8 -#define INTACKCLR 0xfe4100bc #define INT2DISTCR0 0xfe410900 #define INT2DISTCR1 0xfe410904 #define INT2DISTCR2 0xfe410908 @@ -920,19 +918,6 @@ static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567, #define INTC_INTMSK2 INTMSK2 #define INTC_INTMSKCLR1 CnINTMSKCLR1 #define INTC_INTMSKCLR2 INTMSKCLR2 -#define INTC_USERIMASK 0xfe411000 - -#ifdef CONFIG_INTC_BALANCING -unsigned int irq_lookup(unsigned int irq) -{ - return __raw_readl(INTACK) & 1 ? irq : NO_IRQ_IGNORE; -} - -void irq_finish(unsigned int irq) -{ - __raw_writel(irq2evt(irq), INTACKCLR); -} -#endif void __init plat_irq_setup(void) { @@ -947,7 +932,6 @@ void __init plat_irq_setup(void) __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); register_intc_controller(&intc_desc); - register_intc_userimask(INTC_USERIMASK); } void __init plat_irq_setup_pins(int mode) -- cgit v1.1 From f9d885c3e59e50863565bddd2672656b57b15035 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Sat, 2 Oct 2010 01:04:30 +0900 Subject: sh: Support IRQ balancing for SH-X3 proto cores, too. This adds in hardware IRQ auto-distribution support for SH-X3 proto CPUs, following the SH7786 support. Signed-off-by: Paul Mundt --- arch/sh/kernel/cpu/sh4a/setup-shx3.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c index 9158bc5..04a4874 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-shx3.c +++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c @@ -1,7 +1,7 @@ /* * SH-X3 Prototype Setup * - * Copyright (C) 2007 - 2009 Paul Mundt + * Copyright (C) 2007 - 2010 Paul Mundt * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -354,6 +354,10 @@ static struct intc_group groups[] __initdata = { DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11), }; +#define INT2DISTCR0 0xfe4108a0 +#define INT2DISTCR1 0xfe4108a4 +#define INT2DISTCR2 0xfe4108a8 + static struct intc_mask_reg mask_registers[] __initdata = { { 0xfe410030, 0xfe410050, 32, /* CnINTMSK0 / CnINTMSKCLR0 */ { IRQ0, IRQ1, IRQ2, IRQ3 } }, @@ -363,20 +367,23 @@ static struct intc_mask_reg mask_registers[] __initdata = { { FE1, FE0, 0, ATAPI, VCORE0, VIN1, VIN0, IIC, DU, GPIO3, GPIO2, GPIO1, GPIO0, PAM, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* HUDI bits ignored */ - 0, TMU5, TMU4, TMU3, TMU2, TMU1, TMU0, 0, } }, + 0, TMU5, TMU4, TMU3, TMU2, TMU1, TMU0, 0, }, + INTC_SMP_BALANCING(INT2DISTCR0) }, { 0xfe410830, 0xfe410860, 32, /* CnINT2MSK1 / CnINT2MSKCLR1 */ { 0, 0, 0, 0, DTU3, DTU2, DTU1, DTU0, /* IRM bits ignored */ PCII9, PCII8, PCII7, PCII6, PCII5, PCII4, PCII3, PCII2, PCII1, PCII0, DMAC1_DMAE, DMAC1_DMINT11, DMAC1_DMINT10, DMAC1_DMINT9, DMAC1_DMINT8, DMAC1_DMINT7, DMAC1_DMINT6, DMAC0_DMAE, DMAC0_DMINT5, DMAC0_DMINT4, - DMAC0_DMINT3, DMAC0_DMINT2, DMAC0_DMINT1, DMAC0_DMINT0 } }, + DMAC0_DMINT3, DMAC0_DMINT2, DMAC0_DMINT1, DMAC0_DMINT0 }, + INTC_SMP_BALANCING(INT2DISTCR1) }, { 0xfe410840, 0xfe410870, 32, /* CnINT2MSK2 / CnINT2MSKCLR2 */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, SCIF3_TXI, SCIF3_BRI, SCIF3_RXI, SCIF3_ERI, SCIF2_TXI, SCIF2_BRI, SCIF2_RXI, SCIF2_ERI, SCIF1_TXI, SCIF1_BRI, SCIF1_RXI, SCIF1_ERI, - SCIF0_TXI, SCIF0_BRI, SCIF0_RXI, SCIF0_ERI } }, + SCIF0_TXI, SCIF0_BRI, SCIF0_RXI, SCIF0_ERI }, + INTC_SMP_BALANCING(INT2DISTCR2) }, }; static struct intc_prio_reg prio_registers[] __initdata = { -- cgit v1.1 From 65707fb3794e9cf75665f9ef91cfb07c50d3ffa5 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Fri, 1 Oct 2010 08:35:47 -0700 Subject: OMAP3: CPUidle: remove redundant setting of PER next power state When checking how to program the next powerstate for the PER powerdomain, the next state of PER powerdomain was written twice. Remove the duplicate write. Reported-by: Santosh Shilimkar Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/cpuidle34xx.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c index 8ea012e..703b5ec 100644 --- a/arch/arm/mach-omap2/cpuidle34xx.c +++ b/arch/arm/mach-omap2/cpuidle34xx.c @@ -272,10 +272,8 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev, */ per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd); if ((per_next_state == PWRDM_POWER_OFF) && - (core_next_state > PWRDM_POWER_RET)) { + (core_next_state > PWRDM_POWER_RET)) per_next_state = PWRDM_POWER_RET; - pwrdm_set_next_pwrst(per_pd, per_next_state); - } /* Are we changing PER target state? */ if (per_next_state != per_saved_state) -- cgit v1.1 From ebfa88cfa1f00022c500e35db63b5f6c977c95c0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Lo=C3=AFc=20Minier?= Date: Mon, 27 Sep 2010 23:04:20 +0200 Subject: OMAP: PM: Fix build when CONFIG_PM_DEBUG isn't set MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since 6cdee91257bee23a46dc869ca62469b67cba2c7e the references to enable_off_mode and sleep_while_idle can't be resolved when CONFIG_PM_DEBUG isn't set: arch/arm/mach-omap2/built-in.o: In function `omap_uart_restore_context': arch/arm/mach-omap2/serial.c:253: undefined reference to `enable_off_mode' arch/arm/mach-omap2/built-in.o: In function `omap3_can_sleep': arch/arm/mach-omap2/pm34xx.c:479: undefined reference to `sleep_while_idle' Simply #define these in pm.h just like omap2_pm_debug. Signed-off-by: Loïc Minier [khilman: moved down into existing #ifdef section] Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/pm.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index 77770a1..0d75bfd 100644 --- a/arch/arm/mach-omap2/pm.h +++ b/arch/arm/mach-omap2/pm.h @@ -13,9 +13,6 @@ #include -extern u32 enable_off_mode; -extern u32 sleep_while_idle; - extern void *omap3_secure_ram_storage; extern void omap3_pm_off_mode_enable(int); extern void omap_sram_idle(void); @@ -50,10 +47,14 @@ extern struct omap_dm_timer *gptimer_wakeup; extern void omap2_pm_dump(int mode, int resume, unsigned int us); extern void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds); extern int omap2_pm_debug; +extern u32 enable_off_mode; +extern u32 sleep_while_idle; #else #define omap2_pm_dump(mode, resume, us) do {} while (0); #define omap2_pm_wakeup_on_timer(seconds, milliseconds) do {} while (0); #define omap2_pm_debug 0 +#define enable_off_mode 0 +#define sleep_while_idle 0 #endif #if defined(CONFIG_CPU_IDLE) -- cgit v1.1 From 5a3b2f7a5a79082dd3a5f2294cbd85fc3b173d98 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 1 Oct 2010 16:35:24 -0700 Subject: omap: Fix omap_mux_init_signal not to trash muxname Otherwise the muxname passed to the function will get truncated. Based on an earlier patch by rockefeller.lin@innocomm.com. Reported-by: rockefeller.lin@innocomm.com Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/mux.c | 13 +++++++------ arch/arm/mach-omap2/mux.h | 2 +- 2 files changed, 8 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index 6c2f8f0..e33740c 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c @@ -127,17 +127,16 @@ int __init omap_mux_init_gpio(int gpio, int val) return 0; } -int __init omap_mux_init_signal(char *muxname, int val) +int __init omap_mux_init_signal(const char *muxname, int val) { struct omap_mux_entry *e; - char *m0_name = NULL, *mode_name = NULL; - int found = 0; + const char *mode_name; + int found = 0, mode0_len = 0; mode_name = strchr(muxname, '.'); if (mode_name) { - *mode_name = '\0'; + mode0_len = strlen(muxname) - strlen(mode_name); mode_name++; - m0_name = muxname; } else { mode_name = muxname; } @@ -147,9 +146,11 @@ int __init omap_mux_init_signal(char *muxname, int val) char *m0_entry = m->muxnames[0]; int i; - if (m0_name && strcmp(m0_name, m0_entry)) + /* First check for full name in mode0.muxmode format */ + if (mode0_len && strncmp(muxname, m0_entry, mode0_len)) continue; + /* Then check for muxmode only */ for (i = 0; i < OMAP_MUX_NR_MODES; i++) { char *mode_cur = m->muxnames[i]; diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h index a8e040c..350c04f 100644 --- a/arch/arm/mach-omap2/mux.h +++ b/arch/arm/mach-omap2/mux.h @@ -120,7 +120,7 @@ int omap_mux_init_gpio(int gpio, int val); * @muxname: Mux name in mode0_name.signal_name format * @val: Options for the mux register value */ -int omap_mux_init_signal(char *muxname, int val); +int omap_mux_init_signal(const char *muxname, int val); #else -- cgit v1.1 From 76abab213587bfc3b850f36c0a674116d161148d Mon Sep 17 00:00:00 2001 From: Sanjeev Premi Date: Fri, 1 Oct 2010 16:35:24 -0700 Subject: omap2/3: Update revision identification The existing definitions for cpu revision used upper nibble in the bits[15:08]. With OMAP3630, definitions use lower nibble. This patch unifies the definitions to start at lower nibble. Signed-off-by: Sanjeev Premi Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/id.c | 72 +++++++++++++++++++++++------------ arch/arm/plat-omap/include/plat/cpu.h | 36 +++++++++--------- 2 files changed, 66 insertions(+), 42 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 0412233..04a2fa2 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -385,30 +385,54 @@ static void __init omap3_cpuinfo(void) strcpy(cpu_name, "OMAP3503"); } - switch (rev) { - case OMAP_REVBITS_00: - strcpy(cpu_rev, "1.0"); - break; - case OMAP_REVBITS_01: - strcpy(cpu_rev, "1.1"); - break; - case OMAP_REVBITS_02: - strcpy(cpu_rev, "1.2"); - break; - case OMAP_REVBITS_10: - strcpy(cpu_rev, "2.0"); - break; - case OMAP_REVBITS_20: - strcpy(cpu_rev, "2.1"); - break; - case OMAP_REVBITS_30: - strcpy(cpu_rev, "3.0"); - break; - case OMAP_REVBITS_40: - /* FALLTHROUGH */ - default: - /* Use the latest known revision as default */ - strcpy(cpu_rev, "3.1"); + if (cpu_is_omap3630()) { + switch (rev) { + case OMAP_REVBITS_00: + strcpy(cpu_rev, "1.0"); + break; + case OMAP_REVBITS_01: + strcpy(cpu_rev, "1.1"); + break; + case OMAP_REVBITS_02: + /* FALLTHROUGH */ + default: + /* Use the latest known revision as default */ + strcpy(cpu_rev, "1.2"); + } + } else if (cpu_is_omap3505() || cpu_is_omap3517()) { + switch (rev) { + case OMAP_REVBITS_00: + strcpy(cpu_rev, "1.0"); + break; + case OMAP_REVBITS_01: + /* FALLTHROUGH */ + default: + /* Use the latest known revision as default */ + strcpy(cpu_rev, "1.1"); + } + } else { + switch (rev) { + case OMAP_REVBITS_00: + strcpy(cpu_rev, "1.0"); + break; + case OMAP_REVBITS_01: + strcpy(cpu_rev, "2.0"); + break; + case OMAP_REVBITS_02: + strcpy(cpu_rev, "2.1"); + break; + case OMAP_REVBITS_03: + strcpy(cpu_rev, "3.0"); + break; + case OMAP_REVBITS_04: + strcpy(cpu_rev, "3.1"); + break; + case OMAP_REVBITS_05: + /* FALLTHROUGH */ + default: + /* Use the latest known revision as default */ + strcpy(cpu_rev, "3.1.2"); + } } /* Print verbose information */ diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h index 9b38e4b..3fd8b40 100644 --- a/arch/arm/plat-omap/include/plat/cpu.h +++ b/arch/arm/plat-omap/include/plat/cpu.h @@ -68,10 +68,9 @@ unsigned int omap_rev(void); #define OMAP_REVBITS_00 0x00 #define OMAP_REVBITS_01 0x01 #define OMAP_REVBITS_02 0x02 -#define OMAP_REVBITS_10 0x10 -#define OMAP_REVBITS_20 0x20 -#define OMAP_REVBITS_30 0x30 -#define OMAP_REVBITS_40 0x40 +#define OMAP_REVBITS_03 0x03 +#define OMAP_REVBITS_04 0x04 +#define OMAP_REVBITS_05 0x05 /* * Get the CPU revision for OMAP devices @@ -363,23 +362,24 @@ IS_OMAP_TYPE(3517, 0x3517) /* Various silicon revisions for omap2 */ #define OMAP242X_CLASS 0x24200024 -#define OMAP2420_REV_ES1_0 0x24200024 -#define OMAP2420_REV_ES2_0 0x24201024 +#define OMAP2420_REV_ES1_0 OMAP242X_CLASS +#define OMAP2420_REV_ES2_0 (OMAP242X_CLASS | (OMAP_REVBITS_01 << 8)) #define OMAP243X_CLASS 0x24300024 -#define OMAP2430_REV_ES1_0 0x24300024 +#define OMAP2430_REV_ES1_0 OMAP243X_CLASS #define OMAP343X_CLASS 0x34300034 -#define OMAP3430_REV_ES1_0 0x34300034 -#define OMAP3430_REV_ES2_0 0x34301034 -#define OMAP3430_REV_ES2_1 0x34302034 -#define OMAP3430_REV_ES3_0 0x34303034 -#define OMAP3430_REV_ES3_1 0x34304034 -#define OMAP3430_REV_ES3_1_2 0x34305034 - -#define OMAP3630_REV_ES1_0 0x36300034 -#define OMAP3630_REV_ES1_1 0x36300134 -#define OMAP3630_REV_ES1_2 0x36300234 +#define OMAP3430_REV_ES1_0 OMAP343X_CLASS +#define OMAP3430_REV_ES2_0 (OMAP343X_CLASS | (OMAP_REVBITS_01 << 8)) +#define OMAP3430_REV_ES2_1 (OMAP343X_CLASS | (OMAP_REVBITS_02 << 8)) +#define OMAP3430_REV_ES3_0 (OMAP343X_CLASS | (OMAP_REVBITS_03 << 8)) +#define OMAP3430_REV_ES3_1 (OMAP343X_CLASS | (OMAP_REVBITS_04 << 8)) +#define OMAP3430_REV_ES3_1_2 (OMAP343X_CLASS | (OMAP_REVBITS_05 << 8)) + +#define OMAP363X_CLASS 0x36300034 +#define OMAP3630_REV_ES1_0 OMAP363X_CLASS +#define OMAP3630_REV_ES1_1 (OMAP363X_CLASS | (OMAP_REVBITS_01 << 8)) +#define OMAP3630_REV_ES1_2 (OMAP363X_CLASS | (OMAP_REVBITS_02 << 8)) #define OMAP35XX_CLASS 0x35000034 #define OMAP3503_REV(v) (OMAP35XX_CLASS | (0x3503 << 16) | (v << 8)) @@ -390,7 +390,7 @@ IS_OMAP_TYPE(3517, 0x3517) #define OMAP3517_REV(v) (OMAP35XX_CLASS | (0x3517 << 16) | (v << 8)) #define OMAP443X_CLASS 0x44300044 -#define OMAP4430_REV_ES1_0 0x44300044 +#define OMAP4430_REV_ES1_0 OMAP443X_CLASS #define OMAP4430_REV_ES2_0 0x44301044 /* -- cgit v1.1 From 690a4a39b2429a4e397cd79e1dd16b6a5ca4111e Mon Sep 17 00:00:00 2001 From: Grazvydas Ignotas Date: Fri, 1 Oct 2010 16:35:25 -0700 Subject: omap: pandora: add fixed regulator for wlan Instead of enabling the wifi module explicitly using GPIO, add a fixed regulator and hook it to MMC host card power control. This way it will only be enabled when SDIO subsystem wants to talk to it, saving power (as done by Zoom boards). Signed-off-by: Grazvydas Ignotas Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-omap3pandora.c | 43 ++++++++++++++++++++++++-------- 1 file changed, 32 insertions(+), 11 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c index 2d2e6fc..7c222ba 100644 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ b/arch/arm/mach-omap2/board-omap3pandora.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #include @@ -345,6 +346,9 @@ static struct regulator_consumer_supply pandora_vmmc1_supply = static struct regulator_consumer_supply pandora_vmmc2_supply = REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"); +static struct regulator_consumer_supply pandora_vmmc3_supply = + REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.2"); + static struct regulator_consumer_supply pandora_vdda_dac_supply = REGULATOR_SUPPLY("vdda_dac", "omapdss"); @@ -489,6 +493,33 @@ static struct regulator_init_data pandora_vsim = { .consumer_supplies = &pandora_adac_supply, }; +/* Fixed regulator internal to Wifi module */ +static struct regulator_init_data pandora_vmmc3 = { + .constraints = { + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &pandora_vmmc3_supply, +}; + +static struct fixed_voltage_config pandora_vwlan = { + .supply_name = "vwlan", + .microvolts = 1800000, /* 1.8V */ + .gpio = PANDORA_WIFI_NRESET_GPIO, + .startup_delay = 50000, /* 50ms */ + .enable_high = 1, + .enabled_at_boot = 0, + .init_data = &pandora_vmmc3, +}; + +static struct platform_device pandora_vwlan_device = { + .name = "reg-fixed-voltage", + .id = 1, + .dev = { + .platform_data = &pandora_vwlan, + }, +}; + static struct twl4030_usb_data omap3pandora_usb_data = { .usb_mode = T2_USB_MODE_ULPI, }; @@ -645,19 +676,8 @@ static void pandora_wl1251_init(void) if (pandora_wl1251_pdata.irq < 0) goto fail_irq; - ret = gpio_request(PANDORA_WIFI_NRESET_GPIO, "wl1251 nreset"); - if (ret < 0) - goto fail_irq; - - /* start powered so that it probes with MMC subsystem */ - ret = gpio_direction_output(PANDORA_WIFI_NRESET_GPIO, 1); - if (ret < 0) - goto fail_nreset; - return; -fail_nreset: - gpio_free(PANDORA_WIFI_NRESET_GPIO); fail_irq: gpio_free(PANDORA_WIFI_IRQ_GPIO); fail: @@ -669,6 +689,7 @@ static struct platform_device *omap3pandora_devices[] __initdata = { &pandora_keys_gpio, &pandora_dss_device, &pandora_wl1251_data, + &pandora_vwlan_device, }; static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { -- cgit v1.1 From e13bb34bd9bbc01dcab9ed1b8adaa6a199ce059c Mon Sep 17 00:00:00 2001 From: Grazvydas Ignotas Date: Fri, 1 Oct 2010 16:35:25 -0700 Subject: omap: pandora: enable twl4030 charger Add platform data to make use of newly added charging driver. Signed-off-by: Grazvydas Ignotas Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-omap3pandora.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c index 7c222ba..7192635 100644 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ b/arch/arm/mach-omap2/board-omap3pandora.c @@ -533,6 +533,8 @@ static struct twl4030_codec_data omap3pandora_codec_data = { .audio = &omap3pandora_audio_data, }; +static struct twl4030_bci_platform_data pandora_bci_data; + static struct twl4030_platform_data omap3pandora_twldata = { .irq_base = TWL4030_IRQ_BASE, .irq_end = TWL4030_IRQ_END, @@ -548,6 +550,7 @@ static struct twl4030_platform_data omap3pandora_twldata = { .vaux4 = &pandora_vaux4, .vsim = &pandora_vsim, .keypad = &pandora_kp_data, + .bci = &pandora_bci_data, }; static struct i2c_board_info __initdata omap3pandora_i2c_boardinfo[] = { -- cgit v1.1 From 07ad64b60c4d1f2bdbefa5db29ccb235596bc670 Mon Sep 17 00:00:00 2001 From: Madhusudhan Chikkature Date: Fri, 1 Oct 2010 16:35:25 -0700 Subject: OMAP4 ES2: HSMMC soft reset change The omap4 es2 hsmmc has a updated soft reset logic.After the reset is issued monitor a 0->1 transition first. The reset of CMD or DATA lines is complete only after a 0->1->0 transition of SRC or SRD bits. Signed-off-by: Madhusudhan Chikkature Tested-by: Anand Gadiyar Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/hsmmc.c | 3 +++ arch/arm/plat-omap/include/plat/mmc.h | 1 + 2 files changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c index eb92b81..df1311d 100644 --- a/arch/arm/mach-omap2/hsmmc.c +++ b/arch/arm/mach-omap2/hsmmc.c @@ -303,6 +303,9 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) else mmc->slots[0].features |= HSMMC_HAS_PBIAS; + if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0)) + mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET; + switch (c->mmc) { case 1: if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h index 4f819fc..2c4629a8 100644 --- a/arch/arm/plat-omap/include/plat/mmc.h +++ b/arch/arm/plat-omap/include/plat/mmc.h @@ -103,6 +103,7 @@ struct omap_mmc_platform_data { /* we can put the features above into this variable */ #define HSMMC_HAS_PBIAS (1 << 0) +#define HSMMC_HAS_UPDATED_RESET (1 << 1) unsigned features; int switch_pin; /* gpio (card detect) */ -- cgit v1.1 From 531c21ba1a298422ace28efbcdf94d5579a1b702 Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Fri, 1 Oct 2010 16:35:26 -0700 Subject: omap4 hsmmc: Fix the init if CONFIG_MMC_OMAP_HS is not set Avoid possible crash if CONFIG_MMC_OMAP_HS is not set Cc: Andrew Morton Cc: Madhusudhan Chikkature Cc: Adrian Hunter Signed-off-by: Benoit Cousson Signed-off-by: Kishore Kadiyala Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-4430sdp.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index 1bed1e6..cdb9373 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -275,8 +275,14 @@ static int omap4_twl6030_hsmmc_late_init(struct device *dev) static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev) { - struct omap_mmc_platform_data *pdata = dev->platform_data; + struct omap_mmc_platform_data *pdata; + /* dev can be null if CONFIG_MMC_OMAP_HS is not set */ + if (!dev) { + pr_err("Failed %s\n", __func__); + return; + } + pdata = dev->platform_data; pdata->init = omap4_twl6030_hsmmc_late_init; } -- cgit v1.1 From 91a0b089f8358aec866bc9c69da8b84c77beaaf3 Mon Sep 17 00:00:00 2001 From: kishore kadiyala Date: Fri, 1 Oct 2010 16:35:28 -0700 Subject: omap4 hsmmc: Register offset handling In OMAP4, as per new PM programming model, the legacy registers which were there in OMAP3 are all shifted by 0x100 while new one's are added from offset 0 to 0x10. For OMAP4, the register offset appending of 0x100 done in devices.c currently, is moved to driver file.This change fits in for current implementation as well as once the driver undergoes hwmod adaptation. Cc: Andrew Morton Cc: Madhusudhan Chikkature Cc: Adrian Hunter Cc: Benoit Cousson Signed-off-by: Kishore Kadiyala Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/devices.c | 8 +++----- arch/arm/mach-omap2/hsmmc.c | 4 ++++ arch/arm/plat-omap/include/plat/mmc.h | 3 +++ 3 files changed, 10 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 9e5d51b..9bd4b34 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -817,13 +817,13 @@ void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, case 3: if (!cpu_is_omap44xx()) return; - base = OMAP4_MMC4_BASE + OMAP4_MMC_REG_OFFSET; + base = OMAP4_MMC4_BASE; irq = OMAP44XX_IRQ_MMC4; break; case 4: if (!cpu_is_omap44xx()) return; - base = OMAP4_MMC5_BASE + OMAP4_MMC_REG_OFFSET; + base = OMAP4_MMC5_BASE; irq = OMAP44XX_IRQ_MMC5; break; default: @@ -834,10 +834,8 @@ void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, size = OMAP2420_MMC_SIZE; name = "mmci-omap"; } else if (cpu_is_omap44xx()) { - if (i < 3) { - base += OMAP4_MMC_REG_OFFSET; + if (i < 3) irq += OMAP44XX_IRQ_GIC_START; - } size = OMAP4_HSMMC_SIZE; name = "mmci-omap-hs"; } else { diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c index df1311d..ab78a5a 100644 --- a/arch/arm/mach-omap2/hsmmc.c +++ b/arch/arm/mach-omap2/hsmmc.c @@ -266,6 +266,10 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) mmc->slots[0].caps = c->caps; mmc->slots[0].internal_clock = !c->ext_clock; mmc->dma_mask = 0xffffffff; + if (cpu_is_omap44xx()) + mmc->reg_offset = OMAP4_MMC_REG_OFFSET; + else + mmc->reg_offset = 0; mmc->get_context_loss_count = hsmmc_get_context_loss; diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h index 2c4629a8..0ce3099 100644 --- a/arch/arm/plat-omap/include/plat/mmc.h +++ b/arch/arm/plat-omap/include/plat/mmc.h @@ -71,6 +71,9 @@ struct omap_mmc_platform_data { u64 dma_mask; + /* Register offset deviation */ + u16 reg_offset; + struct omap_mmc_slot_data { /* 4/8 wires and any additional host capabilities -- cgit v1.1 From 64be97822b781e921c7eda2d4089fd1fdf3aabba Mon Sep 17 00:00:00 2001 From: kishore kadiyala Date: Fri, 1 Oct 2010 16:35:28 -0700 Subject: omap4 hsmmc: Update ocr mask for MMC2 for regulator to use On OMAP4, MMC2 controller has eMMC which draws power from VAUX regulator on TWL. Though the eMMC supports dual voltage[1.8v/3v] as per ocr register, its VCC is fixed at 3V for operation. With this once the mmc core selects the minimum voltage[1.8] supported based on the ocr value read from OCR register, eMMC will not get detected. Thus the platform data for MMC2 is updated with ocr mask and same will be communicated to core which will set the regulator to always operate at 3V when ever turned ON. Cc: Tony Lindgren Cc: Andrew Morton Cc: Madhusudhan Chikkature Cc: Adrian Hunter Signed-off-by: Kishore Kadiyala Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-4430sdp.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index cdb9373..9f75dc2 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -242,6 +242,7 @@ static struct omap2_hsmmc_info mmc[] = { .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, .nonremovable = true, + .ocr_mask = MMC_VDD_29_30, }, {} /* Terminator */ }; -- cgit v1.1 From 1a96edd70c1f4b4a1904803f8a83900087f4d1da Mon Sep 17 00:00:00 2001 From: Janusz Krzysztofik Date: Fri, 1 Oct 2010 16:37:00 -0700 Subject: OMAP1: Add support for SoC camera interface This patch adds a definition of the OMAP1 camera interface platform device, and a function that allows for providing a board specific platform data. The device will be used with the upcoming OMAP1 SoC camera interface driver. Signed-off-by: Janusz Krzysztofik Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/devices.c | 43 +++++++++++++++++++++++++++++++ arch/arm/mach-omap1/include/mach/camera.h | 11 ++++++++ 2 files changed, 54 insertions(+) create mode 100644 arch/arm/mach-omap1/include/mach/camera.h (limited to 'arch') diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c index aa07256..2c9a030 100644 --- a/arch/arm/mach-omap1/devices.c +++ b/arch/arm/mach-omap1/devices.c @@ -9,6 +9,7 @@ * (at your option) any later version. */ +#include #include #include #include @@ -191,6 +192,48 @@ static inline void omap_init_spi100k(void) } #endif + +#define OMAP1_CAMERA_BASE 0xfffb6800 +#define OMAP1_CAMERA_IOSIZE 0x1c + +static struct resource omap1_camera_resources[] = { + [0] = { + .start = OMAP1_CAMERA_BASE, + .end = OMAP1_CAMERA_BASE + OMAP1_CAMERA_IOSIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = INT_CAMERA, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 omap1_camera_dma_mask = DMA_BIT_MASK(32); + +static struct platform_device omap1_camera_device = { + .name = "omap1-camera", + .id = 0, /* This is used to put cameras on this interface */ + .dev = { + .dma_mask = &omap1_camera_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(omap1_camera_resources), + .resource = omap1_camera_resources, +}; + +void __init omap1_camera_init(void *info) +{ + struct platform_device *dev = &omap1_camera_device; + int ret; + + dev->dev.platform_data = info; + + ret = platform_device_register(dev); + if (ret) + dev_err(&dev->dev, "unable to register device: %d\n", ret); +} + + /*-------------------------------------------------------------------------*/ static inline void omap_init_sti(void) {} diff --git a/arch/arm/mach-omap1/include/mach/camera.h b/arch/arm/mach-omap1/include/mach/camera.h new file mode 100644 index 0000000..fd54b45 --- /dev/null +++ b/arch/arm/mach-omap1/include/mach/camera.h @@ -0,0 +1,11 @@ +#ifndef __ASM_ARCH_CAMERA_H_ +#define __ASM_ARCH_CAMERA_H_ + +void omap1_camera_init(void *); + +static inline void omap1_set_camera_info(struct omap1_cam_platform_data *info) +{ + omap1_camera_init(info); +} + +#endif /* __ASM_ARCH_CAMERA_H_ */ -- cgit v1.1 From 8452e9ef2b08c7bd492194554cdffc67d0b2a51b Mon Sep 17 00:00:00 2001 From: Janusz Krzysztofik Date: Fri, 1 Oct 2010 16:37:00 -0700 Subject: OMAP1: Amstrad Delta: add support for camera This patch adds configuration data and initialization code required for camera support to the Amstrad Delta board. Three devices are declared: SoC camera, OMAP1 camera interface and OV6650 sensor. Default 12MHz clock has been selected for driving the sensor. Pixel clock has been limited to get reasonable frame rates, not exceeding the board capabilities. Since both devices (interface and sensor) support both pixel clock polarities, decision on polarity selection has been left to drivers. Interface GPIO line has been found not functional, thus not configured. Signed-off-by: Janusz Krzysztofik Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/board-ams-delta.c | 45 +++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c index 41992ab..12f7f60 100644 --- a/arch/arm/mach-omap1/board-ams-delta.c +++ b/arch/arm/mach-omap1/board-ams-delta.c @@ -19,6 +19,8 @@ #include #include +#include + #include #include #include @@ -32,6 +34,7 @@ #include #include #include +#include #include @@ -213,10 +216,37 @@ static struct platform_device ams_delta_led_device = { .id = -1 }; +static struct i2c_board_info ams_delta_camera_board_info[] = { + { + I2C_BOARD_INFO("ov6650", 0x60), + }, +}; + +static struct soc_camera_link __initdata ams_delta_iclink = { + .bus_id = 0, /* OMAP1 SoC camera bus */ + .i2c_adapter_id = 1, + .board_info = &ams_delta_camera_board_info[0], + .module_name = "ov6650", +}; + +static struct platform_device ams_delta_camera_device = { + .name = "soc-camera-pdrv", + .id = 0, + .dev = { + .platform_data = &ams_delta_iclink, + }, +}; + +static struct omap1_cam_platform_data ams_delta_camera_platform_data = { + .camexclk_khz = 12000, /* default 12MHz clock, no extra DPLL */ + .lclk_khz_max = 1334, /* results in 5fps CIF, 10fps QCIF */ +}; + static struct platform_device *ams_delta_devices[] __initdata = { &ams_delta_kp_device, &ams_delta_lcd_device, &ams_delta_led_device, + &ams_delta_camera_device, }; static void __init ams_delta_init(void) @@ -225,6 +255,20 @@ static void __init ams_delta_init(void) omap_cfg_reg(UART1_TX); omap_cfg_reg(UART1_RTS); + /* parallel camera interface */ + omap_cfg_reg(H19_1610_CAM_EXCLK); + omap_cfg_reg(J15_1610_CAM_LCLK); + omap_cfg_reg(L18_1610_CAM_VS); + omap_cfg_reg(L15_1610_CAM_HS); + omap_cfg_reg(L19_1610_CAM_D0); + omap_cfg_reg(K14_1610_CAM_D1); + omap_cfg_reg(K15_1610_CAM_D2); + omap_cfg_reg(K19_1610_CAM_D3); + omap_cfg_reg(K18_1610_CAM_D4); + omap_cfg_reg(J14_1610_CAM_D5); + omap_cfg_reg(J19_1610_CAM_D6); + omap_cfg_reg(J18_1610_CAM_D7); + iotable_init(ams_delta_io_desc, ARRAY_SIZE(ams_delta_io_desc)); omap_board_config = ams_delta_config; @@ -236,6 +280,7 @@ static void __init ams_delta_init(void) ams_delta_latch2_write(~0, 0); omap1_usb_init(&ams_delta_usb_config); + omap1_set_camera_info(&ams_delta_camera_platform_data); platform_add_devices(ams_delta_devices, ARRAY_SIZE(ams_delta_devices)); #ifdef CONFIG_AMS_DELTA_FIQ -- cgit v1.1 From 243e76b426e6e040961b84249b4eaab4ad9fa6dc Mon Sep 17 00:00:00 2001 From: Janusz Krzysztofik Date: Fri, 1 Oct 2010 16:37:01 -0700 Subject: OMAP1: Amstrad Delta: add camera controlled LEDS trigger This patch extends the Amstrad Delta camera support with LEDS trigger that can be used for automatic control of the on-board camera LED. The led turns on automatically on camera device open and turns off on camera device close. Signed-off-by: Janusz Krzysztofik Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/board-ams-delta.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c index 12f7f60..248e8bb 100644 --- a/arch/arm/mach-omap1/board-ams-delta.c +++ b/arch/arm/mach-omap1/board-ams-delta.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include @@ -222,11 +223,30 @@ static struct i2c_board_info ams_delta_camera_board_info[] = { }, }; +#ifdef CONFIG_LEDS_TRIGGERS +DEFINE_LED_TRIGGER(ams_delta_camera_led_trigger); + +static int ams_delta_camera_power(struct device *dev, int power) +{ + /* + * turn on camera LED + */ + if (power) + led_trigger_event(ams_delta_camera_led_trigger, LED_FULL); + else + led_trigger_event(ams_delta_camera_led_trigger, LED_OFF); + return 0; +} +#else +#define ams_delta_camera_power NULL +#endif + static struct soc_camera_link __initdata ams_delta_iclink = { .bus_id = 0, /* OMAP1 SoC camera bus */ .i2c_adapter_id = 1, .board_info = &ams_delta_camera_board_info[0], .module_name = "ov6650", + .power = ams_delta_camera_power, }; static struct platform_device ams_delta_camera_device = { @@ -281,6 +301,10 @@ static void __init ams_delta_init(void) omap1_usb_init(&ams_delta_usb_config); omap1_set_camera_info(&ams_delta_camera_platform_data); +#ifdef CONFIG_LEDS_TRIGGERS + led_trigger_register_simple("ams_delta_camera", + &ams_delta_camera_led_trigger); +#endif platform_add_devices(ams_delta_devices, ARRAY_SIZE(ams_delta_devices)); #ifdef CONFIG_AMS_DELTA_FIQ -- cgit v1.1 From 720a6bd785f92782921a1d0f00f15d60997f4037 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Sat, 2 Oct 2010 19:20:51 +0900 Subject: sh: pinmux support for SH-X3 proto CPUs. This adds in support for GPIO/pinmux on the SH-X3 proto CPUs. This will subsequently be used by the x3proto board. Signed-off-by: Paul Mundt --- arch/sh/include/cpu-sh4/cpu/shx3.h | 64 ++++ arch/sh/kernel/cpu/sh4a/Makefile | 1 + arch/sh/kernel/cpu/sh4a/pinmux-shx3.c | 587 ++++++++++++++++++++++++++++++++++ 3 files changed, 652 insertions(+) create mode 100644 arch/sh/include/cpu-sh4/cpu/shx3.h create mode 100644 arch/sh/kernel/cpu/sh4a/pinmux-shx3.c (limited to 'arch') diff --git a/arch/sh/include/cpu-sh4/cpu/shx3.h b/arch/sh/include/cpu-sh4/cpu/shx3.h new file mode 100644 index 0000000..68d9080 --- /dev/null +++ b/arch/sh/include/cpu-sh4/cpu/shx3.h @@ -0,0 +1,64 @@ +#ifndef __CPU_SHX3_H +#define __CPU_SHX3_H + +enum { + /* PA */ + GPIO_PA7, GPIO_PA6, GPIO_PA5, GPIO_PA4, + GPIO_PA3, GPIO_PA2, GPIO_PA1, GPIO_PA0, + + /* PB */ + GPIO_PB7, GPIO_PB6, GPIO_PB5, GPIO_PB4, + GPIO_PB3, GPIO_PB2, GPIO_PB1, GPIO_PB0, + + /* PC */ + GPIO_PC7, GPIO_PC6, GPIO_PC5, GPIO_PC4, + GPIO_PC3, GPIO_PC2, GPIO_PC1, GPIO_PC0, + + /* PD */ + GPIO_PD7, GPIO_PD6, GPIO_PD5, GPIO_PD4, + GPIO_PD3, GPIO_PD2, GPIO_PD1, GPIO_PD0, + + /* PE */ + GPIO_PE7, GPIO_PE6, GPIO_PE5, GPIO_PE4, + GPIO_PE3, GPIO_PE2, GPIO_PE1, GPIO_PE0, + + /* PF */ + GPIO_PF7, GPIO_PF6, GPIO_PF5, GPIO_PF4, + GPIO_PF3, GPIO_PF2, GPIO_PF1, GPIO_PF0, + + /* PG */ + GPIO_PG7, GPIO_PG6, GPIO_PG5, GPIO_PG4, + GPIO_PG3, GPIO_PG2, GPIO_PG1, GPIO_PG0, + + /* PH */ + GPIO_PH5, GPIO_PH4, + GPIO_PH3, GPIO_PH2, GPIO_PH1, GPIO_PH0, + + /* SCIF */ + GPIO_FN_SCK3, GPIO_FN_TXD3, GPIO_FN_RXD3, + GPIO_FN_SCK2, GPIO_FN_TXD2, GPIO_FN_RXD2, + GPIO_FN_SCK1, GPIO_FN_TXD1, GPIO_FN_RXD1, + GPIO_FN_SCK0, GPIO_FN_TXD0, GPIO_FN_RXD0, + + /* LBSC */ + GPIO_FN_D31, GPIO_FN_D30, GPIO_FN_D29, GPIO_FN_D28, + GPIO_FN_D27, GPIO_FN_D26, GPIO_FN_D25, GPIO_FN_D24, + GPIO_FN_D23, GPIO_FN_D22, GPIO_FN_D21, GPIO_FN_D20, + GPIO_FN_D19, GPIO_FN_D18, GPIO_FN_D17, GPIO_FN_D16, + GPIO_FN_WE3, GPIO_FN_WE2, GPIO_FN_CS6, GPIO_FN_CS5, + GPIO_FN_CS4, GPIO_FN_CLKOUTENB, GPIO_FN_BREQ, + GPIO_FN_IOIS16, GPIO_FN_CE2B, GPIO_FN_CE2A, GPIO_FN_BACK, + + /* DMAC */ + GPIO_FN_DACK0, GPIO_FN_DREQ0, GPIO_FN_DRAK0, + GPIO_FN_DACK1, GPIO_FN_DREQ1, GPIO_FN_DRAK1, + GPIO_FN_DACK2, GPIO_FN_DREQ2, GPIO_FN_DRAK2, + GPIO_FN_DACK3, GPIO_FN_DREQ3, GPIO_FN_DRAK3, + + /* INTC */ + GPIO_FN_IRQ3, GPIO_FN_IRQ2, GPIO_FN_IRQ1, GPIO_FN_IRQ0, + GPIO_FN_IRL3, GPIO_FN_IRL2, GPIO_FN_IRL1, GPIO_FN_IRL0, + GPIO_FN_IRQOUT, GPIO_FN_STATUS1, GPIO_FN_STATUS0, +}; + +#endif /* __CPU_SHX3_H */ diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile index f2d6542..cc122b1 100644 --- a/arch/sh/kernel/cpu/sh4a/Makefile +++ b/arch/sh/kernel/cpu/sh4a/Makefile @@ -40,6 +40,7 @@ pinmux-$(CONFIG_CPU_SUBTYPE_SH7724) := pinmux-sh7724.o pinmux-$(CONFIG_CPU_SUBTYPE_SH7757) := pinmux-sh7757.o pinmux-$(CONFIG_CPU_SUBTYPE_SH7785) := pinmux-sh7785.o pinmux-$(CONFIG_CPU_SUBTYPE_SH7786) := pinmux-sh7786.o +pinmux-$(CONFIG_CPU_SUBTYPE_SHX3) := pinmux-shx3.o obj-y += $(clock-y) obj-$(CONFIG_SMP) += $(smp-y) diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c b/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c new file mode 100644 index 0000000..cc3bfac --- /dev/null +++ b/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c @@ -0,0 +1,587 @@ +/* + * SH-X3 prototype CPU pinmux + * + * Copyright (C) 2010 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA, + PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA, + PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA, + PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA, + PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA, + PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA, + PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA, + PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA, + PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA, + PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA, + PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA, + PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA, + PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA, + PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA, + + PH5_DATA, PH4_DATA, + PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA, + PINMUX_DATA_END, + + PINMUX_INPUT_BEGIN, + PA7_IN, PA6_IN, PA5_IN, PA4_IN, + PA3_IN, PA2_IN, PA1_IN, PA0_IN, + PB7_IN, PB6_IN, PB5_IN, PB4_IN, + PB3_IN, PB2_IN, PB1_IN, PB0_IN, + PC7_IN, PC6_IN, PC5_IN, PC4_IN, + PC3_IN, PC2_IN, PC1_IN, PC0_IN, + PD7_IN, PD6_IN, PD5_IN, PD4_IN, + PD3_IN, PD2_IN, PD1_IN, PD0_IN, + PE7_IN, PE6_IN, PE5_IN, PE4_IN, + PE3_IN, PE2_IN, PE1_IN, PE0_IN, + PF7_IN, PF6_IN, PF5_IN, PF4_IN, + PF3_IN, PF2_IN, PF1_IN, PF0_IN, + PG7_IN, PG6_IN, PG5_IN, PG4_IN, + PG3_IN, PG2_IN, PG1_IN, PG0_IN, + + PH5_IN, PH4_IN, + PH3_IN, PH2_IN, PH1_IN, PH0_IN, + PINMUX_INPUT_END, + + PINMUX_INPUT_PULLUP_BEGIN, + PA7_IN_PU, PA6_IN_PU, PA5_IN_PU, PA4_IN_PU, + PA3_IN_PU, PA2_IN_PU, PA1_IN_PU, PA0_IN_PU, + PB7_IN_PU, PB6_IN_PU, PB5_IN_PU, PB4_IN_PU, + PB3_IN_PU, PB2_IN_PU, PB1_IN_PU, PB0_IN_PU, + PC7_IN_PU, PC6_IN_PU, PC5_IN_PU, PC4_IN_PU, + PC3_IN_PU, PC2_IN_PU, PC1_IN_PU, PC0_IN_PU, + PD7_IN_PU, PD6_IN_PU, PD5_IN_PU, PD4_IN_PU, + PD3_IN_PU, PD2_IN_PU, PD1_IN_PU, PD0_IN_PU, + PE7_IN_PU, PE6_IN_PU, PE5_IN_PU, PE4_IN_PU, + PE3_IN_PU, PE2_IN_PU, PE1_IN_PU, PE0_IN_PU, + PF7_IN_PU, PF6_IN_PU, PF5_IN_PU, PF4_IN_PU, + PF3_IN_PU, PF2_IN_PU, PF1_IN_PU, PF0_IN_PU, + PG7_IN_PU, PG6_IN_PU, PG5_IN_PU, PG4_IN_PU, + PG3_IN_PU, PG2_IN_PU, PG1_IN_PU, PG0_IN_PU, + + PH5_IN_PU, PH4_IN_PU, + PH3_IN_PU, PH2_IN_PU, PH1_IN_PU, PH0_IN_PU, + PINMUX_INPUT_PULLUP_END, + + PINMUX_OUTPUT_BEGIN, + PA7_OUT, PA6_OUT, PA5_OUT, PA4_OUT, + PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT, + PB7_OUT, PB6_OUT, PB5_OUT, PB4_OUT, + PB3_OUT, PB2_OUT, PB1_OUT, PB0_OUT, + PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT, + PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT, + PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT, + PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT, + PE7_OUT, PE6_OUT, PE5_OUT, PE4_OUT, + PE3_OUT, PE2_OUT, PE1_OUT, PE0_OUT, + PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT, + PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT, + PG7_OUT, PG6_OUT, PG5_OUT, PG4_OUT, + PG3_OUT, PG2_OUT, PG1_OUT, PG0_OUT, + + PH5_OUT, PH4_OUT, + PH3_OUT, PH2_OUT, PH1_OUT, PH0_OUT, + PINMUX_OUTPUT_END, + + PINMUX_FUNCTION_BEGIN, + PA7_FN, PA6_FN, PA5_FN, PA4_FN, + PA3_FN, PA2_FN, PA1_FN, PA0_FN, + PB7_FN, PB6_FN, PB5_FN, PB4_FN, + PB3_FN, PB2_FN, PB1_FN, PB0_FN, + PC7_FN, PC6_FN, PC5_FN, PC4_FN, + PC3_FN, PC2_FN, PC1_FN, PC0_FN, + PD7_FN, PD6_FN, PD5_FN, PD4_FN, + PD3_FN, PD2_FN, PD1_FN, PD0_FN, + PE7_FN, PE6_FN, PE5_FN, PE4_FN, + PE3_FN, PE2_FN, PE1_FN, PE0_FN, + PF7_FN, PF6_FN, PF5_FN, PF4_FN, + PF3_FN, PF2_FN, PF1_FN, PF0_FN, + PG7_FN, PG6_FN, PG5_FN, PG4_FN, + PG3_FN, PG2_FN, PG1_FN, PG0_FN, + + PH5_FN, PH4_FN, + PH3_FN, PH2_FN, PH1_FN, PH0_FN, + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + + D31_MARK, D30_MARK, D29_MARK, D28_MARK, D27_MARK, D26_MARK, + D25_MARK, D24_MARK, D23_MARK, D22_MARK, D21_MARK, D20_MARK, + D19_MARK, D18_MARK, D17_MARK, D16_MARK, + + BACK_MARK, BREQ_MARK, + WE3_MARK, WE2_MARK, + CS6_MARK, CS5_MARK, CS4_MARK, + CLKOUTENB_MARK, + + DACK3_MARK, DACK2_MARK, DACK1_MARK, DACK0_MARK, + DREQ3_MARK, DREQ2_MARK, DREQ1_MARK, DREQ0_MARK, + + IRQ3_MARK, IRQ2_MARK, IRQ1_MARK, IRQ0_MARK, + + DRAK3_MARK, DRAK2_MARK, DRAK1_MARK, DRAK0_MARK, + + SCK3_MARK, SCK2_MARK, SCK1_MARK, SCK0_MARK, + IRL3_MARK, IRL2_MARK, IRL1_MARK, IRL0_MARK, + TXD3_MARK, TXD2_MARK, TXD1_MARK, TXD0_MARK, + RXD3_MARK, RXD2_MARK, RXD1_MARK, RXD0_MARK, + + CE2B_MARK, CE2A_MARK, IOIS16_MARK, + STATUS1_MARK, STATUS0_MARK, + + IRQOUT_MARK, + + PINMUX_MARK_END, +}; + +static pinmux_enum_t shx3_pinmux_data[] __initdata = { + + /* PA GPIO */ + PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU), + PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT, PA6_IN_PU), + PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT, PA5_IN_PU), + PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT, PA4_IN_PU), + PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT, PA3_IN_PU), + PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT, PA2_IN_PU), + PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT, PA1_IN_PU), + PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT, PA0_IN_PU), + + /* PB GPIO */ + PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT, PB7_IN_PU), + PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT, PB6_IN_PU), + PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT, PB5_IN_PU), + PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT, PB4_IN_PU), + PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT, PB3_IN_PU), + PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT, PB2_IN_PU), + PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT, PB1_IN_PU), + PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT, PB0_IN_PU), + + /* PC GPIO */ + PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT, PC7_IN_PU), + PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT, PC6_IN_PU), + PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT, PC5_IN_PU), + PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT, PC4_IN_PU), + PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT, PC3_IN_PU), + PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT, PC2_IN_PU), + PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT, PC1_IN_PU), + PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT, PC0_IN_PU), + + /* PD GPIO */ + PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT, PD7_IN_PU), + PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT, PD6_IN_PU), + PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT, PD5_IN_PU), + PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT, PD4_IN_PU), + PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT, PD3_IN_PU), + PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT, PD2_IN_PU), + PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT, PD1_IN_PU), + PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT, PD0_IN_PU), + + /* PE GPIO */ + PINMUX_DATA(PE7_DATA, PE7_IN, PE7_OUT, PE7_IN_PU), + PINMUX_DATA(PE6_DATA, PE6_IN, PE6_OUT, PE6_IN_PU), + PINMUX_DATA(PE5_DATA, PE5_IN, PE5_OUT, PE5_IN_PU), + PINMUX_DATA(PE4_DATA, PE4_IN, PE4_OUT, PE4_IN_PU), + PINMUX_DATA(PE3_DATA, PE3_IN, PE3_OUT, PE3_IN_PU), + PINMUX_DATA(PE2_DATA, PE2_IN, PE2_OUT, PE2_IN_PU), + PINMUX_DATA(PE1_DATA, PE1_IN, PE1_OUT, PE1_IN_PU), + PINMUX_DATA(PE0_DATA, PE0_IN, PE0_OUT, PE0_IN_PU), + + /* PF GPIO */ + PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT, PF7_IN_PU), + PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT, PF6_IN_PU), + PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT, PF5_IN_PU), + PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT, PF4_IN_PU), + PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT, PF3_IN_PU), + PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT, PF2_IN_PU), + PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT, PF1_IN_PU), + PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT, PF0_IN_PU), + + /* PG GPIO */ + PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT, PG7_IN_PU), + PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT, PG6_IN_PU), + PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT, PG5_IN_PU), + PINMUX_DATA(PG4_DATA, PG4_IN, PG4_OUT, PG4_IN_PU), + PINMUX_DATA(PG3_DATA, PG3_IN, PG3_OUT, PG3_IN_PU), + PINMUX_DATA(PG2_DATA, PG2_IN, PG2_OUT, PG2_IN_PU), + PINMUX_DATA(PG1_DATA, PG1_IN, PG1_OUT, PG1_IN_PU), + PINMUX_DATA(PG0_DATA, PG0_IN, PG0_OUT, PG0_IN_PU), + + /* PH GPIO */ + PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT, PH5_IN_PU), + PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT, PH4_IN_PU), + PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT, PH3_IN_PU), + PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT, PH2_IN_PU), + PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT, PH1_IN_PU), + PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT, PH0_IN_PU), + + /* PA FN */ + PINMUX_DATA(D31_MARK, PA7_FN), + PINMUX_DATA(D30_MARK, PA6_FN), + PINMUX_DATA(D29_MARK, PA5_FN), + PINMUX_DATA(D28_MARK, PA4_FN), + PINMUX_DATA(D27_MARK, PA3_FN), + PINMUX_DATA(D26_MARK, PA2_FN), + PINMUX_DATA(D25_MARK, PA1_FN), + PINMUX_DATA(D24_MARK, PA0_FN), + + /* PB FN */ + PINMUX_DATA(D23_MARK, PB7_FN), + PINMUX_DATA(D22_MARK, PB6_FN), + PINMUX_DATA(D21_MARK, PB5_FN), + PINMUX_DATA(D20_MARK, PB4_FN), + PINMUX_DATA(D19_MARK, PB3_FN), + PINMUX_DATA(D18_MARK, PB2_FN), + PINMUX_DATA(D17_MARK, PB1_FN), + PINMUX_DATA(D16_MARK, PB0_FN), + + /* PC FN */ + PINMUX_DATA(BACK_MARK, PC7_FN), + PINMUX_DATA(BREQ_MARK, PC6_FN), + PINMUX_DATA(WE3_MARK, PC5_FN), + PINMUX_DATA(WE2_MARK, PC4_FN), + PINMUX_DATA(CS6_MARK, PC3_FN), + PINMUX_DATA(CS5_MARK, PC2_FN), + PINMUX_DATA(CS4_MARK, PC1_FN), + PINMUX_DATA(CLKOUTENB_MARK, PC0_FN), + + /* PD FN */ + PINMUX_DATA(DACK3_MARK, PD7_FN), + PINMUX_DATA(DACK2_MARK, PD6_FN), + PINMUX_DATA(DACK1_MARK, PD5_FN), + PINMUX_DATA(DACK0_MARK, PD4_FN), + PINMUX_DATA(DREQ3_MARK, PD3_FN), + PINMUX_DATA(DREQ2_MARK, PD2_FN), + PINMUX_DATA(DREQ1_MARK, PD1_FN), + PINMUX_DATA(DREQ0_MARK, PD0_FN), + + /* PE FN */ + PINMUX_DATA(IRQ3_MARK, PE7_FN), + PINMUX_DATA(IRQ2_MARK, PE6_FN), + PINMUX_DATA(IRQ1_MARK, PE5_FN), + PINMUX_DATA(IRQ0_MARK, PE4_FN), + PINMUX_DATA(DRAK3_MARK, PE3_FN), + PINMUX_DATA(DRAK2_MARK, PE2_FN), + PINMUX_DATA(DRAK1_MARK, PE1_FN), + PINMUX_DATA(DRAK0_MARK, PE0_FN), + + /* PF FN */ + PINMUX_DATA(SCK3_MARK, PF7_FN), + PINMUX_DATA(SCK2_MARK, PF6_FN), + PINMUX_DATA(SCK1_MARK, PF5_FN), + PINMUX_DATA(SCK0_MARK, PF4_FN), + PINMUX_DATA(IRL3_MARK, PF3_FN), + PINMUX_DATA(IRL2_MARK, PF2_FN), + PINMUX_DATA(IRL1_MARK, PF1_FN), + PINMUX_DATA(IRL0_MARK, PF0_FN), + + /* PG FN */ + PINMUX_DATA(TXD3_MARK, PG7_FN), + PINMUX_DATA(TXD2_MARK, PG6_FN), + PINMUX_DATA(TXD1_MARK, PG5_FN), + PINMUX_DATA(TXD0_MARK, PG4_FN), + PINMUX_DATA(RXD3_MARK, PG3_FN), + PINMUX_DATA(RXD2_MARK, PG2_FN), + PINMUX_DATA(RXD1_MARK, PG1_FN), + PINMUX_DATA(RXD0_MARK, PG0_FN), + + /* PH FN */ + PINMUX_DATA(CE2B_MARK, PH5_FN), + PINMUX_DATA(CE2A_MARK, PH4_FN), + PINMUX_DATA(IOIS16_MARK, PH3_FN), + PINMUX_DATA(STATUS1_MARK, PH2_FN), + PINMUX_DATA(STATUS0_MARK, PH1_FN), + PINMUX_DATA(IRQOUT_MARK, PH0_FN), +}; + +static struct pinmux_gpio shx3_pinmux_gpios[] __initdata = { + /* PA */ + PINMUX_GPIO(GPIO_PA7, PA7_DATA), + PINMUX_GPIO(GPIO_PA6, PA6_DATA), + PINMUX_GPIO(GPIO_PA5, PA5_DATA), + PINMUX_GPIO(GPIO_PA4, PA4_DATA), + PINMUX_GPIO(GPIO_PA3, PA3_DATA), + PINMUX_GPIO(GPIO_PA2, PA2_DATA), + PINMUX_GPIO(GPIO_PA1, PA1_DATA), + PINMUX_GPIO(GPIO_PA0, PA0_DATA), + + /* PB */ + PINMUX_GPIO(GPIO_PB7, PB7_DATA), + PINMUX_GPIO(GPIO_PB6, PB6_DATA), + PINMUX_GPIO(GPIO_PB5, PB5_DATA), + PINMUX_GPIO(GPIO_PB4, PB4_DATA), + PINMUX_GPIO(GPIO_PB3, PB3_DATA), + PINMUX_GPIO(GPIO_PB2, PB2_DATA), + PINMUX_GPIO(GPIO_PB1, PB1_DATA), + PINMUX_GPIO(GPIO_PB0, PB0_DATA), + + /* PC */ + PINMUX_GPIO(GPIO_PC7, PC7_DATA), + PINMUX_GPIO(GPIO_PC6, PC6_DATA), + PINMUX_GPIO(GPIO_PC5, PC5_DATA), + PINMUX_GPIO(GPIO_PC4, PC4_DATA), + PINMUX_GPIO(GPIO_PC3, PC3_DATA), + PINMUX_GPIO(GPIO_PC2, PC2_DATA), + PINMUX_GPIO(GPIO_PC1, PC1_DATA), + PINMUX_GPIO(GPIO_PC0, PC0_DATA), + + /* PD */ + PINMUX_GPIO(GPIO_PD7, PD7_DATA), + PINMUX_GPIO(GPIO_PD6, PD6_DATA), + PINMUX_GPIO(GPIO_PD5, PD5_DATA), + PINMUX_GPIO(GPIO_PD4, PD4_DATA), + PINMUX_GPIO(GPIO_PD3, PD3_DATA), + PINMUX_GPIO(GPIO_PD2, PD2_DATA), + PINMUX_GPIO(GPIO_PD1, PD1_DATA), + PINMUX_GPIO(GPIO_PD0, PD0_DATA), + + /* PE */ + PINMUX_GPIO(GPIO_PE7, PE7_DATA), + PINMUX_GPIO(GPIO_PE6, PE6_DATA), + PINMUX_GPIO(GPIO_PE5, PE5_DATA), + PINMUX_GPIO(GPIO_PE4, PE4_DATA), + PINMUX_GPIO(GPIO_PE3, PE3_DATA), + PINMUX_GPIO(GPIO_PE2, PE2_DATA), + PINMUX_GPIO(GPIO_PE1, PE1_DATA), + PINMUX_GPIO(GPIO_PE0, PE0_DATA), + + /* PF */ + PINMUX_GPIO(GPIO_PF7, PF7_DATA), + PINMUX_GPIO(GPIO_PF6, PF6_DATA), + PINMUX_GPIO(GPIO_PF5, PF5_DATA), + PINMUX_GPIO(GPIO_PF4, PF4_DATA), + PINMUX_GPIO(GPIO_PF3, PF3_DATA), + PINMUX_GPIO(GPIO_PF2, PF2_DATA), + PINMUX_GPIO(GPIO_PF1, PF1_DATA), + PINMUX_GPIO(GPIO_PF0, PF0_DATA), + + /* PG */ + PINMUX_GPIO(GPIO_PG7, PG7_DATA), + PINMUX_GPIO(GPIO_PG6, PG6_DATA), + PINMUX_GPIO(GPIO_PG5, PG5_DATA), + PINMUX_GPIO(GPIO_PG4, PG4_DATA), + PINMUX_GPIO(GPIO_PG3, PG3_DATA), + PINMUX_GPIO(GPIO_PG2, PG2_DATA), + PINMUX_GPIO(GPIO_PG1, PG1_DATA), + PINMUX_GPIO(GPIO_PG0, PG0_DATA), + + /* PH */ + PINMUX_GPIO(GPIO_PH5, PH5_DATA), + PINMUX_GPIO(GPIO_PH4, PH4_DATA), + PINMUX_GPIO(GPIO_PH3, PH3_DATA), + PINMUX_GPIO(GPIO_PH2, PH2_DATA), + PINMUX_GPIO(GPIO_PH1, PH1_DATA), + PINMUX_GPIO(GPIO_PH0, PH0_DATA), + + /* FN */ + PINMUX_GPIO(GPIO_FN_D31, D31_MARK), + PINMUX_GPIO(GPIO_FN_D30, D30_MARK), + PINMUX_GPIO(GPIO_FN_D29, D29_MARK), + PINMUX_GPIO(GPIO_FN_D28, D28_MARK), + PINMUX_GPIO(GPIO_FN_D27, D27_MARK), + PINMUX_GPIO(GPIO_FN_D26, D26_MARK), + PINMUX_GPIO(GPIO_FN_D25, D25_MARK), + PINMUX_GPIO(GPIO_FN_D24, D24_MARK), + PINMUX_GPIO(GPIO_FN_D23, D23_MARK), + PINMUX_GPIO(GPIO_FN_D22, D22_MARK), + PINMUX_GPIO(GPIO_FN_D21, D21_MARK), + PINMUX_GPIO(GPIO_FN_D20, D20_MARK), + PINMUX_GPIO(GPIO_FN_D19, D19_MARK), + PINMUX_GPIO(GPIO_FN_D18, D18_MARK), + PINMUX_GPIO(GPIO_FN_D17, D17_MARK), + PINMUX_GPIO(GPIO_FN_D16, D16_MARK), + PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK), + PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK), + PINMUX_GPIO(GPIO_FN_WE3, WE3_MARK), + PINMUX_GPIO(GPIO_FN_WE2, WE2_MARK), + PINMUX_GPIO(GPIO_FN_CS6, CS6_MARK), + PINMUX_GPIO(GPIO_FN_CS5, CS5_MARK), + PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK), + PINMUX_GPIO(GPIO_FN_CLKOUTENB, CLKOUTENB_MARK), + PINMUX_GPIO(GPIO_FN_DACK3, DACK3_MARK), + PINMUX_GPIO(GPIO_FN_DACK2, DACK2_MARK), + PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), + PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), + PINMUX_GPIO(GPIO_FN_DREQ3, DREQ3_MARK), + PINMUX_GPIO(GPIO_FN_DREQ2, DREQ2_MARK), + PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), + PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), + PINMUX_GPIO(GPIO_FN_IRQ3, IRQ3_MARK), + PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK), + PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK), + PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK), + PINMUX_GPIO(GPIO_FN_DRAK3, DRAK3_MARK), + PINMUX_GPIO(GPIO_FN_DRAK2, DRAK2_MARK), + PINMUX_GPIO(GPIO_FN_DRAK1, DRAK1_MARK), + PINMUX_GPIO(GPIO_FN_DRAK0, DRAK0_MARK), + PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK), + PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK), + PINMUX_GPIO(GPIO_FN_SCK1, SCK1_MARK), + PINMUX_GPIO(GPIO_FN_SCK0, SCK0_MARK), + PINMUX_GPIO(GPIO_FN_IRL3, IRL3_MARK), + PINMUX_GPIO(GPIO_FN_IRL2, IRL2_MARK), + PINMUX_GPIO(GPIO_FN_IRL1, IRL1_MARK), + PINMUX_GPIO(GPIO_FN_IRL0, IRL0_MARK), + PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK), + PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK), + PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK), + PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK), + PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK), + PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK), + PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK), + PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK), + PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK), + PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK), + PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), + PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK), + PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), + PINMUX_GPIO(GPIO_FN_IRQOUT, IRQOUT_MARK), +}; + +static struct pinmux_cfg_reg shx3_pinmux_config_regs[] __initdata = { + { PINMUX_CFG_REG("PABCR", 0xffc70000, 32, 2) { + PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU, + PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU, + PA5_FN, PA5_OUT, PA5_IN, PA5_IN_PU, + PA4_FN, PA4_OUT, PA4_IN, PA4_IN_PU, + PA3_FN, PA3_OUT, PA3_IN, PA3_IN_PU, + PA2_FN, PA2_OUT, PA2_IN, PA2_IN_PU, + PA1_FN, PA1_OUT, PA1_IN, PA1_IN_PU, + PA0_FN, PA0_OUT, PA0_IN, PA0_IN_PU, + PB7_FN, PB7_OUT, PB7_IN, PB7_IN_PU, + PB6_FN, PB6_OUT, PB6_IN, PB6_IN_PU, + PB5_FN, PB5_OUT, PB5_IN, PB5_IN_PU, + PB4_FN, PB4_OUT, PB4_IN, PB4_IN_PU, + PB3_FN, PB3_OUT, PB3_IN, PB3_IN_PU, + PB2_FN, PB2_OUT, PB2_IN, PB2_IN_PU, + PB1_FN, PB1_OUT, PB1_IN, PB1_IN_PU, + PB0_FN, PB0_OUT, PB0_IN, PB0_IN_PU, }, + }, + { PINMUX_CFG_REG("PCDCR", 0xffc70004, 32, 2) { + PC7_FN, PC7_OUT, PC7_IN, PC7_IN_PU, + PC6_FN, PC6_OUT, PC6_IN, PC6_IN_PU, + PC5_FN, PC5_OUT, PC5_IN, PC5_IN_PU, + PC4_FN, PC4_OUT, PC4_IN, PC4_IN_PU, + PC3_FN, PC3_OUT, PC3_IN, PC3_IN_PU, + PC2_FN, PC2_OUT, PC2_IN, PC2_IN_PU, + PC1_FN, PC1_OUT, PC1_IN, PC1_IN_PU, + PC0_FN, PC0_OUT, PC0_IN, PC0_IN_PU, + PD7_FN, PD7_OUT, PD7_IN, PD7_IN_PU, + PD6_FN, PD6_OUT, PD6_IN, PD6_IN_PU, + PD5_FN, PD5_OUT, PD5_IN, PD5_IN_PU, + PD4_FN, PD4_OUT, PD4_IN, PD4_IN_PU, + PD3_FN, PD3_OUT, PD3_IN, PD3_IN_PU, + PD2_FN, PD2_OUT, PD2_IN, PD2_IN_PU, + PD1_FN, PD1_OUT, PD1_IN, PD1_IN_PU, + PD0_FN, PD0_OUT, PD0_IN, PD0_IN_PU, }, + }, + { PINMUX_CFG_REG("PEFCR", 0xffc70008, 32, 2) { + PE7_FN, PE7_OUT, PE7_IN, PE7_IN_PU, + PE6_FN, PE6_OUT, PE6_IN, PE6_IN_PU, + PE5_FN, PE5_OUT, PE5_IN, PE5_IN_PU, + PE4_FN, PE4_OUT, PE4_IN, PE4_IN_PU, + PE3_FN, PE3_OUT, PE3_IN, PE3_IN_PU, + PE2_FN, PE2_OUT, PE2_IN, PE2_IN_PU, + PE1_FN, PE1_OUT, PE1_IN, PE1_IN_PU, + PE0_FN, PE0_OUT, PE0_IN, PE0_IN_PU, + PF7_FN, PF7_OUT, PF7_IN, PF7_IN_PU, + PF6_FN, PF6_OUT, PF6_IN, PF6_IN_PU, + PF5_FN, PF5_OUT, PF5_IN, PF5_IN_PU, + PF4_FN, PF4_OUT, PF4_IN, PF4_IN_PU, + PF3_FN, PF3_OUT, PF3_IN, PF3_IN_PU, + PF2_FN, PF2_OUT, PF2_IN, PF2_IN_PU, + PF1_FN, PF1_OUT, PF1_IN, PF1_IN_PU, + PF0_FN, PF0_OUT, PF0_IN, PF0_IN_PU, }, + }, + { PINMUX_CFG_REG("PGHCR", 0xffc7000c, 32, 2) { + PG7_FN, PG7_OUT, PG7_IN, PG7_IN_PU, + PG6_FN, PG6_OUT, PG6_IN, PG6_IN_PU, + PG5_FN, PG5_OUT, PG5_IN, PG5_IN_PU, + PG4_FN, PG4_OUT, PG4_IN, PG4_IN_PU, + PG3_FN, PG3_OUT, PG3_IN, PG3_IN_PU, + PG2_FN, PG2_OUT, PG2_IN, PG2_IN_PU, + PG1_FN, PG1_OUT, PG1_IN, PG1_IN_PU, + PG0_FN, PG0_OUT, PG0_IN, PG0_IN_PU, + 0, 0, 0, 0, + 0, 0, 0, 0, + PH5_FN, PH5_OUT, PH5_IN, PH5_IN_PU, + PH4_FN, PH4_OUT, PH4_IN, PH4_IN_PU, + PH3_FN, PH3_OUT, PH3_IN, PH3_IN_PU, + PH2_FN, PH2_OUT, PH2_IN, PH2_IN_PU, + PH1_FN, PH1_OUT, PH1_IN, PH1_IN_PU, + PH0_FN, PH0_OUT, PH0_IN, PH0_IN_PU, }, + }, + { }, +}; + +static struct pinmux_data_reg shx3_pinmux_data_regs[] __initdata = { + { PINMUX_DATA_REG("PABDR", 0xffc70010, 32) { + 0, 0, 0, 0, 0, 0, 0, 0, + PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA, + PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA, + 0, 0, 0, 0, 0, 0, 0, 0, + PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA, + PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA, }, + }, + { PINMUX_DATA_REG("PCDDR", 0xffc70014, 32) { + 0, 0, 0, 0, 0, 0, 0, 0, + PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA, + PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA, + 0, 0, 0, 0, 0, 0, 0, 0, + PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA, + PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA, }, + }, + { PINMUX_DATA_REG("PEFDR", 0xffc70018, 32) { + 0, 0, 0, 0, 0, 0, 0, 0, + PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA, + PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA, + 0, 0, 0, 0, 0, 0, 0, 0, + PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA, + PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA, }, + }, + { PINMUX_DATA_REG("PGHDR", 0xffc7001c, 32) { + 0, 0, 0, 0, 0, 0, 0, 0, + PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA, + PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, PH5_DATA, PH4_DATA, + PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA, }, + }, + { }, +}; + +static struct pinmux_info shx3_pinmux_info __initdata = { + .name = "shx3_pfc", + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, + .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, + PINMUX_INPUT_PULLUP_END }, + .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + .first_gpio = GPIO_PA7, + .last_gpio = GPIO_FN_IRQOUT, + .gpios = shx3_pinmux_gpios, + .gpio_data = shx3_pinmux_data, + .gpio_data_size = ARRAY_SIZE(shx3_pinmux_data), + .cfg_regs = shx3_pinmux_config_regs, + .data_regs = shx3_pinmux_data_regs, +}; + +static int __init shx3_pinmux_setup(void) +{ + return register_pinmux(&shx3_pinmux_info); +} +arch_initcall(shx3_pinmux_setup); -- cgit v1.1 From 742759eae6b58a172d8f79ff0938d1e25dc9abc5 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Sat, 2 Oct 2010 19:43:40 +0900 Subject: sh: Handle pinmux for SH-X3 proto IRQ/IRL modes. The SH-X3 proto CPU has all of the external IRQ and IRL pins muxed, make sure that we're able to grab them before attempting to register their respective IRQ controllers. Signed-off-by: Paul Mundt --- arch/sh/Kconfig | 1 + arch/sh/kernel/cpu/sh4a/setup-shx3.c | 24 ++++++++++++++++++++++++ 2 files changed, 25 insertions(+) (limited to 'arch') diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index e46b61d..803f0c1 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -466,6 +466,7 @@ config CPU_SUBTYPE_SHX3 select CPU_SH4A select CPU_SHX3 select GENERIC_CLOCKEVENTS_BROADCAST if SMP + select ARCH_REQUIRE_GPIOLIB # SH4AL-DSP Processor Support diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c index 04a4874..f159ea2 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-shx3.c +++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c @@ -12,7 +12,9 @@ #include #include #include +#include #include +#include #include /* @@ -440,11 +442,33 @@ static DECLARE_INTC_DESC(intc_desc_irl, "shx3-irl", vectors_irl, groups, void __init plat_irq_setup_pins(int mode) { + int ret = 0; + switch (mode) { case IRQ_MODE_IRQ: + ret |= gpio_request(GPIO_FN_IRQ3, intc_desc_irq.name); + ret |= gpio_request(GPIO_FN_IRQ2, intc_desc_irq.name); + ret |= gpio_request(GPIO_FN_IRQ1, intc_desc_irq.name); + ret |= gpio_request(GPIO_FN_IRQ0, intc_desc_irq.name); + + if (unlikely(ret)) { + pr_err("Failed to set IRQ mode\n"); + return; + } + register_intc_controller(&intc_desc_irq); break; case IRQ_MODE_IRL3210: + ret |= gpio_request(GPIO_FN_IRL3, intc_desc_irl.name); + ret |= gpio_request(GPIO_FN_IRL2, intc_desc_irl.name); + ret |= gpio_request(GPIO_FN_IRL1, intc_desc_irl.name); + ret |= gpio_request(GPIO_FN_IRL0, intc_desc_irl.name); + + if (unlikely(ret)) { + pr_err("Failed to set IRL mode\n"); + return; + } + register_intc_controller(&intc_desc_irl); break; default: -- cgit v1.1 From 4bacd796ccd6976b03dd490708a1abc291d5521e Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Sat, 2 Oct 2010 22:02:07 +0900 Subject: sh: Support early IRQ vector map reservation for delayed controllers. Some controllers will need to be initialized lazily due to pinmux constraints, while others may simply have no need to be brought online if there are no backing devices for them attached. In this case it's still necessary to be able to reserve their hardware vector map before dynamic IRQs get a hold of them. Signed-off-by: Paul Mundt --- arch/sh/boards/mach-x3proto/setup.c | 23 ++++++++++++++--------- arch/sh/kernel/cpu/sh4a/setup-shx3.c | 3 +++ 2 files changed, 17 insertions(+), 9 deletions(-) (limited to 'arch') diff --git a/arch/sh/boards/mach-x3proto/setup.c b/arch/sh/boards/mach-x3proto/setup.c index 102bf56..21f1bb6 100644 --- a/arch/sh/boards/mach-x3proto/setup.c +++ b/arch/sh/boards/mach-x3proto/setup.c @@ -129,8 +129,22 @@ static struct platform_device *x3proto_devices[] __initdata = { &m66592_usb_peripheral_device, }; +static void __init x3proto_init_irq(void) +{ + plat_irq_setup_pins(IRQ_MODE_IRL3210); + + /* Set ICR0.LVLMODE */ + __raw_writel(__raw_readl(0xfe410000) | (1 << 21), 0xfe410000); +} + static int __init x3proto_devices_setup(void) { + /* + * IRLs are only needed for ILSEL mappings, so flip over the INTC + * pins at a later point to enable the GPIOs to settle. + */ + x3proto_init_irq(); + r8a66597_usb_host_resources[1].start = r8a66597_usb_host_resources[1].end = ilsel_enable(ILSEL_USBH_I); @@ -145,14 +159,6 @@ static int __init x3proto_devices_setup(void) } device_initcall(x3proto_devices_setup); -static void __init x3proto_init_irq(void) -{ - plat_irq_setup_pins(IRQ_MODE_IRL3210); - - /* Set ICR0.LVLMODE */ - __raw_writel(__raw_readl(0xfe410000) | (1 << 21), 0xfe410000); -} - static void __init x3proto_setup(char **cmdline_p) { register_smp_ops(&shx3_smp_ops); @@ -161,5 +167,4 @@ static void __init x3proto_setup(char **cmdline_p) static struct sh_machine_vector mv_x3proto __initmv = { .mv_name = "x3proto", .mv_setup = x3proto_setup, - .mv_init_irq = x3proto_init_irq, }; diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c index f159ea2..013f0b1 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-shx3.c +++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c @@ -478,6 +478,9 @@ void __init plat_irq_setup_pins(int mode) void __init plat_irq_setup(void) { + reserve_intc_vectors(vectors_irq, ARRAY_SIZE(vectors_irq)); + reserve_intc_vectors(vectors_irl, ARRAY_SIZE(vectors_irl)); + register_intc_controller(&intc_desc); } -- cgit v1.1 From 532f3759d71d1fceb494212187dacc5a78295dc3 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Sun, 3 Oct 2010 03:55:39 +0900 Subject: sh: Allow GPIO chips to register IRQ mappings. As non-PFC chips are added that may support IRQs, pass through to the generic helper instead of triggering the WARN_ON(). Signed-off-by: Paul Mundt --- arch/sh/include/asm/gpio.h | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/sh/include/asm/gpio.h b/arch/sh/include/asm/gpio.h index f8d9a73..04f53d3 100644 --- a/arch/sh/include/asm/gpio.h +++ b/arch/sh/include/asm/gpio.h @@ -41,14 +41,12 @@ static inline int gpio_cansleep(unsigned gpio) static inline int gpio_to_irq(unsigned gpio) { - WARN_ON(1); - return -ENOSYS; + return __gpio_to_irq(gpio); } static inline int irq_to_gpio(unsigned int irq) { - WARN_ON(1); - return -EINVAL; + return -ENOSYS; } #endif /* CONFIG_GPIOLIB */ -- cgit v1.1 From d39d0ed196aa1685bb24771e92f78633c66ac9cb Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Mon, 4 Oct 2010 02:50:32 +0900 Subject: sh: mach-x3proto: Move the ilsel header to a better place. We'll be adding more headers for this board, so move this over to its own directory. Signed-off-by: Paul Mundt --- arch/sh/boards/mach-x3proto/ilsel.c | 2 +- arch/sh/boards/mach-x3proto/setup.c | 2 +- arch/sh/include/asm/ilsel.h | 45 ------------------------------- arch/sh/include/mach-x3proto/mach/ilsel.h | 45 +++++++++++++++++++++++++++++++ 4 files changed, 47 insertions(+), 47 deletions(-) delete mode 100644 arch/sh/include/asm/ilsel.h create mode 100644 arch/sh/include/mach-x3proto/mach/ilsel.h (limited to 'arch') diff --git a/arch/sh/boards/mach-x3proto/ilsel.c b/arch/sh/boards/mach-x3proto/ilsel.c index 5c98427..aa8eb7e 100644 --- a/arch/sh/boards/mach-x3proto/ilsel.c +++ b/arch/sh/boards/mach-x3proto/ilsel.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include /* * ILSEL is split across: diff --git a/arch/sh/boards/mach-x3proto/setup.c b/arch/sh/boards/mach-x3proto/setup.c index 21f1bb6..8fd7510 100644 --- a/arch/sh/boards/mach-x3proto/setup.c +++ b/arch/sh/boards/mach-x3proto/setup.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include static struct resource heartbeat_resources[] = { diff --git a/arch/sh/include/asm/ilsel.h b/arch/sh/include/asm/ilsel.h deleted file mode 100644 index e3d304b..0000000 --- a/arch/sh/include/asm/ilsel.h +++ /dev/null @@ -1,45 +0,0 @@ -#ifndef __ASM_SH_ILSEL_H -#define __ASM_SH_ILSEL_H - -typedef enum { - ILSEL_NONE, - ILSEL_LAN, - ILSEL_USBH_I, - ILSEL_USBH_S, - ILSEL_USBH_V, - ILSEL_RTC, - ILSEL_USBP_I, - ILSEL_USBP_S, - ILSEL_USBP_V, - ILSEL_KEY, - - /* - * ILSEL Aliases - corner cases for interleaved level tables. - * - * Someone thought this was a good idea and less hassle than - * demuxing a shared vector, really. - */ - - /* ILSEL0 and 2 */ - ILSEL_FPGA0, - ILSEL_FPGA1, - ILSEL_EX1, - ILSEL_EX2, - ILSEL_EX3, - ILSEL_EX4, - - /* ILSEL1 and 3 */ - ILSEL_FPGA2 = ILSEL_FPGA0, - ILSEL_FPGA3 = ILSEL_FPGA1, - ILSEL_EX5 = ILSEL_EX1, - ILSEL_EX6 = ILSEL_EX2, - ILSEL_EX7 = ILSEL_EX3, - ILSEL_EX8 = ILSEL_EX4, -} ilsel_source_t; - -/* arch/sh/boards/renesas/x3proto/ilsel.c */ -int ilsel_enable(ilsel_source_t set); -int ilsel_enable_fixed(ilsel_source_t set, unsigned int level); -void ilsel_disable(unsigned int irq); - -#endif /* __ASM_SH_ILSEL_H */ diff --git a/arch/sh/include/mach-x3proto/mach/ilsel.h b/arch/sh/include/mach-x3proto/mach/ilsel.h new file mode 100644 index 0000000..e3d304b --- /dev/null +++ b/arch/sh/include/mach-x3proto/mach/ilsel.h @@ -0,0 +1,45 @@ +#ifndef __ASM_SH_ILSEL_H +#define __ASM_SH_ILSEL_H + +typedef enum { + ILSEL_NONE, + ILSEL_LAN, + ILSEL_USBH_I, + ILSEL_USBH_S, + ILSEL_USBH_V, + ILSEL_RTC, + ILSEL_USBP_I, + ILSEL_USBP_S, + ILSEL_USBP_V, + ILSEL_KEY, + + /* + * ILSEL Aliases - corner cases for interleaved level tables. + * + * Someone thought this was a good idea and less hassle than + * demuxing a shared vector, really. + */ + + /* ILSEL0 and 2 */ + ILSEL_FPGA0, + ILSEL_FPGA1, + ILSEL_EX1, + ILSEL_EX2, + ILSEL_EX3, + ILSEL_EX4, + + /* ILSEL1 and 3 */ + ILSEL_FPGA2 = ILSEL_FPGA0, + ILSEL_FPGA3 = ILSEL_FPGA1, + ILSEL_EX5 = ILSEL_EX1, + ILSEL_EX6 = ILSEL_EX2, + ILSEL_EX7 = ILSEL_EX3, + ILSEL_EX8 = ILSEL_EX4, +} ilsel_source_t; + +/* arch/sh/boards/renesas/x3proto/ilsel.c */ +int ilsel_enable(ilsel_source_t set); +int ilsel_enable_fixed(ilsel_source_t set, unsigned int level); +void ilsel_disable(unsigned int irq); + +#endif /* __ASM_SH_ILSEL_H */ -- cgit v1.1 From 550591143eead286f2cd9d124a55d4a99ed024de Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Mon, 4 Oct 2010 02:59:29 +0900 Subject: sh: mach-x3proto: Support for baseboard GPIOs. This adds trivial support for the GPIOs implemented through the baseboard CPLD, used for driving the button matrix. Signed-off-by: Paul Mundt --- arch/sh/boards/mach-x3proto/Makefile | 2 + arch/sh/boards/mach-x3proto/gpio.c | 135 +++++++++++++++++++++++++++ arch/sh/include/mach-x3proto/mach/hardware.h | 12 +++ 3 files changed, 149 insertions(+) create mode 100644 arch/sh/boards/mach-x3proto/gpio.c create mode 100644 arch/sh/include/mach-x3proto/mach/hardware.h (limited to 'arch') diff --git a/arch/sh/boards/mach-x3proto/Makefile b/arch/sh/boards/mach-x3proto/Makefile index 983e455..708c21c 100644 --- a/arch/sh/boards/mach-x3proto/Makefile +++ b/arch/sh/boards/mach-x3proto/Makefile @@ -1 +1,3 @@ obj-y += setup.o ilsel.o + +obj-$(CONFIG_GENERIC_GPIO) += gpio.o diff --git a/arch/sh/boards/mach-x3proto/gpio.c b/arch/sh/boards/mach-x3proto/gpio.c new file mode 100644 index 0000000..9fcd7ce --- /dev/null +++ b/arch/sh/boards/mach-x3proto/gpio.c @@ -0,0 +1,135 @@ +/* + * arch/sh/boards/mach-x3proto/gpio.c + * + * Renesas SH-X3 Prototype Baseboard GPIO Support. + * + * Copyright (C) 2010 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define KEYCTLR 0xb81c0000 +#define KEYOUTR 0xb81c0002 +#define KEYDETR 0xb81c0004 + +static DEFINE_SPINLOCK(x3proto_gpio_lock); +static unsigned int x3proto_gpio_irq_map[NR_BASEBOARD_GPIOS] = { 0, }; + +static int x3proto_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) +{ + unsigned long flags; + unsigned int data; + + spin_lock_irqsave(&x3proto_gpio_lock, flags); + data = __raw_readw(KEYCTLR); + data |= (1 << gpio); + __raw_writew(data, KEYCTLR); + spin_unlock_irqrestore(&x3proto_gpio_lock, flags); + + return 0; +} + +static int x3proto_gpio_get(struct gpio_chip *chip, unsigned gpio) +{ + return !!(__raw_readw(KEYDETR) & (1 << gpio)); +} + +static int x3proto_gpio_to_irq(struct gpio_chip *chip, unsigned gpio) +{ + return x3proto_gpio_irq_map[gpio]; +} + +static void x3proto_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + struct irq_chip *chip = get_irq_desc_chip(desc); + unsigned long mask; + int pin; + + chip->mask_ack(irq); + + mask = __raw_readw(KEYDETR); + + for_each_set_bit(pin, &mask, NR_BASEBOARD_GPIOS) + generic_handle_irq(x3proto_gpio_to_irq(NULL, pin)); + + chip->unmask(irq); +} + +struct gpio_chip x3proto_gpio_chip = { + .label = "x3proto-gpio", + .direction_input = x3proto_gpio_direction_input, + .get = x3proto_gpio_get, + .to_irq = x3proto_gpio_to_irq, + .base = -1, + .ngpio = NR_BASEBOARD_GPIOS, +}; + +int __init x3proto_gpio_setup(void) +{ + unsigned int ilsel; + int ret, i; + + ilsel = ilsel_enable(ILSEL_KEY); + if (unlikely(ilsel < 0)) + return ilsel; + + ret = gpiochip_add(&x3proto_gpio_chip); + if (unlikely(ret)) + goto err_gpio; + + for (i = 0; i < NR_BASEBOARD_GPIOS; i++) { + unsigned long flags; + unsigned int irq = create_irq(); + + if (unlikely(irq < 0)) { + ret = -EINVAL; + goto err_irq; + } + + spin_lock_irqsave(&x3proto_gpio_lock, flags); + x3proto_gpio_irq_map[i] = irq; + set_irq_chip_and_handler_name(irq, &dummy_irq_chip, + handle_simple_irq, "gpio"); + spin_unlock_irqrestore(&x3proto_gpio_lock, flags); + } + + pr_info("registering '%s' support, handling GPIOs %u -> %u, " + "bound to IRQ %u\n", + x3proto_gpio_chip.label, x3proto_gpio_chip.base, + x3proto_gpio_chip.base + x3proto_gpio_chip.ngpio, + ilsel); + + set_irq_chained_handler(ilsel, x3proto_gpio_irq_handler); + set_irq_wake(ilsel, 1); + + return 0; + +err_irq: + for (; i >= 0; --i) + if (x3proto_gpio_irq_map[i]) + destroy_irq(x3proto_gpio_irq_map[i]); + + ret = gpiochip_remove(&x3proto_gpio_chip); + if (unlikely(ret)) + pr_err("Failed deregistering GPIO\n"); + +err_gpio: + synchronize_irq(ilsel); + + ilsel_disable(ILSEL_KEY); + + return ret; +} diff --git a/arch/sh/include/mach-x3proto/mach/hardware.h b/arch/sh/include/mach-x3proto/mach/hardware.h new file mode 100644 index 0000000..52bca57 --- /dev/null +++ b/arch/sh/include/mach-x3proto/mach/hardware.h @@ -0,0 +1,12 @@ +#ifndef __MACH_X3PROTO_HARDWARE_H +#define __MACH_X3PROTO_HARDWARE_H + +struct gpio_chip; + +/* arch/sh/boards/mach-x3proto/gpio.c */ +int x3proto_gpio_setup(void); +extern struct gpio_chip x3proto_gpio_chip; + +#define NR_BASEBOARD_GPIOS 16 + +#endif /* __MACH_X3PROTO_HARDWARE_H */ -- cgit v1.1 From 2c237329f79aba2cd1d1c1b47fc03df03ad027e1 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Mon, 4 Oct 2010 03:00:49 +0900 Subject: sh: mach-x3proto: gpio-keys support. This adds gpio-keys mappings for the button matrix on the baseboard, now that we have support for the pin controller. Signed-off-by: Paul Mundt --- arch/sh/boards/mach-x3proto/setup.c | 107 +++++++++++++++++++++++++++++++++++- 1 file changed, 105 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/sh/boards/mach-x3proto/setup.c b/arch/sh/boards/mach-x3proto/setup.c index 8fd7510..d682e2b 100644 --- a/arch/sh/boards/mach-x3proto/setup.c +++ b/arch/sh/boards/mach-x3proto/setup.c @@ -1,9 +1,9 @@ /* - * arch/sh/boards/renesas/x3proto/setup.c + * arch/sh/boards/mach-x3proto/setup.c * * Renesas SH-X3 Prototype Board Support. * - * Copyright (C) 2007 - 2008 Paul Mundt + * Copyright (C) 2007 - 2010 Paul Mundt * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -16,9 +16,13 @@ #include #include #include +#include #include #include +#include +#include #include +#include #include static struct resource heartbeat_resources[] = { @@ -122,11 +126,95 @@ static struct platform_device m66592_usb_peripheral_device = { .resource = m66592_usb_peripheral_resources, }; +static struct gpio_keys_button baseboard_buttons[NR_BASEBOARD_GPIOS] = { + { + .desc = "key44", + .code = KEY_POWER, + .active_low = 1, + .wakeup = 1, + }, { + .desc = "key43", + .code = KEY_SUSPEND, + .active_low = 1, + .wakeup = 1, + }, { + .desc = "key42", + .code = KEY_KATAKANAHIRAGANA, + .active_low = 1, + }, { + .desc = "key41", + .code = KEY_SWITCHVIDEOMODE, + .active_low = 1, + }, { + .desc = "key34", + .code = KEY_F12, + .active_low = 1, + }, { + .desc = "key33", + .code = KEY_F11, + .active_low = 1, + }, { + .desc = "key32", + .code = KEY_F10, + .active_low = 1, + }, { + .desc = "key31", + .code = KEY_F9, + .active_low = 1, + }, { + .desc = "key24", + .code = KEY_F8, + .active_low = 1, + }, { + .desc = "key23", + .code = KEY_F7, + .active_low = 1, + }, { + .desc = "key22", + .code = KEY_F6, + .active_low = 1, + }, { + .desc = "key21", + .code = KEY_F5, + .active_low = 1, + }, { + .desc = "key14", + .code = KEY_F4, + .active_low = 1, + }, { + .desc = "key13", + .code = KEY_F3, + .active_low = 1, + }, { + .desc = "key12", + .code = KEY_F2, + .active_low = 1, + }, { + .desc = "key11", + .code = KEY_F1, + .active_low = 1, + }, +}; + +static struct gpio_keys_platform_data baseboard_buttons_data = { + .buttons = baseboard_buttons, + .nbuttons = ARRAY_SIZE(baseboard_buttons), +}; + +static struct platform_device baseboard_buttons_device = { + .name = "gpio-keys", + .id = -1, + .dev = { + .platform_data = &baseboard_buttons_data, + }, +}; + static struct platform_device *x3proto_devices[] __initdata = { &heartbeat_device, &smc91x_device, &r8a66597_usb_host_device, &m66592_usb_peripheral_device, + &baseboard_buttons_device, }; static void __init x3proto_init_irq(void) @@ -139,12 +227,27 @@ static void __init x3proto_init_irq(void) static int __init x3proto_devices_setup(void) { + int ret, i; + /* * IRLs are only needed for ILSEL mappings, so flip over the INTC * pins at a later point to enable the GPIOs to settle. */ x3proto_init_irq(); + /* + * Now that ILSELs are available, set up the baseboard GPIOs. + */ + ret = x3proto_gpio_setup(); + if (unlikely(ret)) + return ret; + + /* + * Propagate dynamic GPIOs for the baseboard button device. + */ + for (i = 0; i < ARRAY_SIZE(baseboard_buttons); i++) + baseboard_buttons[i].gpio = x3proto_gpio_chip.base + i; + r8a66597_usb_host_resources[1].start = r8a66597_usb_host_resources[1].end = ilsel_enable(ILSEL_USBH_I); -- cgit v1.1 From 3bccf534f98ddc4962665b68d99f752ea010aacc Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Mon, 4 Oct 2010 03:07:49 +0900 Subject: sh: mach-x3proto: Improve ILSEL debugging. At the moment ILSEL blows up with a BUG when aliased sets are handed in, but as the enable call is able to hand back errors we opt for that path instead. None of the ILSEL peripherals are vital to the board's operation, so trapping a BUG is a bit excessive. Signed-off-by: Paul Mundt --- arch/sh/boards/mach-x3proto/ilsel.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/sh/boards/mach-x3proto/ilsel.c b/arch/sh/boards/mach-x3proto/ilsel.c index aa8eb7e..95e3461 100644 --- a/arch/sh/boards/mach-x3proto/ilsel.c +++ b/arch/sh/boards/mach-x3proto/ilsel.c @@ -1,14 +1,16 @@ /* - * arch/sh/boards/renesas/x3proto/ilsel.c + * arch/sh/boards/mach-x3proto/ilsel.c * * Helper routines for SH-X3 proto board ILSEL. * - * Copyright (C) 2007 Paul Mundt + * Copyright (C) 2007 - 2010 Paul Mundt * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. */ +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + #include #include #include @@ -64,6 +66,8 @@ static void __ilsel_enable(ilsel_source_t set, unsigned int bit) unsigned int tmp, shift; unsigned long addr; + pr_notice("enabling ILSEL set %d\n", set); + addr = mk_ilsel_addr(bit); shift = mk_ilsel_shift(bit); @@ -92,8 +96,10 @@ int ilsel_enable(ilsel_source_t set) { unsigned int bit; - /* Aliased sources must use ilsel_enable_fixed() */ - BUG_ON(set > ILSEL_KEY); + if (unlikely(set > ILSEL_KEY)) { + pr_err("Aliased sources must use ilsel_enable_fixed()\n"); + return -EINVAL; + } do { bit = find_first_zero_bit(&ilsel_level_map, ILSEL_LEVELS); @@ -140,6 +146,8 @@ void ilsel_disable(unsigned int irq) unsigned long addr; unsigned int tmp; + pr_notice("disabling ILSEL set %d\n", irq); + addr = mk_ilsel_addr(irq); tmp = __raw_readw(addr); -- cgit v1.1 From 872f36a69fea9763f000ec1bc7a5282e43b67b96 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Mon, 4 Oct 2010 05:00:19 +0900 Subject: sh: Drop __initdata for SH-X3 pinmux tables. The gpio sysfs support needs to get at these later, so drop the __initdata annotations. Signed-off-by: Paul Mundt --- arch/sh/kernel/cpu/sh4a/pinmux-shx3.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c b/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c index cc3bfac..aaa5338 100644 --- a/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c +++ b/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c @@ -146,7 +146,7 @@ enum { PINMUX_MARK_END, }; -static pinmux_enum_t shx3_pinmux_data[] __initdata = { +static pinmux_enum_t shx3_pinmux_data[] = { /* PA GPIO */ PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU), @@ -305,7 +305,7 @@ static pinmux_enum_t shx3_pinmux_data[] __initdata = { PINMUX_DATA(IRQOUT_MARK, PH0_FN), }; -static struct pinmux_gpio shx3_pinmux_gpios[] __initdata = { +static struct pinmux_gpio shx3_pinmux_gpios[] = { /* PA */ PINMUX_GPIO(GPIO_PA7, PA7_DATA), PINMUX_GPIO(GPIO_PA6, PA6_DATA), @@ -449,7 +449,7 @@ static struct pinmux_gpio shx3_pinmux_gpios[] __initdata = { PINMUX_GPIO(GPIO_FN_IRQOUT, IRQOUT_MARK), }; -static struct pinmux_cfg_reg shx3_pinmux_config_regs[] __initdata = { +static struct pinmux_cfg_reg shx3_pinmux_config_regs[] = { { PINMUX_CFG_REG("PABCR", 0xffc70000, 32, 2) { PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU, PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU, @@ -525,7 +525,7 @@ static struct pinmux_cfg_reg shx3_pinmux_config_regs[] __initdata = { { }, }; -static struct pinmux_data_reg shx3_pinmux_data_regs[] __initdata = { +static struct pinmux_data_reg shx3_pinmux_data_regs[] = { { PINMUX_DATA_REG("PABDR", 0xffc70010, 32) { 0, 0, 0, 0, 0, 0, 0, 0, PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA, @@ -561,7 +561,7 @@ static struct pinmux_data_reg shx3_pinmux_data_regs[] __initdata = { { }, }; -static struct pinmux_info shx3_pinmux_info __initdata = { +static struct pinmux_info shx3_pinmux_info = { .name = "shx3_pfc", .reserved_id = PINMUX_RESERVED, .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, -- cgit v1.1 From 156a0f8ecb05bae53f1652ddb151c74315a615fb Mon Sep 17 00:00:00 2001 From: Nicolas Kaiser Date: Mon, 4 Oct 2010 12:39:47 +0200 Subject: arm/davinci: remove duplicated include Remove duplicated include. Signed-off-by: Nicolas Kaiser Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/board-da850-evm.c | 1 - 1 file changed, 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index 5e435b0..ef97c7f 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include -- cgit v1.1 From c1e30ad98fe210688edca872686db4a715c2fb23 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Tue, 5 Oct 2010 04:47:03 +0900 Subject: sh: intc: Support virtual mappings for IRQ subgroups. Many interrupts that share a single mask source but are on different hardware vectors will have an associated register tied to an INTEVT that denotes the precise cause for the interrupt exception being triggered. This introduces the concept of IRQ subgroups in the intc core, where a virtual IRQ map is constructed for each of the pre-defined cause bits, and a higher level chained handler takes control of the parent INTEVT. This enables CPUs with heavily muxed IRQ vectors (especially across disjoint blocks) to break things out in to a series of managed chained handlers while being able to dynamically lookup and adopt the IRQs created for them. This is largely an opt-in interface, requiring CPUs to manually submit IRQs for subgroup splitting, in addition to providing identifiers in their enum maps that can be used for lazy lookup via the radix tree. Signed-off-by: Paul Mundt --- arch/sh/kernel/irq.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/sh/kernel/irq.c b/arch/sh/kernel/irq.c index 257de1f..c8e1409 100644 --- a/arch/sh/kernel/irq.c +++ b/arch/sh/kernel/irq.c @@ -283,6 +283,8 @@ void __init init_IRQ(void) if (sh_mv.mv_init_irq) sh_mv.mv_init_irq(); + intc_finalize(); + irq_ctx_init(smp_processor_id()); } -- cgit v1.1 From a09f73fabbeac81f45969ad9ed59e74fae736873 Mon Sep 17 00:00:00 2001 From: Jarkko Nikula Date: Mon, 4 Oct 2010 15:04:53 +0300 Subject: omap: devices: Avoid merge conflict between ASoC and OMAP hwmod changes Upcoming ASoC multi-component and OMAP hwmod changes will conflict in arch/arm/mach-omap2/devices.c. Avoid this by moving a little bit include statement introduced by ASoC Multi-Component Support patch. Signed-off-by: Jarkko Nikula Cc: Paul Walmsley Cc: Tony Lindgren Acked-by: Mark Brown Signed-off-by: Liam Girdwood --- arch/arm/mach-omap2/devices.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 08e1ad5..512ae46 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -25,10 +25,10 @@ #include #include #include +#include #include #include #include -#include #include "mux.h" -- cgit v1.1 From 63509e3c03ae22000c642e33b5006769d1b5db86 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 4 Oct 2010 16:58:01 -0700 Subject: omap: Keep nwires for omap1 and 2420 MMC controller A patch from Sukumar Ghorai changed the nwires to use caps instead. However, nwires is still needed for the earlier controller. Signed-off-by: Tony Lindgren Acked-by: Sukumar Ghorai Signed-off-by: Ming Lei --- arch/arm/mach-omap2/board-n8x0.c | 2 +- arch/arm/plat-omap/include/plat/mmc.h | 9 ++++++--- 2 files changed, 7 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c index 7a93bd5..8fd2269 100644 --- a/arch/arm/mach-omap2/board-n8x0.c +++ b/arch/arm/mach-omap2/board-n8x0.c @@ -488,7 +488,7 @@ static struct omap_mmc_platform_data mmc1_data = { .max_freq = 24000000, .dma_mask = 0xffffffff, .slots[0] = { - .caps = MMC_CAP_4_BIT_DATA, + .wires = 4, .set_power = n8x0_mmc_set_power, .set_bus_mode = n8x0_mmc_set_bus_mode, .get_cover_state = n8x0_mmc_get_cover_state, diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h index 4f819fc..c5f35f8 100644 --- a/arch/arm/plat-omap/include/plat/mmc.h +++ b/arch/arm/plat-omap/include/plat/mmc.h @@ -73,9 +73,12 @@ struct omap_mmc_platform_data { struct omap_mmc_slot_data { - /* 4/8 wires and any additional host capabilities - * need to OR'd all capabilities (ref. linux/mmc/host.h) */ - u32 caps; + /* + * 4/8 wires and any additional host capabilities + * need to OR'd all capabilities (ref. linux/mmc/host.h) + */ + u8 wires; /* Used for the MMC driver on omap1 and 2420 */ + u32 caps; /* Used for the MMC driver on 2430 and later */ /* * nomux means "standard" muxing is wrong on this board, and -- cgit v1.1 From 4b48e6876b641e1138f37a0fc11fb6a4fc3e24e1 Mon Sep 17 00:00:00 2001 From: ext Anand Gadiyar Date: Fri, 1 Oct 2010 22:33:26 +0200 Subject: omap: zoom2/3: fix build caused by wl1271 support Patch "omap: zoom: add mmc3/wl1271 device support" in the wireless tree still uses .wires in struct omap2_hsmmc_info. .wires has now been replaced with .caps in patch "omap: mmc: extended to pass host capabilities from board file" in the OMAP tree. This causes linux-next as of 20101001 build to break as below. Fix this. CC arch/arm/mach-omap2/board-zoom-peripherals.o arch/arm/mach-omap2/board-zoom-peripherals.c:217: error: unknown field 'wires' specified in initializer make[1]: *** [arch/arm/mach-omap2/board-zoom-peripherals.o] Error 1 make: *** [arch/arm/mach-omap2] Error 2 Signed-off-by: Anand Gadiyar Cc: Ohad Ben-Cohen Cc: Tony Lindgren Acked-by: Tony Lindgren Signed-off-by: Luciano Coelho --- arch/arm/mach-omap2/board-zoom-peripherals.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c index 6aa0728..189a6d1 100644 --- a/arch/arm/mach-omap2/board-zoom-peripherals.c +++ b/arch/arm/mach-omap2/board-zoom-peripherals.c @@ -213,7 +213,7 @@ static struct omap2_hsmmc_info mmc[] __initdata = { { .name = "wl1271", .mmc = 3, - .wires = 4, + .caps = MMC_CAP_4_BIT_DATA, .gpio_wp = -EINVAL, .gpio_cd = -EINVAL, .nonremovable = true, -- cgit v1.1 From d91ddc2553426a2d9b6b978b5e346f303fccee67 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Tue, 5 Oct 2010 23:26:42 +0900 Subject: sh: Wire up INTC subgroup splitting for SH7786 SCIF1. SH7786 is the big user for subgroup splitting, mostly for the PCIe block, but those will follow later. For now we simply split up SCIF1, as used by the serial console on SDK7786 and others. Signed-off-by: Paul Mundt --- arch/sh/kernel/cpu/sh4a/setup-sh7786.c | 110 +++++++++++++++++++++------------ 1 file changed, 72 insertions(+), 38 deletions(-) (limited to 'arch') diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c index bbc0a97..c016c00 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c @@ -629,33 +629,10 @@ static void __init sh7786_usb_setup(void) } } -static int __init sh7786_devices_setup(void) -{ - int ret; - - sh7786_usb_setup(); - - ret = platform_add_devices(sh7786_early_devices, - ARRAY_SIZE(sh7786_early_devices)); - if (unlikely(ret != 0)) - return ret; - - return platform_add_devices(sh7786_devices, - ARRAY_SIZE(sh7786_devices)); -} -arch_initcall(sh7786_devices_setup); - -void __init plat_early_device_setup(void) -{ - early_platform_add_devices(sh7786_early_devices, - ARRAY_SIZE(sh7786_early_devices)); -} - enum { UNUSED = 0, /* interrupt sources */ - IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH, IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH, IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH, @@ -693,9 +670,12 @@ enum { Thermal, INTICI0, INTICI1, INTICI2, INTICI3, INTICI4, INTICI5, INTICI6, INTICI7, + + /* Muxed sub-events */ + TXI1, BRI1, RXI1, ERI1, }; -static struct intc_vect vectors[] __initdata = { +static struct intc_vect sh7786_vectors[] __initdata = { INTC_VECT(WDT, 0x3e0), INTC_VECT(TMU0_0, 0x400), INTC_VECT(TMU0_1, 0x420), INTC_VECT(TMU0_2, 0x440), INTC_VECT(TMU0_3, 0x460), @@ -761,7 +741,7 @@ static struct intc_vect vectors[] __initdata = { #define INT2DISTCR2 0xfe410908 #define INT2DISTCR3 0xfe41090c -static struct intc_mask_reg mask_registers[] __initdata = { +static struct intc_mask_reg sh7786_mask_registers[] __initdata = { { CnINTMSK0, CnINTMSKCLR0, 32, { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 }, INTC_SMP_BALANCING(INTDISTCR0) }, @@ -805,7 +785,7 @@ static struct intc_mask_reg mask_registers[] __initdata = { 0, 0, 0, 0, 0, 0, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR3) }, }; -static struct intc_prio_reg prio_registers[] __initdata = { +static struct intc_prio_reg sh7786_prio_registers[] __initdata = { { 0xfe410010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, { 0xfe410800, 0, 32, 8, /* INT2PRI0 */ { 0, 0, 0, WDT } }, @@ -849,11 +829,27 @@ static struct intc_prio_reg prio_registers[] __initdata = { INTICI3, INTICI2, INTICI1, INTICI0 }, INTC_SMP(4, 2) }, }; -static DECLARE_INTC_DESC(intc_desc, "sh7786", vectors, NULL, - mask_registers, prio_registers, NULL); +static struct intc_subgroup sh7786_subgroups[] __initdata = { + { 0xfe410c20, 32, SCIF1, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, TXI1, BRI1, RXI1, ERI1 } }, +}; -/* Support for external interrupt pins in IRQ mode */ +static struct intc_desc sh7786_intc_desc __initdata = { + .name = "sh7786", + .hw = { + .vectors = sh7786_vectors, + .nr_vectors = ARRAY_SIZE(sh7786_vectors), + .mask_regs = sh7786_mask_registers, + .nr_mask_regs = ARRAY_SIZE(sh7786_mask_registers), + .subgroups = sh7786_subgroups, + .nr_subgroups = ARRAY_SIZE(sh7786_subgroups), + .prio_regs = sh7786_prio_registers, + .nr_prio_regs = ARRAY_SIZE(sh7786_prio_registers), + }, +}; +/* Support for external interrupt pins in IRQ mode */ static struct intc_vect vectors_irq0123[] __initdata = { INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240), INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0), @@ -864,23 +860,25 @@ static struct intc_vect vectors_irq4567[] __initdata = { INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0), }; -static struct intc_sense_reg sense_registers[] __initdata = { +static struct intc_sense_reg sh7786_sense_registers[] __initdata = { { 0xfe41001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, }; -static struct intc_mask_reg ack_registers[] __initdata = { +static struct intc_mask_reg sh7786_ack_registers[] __initdata = { { 0xfe410024, 0, 32, /* INTREQ */ { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, }; static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7786-irq0123", - vectors_irq0123, NULL, mask_registers, - prio_registers, sense_registers, ack_registers); + vectors_irq0123, NULL, sh7786_mask_registers, + sh7786_prio_registers, sh7786_sense_registers, + sh7786_ack_registers); static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7786-irq4567", - vectors_irq4567, NULL, mask_registers, - prio_registers, sense_registers, ack_registers); + vectors_irq4567, NULL, sh7786_mask_registers, + sh7786_prio_registers, sh7786_sense_registers, + sh7786_ack_registers); /* External interrupt pins in IRL mode */ @@ -907,10 +905,10 @@ static struct intc_vect vectors_irl4567[] __initdata = { }; static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7786-irl0123", vectors_irl0123, - NULL, mask_registers, NULL, NULL); + NULL, sh7786_mask_registers, NULL, NULL); static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567, - NULL, mask_registers, NULL, NULL); + NULL, sh7786_mask_registers, NULL, NULL); #define INTC_ICR0 0xfe410000 #define INTC_INTMSK0 CnINTMSK0 @@ -931,7 +929,7 @@ void __init plat_irq_setup(void) /* select IRL mode for IRL3-0 + IRL7-4 */ __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); - register_intc_controller(&intc_desc); + register_intc_controller(&sh7786_intc_desc); } void __init plat_irq_setup_pins(int mode) @@ -975,3 +973,39 @@ void __init plat_irq_setup_pins(int mode) void __init plat_mem_setup(void) { } + +static int __init sh7786_devices_setup(void) +{ + int ret, irq; + + sh7786_usb_setup(); + + /* + * De-mux SCIF1 IRQs if possible + */ + irq = intc_irq_lookup(sh7786_intc_desc.name, TXI1); + if (irq > 0) { + scif1_platform_data.irqs[SCIx_TXI_IRQ] = irq; + scif1_platform_data.irqs[SCIx_ERI_IRQ] = + intc_irq_lookup(sh7786_intc_desc.name, ERI1); + scif1_platform_data.irqs[SCIx_BRI_IRQ] = + intc_irq_lookup(sh7786_intc_desc.name, BRI1); + scif1_platform_data.irqs[SCIx_RXI_IRQ] = + intc_irq_lookup(sh7786_intc_desc.name, RXI1); + } + + ret = platform_add_devices(sh7786_early_devices, + ARRAY_SIZE(sh7786_early_devices)); + if (unlikely(ret != 0)) + return ret; + + return platform_add_devices(sh7786_devices, + ARRAY_SIZE(sh7786_devices)); +} +arch_initcall(sh7786_devices_setup); + +void __init plat_early_device_setup(void) +{ + early_platform_add_devices(sh7786_early_devices, + ARRAY_SIZE(sh7786_early_devices)); +} -- cgit v1.1 From de5bbad6770882209b0ac58b0ba9259a98cfb953 Mon Sep 17 00:00:00 2001 From: Akinobu Mita Date: Wed, 6 Oct 2010 00:55:29 +0900 Subject: tile: replace some BUG_ON checks with BUILD_BUG_ON checks Some BUG_ON checks can be detected at compile time rather than at runtime. Signed-off-by: Akinobu Mita Signed-off-by: Chris Metcalf --- arch/tile/lib/atomic_32.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/tile/lib/atomic_32.c b/arch/tile/lib/atomic_32.c index 8040b42..7a5cc70 100644 --- a/arch/tile/lib/atomic_32.c +++ b/arch/tile/lib/atomic_32.c @@ -300,7 +300,7 @@ void __init __init_atomic_per_cpu(void) #else /* ATOMIC_LOCKS_FOUND_VIA_TABLE() */ /* Validate power-of-two and "bigger than cpus" assumption */ - BUG_ON(ATOMIC_HASH_SIZE & (ATOMIC_HASH_SIZE-1)); + BUILD_BUG_ON(ATOMIC_HASH_SIZE & (ATOMIC_HASH_SIZE-1)); BUG_ON(ATOMIC_HASH_SIZE < nr_cpu_ids); /* @@ -314,17 +314,17 @@ void __init __init_atomic_per_cpu(void) BUG_ON((unsigned long)atomic_locks % PAGE_SIZE != 0); /* The locks must all fit on one page. */ - BUG_ON(ATOMIC_HASH_SIZE * sizeof(int) > PAGE_SIZE); + BUILD_BUG_ON(ATOMIC_HASH_SIZE * sizeof(int) > PAGE_SIZE); /* * We use the page offset of the atomic value's address as * an index into atomic_locks, excluding the low 3 bits. * That should not produce more indices than ATOMIC_HASH_SIZE. */ - BUG_ON((PAGE_SIZE >> 3) > ATOMIC_HASH_SIZE); + BUILD_BUG_ON((PAGE_SIZE >> 3) > ATOMIC_HASH_SIZE); #endif /* ATOMIC_LOCKS_FOUND_VIA_TABLE() */ /* The futex code makes this assumption, so we validate it here. */ - BUG_ON(sizeof(atomic_t) != sizeof(int)); + BUILD_BUG_ON(sizeof(atomic_t) != sizeof(int)); } -- cgit v1.1 From 90173882ed15a8034d6d162da5f343a2c7d87587 Mon Sep 17 00:00:00 2001 From: Felipe Contreras Date: Mon, 4 Oct 2010 19:09:14 +0300 Subject: omap: add dsp platform device Otherwise tidspbridge cannot work. It looks like this was dropped in the conversion to staging. I took the liberty of doing some cleaning up. Signed-off-by: Felipe Contreras Acked-by: Tony Lindgren Signed-off-by: Greg Kroah-Hartman --- arch/arm/mach-omap2/Makefile | 4 ++ arch/arm/mach-omap2/dsp.c | 85 +++++++++++++++++++++++++++++++++++ arch/arm/plat-omap/common.c | 2 + arch/arm/plat-omap/devices.c | 30 +++++++++++++ arch/arm/plat-omap/include/plat/dsp.h | 31 +++++++++++++ 5 files changed, 152 insertions(+) create mode 100644 arch/arm/mach-omap2/dsp.c create mode 100644 arch/arm/plat-omap/include/plat/dsp.h (limited to 'arch') diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 88d3a1e..58288a4 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -102,6 +102,10 @@ obj-y += $(iommu-m) $(iommu-y) i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o obj-y += $(i2c-omap-m) $(i2c-omap-y) +ifneq ($(CONFIG_TIDSPBRIDGE),) +obj-y += dsp.o +endif + # Specific board support obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o diff --git a/arch/arm/mach-omap2/dsp.c b/arch/arm/mach-omap2/dsp.c new file mode 100644 index 0000000..6feeeae --- /dev/null +++ b/arch/arm/mach-omap2/dsp.c @@ -0,0 +1,85 @@ +/* + * TI's OMAP DSP platform device registration + * + * Copyright (C) 2005-2006 Texas Instruments, Inc. + * Copyright (C) 2009 Nokia Corporation + * + * Written by Hiroshi DOYU + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include "prm.h" +#include "cm.h" +#ifdef CONFIG_BRIDGE_DVFS +#include +#endif + +#include + +extern phys_addr_t omap_dsp_get_mempool_base(void); + +static struct platform_device *omap_dsp_pdev; + +static struct omap_dsp_platform_data omap_dsp_pdata __initdata = { +#ifdef CONFIG_BRIDGE_DVFS + .dsp_set_min_opp = omap_pm_dsp_set_min_opp, + .dsp_get_opp = omap_pm_dsp_get_opp, + .cpu_set_freq = omap_pm_cpu_set_freq, + .cpu_get_freq = omap_pm_cpu_get_freq, +#endif + .dsp_prm_read = prm_read_mod_reg, + .dsp_prm_write = prm_write_mod_reg, + .dsp_prm_rmw_bits = prm_rmw_mod_reg_bits, + .dsp_cm_read = cm_read_mod_reg, + .dsp_cm_write = cm_write_mod_reg, + .dsp_cm_rmw_bits = cm_rmw_mod_reg_bits, +}; + +static int __init omap_dsp_init(void) +{ + struct platform_device *pdev; + int err = -ENOMEM; + struct omap_dsp_platform_data *pdata = &omap_dsp_pdata; + + pdata->phys_mempool_base = omap_dsp_get_mempool_base(); + + if (pdata->phys_mempool_base) { + pdata->phys_mempool_size = CONFIG_TIDSPBRIDGE_MEMPOOL_SIZE; + pr_info("%s: %x bytes @ %x\n", __func__, + pdata->phys_mempool_size, pdata->phys_mempool_base); + } + + pdev = platform_device_alloc("omap-dsp", -1); + if (!pdev) + goto err_out; + + err = platform_device_add_data(pdev, pdata, sizeof(*pdata)); + if (err) + goto err_out; + + err = platform_device_add(pdev); + if (err) + goto err_out; + + omap_dsp_pdev = pdev; + return 0; + +err_out: + platform_device_put(pdev); + return err; +} +module_init(omap_dsp_init); + +static void __exit omap_dsp_exit(void) +{ + platform_device_unregister(omap_dsp_pdev); +} +module_exit(omap_dsp_exit); + +MODULE_AUTHOR("Hiroshi DOYU"); +MODULE_DESCRIPTION("TI's OMAP DSP platform device registration"); +MODULE_LICENSE("GPL"); diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c index 3008e71..57205a4 100644 --- a/arch/arm/plat-omap/common.c +++ b/arch/arm/plat-omap/common.c @@ -37,6 +37,7 @@ #include #include #include +#include #include @@ -87,6 +88,7 @@ void __init omap_reserve(void) { omapfb_reserve_sdram_memblock(); omap_vram_reserve_sdram_memblock(); + omap_dsp_reserve_sdram_memblock(); } /* diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c index d1920be..4c8f9b9 100644 --- a/arch/arm/plat-omap/devices.c +++ b/arch/arm/plat-omap/devices.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include @@ -272,6 +273,35 @@ static void omap_init_wdt(void) static inline void omap_init_wdt(void) {} #endif +#if defined(CONFIG_TIDSPBRIDGE) || defined(CONFIG_TIDSPBRIDGE_MODULE) + +static phys_addr_t omap_dsp_phys_mempool_base; + +void __init omap_dsp_reserve_sdram_memblock(void) +{ + phys_addr_t size = CONFIG_TIDSPBRIDGE_MEMPOOL_SIZE; + phys_addr_t paddr; + + if (!size) + return; + + paddr = __memblock_alloc_base(size, SZ_1M, MEMBLOCK_REAL_LIMIT); + if (!paddr) { + pr_err("%s: failed to reserve %x bytes\n", + __func__, size); + return; + } + + omap_dsp_phys_mempool_base = paddr; +} + +phys_addr_t omap_dsp_get_mempool_base(void) +{ + return omap_dsp_phys_mempool_base; +} +EXPORT_SYMBOL(omap_dsp_get_mempool_base); +#endif + /* * This gets called after board-specific INIT_MACHINE, and initializes most * on-chip peripherals accessible on this board (except for few like USB): diff --git a/arch/arm/plat-omap/include/plat/dsp.h b/arch/arm/plat-omap/include/plat/dsp.h new file mode 100644 index 0000000..9c604b3 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/dsp.h @@ -0,0 +1,31 @@ +#ifndef __OMAP_DSP_H__ +#define __OMAP_DSP_H__ + +#include + +struct omap_dsp_platform_data { + void (*dsp_set_min_opp) (u8 opp_id); + u8 (*dsp_get_opp) (void); + void (*cpu_set_freq) (unsigned long f); + unsigned long (*cpu_get_freq) (void); + unsigned long mpu_speed[6]; + + /* functions to write and read PRCM registers */ + void (*dsp_prm_write)(u32, s16 , u16); + u32 (*dsp_prm_read)(s16 , u16); + u32 (*dsp_prm_rmw_bits)(u32, u32, s16, s16); + void (*dsp_cm_write)(u32, s16 , u16); + u32 (*dsp_cm_read)(s16 , u16); + u32 (*dsp_cm_rmw_bits)(u32, u32, s16, s16); + + phys_addr_t phys_mempool_base; + phys_addr_t phys_mempool_size; +}; + +#if defined(CONFIG_TIDSPBRIDGE) || defined(CONFIG_TIDSPBRIDGE_MODULE) +extern void omap_dsp_reserve_sdram_memblock(void); +#else +static inline void omap_dsp_reserve_sdram_memblock(void) { } +#endif + +#endif -- cgit v1.1 From 1ec1e82f2510e2bdcb6268ed74aa79e1a7bc9594 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 30 Sep 2010 13:56:34 +0000 Subject: dmaengine: Add Freescale i.MX SDMA support This patch adds support for the Freescale i.MX SDMA engine. The SDMA engine is a scatter/gather DMA engine which is implemented as a seperate coprocessor. SDMA needs its own firmware which is requested using the standard request_firmware mechanism. The firmware has different entry points for each peripheral type, so drivers have to pass the peripheral type to the DMA engine which in turn picks the correct firmware entry point from a table contained in the firmware image itself. The original Freescale code also supports support for transfering data to the internal SRAM which needs different entry points to the firmware. Support for this is currently not implemented. Also, support for the ASRC (asymmetric sample rate converter) is skipped. I took a very simple approach to implement dmaengine support. Only a single descriptor is statically assigned to a each channel. This means that transfers can't be queued up but only a single transfer is in progress. This simplifies implementation a lot and is sufficient for the usual device/memory transfers. Signed-off-by: Sascha Hauer Reviewed-by: Linus Walleij Signed-off-by: Dan Williams --- arch/arm/mach-imx/include/mach/dma-v1.h | 8 +--- arch/arm/plat-mxc/include/mach/dma.h | 67 +++++++++++++++++++++++++++++++++ arch/arm/plat-mxc/include/mach/sdma.h | 17 +++++++++ 3 files changed, 86 insertions(+), 6 deletions(-) create mode 100644 arch/arm/plat-mxc/include/mach/dma.h create mode 100644 arch/arm/plat-mxc/include/mach/sdma.h (limited to 'arch') diff --git a/arch/arm/mach-imx/include/mach/dma-v1.h b/arch/arm/mach-imx/include/mach/dma-v1.h index 287431c..ac6fd71 100644 --- a/arch/arm/mach-imx/include/mach/dma-v1.h +++ b/arch/arm/mach-imx/include/mach/dma-v1.h @@ -27,6 +27,8 @@ #define imx_has_dma_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27()) +#include + #define IMX_DMA_CHANNELS 16 #define DMA_MODE_READ 0 @@ -96,12 +98,6 @@ int imx_dma_request(int channel, const char *name); void imx_dma_free(int channel); -enum imx_dma_prio { - DMA_PRIO_HIGH = 0, - DMA_PRIO_MEDIUM = 1, - DMA_PRIO_LOW = 2 -}; - int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio); #endif /* __MACH_DMA_V1_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/dma.h b/arch/arm/plat-mxc/include/mach/dma.h new file mode 100644 index 0000000..ef77515 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/dma.h @@ -0,0 +1,67 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MXC_DMA_H__ +#define __ASM_ARCH_MXC_DMA_H__ + +#include +#include +#include + +/* + * This enumerates peripheral types. Used for SDMA. + */ +enum sdma_peripheral_type { + IMX_DMATYPE_SSI, /* MCU domain SSI */ + IMX_DMATYPE_SSI_SP, /* Shared SSI */ + IMX_DMATYPE_MMC, /* MMC */ + IMX_DMATYPE_SDHC, /* SDHC */ + IMX_DMATYPE_UART, /* MCU domain UART */ + IMX_DMATYPE_UART_SP, /* Shared UART */ + IMX_DMATYPE_FIRI, /* FIRI */ + IMX_DMATYPE_CSPI, /* MCU domain CSPI */ + IMX_DMATYPE_CSPI_SP, /* Shared CSPI */ + IMX_DMATYPE_SIM, /* SIM */ + IMX_DMATYPE_ATA, /* ATA */ + IMX_DMATYPE_CCM, /* CCM */ + IMX_DMATYPE_EXT, /* External peripheral */ + IMX_DMATYPE_MSHC, /* Memory Stick Host Controller */ + IMX_DMATYPE_MSHC_SP, /* Shared Memory Stick Host Controller */ + IMX_DMATYPE_DSP, /* DSP */ + IMX_DMATYPE_MEMORY, /* Memory */ + IMX_DMATYPE_FIFO_MEMORY,/* FIFO type Memory */ + IMX_DMATYPE_SPDIF, /* SPDIF */ + IMX_DMATYPE_IPU_MEMORY, /* IPU Memory */ + IMX_DMATYPE_ASRC, /* ASRC */ + IMX_DMATYPE_ESAI, /* ESAI */ +}; + +enum imx_dma_prio { + DMA_PRIO_HIGH = 0, + DMA_PRIO_MEDIUM = 1, + DMA_PRIO_LOW = 2 +}; + +struct imx_dma_data { + int dma_request; /* DMA request line */ + enum sdma_peripheral_type peripheral_type; + int priority; +}; + +static inline int imx_dma_is_ipu(struct dma_chan *chan) +{ + return !strcmp(dev_name(chan->device->dev), "ipu-core"); +} + +static inline int imx_dma_is_general_purpose(struct dma_chan *chan) +{ + return !strcmp(dev_name(chan->device->dev), "imx-sdma") || + !strcmp(dev_name(chan->device->dev), "imx-dma"); +} + +#endif diff --git a/arch/arm/plat-mxc/include/mach/sdma.h b/arch/arm/plat-mxc/include/mach/sdma.h new file mode 100644 index 0000000..9be1122 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/sdma.h @@ -0,0 +1,17 @@ +#ifndef __MACH_MXC_SDMA_H__ +#define __MACH_MXC_SDMA_H__ + +/** + * struct sdma_platform_data - platform specific data for SDMA engine + * + * @sdma_version The version of this SDMA engine + * @cpu_name used to generate the firmware name + * @to_version CPU Tape out version + */ +struct sdma_platform_data { + int sdma_version; + char *cpu_name; + int to_version; +}; + +#endif /* __MACH_MXC_SDMA_H__ */ -- cgit v1.1 From bde40898c814362e8041cad0e989c7a749c417ec Mon Sep 17 00:00:00 2001 From: Akinobu Mita Date: Tue, 5 Oct 2010 15:54:00 +0000 Subject: sh: fix uninitialized spinlock The spinlock in traps_64.c is used without initialization. This fixes it by declaring DEFINE_SPINLOCK() and makes the spinlock static variable. Signed-off-by: Akinobu Mita Cc: Paul Mundt Cc: linux-sh@vger.kernel.org Signed-off-by: Paul Mundt --- arch/sh/kernel/traps_64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/sh/kernel/traps_64.c b/arch/sh/kernel/traps_64.c index e67e140..fda6355 100644 --- a/arch/sh/kernel/traps_64.c +++ b/arch/sh/kernel/traps_64.c @@ -50,7 +50,7 @@ asmlinkage void do_##name(unsigned long error_code, struct pt_regs *regs) \ do_unhandled_exception(trapnr, signr, str, __stringify(name), error_code, regs, current); \ } -spinlock_t die_lock; +static DEFINE_SPINLOCK(die_lock); void die(const char * str, struct pt_regs * regs, long err) { -- cgit v1.1 From 901c28c257eb8903a7d66c900df163e2c13ca995 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Tue, 5 Oct 2010 08:16:08 +0000 Subject: sh: Fix address calculation of Initrd Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Paul Mundt --- arch/sh/kernel/setup.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c index f24d0ea..4e27846 100644 --- a/arch/sh/kernel/setup.c +++ b/arch/sh/kernel/setup.c @@ -135,8 +135,9 @@ void __init check_for_initrd(void) goto disable; } - if (unlikely(start < PAGE_OFFSET)) { - pr_err("initrd start < PAGE_OFFSET\n"); + if (unlikely(start < __MEMORY_START)) { + pr_err("initrd start (%08lx) < __MEMORY_START(%x)\n", + start, __MEMORY_START); goto disable; } @@ -157,7 +158,7 @@ void __init check_for_initrd(void) /* * Address sanitization */ - initrd_start = (unsigned long)__va(__pa(start)); + initrd_start = (unsigned long)__va(start); initrd_end = initrd_start + INITRD_SIZE; memblock_reserve(__pa(initrd_start), INITRD_SIZE); -- cgit v1.1 From 46f12936fd2945ffaf774e728fe5044f06ed5574 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Sun, 3 Oct 2010 04:24:42 +0000 Subject: sh: fix an ms7724se compile breakage Fix a compile breakage, caused by my own careless copy-paste. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Paul Mundt --- arch/sh/boards/mach-se/7724/setup.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) (limited to 'arch') diff --git a/arch/sh/boards/mach-se/7724/setup.c b/arch/sh/boards/mach-se/7724/setup.c index 3099c36..fe208d6 100644 --- a/arch/sh/boards/mach-se/7724/setup.c +++ b/arch/sh/boards/mach-se/7724/setup.c @@ -148,14 +148,14 @@ const static struct fb_videomode lcdc_720p_modes[] = { { .name = "LB070WV1", .sync = 0, /* hsync and vsync are active low */ - .xres = 1280; - .yres = 720; - .left_margin = 220; - .right_margin = 110; - .hsync_len = 40; - .upper_margin = 20; - .lower_margin = 5; - .vsync_len = 5; + .xres = 1280, + .yres = 720, + .left_margin = 220, + .right_margin = 110, + .hsync_len = 40, + .upper_margin = 20, + .lower_margin = 5, + .vsync_len = 5, }, }; @@ -163,14 +163,14 @@ const static struct fb_videomode lcdc_vga_modes[] = { { .name = "LB070WV1", .sync = 0, /* hsync and vsync are active low */ - .xres = 640; - .yres = 480; - .left_margin = 105; - .right_margin = 50; - .hsync_len = 96; - .upper_margin = 33; - .lower_margin = 10; - .vsync_len = 2; + .xres = 640, + .yres = 480, + .left_margin = 105, + .right_margin = 50, + .hsync_len = 96, + .upper_margin = 33, + .lower_margin = 10, + .vsync_len = 2, }, }; -- cgit v1.1 From 532daaa1108390c5c0070ab6d32bd20b53ee4e41 Mon Sep 17 00:00:00 2001 From: Nicolas Kaiser Date: Mon, 4 Oct 2010 10:39:29 +0000 Subject: arm/shmobile: remove duplicated include Remove duplicated include. Signed-off-by: Nicolas Kaiser Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/board-ap4evb.c | 1 - 1 file changed, 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c index 3dd76f0..943cc21 100644 --- a/arch/arm/mach-shmobile/board-ap4evb.c +++ b/arch/arm/mach-shmobile/board-ap4evb.c @@ -30,7 +30,6 @@ #include #include #include -#include #include #include #include -- cgit v1.1 From 06c7a489a97fce99fd86611f6f32e565e686e5d8 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Thu, 7 Oct 2010 02:57:39 +0900 Subject: sh: Fix up the SH-3 build. SH-3 lacks an MMUCR_TI definition for global TLB flushes. As SH-3 parts lack a split TLB, the same global flush behaviour is accomplished through the flush bit, which just happens to be the same as on SH-4. This fixes up the build for all SH-3 MMU parts. Signed-off-by: Paul Mundt --- arch/sh/include/cpu-sh3/cpu/mmu_context.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/sh/include/cpu-sh3/cpu/mmu_context.h b/arch/sh/include/cpu-sh3/cpu/mmu_context.h index ab09da7..0c7c735 100644 --- a/arch/sh/include/cpu-sh3/cpu/mmu_context.h +++ b/arch/sh/include/cpu-sh3/cpu/mmu_context.h @@ -16,6 +16,7 @@ #define MMU_TEA 0xFFFFFFFC /* TLB Exception Address */ #define MMUCR 0xFFFFFFE0 /* MMU Control Register */ +#define MMUCR_TI (1 << 2) /* TLB flush bit */ #define MMU_TLB_ADDRESS_ARRAY 0xF2000000 #define MMU_PAGE_ASSOC_BIT 0x80 -- cgit v1.1 From 968f19ae802fdc6b6b6b5af6fe79cf23d281be0f Mon Sep 17 00:00:00 2001 From: Ira Snyder Date: Thu, 30 Sep 2010 11:46:46 +0000 Subject: fsldma: improved DMA_SLAVE support Now that the generic DMAEngine API has support for scatterlist to scatterlist copying, the device_prep_slave_sg() portion of the DMA_SLAVE API is no longer necessary and has been removed. However, the device_control() portion of the DMA_SLAVE API is still useful to control device specific parameters, such as externally controlled DMA transfers and maximum burst length. A special dma_ctrl_cmd has been added to enable externally controlled DMA transfers. This is currently specific to the Freescale DMA controller, but can easily be made generic when another user is found. Signed-off-by: Ira W. Snyder Signed-off-by: Dan Williams --- arch/powerpc/include/asm/fsldma.h | 137 -------------------------------------- 1 file changed, 137 deletions(-) delete mode 100644 arch/powerpc/include/asm/fsldma.h (limited to 'arch') diff --git a/arch/powerpc/include/asm/fsldma.h b/arch/powerpc/include/asm/fsldma.h deleted file mode 100644 index debc5ed..0000000 --- a/arch/powerpc/include/asm/fsldma.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - * Freescale MPC83XX / MPC85XX DMA Controller - * - * Copyright (c) 2009 Ira W. Snyder - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#ifndef __ARCH_POWERPC_ASM_FSLDMA_H__ -#define __ARCH_POWERPC_ASM_FSLDMA_H__ - -#include -#include - -/* - * Definitions for the Freescale DMA controller's DMA_SLAVE implemention - * - * The Freescale DMA_SLAVE implementation was designed to handle many-to-many - * transfers. An example usage would be an accelerated copy between two - * scatterlists. Another example use would be an accelerated copy from - * multiple non-contiguous device buffers into a single scatterlist. - * - * A DMA_SLAVE transaction is defined by a struct fsl_dma_slave. This - * structure contains a list of hardware addresses that should be copied - * to/from the scatterlist passed into device_prep_slave_sg(). The structure - * also has some fields to enable hardware-specific features. - */ - -/** - * struct fsl_dma_hw_addr - * @entry: linked list entry - * @address: the hardware address - * @length: length to transfer - * - * Holds a single physical hardware address / length pair for use - * with the DMAEngine DMA_SLAVE API. - */ -struct fsl_dma_hw_addr { - struct list_head entry; - - dma_addr_t address; - size_t length; -}; - -/** - * struct fsl_dma_slave - * @addresses: a linked list of struct fsl_dma_hw_addr structures - * @request_count: value for DMA request count - * @src_loop_size: setup and enable constant source-address DMA transfers - * @dst_loop_size: setup and enable constant destination address DMA transfers - * @external_start: enable externally started DMA transfers - * @external_pause: enable externally paused DMA transfers - * - * Holds a list of address / length pairs for use with the DMAEngine - * DMA_SLAVE API implementation for the Freescale DMA controller. - */ -struct fsl_dma_slave { - - /* List of hardware address/length pairs */ - struct list_head addresses; - - /* Support for extra controller features */ - unsigned int request_count; - unsigned int src_loop_size; - unsigned int dst_loop_size; - bool external_start; - bool external_pause; -}; - -/** - * fsl_dma_slave_append - add an address/length pair to a struct fsl_dma_slave - * @slave: the &struct fsl_dma_slave to add to - * @address: the hardware address to add - * @length: the length of bytes to transfer from @address - * - * Add a hardware address/length pair to a struct fsl_dma_slave. Returns 0 on - * success, -ERRNO otherwise. - */ -static inline int fsl_dma_slave_append(struct fsl_dma_slave *slave, - dma_addr_t address, size_t length) -{ - struct fsl_dma_hw_addr *addr; - - addr = kzalloc(sizeof(*addr), GFP_ATOMIC); - if (!addr) - return -ENOMEM; - - INIT_LIST_HEAD(&addr->entry); - addr->address = address; - addr->length = length; - - list_add_tail(&addr->entry, &slave->addresses); - return 0; -} - -/** - * fsl_dma_slave_free - free a struct fsl_dma_slave - * @slave: the struct fsl_dma_slave to free - * - * Free a struct fsl_dma_slave and all associated address/length pairs - */ -static inline void fsl_dma_slave_free(struct fsl_dma_slave *slave) -{ - struct fsl_dma_hw_addr *addr, *tmp; - - if (slave) { - list_for_each_entry_safe(addr, tmp, &slave->addresses, entry) { - list_del(&addr->entry); - kfree(addr); - } - - kfree(slave); - } -} - -/** - * fsl_dma_slave_alloc - allocate a struct fsl_dma_slave - * @gfp: the flags to pass to kmalloc when allocating this structure - * - * Allocate a struct fsl_dma_slave for use by the DMA_SLAVE API. Returns a new - * struct fsl_dma_slave on success, or NULL on failure. - */ -static inline struct fsl_dma_slave *fsl_dma_slave_alloc(gfp_t gfp) -{ - struct fsl_dma_slave *slave; - - slave = kzalloc(sizeof(*slave), gfp); - if (!slave) - return NULL; - - INIT_LIST_HEAD(&slave->addresses); - return slave; -} - -#endif /* __ARCH_POWERPC_ASM_FSLDMA_H__ */ -- cgit v1.1 From 661385f9c34e15c2f2c57b80e8cb2c7b910fdbd3 Mon Sep 17 00:00:00 2001 From: Per Forlin Date: Wed, 6 Oct 2010 09:05:28 +0000 Subject: DMAENGINE: Remove stedma40_set_psize and pre_transfer hook in ste_dma40 Remove obsolete pre_transfer hook in stedma40_chan_cfg. The intent of this hook is merely to handle burst size compensation for ux500 variant MMCI. Remove obsolete stedma40_set_psize since it is only called from pre_transfer. DMAEngine device_control replaces the functionality of stedma40_set_psize. Signed-off-by: Per Forlin Signed-off-by: Dan Williams --- arch/arm/plat-nomadik/include/plat/ste_dma40.h | 24 +----------------------- 1 file changed, 1 insertion(+), 23 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-nomadik/include/plat/ste_dma40.h b/arch/arm/plat-nomadik/include/plat/ste_dma40.h index 1127af2..660552d 100644 --- a/arch/arm/plat-nomadik/include/plat/ste_dma40.h +++ b/arch/arm/plat-nomadik/include/plat/ste_dma40.h @@ -1,6 +1,6 @@ /* * Copyright (C) ST-Ericsson SA 2007-2010 - * Author: Per Friden for ST-Ericsson + * Author: Per Forlin for ST-Ericsson * Author: Jonas Aaberg for ST-Ericsson * License terms: GNU General Public License (GPL) version 2 */ @@ -123,10 +123,6 @@ struct stedma40_half_channel_info { * @dst_dev_type: Dst device type * @src_info: Parameters for dst half channel * @dst_info: Parameters for dst half channel - * @pre_transfer_data: Data to be passed on to the pre_transfer() function. - * @pre_transfer: Callback used if needed before preparation of transfer. - * Only called if device is set. size of bytes to transfer - * (in case of multiple element transfer size is size of the first element). * * * This structure has to be filled by the client drivers. @@ -140,10 +136,6 @@ struct stedma40_chan_cfg { int dst_dev_type; struct stedma40_half_channel_info src_info; struct stedma40_half_channel_info dst_info; - void *pre_transfer_data; - int (*pre_transfer) (struct dma_chan *chan, - void *data, - int size); }; /** @@ -171,20 +163,6 @@ struct stedma40_platform_data { }; /** - * setdma40_set_psize() - Used for changing the package size of an - * already configured dma channel. - * - * @chan: dmaengine handle - * @src_psize: new package side for src. (STEDMA40_PSIZE*) - * @src_psize: new package side for dst. (STEDMA40_PSIZE*) - * - * returns 0 on ok, otherwise negative error number. - */ -int stedma40_set_psize(struct dma_chan *chan, - int src_psize, - int dst_psize); - -/** * stedma40_filter() - Provides stedma40_chan_cfg to the * ste_dma40 dma driver via the dmaengine framework. * does some checking of what's provided. -- cgit v1.1 From 9646b7985e906e5fcea9375f016b4519c8318c21 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 6 Oct 2010 09:05:29 +0000 Subject: DMAENGINE: define a dummy filter function for ste_dma40 All platform data has to be made conditional on CONFIG_STEDMA40 or we can provide a simple dummy filter functions as to avoid cluttering the code with other #ifdef:s. Signed-off-by: Linus Walleij Signed-off-by: Dan Williams --- arch/arm/plat-nomadik/include/plat/ste_dma40.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'arch') diff --git a/arch/arm/plat-nomadik/include/plat/ste_dma40.h b/arch/arm/plat-nomadik/include/plat/ste_dma40.h index 660552d..3dd4255 100644 --- a/arch/arm/plat-nomadik/include/plat/ste_dma40.h +++ b/arch/arm/plat-nomadik/include/plat/ste_dma40.h @@ -162,6 +162,8 @@ struct stedma40_platform_data { int disabled_channels[STEDMA40_MAX_PHYS]; }; +#ifdef CONFIG_STE_DMA40 + /** * stedma40_filter() - Provides stedma40_chan_cfg to the * ste_dma40 dma driver via the dmaengine framework. @@ -223,4 +225,21 @@ dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan, direction, flags); } +#else +static inline bool stedma40_filter(struct dma_chan *chan, void *data) +{ + return false; +} + +static inline struct +dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan, + dma_addr_t addr, + unsigned int size, + enum dma_data_direction direction, + unsigned long flags) +{ + return NULL; +} +#endif + #endif -- cgit v1.1 From f14362d1fe81cece6f1d78483e5bbfcf8cc497bf Mon Sep 17 00:00:00 2001 From: Ian Munsie Date: Fri, 1 Oct 2010 17:06:07 +1000 Subject: powerpc, of_serial: Endianness issues setting up the serial ports The speed and clock of the serial ports is retrieved from the device tree in both the PowerPC legacy serial code and the Open Firmware serial driver, therefore they need to handle the fact that the device tree is always big endian, while the CPU may not be. Also fix other device tree references in the legacy serial code. Signed-off-by: Ian Munsie Signed-off-by: Grant Likely --- arch/powerpc/kernel/legacy_serial.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/kernel/legacy_serial.c b/arch/powerpc/kernel/legacy_serial.c index c1fd0f9..c834757 100644 --- a/arch/powerpc/kernel/legacy_serial.c +++ b/arch/powerpc/kernel/legacy_serial.c @@ -52,14 +52,14 @@ static int __init add_legacy_port(struct device_node *np, int want_index, phys_addr_t taddr, unsigned long irq, upf_t flags, int irq_check_parent) { - const u32 *clk, *spd; + const __be32 *clk, *spd; u32 clock = BASE_BAUD * 16; int index; /* get clock freq. if present */ clk = of_get_property(np, "clock-frequency", NULL); if (clk && *clk) - clock = *clk; + clock = be32_to_cpup(clk); /* get default speed if present */ spd = of_get_property(np, "current-speed", NULL); @@ -109,7 +109,7 @@ static int __init add_legacy_port(struct device_node *np, int want_index, legacy_serial_infos[index].taddr = taddr; legacy_serial_infos[index].np = of_node_get(np); legacy_serial_infos[index].clock = clock; - legacy_serial_infos[index].speed = spd ? *spd : 0; + legacy_serial_infos[index].speed = spd ? be32_to_cpup(spd) : 0; legacy_serial_infos[index].irq_check_parent = irq_check_parent; printk(KERN_DEBUG "Found legacy serial port %d for %s\n", @@ -168,7 +168,7 @@ static int __init add_legacy_soc_port(struct device_node *np, static int __init add_legacy_isa_port(struct device_node *np, struct device_node *isa_brg) { - const u32 *reg; + const __be32 *reg; const char *typep; int index = -1; u64 taddr; @@ -181,7 +181,7 @@ static int __init add_legacy_isa_port(struct device_node *np, return -1; /* Verify it's an IO port, we don't support anything else */ - if (!(reg[0] & 0x00000001)) + if (!(be32_to_cpu(reg[0]) & 0x00000001)) return -1; /* Now look for an "ibm,aix-loc" property that gives us ordering @@ -202,7 +202,7 @@ static int __init add_legacy_isa_port(struct device_node *np, taddr = 0; /* Add port, irq will be dealt with later */ - return add_legacy_port(np, index, UPIO_PORT, reg[1], taddr, + return add_legacy_port(np, index, UPIO_PORT, be32_to_cpu(reg[1]), taddr, NO_IRQ, UPF_BOOT_AUTOCONF, 0); } @@ -251,9 +251,9 @@ static int __init add_legacy_pci_port(struct device_node *np, * we get to their "reg" property */ if (np != pci_dev) { - const u32 *reg = of_get_property(np, "reg", NULL); - if (reg && (*reg < 4)) - index = lindex = *reg; + const __be32 *reg = of_get_property(np, "reg", NULL); + if (reg && (be32_to_cpup(reg) < 4)) + index = lindex = be32_to_cpup(reg); } /* Local index means it's the Nth port in the PCI chip. Unfortunately @@ -507,7 +507,7 @@ static int __init check_legacy_serial_console(void) struct device_node *prom_stdout = NULL; int i, speed = 0, offset = 0; const char *name; - const u32 *spd; + const __be32 *spd; DBG(" -> check_legacy_serial_console()\n"); @@ -547,7 +547,7 @@ static int __init check_legacy_serial_console(void) } spd = of_get_property(prom_stdout, "current-speed", NULL); if (spd) - speed = *spd; + speed = be32_to_cpup(spd); if (strcmp(name, "serial") != 0) goto not_found; -- cgit v1.1 From 68f4d5a00adaab33b136fce2c72d5c377b39b0b0 Mon Sep 17 00:00:00 2001 From: Zhao Yakui Date: Fri, 8 Oct 2010 09:47:33 +0800 Subject: x86, setup: Use string copy operation to optimze copy in kernel compression The kernel decompression code parses the ELF header and then copies the segment to the corresponding destination. Currently it uses slow byte-copy code. This patch makes it use the string copy operations instead. In the test the copy performance can be improved very significantly after using the string copy operation mechanism. 1. The copy time can be reduced from 150ms to 20ms on one Atom machine 2. The copy time can be reduced about 80% on another machine The time is reduced from 7ms to 1.5ms when using 32-bit kernel. The time is reduced from 10ms to 2ms when using 64-bit kernel. Signed-off-by: Zhao Yakui LKML-Reference: <1286502453-7043-1-git-send-email-yakui.zhao@intel.com> Signed-off-by: H. Peter Anvin --- arch/x86/boot/compressed/misc.c | 29 +++++++++++++++++++++++------ 1 file changed, 23 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/x86/boot/compressed/misc.c b/arch/x86/boot/compressed/misc.c index 8f7bef8..23f315c 100644 --- a/arch/x86/boot/compressed/misc.c +++ b/arch/x86/boot/compressed/misc.c @@ -229,18 +229,35 @@ void *memset(void *s, int c, size_t n) ss[i] = c; return s; } - +#ifdef CONFIG_X86_32 void *memcpy(void *dest, const void *src, size_t n) { - int i; - const char *s = src; - char *d = dest; + int d0, d1, d2; + asm volatile( + "rep ; movsl\n\t" + "movl %4,%%ecx\n\t" + "rep ; movsb\n\t" + : "=&c" (d0), "=&D" (d1), "=&S" (d2) + : "0" (n >> 2), "g" (n & 3), "1" (dest), "2" (src) + : "memory"); - for (i = 0; i < n; i++) - d[i] = s[i]; return dest; } +#else +void *memcpy(void *dest, const void *src, size_t n) +{ + long d0, d1, d2; + asm volatile( + "rep ; movsq\n\t" + "movq %4,%%rcx\n\t" + "rep ; movsb\n\t" + : "=&c" (d0), "=&D" (d1), "=&S" (d2) + : "0" (n >> 3), "g" (n & 7), "1" (dest), "2" (src) + : "memory"); + return dest; +} +#endif static void error(char *x) { -- cgit v1.1 From f672b49b07a4a152fc4251f2aec6b4d05164c4cd Mon Sep 17 00:00:00 2001 From: Andi Kleen Date: Mon, 27 Sep 2010 22:05:55 +0200 Subject: x86: HWPOISON: Report correct address granuality for huge hwpoison faults An earlier patch fixed the hwpoison fault handling to encode the huge page size in the fault code of the page fault handler. This is needed to report this information in SIGBUS to user space. This is a straight forward patch to pass this information through to the signal handling in the x86 specific fault.c Cc: x86@kernel.org Cc: Naoya Horiguchi Cc: fengguang.wu@intel.com Signed-off-by: Andi Kleen --- arch/x86/mm/fault.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c index 4c4508e..1d15a27 100644 --- a/arch/x86/mm/fault.c +++ b/arch/x86/mm/fault.c @@ -11,6 +11,7 @@ #include /* __kprobes, ... */ #include /* kmmio_handler, ... */ #include /* perf_sw_event */ +#include /* hstate_index_to_shift */ #include /* dotraplinkage, ... */ #include /* pgd_*(), ... */ @@ -160,15 +161,20 @@ is_prefetch(struct pt_regs *regs, unsigned long error_code, unsigned long addr) static void force_sig_info_fault(int si_signo, int si_code, unsigned long address, - struct task_struct *tsk) + struct task_struct *tsk, int fault) { + unsigned lsb = 0; siginfo_t info; info.si_signo = si_signo; info.si_errno = 0; info.si_code = si_code; info.si_addr = (void __user *)address; - info.si_addr_lsb = si_code == BUS_MCEERR_AR ? PAGE_SHIFT : 0; + if (fault & VM_FAULT_HWPOISON_LARGE) + lsb = hstate_index_to_shift(VM_FAULT_GET_HINDEX(fault)); + if (fault & VM_FAULT_HWPOISON) + lsb = PAGE_SHIFT; + info.si_addr_lsb = lsb; force_sig_info(si_signo, &info, tsk); } @@ -731,7 +737,7 @@ __bad_area_nosemaphore(struct pt_regs *regs, unsigned long error_code, tsk->thread.error_code = error_code | (address >= TASK_SIZE); tsk->thread.trap_no = 14; - force_sig_info_fault(SIGSEGV, si_code, address, tsk); + force_sig_info_fault(SIGSEGV, si_code, address, tsk, 0); return; } @@ -816,14 +822,14 @@ do_sigbus(struct pt_regs *regs, unsigned long error_code, unsigned long address, tsk->thread.trap_no = 14; #ifdef CONFIG_MEMORY_FAILURE - if (fault & VM_FAULT_HWPOISON) { + if (fault & (VM_FAULT_HWPOISON|VM_FAULT_HWPOISON_LARGE)) { printk(KERN_ERR "MCE: Killing %s:%d due to hardware memory corruption fault at %lx\n", tsk->comm, tsk->pid, address); code = BUS_MCEERR_AR; } #endif - force_sig_info_fault(SIGBUS, code, address, tsk); + force_sig_info_fault(SIGBUS, code, address, tsk, fault); } static noinline void @@ -833,7 +839,8 @@ mm_fault_error(struct pt_regs *regs, unsigned long error_code, if (fault & VM_FAULT_OOM) { out_of_memory(regs, error_code, address); } else { - if (fault & (VM_FAULT_SIGBUS|VM_FAULT_HWPOISON)) + if (fault & (VM_FAULT_SIGBUS|VM_FAULT_HWPOISON| + VM_FAULT_HWPOISON_LARGE)) do_sigbus(regs, error_code, address, fault); else BUG(); -- cgit v1.1 From 4d63bc1de704c6f413979261bf42781cf364eb14 Mon Sep 17 00:00:00 2001 From: Manjunath Kondaiah G Date: Fri, 8 Oct 2010 09:56:11 -0700 Subject: OMAP: mach-omap2: Fix incorrect assignment warnings This patch fixes below sparse warnings for incorrect assignments. arch/arm/mach-omap2/control.c:195:16: warning: incorrect type in assignment (different address spaces) arch/arm/mach-omap2/control.c:195:16: expected unsigned int [usertype] *v_addr arch/arm/mach-omap2/control.c:195:16: got void [noderef] * arch/arm/mach-omap2/control.c:199:25: warning: incorrect type in argument 1 (different address spaces) arch/arm/mach-omap2/control.c:199:25: expected void const volatile [noderef] * arch/arm/mach-omap2/control.c:199:25: got unsigned int [usertype] * arch/arm/mach-omap2/control.c:320:28: warning: incorrect type in assignment (different address spaces) arch/arm/mach-omap2/control.c:320:28: expected void *[noderef] scratchpad_address arch/arm/mach-omap2/control.c:320:28: got void [noderef] * arch/arm/mach-omap2/control.c:321:9: warning: incorrect type in argument 1 (different address spaces) arch/arm/mach-omap2/control.c:321:9: expected void volatile [noderef] * arch/arm/mach-omap2/control.c:321:9: got void *[noderef] scratchpad_address arch/arm/mach-omap2/control.c:324:9: warning: incorrect type in argument 1 (different address spaces) arch/arm/mach-omap2/control.c:324:9: expected void volatile [noderef] * arch/arm/mach-omap2/control.c:324:9: got void * arch/arm/mach-omap2/control.c:327:9: warning: incorrect type in argument 1 (different address spaces) arch/arm/mach-omap2/control.c:327:9: expected void volatile [noderef] * arch/arm/mach-omap2/control.c:327:9: got void * arch/arm/mach-omap2/control.c:334:9: warning: incorrect type in argument 1 (different address spaces) arch/arm/mach-omap2/control.c:334:9: expected void volatile [noderef] * arch/arm/mach-omap2/control.c:334:9: got void * arch/arm/mach-omap2/control.c:321:9: warning: dereference of noderef expression arch/arm/mach-omap2/control.c:324:9: warning: dereference of noderef expression arch/arm/mach-omap2/control.c:327:9: warning: dereference of noderef expression arch/arm/mach-omap2/control.c:334:9: warning: dereference of noderef expression arch/arm/mach-omap2/pm34xx.c:323:28: warning: incorrect type in assignment (different address spaces) arch/arm/mach-omap2/pm34xx.c:323:28: expected unsigned int [usertype] *scratchpad_address arch/arm/mach-omap2/pm34xx.c:323:28: got void [noderef] * arch/arm/mach-omap2/pm34xx.c:326:26: warning: incorrect type in argument 1 (different address spaces) arch/arm/mach-omap2/pm34xx.c:326:26: expected void const volatile [noderef] * arch/arm/mach-omap2/pm34xx.c:326:26: got unsigned int [usertype] * arch/arm/mach-omap2/pm34xx.c:329:26: warning: incorrect type in argument 1 (different address spaces) arch/arm/mach-omap2/pm34xx.c:329:26: expected void const volatile [noderef] * arch/arm/mach-omap2/pm34xx.c:329:26: got unsigned int [usertype] * arch/arm/mach-omap2/pm34xx.c:334:29: warning: incorrect type in argument 1 (different address spaces) arch/arm/mach-omap2/pm34xx.c:334:29: expected void const volatile [noderef] * arch/arm/mach-omap2/pm34xx.c:334:29: got unsigned int [usertype] * Signed-off-by: Manjunath Kondaiah G Cc: linux-arm-kernel@lists.infradead.org Cc: Nishanth Menon Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/control.c | 4 ++-- arch/arm/mach-omap2/pm34xx.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index 8b3c469..d21faba 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -215,7 +215,7 @@ void omap4_ctrl_pad_writel(u32 val, u16 offset) void omap3_clear_scratchpad_contents(void) { u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET; - u32 *v_addr; + void __iomem *v_addr; u32 offset = 0; v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM); if (prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) & @@ -231,7 +231,7 @@ void omap3_clear_scratchpad_contents(void) /* Populate the scratchpad structure with restore structure */ void omap3_save_scratchpad_contents(void) { - void * __iomem scratchpad_address; + void __iomem *scratchpad_address; u32 arm_context_addr; struct omap3_scratchpad scratchpad_contents; struct omap3_scratchpad_prcm_block prcm_block_contents; diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index d2b940c..ac572aa 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -310,7 +310,7 @@ static void restore_control_register(u32 val) /* Function to restore the table entry that was modified for enabling MMU */ static void restore_table_entry(void) { - u32 *scratchpad_address; + void __iomem *scratchpad_address; u32 previous_value, control_reg_value; u32 *address; -- cgit v1.1 From 38815733972655ee3cbfc34e254c403c332693c3 Mon Sep 17 00:00:00 2001 From: Manjunath Kondaiah G Date: Fri, 8 Oct 2010 09:56:37 -0700 Subject: OMAP: mach-omap2: Fix static declaration warnings This patch fixes sparse warnings due to non declaration of static structures and variables. Sparse warning logs fixed: arch/arm/mach-omap2/control.c:88:6: warning: symbol 'omap3_secure_ram_storage' was not declared. Should it be static? n arch/arm/mach-omap2/timer-gp.c:50:22: warning: symbol 'gptimer_wakeup' was not declared. Should it be static? arch/arm/mach-omap2/timer-gp.c:240:18: warning: symbol 'omap_timer' was not declared. Should it be static? arch/arm/mach-omap2/prcm.c:121:24: warning: symbol 'prcm_context' was not declared. Should it be static? arch/arm/mach-omap2/mux2420.c:510:29: warning: symbol 'omap2420_pop_ball' was not declared. Should it be static? arch/arm/mach-omap2/mux2430.c:589:29: warning: symbol 'omap2430_pop_ball' was not declared. Should it be static? arch/arm/mach-omap2/mux34xx.c:934:28: warning: symbol 'omap3_cus_subset' was not declared. Should it be static? arch/arm/mach-omap2/mux34xx.c:1080:29: warning: symbol 'omap3_cus_ball' was not declared. Should it be static? arch/arm/mach-omap2/mux34xx.c:1272:28: warning: symbol 'omap3_cbb_subset' was not declared. Should it be static? arch/arm/mach-omap2/mux34xx.c:1393:29: warning: symbol 'omap3_cbb_ball' was not declared. Should it be static? arch/arm/mach-omap2/mux34xx.c:1603:28: warning: symbol 'omap36xx_cbp_subset' was not declared. Should it be static? arch/arm/mach-omap2/mux34xx.c:1821:29: warning: symbol 'omap36xx_cbp_ball' was not declared. Should it be static? arch/arm/mach-omap2/pm-debug.c:165:15: warning: symbol 'pm_dbg_dir' was not declared. Should it be static? arch/arm/mach-omap2/board-omap3evm.c:587:30: warning: symbol 'ads7846_config' was not declared. Should it be static? arch/arm/mach-omap2/board-omap3evm.c:606:23: warning: symbol 'omap3evm_spi_board_info' was not declared. Should it be static? arch/arm/mach-omap2/board-rx51-sdram.c:46:25: warning: symbol 'rx51_sdrc_params' was not declared. Should it be static? arch/arm/mach-omap2/board-rx51-sdram.c:211:25: warning: symbol 'rx51_get_sdram_timings' was not declared. Should it be static? arch/arm/mach-omap2/board-omap3touchbook.c:64:15: warning: symbol 'touchbook_revision' was not declared. Should it be static? arch/arm/mach-omap2/board-am3517evm.c:350:24: warning: symbol 'am3517_evm_dss_device' was not declared. Should it be static? arch/arm/mach-omap2/board-omap3stalker.c:567:23: warning: symbol 'omap3stalker_spi_board_info' was not declared. Should it be static? Signed-off-by: Manjunath Kondaiah G Cc: linux-arm-kernel@lists.infradead.org Cc: Nishanth Menon Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-am3517evm.c | 2 +- arch/arm/mach-omap2/board-omap3evm.c | 4 ++-- arch/arm/mach-omap2/board-omap3stalker.c | 2 +- arch/arm/mach-omap2/board-omap3touchbook.c | 2 +- arch/arm/mach-omap2/board-rx51-sdram.c | 2 +- arch/arm/mach-omap2/control.c | 1 + arch/arm/mach-omap2/mux2420.c | 2 +- arch/arm/mach-omap2/mux2430.c | 2 +- arch/arm/mach-omap2/mux34xx.c | 12 ++++++------ arch/arm/mach-omap2/pm-debug.c | 2 +- arch/arm/mach-omap2/prcm.c | 2 +- arch/arm/plat-omap/include/plat/dmtimer.h | 2 ++ arch/arm/plat-omap/include/plat/sdrc.h | 1 + 13 files changed, 20 insertions(+), 16 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index 4d0f585..197289b 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c @@ -347,7 +347,7 @@ static struct omap_dss_board_info am3517_evm_dss_data = { .default_device = &am3517_evm_lcd_device, }; -struct platform_device am3517_evm_dss_device = { +static struct platform_device am3517_evm_dss_device = { .name = "omapdss", .id = -1, .dev = { diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index 523ba55..c8267d2 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -585,7 +585,7 @@ static int ads7846_get_pendown_state(void) return !gpio_get_value(OMAP3_EVM_TS_GPIO); } -struct ads7846_platform_data ads7846_config = { +static struct ads7846_platform_data ads7846_config = { .x_max = 0x0fff, .y_max = 0x0fff, .x_plate_ohms = 180, @@ -604,7 +604,7 @@ static struct omap2_mcspi_device_config ads7846_mcspi_config = { .single_channel = 1, /* 0: slave, 1: master */ }; -struct spi_board_info omap3evm_spi_board_info[] = { +static struct spi_board_info omap3evm_spi_board_info[] = { [0] = { .modalias = "ads7846", .bus_num = 1, diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c index c1b881d..55d24b6 100644 --- a/arch/arm/mach-omap2/board-omap3stalker.c +++ b/arch/arm/mach-omap2/board-omap3stalker.c @@ -565,7 +565,7 @@ static struct omap2_mcspi_device_config ads7846_mcspi_config = { .single_channel = 1, /* 0: slave, 1: master */ }; -struct spi_board_info omap3stalker_spi_board_info[] = { +static struct spi_board_info omap3stalker_spi_board_info[] = { [0] = { .modalias = "ads7846", .bus_num = 1, diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c index 9ab18fd..09197a5 100644 --- a/arch/arm/mach-omap2/board-omap3touchbook.c +++ b/arch/arm/mach-omap2/board-omap3touchbook.c @@ -62,7 +62,7 @@ #define TB_BL_PWM_TIMER 9 #define TB_KILL_POWER_GPIO 168 -unsigned long touchbook_revision; +static unsigned long touchbook_revision; static struct mtd_partition omap3touchbook_nand_partitions[] = { /* All the partition sizes are listed in terms of NAND block size */ diff --git a/arch/arm/mach-omap2/board-rx51-sdram.c b/arch/arm/mach-omap2/board-rx51-sdram.c index f392844..a43b2c5 100644 --- a/arch/arm/mach-omap2/board-rx51-sdram.c +++ b/arch/arm/mach-omap2/board-rx51-sdram.c @@ -43,7 +43,7 @@ struct sdram_timings { u32 tWTR; }; -struct omap_sdrc_params rx51_sdrc_params[4]; +static struct omap_sdrc_params rx51_sdrc_params[4]; static const struct sdram_timings rx51_timings[] = { { diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index d21faba..5d9b30d 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -23,6 +23,7 @@ #include "cm.h" #include "prm.h" #include "sdrc.h" +#include "pm.h" static void __iomem *omap2_ctrl_base; static void __iomem *omap4_ctrl_pad_base; diff --git a/arch/arm/mach-omap2/mux2420.c b/arch/arm/mach-omap2/mux2420.c index fdb04a7..414af54 100644 --- a/arch/arm/mach-omap2/mux2420.c +++ b/arch/arm/mach-omap2/mux2420.c @@ -507,7 +507,7 @@ static struct omap_mux __initdata omap2420_muxmodes[] = { * Balls for 447-pin POP package */ #ifdef CONFIG_DEBUG_FS -struct omap_ball __initdata omap2420_pop_ball[] = { +static struct omap_ball __initdata omap2420_pop_ball[] = { _OMAP2420_BALLENTRY(CAM_D0, "y4", NULL), _OMAP2420_BALLENTRY(CAM_D1, "y3", NULL), _OMAP2420_BALLENTRY(CAM_D2, "u7", NULL), diff --git a/arch/arm/mach-omap2/mux2430.c b/arch/arm/mach-omap2/mux2430.c index 7dcaaa8..84d2c5a 100644 --- a/arch/arm/mach-omap2/mux2430.c +++ b/arch/arm/mach-omap2/mux2430.c @@ -586,7 +586,7 @@ static struct omap_mux __initdata omap2430_muxmodes[] = { * 447-pin s-PBGA Package, 0.00mm Ball Pitch (Bottom) */ #ifdef CONFIG_DEBUG_FS -struct omap_ball __initdata omap2430_pop_ball[] = { +static struct omap_ball __initdata omap2430_pop_ball[] = { _OMAP2430_BALLENTRY(CAM_D0, "t8", NULL), _OMAP2430_BALLENTRY(CAM_D1, "t4", NULL), _OMAP2430_BALLENTRY(CAM_D10, "r4", NULL), diff --git a/arch/arm/mach-omap2/mux34xx.c b/arch/arm/mach-omap2/mux34xx.c index f64d7ee..574e54e 100644 --- a/arch/arm/mach-omap2/mux34xx.c +++ b/arch/arm/mach-omap2/mux34xx.c @@ -931,7 +931,7 @@ struct omap_ball __initdata omap3_cbc_ball[] = { * Signals different on CUS package compared to superset */ #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CUS) -struct omap_mux __initdata omap3_cus_subset[] = { +static struct omap_mux __initdata omap3_cus_subset[] = { _OMAP3_MUXENTRY(CAM_D10, 109, "cam_d10", NULL, NULL, NULL, "gpio_109", NULL, NULL, "safe_mode"), @@ -1077,7 +1077,7 @@ struct omap_mux __initdata omap3_cus_subset[] = { */ #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \ && defined(CONFIG_OMAP_PACKAGE_CUS) -struct omap_ball __initdata omap3_cus_ball[] = { +static struct omap_ball __initdata omap3_cus_ball[] = { _OMAP3_BALLENTRY(CAM_D0, "ab18", NULL), _OMAP3_BALLENTRY(CAM_D1, "ac18", NULL), _OMAP3_BALLENTRY(CAM_D10, "f21", NULL), @@ -1269,7 +1269,7 @@ struct omap_ball __initdata omap3_cus_ball[] = { * Signals different on CBB package comapared to superset */ #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBB) -struct omap_mux __initdata omap3_cbb_subset[] = { +static struct omap_mux __initdata omap3_cbb_subset[] = { _OMAP3_MUXENTRY(CAM_D10, 109, "cam_d10", NULL, NULL, NULL, "gpio_109", NULL, NULL, "safe_mode"), @@ -1390,7 +1390,7 @@ struct omap_mux __initdata omap3_cbb_subset[] = { */ #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \ && defined(CONFIG_OMAP_PACKAGE_CBB) -struct omap_ball __initdata omap3_cbb_ball[] = { +static struct omap_ball __initdata omap3_cbb_ball[] = { _OMAP3_BALLENTRY(CAM_D0, "ag17", NULL), _OMAP3_BALLENTRY(CAM_D1, "ah17", NULL), _OMAP3_BALLENTRY(CAM_D10, "b25", NULL), @@ -1600,7 +1600,7 @@ struct omap_ball __initdata omap3_cbb_ball[] = { * Signals different on 36XX CBP package comapared to 34XX CBC package */ #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBP) -struct omap_mux __initdata omap36xx_cbp_subset[] = { +static struct omap_mux __initdata omap36xx_cbp_subset[] = { _OMAP3_MUXENTRY(CAM_D0, 99, "cam_d0", NULL, "csi2_dx2", NULL, "gpio_99", NULL, NULL, "safe_mode"), @@ -1818,7 +1818,7 @@ struct omap_mux __initdata omap36xx_cbp_subset[] = { */ #if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \ && defined (CONFIG_OMAP_PACKAGE_CBP) -struct omap_ball __initdata omap36xx_cbp_ball[] = { +static struct omap_ball __initdata omap36xx_cbp_ball[] = { _OMAP3_BALLENTRY(CAM_D0, "ag17", NULL), _OMAP3_BALLENTRY(CAM_D1, "ah17", NULL), _OMAP3_BALLENTRY(CAM_D10, "b25", NULL), diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c index af00c17..5e81517 100644 --- a/arch/arm/mach-omap2/pm-debug.c +++ b/arch/arm/mach-omap2/pm-debug.c @@ -167,7 +167,7 @@ void omap2_pm_dump(int mode, int resume, unsigned int us) static void pm_dbg_regset_store(u32 *ptr); -struct dentry *pm_dbg_dir; +static struct dentry *pm_dbg_dir; static int pm_dbg_init_done; diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c index d4388d34..a48a1e2 100644 --- a/arch/arm/mach-omap2/prcm.c +++ b/arch/arm/mach-omap2/prcm.c @@ -119,7 +119,7 @@ struct omap3_prcm_regs { u32 wkup_pm_wken; }; -struct omap3_prcm_regs prcm_context; +static struct omap3_prcm_regs prcm_context; u32 omap_prcm_get_reset_sources(void) { diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h index 20f1054..dfa3aff 100644 --- a/arch/arm/plat-omap/include/plat/dmtimer.h +++ b/arch/arm/plat-omap/include/plat/dmtimer.h @@ -45,6 +45,8 @@ #define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02 struct omap_dm_timer; +extern struct omap_dm_timer *gptimer_wakeup; +extern struct sys_timer omap_timer; struct clk; int omap_dm_timer_init(void); diff --git a/arch/arm/plat-omap/include/plat/sdrc.h b/arch/arm/plat-omap/include/plat/sdrc.h index 7b76f50..efd87c8 100644 --- a/arch/arm/plat-omap/include/plat/sdrc.h +++ b/arch/arm/plat-omap/include/plat/sdrc.h @@ -147,6 +147,7 @@ struct memory_timings { }; extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode); +struct omap_sdrc_params *rx51_get_sdram_timings(void); u32 omap2xxx_sdrc_dll_is_unlocked(void); u32 omap2xxx_sdrc_reprogram(u32 level, u32 force); -- cgit v1.1 From 04aeae777945df0e3e37d968d211c821c7458cc5 Mon Sep 17 00:00:00 2001 From: Manjunath Kondaiah G Date: Fri, 8 Oct 2010 09:58:35 -0700 Subject: OMAP2plus: Fix static function warnings This patch fixes sparse warnings due non declarations of static functions. arch/arm/mach-omap2/timer-gp.c:115:12: warning: symbol 'omap2_gp_clockevent_set_gptimer' was not declared. Should it be static? arch/arm/mach-omap2/powerdomain.c:993:5: warning: symbol 'pwrdm_set_lowpwrstchange' was not declared. Should it be static? arch/arm/mach-omap2/board-flash.c:141:8: warning: symbol 'board_nand_init' was not declared. Should it be static? arch/arm/mach-omap2/board-n8x0.c:416:6: warning: symbol 'n8x0_mmc_slot1_cover_handler' was not declared. Should it be static? arch/arm/mach-omap2/board-n8x0.c:544:13: warning: symbol 'n8x0_mmc_init' was not declared. Should it be static? arch/arm/mach-omap2/board-rx51-peripherals.c:902:13: warning: symbol 'rx51_peripherals_init' was not declared. Should it be static? arch/arm/mach-omap2/board-rx51-video.c:107:13: warning: symbol 'rx51_video_mem_init' was not declared. Should it be static? arch/arm/mach-omap2/board-zoom-debugboard.c:155:12: warning: symbol 'zoom_debugboard_init' was not declared. Should it be static? arch/arm/mach-omap2/board-zoom-peripherals.c:280:13: warning: symbol 'zoom_peripherals_init' was not declared. Should it be static? arch/arm/mach-omap2/board-igep0020.c:110:13: warning: symbol 'igep2_flash_init' was not declared. Should it be static? arch/arm/mach-omap2/board-am3517evm.c:109:6: warning: symbol 'am3517_evm_ethernet_init' was not declared. Should it be static? drivers/mtd/onenand/omap2.c:577:5: warning: symbol 'omap2_onenand_rephase' was not declared. Should it be static? Signed-off-by: Manjunath Kondaiah G Cc: linux-arm-kernel@lists.infradead.org Cc: Nishanth Menon Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-3430sdp.c | 3 +-- arch/arm/mach-omap2/board-3630sdp.c | 2 +- arch/arm/mach-omap2/board-4430sdp.c | 3 ++- arch/arm/mach-omap2/board-am3517evm.c | 2 +- arch/arm/mach-omap2/board-devkit8000.c | 2 +- arch/arm/mach-omap2/board-flash.c | 3 ++- arch/arm/mach-omap2/board-flash.h | 30 ++++++++++++++++++++++++++ arch/arm/mach-omap2/board-igep0020.c | 4 ++-- arch/arm/mach-omap2/board-ldp.c | 1 + arch/arm/mach-omap2/board-n8x0.c | 16 +------------- arch/arm/mach-omap2/board-omap3beagle.c | 2 +- arch/arm/mach-omap2/board-omap3logic.c | 2 +- arch/arm/mach-omap2/board-omap3stalker.c | 2 +- arch/arm/mach-omap2/board-omap3touchbook.c | 2 +- arch/arm/mach-omap2/board-omap4panda.c | 2 +- arch/arm/mach-omap2/board-rx51-peripherals.c | 2 ++ arch/arm/mach-omap2/board-rx51-video.c | 2 ++ arch/arm/mach-omap2/board-zoom-debugboard.c | 2 ++ arch/arm/mach-omap2/board-zoom-peripherals.c | 2 ++ arch/arm/mach-omap2/board-zoom2.c | 1 + arch/arm/mach-omap2/board-zoom3.c | 1 + arch/arm/mach-omap2/include/mach/board-flash.h | 28 ------------------------ arch/arm/mach-omap2/include/mach/board-rx51.h | 11 ++++++++++ arch/arm/mach-omap2/include/mach/board-zoom.h | 4 ---- arch/arm/mach-omap2/timer-gp.c | 2 ++ arch/arm/mach-omap2/timer-gp.h | 16 ++++++++++++++ arch/arm/plat-omap/include/plat/powerdomain.h | 1 + arch/arm/plat-omap/include/plat/timer-gp.h | 17 --------------- 28 files changed, 87 insertions(+), 78 deletions(-) create mode 100644 arch/arm/mach-omap2/board-flash.h delete mode 100644 arch/arm/mach-omap2/include/mach/board-flash.h create mode 100644 arch/arm/mach-omap2/include/mach/board-rx51.h create mode 100644 arch/arm/mach-omap2/timer-gp.h delete mode 100644 arch/arm/plat-omap/include/plat/timer-gp.h (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index 3eb9839..9a65522 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -42,8 +42,7 @@ #include #include -#include - +#include "board-flash.h" #include "mux.h" #include "sdram-qimonda-hyb18m512160af-6.h" #include "hsmmc.h" diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c index b359c3f..2b2e0ef 100644 --- a/arch/arm/mach-omap2/board-3630sdp.c +++ b/arch/arm/mach-omap2/board-3630sdp.c @@ -21,8 +21,8 @@ #include #include -#include +#include "board-flash.h" #include "mux.h" #include "sdram-hynix-h8mbx00u0mer-0em.h" diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index 1bed1e6..d70b580 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -33,10 +33,11 @@ #include #include #include -#include #include #include + #include "hsmmc.h" +#include "timer-gp.h" #define ETH_KS8851_IRQ 34 #define ETH_KS8851_POWER_ON 48 diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index 197289b..ae22ea8 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c @@ -106,7 +106,7 @@ static void am3517_disable_ethernet_int(void) regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); } -void am3517_evm_ethernet_init(struct emac_platform_data *pdata) +static void am3517_evm_ethernet_init(struct emac_platform_data *pdata) { unsigned int regval; diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c index de5e2c2..1aff79e 100644 --- a/arch/arm/mach-omap2/board-devkit8000.c +++ b/arch/arm/mach-omap2/board-devkit8000.c @@ -45,7 +45,6 @@ #include #include #include -#include #include #include @@ -59,6 +58,7 @@ #include "mux.h" #include "hsmmc.h" +#include "timer-gp.h" #define NAND_BLOCK_SIZE SZ_128K diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c index ac834aa..fd38c05 100644 --- a/arch/arm/mach-omap2/board-flash.c +++ b/arch/arm/mach-omap2/board-flash.c @@ -21,7 +21,8 @@ #include #include #include -#include + +#include "board-flash.h" #define REG_FPGA_REV 0x10 #define REG_FPGA_DIP_SWITCH_INPUT2 0x60 diff --git a/arch/arm/mach-omap2/board-flash.h b/arch/arm/mach-omap2/board-flash.h new file mode 100644 index 0000000..69befe0 --- /dev/null +++ b/arch/arm/mach-omap2/board-flash.h @@ -0,0 +1,30 @@ +/* + * board-sdp.h + * + * Information structures for SDP-specific board config data + * + * Copyright (C) 2009 Nokia Corporation + * Copyright (C) 2009 Texas Instruments + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include + +#define PDC_NOR 1 +#define PDC_NAND 2 +#define PDC_ONENAND 3 +#define DBG_MPDB 4 + +struct flash_partitions { + struct mtd_partition *parts; + int nr_parts; +}; + +extern void board_flash_init(struct flash_partitions [], + char chip_sel[][GPMC_CS_NUM]); +extern void board_nand_init(struct mtd_partition *nand_parts, + u8 nr_parts, u8 cs); diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index f3f0280..c437031 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -108,7 +108,7 @@ static struct platform_device igep2_onenand_device = { }, }; -void __init igep2_flash_init(void) +static void __init igep2_flash_init(void) { u8 cs = 0; u8 onenandcs = GPMC_CS_NUM + 1; @@ -142,7 +142,7 @@ void __init igep2_flash_init(void) } #else -void __init igep2_flash_init(void) {} +static void __init igep2_flash_init(void) {} #endif #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c index 58698e3..38c4451 100644 --- a/arch/arm/mach-omap2/board-ldp.c +++ b/arch/arm/mach-omap2/board-ldp.c @@ -45,6 +45,7 @@ #include #include +#include "board-flash.h" #include "mux.h" #include "hsmmc.h" diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c index 8fd2269..abdcc39 100644 --- a/arch/arm/mach-omap2/board-n8x0.c +++ b/arch/arm/mach-omap2/board-n8x0.c @@ -384,15 +384,6 @@ static void n8x0_mmc_callback(void *data, u8 card_mask) omap_mmc_notify_cover_event(mmc_device, index, *openp); } -void n8x0_mmc_slot1_cover_handler(void *arg, int closed_state) -{ - if (mmc_device == NULL) - return; - - slot1_cover_open = !closed_state; - omap_mmc_notify_cover_event(mmc_device, 0, closed_state); -} - static int n8x0_mmc_late_init(struct device *dev) { int r, bit, *openp; @@ -512,7 +503,7 @@ static struct omap_mmc_platform_data mmc1_data = { static struct omap_mmc_platform_data *mmc_data[OMAP24XX_NR_MMC]; -void __init n8x0_mmc_init(void) +static void __init n8x0_mmc_init(void) { int err; @@ -561,11 +552,6 @@ void __init n8x0_mmc_init(void) void __init n8x0_mmc_init(void) { } - -void n8x0_mmc_slot1_cover_handler(void *arg, int state) -{ -} - #endif /* CONFIG_MMC_OMAP */ #ifdef CONFIG_MENELAUS diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 7e70488..73689c0 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -44,10 +44,10 @@ #include #include #include -#include #include "mux.h" #include "hsmmc.h" +#include "timer-gp.h" #define NAND_BLOCK_SIZE SZ_128K diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c index 4c045cf..3151cf2 100644 --- a/arch/arm/mach-omap2/board-omap3logic.c +++ b/arch/arm/mach-omap2/board-omap3logic.c @@ -35,13 +35,13 @@ #include "mux.h" #include "hsmmc.h" +#include "timer-gp.h" #include #include #include #include #include -#include #include #include diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c index 55d24b6..c5bd764 100644 --- a/arch/arm/mach-omap2/board-omap3stalker.c +++ b/arch/arm/mach-omap2/board-omap3stalker.c @@ -39,7 +39,6 @@ #include #include #include -#include #include #include @@ -53,6 +52,7 @@ #include "sdram-micron-mt46h32m32lf-6.h" #include "mux.h" #include "hsmmc.h" +#include "timer-gp.h" #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) #define OMAP3STALKER_ETHR_START 0x2c000000 diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c index 09197a5..7d56938 100644 --- a/arch/arm/mach-omap2/board-omap3touchbook.c +++ b/arch/arm/mach-omap2/board-omap3touchbook.c @@ -48,10 +48,10 @@ #include #include #include -#include #include "mux.h" #include "hsmmc.h" +#include "timer-gp.h" #include diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index aa8296e..83bd1fe 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -35,10 +35,10 @@ #include #include #include -#include #include #include #include "hsmmc.h" +#include "timer-gp.h" static struct gpio_led gpio_leds[] = { diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index a3dbaa7..cf6f12e 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -32,6 +32,8 @@ #include #include +#include + #include #include diff --git a/arch/arm/mach-omap2/board-rx51-video.c b/arch/arm/mach-omap2/board-rx51-video.c index 5a1005b..85503fe 100644 --- a/arch/arm/mach-omap2/board-rx51-video.c +++ b/arch/arm/mach-omap2/board-rx51-video.c @@ -20,6 +20,8 @@ #include #include +#include + #include "mux.h" #define RX51_LCD_RESET_GPIO 90 diff --git a/arch/arm/mach-omap2/board-zoom-debugboard.c b/arch/arm/mach-omap2/board-zoom-debugboard.c index 1d7f827..007ebdc 100644 --- a/arch/arm/mach-omap2/board-zoom-debugboard.c +++ b/arch/arm/mach-omap2/board-zoom-debugboard.c @@ -16,6 +16,8 @@ #include +#include + #define ZOOM_SMSC911X_CS 7 #define ZOOM_SMSC911X_GPIO 158 #define ZOOM_QUADUART_CS 3 diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c index e5eac46..b8dee5e 100644 --- a/arch/arm/mach-omap2/board-zoom-peripherals.c +++ b/arch/arm/mach-omap2/board-zoom-peripherals.c @@ -25,6 +25,8 @@ #include #include +#include + #include "mux.h" #include "hsmmc.h" diff --git a/arch/arm/mach-omap2/board-zoom2.c b/arch/arm/mach-omap2/board-zoom2.c index 3ad9ecf..d356ef5 100644 --- a/arch/arm/mach-omap2/board-zoom2.c +++ b/arch/arm/mach-omap2/board-zoom2.c @@ -23,6 +23,7 @@ #include +#include "board-flash.h" #include "mux.h" #include "sdram-micron-mt46h32m32lf-6.h" diff --git a/arch/arm/mach-omap2/board-zoom3.c b/arch/arm/mach-omap2/board-zoom3.c index 6ca0b83..95895d5 100644 --- a/arch/arm/mach-omap2/board-zoom3.c +++ b/arch/arm/mach-omap2/board-zoom3.c @@ -22,6 +22,7 @@ #include #include +#include "board-flash.h" #include "mux.h" #include "sdram-hynix-h8mbx00u0mer-0em.h" diff --git a/arch/arm/mach-omap2/include/mach/board-flash.h b/arch/arm/mach-omap2/include/mach/board-flash.h deleted file mode 100644 index b2242ae..0000000 --- a/arch/arm/mach-omap2/include/mach/board-flash.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * board-sdp.h - * - * Information structures for SDP-specific board config data - * - * Copyright (C) 2009 Nokia Corporation - * Copyright (C) 2009 Texas Instruments - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include -#include -#include - -#define PDC_NOR 1 -#define PDC_NAND 2 -#define PDC_ONENAND 3 -#define DBG_MPDB 4 - -struct flash_partitions { - struct mtd_partition *parts; - int nr_parts; -}; - -extern void board_flash_init(struct flash_partitions [], - char chip_sel[][GPMC_CS_NUM]); diff --git a/arch/arm/mach-omap2/include/mach/board-rx51.h b/arch/arm/mach-omap2/include/mach/board-rx51.h new file mode 100644 index 0000000..b76f49e --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/board-rx51.h @@ -0,0 +1,11 @@ +/* + * Defines for rx51 boards + */ + +#ifndef _OMAP_BOARD_RX51_H +#define _OMAP_BOARD_RX51_H + +extern void __init rx51_peripherals_init(void); +extern void __init rx51_video_mem_init(void); + +#endif diff --git a/arch/arm/mach-omap2/include/mach/board-zoom.h b/arch/arm/mach-omap2/include/mach/board-zoom.h index 3af69d2..3986f24 100644 --- a/arch/arm/mach-omap2/include/mach/board-zoom.h +++ b/arch/arm/mach-omap2/include/mach/board-zoom.h @@ -1,11 +1,7 @@ /* * Defines for zoom boards */ -#include -#include - #define ZOOM_NAND_CS 0 -extern void __init board_nand_init(struct mtd_partition *, u8 nr_parts, u8 cs); extern int __init zoom_debugboard_init(void); extern void __init zoom_peripherals_init(void); diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c index 5a3e606..e13c29e 100644 --- a/arch/arm/mach-omap2/timer-gp.c +++ b/arch/arm/mach-omap2/timer-gp.c @@ -40,6 +40,8 @@ #include #include +#include "timer-gp.h" + /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */ #define MAX_GPTIMER_ID 12 diff --git a/arch/arm/mach-omap2/timer-gp.h b/arch/arm/mach-omap2/timer-gp.h new file mode 100644 index 0000000..5c1072c --- /dev/null +++ b/arch/arm/mach-omap2/timer-gp.h @@ -0,0 +1,16 @@ +/* + * OMAP2/3 GPTIMER support.headers + * + * Copyright (C) 2009 Nokia Corporation + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H +#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H + +extern int __init omap2_gp_clockevent_set_gptimer(u8 id); + +#endif diff --git a/arch/arm/plat-omap/include/plat/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h index 3ea7220..9ca420d 100644 --- a/arch/arm/plat-omap/include/plat/powerdomain.h +++ b/arch/arm/plat-omap/include/plat/powerdomain.h @@ -162,5 +162,6 @@ int pwrdm_state_switch(struct powerdomain *pwrdm); int pwrdm_clkdm_state_switch(struct clockdomain *clkdm); int pwrdm_pre_transition(void); int pwrdm_post_transition(void); +int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm); #endif diff --git a/arch/arm/plat-omap/include/plat/timer-gp.h b/arch/arm/plat-omap/include/plat/timer-gp.h deleted file mode 100644 index c88d346..0000000 --- a/arch/arm/plat-omap/include/plat/timer-gp.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * OMAP2/3 GPTIMER support.headers - * - * Copyright (C) 2009 Nokia Corporation - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ - -#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H -#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H - -int __init omap2_gp_clockevent_set_gptimer(u8 id); - -#endif - -- cgit v1.1 From 600ecd9874d56d310a597b1e0a3936f195c83022 Mon Sep 17 00:00:00 2001 From: Manjunath Kondaiah G Date: Fri, 8 Oct 2010 09:59:20 -0700 Subject: OMAP: mach-omap2: Fix miscellaneous sparse warnings This patch fixes miscellaneous sparse warnings in mach-omap2. arch/arm/mach-omap2/board-am3517evm.c:141:17: warning: Initializer entry defined twice arch/arm/mach-omap2/board-am3517evm.c:142:18: also defined here arch/arm/mach-omap2/irq.c:50:35: warning: Using plain integer as NULL pointer Signed-off-by: Manjunath Kondaiah G Cc: linux-arm-kernel@lists.infradead.org Cc: Nishanth Menon Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-am3517evm.c | 1 - arch/arm/mach-omap2/irq.c | 1 - 2 files changed, 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index ae22ea8..b091741 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c @@ -139,7 +139,6 @@ static void am3517_evm_ethernet_init(struct emac_platform_data *pdata) static struct i2c_board_info __initdata am3517evm_i2c1_boardinfo[] = { { I2C_BOARD_INFO("s35390a", 0x30), - .type = "s35390a", }, }; diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index 26aeef5..32eeabe 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c @@ -47,7 +47,6 @@ static struct omap_irq_bank { } __attribute__ ((aligned(4))) irq_banks[] = { { /* MPU INTC */ - .base_reg = 0, .nr_irqs = 96, }, }; -- cgit v1.1 From b0a330dc5eff6b27cce3b7b5dbea9379d969f73e Mon Sep 17 00:00:00 2001 From: Manjunath Kondaiah G Date: Fri, 8 Oct 2010 10:00:19 -0700 Subject: OMAP: plat-omap: Fix static function warnings This patch fixes sparse warnings due non declarations of static functions. arch/arm/plat-omap/sram.c:130:13: warning: symbol 'omap_detect_sram' was not declared. Should it be static? arch/arm/plat-omap/sram.c:216:13: warning: symbol 'omap_map_sram' was not declared. Should it be static? arch/arm/plat-omap/sram.c:450:12: warning: symbol 'omap_sram_init' was not declared. Should it be static? arch/arm/plat-omap/sram.c:348:12: warning: symbol 'omap242x_sram_init' was not declared. Should it be static? arch/arm/plat-omap/sram.c:369:12: warning: symbol 'omap243x_sram_init' was not declared. Should it be static? arch/arm/plat-omap/sram.c:425:12: warning: symbol 'omap34xx_sram_init' was not declared. Should it be static? arch/arm/plat-omap/sram.c:441:12: warning: symbol 'omap44xx_sram_init' was not declared. Should it be static arch/arm/plat-omap/mcbsp.c:36:6: warning: symbol 'omap_mcbsp_write' was not declared. Should it be static? arch/arm/plat-omap/mcbsp.c:50:5: warning: symbol 'omap_mcbsp_read' was not declared. Should it be static? arch/arm/plat-omap/mcbsp.c:65:6: warning: symbol 'omap_mcbsp_st_write' was not declared. Should it be static? arch/arm/plat-omap/mcbsp.c:70:5: warning: symbol 'omap_mcbsp_st_read' was not declared. Should it be static? arch/arm/plat-omap/mcbsp.c:1648:15: warning: symbol 'omap_st_add' was not declared. Should it be static? arch/arm/plat-omap/fb.c:414:15: warning: symbol 'omapfb_reserve_sram' was not declared. Should it be static? arch/arm/plat-omap/cpu-omap.c:43:5: warning: symbol 'omap_verify_speed' was not declared. Should it be static? arch/arm/plat-omap/cpu-omap.c:61:14: warning: symbol 'omap_getspeed' was not declared. Should it be static? Signed-off-by: Manjunath Kondaiah G Cc: linux-arm-kernel@lists.infradead.org Cc: Nishanth Menon Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/io.c | 1 + arch/arm/mach-omap2/io.h | 7 +++++++ arch/arm/plat-omap/cpu-omap.c | 4 ++-- arch/arm/plat-omap/fb.c | 2 ++ arch/arm/plat-omap/fb.h | 10 ++++++++++ arch/arm/plat-omap/include/plat/sram.h | 1 - arch/arm/plat-omap/mcbsp.c | 10 +++++----- arch/arm/plat-omap/sram.c | 21 +++++++++------------ arch/arm/plat-omap/sram.h | 6 ++++++ 9 files changed, 42 insertions(+), 20 deletions(-) create mode 100644 arch/arm/mach-omap2/io.h create mode 100644 arch/arm/plat-omap/fb.h create mode 100644 arch/arm/plat-omap/sram.h (limited to 'arch') diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 490d870..40562dd 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -36,6 +36,7 @@ #include "clock2xxx.h" #include "clock3xxx.h" #include "clock44xx.h" +#include "io.h" #include #include diff --git a/arch/arm/mach-omap2/io.h b/arch/arm/mach-omap2/io.h new file mode 100644 index 0000000..fd230c6 --- /dev/null +++ b/arch/arm/mach-omap2/io.h @@ -0,0 +1,7 @@ + +#ifndef __MACH_OMAP2_IO_H__ +#define __MACH_OMAP2_IO_H__ + +extern int __init omap_sram_init(void); + +#endif /* __MACH_OMAP2_IO_H__ */ diff --git a/arch/arm/plat-omap/cpu-omap.c b/arch/arm/plat-omap/cpu-omap.c index 6d3d333..11c54ec 100644 --- a/arch/arm/plat-omap/cpu-omap.c +++ b/arch/arm/plat-omap/cpu-omap.c @@ -40,7 +40,7 @@ static struct clk *mpu_clk; /* TODO: Add support for SDRAM timing changes */ -int omap_verify_speed(struct cpufreq_policy *policy) +static int omap_verify_speed(struct cpufreq_policy *policy) { if (freq_table) return cpufreq_frequency_table_verify(policy, freq_table); @@ -58,7 +58,7 @@ int omap_verify_speed(struct cpufreq_policy *policy) return 0; } -unsigned int omap_getspeed(unsigned int cpu) +static unsigned int omap_getspeed(unsigned int cpu) { unsigned long rate; diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c index 0054b95..725df5c 100644 --- a/arch/arm/plat-omap/fb.c +++ b/arch/arm/plat-omap/fb.c @@ -36,6 +36,8 @@ #include #include +#include "fb.h" + #if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE) static struct omapfb_platform_data omapfb_config; diff --git a/arch/arm/plat-omap/fb.h b/arch/arm/plat-omap/fb.h new file mode 100644 index 0000000..d765d0b --- /dev/null +++ b/arch/arm/plat-omap/fb.h @@ -0,0 +1,10 @@ +#ifndef __PLAT_OMAP_FB_H__ +#define __PLAT_OMAP_FB_H__ + +extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart, + unsigned long sram_vstart, + unsigned long sram_size, + unsigned long pstart_avail, + unsigned long size_avail); + +#endif /* __PLAT_OMAP_FB_H__ */ diff --git a/arch/arm/plat-omap/include/plat/sram.h b/arch/arm/plat-omap/include/plat/sram.h index 16a1b45..5905100 100644 --- a/arch/arm/plat-omap/include/plat/sram.h +++ b/arch/arm/plat-omap/include/plat/sram.h @@ -11,7 +11,6 @@ #ifndef __ARCH_ARM_OMAP_SRAM_H #define __ARCH_ARM_OMAP_SRAM_H -extern int __init omap_sram_init(void); extern void * omap_sram_push(void * start, unsigned long size); extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl); diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index ecbfe39..b2e0469 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c @@ -33,7 +33,7 @@ struct omap_mcbsp **mcbsp_ptr; int omap_mcbsp_count, omap_mcbsp_cache_size; -void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val) +static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val) { if (cpu_class_is_omap1()) { ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)] = (u16)val; @@ -47,7 +47,7 @@ void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val) } } -int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache) +static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache) { if (cpu_class_is_omap1()) { return !from_cache ? __raw_readw(mcbsp->io_base + reg) : @@ -62,12 +62,12 @@ int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache) } #ifdef CONFIG_ARCH_OMAP3 -void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val) +static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val) { __raw_writel(val, mcbsp->st_data->io_base_st + reg); } -int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg) +static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg) { return __raw_readl(mcbsp->st_data->io_base_st + reg); } @@ -1648,7 +1648,7 @@ static const struct attribute_group sidetone_attr_group = { .attrs = (struct attribute **)sidetone_attrs, }; -int __devinit omap_st_add(struct omap_mcbsp *mcbsp) +static int __devinit omap_st_add(struct omap_mcbsp *mcbsp) { struct omap_mcbsp_platform_data *pdata = mcbsp->pdata; struct omap_mcbsp_st_data *st_data; diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index 98c86ff1..dba5704 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include @@ -31,6 +32,8 @@ #include #include +#include "sram.h" +#include "fb.h" #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) # include "../mach-omap2/prm.h" @@ -79,12 +82,6 @@ static unsigned long omap_sram_base; static unsigned long omap_sram_size; static unsigned long omap_sram_ceil; -extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart, - unsigned long sram_vstart, - unsigned long sram_size, - unsigned long pstart_avail, - unsigned long size_avail); - /* * Depending on the target RAMFS firewall setup, the public usable amount of * SRAM varies. The default accessible size for all device types is 2k. A GP @@ -118,7 +115,7 @@ static int is_sram_locked(void) * to secure SRAM will hang the system. Also the SRAM is not * yet mapped at this point. */ -void __init omap_detect_sram(void) +static void __init omap_detect_sram(void) { unsigned long reserved; @@ -204,7 +201,7 @@ static struct map_desc omap_sram_io_desc[] __initdata = { /* * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early. */ -void __init omap_map_sram(void) +static void __init omap_map_sram(void) { unsigned long base; @@ -336,7 +333,7 @@ u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass) #endif #ifdef CONFIG_ARCH_OMAP2420 -int __init omap242x_sram_init(void) +static int __init omap242x_sram_init(void) { _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init, omap242x_sram_ddr_init_sz); @@ -357,7 +354,7 @@ static inline int omap242x_sram_init(void) #endif #ifdef CONFIG_ARCH_OMAP2430 -int __init omap243x_sram_init(void) +static int __init omap243x_sram_init(void) { _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init, omap243x_sram_ddr_init_sz); @@ -413,7 +410,7 @@ void omap3_sram_restore_context(void) } #endif /* CONFIG_PM */ -int __init omap34xx_sram_init(void) +static int __init omap34xx_sram_init(void) { _omap3_sram_configure_core_dpll = omap_sram_push(omap3_sram_configure_core_dpll, @@ -429,7 +426,7 @@ static inline int omap34xx_sram_init(void) #endif #ifdef CONFIG_ARCH_OMAP4 -int __init omap44xx_sram_init(void) +static int __init omap44xx_sram_init(void) { printk(KERN_ERR "FIXME: %s not implemented\n", __func__); diff --git a/arch/arm/plat-omap/sram.h b/arch/arm/plat-omap/sram.h new file mode 100644 index 0000000..29b43ef --- /dev/null +++ b/arch/arm/plat-omap/sram.h @@ -0,0 +1,6 @@ +#ifndef __PLAT_OMAP_SRAM_H__ +#define __PLAT_OMAP_SRAM_H__ + +extern int __init omap_sram_init(void); + +#endif /* __PLAT_OMAP_SRAM_H__ */ -- cgit v1.1 From bead4375731ad283cccbcbcb55bc7549c9746168 Mon Sep 17 00:00:00 2001 From: Manjunath Kondaiah G Date: Fri, 8 Oct 2010 10:01:13 -0700 Subject: OMAP3: Keypad: Fix incorrect type initializer The keypad matrix variable declaration is not matching with structure variable keymap declared in keypad_matrix.h. Due to this, following sparse warnings are generated with omap3_defconfig. arch/arm/mach-omap2/board-devkit8000.c:223:14: warning: incorrect type in initializer (different signedness) arch/arm/mach-omap2/board-devkit8000.c:223:14: expected unsigned int const [usertype] *keymap arch/arm/mach-omap2/board-devkit8000.c:223:14: got int static [toplevel] * arch/arm/mach-omap2/board-ldp.c:107:14: warning: incorrect type in initializer (different signedness) arch/arm/mach-omap2/board-ldp.c:107:14: expected unsigned int const [usertype] *keymap arch/arm/mach-omap2/board-ldp.c:107:14: got int static [toplevel] * arch/arm/mach-omap2/board-omap3evm.c:472:14: warning: incorrect type in initializer (different signedness) arch/arm/mach-omap2/board-omap3evm.c:472:14: expected unsigned int const [usertype] *keymap arch/arm/mach-omap2/board-omap3evm.c:472:14: got int static [toplevel] * arch/arm/mach-omap2/board-3430sdp.c:114:14: warning: incorrect type in initializer (different signedness) arch/arm/mach-omap2/board-3430sdp.c:114:14: expected unsigned int const [usertype] *keymap arch/arm/mach-omap2/board-3430sdp.c:114:14: got int static [toplevel] * arch/arm/mach-omap2/board-rx51-peripherals.c:248:14: warning: incorrect type in initializer (different signedness) arch/arm/mach-omap2/board-rx51-peripherals.c:248:14: expected unsigned int const [usertype] *keymap arch/arm/mach-omap2/board-rx51-peripherals.c:248:14: got int static [toplevel] * arch/arm/mach-omap2/board-zoom-peripherals.c:88:14: warning: incorrect type in initializer (different signedness) arch/arm/mach-omap2/board-zoom-peripherals.c:88:14: expected unsigned int const [usertype] *keymap arch/arm/mach-omap2/board-zoom-peripherals.c:88:14: got int static [toplevel] * arch/arm/mach-omap2/board-cm-t35.c:568:14: warning: incorrect type in initializer (different signedness) arch/arm/mach-omap2/board-cm-t35.c:568:14: expected unsigned int const [usertype] *keymap arch/arm/mach-omap2/board-cm-t35.c:568:14: got int static [toplevel] * arch/arm/mach-omap2/board-omap3stalker.c:415:13: warning: incorrect type in initializer (different signedness) arch/arm/mach-omap2/board-omap3stalker.c:415:13: expected unsigned int const [usertype] *keymap arch/arm/mach-omap2/board-omap3stalker.c:415:13: got int static [toplevel] * This patch modifies the variable keymap declaration as per declaration in matrix_keymap structure. Signed-off-by: Manjunath Kondaiah G Cc: linux-input@vger.kernel.org Cc: Dmitry Torokhov Cc: linux-arm-kernel@lists.infradead.org Cc: Nishanth Menon Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-3430sdp.c | 2 +- arch/arm/mach-omap2/board-cm-t35.c | 2 +- arch/arm/mach-omap2/board-devkit8000.c | 2 +- arch/arm/mach-omap2/board-ldp.c | 2 +- arch/arm/mach-omap2/board-omap3evm.c | 2 +- arch/arm/mach-omap2/board-omap3stalker.c | 2 +- arch/arm/mach-omap2/board-rx51-peripherals.c | 2 +- arch/arm/mach-omap2/board-zoom-peripherals.c | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index 9a65522..9ba2ee2 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -76,7 +76,7 @@ static struct cpuidle_params omap3_cpuidle_params_table[] = { {1, 10000, 30000, 300000}, }; -static int board_keymap[] = { +static uint32_t board_keymap[] = { KEY(0, 0, KEY_LEFT), KEY(0, 1, KEY_RIGHT), KEY(0, 2, KEY_A), diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index b72009a..2b328b9 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c @@ -559,7 +559,7 @@ static struct twl4030_usb_data cm_t35_usb_data = { .usb_mode = T2_USB_MODE_ULPI, }; -static int cm_t35_keymap[] = { +static uint32_t cm_t35_keymap[] = { KEY(0, 0, KEY_A), KEY(0, 1, KEY_B), KEY(0, 2, KEY_LEFT), KEY(1, 0, KEY_UP), KEY(1, 1, KEY_ENTER), KEY(1, 2, KEY_DOWN), KEY(2, 0, KEY_RIGHT), KEY(2, 1, KEY_C), KEY(2, 2, KEY_D), diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c index 1aff79e..ad9ad95 100644 --- a/arch/arm/mach-omap2/board-devkit8000.c +++ b/arch/arm/mach-omap2/board-devkit8000.c @@ -199,7 +199,7 @@ static struct platform_device devkit8000_dss_device = { static struct regulator_consumer_supply devkit8000_vdda_dac_supply = REGULATOR_SUPPLY("vdda_dac", "omapdss"); -static int board_keymap[] = { +static uint32_t board_keymap[] = { KEY(0, 0, KEY_1), KEY(1, 0, KEY_2), KEY(2, 0, KEY_3), diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c index 38c4451..7c1e6ad 100644 --- a/arch/arm/mach-omap2/board-ldp.c +++ b/arch/arm/mach-omap2/board-ldp.c @@ -84,7 +84,7 @@ static struct platform_device ldp_smsc911x_device = { }, }; -static int board_keymap[] = { +static uint32_t board_keymap[] = { KEY(0, 0, KEY_1), KEY(1, 0, KEY_2), KEY(2, 0, KEY_3), diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index c8267d2..6339927 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -447,7 +447,7 @@ static struct twl4030_usb_data omap3evm_usb_data = { .usb_mode = T2_USB_MODE_ULPI, }; -static int board_keymap[] = { +static uint32_t board_keymap[] = { KEY(0, 0, KEY_LEFT), KEY(0, 1, KEY_DOWN), KEY(0, 2, KEY_ENTER), diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c index c5bd764..db644c1 100644 --- a/arch/arm/mach-omap2/board-omap3stalker.c +++ b/arch/arm/mach-omap2/board-omap3stalker.c @@ -390,7 +390,7 @@ static struct twl4030_usb_data omap3stalker_usb_data = { .usb_mode = T2_USB_MODE_ULPI, }; -static int board_keymap[] = { +static uint32_t board_keymap[] = { KEY(0, 0, KEY_LEFT), KEY(0, 1, KEY_DOWN), KEY(0, 2, KEY_ENTER), diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index cf6f12e..25a273d 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -186,7 +186,7 @@ static void __init rx51_add_gpio_keys(void) } #endif /* CONFIG_KEYBOARD_GPIO || CONFIG_KEYBOARD_GPIO_MODULE */ -static int board_keymap[] = { +static uint32_t board_keymap[] = { /* * Note that KEY(x, 8, KEY_XXX) entries represent "entrire row * connected to the ground" matrix state. diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c index b8dee5e..073fd9b4 100644 --- a/arch/arm/mach-omap2/board-zoom-peripherals.c +++ b/arch/arm/mach-omap2/board-zoom-peripherals.c @@ -31,7 +31,7 @@ #include "hsmmc.h" /* Zoom2 has Qwerty keyboard*/ -static int board_keymap[] = { +static uint32_t board_keymap[] = { KEY(0, 0, KEY_E), KEY(0, 1, KEY_R), KEY(0, 2, KEY_T), -- cgit v1.1 From e844b1da87270d96aef3fc79763ecc2c6541a71b Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Fri, 8 Oct 2010 10:22:11 -0700 Subject: omap3: Add minimal OMAP3 IGEP module support The OMAP3 IGEP module is a low-power, high performance production-ready system-on-module (SOM) based on TI's OMAP3 family. More about this board at www.igep.es. Signed-off-by: Enric Balletbo i Serra [tony@atomide.com: updated for the mmc changes and to be selected by default] Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/Kconfig | 6 + arch/arm/mach-omap2/Makefile | 2 + arch/arm/mach-omap2/board-igep0030.c | 402 +++++++++++++++++++++++++++ arch/arm/plat-omap/include/plat/uncompress.h | 1 + 4 files changed, 411 insertions(+) create mode 100644 arch/arm/mach-omap2/board-igep0030.c (limited to 'arch') diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 91dd215..2b79b84 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -254,6 +254,12 @@ config MACH_IGEP0020 default y select OMAP_PACKAGE_CBB +config MACH_IGEP0030 + bool "IGEP OMAP3 module" + depends on ARCH_OMAP3 + default y + select OMAP_PACKAGE_CBB + config MACH_SBC3530 bool "OMAP3 SBC STALKER board" depends on ARCH_OMAP3 diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 9edacb0..d8b1de6 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -158,6 +158,8 @@ obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o \ obj-$(CONFIG_MACH_CM_T3517) += board-cm-t3517.o obj-$(CONFIG_MACH_IGEP0020) += board-igep0020.o \ hsmmc.o +obj-$(CONFIG_MACH_IGEP0030) += board-igep0030.o \ + hsmmc.o obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK) += board-omap3touchbook.o \ hsmmc.o obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o \ diff --git a/arch/arm/mach-omap2/board-igep0030.c b/arch/arm/mach-omap2/board-igep0030.c new file mode 100644 index 0000000..7ed41e0 --- /dev/null +++ b/arch/arm/mach-omap2/board-igep0030.c @@ -0,0 +1,402 @@ +/* + * Copyright (C) 2010 - ISEE 2007 SL + * + * Modified from mach-omap2/board-generic.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include + +#include "mux.h" +#include "hsmmc.h" +#include "sdram-numonyx-m65kxxxxam.h" + +#define IGEP3_GPIO_LED0_GREEN 54 +#define IGEP3_GPIO_LED0_RED 53 +#define IGEP3_GPIO_LED1_RED 16 + +#define IGEP3_GPIO_WIFI_NPD 138 +#define IGEP3_GPIO_WIFI_NRESET 139 +#define IGEP3_GPIO_BT_NRESET 137 + +#define IGEP3_GPIO_USBH_NRESET 115 + + +#if defined(CONFIG_MTD_ONENAND_OMAP2) || \ + defined(CONFIG_MTD_ONENAND_OMAP2_MODULE) + +#define ONENAND_MAP 0x20000000 + +/* + * x2 Flash built-in COMBO POP MEMORY + * Since the device is equipped with two DataRAMs, and two-plane NAND + * Flash memory array, these two component enables simultaneous program + * of 4KiB. Plane1 has only even blocks such as block0, block2, block4 + * while Plane2 has only odd blocks such as block1, block3, block5. + * So MTD regards it as 4KiB page size and 256KiB block size 64*(2*2048) + */ + +static struct mtd_partition igep3_onenand_partitions[] = { + { + .name = "X-Loader", + .offset = 0, + .size = 2 * (64*(2*2048)) + }, + { + .name = "U-Boot", + .offset = MTDPART_OFS_APPEND, + .size = 6 * (64*(2*2048)), + }, + { + .name = "Environment", + .offset = MTDPART_OFS_APPEND, + .size = 2 * (64*(2*2048)), + }, + { + .name = "Kernel", + .offset = MTDPART_OFS_APPEND, + .size = 12 * (64*(2*2048)), + }, + { + .name = "File System", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct omap_onenand_platform_data igep3_onenand_pdata = { + .parts = igep3_onenand_partitions, + .nr_parts = ARRAY_SIZE(igep3_onenand_partitions), + .onenand_setup = NULL, + .dma_channel = -1, /* disable DMA in OMAP OneNAND driver */ +}; + +static struct platform_device igep3_onenand_device = { + .name = "omap2-onenand", + .id = -1, + .dev = { + .platform_data = &igep3_onenand_pdata, + }, +}; + +void __init igep3_flash_init(void) +{ + u8 cs = 0; + u8 onenandcs = GPMC_CS_NUM + 1; + + for (cs = 0; cs < GPMC_CS_NUM; cs++) { + u32 ret; + ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); + + /* Check if NAND/oneNAND is configured */ + if ((ret & 0xC00) == 0x800) + /* NAND found */ + pr_err("IGEP3: Unsupported NAND found\n"); + else { + ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); + + if ((ret & 0x3F) == (ONENAND_MAP >> 24)) + /* OneNAND found */ + onenandcs = cs; + } + } + + if (onenandcs > GPMC_CS_NUM) { + pr_err("IGEP3: Unable to find configuration in GPMC\n"); + return; + } + + igep3_onenand_pdata.cs = onenandcs; + + if (platform_device_register(&igep3_onenand_device) < 0) + pr_err("IGEP3: Unable to register OneNAND device\n"); +} + +#else +void __init igep3_flash_init(void) {} +#endif + +static struct regulator_consumer_supply igep3_vmmc1_supply = { + .supply = "vmmc", +}; + +/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ +static struct regulator_init_data igep3_vmmc1 = { + .constraints = { + .min_uV = 1850000, + .max_uV = 3150000, + .valid_modes_mask = REGULATOR_MODE_NORMAL + | REGULATOR_MODE_STANDBY, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE + | REGULATOR_CHANGE_MODE + | REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &igep3_vmmc1_supply, +}; + +static struct omap2_hsmmc_info mmc[] = { + [0] = { + .mmc = 1, + .caps = MMC_CAP_4_BIT_DATA, + .gpio_cd = -EINVAL, + .gpio_wp = -EINVAL, + }, +#if defined(CONFIG_LIBERTAS_SDIO) || defined(CONFIG_LIBERTAS_SDIO_MODULE) + [1] = { + .mmc = 2, + .caps = MMC_CAP_4_BIT_DATA, + .gpio_cd = -EINVAL, + .gpio_wp = -EINVAL, + }, +#endif + {} /* Terminator */ +}; + +#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) +#include + +static struct gpio_led igep3_gpio_leds[] = { + [0] = { + .name = "gpio-led:red:d0", + .gpio = IGEP3_GPIO_LED0_RED, + .default_trigger = "default-off" + }, + [1] = { + .name = "gpio-led:green:d0", + .gpio = IGEP3_GPIO_LED0_GREEN, + .default_trigger = "default-off", + }, + [2] = { + .name = "gpio-led:red:d1", + .gpio = IGEP3_GPIO_LED1_RED, + .default_trigger = "default-off", + }, + [3] = { + .name = "gpio-led:green:d1", + .default_trigger = "heartbeat", + .gpio = -EINVAL, /* gets replaced */ + }, +}; + +static struct gpio_led_platform_data igep3_led_pdata = { + .leds = igep3_gpio_leds, + .num_leds = ARRAY_SIZE(igep3_gpio_leds), +}; + +static struct platform_device igep3_led_device = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &igep3_led_pdata, + }, +}; + +static void __init igep3_leds_init(void) +{ + platform_device_register(&igep3_led_device); +} + +#else +static inline void igep3_leds_init(void) +{ + if ((gpio_request(IGEP3_GPIO_LED0_RED, "gpio-led:red:d0") == 0) && + (gpio_direction_output(IGEP3_GPIO_LED0_RED, 1) == 0)) { + gpio_export(IGEP3_GPIO_LED0_RED, 0); + gpio_set_value(IGEP3_GPIO_LED0_RED, 1); + } else + pr_warning("IGEP3: Could not obtain gpio GPIO_LED0_RED\n"); + + if ((gpio_request(IGEP3_GPIO_LED0_GREEN, "gpio-led:green:d0") == 0) && + (gpio_direction_output(IGEP3_GPIO_LED0_GREEN, 1) == 0)) { + gpio_export(IGEP3_GPIO_LED0_GREEN, 0); + gpio_set_value(IGEP3_GPIO_LED0_GREEN, 1); + } else + pr_warning("IGEP3: Could not obtain gpio GPIO_LED0_GREEN\n"); + + if ((gpio_request(IGEP3_GPIO_LED1_RED, "gpio-led:red:d1") == 0) && + (gpio_direction_output(IGEP3_GPIO_LED1_RED, 1) == 0)) { + gpio_export(IGEP3_GPIO_LED1_RED, 0); + gpio_set_value(IGEP3_GPIO_LED1_RED, 1); + } else + pr_warning("IGEP3: Could not obtain gpio GPIO_LED1_RED\n"); +} +#endif + +static int igep3_twl4030_gpio_setup(struct device *dev, + unsigned gpio, unsigned ngpio) +{ + /* gpio + 0 is "mmc0_cd" (input/IRQ) */ + mmc[0].gpio_cd = gpio + 0; + omap2_hsmmc_init(mmc); + + /* + * link regulators to MMC adapters ... we "know" the + * regulators will be set up only *after* we return. + */ + igep3_vmmc1_supply.dev = mmc[0].dev; + + /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */ +#if !defined(CONFIG_LEDS_GPIO) && !defined(CONFIG_LEDS_GPIO_MODULE) + if ((gpio_request(gpio+TWL4030_GPIO_MAX+1, "gpio-led:green:d1") == 0) + && (gpio_direction_output(gpio + TWL4030_GPIO_MAX + 1, 1) == 0)) { + gpio_export(gpio + TWL4030_GPIO_MAX + 1, 0); + gpio_set_value(gpio + TWL4030_GPIO_MAX + 1, 0); + } else + pr_warning("IGEP3: Could not obtain gpio GPIO_LED1_GREEN\n"); +#else + igep3_gpio_leds[3].gpio = gpio + TWL4030_GPIO_MAX + 1; +#endif + + return 0; +}; + +static struct twl4030_gpio_platform_data igep3_twl4030_gpio_pdata = { + .gpio_base = OMAP_MAX_GPIO_LINES, + .irq_base = TWL4030_GPIO_IRQ_BASE, + .irq_end = TWL4030_GPIO_IRQ_END, + .use_leds = true, + .setup = igep3_twl4030_gpio_setup, +}; + +static struct twl4030_usb_data igep3_twl4030_usb_data = { + .usb_mode = T2_USB_MODE_ULPI, +}; + +static void __init igep3_init_irq(void) +{ + omap2_init_common_hw(m65kxxxxam_sdrc_params, m65kxxxxam_sdrc_params); + omap_init_irq(); + omap_gpio_init(); +} + +static struct twl4030_platform_data igep3_twl4030_pdata = { + .irq_base = TWL4030_IRQ_BASE, + .irq_end = TWL4030_IRQ_END, + + /* platform_data for children goes here */ + .usb = &igep3_twl4030_usb_data, + .gpio = &igep3_twl4030_gpio_pdata, + .vmmc1 = &igep3_vmmc1, +}; + +static struct i2c_board_info __initdata igep3_i2c_boardinfo[] = { + { + I2C_BOARD_INFO("twl4030", 0x48), + .flags = I2C_CLIENT_WAKE, + .irq = INT_34XX_SYS_NIRQ, + .platform_data = &igep3_twl4030_pdata, + }, +}; + +static int __init igep3_i2c_init(void) +{ + omap_register_i2c_bus(1, 2600, igep3_i2c_boardinfo, + ARRAY_SIZE(igep3_i2c_boardinfo)); + + return 0; +} + +static struct omap_musb_board_data musb_board_data = { + .interface_type = MUSB_INTERFACE_ULPI, + .mode = MUSB_OTG, + .power = 100, +}; + +#if defined(CONFIG_LIBERTAS_SDIO) || defined(CONFIG_LIBERTAS_SDIO_MODULE) + +static void __init igep3_wifi_bt_init(void) +{ + /* Configure MUX values for W-LAN + Bluetooth GPIO's */ + omap_mux_init_gpio(IGEP3_GPIO_WIFI_NPD, OMAP_PIN_OUTPUT); + omap_mux_init_gpio(IGEP3_GPIO_WIFI_NRESET, OMAP_PIN_OUTPUT); + omap_mux_init_gpio(IGEP3_GPIO_BT_NRESET, OMAP_PIN_OUTPUT); + + /* Set GPIO's for W-LAN + Bluetooth combo module */ + if ((gpio_request(IGEP3_GPIO_WIFI_NPD, "GPIO_WIFI_NPD") == 0) && + (gpio_direction_output(IGEP3_GPIO_WIFI_NPD, 1) == 0)) { + gpio_export(IGEP3_GPIO_WIFI_NPD, 0); + } else + pr_warning("IGEP3: Could not obtain gpio GPIO_WIFI_NPD\n"); + + if ((gpio_request(IGEP3_GPIO_WIFI_NRESET, "GPIO_WIFI_NRESET") == 0) && + (gpio_direction_output(IGEP3_GPIO_WIFI_NRESET, 1) == 0)) { + gpio_export(IGEP3_GPIO_WIFI_NRESET, 0); + gpio_set_value(IGEP3_GPIO_WIFI_NRESET, 0); + udelay(10); + gpio_set_value(IGEP3_GPIO_WIFI_NRESET, 1); + } else + pr_warning("IGEP3: Could not obtain gpio GPIO_WIFI_NRESET\n"); + + if ((gpio_request(IGEP3_GPIO_BT_NRESET, "GPIO_BT_NRESET") == 0) && + (gpio_direction_output(IGEP3_GPIO_BT_NRESET, 1) == 0)) { + gpio_export(IGEP3_GPIO_BT_NRESET, 0); + } else + pr_warning("IGEP3: Could not obtain gpio GPIO_BT_NRESET\n"); +} +#else +void __init igep3_wifi_bt_init(void) {} +#endif + +#ifdef CONFIG_OMAP_MUX +static struct omap_board_mux board_mux[] __initdata = { + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; +#else +#define board_mux NULL +#endif + +static void __init igep3_init(void) +{ + omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); + + /* Register I2C busses and drivers */ + igep3_i2c_init(); + + omap_serial_init(); + usb_musb_init(&musb_board_data); + + igep3_flash_init(); + igep3_leds_init(); + + /* + * WLAN-BT combo module from MuRata wich has a Marvell WLAN + * (88W8686) + CSR Bluetooth chipset. Uses SDIO interface. + */ + igep3_wifi_bt_init(); + +} + +MACHINE_START(IGEP0030, "IGEP OMAP3 module") + .phys_io = 0x48000000, + .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc, + .boot_params = 0x80000100, + .map_io = omap3_map_io, + .init_irq = igep3_init_irq, + .init_machine = igep3_init, + .timer = &omap_timer, +MACHINE_END diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h index 2769395..9036e37 100644 --- a/arch/arm/plat-omap/include/plat/uncompress.h +++ b/arch/arm/plat-omap/include/plat/uncompress.h @@ -146,6 +146,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id) DEBUG_LL_OMAP3(3, cm_t35); DEBUG_LL_OMAP3(3, cm_t3517); DEBUG_LL_OMAP3(3, igep0020); + DEBUG_LL_OMAP3(3, igep0030); DEBUG_LL_OMAP3(3, nokia_rx51); DEBUG_LL_OMAP3(3, omap3517evm); DEBUG_LL_OMAP3(3, omap3_beagle); -- cgit v1.1 From 61e118dd7755417c541a8ecf32a82c3971258cff Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Fri, 8 Oct 2010 10:22:19 -0700 Subject: omap3: Add external VBUS power switch and overcurrent detect onIGEP v2 board GPIO for various devices are missing from the board initialization. This patch adds support for the VBUS and over current gpios. Without this patch, input/outputs from these two sources are ignored. Signed-off-by: Enric Balletbo i Serra Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-igep0020.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index c437031..2f40d77 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -275,6 +275,22 @@ static int igep2_twl_gpio_setup(struct device *dev, igep2_vmmc1_supply.dev = mmc[0].dev; igep2_vmmc2_supply.dev = mmc[1].dev; + /* + * REVISIT: need ehci-omap hooks for external VBUS + * power switch and overcurrent detect + */ + if ((gpio_request(gpio + 1, "GPIO_EHCI_NOC") < 0) || + (gpio_direction_input(gpio + 1) < 0)) + pr_err("IGEP2: Could not obtain gpio for EHCI NOC"); + + /* + * TWL4030_GPIO_MAX + 0 == ledA, GPIO_USBH_CPEN + * (out, active low) + */ + if ((gpio_request(gpio + TWL4030_GPIO_MAX, "GPIO_USBH_CPEN") < 0) || + (gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0) < 0)) + pr_err("IGEP2: Could not obtain gpio for USBH_CPEN"); + return 0; }; -- cgit v1.1 From bee153906424f3bf669afec397c810b76117e22b Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Fri, 8 Oct 2010 10:22:28 -0700 Subject: omap3: fix and improve the LED handling on IGEP v2 board The IGEP v2 board has four leds, this patch allows control all of these LEDs using the LED class if CONFIG_LEDS_GPIO is selected or using the General Purpose Input/Output (GPIO) interface if CONFIG_LEDS_GPIO is not selected. Signed-off-by: Enric Balletbo i Serra Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-igep0020.c | 156 +++++++++++++++++++---------------- 1 file changed, 87 insertions(+), 69 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index 2f40d77..d7a0db7 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -262,6 +262,77 @@ static struct omap2_hsmmc_info mmc[] = { {} /* Terminator */ }; +#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) +#include + +static struct gpio_led igep2_gpio_leds[] = { + [0] = { + .name = "gpio-led:red:d0", + .gpio = IGEP2_GPIO_LED0_RED, + .default_trigger = "default-off" + }, + [1] = { + .name = "gpio-led:green:d0", + .gpio = IGEP2_GPIO_LED0_GREEN, + .default_trigger = "default-off", + }, + [2] = { + .name = "gpio-led:red:d1", + .gpio = IGEP2_GPIO_LED1_RED, + .default_trigger = "default-off", + }, + [3] = { + .name = "gpio-led:green:d1", + .default_trigger = "heartbeat", + .gpio = -EINVAL, /* gets replaced */ + }, +}; + +static struct gpio_led_platform_data igep2_led_pdata = { + .leds = igep2_gpio_leds, + .num_leds = ARRAY_SIZE(igep2_gpio_leds), +}; + +static struct platform_device igep2_led_device = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &igep2_led_pdata, + }, +}; + +static void __init igep2_leds_init(void) +{ + platform_device_register(&igep2_led_device); +} + +#else +static inline void igep2_leds_init(void) +{ + if ((gpio_request(IGEP2_GPIO_LED0_RED, "gpio-led:red:d0") == 0) && + (gpio_direction_output(IGEP2_GPIO_LED0_RED, 1) == 0)) { + gpio_export(IGEP2_GPIO_LED0_RED, 0); + gpio_set_value(IGEP2_GPIO_LED0_RED, 0); + } else + pr_warning("IGEP v2: Could not obtain gpio GPIO_LED0_RED\n"); + + if ((gpio_request(IGEP2_GPIO_LED0_GREEN, "gpio-led:green:d0") == 0) && + (gpio_direction_output(IGEP2_GPIO_LED0_GREEN, 1) == 0)) { + gpio_export(IGEP2_GPIO_LED0_GREEN, 0); + gpio_set_value(IGEP2_GPIO_LED0_GREEN, 0); + } else + pr_warning("IGEP v2: Could not obtain gpio GPIO_LED0_GREEN\n"); + + if ((gpio_request(IGEP2_GPIO_LED1_RED, "gpio-led:red:d1") == 0) && + (gpio_direction_output(IGEP2_GPIO_LED1_RED, 1) == 0)) { + gpio_export(IGEP2_GPIO_LED1_RED, 0); + gpio_set_value(IGEP2_GPIO_LED1_RED, 0); + } else + pr_warning("IGEP v2: Could not obtain gpio GPIO_LED1_RED\n"); + +} +#endif + static int igep2_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio) { @@ -291,14 +362,26 @@ static int igep2_twl_gpio_setup(struct device *dev, (gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0) < 0)) pr_err("IGEP2: Could not obtain gpio for USBH_CPEN"); + /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */ +#if !defined(CONFIG_LEDS_GPIO) && !defined(CONFIG_LEDS_GPIO_MODULE) + if ((gpio_request(gpio+TWL4030_GPIO_MAX+1, "gpio-led:green:d1") == 0) + && (gpio_direction_output(gpio + TWL4030_GPIO_MAX + 1, 1) == 0)) { + gpio_export(gpio + TWL4030_GPIO_MAX + 1, 0); + gpio_set_value(gpio + TWL4030_GPIO_MAX + 1, 0); + } else + pr_warning("IGEP v2: Could not obtain gpio GPIO_LED1_GREEN\n"); +#else + igep2_gpio_leds[3].gpio = gpio + TWL4030_GPIO_MAX + 1; +#endif + return 0; }; -static struct twl4030_gpio_platform_data igep2_gpio_data = { +static struct twl4030_gpio_platform_data igep2_twl4030_gpio_pdata = { .gpio_base = OMAP_MAX_GPIO_LINES, .irq_base = TWL4030_GPIO_IRQ_BASE, .irq_end = TWL4030_GPIO_IRQ_END, - .use_leds = false, + .use_leds = true, .setup = igep2_twl_gpio_setup, }; @@ -372,47 +455,6 @@ static void __init igep2_display_init(void) pr_err("IGEP v2: Could not obtain gpio GPIO_DVI_PUP\n"); } -#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) -#include - -static struct gpio_led igep2_gpio_leds[] = { - { - .name = "led0:red", - .gpio = IGEP2_GPIO_LED0_RED, - }, - { - .name = "led0:green", - .default_trigger = "heartbeat", - .gpio = IGEP2_GPIO_LED0_GREEN, - }, - { - .name = "led1:red", - .gpio = IGEP2_GPIO_LED1_RED, - }, -}; - -static struct gpio_led_platform_data igep2_led_pdata = { - .leds = igep2_gpio_leds, - .num_leds = ARRAY_SIZE(igep2_gpio_leds), -}; - -static struct platform_device igep2_led_device = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &igep2_led_pdata, - }, -}; - -static void __init igep2_init_led(void) -{ - platform_device_register(&igep2_led_device); -} - -#else -static inline void igep2_init_led(void) {} -#endif - static struct platform_device *igep2_devices[] __initdata = { &igep2_dss_device, }; @@ -442,7 +484,7 @@ static struct twl4030_platform_data igep2_twldata = { /* platform_data for children goes here */ .usb = &igep2_usb_data, .codec = &igep2_codec_data, - .gpio = &igep2_gpio_data, + .gpio = &igep2_twl4030_gpio_pdata, .vmmc1 = &igep2_vmmc1, .vmmc2 = &igep2_vmmc2, .vpll2 = &igep2_vpll2, @@ -503,34 +545,10 @@ static void __init igep2_init(void) usb_ehci_init(&ehci_pdata); igep2_flash_init(); - igep2_init_led(); + igep2_leds_init(); igep2_display_init(); igep2_init_smsc911x(); - /* GPIO userspace leds */ -#if !defined(CONFIG_LEDS_GPIO) && !defined(CONFIG_LEDS_GPIO_MODULE) - if ((gpio_request(IGEP2_GPIO_LED0_RED, "led0:red") == 0) && - (gpio_direction_output(IGEP2_GPIO_LED0_RED, 1) == 0)) { - gpio_export(IGEP2_GPIO_LED0_RED, 0); - gpio_set_value(IGEP2_GPIO_LED0_RED, 0); - } else - pr_warning("IGEP v2: Could not obtain gpio GPIO_LED0_RED\n"); - - if ((gpio_request(IGEP2_GPIO_LED0_GREEN, "led0:green") == 0) && - (gpio_direction_output(IGEP2_GPIO_LED0_GREEN, 1) == 0)) { - gpio_export(IGEP2_GPIO_LED0_GREEN, 0); - gpio_set_value(IGEP2_GPIO_LED0_GREEN, 0); - } else - pr_warning("IGEP v2: Could not obtain gpio GPIO_LED0_GREEN\n"); - - if ((gpio_request(IGEP2_GPIO_LED1_RED, "led1:red") == 0) && - (gpio_direction_output(IGEP2_GPIO_LED1_RED, 1) == 0)) { - gpio_export(IGEP2_GPIO_LED1_RED, 0); - gpio_set_value(IGEP2_GPIO_LED1_RED, 0); - } else - pr_warning("IGEP v2: Could not obtain gpio GPIO_LED1_RED\n"); -#endif - /* GPIO W-LAN + Bluetooth combo module */ if ((gpio_request(IGEP2_GPIO_WIFI_NPD, "GPIO_WIFI_NPD") == 0) && (gpio_direction_output(IGEP2_GPIO_WIFI_NPD, 1) == 0)) { -- cgit v1.1 From 3f8c48d95f8e4ed3ea241c3e8704b5ff6c423fa4 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Fri, 8 Oct 2010 10:22:35 -0700 Subject: omap3: Introduce function to detect the IGEP v2 hardwarerevision There are currently two versions of IGEP v2 board, this patch introduces a function to detect the hardware revision of IGEP board. -------------------------- | Id. | Hw Rev. | GPIO 28 | -------------------------- | 0 | B/C | high | | 1 | C | low | -------------------------- Signed-off-by: Enric Balletbo i Serra Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-igep0020.c | 47 ++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index d7a0db7..e70bc87 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -46,6 +46,49 @@ #define IGEP2_GPIO_WIFI_NPD 94 #define IGEP2_GPIO_WIFI_NRESET 95 +/* + * IGEP2 Hardware Revision Table + * + * -------------------------- + * | Id. | Hw Rev. | HW0 (28) | + * -------------------------- + * | 0 | B/C | high | + * | 1 | C | low | + * -------------------------- + */ + +#define IGEP2_BOARD_HWREV_B 0 +#define IGEP2_BOARD_HWREV_C 1 + +static u8 hwrev; + +static void __init igep2_get_revision(void) +{ + u8 ret; + + omap_mux_init_gpio(IGEP2_GPIO_LED1_RED, OMAP_PIN_INPUT); + + if ((gpio_request(IGEP2_GPIO_LED1_RED, "GPIO_HW0_REV") == 0) && + (gpio_direction_input(IGEP2_GPIO_LED1_RED) == 0)) { + ret = gpio_get_value(IGEP2_GPIO_LED1_RED); + if (ret == 0) { + pr_info("IGEP2: Hardware Revision C (B-NON compatible)\n"); + hwrev = IGEP2_BOARD_HWREV_C; + } else if (ret == 1) { + pr_info("IGEP2: Hardware Revision B/C (B compatible)\n"); + hwrev = IGEP2_BOARD_HWREV_B; + } else { + pr_err("IGEP2: Unknown Hardware Revision\n"); + hwrev = -1; + } + } else { + pr_warning("IGEP2: Could not obtain gpio GPIO_HW0_REV\n"); + pr_err("IGEP2: Unknown Hardware Revision\n"); + } + + gpio_free(IGEP2_GPIO_LED1_RED); +} + #if defined(CONFIG_MTD_ONENAND_OMAP2) || \ defined(CONFIG_MTD_ONENAND_OMAP2_MODULE) @@ -538,6 +581,10 @@ static struct omap_board_mux board_mux[] __initdata = { static void __init igep2_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); + + /* Get IGEP2 hardware revision */ + igep2_get_revision(); + igep2_i2c_init(); platform_add_devices(igep2_devices, ARRAY_SIZE(igep2_devices)); omap_serial_init(); -- cgit v1.1 From 5a9fcc9980ae741c4657029c7e92d914072f824a Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Fri, 8 Oct 2010 10:22:43 -0700 Subject: omap3: Fix handling some GPIO's for WLAN-BT combo on IGEP v2 Some GPIO's used by WLAN-BT combo on IGEP v2 depends on hardware revision. This patch handles these GPIO's. ---------------------------------------------------------- | Hw Rev. | WIFI_NPD | WIFI_NRESET | BT_NRESET | ---------------------------------------------------------- | B | gpio94 | gpio95 | - | | B/C (B-compatible) | gpio94 | gpio95 | gpio137 | | C | gpio138 | gpio139 | gpio137 | ---------------------------------------------------------- Signed-off-by: Enric Balletbo i Serra Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-igep0020.c | 96 ++++++++++++++++++++++++++---------- 1 file changed, 69 insertions(+), 27 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index e70bc87..22f73b4 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -39,22 +39,28 @@ #define IGEP2_SMSC911X_CS 5 #define IGEP2_SMSC911X_GPIO 176 #define IGEP2_GPIO_USBH_NRESET 24 -#define IGEP2_GPIO_LED0_GREEN 26 -#define IGEP2_GPIO_LED0_RED 27 -#define IGEP2_GPIO_LED1_RED 28 -#define IGEP2_GPIO_DVI_PUP 170 -#define IGEP2_GPIO_WIFI_NPD 94 -#define IGEP2_GPIO_WIFI_NRESET 95 +#define IGEP2_GPIO_LED0_GREEN 26 +#define IGEP2_GPIO_LED0_RED 27 +#define IGEP2_GPIO_LED1_RED 28 +#define IGEP2_GPIO_DVI_PUP 170 + +#define IGEP2_RB_GPIO_WIFI_NPD 94 +#define IGEP2_RB_GPIO_WIFI_NRESET 95 +#define IGEP2_RB_GPIO_BT_NRESET 137 +#define IGEP2_RC_GPIO_WIFI_NPD 138 +#define IGEP2_RC_GPIO_WIFI_NRESET 139 +#define IGEP2_RC_GPIO_BT_NRESET 137 /* * IGEP2 Hardware Revision Table * - * -------------------------- - * | Id. | Hw Rev. | HW0 (28) | - * -------------------------- - * | 0 | B/C | high | - * | 1 | C | low | - * -------------------------- + * -------------------------------------------------------------------------- + * | Id. | Hw Rev. | HW0 (28) | WIFI_NPD | WIFI_NRESET | BT_NRESET | + * -------------------------------------------------------------------------- + * | 0 | B | high | gpio94 | gpio95 | - | + * | 0 | B/C (B-compatible) | high | gpio94 | gpio95 | gpio137 | + * | 1 | C | low | gpio138 | gpio139 | gpio137 | + * -------------------------------------------------------------------------- */ #define IGEP2_BOARD_HWREV_B 0 @@ -296,12 +302,14 @@ static struct omap2_hsmmc_info mmc[] = { .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, }, +#if defined(CONFIG_LIBERTAS_SDIO) || defined(CONFIG_LIBERTAS_SDIO_MODULE) { .mmc = 2, .caps = MMC_CAP_4_BIT_DATA, .gpio_cd = -EINVAL, .gpio_wp = -EINVAL, }, +#endif {} /* Terminator */ }; @@ -578,6 +586,50 @@ static struct omap_board_mux board_mux[] __initdata = { #define board_mux NULL #endif +#if defined(CONFIG_LIBERTAS_SDIO) || defined(CONFIG_LIBERTAS_SDIO_MODULE) + +static void __init igep2_wlan_bt_init(void) +{ + unsigned npd, wreset, btreset; + + /* GPIO's for WLAN-BT combo depends on hardware revision */ + if (hwrev == IGEP2_BOARD_HWREV_B) { + npd = IGEP2_RB_GPIO_WIFI_NPD; + wreset = IGEP2_RB_GPIO_WIFI_NRESET; + btreset = IGEP2_RB_GPIO_BT_NRESET; + } else if (hwrev == IGEP2_BOARD_HWREV_C) { + npd = IGEP2_RC_GPIO_WIFI_NPD; + wreset = IGEP2_RC_GPIO_WIFI_NRESET; + btreset = IGEP2_RC_GPIO_BT_NRESET; + } else + return; + + /* Set GPIO's for WLAN-BT combo module */ + if ((gpio_request(npd, "GPIO_WIFI_NPD") == 0) && + (gpio_direction_output(npd, 1) == 0)) { + gpio_export(npd, 0); + } else + pr_warning("IGEP2: Could not obtain gpio GPIO_WIFI_NPD\n"); + + if ((gpio_request(wreset, "GPIO_WIFI_NRESET") == 0) && + (gpio_direction_output(wreset, 1) == 0)) { + gpio_export(wreset, 0); + gpio_set_value(wreset, 0); + udelay(10); + gpio_set_value(wreset, 1); + } else + pr_warning("IGEP2: Could not obtain gpio GPIO_WIFI_NRESET\n"); + + if ((gpio_request(btreset, "GPIO_BT_NRESET") == 0) && + (gpio_direction_output(btreset, 1) == 0)) { + gpio_export(btreset, 0); + } else + pr_warning("IGEP2: Could not obtain gpio GPIO_BT_NRESET\n"); +} +#else +static inline void __init igep2_wlan_bt_init(void) { } +#endif + static void __init igep2_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); @@ -596,22 +648,12 @@ static void __init igep2_init(void) igep2_display_init(); igep2_init_smsc911x(); - /* GPIO W-LAN + Bluetooth combo module */ - if ((gpio_request(IGEP2_GPIO_WIFI_NPD, "GPIO_WIFI_NPD") == 0) && - (gpio_direction_output(IGEP2_GPIO_WIFI_NPD, 1) == 0)) { - gpio_export(IGEP2_GPIO_WIFI_NPD, 0); -/* gpio_set_value(IGEP2_GPIO_WIFI_NPD, 0); */ - } else - pr_warning("IGEP v2: Could not obtain gpio GPIO_WIFI_NPD\n"); + /* + * WLAN-BT combo module from MuRata wich has a Marvell WLAN + * (88W8686) + CSR Bluetooth chipset. Uses SDIO interface. + */ + igep2_wlan_bt_init(); - if ((gpio_request(IGEP2_GPIO_WIFI_NRESET, "GPIO_WIFI_NRESET") == 0) && - (gpio_direction_output(IGEP2_GPIO_WIFI_NRESET, 1) == 0)) { - gpio_export(IGEP2_GPIO_WIFI_NRESET, 0); - gpio_set_value(IGEP2_GPIO_WIFI_NRESET, 0); - udelay(10); - gpio_set_value(IGEP2_GPIO_WIFI_NRESET, 1); - } else - pr_warning("IGEP v2: Could not obtain gpio GPIO_WIFI_NRESET\n"); } MACHINE_START(IGEP0020, "IGEP v2 board") -- cgit v1.1 From 91d139cf3630eff73f161494ee0c596472c11fef Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Fri, 8 Oct 2010 10:22:51 -0700 Subject: omap3: Add i2c eeprom driver to read EDID on IGEP v2 Add i2c eeprom driver to access monitor EDID binary information from user space, something that is required by 'decode-edid' and 'parse-edid'. Signed-off-by: Enric Balletbo i Serra Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-igep0020.c | 33 ++++++++++++++++++++++++--------- 1 file changed, 24 insertions(+), 9 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index 22f73b4..cfd67bf 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -542,7 +542,7 @@ static struct twl4030_platform_data igep2_twldata = { }; -static struct i2c_board_info __initdata igep2_i2c_boardinfo[] = { +static struct i2c_board_info __initdata igep2_i2c1_boardinfo[] = { { I2C_BOARD_INFO("twl4030", 0x48), .flags = I2C_CLIENT_WAKE, @@ -551,14 +551,29 @@ static struct i2c_board_info __initdata igep2_i2c_boardinfo[] = { }, }; -static int __init igep2_i2c_init(void) +static struct i2c_board_info __initdata igep2_i2c3_boardinfo[] = { + { + I2C_BOARD_INFO("eeprom", 0x50), + }, +}; + +static void __init igep2_i2c_init(void) { - omap_register_i2c_bus(1, 2600, igep2_i2c_boardinfo, - ARRAY_SIZE(igep2_i2c_boardinfo)); - /* Bus 3 is attached to the DVI port where devices like the pico DLP - * projector don't work reliably with 400kHz */ - omap_register_i2c_bus(3, 100, NULL, 0); - return 0; + int ret; + + ret = omap_register_i2c_bus(1, 2600, igep2_i2c1_boardinfo, + ARRAY_SIZE(igep2_i2c1_boardinfo)); + if (ret) + pr_warning("IGEP2: Could not register I2C1 bus (%d)\n", ret); + + /* + * Bus 3 is attached to the DVI port where devices like the pico DLP + * projector don't work reliably with 400kHz + */ + ret = omap_register_i2c_bus(3, 100, igep2_i2c3_boardinfo, + ARRAY_SIZE(igep2_i2c3_boardinfo)); + if (ret) + pr_warning("IGEP2: Could not register I2C3 bus (%d)\n", ret); } static struct omap_musb_board_data musb_board_data = { @@ -636,7 +651,7 @@ static void __init igep2_init(void) /* Get IGEP2 hardware revision */ igep2_get_revision(); - + /* Register I2C busses and drivers */ igep2_i2c_init(); platform_add_devices(igep2_devices, ARRAY_SIZE(igep2_devices)); omap_serial_init(); -- cgit v1.1 From 72f381ba0565b358dc10c67ff47728a2c9aa5457 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Fri, 8 Oct 2010 10:22:57 -0700 Subject: omap3: Remove VMMC2 regulator on IGEP v2 VMMC2 regulator is configured but it's not used for the IGEP v2, so remove this regulator from board. Signed-off-by: Enric Balletbo i Serra Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-igep0020.c | 26 +++----------------------- 1 file changed, 3 insertions(+), 23 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index cfd67bf..152f7577 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -261,10 +261,6 @@ static struct regulator_consumer_supply igep2_vmmc1_supply = { .supply = "vmmc", }; -static struct regulator_consumer_supply igep2_vmmc2_supply = { - .supply = "vmmc", -}; - /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ static struct regulator_init_data igep2_vmmc1 = { .constraints = { @@ -280,21 +276,6 @@ static struct regulator_init_data igep2_vmmc1 = { .consumer_supplies = &igep2_vmmc1_supply, }; -/* VMMC2 for OMAP VDD_MMC2 (i/o) and MMC2 WIFI */ -static struct regulator_init_data igep2_vmmc2 = { - .constraints = { - .min_uV = 1850000, - .max_uV = 3150000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE - | REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &igep2_vmmc2_supply, -}; - static struct omap2_hsmmc_info mmc[] = { { .mmc = 1, @@ -391,11 +372,11 @@ static int igep2_twl_gpio_setup(struct device *dev, mmc[0].gpio_cd = gpio + 0; omap2_hsmmc_init(mmc); - /* link regulators to MMC adapters ... we "know" the + /* + * link regulators to MMC adapters ... we "know" the * regulators will be set up only *after* we return. - */ + */ igep2_vmmc1_supply.dev = mmc[0].dev; - igep2_vmmc2_supply.dev = mmc[1].dev; /* * REVISIT: need ehci-omap hooks for external VBUS @@ -537,7 +518,6 @@ static struct twl4030_platform_data igep2_twldata = { .codec = &igep2_codec_data, .gpio = &igep2_twl4030_gpio_pdata, .vmmc1 = &igep2_vmmc1, - .vmmc2 = &igep2_vmmc2, .vpll2 = &igep2_vpll2, }; -- cgit v1.1 From 20252d46597e457b7506f28be05478be457b8c4f Mon Sep 17 00:00:00 2001 From: Charulatha V Date: Fri, 8 Oct 2010 10:23:06 -0700 Subject: OMAP2PLUS: WDT: Fix: Disable WDT after reset during init Inorder to avoid any assumptions from bootloader, the watchdog timer module is reset during init. This enables the watchdog timer. Therefore, it is required to disable WDT after it is reset during init. Otherwise the system would reboot as per the default watchdog timer registers settings. Later, when the watchdog driver is loaded, the watchdog timer settings is adjusted as per the default timer_margin set in the driver and the driver would supports the normal operations supported by OMAP watchdog timer. Signed-off-by: Charulatha V Reported-by: Kevin Hilman Acked-by: Kevin Hilman Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/devices.c | 61 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 5eb0b58..818452a 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -914,11 +914,72 @@ static inline void omap_init_vout(void) {} /*-------------------------------------------------------------------------*/ +/* + * Inorder to avoid any assumptions from bootloader regarding WDT + * settings, WDT module is reset during init. This enables the watchdog + * timer. Hence it is required to disable the watchdog after the WDT reset + * during init. Otherwise the system would reboot as per the default + * watchdog timer registers settings. + */ +#define OMAP_WDT_WPS (0x34) +#define OMAP_WDT_SPR (0x48) + +static int omap2_disable_wdt(struct omap_hwmod *oh, void *unused) +{ + void __iomem *base; + int ret; + + if (!oh) { + pr_err("%s: Could not look up wdtimer_hwmod\n", __func__); + return -EINVAL; + } + + base = omap_hwmod_get_mpu_rt_va(oh); + if (!base) { + pr_err("%s: Could not get the base address for %s\n", + oh->name, __func__); + return -EINVAL; + } + + /* Enable the clocks before accessing the WDT registers */ + ret = omap_hwmod_enable(oh); + if (ret) { + pr_err("%s: Could not enable clocks for %s\n", + oh->name, __func__); + return ret; + } + + /* sequence required to disable watchdog */ + __raw_writel(0xAAAA, base + OMAP_WDT_SPR); + while (__raw_readl(base + OMAP_WDT_WPS) & 0x10) + cpu_relax(); + + __raw_writel(0x5555, base + OMAP_WDT_SPR); + while (__raw_readl(base + OMAP_WDT_WPS) & 0x10) + cpu_relax(); + + ret = omap_hwmod_idle(oh); + if (ret) + pr_err("%s: Could not disable clocks for %s\n", + oh->name, __func__); + + return ret; +} + +static void __init omap_disable_wdt(void) +{ + if (cpu_class_is_omap2()) + omap_hwmod_for_each_by_class("wd_timer", + omap2_disable_wdt, NULL); + return; +} + static int __init omap2_init_devices(void) { /* please keep these calls, and their implementations above, * in alphabetical order so they're easier to sort through. */ + omap_disable_wdt(); omap_hsmmc_reset(); omap_init_camera(); omap_init_mbox(); -- cgit v1.1 From c710e19222794f45f2376ba6f00dc675dc4279d6 Mon Sep 17 00:00:00 2001 From: Nicolas Kaiser Date: Fri, 8 Oct 2010 10:23:14 -0700 Subject: arm/omap: remove duplicated include Remove duplicated include. Signed-off-by: Nicolas Kaiser Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-cm-t35.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index 2b328b9..16aceeb 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c @@ -238,8 +238,6 @@ static inline void cm_t35_init_nand(void) {} defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) #include -#include - static struct omap2_mcspi_device_config ads7846_mcspi_config = { .turbo_mode = 0, .single_channel = 1, /* 0: slave, 1: master */ -- cgit v1.1 From cc7a1d2a540a780066aa562c651a88dd28b6fc8a Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Fri, 8 Oct 2010 10:23:22 -0700 Subject: omap: hwmod: Handle modules with 16bit registers Some modules which have 16bit registers can cause imprecise aborts if a __raw_readl/writel is used to read/write 32 bits. Add an additional flag to identify modules which have such hard requirement, and handle it in the hwmod framework. Signed-off-by: Rajendra Nayak Acked-by: Paul Walmsley Tested-by: Kevin Hilman Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod.c | 24 +++++++++++++++--------- arch/arm/plat-omap/include/plat/omap_hwmod.h | 6 ++++-- 2 files changed, 19 insertions(+), 11 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 955861a..5a30658 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -184,7 +184,7 @@ static int _update_sysc_cache(struct omap_hwmod *oh) /* XXX ensure module interface clock is up */ - oh->_sysc_cache = omap_hwmod_readl(oh, oh->class->sysc->sysc_offs); + oh->_sysc_cache = omap_hwmod_read(oh, oh->class->sysc->sysc_offs); if (!(oh->class->sysc->sysc_flags & SYSC_NO_CACHE)) oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED; @@ -211,7 +211,7 @@ static void _write_sysconfig(u32 v, struct omap_hwmod *oh) if (oh->_sysc_cache != v) { oh->_sysc_cache = v; - omap_hwmod_writel(v, oh, oh->class->sysc->sysc_offs); + omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs); } } @@ -1133,12 +1133,12 @@ static int _reset(struct omap_hwmod *oh) _write_sysconfig(v, oh); if (oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS) - omap_test_timeout((omap_hwmod_readl(oh, + omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs) & SYSS_RESETDONE_MASK), MAX_MODULE_SOFTRESET_WAIT, c); else if (oh->class->sysc->sysc_flags & SYSC_HAS_RESET_STATUS) - omap_test_timeout(!(omap_hwmod_readl(oh, + omap_test_timeout(!(omap_hwmod_read(oh, oh->class->sysc->sysc_offs) & SYSC_TYPE2_SOFTRESET_MASK), MAX_MODULE_SOFTRESET_WAIT, c); @@ -1378,14 +1378,20 @@ static int _setup(struct omap_hwmod *oh, void *data) /* Public functions */ -u32 omap_hwmod_readl(struct omap_hwmod *oh, u16 reg_offs) +u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs) { - return __raw_readl(oh->_mpu_rt_va + reg_offs); + if (oh->flags & HWMOD_16BIT_REG) + return __raw_readw(oh->_mpu_rt_va + reg_offs); + else + return __raw_readl(oh->_mpu_rt_va + reg_offs); } -void omap_hwmod_writel(u32 v, struct omap_hwmod *oh, u16 reg_offs) +void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs) { - __raw_writel(v, oh->_mpu_rt_va + reg_offs); + if (oh->flags & HWMOD_16BIT_REG) + __raw_writew(v, oh->_mpu_rt_va + reg_offs); + else + __raw_writel(v, oh->_mpu_rt_va + reg_offs); } /** @@ -1732,7 +1738,7 @@ void omap_hwmod_ocp_barrier(struct omap_hwmod *oh) * Forces posted writes to complete on the OCP thread handling * register writes */ - omap_hwmod_readl(oh, oh->class->sysc->sysc_offs); + omap_hwmod_read(oh, oh->class->sysc->sysc_offs); } /** diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index c1835af..7eaa8ed 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -370,6 +370,7 @@ struct omap_hwmod_omap4_prcm { * This is needed for devices like DSS that require optional clocks enabled * in order to complete the reset. Optional clocks will be disabled * again after the reset. + * HWMOD_16BIT_REG: Module has 16bit registers */ #define HWMOD_SWSUP_SIDLE (1 << 0) #define HWMOD_SWSUP_MSTANDBY (1 << 1) @@ -379,6 +380,7 @@ struct omap_hwmod_omap4_prcm { #define HWMOD_SET_DEFAULT_CLOCKACT (1 << 5) #define HWMOD_NO_IDLEST (1 << 6) #define HWMOD_CONTROL_OPT_CLKS_IN_RESET (1 << 7) +#define HWMOD_16BIT_REG (1 << 8) /* * omap_hwmod._int_flags definitions @@ -527,8 +529,8 @@ int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode); int omap_hwmod_reset(struct omap_hwmod *oh); void omap_hwmod_ocp_barrier(struct omap_hwmod *oh); -void omap_hwmod_writel(u32 v, struct omap_hwmod *oh, u16 reg_offs); -u32 omap_hwmod_readl(struct omap_hwmod *oh, u16 reg_offs); +void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs); +u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs); int omap_hwmod_count_resources(struct omap_hwmod *oh); int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res); -- cgit v1.1 From 503923eeecb93ff69ee940549f314e0fe3a68429 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Fri, 8 Oct 2010 10:23:32 -0700 Subject: OMAP2: PM: check UART status before trying to idle As is done on OMAP3, check omap_uart_can_sleep() as one of the pre-conditions for entering the idle loop. Without this check, entering idle introduces large latencies on active UARTs, and is especially noticable on serial console. Signed-off-by: Kevin Hilman Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/pm24xx.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index 6aeedea..f5c7ef9 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -245,6 +245,8 @@ static int omap2_can_sleep(void) { if (omap2_fclks_active()) return 0; + if (!omap_uart_can_sleep()) + return 0; if (osc_ck->usecount > 1) return 0; if (omap_dma_running()) -- cgit v1.1 From 6f911492ed901dcafc9c5c7f507087bb94218ba7 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 8 Oct 2010 10:23:44 -0700 Subject: omap: Update omap2plus_defconfig to use ttyO instead ttyS With the omap-serial the device has changed from ttyS to ttyO as the system may have both omap-serial and 8250 ports. Note that systems using omap-serial need to be updated to use ttyO[012] instead of ttyS[012] in the bootloader, CONFIG_CMDLINE, /etc/inittab, and the root file system with mknod. Also you may need to add ttyO[012] to /etc/securetty. Signed-off-by: Tony Lindgren --- arch/arm/configs/omap2plus_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index 7deec89..ccedde1 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -63,7 +63,7 @@ CONFIG_AEABI=y CONFIG_LEDS=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="root=/dev/mmcblk0p2 rootwait console=ttyS2,115200" +CONFIG_CMDLINE="root=/dev/mmcblk0p2 rootwait console=ttyO2,115200" CONFIG_KEXEC=y CONFIG_FPE_NWFPE=y CONFIG_VFP=y -- cgit v1.1 From 6515e48932c8bf04227f9dd638c8ac634f89ba24 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Fri, 8 Oct 2010 11:40:17 -0600 Subject: OMAP2+: Kconfig: disallow builds for boards that don't use the currently-selected SoC Currently, if, for example, CONFIG_ARCH_OMAP2420 is not selected, OMAP2420 board files can still be included in the build. This results in link errors: arch/arm/mach-omap2/built-in.o: In function `omap_generic_map_io': .../arch/arm/mach-omap2/board-generic.c:51: undefined reference to `omap2_set_globals_242x' arch/arm/mach-omap2/built-in.o: In function `omap_h4_init': .../arch/arm/mach-omap2/board-h4.c:330: undefined reference to `omap2420_mux_init' arch/arm/mach-omap2/built-in.o: In function `omap_h4_map_io': .../arch/arm/mach-omap2/board-h4.c:373: undefined reference to `omap2_set_globals_242x' arch/arm/mach-omap2/built-in.o: In function `omap_apollon_init': .../arch/arm/mach-omap2/board-apollon.c:325: undefined reference to `omap2420_mux_init' arch/arm/mach-omap2/built-in.o: In function `omap_apollon_map_io': .../arch/arm/mach-omap2/board-apollon.c:353: undefined reference to `omap2_set_globals_242x' make: *** [.tmp_vmlinux1] Error 1 Fix this by making the boards depend on the Kconfig option for the specific SoC that they use. Also, while here, fix the mach-omap2/board-generic.c file to remove the dependency on OMAP2420. Charulatha Varadarajan caught a typo - thanks Charu. Signed-off-by: Paul Walmsley Cc: Tony Lindgren Cc: Charulatha Varadarajan --- arch/arm/mach-omap2/Kconfig | 6 +++--- arch/arm/mach-omap2/board-generic.c | 16 ++++++++++++++-- 2 files changed, 17 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 2b79b84..ab784bf 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -100,20 +100,20 @@ config MACH_OMAP2_TUSB6010 config MACH_OMAP_H4 bool "OMAP 2420 H4 board" - depends on ARCH_OMAP2 + depends on ARCH_OMAP2420 default y select OMAP_PACKAGE_ZAF select OMAP_DEBUG_DEVICES config MACH_OMAP_APOLLON bool "OMAP 2420 Apollon board" - depends on ARCH_OMAP2 + depends on ARCH_OMAP2420 default y select OMAP_PACKAGE_ZAC config MACH_OMAP_2430SDP bool "OMAP 2430 SDP board" - depends on ARCH_OMAP2 + depends on ARCH_OMAP2430 default y select OMAP_PACKAGE_ZAC diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 3482b99..8aee862 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -48,10 +48,22 @@ static void __init omap_generic_init(void) static void __init omap_generic_map_io(void) { - omap2_set_globals_242x(); /* should be 242x, 243x, or 343x */ - omap242x_map_common_io(); + if (cpu_is_omap242x()) { + omap2_set_globals_242x(); + omap242x_map_common_io(); + } else if (cpu_is_omap243x()) { + omap2_set_globals_243x(); + omap243x_map_common_io(); + } else if (cpu_is_omap34xx()) { + omap2_set_globals_3xxx(); + omap34xx_map_common_io(); + } else if (cpu_is_omap44xx()) { + omap2_set_globals_443x(); + omap44xx_map_common_io(); + } } +/* XXX This machine entry name should be updated */ MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx") /* Maintainer: Paul Mundt */ .phys_io = 0x48000000, -- cgit v1.1 From 54164bb2927edd9f183a108a0d037d80639c8429 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Fri, 8 Oct 2010 11:40:17 -0600 Subject: OMAP2420: CTRL: fix OMAP242X_CTRL_REGADDR macro Conform the OMAP2420_CTRL_BASE macro name to the standard of the rest of the OMAP*_CTRL_BASE macro names. This fixes a bug in the OMAP2420 SCM code that prevented OMAP242X_CTRL_REGADDR from working. Signed-off-by: Paul Walmsley --- arch/arm/plat-omap/common.c | 2 +- arch/arm/plat-omap/include/plat/omap24xx.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c index 947de3f..cbaf14b 100644 --- a/arch/arm/plat-omap/common.c +++ b/arch/arm/plat-omap/common.c @@ -268,7 +268,7 @@ static struct omap_globals omap242x_globals = { .tap = OMAP2_L4_IO_ADDRESS(0x48014000), .sdrc = OMAP2420_SDRC_BASE, .sms = OMAP2420_SMS_BASE, - .ctrl = OMAP2420_CTRL_BASE, + .ctrl = OMAP242X_CTRL_BASE, .prm = OMAP2420_PRM_BASE, .cm = OMAP2420_CM_BASE, }; diff --git a/arch/arm/plat-omap/include/plat/omap24xx.h b/arch/arm/plat-omap/include/plat/omap24xx.h index 7055672..92df9e2 100644 --- a/arch/arm/plat-omap/include/plat/omap24xx.h +++ b/arch/arm/plat-omap/include/plat/omap24xx.h @@ -40,7 +40,7 @@ #define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000) #define OMAP24XX_IVA_INTC_BASE 0x40000000 -#define OMAP2420_CTRL_BASE L4_24XX_BASE +#define OMAP242X_CTRL_BASE L4_24XX_BASE #define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000) #define OMAP2420_PRCM_BASE (L4_24XX_BASE + 0x8000) #define OMAP2420_CM_BASE (L4_24XX_BASE + 0x8000) -- cgit v1.1 From 1bccb345bd8c5652017013d7e963fdd158ead600 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Fri, 8 Oct 2010 11:40:17 -0600 Subject: OMAP2420: clock: add MCBSP_CLKS node and clkdev aliases Add the MCBSP_CLKS clock and the clksel structures needed to support clock framework-based source switching for McBSP 1 and 2. Also, add clkdev aliases on the parent clocks for the McBSP source switching code, added in a subsequent patch. Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clock2420_data.c | 40 ++++++++++++++++++++++++++++++++++-- 1 file changed, 38 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c index 5f2066a..7086fe4 100644 --- a/arch/arm/mach-omap2/clock2420_data.c +++ b/arch/arm/mach-omap2/clock2420_data.c @@ -18,6 +18,7 @@ #include #include +#include #include "clock.h" #include "clock2xxx.h" @@ -89,6 +90,12 @@ static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ .clkdm_name = "wkup_clkdm", }; +/* Optional external clock input for McBSP CLKS */ +static struct clk mcbsp_clks = { + .name = "mcbsp_clks", + .ops = &clkops_null, +}; + /* * Analog domain root source clocks */ @@ -1135,14 +1142,34 @@ static struct clk mcbsp1_ick = { .recalc = &followparent_recalc, }; +static const struct clksel_rate common_mcbsp_96m_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel mcbsp_fck_clksel[] = { + { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates }, + { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, + { .parent = NULL } +}; + static struct clk mcbsp1_fck = { .name = "mcbsp1_fck", .ops = &clkops_omap2_dflt_wait, .parent = &func_96m_ck, + .init = &omap2_init_clksel_parent, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, - .recalc = &followparent_recalc, + .clksel_reg = OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), + .clksel_mask = OMAP2_MCBSP1_CLKS_MASK, + .clksel = mcbsp_fck_clksel, + .recalc = &omap2_clksel_recalc, }; static struct clk mcbsp2_ick = { @@ -1159,10 +1186,14 @@ static struct clk mcbsp2_fck = { .name = "mcbsp2_fck", .ops = &clkops_omap2_dflt_wait, .parent = &func_96m_ck, + .init = &omap2_init_clksel_parent, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, - .recalc = &followparent_recalc, + .clksel_reg = OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), + .clksel_mask = OMAP2_MCBSP2_CLKS_MASK, + .clksel = mcbsp_fck_clksel, + .recalc = &omap2_clksel_recalc, }; static struct clk mcspi1_ick = { @@ -1721,6 +1752,9 @@ static struct omap_clk omap2420_clks[] = { CLK(NULL, "osc_ck", &osc_ck, CK_242X), CLK(NULL, "sys_ck", &sys_ck, CK_242X), CLK(NULL, "alt_ck", &alt_ck, CK_242X), + CLK("omap-mcbsp.1", "pad_fck", &mcbsp_clks, CK_242X), + CLK("omap-mcbsp.2", "pad_fck", &mcbsp_clks, CK_242X), + CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_242X), /* internal analog sources */ CLK(NULL, "dpll_ck", &dpll_ck, CK_242X), CLK(NULL, "apll96_ck", &apll96_ck, CK_242X), @@ -1728,6 +1762,8 @@ static struct omap_clk omap2420_clks[] = { /* internal prcm root sources */ CLK(NULL, "func_54m_ck", &func_54m_ck, CK_242X), CLK(NULL, "core_ck", &core_ck, CK_242X), + CLK("omap-mcbsp.1", "prcm_fck", &func_96m_ck, CK_242X), + CLK("omap-mcbsp.2", "prcm_fck", &func_96m_ck, CK_242X), CLK(NULL, "func_96m_ck", &func_96m_ck, CK_242X), CLK(NULL, "func_48m_ck", &func_48m_ck, CK_242X), CLK(NULL, "func_12m_ck", &func_12m_ck, CK_242X), -- cgit v1.1 From b115b743c2e4bcee9ddc91f7ae2942a06e1a53db Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Fri, 8 Oct 2010 11:40:18 -0600 Subject: OMAP2430: clock: add MCBSP_CLKS node and clkdev aliases Add the MCBSP_CLKS clock and the clksel structures needed to support clock framework-based source switching for McBSPs 1-5. Also, add clkdev aliases on the parent clocks for the McBSP source switching code, added in a subsequent patch. Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clock2430_data.c | 64 +++++++++++++++++++++++++++++++++--- 1 file changed, 59 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c index 701a171..4548319 100644 --- a/arch/arm/mach-omap2/clock2430_data.c +++ b/arch/arm/mach-omap2/clock2430_data.c @@ -18,6 +18,7 @@ #include #include +#include #include "clock.h" #include "clock2xxx.h" @@ -89,6 +90,12 @@ static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ .clkdm_name = "wkup_clkdm", }; +/* Optional external clock input for McBSP CLKS */ +static struct clk mcbsp_clks = { + .name = "mcbsp_clks", + .ops = &clkops_null, +}; + /* * Analog domain root source clocks */ @@ -1123,14 +1130,34 @@ static struct clk mcbsp1_ick = { .recalc = &followparent_recalc, }; +static const struct clksel_rate common_mcbsp_96m_rates[] = { + { .div = 1, .val = 0, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { + { .div = 1, .val = 1, .flags = RATE_IN_24XX }, + { .div = 0 } +}; + +static const struct clksel mcbsp_fck_clksel[] = { + { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates }, + { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, + { .parent = NULL } +}; + static struct clk mcbsp1_fck = { .name = "mcbsp1_fck", .ops = &clkops_omap2_dflt_wait, .parent = &func_96m_ck, + .init = &omap2_init_clksel_parent, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, - .recalc = &followparent_recalc, + .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), + .clksel_mask = OMAP2_MCBSP1_CLKS_MASK, + .clksel = mcbsp_fck_clksel, + .recalc = &omap2_clksel_recalc, }; static struct clk mcbsp2_ick = { @@ -1147,10 +1174,14 @@ static struct clk mcbsp2_fck = { .name = "mcbsp2_fck", .ops = &clkops_omap2_dflt_wait, .parent = &func_96m_ck, + .init = &omap2_init_clksel_parent, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, - .recalc = &followparent_recalc, + .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), + .clksel_mask = OMAP2_MCBSP2_CLKS_MASK, + .clksel = mcbsp_fck_clksel, + .recalc = &omap2_clksel_recalc, }; static struct clk mcbsp3_ick = { @@ -1167,10 +1198,14 @@ static struct clk mcbsp3_fck = { .name = "mcbsp3_fck", .ops = &clkops_omap2_dflt_wait, .parent = &func_96m_ck, + .init = &omap2_init_clksel_parent, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, - .recalc = &followparent_recalc, + .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1), + .clksel_mask = OMAP2_MCBSP3_CLKS_MASK, + .clksel = mcbsp_fck_clksel, + .recalc = &omap2_clksel_recalc, }; static struct clk mcbsp4_ick = { @@ -1187,10 +1222,14 @@ static struct clk mcbsp4_fck = { .name = "mcbsp4_fck", .ops = &clkops_omap2_dflt_wait, .parent = &func_96m_ck, + .init = &omap2_init_clksel_parent, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, - .recalc = &followparent_recalc, + .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1), + .clksel_mask = OMAP2_MCBSP4_CLKS_MASK, + .clksel = mcbsp_fck_clksel, + .recalc = &omap2_clksel_recalc, }; static struct clk mcbsp5_ick = { @@ -1207,10 +1246,14 @@ static struct clk mcbsp5_fck = { .name = "mcbsp5_fck", .ops = &clkops_omap2_dflt_wait, .parent = &func_96m_ck, + .init = &omap2_init_clksel_parent, .clkdm_name = "core_l4_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, - .recalc = &followparent_recalc, + .clksel_reg = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1), + .clksel_mask = OMAP2_MCBSP5_CLKS_MASK, + .clksel = mcbsp_fck_clksel, + .recalc = &omap2_clksel_recalc, }; static struct clk mcspi1_ick = { @@ -1808,6 +1851,12 @@ static struct omap_clk omap2430_clks[] = { CLK(NULL, "osc_ck", &osc_ck, CK_243X), CLK(NULL, "sys_ck", &sys_ck, CK_243X), CLK(NULL, "alt_ck", &alt_ck, CK_243X), + CLK("omap-mcbsp.1", "pad_fck", &mcbsp_clks, CK_243X), + CLK("omap-mcbsp.2", "pad_fck", &mcbsp_clks, CK_243X), + CLK("omap-mcbsp.3", "pad_fck", &mcbsp_clks, CK_243X), + CLK("omap-mcbsp.4", "pad_fck", &mcbsp_clks, CK_243X), + CLK("omap-mcbsp.5", "pad_fck", &mcbsp_clks, CK_243X), + CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_243X), /* internal analog sources */ CLK(NULL, "dpll_ck", &dpll_ck, CK_243X), CLK(NULL, "apll96_ck", &apll96_ck, CK_243X), @@ -1815,6 +1864,11 @@ static struct omap_clk omap2430_clks[] = { /* internal prcm root sources */ CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X), CLK(NULL, "core_ck", &core_ck, CK_243X), + CLK("omap-mcbsp.1", "prcm_fck", &func_96m_ck, CK_243X), + CLK("omap-mcbsp.2", "prcm_fck", &func_96m_ck, CK_243X), + CLK("omap-mcbsp.3", "prcm_fck", &func_96m_ck, CK_243X), + CLK("omap-mcbsp.4", "prcm_fck", &func_96m_ck, CK_243X), + CLK("omap-mcbsp.5", "prcm_fck", &func_96m_ck, CK_243X), CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X), CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X), CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X), -- cgit v1.1 From 829e5b127a33d3baa227e87636032f36cd4c05fc Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Fri, 8 Oct 2010 11:40:18 -0600 Subject: OMAP3xxx: clock: add clkdev aliases for McBSP fclk source switching The OMAP3 clock tree already contains the infrastructure to support clock framework-based McBSP functional clock source switching. But it did not contain the clkdev aliases for the McBSP code to refer to the parent clocks in an SoC integration-neutral way. So, add the clkdev aliases for the parent clocks. Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clock3xxx_data.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index ba01ec0..4ac1fb8 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -3208,6 +3208,11 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX), CLK(NULL, "sys_ck", &sys_ck, CK_3XXX), CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX), + CLK("omap-mcbsp.1", "pad_fck", &mcbsp_clks, CK_3XXX), + CLK("omap-mcbsp.2", "pad_fck", &mcbsp_clks, CK_3XXX), + CLK("omap-mcbsp.3", "pad_fck", &mcbsp_clks, CK_3XXX), + CLK("omap-mcbsp.4", "pad_fck", &mcbsp_clks, CK_3XXX), + CLK("omap-mcbsp.5", "pad_fck", &mcbsp_clks, CK_3XXX), CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX), CLK(NULL, "sys_clkout1", &sys_clkout1, CK_3XXX), CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX), @@ -3273,6 +3278,8 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2 | CK_AM35XX), CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2 | CK_AM35XX), CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2 | CK_AM35XX), + CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck, CK_3XXX), + CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck, CK_3XXX), CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX), CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2 | CK_AM35XX), CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_3XXX), @@ -3366,6 +3373,9 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX), CLK(NULL, "gpt12_ick", &gpt12_ick, CK_3XXX), CLK(NULL, "gpt1_ick", &gpt1_ick, CK_3XXX), + CLK("omap-mcbsp.2", "prcm_fck", &per_96m_fck, CK_3XXX), + CLK("omap-mcbsp.3", "prcm_fck", &per_96m_fck, CK_3XXX), + CLK("omap-mcbsp.4", "prcm_fck", &per_96m_fck, CK_3XXX), CLK(NULL, "per_96m_fck", &per_96m_fck, CK_3XXX), CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX), CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX), -- cgit v1.1 From cf4c87abe238ec17cd0255b4e21abd949d7f811e Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Fri, 8 Oct 2010 11:40:19 -0600 Subject: OMAP: McBSP: implement McBSP CLKR and FSR signal muxing via mach-omap2/mcbsp.c The OMAP ASoC McBSP code implemented CLKR and FSR signal muxing via direct System Control Module writes on OMAP2+. This required the omap_ctrl_{read,write}l() functions to be exported, which is against policy: the only code that should call those functions directly is OMAP core code, not device drivers. omap_ctrl_{read,write}*() are no longer exported, so the driver no longer builds as a module. Fix the pinmuxing part of the problem by removing calls to omap_ctrl_{read,write}l() from the OMAP ASoC McBSP code and implementing signal muxing functions in arch/arm/mach-omap2/mcbsp.c. Due to the unfortunate way that McBSP support is implemented in ASoC and the OMAP tree, these symbols must be exported for use by sound/soc/omap/omap-mcbsp.c. Going forward, the McBSP device driver should be moved from arch/arm/*omap* into drivers/ or sound/soc/*, and the CPU DAI driver should be implemented as a platform_driver as many other ASoC CPU DAI drivers are. These two steps should resolve many of the layering problems, which will rapidly reappear during a McBSP hwmod/PM runtime conversion. Signed-off-by: Paul Walmsley Acked-by: Jarkko Nikula Acked-by: Peter Ujfalusi Acked-by: Liam Girdwood Acked-by: Mark Brown --- arch/arm/mach-omap2/mcbsp.c | 30 ++++++++++++++++++++++++++++++ arch/arm/plat-omap/include/plat/control.h | 2 ++ arch/arm/plat-omap/include/plat/mcbsp.h | 13 ++++++++++++- arch/arm/plat-omap/mcbsp.c | 1 + 4 files changed, 45 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index 88b8790..4c9c999 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c @@ -22,7 +22,37 @@ #include #include #include +#include +/* McBSP internal signal muxing functions */ + +void omap2_mcbsp1_mux_clkr_src(u8 mux) +{ + u32 v; + + v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); + if (mux == CLKR_SRC_CLKR) + v &= OMAP2_MCBSP1_CLKR_MASK; + else if (mux == CLKR_SRC_CLKX) + v |= OMAP2_MCBSP1_CLKR_MASK; + omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0); +} +EXPORT_SYMBOL(omap2_mcbsp1_mux_clkr_src); + +void omap2_mcbsp1_mux_fsr_src(u8 mux) +{ + u32 v; + + v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); + if (mux == FSR_SRC_FSR) + v &= OMAP2_MCBSP1_FSR_MASK; + else if (mux == FSR_SRC_FSX) + v |= OMAP2_MCBSP1_FSR_MASK; + omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0); +} +EXPORT_SYMBOL(omap2_mcbsp1_mux_fsr_src); + +/* Platform data */ #ifdef CONFIG_ARCH_OMAP2420 static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = { diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/plat-omap/include/plat/control.h index 19c9b2a..54b0c35 100644 --- a/arch/arm/plat-omap/include/plat/control.h +++ b/arch/arm/plat-omap/include/plat/control.h @@ -223,6 +223,8 @@ #define OMAP2_MMCSDIO1ADPCLKISEL (1 << 24) /* MMC1 loop back clock */ #define OMAP24XX_USBSTANDBYCTRL (1 << 15) #define OMAP2_MCBSP2_CLKS_MASK (1 << 6) +#define OMAP2_MCBSP1_FSR_MASK (1 << 4) +#define OMAP2_MCBSP1_CLKR_MASK (1 << 3) #define OMAP2_MCBSP1_CLKS_MASK (1 << 2) /* CONTROL_DEVCONF1 bits */ diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h index b4ff6a1..886d0e6 100644 --- a/arch/arm/plat-omap/include/plat/mcbsp.h +++ b/arch/arm/plat-omap/include/plat/mcbsp.h @@ -312,6 +312,14 @@ #define RFSREN 0x0002 #define RSYNCERREN 0x0001 +/* CLKR signal muxing options */ +#define CLKR_SRC_CLKR 0 +#define CLKR_SRC_CLKX 1 + +/* FSR signal muxing options */ +#define FSR_SRC_FSR 0 +#define FSR_SRC_FSX 1 + /* we don't do multichannel for now */ struct omap_mcbsp_reg_cfg { u16 spcr2; @@ -501,7 +509,6 @@ int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int leng int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word); int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word); - /* SPI specific API */ void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg); @@ -510,6 +517,10 @@ int omap_mcbsp_pollread(unsigned int id, u16 * buf); int omap_mcbsp_pollwrite(unsigned int id, u16 buf); int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type); +/* McBSP signal muxing API */ +void omap2_mcbsp1_mux_clkr_src(u8 mux); +void omap2_mcbsp1_mux_fsr_src(u8 mux); + #ifdef CONFIG_ARCH_OMAP3 /* Sidetone specific API */ int omap_st_set_chgain(unsigned int id, int channel, s16 chgain); diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index b2e0469..9836fb5 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c @@ -27,6 +27,7 @@ #include #include +#include #include "../mach-omap2/cm-regbits-34xx.h" -- cgit v1.1 From d13586574d373ef40acd4725c9a269daa355e412 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Fri, 8 Oct 2010 11:40:19 -0600 Subject: OMAP: McBSP: implement functional clock switching via clock framework Previously the OMAP McBSP ASoC driver implemented CLKS switching by using omap_ctrl_{read,write}l() directly. This is against policy; the OMAP System Control Module functions are not intended to be exported to drivers. These symbols are no longer exported, so as a result, the OMAP McBSP ASoC driver does not build as a module. Resolve the CLKS clock changing portion of this problem by creating a clock parent changing function that lives in arch/arm/mach-omap2/mcbsp.c, and modify the ASoC driver to use it. Due to the unfortunate way that McBSP support is implemented in ASoC and the OMAP tree, this symbol must be exported for use by sound/soc/omap/omap-mcbsp.c. Going forward, the McBSP device driver should be moved from arch/arm/*omap* into drivers/ or sound/soc/* and the CPU DAI driver should be implemented as a platform_driver as many other ASoC CPU DAI drivers are. These two steps should resolve many of the layering problems, which will rapidly reappear during a McBSP hwmod/PM runtime conversions. Signed-off-by: Paul Walmsley Acked-by: Jarkko Nikula Acked-by: Peter Ujfalusi Acked-by: Liam Girdwood Acked-by: Mark Brown --- arch/arm/mach-omap2/mcbsp.c | 51 +++++++++++++++++++++++++++++++++ arch/arm/plat-omap/include/plat/mcbsp.h | 11 +++++++ arch/arm/plat-omap/mcbsp.c | 3 -- 3 files changed, 62 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index 4c9c999..51abced 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c @@ -52,6 +52,54 @@ void omap2_mcbsp1_mux_fsr_src(u8 mux) } EXPORT_SYMBOL(omap2_mcbsp1_mux_fsr_src); +/* McBSP CLKS source switching function */ + +int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id) +{ + struct omap_mcbsp *mcbsp; + struct clk *fck_src; + char *fck_src_name; + int r; + + if (!omap_mcbsp_check_valid_id(id)) { + pr_err("%s: Invalid id (%d)\n", __func__, id + 1); + return -EINVAL; + } + mcbsp = id_to_mcbsp_ptr(id); + + if (fck_src_id == MCBSP_CLKS_PAD_SRC) + fck_src_name = "pad_fck"; + else if (fck_src_id == MCBSP_CLKS_PRCM_SRC) + fck_src_name = "prcm_fck"; + else + return -EINVAL; + + fck_src = clk_get(mcbsp->dev, fck_src_name); + if (IS_ERR_OR_NULL(fck_src)) { + pr_err("omap-mcbsp: %s: could not clk_get() %s\n", "clks", + fck_src_name); + return -EINVAL; + } + + clk_disable(mcbsp->fclk); + + r = clk_set_parent(mcbsp->fclk, fck_src); + if (IS_ERR_VALUE(r)) { + pr_err("omap-mcbsp: %s: could not clk_set_parent() to %s\n", + "clks", fck_src_name); + clk_put(fck_src); + return -EINVAL; + } + + clk_enable(mcbsp->fclk); + + clk_put(fck_src); + + return 0; +} +EXPORT_SYMBOL(omap2_mcbsp_set_clks_src); + + /* Platform data */ #ifdef CONFIG_ARCH_OMAP2420 @@ -190,18 +238,21 @@ static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = { .dma_rx_sync = OMAP44XX_DMA_MCBSP2_RX, .dma_tx_sync = OMAP44XX_DMA_MCBSP2_TX, .tx_irq = OMAP44XX_IRQ_MCBSP2, + /* XXX .ops ? */ }, { .phys_base = OMAP44XX_MCBSP3_BASE, .dma_rx_sync = OMAP44XX_DMA_MCBSP3_RX, .dma_tx_sync = OMAP44XX_DMA_MCBSP3_TX, .tx_irq = OMAP44XX_IRQ_MCBSP3, + /* XXX .ops ? */ }, { .phys_base = OMAP44XX_MCBSP4_BASE, .dma_rx_sync = OMAP44XX_DMA_MCBSP4_RX, .dma_tx_sync = OMAP44XX_DMA_MCBSP4_TX, .tx_irq = OMAP44XX_IRQ_MCBSP4, + /* XXX .ops ? */ }, }; #define OMAP44XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap44xx_mcbsp_pdata) diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h index 886d0e6..4da6f94a 100644 --- a/arch/arm/plat-omap/include/plat/mcbsp.h +++ b/arch/arm/plat-omap/include/plat/mcbsp.h @@ -320,6 +320,10 @@ #define FSR_SRC_FSR 0 #define FSR_SRC_FSX 1 +/* McBSP functional clock sources */ +#define MCBSP_CLKS_PAD_SRC 0 +#define MCBSP_CLKS_PRCM_SRC 1 + /* we don't do multichannel for now */ struct omap_mcbsp_reg_cfg { u16 spcr2; @@ -406,6 +410,7 @@ struct omap_mcbsp_spi_cfg { struct omap_mcbsp_ops { void (*request)(unsigned int); void (*free)(unsigned int); + int (*set_clks_src)(u8, u8); }; struct omap_mcbsp_platform_data { @@ -472,6 +477,9 @@ struct omap_mcbsp { extern struct omap_mcbsp **mcbsp_ptr; extern int omap_mcbsp_count, omap_mcbsp_cache_size; +#define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count) +#define id_to_mcbsp_ptr(id) mcbsp_ptr[id]; + int omap_mcbsp_init(void); void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, int size); @@ -509,6 +517,9 @@ int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int leng int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word); int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word); + +/* McBSP functional clock source changing function */ +extern int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id); /* SPI specific API */ void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg); diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index 9836fb5..09f8c287 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c @@ -81,9 +81,6 @@ static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg) #define MCBSP_READ_CACHE(mcbsp, reg) \ omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1) -#define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count) -#define id_to_mcbsp_ptr(id) mcbsp_ptr[id]; - #define MCBSP_ST_READ(mcbsp, reg) \ omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg) #define MCBSP_ST_WRITE(mcbsp, reg, val) \ -- cgit v1.1 From aa218dafd7b37ba92fcfdd6d5c8d459772f88042 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Fri, 8 Oct 2010 11:40:19 -0600 Subject: OMAP: split plat-omap/common.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Split plat-omap/common.c into three pieces: 1. the 32KiHz sync timer and clocksource code, which now lives in plat-omap/counter_32k.c; 2. the OMAP2+ common code, which has been moved to mach-omap2/common.c; 3. and the remainder of the OMAP-wide common code, which includes the deprecated ATAGs code and a deprecated video RAM reservation function. The primary motivation for doing this is to move the OMAP2+-specific parts into an OMAP2+-specific file, so that build breakage related to the System Control Module code can be resolved. Benoît Cousson suggested a new filename and found some bugs in the counter_32k.c comments - thanks Benoît. Signed-off-by: Paul Walmsley Cc: Benoît Cousson --- arch/arm/mach-omap2/Makefile | 3 +- arch/arm/mach-omap2/common.c | 135 +++++++++++++++++++ arch/arm/plat-omap/Makefile | 2 +- arch/arm/plat-omap/common.c | 275 --------------------------------------- arch/arm/plat-omap/counter_32k.c | 183 ++++++++++++++++++++++++++ arch/arm/plat-omap/devices.c | 1 - arch/arm/plat-omap/sram.c | 3 - 7 files changed, 321 insertions(+), 281 deletions(-) create mode 100644 arch/arm/mach-omap2/common.c create mode 100644 arch/arm/plat-omap/counter_32k.c (limited to 'arch') diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index d8b1de6..7352412 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -3,7 +3,8 @@ # # Common support -obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o pm.o +obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o pm.o \ + common.o omap-2-3-common = irq.o sdrc.o prm2xxx_3xxx.o hwmod-common = omap_hwmod.o \ diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c new file mode 100644 index 0000000..cddc89a --- /dev/null +++ b/arch/arm/mach-omap2/common.c @@ -0,0 +1,135 @@ +/* + * linux/arch/arm/mach-omap2/common.c + * + * Code common to all OMAP2+ machines. + * + * Copyright (C) 2009 Texas Instruments + * Copyright (C) 2010 Nokia Corporation + * Tony Lindgren + * Added OMAP4 support - Santosh Shilimkar + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "sdrc.h" + +/* Global address base setup code */ + +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) + +static void __init __omap2_set_globals(struct omap_globals *omap2_globals) +{ + omap2_set_globals_tap(omap2_globals); + omap2_set_globals_sdrc(omap2_globals); + omap2_set_globals_control(omap2_globals); + omap2_set_globals_prcm(omap2_globals); +} + +#endif + +#if defined(CONFIG_ARCH_OMAP2420) + +static struct omap_globals omap242x_globals = { + .class = OMAP242X_CLASS, + .tap = OMAP2_L4_IO_ADDRESS(0x48014000), + .sdrc = OMAP2420_SDRC_BASE, + .sms = OMAP2420_SMS_BASE, + .ctrl = OMAP242X_CTRL_BASE, + .prm = OMAP2420_PRM_BASE, + .cm = OMAP2420_CM_BASE, + .uart1_phys = OMAP2_UART1_BASE, + .uart2_phys = OMAP2_UART2_BASE, + .uart3_phys = OMAP2_UART3_BASE, +}; + +void __init omap2_set_globals_242x(void) +{ + __omap2_set_globals(&omap242x_globals); +} +#endif + +#if defined(CONFIG_ARCH_OMAP2430) + +static struct omap_globals omap243x_globals = { + .class = OMAP243X_CLASS, + .tap = OMAP2_L4_IO_ADDRESS(0x4900a000), + .sdrc = OMAP243X_SDRC_BASE, + .sms = OMAP243X_SMS_BASE, + .ctrl = OMAP243X_CTRL_BASE, + .prm = OMAP2430_PRM_BASE, + .cm = OMAP2430_CM_BASE, + .uart1_phys = OMAP2_UART1_BASE, + .uart2_phys = OMAP2_UART2_BASE, + .uart3_phys = OMAP2_UART3_BASE, +}; + +void __init omap2_set_globals_243x(void) +{ + __omap2_set_globals(&omap243x_globals); +} +#endif + +#if defined(CONFIG_ARCH_OMAP3) + +static struct omap_globals omap3_globals = { + .class = OMAP343X_CLASS, + .tap = OMAP2_L4_IO_ADDRESS(0x4830A000), + .sdrc = OMAP343X_SDRC_BASE, + .sms = OMAP343X_SMS_BASE, + .ctrl = OMAP343X_CTRL_BASE, + .prm = OMAP3430_PRM_BASE, + .cm = OMAP3430_CM_BASE, + .uart1_phys = OMAP3_UART1_BASE, + .uart2_phys = OMAP3_UART2_BASE, + .uart3_phys = OMAP3_UART3_BASE, + .uart4_phys = OMAP3_UART4_BASE, /* Only on 3630 */ +}; + +void __init omap2_set_globals_3xxx(void) +{ + __omap2_set_globals(&omap3_globals); +} + +void __init omap3_map_io(void) +{ + omap2_set_globals_3xxx(); + omap34xx_map_common_io(); +} +#endif + +#if defined(CONFIG_ARCH_OMAP4) +static struct omap_globals omap4_globals = { + .class = OMAP443X_CLASS, + .tap = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE), + .ctrl = OMAP443X_SCM_BASE, + .ctrl_pad = OMAP443X_CTRL_BASE, + .prm = OMAP4430_PRM_BASE, + .cm = OMAP4430_CM_BASE, + .cm2 = OMAP4430_CM2_BASE, + .uart1_phys = OMAP4_UART1_BASE, + .uart2_phys = OMAP4_UART2_BASE, + .uart3_phys = OMAP4_UART3_BASE, + .uart4_phys = OMAP4_UART4_BASE, +}; + +void __init omap2_set_globals_443x(void) +{ + omap2_set_globals_tap(&omap4_globals); + omap2_set_globals_control(&omap4_globals); + omap2_set_globals_prcm(&omap4_globals); +} +#endif + diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile index 2a15191..a4a1285 100644 --- a/arch/arm/plat-omap/Makefile +++ b/arch/arm/plat-omap/Makefile @@ -4,7 +4,7 @@ # Common support obj-y := common.o sram.o clock.o devices.o dma.o mux.o gpio.o \ - usb.o fb.o io.o + usb.o fb.o io.o counter_32k.o obj-m := obj-n := obj- := diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c index cbaf14b..221a675 100644 --- a/arch/arm/plat-omap/common.c +++ b/arch/arm/plat-omap/common.c @@ -11,38 +11,15 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -#include #include #include -#include -#include -#include -#include -#include -#include -#include #include #include -#include -#include -#include -#include -#include - #include #include -#include -#include -#include -#include #include -#include - -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) -# include "../mach-omap2/sdrc.h" -#endif #define NO_LENGTH_CHECK 0xffffffff @@ -88,255 +65,3 @@ void __init omap_reserve(void) omapfb_reserve_sdram_memblock(); omap_vram_reserve_sdram_memblock(); } - -/* - * 32KHz clocksource ... always available, on pretty most chips except - * OMAP 730 and 1510. Other timers could be used as clocksources, with - * higher resolution in free-running counter modes (e.g. 12 MHz xtal), - * but systems won't necessarily want to spend resources that way. - */ - -#define OMAP16XX_TIMER_32K_SYNCHRONIZED 0xfffbc410 - -#if !(defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP15XX)) - -#include - -/* - * offset_32k holds the init time counter value. It is then subtracted - * from every counter read to achieve a counter that counts time from the - * kernel boot (needed for sched_clock()). - */ -static u32 offset_32k __read_mostly; - -#ifdef CONFIG_ARCH_OMAP16XX -static cycle_t omap16xx_32k_read(struct clocksource *cs) -{ - return omap_readl(OMAP16XX_TIMER_32K_SYNCHRONIZED) - offset_32k; -} -#else -#define omap16xx_32k_read NULL -#endif - -#ifdef CONFIG_ARCH_OMAP2420 -static cycle_t omap2420_32k_read(struct clocksource *cs) -{ - return omap_readl(OMAP2420_32KSYNCT_BASE + 0x10) - offset_32k; -} -#else -#define omap2420_32k_read NULL -#endif - -#ifdef CONFIG_ARCH_OMAP2430 -static cycle_t omap2430_32k_read(struct clocksource *cs) -{ - return omap_readl(OMAP2430_32KSYNCT_BASE + 0x10) - offset_32k; -} -#else -#define omap2430_32k_read NULL -#endif - -#ifdef CONFIG_ARCH_OMAP3 -static cycle_t omap34xx_32k_read(struct clocksource *cs) -{ - return omap_readl(OMAP3430_32KSYNCT_BASE + 0x10) - offset_32k; -} -#else -#define omap34xx_32k_read NULL -#endif - -#ifdef CONFIG_ARCH_OMAP4 -static cycle_t omap44xx_32k_read(struct clocksource *cs) -{ - return omap_readl(OMAP4430_32KSYNCT_BASE + 0x10) - offset_32k; -} -#else -#define omap44xx_32k_read NULL -#endif - -/* - * Kernel assumes that sched_clock can be called early but may not have - * things ready yet. - */ -static cycle_t omap_32k_read_dummy(struct clocksource *cs) -{ - return 0; -} - -static struct clocksource clocksource_32k = { - .name = "32k_counter", - .rating = 250, - .read = omap_32k_read_dummy, - .mask = CLOCKSOURCE_MASK(32), - .shift = 10, - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -/* - * Returns current time from boot in nsecs. It's OK for this to wrap - * around for now, as it's just a relative time stamp. - */ -unsigned long long sched_clock(void) -{ - return clocksource_cyc2ns(clocksource_32k.read(&clocksource_32k), - clocksource_32k.mult, clocksource_32k.shift); -} - -/** - * read_persistent_clock - Return time from a persistent clock. - * - * Reads the time from a source which isn't disabled during PM, the - * 32k sync timer. Convert the cycles elapsed since last read into - * nsecs and adds to a monotonically increasing timespec. - */ -static struct timespec persistent_ts; -static cycles_t cycles, last_cycles; -void read_persistent_clock(struct timespec *ts) -{ - unsigned long long nsecs; - cycles_t delta; - struct timespec *tsp = &persistent_ts; - - last_cycles = cycles; - cycles = clocksource_32k.read(&clocksource_32k); - delta = cycles - last_cycles; - - nsecs = clocksource_cyc2ns(delta, - clocksource_32k.mult, clocksource_32k.shift); - - timespec_add_ns(tsp, nsecs); - *ts = *tsp; -} - -static int __init omap_init_clocksource_32k(void) -{ - static char err[] __initdata = KERN_ERR - "%s: can't register clocksource!\n"; - - if (cpu_is_omap16xx() || cpu_class_is_omap2()) { - struct clk *sync_32k_ick; - - if (cpu_is_omap16xx()) - clocksource_32k.read = omap16xx_32k_read; - else if (cpu_is_omap2420()) - clocksource_32k.read = omap2420_32k_read; - else if (cpu_is_omap2430()) - clocksource_32k.read = omap2430_32k_read; - else if (cpu_is_omap34xx()) - clocksource_32k.read = omap34xx_32k_read; - else if (cpu_is_omap44xx()) - clocksource_32k.read = omap44xx_32k_read; - else - return -ENODEV; - - sync_32k_ick = clk_get(NULL, "omap_32ksync_ick"); - if (sync_32k_ick) - clk_enable(sync_32k_ick); - - clocksource_32k.mult = clocksource_hz2mult(32768, - clocksource_32k.shift); - - offset_32k = clocksource_32k.read(&clocksource_32k); - - if (clocksource_register(&clocksource_32k)) - printk(err, clocksource_32k.name); - } - return 0; -} -arch_initcall(omap_init_clocksource_32k); - -#endif /* !(defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP15XX)) */ - -/* Global address base setup code */ - -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) - -static void __init __omap2_set_globals(struct omap_globals *omap2_globals) -{ - omap2_set_globals_tap(omap2_globals); - omap2_set_globals_sdrc(omap2_globals); - omap2_set_globals_control(omap2_globals); - omap2_set_globals_prcm(omap2_globals); -} - -#endif - -#if defined(CONFIG_ARCH_OMAP2420) - -static struct omap_globals omap242x_globals = { - .class = OMAP242X_CLASS, - .tap = OMAP2_L4_IO_ADDRESS(0x48014000), - .sdrc = OMAP2420_SDRC_BASE, - .sms = OMAP2420_SMS_BASE, - .ctrl = OMAP242X_CTRL_BASE, - .prm = OMAP2420_PRM_BASE, - .cm = OMAP2420_CM_BASE, -}; - -void __init omap2_set_globals_242x(void) -{ - __omap2_set_globals(&omap242x_globals); -} -#endif - -#if defined(CONFIG_ARCH_OMAP2430) - -static struct omap_globals omap243x_globals = { - .class = OMAP243X_CLASS, - .tap = OMAP2_L4_IO_ADDRESS(0x4900a000), - .sdrc = OMAP243X_SDRC_BASE, - .sms = OMAP243X_SMS_BASE, - .ctrl = OMAP243X_CTRL_BASE, - .prm = OMAP2430_PRM_BASE, - .cm = OMAP2430_CM_BASE, -}; - -void __init omap2_set_globals_243x(void) -{ - __omap2_set_globals(&omap243x_globals); -} -#endif - -#if defined(CONFIG_ARCH_OMAP3) - -static struct omap_globals omap3_globals = { - .class = OMAP343X_CLASS, - .tap = OMAP2_L4_IO_ADDRESS(0x4830A000), - .sdrc = OMAP343X_SDRC_BASE, - .sms = OMAP343X_SMS_BASE, - .ctrl = OMAP343X_CTRL_BASE, - .prm = OMAP3430_PRM_BASE, - .cm = OMAP3430_CM_BASE, -}; - -void __init omap2_set_globals_3xxx(void) -{ - __omap2_set_globals(&omap3_globals); -} - -void __init omap3_map_io(void) -{ - omap2_set_globals_3xxx(); - omap34xx_map_common_io(); -} -#endif - -#if defined(CONFIG_ARCH_OMAP4) -static struct omap_globals omap4_globals = { - .class = OMAP443X_CLASS, - .tap = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE), - .ctrl = OMAP443X_SCM_BASE, - .ctrl_pad = OMAP443X_CTRL_BASE, - .prm = OMAP4430_PRM_BASE, - .cm = OMAP4430_CM_BASE, - .cm2 = OMAP4430_CM2_BASE, -}; - -void __init omap2_set_globals_443x(void) -{ - omap2_set_globals_tap(&omap4_globals); - omap2_set_globals_control(&omap4_globals); - omap2_set_globals_prcm(&omap4_globals); -} -#endif - diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c new file mode 100644 index 0000000..155fe43 --- /dev/null +++ b/arch/arm/plat-omap/counter_32k.c @@ -0,0 +1,183 @@ +/* + * OMAP 32ksynctimer/counter_32k-related code + * + * Copyright (C) 2009 Texas Instruments + * Copyright (C) 2010 Nokia Corporation + * Tony Lindgren + * Added OMAP4 support - Santosh Shilimkar + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * NOTE: This timer is not the same timer as the old OMAP1 MPU timer. + */ +#include +#include +#include +#include + +#include +#include + +#include + + +/* + * 32KHz clocksource ... always available, on pretty most chips except + * OMAP 730 and 1510. Other timers could be used as clocksources, with + * higher resolution in free-running counter modes (e.g. 12 MHz xtal), + * but systems won't necessarily want to spend resources that way. + */ + +#define OMAP16XX_TIMER_32K_SYNCHRONIZED 0xfffbc410 + +#if !(defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP15XX)) + +#include + +/* + * offset_32k holds the init time counter value. It is then subtracted + * from every counter read to achieve a counter that counts time from the + * kernel boot (needed for sched_clock()). + */ +static u32 offset_32k __read_mostly; + +#ifdef CONFIG_ARCH_OMAP16XX +static cycle_t omap16xx_32k_read(struct clocksource *cs) +{ + return omap_readl(OMAP16XX_TIMER_32K_SYNCHRONIZED) - offset_32k; +} +#else +#define omap16xx_32k_read NULL +#endif + +#ifdef CONFIG_ARCH_OMAP2420 +static cycle_t omap2420_32k_read(struct clocksource *cs) +{ + return omap_readl(OMAP2420_32KSYNCT_BASE + 0x10) - offset_32k; +} +#else +#define omap2420_32k_read NULL +#endif + +#ifdef CONFIG_ARCH_OMAP2430 +static cycle_t omap2430_32k_read(struct clocksource *cs) +{ + return omap_readl(OMAP2430_32KSYNCT_BASE + 0x10) - offset_32k; +} +#else +#define omap2430_32k_read NULL +#endif + +#ifdef CONFIG_ARCH_OMAP3 +static cycle_t omap34xx_32k_read(struct clocksource *cs) +{ + return omap_readl(OMAP3430_32KSYNCT_BASE + 0x10) - offset_32k; +} +#else +#define omap34xx_32k_read NULL +#endif + +#ifdef CONFIG_ARCH_OMAP4 +static cycle_t omap44xx_32k_read(struct clocksource *cs) +{ + return omap_readl(OMAP4430_32KSYNCT_BASE + 0x10) - offset_32k; +} +#else +#define omap44xx_32k_read NULL +#endif + +/* + * Kernel assumes that sched_clock can be called early but may not have + * things ready yet. + */ +static cycle_t omap_32k_read_dummy(struct clocksource *cs) +{ + return 0; +} + +static struct clocksource clocksource_32k = { + .name = "32k_counter", + .rating = 250, + .read = omap_32k_read_dummy, + .mask = CLOCKSOURCE_MASK(32), + .shift = 10, + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +/* + * Returns current time from boot in nsecs. It's OK for this to wrap + * around for now, as it's just a relative time stamp. + */ +unsigned long long sched_clock(void) +{ + return clocksource_cyc2ns(clocksource_32k.read(&clocksource_32k), + clocksource_32k.mult, clocksource_32k.shift); +} + +/** + * read_persistent_clock - Return time from a persistent clock. + * + * Reads the time from a source which isn't disabled during PM, the + * 32k sync timer. Convert the cycles elapsed since last read into + * nsecs and adds to a monotonically increasing timespec. + */ +static struct timespec persistent_ts; +static cycles_t cycles, last_cycles; +void read_persistent_clock(struct timespec *ts) +{ + unsigned long long nsecs; + cycles_t delta; + struct timespec *tsp = &persistent_ts; + + last_cycles = cycles; + cycles = clocksource_32k.read(&clocksource_32k); + delta = cycles - last_cycles; + + nsecs = clocksource_cyc2ns(delta, + clocksource_32k.mult, clocksource_32k.shift); + + timespec_add_ns(tsp, nsecs); + *ts = *tsp; +} + +static int __init omap_init_clocksource_32k(void) +{ + static char err[] __initdata = KERN_ERR + "%s: can't register clocksource!\n"; + + if (cpu_is_omap16xx() || cpu_class_is_omap2()) { + struct clk *sync_32k_ick; + + if (cpu_is_omap16xx()) + clocksource_32k.read = omap16xx_32k_read; + else if (cpu_is_omap2420()) + clocksource_32k.read = omap2420_32k_read; + else if (cpu_is_omap2430()) + clocksource_32k.read = omap2430_32k_read; + else if (cpu_is_omap34xx()) + clocksource_32k.read = omap34xx_32k_read; + else if (cpu_is_omap44xx()) + clocksource_32k.read = omap44xx_32k_read; + else + return -ENODEV; + + sync_32k_ick = clk_get(NULL, "omap_32ksync_ick"); + if (sync_32k_ick) + clk_enable(sync_32k_ick); + + clocksource_32k.mult = clocksource_hz2mult(32768, + clocksource_32k.shift); + + offset_32k = clocksource_32k.read(&clocksource_32k); + + if (clocksource_register(&clocksource_32k)) + printk(err, clocksource_32k.name); + } + return 0; +} +arch_initcall(omap_init_clocksource_32k); + +#endif /* !(defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP15XX)) */ + diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c index 8e88e0e..1e2383e 100644 --- a/arch/arm/plat-omap/devices.c +++ b/arch/arm/plat-omap/devices.c @@ -21,7 +21,6 @@ #include #include -#include #include #include #include diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index dba5704..c209163 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -31,10 +31,8 @@ #include #include -#include #include "sram.h" #include "fb.h" - #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) # include "../mach-omap2/prm.h" # include "../mach-omap2/cm.h" @@ -71,7 +69,6 @@ #define OMAP34XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68012858) #define OMAP34XX_VA_ADDR_MATCH2 OMAP2_L3_IO_ADDRESS(0x68012880) #define OMAP34XX_VA_SMS_RG_ATT0 OMAP2_L3_IO_ADDRESS(0x6C000048) -#define OMAP34XX_VA_CONTROL_STAT OMAP2_L4_IO_ADDRESS(0x480022F0) #define GP_DEVICE 0x300 -- cgit v1.1 From 4814ced5116e3b73dc4f63eec84999739fc8ed11 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Fri, 8 Oct 2010 11:40:20 -0600 Subject: OMAP: control: move plat-omap/control.h to mach-omap2/control.h Only OMAP2+ platforms have the System Control Module (SCM) IP block. In the past, we've kept the SCM header file in plat-omap. This has led to abuse - device drivers including it; includes being added that create implicit dependencies on OMAP2+ builds; etc. In response, move the SCM headers into mach-omap2/. As part of this, remove the direct SCM access from the OMAP UDC driver. It was clearly broken. The UDC code needs an indepth review for use on OMAP2+ chips. Signed-off-by: Paul Walmsley Cc: Cory Maccarrone Cc: Kyungmin Park --- arch/arm/mach-omap2/board-3430sdp.c | 2 +- arch/arm/mach-omap2/board-4430sdp.c | 2 +- arch/arm/mach-omap2/board-am3517evm.c | 2 +- arch/arm/mach-omap2/board-apollon.c | 2 +- arch/arm/mach-omap2/board-cm-t3517.c | 2 +- arch/arm/mach-omap2/board-h4.c | 2 +- arch/arm/mach-omap2/board-ldp.c | 2 +- arch/arm/mach-omap2/board-omap3logic.c | 2 +- arch/arm/mach-omap2/board-omap4panda.c | 4 +- arch/arm/mach-omap2/clock2420_data.c | 2 +- arch/arm/mach-omap2/clock2430_data.c | 2 +- arch/arm/mach-omap2/clock3xxx_data.c | 2 +- arch/arm/mach-omap2/clock44xx_data.c | 2 +- arch/arm/mach-omap2/common.c | 2 +- arch/arm/mach-omap2/control.c | 3 +- arch/arm/mach-omap2/control.h | 368 ++++++++++++++++++++++++++ arch/arm/mach-omap2/cpuidle34xx.c | 2 +- arch/arm/mach-omap2/devices.c | 3 +- arch/arm/mach-omap2/hsmmc.c | 2 +- arch/arm/mach-omap2/id.c | 3 +- arch/arm/mach-omap2/mcbsp.c | 4 +- arch/arm/mach-omap2/mux.c | 8 +- arch/arm/mach-omap2/pm24xx.c | 2 +- arch/arm/mach-omap2/pm34xx.c | 2 +- arch/arm/mach-omap2/prcm.c | 2 +- arch/arm/mach-omap2/serial.c | 2 +- arch/arm/mach-omap2/sleep34xx.S | 2 +- arch/arm/mach-omap2/usb-fs.c | 6 +- arch/arm/plat-omap/include/plat/control.h | 368 -------------------------- arch/arm/plat-omap/include/plat/omap-serial.h | 1 - arch/arm/plat-omap/mcbsp.c | 1 - 31 files changed, 404 insertions(+), 405 deletions(-) create mode 100644 arch/arm/mach-omap2/control.h delete mode 100644 arch/arm/plat-omap/include/plat/control.h (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index 9ba2ee2..88b5734 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -39,7 +39,6 @@ #include #include -#include #include #include "board-flash.h" @@ -47,6 +46,7 @@ #include "sdram-qimonda-hyb18m512160af-6.h" #include "hsmmc.h" #include "pm.h" +#include "control.h" #define CONFIG_DISABLE_HFCLK 1 diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index 1d7d70a..aafd30680 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -32,12 +32,12 @@ #include #include -#include #include #include #include "hsmmc.h" #include "timer-gp.h" +#include "control.h" #define ETH_KS8851_IRQ 34 #define ETH_KS8851_POWER_ON 48 diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index b091741..fada04e 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c @@ -32,11 +32,11 @@ #include #include -#include #include #include #include "mux.h" +#include "control.h" #define AM35XX_EVM_PHY_MASK (0xF) #define AM35XX_EVM_MDIO_FREQUENCY (1000000) diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c index c6421a7..102719c 100644 --- a/arch/arm/mach-omap2/board-apollon.c +++ b/arch/arm/mach-omap2/board-apollon.c @@ -39,9 +39,9 @@ #include #include #include -#include #include "mux.h" +#include "control.h" /* LED & Switch macros */ #define LED0_GPIO13 13 diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c index 1115b8a..c49319f 100644 --- a/arch/arm/mach-omap2/board-cm-t3517.c +++ b/arch/arm/mach-omap2/board-cm-t3517.c @@ -40,7 +40,6 @@ #include #include -#include #include #include #include @@ -48,6 +47,7 @@ #include #include "mux.h" +#include "control.h" #if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) static struct gpio_led cm_t3517_leds[] = { diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c index e09bd68..08492a3 100644 --- a/arch/arm/mach-omap2/board-h4.c +++ b/arch/arm/mach-omap2/board-h4.c @@ -31,7 +31,6 @@ #include #include -#include #include #include #include @@ -42,6 +41,7 @@ #include #include "mux.h" +#include "control.h" #define H4_FLASH_CS 0 #define H4_SMC91X_CS 1 diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c index 7c1e6ad..8495f37 100644 --- a/arch/arm/mach-omap2/board-ldp.c +++ b/arch/arm/mach-omap2/board-ldp.c @@ -42,12 +42,12 @@ #include #include -#include #include #include "board-flash.h" #include "mux.h" #include "hsmmc.h" +#include "control.h" #define LDP_SMSC911X_CS 1 #define LDP_SMSC911X_GPIO 152 diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c index 3151cf2..44ff674 100644 --- a/arch/arm/mach-omap2/board-omap3logic.c +++ b/arch/arm/mach-omap2/board-omap3logic.c @@ -36,6 +36,7 @@ #include "mux.h" #include "hsmmc.h" #include "timer-gp.h" +#include "control.h" #include #include @@ -43,7 +44,6 @@ #include #include #include -#include #define OMAP3LOGIC_SMSC911X_CS 1 diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index 83bd1fe..992a03e 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -34,12 +34,12 @@ #include #include -#include #include #include -#include "hsmmc.h" #include "timer-gp.h" +#include "hsmmc.h" +#include "control.h" static struct gpio_led gpio_leds[] = { { diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c index 7086fe4..21f8562 100644 --- a/arch/arm/mach-omap2/clock2420_data.c +++ b/arch/arm/mach-omap2/clock2420_data.c @@ -18,7 +18,6 @@ #include #include -#include #include "clock.h" #include "clock2xxx.h" @@ -28,6 +27,7 @@ #include "prm-regbits-24xx.h" #include "cm-regbits-24xx.h" #include "sdrc.h" +#include "control.h" #define OMAP_CM_REGADDR OMAP2420_CM_REGADDR diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c index 4548319..e32afcb 100644 --- a/arch/arm/mach-omap2/clock2430_data.c +++ b/arch/arm/mach-omap2/clock2430_data.c @@ -18,7 +18,6 @@ #include #include -#include #include "clock.h" #include "clock2xxx.h" @@ -28,6 +27,7 @@ #include "prm-regbits-24xx.h" #include "cm-regbits-24xx.h" #include "sdrc.h" +#include "control.h" #define OMAP_CM_REGADDR OMAP2430_CM_REGADDR diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index 4ac1fb8..d85ecd5 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -20,7 +20,6 @@ #include #include -#include #include #include "clock.h" @@ -33,6 +32,7 @@ #include "cm-regbits-34xx.h" #include "prm.h" #include "prm-regbits-34xx.h" +#include "control.h" /* * clocks diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 67fac44..1599836 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include "clock.h" @@ -35,6 +34,7 @@ #include "cm-regbits-44xx.h" #include "prm.h" #include "prm-regbits-44xx.h" +#include "control.h" /* Root clocks */ diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c index cddc89a..778929f 100644 --- a/arch/arm/mach-omap2/common.c +++ b/arch/arm/mach-omap2/common.c @@ -19,12 +19,12 @@ #include #include -#include #include #include #include "sdrc.h" +#include "control.h" /* Global address base setup code */ diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index 5d9b30d..1fa3294 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -16,14 +16,15 @@ #include #include -#include #include + #include "cm-regbits-34xx.h" #include "prm-regbits-34xx.h" #include "cm.h" #include "prm.h" #include "sdrc.h" #include "pm.h" +#include "control.h" static void __iomem *omap2_ctrl_base; static void __iomem *omap4_ctrl_pad_base; diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h new file mode 100644 index 0000000..b6c6b7c --- /dev/null +++ b/arch/arm/mach-omap2/control.h @@ -0,0 +1,368 @@ +/* + * arch/arm/mach-omap2/control.h + * + * OMAP2/3/4 System Control Module definitions + * + * Copyright (C) 2007-2010 Texas Instruments, Inc. + * Copyright (C) 2007-2008, 2010 Nokia Corporation + * + * Written by Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H +#define __ARCH_ARM_MACH_OMAP2_CONTROL_H + +#include +#include +#include +#include +#include + +#ifndef __ASSEMBLY__ +#define OMAP242X_CTRL_REGADDR(reg) \ + OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) +#define OMAP243X_CTRL_REGADDR(reg) \ + OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) +#define OMAP343X_CTRL_REGADDR(reg) \ + OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) +#else +#define OMAP242X_CTRL_REGADDR(reg) \ + OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) +#define OMAP243X_CTRL_REGADDR(reg) \ + OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) +#define OMAP343X_CTRL_REGADDR(reg) \ + OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) +#endif /* __ASSEMBLY__ */ + +/* + * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for + * OMAP24XX and OMAP34XX. + */ + +/* Control submodule offsets */ + +#define OMAP2_CONTROL_INTERFACE 0x000 +#define OMAP2_CONTROL_PADCONFS 0x030 +#define OMAP2_CONTROL_GENERAL 0x270 +#define OMAP343X_CONTROL_MEM_WKUP 0x600 +#define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00 +#define OMAP343X_CONTROL_GENERAL_WKUP 0xa60 + +/* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */ + +#define OMAP2_CONTROL_SYSCONFIG (OMAP2_CONTROL_INTERFACE + 0x10) + +/* CONTROL_GENERAL register offsets common to OMAP2 & 3 */ +#define OMAP2_CONTROL_DEVCONF0 (OMAP2_CONTROL_GENERAL + 0x0004) +#define OMAP2_CONTROL_MSUSPENDMUX_0 (OMAP2_CONTROL_GENERAL + 0x0020) +#define OMAP2_CONTROL_MSUSPENDMUX_1 (OMAP2_CONTROL_GENERAL + 0x0024) +#define OMAP2_CONTROL_MSUSPENDMUX_2 (OMAP2_CONTROL_GENERAL + 0x0028) +#define OMAP2_CONTROL_MSUSPENDMUX_3 (OMAP2_CONTROL_GENERAL + 0x002c) +#define OMAP2_CONTROL_MSUSPENDMUX_4 (OMAP2_CONTROL_GENERAL + 0x0030) +#define OMAP2_CONTROL_MSUSPENDMUX_5 (OMAP2_CONTROL_GENERAL + 0x0034) +#define OMAP2_CONTROL_SEC_CTRL (OMAP2_CONTROL_GENERAL + 0x0040) +#define OMAP2_CONTROL_RPUB_KEY_H_0 (OMAP2_CONTROL_GENERAL + 0x0090) +#define OMAP2_CONTROL_RPUB_KEY_H_1 (OMAP2_CONTROL_GENERAL + 0x0094) +#define OMAP2_CONTROL_RPUB_KEY_H_2 (OMAP2_CONTROL_GENERAL + 0x0098) +#define OMAP2_CONTROL_RPUB_KEY_H_3 (OMAP2_CONTROL_GENERAL + 0x009c) + +/* 242x-only CONTROL_GENERAL register offsets */ +#define OMAP242X_CONTROL_DEVCONF OMAP2_CONTROL_DEVCONF0 /* match TRM */ +#define OMAP242X_CONTROL_OCM_RAM_PERM (OMAP2_CONTROL_GENERAL + 0x0068) + +/* 243x-only CONTROL_GENERAL register offsets */ +/* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */ +#define OMAP243X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0078) +#define OMAP243X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x007c) +#define OMAP243X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) +#define OMAP243X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) +#define OMAP243X_CONTROL_IVA2_GEMCFG (OMAP2_CONTROL_GENERAL + 0x0198) +#define OMAP243X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x0230) + +/* 24xx-only CONTROL_GENERAL register offsets */ +#define OMAP24XX_CONTROL_DEBOBS (OMAP2_CONTROL_GENERAL + 0x0000) +#define OMAP24XX_CONTROL_EMU_SUPPORT (OMAP2_CONTROL_GENERAL + 0x0008) +#define OMAP24XX_CONTROL_SEC_TEST (OMAP2_CONTROL_GENERAL + 0x0044) +#define OMAP24XX_CONTROL_PSA_CTRL (OMAP2_CONTROL_GENERAL + 0x0048) +#define OMAP24XX_CONTROL_PSA_CMD (OMAP2_CONTROL_GENERAL + 0x004c) +#define OMAP24XX_CONTROL_PSA_VALUE (OMAP2_CONTROL_GENERAL + 0x0050) +#define OMAP24XX_CONTROL_SEC_EMU (OMAP2_CONTROL_GENERAL + 0x0060) +#define OMAP24XX_CONTROL_SEC_TAP (OMAP2_CONTROL_GENERAL + 0x0064) +#define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD (OMAP2_CONTROL_GENERAL + 0x006c) +#define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD (OMAP2_CONTROL_GENERAL + 0x0070) +#define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD (OMAP2_CONTROL_GENERAL + 0x0074) +#define OMAP24XX_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0080) +#define OMAP24XX_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0084) +#define OMAP24XX_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0088) +#define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x008c) +#define OMAP24XX_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a0) +#define OMAP24XX_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00a4) +#define OMAP24XX_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00a8) +#define OMAP24XX_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00ac) +#define OMAP24XX_CONTROL_CUST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00b0) +#define OMAP24XX_CONTROL_CUST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00b4) +#define OMAP24XX_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c0) +#define OMAP24XX_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00c4) +#define OMAP24XX_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00c8) +#define OMAP24XX_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00cc) +#define OMAP24XX_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d0) +#define OMAP24XX_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00d4) +#define OMAP24XX_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00d8) +#define OMAP24XX_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00dc) +#define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0) +#define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4) + +#define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP2_CONTROL_INTERFACE + 0x01b0) + +/* 34xx-only CONTROL_GENERAL register offsets */ +#define OMAP343X_CONTROL_PADCONF_OFF (OMAP2_CONTROL_GENERAL + 0x0000) +#define OMAP343X_CONTROL_MEM_DFTRW0 (OMAP2_CONTROL_GENERAL + 0x0008) +#define OMAP343X_CONTROL_MEM_DFTRW1 (OMAP2_CONTROL_GENERAL + 0x000c) +#define OMAP343X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0068) +#define OMAP343X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x006c) +#define OMAP343X_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0070) +#define OMAP343X_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0074) +#define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG (OMAP2_CONTROL_GENERAL + 0x0078) +#define OMAP343X_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0080) +#define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x0084) +#define OMAP343X_CONTROL_RPUB_KEY_H_4 (OMAP2_CONTROL_GENERAL + 0x00a0) +#define OMAP343X_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a8) +#define OMAP343X_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00ac) +#define OMAP343X_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00b0) +#define OMAP343X_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00b4) +#define OMAP343X_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c8) +#define OMAP343X_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00cc) +#define OMAP343X_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00d0) +#define OMAP343X_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00d4) +#define OMAP343X_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d8) +#define OMAP343X_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00dc) +#define OMAP343X_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00e0) +#define OMAP343X_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00e4) +#define OMAP343X_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e8) +#define OMAP343X_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00ec) +#define OMAP343X_CONTROL_TEST_KEY_10 (OMAP2_CONTROL_GENERAL + 0x00f0) +#define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2_CONTROL_GENERAL + 0x00f4) +#define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2_CONTROL_GENERAL + 0x00f8) +#define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc) +#define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) +#define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) +#define OMAP343X_CONTROL_DEBOBS(i) (OMAP2_CONTROL_GENERAL + 0x01B0 \ + + ((i) >> 1) * 4 + (!((i) & 1)) * 2) +#define OMAP343X_CONTROL_PROG_IO0 (OMAP2_CONTROL_GENERAL + 0x01D4) +#define OMAP343X_CONTROL_PROG_IO1 (OMAP2_CONTROL_GENERAL + 0x01D8) +#define OMAP343X_CONTROL_DSS_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E0) +#define OMAP343X_CONTROL_CORE_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E4) +#define OMAP343X_CONTROL_PER_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E8) +#define OMAP343X_CONTROL_USBHOST_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01EC) +#define OMAP343X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x02B0) +#define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02B4) +#define OMAP343X_CONTROL_SRAMLDO4 (OMAP2_CONTROL_GENERAL + 0x02B8) +#define OMAP343X_CONTROL_SRAMLDO5 (OMAP2_CONTROL_GENERAL + 0x02C0) +#define OMAP343X_CONTROL_CSI (OMAP2_CONTROL_GENERAL + 0x02C4) + +/* AM35XX only CONTROL_GENERAL register offsets */ +#define AM35XX_CONTROL_MSUSPENDMUX_6 (OMAP2_CONTROL_GENERAL + 0x0038) +#define AM35XX_CONTROL_DEVCONF2 (OMAP2_CONTROL_GENERAL + 0x0310) +#define AM35XX_CONTROL_DEVCONF3 (OMAP2_CONTROL_GENERAL + 0x0314) +#define AM35XX_CONTROL_CBA_PRIORITY (OMAP2_CONTROL_GENERAL + 0x0320) +#define AM35XX_CONTROL_LVL_INTR_CLEAR (OMAP2_CONTROL_GENERAL + 0x0324) +#define AM35XX_CONTROL_IP_SW_RESET (OMAP2_CONTROL_GENERAL + 0x0328) +#define AM35XX_CONTROL_IPSS_CLK_CTRL (OMAP2_CONTROL_GENERAL + 0x032C) + +/* 34xx PADCONF register offsets */ +#define OMAP343X_PADCONF_ETK(i) (OMAP2_CONTROL_PADCONFS + 0x5a8 + \ + (i)*2) +#define OMAP343X_PADCONF_ETK_CLK OMAP343X_PADCONF_ETK(0) +#define OMAP343X_PADCONF_ETK_CTL OMAP343X_PADCONF_ETK(1) +#define OMAP343X_PADCONF_ETK_D0 OMAP343X_PADCONF_ETK(2) +#define OMAP343X_PADCONF_ETK_D1 OMAP343X_PADCONF_ETK(3) +#define OMAP343X_PADCONF_ETK_D2 OMAP343X_PADCONF_ETK(4) +#define OMAP343X_PADCONF_ETK_D3 OMAP343X_PADCONF_ETK(5) +#define OMAP343X_PADCONF_ETK_D4 OMAP343X_PADCONF_ETK(6) +#define OMAP343X_PADCONF_ETK_D5 OMAP343X_PADCONF_ETK(7) +#define OMAP343X_PADCONF_ETK_D6 OMAP343X_PADCONF_ETK(8) +#define OMAP343X_PADCONF_ETK_D7 OMAP343X_PADCONF_ETK(9) +#define OMAP343X_PADCONF_ETK_D8 OMAP343X_PADCONF_ETK(10) +#define OMAP343X_PADCONF_ETK_D9 OMAP343X_PADCONF_ETK(11) +#define OMAP343X_PADCONF_ETK_D10 OMAP343X_PADCONF_ETK(12) +#define OMAP343X_PADCONF_ETK_D11 OMAP343X_PADCONF_ETK(13) +#define OMAP343X_PADCONF_ETK_D12 OMAP343X_PADCONF_ETK(14) +#define OMAP343X_PADCONF_ETK_D13 OMAP343X_PADCONF_ETK(15) +#define OMAP343X_PADCONF_ETK_D14 OMAP343X_PADCONF_ETK(16) +#define OMAP343X_PADCONF_ETK_D15 OMAP343X_PADCONF_ETK(17) + +/* 34xx GENERAL_WKUP regist offsets */ +#define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) (OMAP343X_CONTROL_GENERAL_WKUP + \ + 0x008 + (i)) +#define OMAP343X_CONTROL_WKUP_DEBOBS0 (OMAP343X_CONTROL_GENERAL_WKUP + 0x008) +#define OMAP343X_CONTROL_WKUP_DEBOBS1 (OMAP343X_CONTROL_GENERAL_WKUP + 0x00C) +#define OMAP343X_CONTROL_WKUP_DEBOBS2 (OMAP343X_CONTROL_GENERAL_WKUP + 0x010) +#define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014) +#define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018) + +/* 34xx D2D idle-related pins, handled by PM core */ +#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250 +#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254 + +/* + * REVISIT: This list of registers is not comprehensive - there are more + * that should be added. + */ + +/* + * Control module register bit defines - these should eventually go into + * their own regbits file. Some of these will be complicated, depending + * on the device type (general-purpose, emulator, test, secure, bad, other) + * and the security mode (secure, non-secure, don't care) + */ +/* CONTROL_DEVCONF0 bits */ +#define OMAP2_MMCSDIO1ADPCLKISEL (1 << 24) /* MMC1 loop back clock */ +#define OMAP24XX_USBSTANDBYCTRL (1 << 15) +#define OMAP2_MCBSP2_CLKS_MASK (1 << 6) +#define OMAP2_MCBSP1_FSR_MASK (1 << 4) +#define OMAP2_MCBSP1_CLKR_MASK (1 << 3) +#define OMAP2_MCBSP1_CLKS_MASK (1 << 2) + +/* CONTROL_DEVCONF1 bits */ +#define OMAP243X_MMC1_ACTIVE_OVERWRITE (1 << 31) +#define OMAP2_MMCSDIO2ADPCLKISEL (1 << 6) /* MMC2 loop back clock */ +#define OMAP2_MCBSP5_CLKS_MASK (1 << 4) /* > 242x */ +#define OMAP2_MCBSP4_CLKS_MASK (1 << 2) /* > 242x */ +#define OMAP2_MCBSP3_CLKS_MASK (1 << 0) /* > 242x */ + +/* CONTROL_STATUS bits */ +#define OMAP2_DEVICETYPE_MASK (0x7 << 8) +#define OMAP2_SYSBOOT_5_MASK (1 << 5) +#define OMAP2_SYSBOOT_4_MASK (1 << 4) +#define OMAP2_SYSBOOT_3_MASK (1 << 3) +#define OMAP2_SYSBOOT_2_MASK (1 << 2) +#define OMAP2_SYSBOOT_1_MASK (1 << 1) +#define OMAP2_SYSBOOT_0_MASK (1 << 0) + +/* CONTROL_PBIAS_LITE bits */ +#define OMAP343X_PBIASLITESUPPLY_HIGH1 (1 << 15) +#define OMAP343X_PBIASLITEVMODEERROR1 (1 << 11) +#define OMAP343X_PBIASSPEEDCTRL1 (1 << 10) +#define OMAP343X_PBIASLITEPWRDNZ1 (1 << 9) +#define OMAP343X_PBIASLITEVMODE1 (1 << 8) +#define OMAP343X_PBIASLITESUPPLY_HIGH0 (1 << 7) +#define OMAP343X_PBIASLITEVMODEERROR0 (1 << 3) +#define OMAP2_PBIASSPEEDCTRL0 (1 << 2) +#define OMAP2_PBIASLITEPWRDNZ0 (1 << 1) +#define OMAP2_PBIASLITEVMODE0 (1 << 0) + +/* CONTROL_PROG_IO1 bits */ +#define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20) + +/* CONTROL_IVA2_BOOTMOD bits */ +#define OMAP3_IVA2_BOOTMOD_SHIFT 0 +#define OMAP3_IVA2_BOOTMOD_MASK (0xf << 0) +#define OMAP3_IVA2_BOOTMOD_IDLE (0x1 << 0) + +/* CONTROL_PADCONF_X bits */ +#define OMAP3_PADCONF_WAKEUPEVENT0 (1 << 15) +#define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14) + +#define OMAP343X_SCRATCHPAD_ROM (OMAP343X_CTRL_BASE + 0x860) +#define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910) +#define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C + +/* AM35XX_CONTROL_IPSS_CLK_CTRL bits */ +#define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0 +#define AM35XX_CPGMAC_VBUSP_CLK_SHIFT 1 +#define AM35XX_VPFE_VBUSP_CLK_SHIFT 2 +#define AM35XX_HECC_VBUSP_CLK_SHIFT 3 +#define AM35XX_USBOTG_FCLK_SHIFT 8 +#define AM35XX_CPGMAC_FCLK_SHIFT 9 +#define AM35XX_VPFE_FCLK_SHIFT 10 + +/*AM35XX CONTROL_LVL_INTR_CLEAR bits*/ +#define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0) +#define AM35XX_CPGMAC_C0_RX_PULSE_CLR BIT(1) +#define AM35XX_CPGMAC_C0_RX_THRESH_CLR BIT(2) +#define AM35XX_CPGMAC_C0_TX_PULSE_CLR BIT(3) +#define AM35XX_USBOTGSS_INT_CLR BIT(4) +#define AM35XX_VPFE_CCDC_VD0_INT_CLR BIT(5) +#define AM35XX_VPFE_CCDC_VD1_INT_CLR BIT(6) +#define AM35XX_VPFE_CCDC_VD2_INT_CLR BIT(7) + +/*AM35XX CONTROL_IP_SW_RESET bits*/ +#define AM35XX_USBOTGSS_SW_RST BIT(0) +#define AM35XX_CPGMACSS_SW_RST BIT(1) +#define AM35XX_VPFE_VBUSP_SW_RST BIT(2) +#define AM35XX_HECC_SW_RST BIT(3) +#define AM35XX_VPFE_PCLK_SW_RST BIT(4) + +/* + * CONTROL OMAP STATUS register to identify OMAP3 features + */ +#define OMAP3_CONTROL_OMAP_STATUS 0x044c + +#define OMAP3_SGX_SHIFT 13 +#define OMAP3_SGX_MASK (3 << OMAP3_SGX_SHIFT) +#define FEAT_SGX_FULL 0 +#define FEAT_SGX_HALF 1 +#define FEAT_SGX_NONE 2 + +#define OMAP3_IVA_SHIFT 12 +#define OMAP3_IVA_MASK (1 << OMAP3_SGX_SHIFT) +#define FEAT_IVA 0 +#define FEAT_IVA_NONE 1 + +#define OMAP3_L2CACHE_SHIFT 10 +#define OMAP3_L2CACHE_MASK (3 << OMAP3_L2CACHE_SHIFT) +#define FEAT_L2CACHE_NONE 0 +#define FEAT_L2CACHE_64KB 1 +#define FEAT_L2CACHE_128KB 2 +#define FEAT_L2CACHE_256KB 3 + +#define OMAP3_ISP_SHIFT 5 +#define OMAP3_ISP_MASK (1 << OMAP3_ISP_SHIFT) +#define FEAT_ISP 0 +#define FEAT_ISP_NONE 1 + +#define OMAP3_NEON_SHIFT 4 +#define OMAP3_NEON_MASK (1 << OMAP3_NEON_SHIFT) +#define FEAT_NEON 0 +#define FEAT_NEON_NONE 1 + + +#ifndef __ASSEMBLY__ +#ifdef CONFIG_ARCH_OMAP2PLUS +extern void __iomem *omap_ctrl_base_get(void); +extern u8 omap_ctrl_readb(u16 offset); +extern u16 omap_ctrl_readw(u16 offset); +extern u32 omap_ctrl_readl(u16 offset); +extern u32 omap4_ctrl_pad_readl(u16 offset); +extern void omap_ctrl_writeb(u8 val, u16 offset); +extern void omap_ctrl_writew(u16 val, u16 offset); +extern void omap_ctrl_writel(u32 val, u16 offset); +extern void omap4_ctrl_pad_writel(u32 val, u16 offset); + +extern void omap3_save_scratchpad_contents(void); +extern void omap3_clear_scratchpad_contents(void); +extern u32 *get_restore_pointer(void); +extern u32 *get_es3_restore_pointer(void); +extern u32 omap3_arm_context[128]; +extern void omap3_control_save_context(void); +extern void omap3_control_restore_context(void); + +#else +#define omap_ctrl_base_get() 0 +#define omap_ctrl_readb(x) 0 +#define omap_ctrl_readw(x) 0 +#define omap_ctrl_readl(x) 0 +#define omap4_ctrl_pad_readl(x) 0 +#define omap_ctrl_writeb(x, y) WARN_ON(1) +#define omap_ctrl_writew(x, y) WARN_ON(1) +#define omap_ctrl_writel(x, y) WARN_ON(1) +#define omap4_ctrl_pad_writel(x, y) WARN_ON(1) +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_ARM_MACH_OMAP2_CONTROL_H */ + diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c index 703b5ec..0d50b45 100644 --- a/arch/arm/mach-omap2/cpuidle34xx.c +++ b/arch/arm/mach-omap2/cpuidle34xx.c @@ -29,10 +29,10 @@ #include #include #include -#include #include #include "pm.h" +#include "control.h" #ifdef CONFIG_CPU_IDLE diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 818452a..eaf3799 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -9,7 +9,6 @@ * (at your option) any later version. */ -#include #include #include #include @@ -23,7 +22,6 @@ #include #include -#include #include #include #include @@ -33,6 +31,7 @@ #include #include "mux.h" +#include "control.h" #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE) diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c index ab78a5a..34272e4 100644 --- a/arch/arm/mach-omap2/hsmmc.c +++ b/arch/arm/mach-omap2/hsmmc.c @@ -14,11 +14,11 @@ #include #include #include -#include #include #include #include "hsmmc.h" +#include "control.h" #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 04a2fa2..5f9086c 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -22,11 +22,12 @@ #include #include -#include #include #include +#include "control.h" + static struct omap_chip_id omap_chip; static unsigned int omap_revision; diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index 51abced..eba9fa1 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c @@ -22,7 +22,9 @@ #include #include #include -#include + +#include "control.h" + /* McBSP internal signal muxing functions */ diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index e33740c..074536a 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c @@ -23,12 +23,11 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA * */ -#include +#include #include #include -#include -#include #include +#include #include #include #include @@ -36,8 +35,7 @@ #include -#include - +#include "control.h" #include "mux.h" #define OMAP_MUX_BASE_OFFSET 0x30 /* Offset from CTRL_BASE */ diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index f5c7ef9..a40457d 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -38,7 +38,6 @@ #include #include #include -#include #include #include @@ -48,6 +47,7 @@ #include "cm-regbits-24xx.h" #include "sdrc.h" #include "pm.h" +#include "control.h" #include #include diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index e57c9ae..8c8f1acd 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -32,7 +32,6 @@ #include #include #include -#include #include #include #include @@ -48,6 +47,7 @@ #include "prm.h" #include "pm.h" #include "sdrc.h" +#include "control.h" /* Scratchpad offsets */ #define OMAP343X_TABLE_ADDRESS_OFFSET 0x31 diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c index a48a1e2..a51846e 100644 --- a/arch/arm/mach-omap2/prcm.c +++ b/arch/arm/mach-omap2/prcm.c @@ -26,7 +26,6 @@ #include #include #include -#include #include "clock.h" #include "clock2xxx.h" @@ -34,6 +33,7 @@ #include "prm.h" #include "prm-regbits-24xx.h" #include "prm-regbits-44xx.h" +#include "control.h" static void __iomem *prm_base; static void __iomem *cm_base; diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index 0bcc9df..338e46a 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -35,7 +35,6 @@ #include #include #include -#include #include #include #include @@ -44,6 +43,7 @@ #include "pm.h" #include "cm.h" #include "prm-regbits-34xx.h" +#include "control.h" #define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52 #define UART_OMAP_WER 0x17 /* Wake-up enable register */ diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S index ba53191..2fb205a 100644 --- a/arch/arm/mach-omap2/sleep34xx.S +++ b/arch/arm/mach-omap2/sleep34xx.S @@ -27,11 +27,11 @@ #include #include #include -#include #include "cm.h" #include "prm.h" #include "sdrc.h" +#include "control.h" #define SDRC_SCRATCHPAD_SEM_V 0xfa00291c diff --git a/arch/arm/mach-omap2/usb-fs.c b/arch/arm/mach-omap2/usb-fs.c index a216d88..1481078 100644 --- a/arch/arm/mach-omap2/usb-fs.c +++ b/arch/arm/mach-omap2/usb-fs.c @@ -29,18 +29,18 @@ #include -#include #include #include +#include "control.h" +#include "mux.h" + #define INT_USB_IRQ_GEN INT_24XX_USB_IRQ_GEN #define INT_USB_IRQ_NISO INT_24XX_USB_IRQ_NISO #define INT_USB_IRQ_ISO INT_24XX_USB_IRQ_ISO #define INT_USB_IRQ_HGEN INT_24XX_USB_IRQ_HGEN #define INT_USB_IRQ_OTG INT_24XX_USB_IRQ_OTG -#include "mux.h" - #if defined(CONFIG_ARCH_OMAP2) #ifdef CONFIG_USB_GADGET_OMAP diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/plat-omap/include/plat/control.h deleted file mode 100644 index 54b0c35..0000000 --- a/arch/arm/plat-omap/include/plat/control.h +++ /dev/null @@ -1,368 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/control.h - * - * OMAP2/3/4 System Control Module definitions - * - * Copyright (C) 2007-2009 Texas Instruments, Inc. - * Copyright (C) 2007-2008 Nokia Corporation - * - * Written by Paul Walmsley - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_CONTROL_H -#define __ASM_ARCH_CONTROL_H - -#include -#include -#include -#include -#include - -#ifndef __ASSEMBLY__ -#define OMAP242X_CTRL_REGADDR(reg) \ - OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) -#define OMAP243X_CTRL_REGADDR(reg) \ - OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) -#define OMAP343X_CTRL_REGADDR(reg) \ - OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) -#else -#define OMAP242X_CTRL_REGADDR(reg) \ - OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) -#define OMAP243X_CTRL_REGADDR(reg) \ - OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) -#define OMAP343X_CTRL_REGADDR(reg) \ - OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) -#endif /* __ASSEMBLY__ */ - -/* - * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for - * OMAP24XX and OMAP34XX. - */ - -/* Control submodule offsets */ - -#define OMAP2_CONTROL_INTERFACE 0x000 -#define OMAP2_CONTROL_PADCONFS 0x030 -#define OMAP2_CONTROL_GENERAL 0x270 -#define OMAP343X_CONTROL_MEM_WKUP 0x600 -#define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00 -#define OMAP343X_CONTROL_GENERAL_WKUP 0xa60 - -/* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */ - -#define OMAP2_CONTROL_SYSCONFIG (OMAP2_CONTROL_INTERFACE + 0x10) - -/* CONTROL_GENERAL register offsets common to OMAP2 & 3 */ -#define OMAP2_CONTROL_DEVCONF0 (OMAP2_CONTROL_GENERAL + 0x0004) -#define OMAP2_CONTROL_MSUSPENDMUX_0 (OMAP2_CONTROL_GENERAL + 0x0020) -#define OMAP2_CONTROL_MSUSPENDMUX_1 (OMAP2_CONTROL_GENERAL + 0x0024) -#define OMAP2_CONTROL_MSUSPENDMUX_2 (OMAP2_CONTROL_GENERAL + 0x0028) -#define OMAP2_CONTROL_MSUSPENDMUX_3 (OMAP2_CONTROL_GENERAL + 0x002c) -#define OMAP2_CONTROL_MSUSPENDMUX_4 (OMAP2_CONTROL_GENERAL + 0x0030) -#define OMAP2_CONTROL_MSUSPENDMUX_5 (OMAP2_CONTROL_GENERAL + 0x0034) -#define OMAP2_CONTROL_SEC_CTRL (OMAP2_CONTROL_GENERAL + 0x0040) -#define OMAP2_CONTROL_RPUB_KEY_H_0 (OMAP2_CONTROL_GENERAL + 0x0090) -#define OMAP2_CONTROL_RPUB_KEY_H_1 (OMAP2_CONTROL_GENERAL + 0x0094) -#define OMAP2_CONTROL_RPUB_KEY_H_2 (OMAP2_CONTROL_GENERAL + 0x0098) -#define OMAP2_CONTROL_RPUB_KEY_H_3 (OMAP2_CONTROL_GENERAL + 0x009c) - -/* 242x-only CONTROL_GENERAL register offsets */ -#define OMAP242X_CONTROL_DEVCONF OMAP2_CONTROL_DEVCONF0 /* match TRM */ -#define OMAP242X_CONTROL_OCM_RAM_PERM (OMAP2_CONTROL_GENERAL + 0x0068) - -/* 243x-only CONTROL_GENERAL register offsets */ -/* CONTROL_IVA2_BOOT{ADDR,MOD} are at the same place on 343x - noted below */ -#define OMAP243X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0078) -#define OMAP243X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x007c) -#define OMAP243X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) -#define OMAP243X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) -#define OMAP243X_CONTROL_IVA2_GEMCFG (OMAP2_CONTROL_GENERAL + 0x0198) -#define OMAP243X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x0230) - -/* 24xx-only CONTROL_GENERAL register offsets */ -#define OMAP24XX_CONTROL_DEBOBS (OMAP2_CONTROL_GENERAL + 0x0000) -#define OMAP24XX_CONTROL_EMU_SUPPORT (OMAP2_CONTROL_GENERAL + 0x0008) -#define OMAP24XX_CONTROL_SEC_TEST (OMAP2_CONTROL_GENERAL + 0x0044) -#define OMAP24XX_CONTROL_PSA_CTRL (OMAP2_CONTROL_GENERAL + 0x0048) -#define OMAP24XX_CONTROL_PSA_CMD (OMAP2_CONTROL_GENERAL + 0x004c) -#define OMAP24XX_CONTROL_PSA_VALUE (OMAP2_CONTROL_GENERAL + 0x0050) -#define OMAP24XX_CONTROL_SEC_EMU (OMAP2_CONTROL_GENERAL + 0x0060) -#define OMAP24XX_CONTROL_SEC_TAP (OMAP2_CONTROL_GENERAL + 0x0064) -#define OMAP24XX_CONTROL_OCM_PUB_RAM_ADD (OMAP2_CONTROL_GENERAL + 0x006c) -#define OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD (OMAP2_CONTROL_GENERAL + 0x0070) -#define OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD (OMAP2_CONTROL_GENERAL + 0x0074) -#define OMAP24XX_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0080) -#define OMAP24XX_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0084) -#define OMAP24XX_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0088) -#define OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x008c) -#define OMAP24XX_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a0) -#define OMAP24XX_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00a4) -#define OMAP24XX_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00a8) -#define OMAP24XX_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00ac) -#define OMAP24XX_CONTROL_CUST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00b0) -#define OMAP24XX_CONTROL_CUST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00b4) -#define OMAP24XX_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c0) -#define OMAP24XX_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00c4) -#define OMAP24XX_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00c8) -#define OMAP24XX_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00cc) -#define OMAP24XX_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d0) -#define OMAP24XX_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00d4) -#define OMAP24XX_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00d8) -#define OMAP24XX_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00dc) -#define OMAP24XX_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e0) -#define OMAP24XX_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00e4) - -#define OMAP343X_CONTROL_PADCONF_SYSNIRQ (OMAP2_CONTROL_INTERFACE + 0x01b0) - -/* 34xx-only CONTROL_GENERAL register offsets */ -#define OMAP343X_CONTROL_PADCONF_OFF (OMAP2_CONTROL_GENERAL + 0x0000) -#define OMAP343X_CONTROL_MEM_DFTRW0 (OMAP2_CONTROL_GENERAL + 0x0008) -#define OMAP343X_CONTROL_MEM_DFTRW1 (OMAP2_CONTROL_GENERAL + 0x000c) -#define OMAP343X_CONTROL_DEVCONF1 (OMAP2_CONTROL_GENERAL + 0x0068) -#define OMAP343X_CONTROL_CSIRXFE (OMAP2_CONTROL_GENERAL + 0x006c) -#define OMAP343X_CONTROL_SEC_STATUS (OMAP2_CONTROL_GENERAL + 0x0070) -#define OMAP343X_CONTROL_SEC_ERR_STATUS (OMAP2_CONTROL_GENERAL + 0x0074) -#define OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG (OMAP2_CONTROL_GENERAL + 0x0078) -#define OMAP343X_CONTROL_STATUS (OMAP2_CONTROL_GENERAL + 0x0080) -#define OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS (OMAP2_CONTROL_GENERAL + 0x0084) -#define OMAP343X_CONTROL_RPUB_KEY_H_4 (OMAP2_CONTROL_GENERAL + 0x00a0) -#define OMAP343X_CONTROL_RAND_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00a8) -#define OMAP343X_CONTROL_RAND_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00ac) -#define OMAP343X_CONTROL_RAND_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00b0) -#define OMAP343X_CONTROL_RAND_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00b4) -#define OMAP343X_CONTROL_TEST_KEY_0 (OMAP2_CONTROL_GENERAL + 0x00c8) -#define OMAP343X_CONTROL_TEST_KEY_1 (OMAP2_CONTROL_GENERAL + 0x00cc) -#define OMAP343X_CONTROL_TEST_KEY_2 (OMAP2_CONTROL_GENERAL + 0x00d0) -#define OMAP343X_CONTROL_TEST_KEY_3 (OMAP2_CONTROL_GENERAL + 0x00d4) -#define OMAP343X_CONTROL_TEST_KEY_4 (OMAP2_CONTROL_GENERAL + 0x00d8) -#define OMAP343X_CONTROL_TEST_KEY_5 (OMAP2_CONTROL_GENERAL + 0x00dc) -#define OMAP343X_CONTROL_TEST_KEY_6 (OMAP2_CONTROL_GENERAL + 0x00e0) -#define OMAP343X_CONTROL_TEST_KEY_7 (OMAP2_CONTROL_GENERAL + 0x00e4) -#define OMAP343X_CONTROL_TEST_KEY_8 (OMAP2_CONTROL_GENERAL + 0x00e8) -#define OMAP343X_CONTROL_TEST_KEY_9 (OMAP2_CONTROL_GENERAL + 0x00ec) -#define OMAP343X_CONTROL_TEST_KEY_10 (OMAP2_CONTROL_GENERAL + 0x00f0) -#define OMAP343X_CONTROL_TEST_KEY_11 (OMAP2_CONTROL_GENERAL + 0x00f4) -#define OMAP343X_CONTROL_TEST_KEY_12 (OMAP2_CONTROL_GENERAL + 0x00f8) -#define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc) -#define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) -#define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) -#define OMAP343X_CONTROL_DEBOBS(i) (OMAP2_CONTROL_GENERAL + 0x01B0 \ - + ((i) >> 1) * 4 + (!((i) & 1)) * 2) -#define OMAP343X_CONTROL_PROG_IO0 (OMAP2_CONTROL_GENERAL + 0x01D4) -#define OMAP343X_CONTROL_PROG_IO1 (OMAP2_CONTROL_GENERAL + 0x01D8) -#define OMAP343X_CONTROL_DSS_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E0) -#define OMAP343X_CONTROL_CORE_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E4) -#define OMAP343X_CONTROL_PER_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01E8) -#define OMAP343X_CONTROL_USBHOST_DPLL_SPREADING (OMAP2_CONTROL_GENERAL + 0x01EC) -#define OMAP343X_CONTROL_PBIAS_LITE (OMAP2_CONTROL_GENERAL + 0x02B0) -#define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02B4) -#define OMAP343X_CONTROL_SRAMLDO4 (OMAP2_CONTROL_GENERAL + 0x02B8) -#define OMAP343X_CONTROL_SRAMLDO5 (OMAP2_CONTROL_GENERAL + 0x02C0) -#define OMAP343X_CONTROL_CSI (OMAP2_CONTROL_GENERAL + 0x02C4) - -/* AM35XX only CONTROL_GENERAL register offsets */ -#define AM35XX_CONTROL_MSUSPENDMUX_6 (OMAP2_CONTROL_GENERAL + 0x0038) -#define AM35XX_CONTROL_DEVCONF2 (OMAP2_CONTROL_GENERAL + 0x0310) -#define AM35XX_CONTROL_DEVCONF3 (OMAP2_CONTROL_GENERAL + 0x0314) -#define AM35XX_CONTROL_CBA_PRIORITY (OMAP2_CONTROL_GENERAL + 0x0320) -#define AM35XX_CONTROL_LVL_INTR_CLEAR (OMAP2_CONTROL_GENERAL + 0x0324) -#define AM35XX_CONTROL_IP_SW_RESET (OMAP2_CONTROL_GENERAL + 0x0328) -#define AM35XX_CONTROL_IPSS_CLK_CTRL (OMAP2_CONTROL_GENERAL + 0x032C) - -/* 34xx PADCONF register offsets */ -#define OMAP343X_PADCONF_ETK(i) (OMAP2_CONTROL_PADCONFS + 0x5a8 + \ - (i)*2) -#define OMAP343X_PADCONF_ETK_CLK OMAP343X_PADCONF_ETK(0) -#define OMAP343X_PADCONF_ETK_CTL OMAP343X_PADCONF_ETK(1) -#define OMAP343X_PADCONF_ETK_D0 OMAP343X_PADCONF_ETK(2) -#define OMAP343X_PADCONF_ETK_D1 OMAP343X_PADCONF_ETK(3) -#define OMAP343X_PADCONF_ETK_D2 OMAP343X_PADCONF_ETK(4) -#define OMAP343X_PADCONF_ETK_D3 OMAP343X_PADCONF_ETK(5) -#define OMAP343X_PADCONF_ETK_D4 OMAP343X_PADCONF_ETK(6) -#define OMAP343X_PADCONF_ETK_D5 OMAP343X_PADCONF_ETK(7) -#define OMAP343X_PADCONF_ETK_D6 OMAP343X_PADCONF_ETK(8) -#define OMAP343X_PADCONF_ETK_D7 OMAP343X_PADCONF_ETK(9) -#define OMAP343X_PADCONF_ETK_D8 OMAP343X_PADCONF_ETK(10) -#define OMAP343X_PADCONF_ETK_D9 OMAP343X_PADCONF_ETK(11) -#define OMAP343X_PADCONF_ETK_D10 OMAP343X_PADCONF_ETK(12) -#define OMAP343X_PADCONF_ETK_D11 OMAP343X_PADCONF_ETK(13) -#define OMAP343X_PADCONF_ETK_D12 OMAP343X_PADCONF_ETK(14) -#define OMAP343X_PADCONF_ETK_D13 OMAP343X_PADCONF_ETK(15) -#define OMAP343X_PADCONF_ETK_D14 OMAP343X_PADCONF_ETK(16) -#define OMAP343X_PADCONF_ETK_D15 OMAP343X_PADCONF_ETK(17) - -/* 34xx GENERAL_WKUP regist offsets */ -#define OMAP343X_CONTROL_WKUP_DEBOBSMUX(i) (OMAP343X_CONTROL_GENERAL_WKUP + \ - 0x008 + (i)) -#define OMAP343X_CONTROL_WKUP_DEBOBS0 (OMAP343X_CONTROL_GENERAL_WKUP + 0x008) -#define OMAP343X_CONTROL_WKUP_DEBOBS1 (OMAP343X_CONTROL_GENERAL_WKUP + 0x00C) -#define OMAP343X_CONTROL_WKUP_DEBOBS2 (OMAP343X_CONTROL_GENERAL_WKUP + 0x010) -#define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014) -#define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018) - -/* 34xx D2D idle-related pins, handled by PM core */ -#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250 -#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254 - -/* - * REVISIT: This list of registers is not comprehensive - there are more - * that should be added. - */ - -/* - * Control module register bit defines - these should eventually go into - * their own regbits file. Some of these will be complicated, depending - * on the device type (general-purpose, emulator, test, secure, bad, other) - * and the security mode (secure, non-secure, don't care) - */ -/* CONTROL_DEVCONF0 bits */ -#define OMAP2_MMCSDIO1ADPCLKISEL (1 << 24) /* MMC1 loop back clock */ -#define OMAP24XX_USBSTANDBYCTRL (1 << 15) -#define OMAP2_MCBSP2_CLKS_MASK (1 << 6) -#define OMAP2_MCBSP1_FSR_MASK (1 << 4) -#define OMAP2_MCBSP1_CLKR_MASK (1 << 3) -#define OMAP2_MCBSP1_CLKS_MASK (1 << 2) - -/* CONTROL_DEVCONF1 bits */ -#define OMAP243X_MMC1_ACTIVE_OVERWRITE (1 << 31) -#define OMAP2_MMCSDIO2ADPCLKISEL (1 << 6) /* MMC2 loop back clock */ -#define OMAP2_MCBSP5_CLKS_MASK (1 << 4) /* > 242x */ -#define OMAP2_MCBSP4_CLKS_MASK (1 << 2) /* > 242x */ -#define OMAP2_MCBSP3_CLKS_MASK (1 << 0) /* > 242x */ - -/* CONTROL_STATUS bits */ -#define OMAP2_DEVICETYPE_MASK (0x7 << 8) -#define OMAP2_SYSBOOT_5_MASK (1 << 5) -#define OMAP2_SYSBOOT_4_MASK (1 << 4) -#define OMAP2_SYSBOOT_3_MASK (1 << 3) -#define OMAP2_SYSBOOT_2_MASK (1 << 2) -#define OMAP2_SYSBOOT_1_MASK (1 << 1) -#define OMAP2_SYSBOOT_0_MASK (1 << 0) - -/* CONTROL_PBIAS_LITE bits */ -#define OMAP343X_PBIASLITESUPPLY_HIGH1 (1 << 15) -#define OMAP343X_PBIASLITEVMODEERROR1 (1 << 11) -#define OMAP343X_PBIASSPEEDCTRL1 (1 << 10) -#define OMAP343X_PBIASLITEPWRDNZ1 (1 << 9) -#define OMAP343X_PBIASLITEVMODE1 (1 << 8) -#define OMAP343X_PBIASLITESUPPLY_HIGH0 (1 << 7) -#define OMAP343X_PBIASLITEVMODEERROR0 (1 << 3) -#define OMAP2_PBIASSPEEDCTRL0 (1 << 2) -#define OMAP2_PBIASLITEPWRDNZ0 (1 << 1) -#define OMAP2_PBIASLITEVMODE0 (1 << 0) - -/* CONTROL_PROG_IO1 bits */ -#define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20) - -/* CONTROL_IVA2_BOOTMOD bits */ -#define OMAP3_IVA2_BOOTMOD_SHIFT 0 -#define OMAP3_IVA2_BOOTMOD_MASK (0xf << 0) -#define OMAP3_IVA2_BOOTMOD_IDLE (0x1 << 0) - -/* CONTROL_PADCONF_X bits */ -#define OMAP3_PADCONF_WAKEUPEVENT0 (1 << 15) -#define OMAP3_PADCONF_WAKEUPENABLE0 (1 << 14) - -#define OMAP343X_SCRATCHPAD_ROM (OMAP343X_CTRL_BASE + 0x860) -#define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910) -#define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C - -/* AM35XX_CONTROL_IPSS_CLK_CTRL bits */ -#define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0 -#define AM35XX_CPGMAC_VBUSP_CLK_SHIFT 1 -#define AM35XX_VPFE_VBUSP_CLK_SHIFT 2 -#define AM35XX_HECC_VBUSP_CLK_SHIFT 3 -#define AM35XX_USBOTG_FCLK_SHIFT 8 -#define AM35XX_CPGMAC_FCLK_SHIFT 9 -#define AM35XX_VPFE_FCLK_SHIFT 10 - -/*AM35XX CONTROL_LVL_INTR_CLEAR bits*/ -#define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0) -#define AM35XX_CPGMAC_C0_RX_PULSE_CLR BIT(1) -#define AM35XX_CPGMAC_C0_RX_THRESH_CLR BIT(2) -#define AM35XX_CPGMAC_C0_TX_PULSE_CLR BIT(3) -#define AM35XX_USBOTGSS_INT_CLR BIT(4) -#define AM35XX_VPFE_CCDC_VD0_INT_CLR BIT(5) -#define AM35XX_VPFE_CCDC_VD1_INT_CLR BIT(6) -#define AM35XX_VPFE_CCDC_VD2_INT_CLR BIT(7) - -/*AM35XX CONTROL_IP_SW_RESET bits*/ -#define AM35XX_USBOTGSS_SW_RST BIT(0) -#define AM35XX_CPGMACSS_SW_RST BIT(1) -#define AM35XX_VPFE_VBUSP_SW_RST BIT(2) -#define AM35XX_HECC_SW_RST BIT(3) -#define AM35XX_VPFE_PCLK_SW_RST BIT(4) - -/* - * CONTROL OMAP STATUS register to identify OMAP3 features - */ -#define OMAP3_CONTROL_OMAP_STATUS 0x044c - -#define OMAP3_SGX_SHIFT 13 -#define OMAP3_SGX_MASK (3 << OMAP3_SGX_SHIFT) -#define FEAT_SGX_FULL 0 -#define FEAT_SGX_HALF 1 -#define FEAT_SGX_NONE 2 - -#define OMAP3_IVA_SHIFT 12 -#define OMAP3_IVA_MASK (1 << OMAP3_SGX_SHIFT) -#define FEAT_IVA 0 -#define FEAT_IVA_NONE 1 - -#define OMAP3_L2CACHE_SHIFT 10 -#define OMAP3_L2CACHE_MASK (3 << OMAP3_L2CACHE_SHIFT) -#define FEAT_L2CACHE_NONE 0 -#define FEAT_L2CACHE_64KB 1 -#define FEAT_L2CACHE_128KB 2 -#define FEAT_L2CACHE_256KB 3 - -#define OMAP3_ISP_SHIFT 5 -#define OMAP3_ISP_MASK (1<< OMAP3_ISP_SHIFT) -#define FEAT_ISP 0 -#define FEAT_ISP_NONE 1 - -#define OMAP3_NEON_SHIFT 4 -#define OMAP3_NEON_MASK (1<< OMAP3_NEON_SHIFT) -#define FEAT_NEON 0 -#define FEAT_NEON_NONE 1 - - -#ifndef __ASSEMBLY__ -#ifdef CONFIG_ARCH_OMAP2PLUS -extern void __iomem *omap_ctrl_base_get(void); -extern u8 omap_ctrl_readb(u16 offset); -extern u16 omap_ctrl_readw(u16 offset); -extern u32 omap_ctrl_readl(u16 offset); -extern u32 omap4_ctrl_pad_readl(u16 offset); -extern void omap_ctrl_writeb(u8 val, u16 offset); -extern void omap_ctrl_writew(u16 val, u16 offset); -extern void omap_ctrl_writel(u32 val, u16 offset); -extern void omap4_ctrl_pad_writel(u32 val, u16 offset); - -extern void omap3_save_scratchpad_contents(void); -extern void omap3_clear_scratchpad_contents(void); -extern u32 *get_restore_pointer(void); -extern u32 *get_es3_restore_pointer(void); -extern u32 omap3_arm_context[128]; -extern void omap3_control_save_context(void); -extern void omap3_control_restore_context(void); - -#else -#define omap_ctrl_base_get() 0 -#define omap_ctrl_readb(x) 0 -#define omap_ctrl_readw(x) 0 -#define omap_ctrl_readl(x) 0 -#define omap4_ctrl_pad_readl(x) 0 -#define omap_ctrl_writeb(x, y) WARN_ON(1) -#define omap_ctrl_writew(x, y) WARN_ON(1) -#define omap_ctrl_writel(x, y) WARN_ON(1) -#define omap4_ctrl_pad_writel(x, y) WARN_ON(1) -#endif -#endif /* __ASSEMBLY__ */ - -#endif /* __ASM_ARCH_CONTROL_H */ - diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h index 0d6f076..c8dae02 100644 --- a/arch/arm/plat-omap/include/plat/omap-serial.h +++ b/arch/arm/plat-omap/include/plat/omap-serial.h @@ -20,7 +20,6 @@ #include #include -#include #include #define DRIVER_NAME "omap-hsuart" diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index 09f8c287..45d99e9 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c @@ -27,7 +27,6 @@ #include #include -#include #include "../mach-omap2/cm-regbits-34xx.h" -- cgit v1.1 From 6041c27f51f237b59ea0838c33e08223cf98e43e Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Fri, 8 Oct 2010 11:40:20 -0600 Subject: OMAP2+: clock: reduce the amount of standard debugging while disabling unused clocks Reduce the amount of debugging generated by default when unused clocks are being disabled by the clock code. The previous code would only generate debug-level messages, but some people who wished to run production kernels with debug-level messages enabled reported that the large number of clock disable messages were slowing boot. Now to enable clock-by-clock disable messages, DEBUG needs to be defined in mach-omap2/clock.c. Signed-off-by: Paul Walmsley Cc: Tuukka Tikkanen Cc: Tim Bird --- arch/arm/mach-omap2/clock.c | 2 +- arch/arm/plat-omap/clock.c | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 605f531..b5babf5 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -395,7 +395,7 @@ void omap2_clk_disable_unused(struct clk *clk) if ((regval32 & (1 << clk->enable_bit)) == v) return; - printk(KERN_DEBUG "Disabling unused clock \"%s\"\n", clk->name); + pr_debug("Disabling unused clock \"%s\"\n", clk->name); if (cpu_is_omap34xx()) { omap2_clk_enable(clk); omap2_clk_disable(clk); diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c index 7190cbd..fc62fb5 100644 --- a/arch/arm/plat-omap/clock.c +++ b/arch/arm/plat-omap/clock.c @@ -60,7 +60,7 @@ void clk_disable(struct clk *clk) spin_lock_irqsave(&clockfw_lock, flags); if (clk->usecount == 0) { - printk(KERN_ERR "Trying disable clock %s with 0 usecount\n", + pr_err("Trying disable clock %s with 0 usecount\n", clk->name); WARN_ON(1); goto out; @@ -397,6 +397,7 @@ static int __init clk_disable_unused(void) struct clk *ck; unsigned long flags; + pr_info("clock: disabling unused clocks to save power\n"); list_for_each_entry(ck, &clocks, node) { if (ck->ops == &clkops_null) continue; @@ -418,7 +419,7 @@ late_initcall(clk_disable_unused); int __init clk_init(struct clk_functions * custom_clocks) { if (!custom_clocks) { - printk(KERN_ERR "No custom clock functions registered\n"); + pr_err("No custom clock functions registered\n"); BUG(); } -- cgit v1.1 From 425925dd750acc17234977decfda1f9cc223389a Mon Sep 17 00:00:00 2001 From: Jarkko Nikula Date: Fri, 8 Oct 2010 11:40:20 -0600 Subject: OMAP: McBSP: Fix CLKR and FSR signal muxing Fix bit clear. Now it clears all other bits than mask bit where it should clear only it. Signed-off-by: Jarkko Nikula Acked-by: Paul Walmsley Acked-by: Peter Ujfalusi --- arch/arm/mach-omap2/mcbsp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index eba9fa1..f6b772e 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c @@ -34,7 +34,7 @@ void omap2_mcbsp1_mux_clkr_src(u8 mux) v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); if (mux == CLKR_SRC_CLKR) - v &= OMAP2_MCBSP1_CLKR_MASK; + v &= ~OMAP2_MCBSP1_CLKR_MASK; else if (mux == CLKR_SRC_CLKX) v |= OMAP2_MCBSP1_CLKR_MASK; omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0); @@ -47,7 +47,7 @@ void omap2_mcbsp1_mux_fsr_src(u8 mux) v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); if (mux == FSR_SRC_FSR) - v &= OMAP2_MCBSP1_FSR_MASK; + v &= ~OMAP2_MCBSP1_FSR_MASK; else if (mux == FSR_SRC_FSX) v |= OMAP2_MCBSP1_FSR_MASK; omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0); -- cgit v1.1 From e4cc41d7bc31cbf99fc633e4d3ab708b55696096 Mon Sep 17 00:00:00 2001 From: Jarkko Nikula Date: Fri, 8 Oct 2010 11:40:21 -0600 Subject: OMAP: McBSP: Swap CLKS source definition This is just a readability and debugging improvement. As selection bit in DEVCONF register is cleared when using 96 MHz PRCM source and set when using external CLKS pin, change definitions to be sync with these. Signed-off-by: Jarkko Nikula Acked-by: Paul Walmsley Acked-by: Peter Ujfalusi --- arch/arm/plat-omap/include/plat/mcbsp.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h index 4da6f94a..e19abf2 100644 --- a/arch/arm/plat-omap/include/plat/mcbsp.h +++ b/arch/arm/plat-omap/include/plat/mcbsp.h @@ -321,8 +321,8 @@ #define FSR_SRC_FSX 1 /* McBSP functional clock sources */ -#define MCBSP_CLKS_PAD_SRC 0 -#define MCBSP_CLKS_PRCM_SRC 1 +#define MCBSP_CLKS_PRCM_SRC 0 +#define MCBSP_CLKS_PAD_SRC 1 /* we don't do multichannel for now */ struct omap_mcbsp_reg_cfg { -- cgit v1.1 From 4367260c0bc1773c00b2309a31b31657cabfda3f Mon Sep 17 00:00:00 2001 From: Jarkko Nikula Date: Fri, 8 Oct 2010 11:40:21 -0600 Subject: OMAP: McBSP: Remove null omap44xx ops comment It seems these comments where accidentally added so remove them. Signed-off-by: Jarkko Nikula Acked-by: Paul Walmsley Acked-by: Peter Ujfalusi --- arch/arm/mach-omap2/mcbsp.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index f6b772e..f9c9df5 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c @@ -240,21 +240,18 @@ static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = { .dma_rx_sync = OMAP44XX_DMA_MCBSP2_RX, .dma_tx_sync = OMAP44XX_DMA_MCBSP2_TX, .tx_irq = OMAP44XX_IRQ_MCBSP2, - /* XXX .ops ? */ }, { .phys_base = OMAP44XX_MCBSP3_BASE, .dma_rx_sync = OMAP44XX_DMA_MCBSP3_RX, .dma_tx_sync = OMAP44XX_DMA_MCBSP3_TX, .tx_irq = OMAP44XX_IRQ_MCBSP3, - /* XXX .ops ? */ }, { .phys_base = OMAP44XX_MCBSP4_BASE, .dma_rx_sync = OMAP44XX_DMA_MCBSP4_RX, .dma_tx_sync = OMAP44XX_DMA_MCBSP4_TX, .tx_irq = OMAP44XX_IRQ_MCBSP4, - /* XXX .ops ? */ }, }; #define OMAP44XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap44xx_mcbsp_pdata) -- cgit v1.1 From 191183b94cc511d0fc2326c83165d95aeabacac4 Mon Sep 17 00:00:00 2001 From: David Anders Date: Thu, 7 Oct 2010 19:36:28 +0000 Subject: omap4: pandaboard: remove unused hsmmc definition remove the second hsmmc definition as it is only used on the expansion header of the PandaBoard and can be mux for other functions. Signed-off-by: David Anders Signed-off-by: Anand Gadiyar Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-omap4panda.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index 83bd1fe..d8c70c1 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -98,10 +98,6 @@ static struct regulator_consumer_supply omap4_panda_vmmc_supply[] = { .supply = "vmmc", .dev_name = "mmci-omap-hs.0", }, - { - .supply = "vmmc", - .dev_name = "mmci-omap-hs.1", - }, }; static int omap4_twl6030_hsmmc_late_init(struct device *dev) @@ -187,7 +183,7 @@ static struct regulator_init_data omap4_panda_vmmc = { | REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, }, - .num_consumer_supplies = 2, + .num_consumer_supplies = 1, .consumer_supplies = omap4_panda_vmmc_supply, }; -- cgit v1.1 From b9b52620823f84f95f3fd94dd6769b7102d7888a Mon Sep 17 00:00:00 2001 From: David Anders Date: Thu, 7 Oct 2010 19:36:29 +0000 Subject: omap4: pandaboard: Fix the init if CONFIG_MMC_OMAP_HS is not set Avoid possible crash if CONFIG_MMC_OMAP_HS is not set. Signed-off-by: David Anders Signed-off-by: Anand Gadiyar Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-omap4panda.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index d8c70c1..e9c6b24 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -116,7 +116,14 @@ static int omap4_twl6030_hsmmc_late_init(struct device *dev) static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev) { - struct omap_mmc_platform_data *pdata = dev->platform_data; + struct omap_mmc_platform_data *pdata; + + /* dev can be null if CONFIG_MMC_OMAP_HS is not set */ + if (!dev) { + pr_err("Failed omap4_twl6030_hsmmc_set_late_init\n"); + return; + } + pdata = dev->platform_data; pdata->init = omap4_twl6030_hsmmc_late_init; } -- cgit v1.1 From 4415beb6fb519c4e98491666838494a8c46cc3ee Mon Sep 17 00:00:00 2001 From: David Anders Date: Thu, 7 Oct 2010 19:36:30 +0000 Subject: omap4: pandaboard: enable the ehci port on pandaboard The OMAP4 PandaBoard has EHCI port1 hooked up to an external SMSC3320 transciever. GPIO 1 is used to power on the transceiver and GPIO 62 for reset on the transceiver. Signed-off-by: David Anders Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-omap4panda.c | 54 ++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index e9c6b24..5eb1a77 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -41,6 +41,9 @@ #include "timer-gp.h" +#define GPIO_HUB_POWER 1 +#define GPIO_HUB_NRESET 62 + static struct gpio_led gpio_leds[] = { { .name = "pandaboard::status1", @@ -78,6 +81,56 @@ static void __init omap4_panda_init_irq(void) omap_gpio_init(); } +static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { + .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, + .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN, + .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, + .phy_reset = false, + .reset_gpio_port[0] = -EINVAL, + .reset_gpio_port[1] = -EINVAL, + .reset_gpio_port[2] = -EINVAL +}; + +static void __init omap4_ehci_init(void) +{ + int ret; + + + /* disable the power to the usb hub prior to init */ + ret = gpio_request(GPIO_HUB_POWER, "hub_power"); + if (ret) { + pr_err("Cannot request GPIO %d\n", GPIO_HUB_POWER); + goto error1; + } + gpio_export(GPIO_HUB_POWER, 0); + gpio_direction_output(GPIO_HUB_POWER, 0); + gpio_set_value(GPIO_HUB_POWER, 0); + + /* reset phy+hub */ + ret = gpio_request(GPIO_HUB_NRESET, "hub_nreset"); + if (ret) { + pr_err("Cannot request GPIO %d\n", GPIO_HUB_NRESET); + goto error2; + } + gpio_export(GPIO_HUB_NRESET, 0); + gpio_direction_output(GPIO_HUB_NRESET, 0); + gpio_set_value(GPIO_HUB_NRESET, 0); + gpio_set_value(GPIO_HUB_NRESET, 1); + + usb_ehci_init(&ehci_pdata); + + /* enable power to hub */ + gpio_set_value(GPIO_HUB_POWER, 1); + return; + +error2: + gpio_free(GPIO_HUB_POWER); +error1: + pr_err("Unable to initialize EHCI power/reset\n"); + return; + +} + static struct omap_musb_board_data musb_board_data = { .interface_type = MUSB_INTERFACE_UTMI, .mode = MUSB_PERIPHERAL, @@ -314,6 +367,7 @@ static void __init omap4_panda_init(void) omap4_twl6030_hsmmc_init(mmc); /* OMAP4 Panda uses internal transceiver so register nop transceiver */ usb_nop_xceiv_register(); + omap4_ehci_init(); /* FIXME: allow multi-omap to boot until musb is updated for omap4 */ if (!cpu_is_omap44xx()) usb_musb_init(&musb_board_data); -- cgit v1.1 From 4e13efc99106723960a27e55f560028bced5076d Mon Sep 17 00:00:00 2001 From: Andres Salomon Date: Fri, 8 Oct 2010 11:34:24 -0700 Subject: sparc: stop exporting openprom.h header It's unknown why openprom.h was being exported; there doesn't seem to be any reason for it currently, and it creates headaches with userspace being able to potentially use the structures in there. So, don't export it anymore. Signed-off-by: Andres Salomon Acked-by: David S. Miller Signed-off-by: Grant Likely --- arch/sparc/include/asm/Kbuild | 1 - 1 file changed, 1 deletion(-) (limited to 'arch') diff --git a/arch/sparc/include/asm/Kbuild b/arch/sparc/include/asm/Kbuild index deeb0fb..3c93f08 100644 --- a/arch/sparc/include/asm/Kbuild +++ b/arch/sparc/include/asm/Kbuild @@ -7,7 +7,6 @@ header-y += display7seg.h header-y += envctrl.h header-y += fbio.h header-y += jsflash.h -header-y += openprom.h header-y += openpromio.h header-y += perfctr.h header-y += psrcompat.h -- cgit v1.1 From 8d1255627d4ce9cb4b9d0a1c44b6c18d92e84a99 Mon Sep 17 00:00:00 2001 From: Andres Salomon Date: Fri, 8 Oct 2010 14:18:11 -0700 Subject: of/sparc: convert various prom_* functions to use phandle Rather than passing around ints everywhere, use the phandle type where appropriate for the various functions that talk to the PROM. Signed-off-by: Andres Salomon Acked-by: David S. Miller Signed-off-by: Grant Likely --- arch/sparc/include/asm/floppy_32.h | 3 +- arch/sparc/include/asm/openprom.h | 16 +++++----- arch/sparc/include/asm/oplib_32.h | 44 +++++++++++++-------------- arch/sparc/include/asm/oplib_64.h | 39 ++++++++++++------------ arch/sparc/kernel/auxio_32.c | 4 +-- arch/sparc/kernel/btext.c | 4 +-- arch/sparc/kernel/devices.c | 23 +++++++------- arch/sparc/kernel/pcic.c | 4 +-- arch/sparc/kernel/setup_64.c | 2 +- arch/sparc/kernel/starfire.c | 2 +- arch/sparc/kernel/tadpole.c | 2 +- arch/sparc/mm/init_64.c | 2 +- arch/sparc/mm/srmmu.c | 8 +++-- arch/sparc/mm/sun4c.c | 2 +- arch/sparc/prom/init_32.c | 2 +- arch/sparc/prom/init_64.c | 4 +-- arch/sparc/prom/memory.c | 3 +- arch/sparc/prom/misc_64.c | 6 ++-- arch/sparc/prom/ranges.c | 6 ++-- arch/sparc/prom/tree_32.c | 58 ++++++++++++++++++----------------- arch/sparc/prom/tree_64.c | 62 +++++++++++++++++++------------------- 21 files changed, 154 insertions(+), 142 deletions(-) (limited to 'arch') diff --git a/arch/sparc/include/asm/floppy_32.h b/arch/sparc/include/asm/floppy_32.h index c792830..86666f7 100644 --- a/arch/sparc/include/asm/floppy_32.h +++ b/arch/sparc/include/asm/floppy_32.h @@ -304,7 +304,8 @@ static struct linux_prom_registers fd_regs[2]; static int sun_floppy_init(void) { char state[128]; - int tnode, fd_node, num_regs; + phandle tnode, fd_node; + int num_regs; struct resource r; use_virtual_dma = 1; diff --git a/arch/sparc/include/asm/openprom.h b/arch/sparc/include/asm/openprom.h index 963e1a4..81cd434 100644 --- a/arch/sparc/include/asm/openprom.h +++ b/arch/sparc/include/asm/openprom.h @@ -11,6 +11,8 @@ #define LINUX_OPPROM_MAGIC 0x10010407 #ifndef __ASSEMBLY__ +#include + /* V0 prom device operations. */ struct linux_dev_v0_funcs { int (*v0_devopen)(char *device_str); @@ -26,7 +28,7 @@ struct linux_dev_v0_funcs { /* V2 and later prom device operations. */ struct linux_dev_v2_funcs { - int (*v2_inst2pkg)(int d); /* Convert ihandle to phandle */ + phandle (*v2_inst2pkg)(int d); /* Convert ihandle to phandle */ char * (*v2_dumb_mem_alloc)(char *va, unsigned sz); void (*v2_dumb_mem_free)(char *va, unsigned sz); @@ -168,12 +170,12 @@ struct linux_romvec { /* Routines for traversing the prom device tree. */ struct linux_nodeops { - int (*no_nextnode)(int node); - int (*no_child)(int node); - int (*no_proplen)(int node, const char *name); - int (*no_getprop)(int node, const char *name, char *val); - int (*no_setprop)(int node, const char *name, char *val, int len); - char * (*no_nextprop)(int node, char *name); + phandle (*no_nextnode)(phandle node); + phandle (*no_child)(phandle node); + int (*no_proplen)(phandle node, const char *name); + int (*no_getprop)(phandle node, const char *name, char *val); + int (*no_setprop)(phandle node, const char *name, char *val, int len); + char * (*no_nextprop)(phandle node, char *name); }; /* More fun PROM structures for device probing. */ diff --git a/arch/sparc/include/asm/oplib_32.h b/arch/sparc/include/asm/oplib_32.h index 33e31ce..51296a6 100644 --- a/arch/sparc/include/asm/oplib_32.h +++ b/arch/sparc/include/asm/oplib_32.h @@ -30,7 +30,7 @@ extern unsigned int prom_rev, prom_prev; /* Root node of the prom device tree, this stays constant after * initialization is complete. */ -extern int prom_root_node; +extern phandle prom_root_node; /* Pointer to prom structure containing the device tree traversal * and usage utility functions. Only prom-lib should use these, @@ -178,68 +178,68 @@ extern void prom_putsegment(int context, unsigned long virt_addr, /* PROM device tree traversal functions... */ /* Get the child node of the given node, or zero if no child exists. */ -extern int prom_getchild(int parent_node); +extern phandle prom_getchild(phandle parent_node); /* Get the next sibling node of the given node, or zero if no further * siblings exist. */ -extern int prom_getsibling(int node); +extern phandle prom_getsibling(phandle node); /* Get the length, at the passed node, of the given property type. * Returns -1 on error (ie. no such property at this node). */ -extern int prom_getproplen(int thisnode, const char *property); +extern int prom_getproplen(phandle thisnode, const char *property); /* Fetch the requested property using the given buffer. Returns * the number of bytes the prom put into your buffer or -1 on error. */ -extern int __must_check prom_getproperty(int thisnode, const char *property, +extern int __must_check prom_getproperty(phandle thisnode, const char *property, char *prop_buffer, int propbuf_size); /* Acquire an integer property. */ -extern int prom_getint(int node, char *property); +extern int prom_getint(phandle node, char *property); /* Acquire an integer property, with a default value. */ -extern int prom_getintdefault(int node, char *property, int defval); +extern int prom_getintdefault(phandle node, char *property, int defval); /* Acquire a boolean property, 0=FALSE 1=TRUE. */ -extern int prom_getbool(int node, char *prop); +extern int prom_getbool(phandle node, char *prop); /* Acquire a string property, null string on error. */ -extern void prom_getstring(int node, char *prop, char *buf, int bufsize); +extern void prom_getstring(phandle node, char *prop, char *buf, int bufsize); /* Does the passed node have the given "name"? YES=1 NO=0 */ -extern int prom_nodematch(int thisnode, char *name); +extern int prom_nodematch(phandle thisnode, char *name); /* Search all siblings starting at the passed node for "name" matching * the given string. Returns the node on success, zero on failure. */ -extern int prom_searchsiblings(int node_start, char *name); +extern phandle prom_searchsiblings(phandle node_start, char *name); /* Return the first property type, as a string, for the given node. * Returns a null string on error. */ -extern char *prom_firstprop(int node, char *buffer); +extern char *prom_firstprop(phandle node, char *buffer); /* Returns the next property after the passed property for the given * node. Returns null string on failure. */ -extern char *prom_nextprop(int node, char *prev_property, char *buffer); +extern char *prom_nextprop(phandle node, char *prev_property, char *buffer); /* Returns phandle of the path specified */ -extern int prom_finddevice(char *name); +extern phandle prom_finddevice(char *name); /* Returns 1 if the specified node has given property. */ -extern int prom_node_has_property(int node, char *property); +extern int prom_node_has_property(phandle node, char *property); /* Set the indicated property at the given node with the passed value. * Returns the number of bytes of your value that the prom took. */ -extern int prom_setprop(int node, const char *prop_name, char *prop_value, +extern int prom_setprop(phandle node, const char *prop_name, char *prop_value, int value_size); -extern int prom_pathtoinode(char *path); -extern int prom_inst2pkg(int); +extern phandle prom_pathtoinode(char *path); +extern phandle prom_inst2pkg(int); /* Dorking with Bus ranges... */ @@ -247,13 +247,13 @@ extern int prom_inst2pkg(int); extern void prom_apply_obio_ranges(struct linux_prom_registers *obioregs, int nregs); /* Apply ranges of any prom node (and optionally parent node as well) to registers. */ -extern void prom_apply_generic_ranges(int node, int parent, +extern void prom_apply_generic_ranges(phandle node, phandle parent, struct linux_prom_registers *sbusregs, int nregs); /* CPU probing helpers. */ -int cpu_find_by_instance(int instance, int *prom_node, int *mid); -int cpu_find_by_mid(int mid, int *prom_node); -int cpu_get_hwmid(int prom_node); +int cpu_find_by_instance(int instance, phandle *prom_node, int *mid); +int cpu_find_by_mid(int mid, phandle *prom_node); +int cpu_get_hwmid(phandle prom_node); extern spinlock_t prom_lock; diff --git a/arch/sparc/include/asm/oplib_64.h b/arch/sparc/include/asm/oplib_64.h index 3e0b2d6..c9cc078 100644 --- a/arch/sparc/include/asm/oplib_64.h +++ b/arch/sparc/include/asm/oplib_64.h @@ -16,7 +16,7 @@ extern char prom_version[]; /* Root node of the prom device tree, this stays constant after * initialization is complete. */ -extern int prom_root_node; +extern phandle prom_root_node; /* PROM stdin and stdout */ extern int prom_stdin, prom_stdout; @@ -24,7 +24,7 @@ extern int prom_stdin, prom_stdout; /* /chosen node of the prom device tree, this stays constant after * initialization is complete. */ -extern int prom_chosen_node; +extern phandle prom_chosen_node; /* Helper values and strings in arch/sparc64/kernel/head.S */ extern const char prom_peer_name[]; @@ -218,68 +218,69 @@ extern void prom_unmap(unsigned long size, unsigned long vaddr); /* PROM device tree traversal functions... */ /* Get the child node of the given node, or zero if no child exists. */ -extern int prom_getchild(int parent_node); +extern phandle prom_getchild(phandle parent_node); /* Get the next sibling node of the given node, or zero if no further * siblings exist. */ -extern int prom_getsibling(int node); +extern phandle prom_getsibling(phandle node); /* Get the length, at the passed node, of the given property type. * Returns -1 on error (ie. no such property at this node). */ -extern int prom_getproplen(int thisnode, const char *property); +extern int prom_getproplen(phandle thisnode, const char *property); /* Fetch the requested property using the given buffer. Returns * the number of bytes the prom put into your buffer or -1 on error. */ -extern int prom_getproperty(int thisnode, const char *property, +extern int prom_getproperty(phandle thisnode, const char *property, char *prop_buffer, int propbuf_size); /* Acquire an integer property. */ -extern int prom_getint(int node, const char *property); +extern int prom_getint(phandle node, const char *property); /* Acquire an integer property, with a default value. */ -extern int prom_getintdefault(int node, const char *property, int defval); +extern int prom_getintdefault(phandle node, const char *property, int defval); /* Acquire a boolean property, 0=FALSE 1=TRUE. */ -extern int prom_getbool(int node, const char *prop); +extern int prom_getbool(phandle node, const char *prop); /* Acquire a string property, null string on error. */ -extern void prom_getstring(int node, const char *prop, char *buf, int bufsize); +extern void prom_getstring(phandle node, const char *prop, char *buf, + int bufsize); /* Does the passed node have the given "name"? YES=1 NO=0 */ -extern int prom_nodematch(int thisnode, const char *name); +extern int prom_nodematch(phandle thisnode, const char *name); /* Search all siblings starting at the passed node for "name" matching * the given string. Returns the node on success, zero on failure. */ -extern int prom_searchsiblings(int node_start, const char *name); +extern phandle prom_searchsiblings(phandle node_start, const char *name); /* Return the first property type, as a string, for the given node. * Returns a null string on error. Buffer should be at least 32B long. */ -extern char *prom_firstprop(int node, char *buffer); +extern char *prom_firstprop(phandle node, char *buffer); /* Returns the next property after the passed property for the given * node. Returns null string on failure. Buffer should be at least 32B long. */ -extern char *prom_nextprop(int node, const char *prev_property, char *buffer); +extern char *prom_nextprop(phandle node, const char *prev_property, char *buf); /* Returns 1 if the specified node has given property. */ -extern int prom_node_has_property(int node, const char *property); +extern int prom_node_has_property(phandle node, const char *property); /* Returns phandle of the path specified */ -extern int prom_finddevice(const char *name); +extern phandle prom_finddevice(const char *name); /* Set the indicated property at the given node with the passed value. * Returns the number of bytes of your value that the prom took. */ -extern int prom_setprop(int node, const char *prop_name, char *prop_value, +extern int prom_setprop(phandle node, const char *prop_name, char *prop_value, int value_size); -extern int prom_pathtoinode(const char *path); -extern int prom_inst2pkg(int); +extern phandle prom_pathtoinode(const char *path); +extern phandle prom_inst2pkg(int); extern int prom_service_exists(const char *service_name); extern void prom_sun4v_guest_soft_state(void); diff --git a/arch/sparc/kernel/auxio_32.c b/arch/sparc/kernel/auxio_32.c index ee8d214..35f4883 100644 --- a/arch/sparc/kernel/auxio_32.c +++ b/arch/sparc/kernel/auxio_32.c @@ -23,7 +23,7 @@ static DEFINE_SPINLOCK(auxio_lock); void __init auxio_probe(void) { - int node, auxio_nd; + phandle node, auxio_nd; struct linux_prom_registers auxregs[1]; struct resource r; @@ -113,7 +113,7 @@ volatile unsigned char * auxio_power_register = NULL; void __init auxio_power_probe(void) { struct linux_prom_registers regs; - int node; + phandle node; struct resource r; /* Attempt to find the sun4m power control node. */ diff --git a/arch/sparc/kernel/btext.c b/arch/sparc/kernel/btext.c index 8cc2d56..89aa4eb 100644 --- a/arch/sparc/kernel/btext.c +++ b/arch/sparc/kernel/btext.c @@ -40,7 +40,7 @@ static unsigned char *dispDeviceBase __force_data; static unsigned char vga_font[cmapsz]; -static int __init btext_initialize(unsigned int node) +static int __init btext_initialize(phandle node) { unsigned int width, height, depth, pitch; unsigned long address = 0; @@ -309,7 +309,7 @@ static struct console btext_console = { int __init btext_find_display(void) { - unsigned int node; + phandle node; char type[32]; int ret; diff --git a/arch/sparc/kernel/devices.c b/arch/sparc/kernel/devices.c index 62dc7a0..d2eddd6 100644 --- a/arch/sparc/kernel/devices.c +++ b/arch/sparc/kernel/devices.c @@ -31,9 +31,9 @@ static char *cpu_mid_prop(void) return "mid"; } -static int check_cpu_node(int nd, int *cur_inst, - int (*compare)(int, int, void *), void *compare_arg, - int *prom_node, int *mid) +static int check_cpu_node(phandle nd, int *cur_inst, + int (*compare)(phandle, int, void *), void *compare_arg, + phandle *prom_node, int *mid) { if (!compare(nd, *cur_inst, compare_arg)) { if (prom_node) @@ -51,8 +51,8 @@ static int check_cpu_node(int nd, int *cur_inst, return -ENODEV; } -static int __cpu_find_by(int (*compare)(int, int, void *), void *compare_arg, - int *prom_node, int *mid) +static int __cpu_find_by(int (*compare)(phandle, int, void *), + void *compare_arg, phandle *prom_node, int *mid) { struct device_node *dp; int cur_inst; @@ -71,7 +71,7 @@ static int __cpu_find_by(int (*compare)(int, int, void *), void *compare_arg, return -ENODEV; } -static int cpu_instance_compare(int nd, int instance, void *_arg) +static int cpu_instance_compare(phandle nd, int instance, void *_arg) { int desired_instance = (int) _arg; @@ -80,13 +80,13 @@ static int cpu_instance_compare(int nd, int instance, void *_arg) return -ENODEV; } -int cpu_find_by_instance(int instance, int *prom_node, int *mid) +int cpu_find_by_instance(int instance, phandle *prom_node, int *mid) { return __cpu_find_by(cpu_instance_compare, (void *)instance, prom_node, mid); } -static int cpu_mid_compare(int nd, int instance, void *_arg) +static int cpu_mid_compare(phandle nd, int instance, void *_arg) { int desired_mid = (int) _arg; int this_mid; @@ -98,7 +98,7 @@ static int cpu_mid_compare(int nd, int instance, void *_arg) return -ENODEV; } -int cpu_find_by_mid(int mid, int *prom_node) +int cpu_find_by_mid(int mid, phandle *prom_node) { return __cpu_find_by(cpu_mid_compare, (void *)mid, prom_node, NULL); @@ -108,7 +108,7 @@ int cpu_find_by_mid(int mid, int *prom_node) * address (0-3). This gives us the true hardware mid, which might have * some other bits set. On 4d hardware and software mids are the same. */ -int cpu_get_hwmid(int prom_node) +int cpu_get_hwmid(phandle prom_node) { return prom_getintdefault(prom_node, cpu_mid_prop(), -ENODEV); } @@ -119,7 +119,8 @@ void __init device_scan(void) #ifndef CONFIG_SMP { - int err, cpu_node; + phandle cpu_node; + int err; err = cpu_find_by_instance(0, &cpu_node, NULL); if (err) { /* Probably a sun4e, Sun is trying to trick us ;-) */ diff --git a/arch/sparc/kernel/pcic.c b/arch/sparc/kernel/pcic.c index d36a8d3..aeaa09a 100644 --- a/arch/sparc/kernel/pcic.c +++ b/arch/sparc/kernel/pcic.c @@ -284,7 +284,7 @@ int __init pcic_probe(void) struct linux_prom_registers regs[PROMREG_MAX]; struct linux_pbm_info* pbm; char namebuf[64]; - int node; + phandle node; int err; if (pcic0_up) { @@ -440,7 +440,7 @@ static int __devinit pdev_to_pnode(struct linux_pbm_info *pbm, { struct linux_prom_pci_registers regs[PROMREG_MAX]; int err; - int node = prom_getchild(pbm->prom_node); + phandle node = prom_getchild(pbm->prom_node); while(node) { err = prom_getproperty(node, "reg", diff --git a/arch/sparc/kernel/setup_64.c b/arch/sparc/kernel/setup_64.c index 5f72de6..29bafe0 100644 --- a/arch/sparc/kernel/setup_64.c +++ b/arch/sparc/kernel/setup_64.c @@ -315,7 +315,7 @@ void __init setup_arch(char **cmdline_p) #ifdef CONFIG_IP_PNP if (!ic_set_manually) { - int chosen = prom_finddevice ("/chosen"); + phandle chosen = prom_finddevice("/chosen"); u32 cl, sv, gw; cl = prom_getintdefault (chosen, "client-ip", 0); diff --git a/arch/sparc/kernel/starfire.c b/arch/sparc/kernel/starfire.c index 060d0f3..a4446c0 100644 --- a/arch/sparc/kernel/starfire.c +++ b/arch/sparc/kernel/starfire.c @@ -23,7 +23,7 @@ int this_is_starfire = 0; void check_if_starfire(void) { - int ssnode = prom_finddevice("/ssp-serial"); + phandle ssnode = prom_finddevice("/ssp-serial"); if (ssnode != 0 && ssnode != -1) this_is_starfire = 1; } diff --git a/arch/sparc/kernel/tadpole.c b/arch/sparc/kernel/tadpole.c index f476a5f..9aba8bd 100644 --- a/arch/sparc/kernel/tadpole.c +++ b/arch/sparc/kernel/tadpole.c @@ -100,7 +100,7 @@ static void swift_clockstop(void) void __init clock_stop_probe(void) { - unsigned int node, clk_nd; + phandle node, clk_nd; char name[20]; prom_getstring(prom_root_node, "name", name, sizeof(name)); diff --git a/arch/sparc/mm/init_64.c b/arch/sparc/mm/init_64.c index f043451..9b020d6 100644 --- a/arch/sparc/mm/init_64.c +++ b/arch/sparc/mm/init_64.c @@ -88,7 +88,7 @@ static void __init read_obp_memory(const char *property, struct linux_prom64_registers *regs, int *num_ents) { - int node = prom_finddevice("/memory"); + phandle node = prom_finddevice("/memory"); int prop_size = prom_getproplen(node, property); int ents, ret, i; diff --git a/arch/sparc/mm/srmmu.c b/arch/sparc/mm/srmmu.c index b0b43aa..92319aa 100644 --- a/arch/sparc/mm/srmmu.c +++ b/arch/sparc/mm/srmmu.c @@ -1262,7 +1262,8 @@ extern unsigned long bootmem_init(unsigned long *pages_avail); void __init srmmu_paging_init(void) { - int i, cpunode; + int i; + phandle cpunode; char node_str[128]; pgd_t *pgd; pmd_t *pmd; @@ -1398,7 +1399,8 @@ static void __init srmmu_is_bad(void) static void __init init_vac_layout(void) { - int nd, cache_lines; + phandle nd; + int cache_lines; char node_str[128]; #ifdef CONFIG_SMP int cpu = 0; @@ -2082,7 +2084,7 @@ static void __init get_srmmu_type(void) /* Next check for Fujitsu Swift. */ if(psr_typ == 0 && psr_vers == 4) { - int cpunode; + phandle cpunode; char node_str[128]; /* Look if it is not a TurboSparc emulating Swift... */ diff --git a/arch/sparc/mm/sun4c.c b/arch/sparc/mm/sun4c.c index 4289f90..ddd0d86 100644 --- a/arch/sparc/mm/sun4c.c +++ b/arch/sparc/mm/sun4c.c @@ -420,7 +420,7 @@ volatile unsigned long __iomem *sun4c_memerr_reg = NULL; void __init sun4c_probe_memerr_reg(void) { - int node; + phandle node; struct linux_prom_registers regs[1]; node = prom_getchild(prom_root_node); diff --git a/arch/sparc/prom/init_32.c b/arch/sparc/prom/init_32.c index ccb36c7..d342dba 100644 --- a/arch/sparc/prom/init_32.c +++ b/arch/sparc/prom/init_32.c @@ -20,7 +20,7 @@ enum prom_major_version prom_vers; unsigned int prom_rev, prom_prev; /* The root node of the prom device tree. */ -int prom_root_node; +phandle prom_root_node; EXPORT_SYMBOL(prom_root_node); /* Pointer to the device tree operations structure. */ diff --git a/arch/sparc/prom/init_64.c b/arch/sparc/prom/init_64.c index 7b00f89..3ff911e 100644 --- a/arch/sparc/prom/init_64.c +++ b/arch/sparc/prom/init_64.c @@ -19,7 +19,7 @@ char prom_version[80]; /* The root node of the prom device tree. */ int prom_stdin, prom_stdout; -int prom_chosen_node; +phandle prom_chosen_node; /* You must call prom_init() before you attempt to use any of the * routines in the prom library. It returns 0 on success, 1 on @@ -30,7 +30,7 @@ extern void prom_cif_init(void *, void *); void __init prom_init(void *cif_handler, void *cif_stack) { - int node; + phandle node; prom_cif_init(cif_handler, cif_stack); diff --git a/arch/sparc/prom/memory.c b/arch/sparc/prom/memory.c index fac7899..3f263a6 100644 --- a/arch/sparc/prom/memory.c +++ b/arch/sparc/prom/memory.c @@ -31,7 +31,8 @@ static int __init prom_meminit_v0(void) static int __init prom_meminit_v2(void) { struct linux_prom_registers reg[64]; - int node, size, num_ents, i; + phandle node; + int size, num_ents, i; node = prom_searchsiblings(prom_getchild(prom_root_node), "memory"); size = prom_getproperty(node, "available", (char *) reg, sizeof(reg)); diff --git a/arch/sparc/prom/misc_64.c b/arch/sparc/prom/misc_64.c index 6cb1581..d24bc44 100644 --- a/arch/sparc/prom/misc_64.c +++ b/arch/sparc/prom/misc_64.c @@ -183,7 +183,8 @@ unsigned char prom_get_idprom(char *idbuf, int num_bytes) int prom_get_mmu_ihandle(void) { - int node, ret; + phandle node; + int ret; if (prom_mmu_ihandle_cache != 0) return prom_mmu_ihandle_cache; @@ -201,7 +202,8 @@ int prom_get_mmu_ihandle(void) static int prom_get_memory_ihandle(void) { static int memory_ihandle_cache; - int node, ret; + phandle node; + int ret; if (memory_ihandle_cache != 0) return memory_ihandle_cache; diff --git a/arch/sparc/prom/ranges.c b/arch/sparc/prom/ranges.c index aeff43e..541fc82 100644 --- a/arch/sparc/prom/ranges.c +++ b/arch/sparc/prom/ranges.c @@ -68,7 +68,7 @@ EXPORT_SYMBOL(prom_apply_obio_ranges); void __init prom_ranges_init(void) { - int node, obio_node; + phandle node, obio_node; int success; num_obio_ranges = 0; @@ -89,8 +89,8 @@ void __init prom_ranges_init(void) prom_printf("PROMLIB: obio_ranges %d\n", num_obio_ranges); } -void -prom_apply_generic_ranges (int node, int parent, struct linux_prom_registers *regs, int nregs) +void prom_apply_generic_ranges(phandle node, phandle parent, + struct linux_prom_registers *regs, int nregs) { int success; int num_ranges; diff --git a/arch/sparc/prom/tree_32.c b/arch/sparc/prom/tree_32.c index b21592f..63e08e1 100644 --- a/arch/sparc/prom/tree_32.c +++ b/arch/sparc/prom/tree_32.c @@ -20,10 +20,10 @@ extern void restore_current(void); static char promlib_buf[128]; /* Internal version of prom_getchild that does not alter return values. */ -int __prom_getchild(int node) +phandle __prom_getchild(phandle node) { unsigned long flags; - int cnode; + phandle cnode; spin_lock_irqsave(&prom_lock, flags); cnode = prom_nodeops->no_child(node); @@ -36,9 +36,9 @@ int __prom_getchild(int node) /* Return the child of node 'node' or zero if no this node has no * direct descendent. */ -int prom_getchild(int node) +phandle prom_getchild(phandle node) { - int cnode; + phandle cnode; if (node == -1) return 0; @@ -52,10 +52,10 @@ int prom_getchild(int node) EXPORT_SYMBOL(prom_getchild); /* Internal version of prom_getsibling that does not alter return values. */ -int __prom_getsibling(int node) +phandle __prom_getsibling(phandle node) { unsigned long flags; - int cnode; + phandle cnode; spin_lock_irqsave(&prom_lock, flags); cnode = prom_nodeops->no_nextnode(node); @@ -68,9 +68,9 @@ int __prom_getsibling(int node) /* Return the next sibling of node 'node' or zero if no more siblings * at this level of depth in the tree. */ -int prom_getsibling(int node) +phandle prom_getsibling(phandle node) { - int sibnode; + phandle sibnode; if (node == -1) return 0; @@ -86,7 +86,7 @@ EXPORT_SYMBOL(prom_getsibling); /* Return the length in bytes of property 'prop' at node 'node'. * Return -1 on error. */ -int prom_getproplen(int node, const char *prop) +int prom_getproplen(phandle node, const char *prop) { int ret; unsigned long flags; @@ -106,7 +106,7 @@ EXPORT_SYMBOL(prom_getproplen); * 'buffer' which has a size of 'bufsize'. If the acquisition * was successful the length will be returned, else -1 is returned. */ -int prom_getproperty(int node, const char *prop, char *buffer, int bufsize) +int prom_getproperty(phandle node, const char *prop, char *buffer, int bufsize) { int plen, ret; unsigned long flags; @@ -126,7 +126,7 @@ EXPORT_SYMBOL(prom_getproperty); /* Acquire an integer property and return its value. Returns -1 * on failure. */ -int prom_getint(int node, char *prop) +int prom_getint(phandle node, char *prop) { static int intprop; @@ -140,7 +140,7 @@ EXPORT_SYMBOL(prom_getint); /* Acquire an integer property, upon error return the passed default * integer. */ -int prom_getintdefault(int node, char *property, int deflt) +int prom_getintdefault(phandle node, char *property, int deflt) { int retval; @@ -152,7 +152,7 @@ int prom_getintdefault(int node, char *property, int deflt) EXPORT_SYMBOL(prom_getintdefault); /* Acquire a boolean property, 1=TRUE 0=FALSE. */ -int prom_getbool(int node, char *prop) +int prom_getbool(phandle node, char *prop) { int retval; @@ -166,7 +166,7 @@ EXPORT_SYMBOL(prom_getbool); * string on error. The char pointer is the user supplied string * buffer. */ -void prom_getstring(int node, char *prop, char *user_buf, int ubuf_size) +void prom_getstring(phandle node, char *prop, char *user_buf, int ubuf_size) { int len; @@ -180,7 +180,7 @@ EXPORT_SYMBOL(prom_getstring); /* Does the device at node 'node' have name 'name'? * YES = 1 NO = 0 */ -int prom_nodematch(int node, char *name) +int prom_nodematch(phandle node, char *name) { int error; @@ -194,10 +194,11 @@ int prom_nodematch(int node, char *name) /* Search siblings at 'node_start' for a node with name * 'nodename'. Return node if successful, zero if not. */ -int prom_searchsiblings(int node_start, char *nodename) +phandle prom_searchsiblings(phandle node_start, char *nodename) { - int thisnode, error; + phandle thisnode; + int error; for(thisnode = node_start; thisnode; thisnode=prom_getsibling(thisnode)) { @@ -213,7 +214,7 @@ int prom_searchsiblings(int node_start, char *nodename) EXPORT_SYMBOL(prom_searchsiblings); /* Interal version of nextprop that does not alter return values. */ -char * __prom_nextprop(int node, char * oprop) +char *__prom_nextprop(phandle node, char * oprop) { unsigned long flags; char *prop; @@ -228,7 +229,7 @@ char * __prom_nextprop(int node, char * oprop) /* Return the first property name for node 'node'. */ /* buffer is unused argument, but as v9 uses it, we need to have the same interface */ -char * prom_firstprop(int node, char *bufer) +char *prom_firstprop(phandle node, char *bufer) { if (node == 0 || node == -1) return ""; @@ -241,7 +242,7 @@ EXPORT_SYMBOL(prom_firstprop); * at node 'node' . Returns empty string if no more * property types for this node. */ -char * prom_nextprop(int node, char *oprop, char *buffer) +char *prom_nextprop(phandle node, char *oprop, char *buffer) { if (node == 0 || node == -1) return ""; @@ -250,11 +251,11 @@ char * prom_nextprop(int node, char *oprop, char *buffer) } EXPORT_SYMBOL(prom_nextprop); -int prom_finddevice(char *name) +phandle prom_finddevice(char *name) { char nbuf[128]; char *s = name, *d; - int node = prom_root_node, node2; + phandle node = prom_root_node, node2; unsigned int which_io, phys_addr; struct linux_prom_registers reg[PROMREG_MAX]; @@ -298,7 +299,7 @@ int prom_finddevice(char *name) } EXPORT_SYMBOL(prom_finddevice); -int prom_node_has_property(int node, char *prop) +int prom_node_has_property(phandle node, char *prop) { char *current_property = ""; @@ -314,7 +315,7 @@ EXPORT_SYMBOL(prom_node_has_property); /* Set property 'pname' at node 'node' to value 'value' which has a length * of 'size' bytes. Return the number of bytes the prom accepted. */ -int prom_setprop(int node, const char *pname, char *value, int size) +int prom_setprop(phandle node, const char *pname, char *value, int size) { unsigned long flags; int ret; @@ -329,9 +330,9 @@ int prom_setprop(int node, const char *pname, char *value, int size) } EXPORT_SYMBOL(prom_setprop); -int prom_inst2pkg(int inst) +phandle prom_inst2pkg(int inst) { - int node; + phandle node; unsigned long flags; spin_lock_irqsave(&prom_lock, flags); @@ -345,9 +346,10 @@ int prom_inst2pkg(int inst) /* Return 'node' assigned to a particular prom 'path' * FIXME: Should work for v0 as well */ -int prom_pathtoinode(char *path) +phandle prom_pathtoinode(char *path) { - int node, inst; + phandle node; + int inst; inst = prom_devopen (path); if (inst == -1) return 0; diff --git a/arch/sparc/prom/tree_64.c b/arch/sparc/prom/tree_64.c index 9d3f913..691be68 100644 --- a/arch/sparc/prom/tree_64.c +++ b/arch/sparc/prom/tree_64.c @@ -16,7 +16,7 @@ #include #include -static int prom_node_to_node(const char *type, int node) +static phandle prom_node_to_node(const char *type, phandle node) { unsigned long args[5]; @@ -28,20 +28,20 @@ static int prom_node_to_node(const char *type, int node) p1275_cmd_direct(args); - return (int) args[4]; + return (phandle) args[4]; } /* Return the child of node 'node' or zero if no this node has no * direct descendent. */ -inline int __prom_getchild(int node) +inline phandle __prom_getchild(phandle node) { return prom_node_to_node("child", node); } -inline int prom_getchild(int node) +inline phandle prom_getchild(phandle node) { - int cnode; + phandle cnode; if (node == -1) return 0; @@ -52,9 +52,9 @@ inline int prom_getchild(int node) } EXPORT_SYMBOL(prom_getchild); -inline int prom_getparent(int node) +inline phandle prom_getparent(phandle node) { - int cnode; + phandle cnode; if (node == -1) return 0; @@ -67,14 +67,14 @@ inline int prom_getparent(int node) /* Return the next sibling of node 'node' or zero if no more siblings * at this level of depth in the tree. */ -inline int __prom_getsibling(int node) +inline phandle __prom_getsibling(phandle node) { return prom_node_to_node(prom_peer_name, node); } -inline int prom_getsibling(int node) +inline phandle prom_getsibling(phandle node) { - int sibnode; + phandle sibnode; if (node == -1) return 0; @@ -89,7 +89,7 @@ EXPORT_SYMBOL(prom_getsibling); /* Return the length in bytes of property 'prop' at node 'node'. * Return -1 on error. */ -inline int prom_getproplen(int node, const char *prop) +inline int prom_getproplen(phandle node, const char *prop) { unsigned long args[6]; @@ -113,7 +113,7 @@ EXPORT_SYMBOL(prom_getproplen); * 'buffer' which has a size of 'bufsize'. If the acquisition * was successful the length will be returned, else -1 is returned. */ -inline int prom_getproperty(int node, const char *prop, +inline int prom_getproperty(phandle node, const char *prop, char *buffer, int bufsize) { unsigned long args[8]; @@ -141,7 +141,7 @@ EXPORT_SYMBOL(prom_getproperty); /* Acquire an integer property and return its value. Returns -1 * on failure. */ -inline int prom_getint(int node, const char *prop) +inline int prom_getint(phandle node, const char *prop) { int intprop; @@ -156,7 +156,7 @@ EXPORT_SYMBOL(prom_getint); * integer. */ -int prom_getintdefault(int node, const char *property, int deflt) +int prom_getintdefault(phandle node, const char *property, int deflt) { int retval; @@ -169,7 +169,7 @@ int prom_getintdefault(int node, const char *property, int deflt) EXPORT_SYMBOL(prom_getintdefault); /* Acquire a boolean property, 1=TRUE 0=FALSE. */ -int prom_getbool(int node, const char *prop) +int prom_getbool(phandle node, const char *prop) { int retval; @@ -184,7 +184,8 @@ EXPORT_SYMBOL(prom_getbool); * string on error. The char pointer is the user supplied string * buffer. */ -void prom_getstring(int node, const char *prop, char *user_buf, int ubuf_size) +void prom_getstring(phandle node, const char *prop, char *user_buf, + int ubuf_size) { int len; @@ -198,7 +199,7 @@ EXPORT_SYMBOL(prom_getstring); /* Does the device at node 'node' have name 'name'? * YES = 1 NO = 0 */ -int prom_nodematch(int node, const char *name) +int prom_nodematch(phandle node, const char *name) { char namebuf[128]; prom_getproperty(node, "name", namebuf, sizeof(namebuf)); @@ -210,10 +211,10 @@ int prom_nodematch(int node, const char *name) /* Search siblings at 'node_start' for a node with name * 'nodename'. Return node if successful, zero if not. */ -int prom_searchsiblings(int node_start, const char *nodename) +phandle prom_searchsiblings(phandle node_start, const char *nodename) { - - int thisnode, error; + phandle thisnode; + int error; char promlib_buf[128]; for(thisnode = node_start; thisnode; @@ -234,7 +235,7 @@ static const char *prom_nextprop_name = "nextprop"; /* Return the first property type for node 'node'. * buffer should be at least 32B in length */ -inline char *prom_firstprop(int node, char *buffer) +inline char *prom_firstprop(phandle node, char *buffer) { unsigned long args[7]; @@ -260,7 +261,7 @@ EXPORT_SYMBOL(prom_firstprop); * at node 'node' . Returns NULL string if no more * property types for this node. */ -inline char *prom_nextprop(int node, const char *oprop, char *buffer) +inline char *prom_nextprop(phandle node, const char *oprop, char *buffer) { unsigned long args[7]; char buf[32]; @@ -288,8 +289,7 @@ inline char *prom_nextprop(int node, const char *oprop, char *buffer) } EXPORT_SYMBOL(prom_nextprop); -int -prom_finddevice(const char *name) +phandle prom_finddevice(const char *name) { unsigned long args[5]; @@ -307,7 +307,7 @@ prom_finddevice(const char *name) } EXPORT_SYMBOL(prom_finddevice); -int prom_node_has_property(int node, const char *prop) +int prom_node_has_property(phandle node, const char *prop) { char buf [32]; @@ -325,7 +325,7 @@ EXPORT_SYMBOL(prom_node_has_property); * of 'size' bytes. Return the number of bytes the prom accepted. */ int -prom_setprop(int node, const char *pname, char *value, int size) +prom_setprop(phandle node, const char *pname, char *value, int size) { unsigned long args[8]; @@ -355,10 +355,10 @@ prom_setprop(int node, const char *pname, char *value, int size) } EXPORT_SYMBOL(prom_setprop); -inline int prom_inst2pkg(int inst) +inline phandle prom_inst2pkg(int inst) { unsigned long args[5]; - int node; + phandle node; args[0] = (unsigned long) "instance-to-package"; args[1] = 1; @@ -377,10 +377,10 @@ inline int prom_inst2pkg(int inst) /* Return 'node' assigned to a particular prom 'path' * FIXME: Should work for v0 as well */ -int -prom_pathtoinode(const char *path) +phandle prom_pathtoinode(const char *path) { - int node, inst; + phandle node; + int inst; inst = prom_devopen (path); if (inst == 0) -- cgit v1.1 From 9bdf6bab4ecfb6a8ca50c0c46f2365ef6c3e35b7 Mon Sep 17 00:00:00 2001 From: Andres Salomon Date: Mon, 30 Aug 2010 03:57:28 +0000 Subject: sparc: break out some PROM device-tree building code out into drivers/of Transitioning into making this useful for architectures other than sparc. This is a verbatim copy of all functions/variables that've been moved. Signed-off-by: Andres Salomon Acked-by: David S. Miller Signed-off-by: Grant Likely --- arch/sparc/kernel/prom_common.c | 190 +--------------------------------------- 1 file changed, 1 insertion(+), 189 deletions(-) (limited to 'arch') diff --git a/arch/sparc/kernel/prom_common.c b/arch/sparc/kernel/prom_common.c index 1f830da..7b454f6 100644 --- a/arch/sparc/kernel/prom_common.c +++ b/arch/sparc/kernel/prom_common.c @@ -26,8 +26,6 @@ #include "prom.h" -void (*prom_build_more)(struct device_node *dp, struct device_node ***nextp); - struct device_node *of_console_device; EXPORT_SYMBOL(of_console_device); @@ -119,192 +117,6 @@ int of_find_in_proplist(const char *list, const char *match, int len) } EXPORT_SYMBOL(of_find_in_proplist); -unsigned int prom_unique_id; - -static struct property * __init build_one_prop(phandle node, char *prev, - char *special_name, - void *special_val, - int special_len) -{ - static struct property *tmp = NULL; - struct property *p; - const char *name; - - if (tmp) { - p = tmp; - memset(p, 0, sizeof(*p) + 32); - tmp = NULL; - } else { - p = prom_early_alloc(sizeof(struct property) + 32); - p->unique_id = prom_unique_id++; - } - - p->name = (char *) (p + 1); - if (special_name) { - strcpy(p->name, special_name); - p->length = special_len; - p->value = prom_early_alloc(special_len); - memcpy(p->value, special_val, special_len); - } else { - if (prev == NULL) { - name = prom_firstprop(node, p->name); - } else { - name = prom_nextprop(node, prev, p->name); - } - - if (!name || strlen(name) == 0) { - tmp = p; - return NULL; - } -#ifdef CONFIG_SPARC32 - strcpy(p->name, name); -#endif - p->length = prom_getproplen(node, p->name); - if (p->length <= 0) { - p->length = 0; - } else { - int len; - - p->value = prom_early_alloc(p->length + 1); - len = prom_getproperty(node, p->name, p->value, - p->length); - if (len <= 0) - p->length = 0; - ((unsigned char *)p->value)[p->length] = '\0'; - } - } - return p; -} - -static struct property * __init build_prop_list(phandle node) -{ - struct property *head, *tail; - - head = tail = build_one_prop(node, NULL, - ".node", &node, sizeof(node)); - - tail->next = build_one_prop(node, NULL, NULL, NULL, 0); - tail = tail->next; - while(tail) { - tail->next = build_one_prop(node, tail->name, - NULL, NULL, 0); - tail = tail->next; - } - - return head; -} - -static char * __init get_one_property(phandle node, const char *name) -{ - char *buf = ""; - int len; - - len = prom_getproplen(node, name); - if (len > 0) { - buf = prom_early_alloc(len); - len = prom_getproperty(node, name, buf, len); - } - - return buf; -} - -static struct device_node * __init prom_create_node(phandle node, - struct device_node *parent) -{ - struct device_node *dp; - - if (!node) - return NULL; - - dp = prom_early_alloc(sizeof(*dp)); - dp->unique_id = prom_unique_id++; - dp->parent = parent; - - kref_init(&dp->kref); - - dp->name = get_one_property(node, "name"); - dp->type = get_one_property(node, "device_type"); - dp->phandle = node; - - dp->properties = build_prop_list(node); - - irq_trans_init(dp); - - return dp; -} - -char * __init build_full_name(struct device_node *dp) -{ - int len, ourlen, plen; - char *n; - - plen = strlen(dp->parent->full_name); - ourlen = strlen(dp->path_component_name); - len = ourlen + plen + 2; - - n = prom_early_alloc(len); - strcpy(n, dp->parent->full_name); - if (!of_node_is_root(dp->parent)) { - strcpy(n + plen, "/"); - plen++; - } - strcpy(n + plen, dp->path_component_name); - - return n; -} - -static struct device_node * __init prom_build_tree(struct device_node *parent, - phandle node, - struct device_node ***nextp) -{ - struct device_node *ret = NULL, *prev_sibling = NULL; - struct device_node *dp; - - while (1) { - dp = prom_create_node(node, parent); - if (!dp) - break; - - if (prev_sibling) - prev_sibling->sibling = dp; - - if (!ret) - ret = dp; - prev_sibling = dp; - - *(*nextp) = dp; - *nextp = &dp->allnext; - - dp->path_component_name = build_path_component(dp); - dp->full_name = build_full_name(dp); - - dp->child = prom_build_tree(dp, prom_getchild(node), nextp); - - if (prom_build_more) - prom_build_more(dp, nextp); - - node = prom_getsibling(node); - } - - return ret; -} - unsigned int prom_early_allocated __initdata; -void __init prom_build_devicetree(void) -{ - struct device_node **nextp; - - allnodes = prom_create_node(prom_root_node, NULL); - allnodes->path_component_name = ""; - allnodes->full_name = "/"; - - nextp = &allnodes->allnext; - allnodes->child = prom_build_tree(allnodes, - prom_getchild(allnodes->phandle), - &nextp); - of_console_init(); - - printk("PROM: Built device tree with %u bytes of memory.\n", - prom_early_allocated); -} +#include "../../../drivers/of/pdt.c" -- cgit v1.1 From 708ff2a0097b02d32d375b66996661f36cd4d6d1 Mon Sep 17 00:00:00 2001 From: Akinobu Mita Date: Wed, 29 Sep 2010 18:08:50 +0900 Subject: bitops: make asm-generic/bitops/find.h more generic asm-generic/bitops/find.h has the extern declarations of find_next_bit() and find_next_zero_bit() and the macro definitions of find_first_bit() and find_first_zero_bit(). It is only usable by the architectures which enables CONFIG_GENERIC_FIND_NEXT_BIT and disables CONFIG_GENERIC_FIND_FIRST_BIT. x86 and tile enable both CONFIG_GENERIC_FIND_NEXT_BIT and CONFIG_GENERIC_FIND_FIRST_BIT. These architectures cannot include asm-generic/bitops/find.h in their asm/bitops.h. So ifdefed extern declarations of find_first_bit and find_first_zero_bit() are put in linux/bitops.h. This makes asm-generic/bitops/find.h usable by these architectures and use it. Also this change is needed for the forthcoming duplicated extern declarations cleanup. Signed-off-by: Akinobu Mita Signed-off-by: Arnd Bergmann Cc: Thomas Gleixner Cc: Ingo Molnar Cc: "H. Peter Anvin" Cc: x86@kernel.org Cc: Chris Metcalf --- arch/tile/include/asm/bitops.h | 1 + arch/x86/include/asm/bitops.h | 2 ++ 2 files changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/tile/include/asm/bitops.h b/arch/tile/include/asm/bitops.h index 6832b4b..6d4f0ff 100644 --- a/arch/tile/include/asm/bitops.h +++ b/arch/tile/include/asm/bitops.h @@ -120,6 +120,7 @@ static inline unsigned long __arch_hweight64(__u64 w) #include #include +#include #include #include #include diff --git a/arch/x86/include/asm/bitops.h b/arch/x86/include/asm/bitops.h index bafd80d..903683b0 100644 --- a/arch/x86/include/asm/bitops.h +++ b/arch/x86/include/asm/bitops.h @@ -440,6 +440,8 @@ static inline int fls(int x) #ifdef __KERNEL__ +#include + #include #define ARCH_HAS_FAST_MULTIPLIER 1 -- cgit v1.1 From 3cfc535c5df8122af1258ae05aaf2770c033425d Mon Sep 17 00:00:00 2001 From: Andres Salomon Date: Sun, 10 Oct 2010 21:42:33 -0600 Subject: of/promtree: make drivers/of/pdt.c no longer sparc-only Clean up pdt.c: - make build dependent upon config OF_PROMTREE - #ifdef out the sparc-specific stuff - create pdt-specific header Signed-off-by: Andres Salomon Acked-by: David S. Miller Signed-off-by: Grant Likely --- arch/sparc/Kconfig | 1 + arch/sparc/include/asm/prom.h | 5 +++-- arch/sparc/kernel/prom.h | 6 ------ arch/sparc/kernel/prom_common.c | 10 +++++++++- 4 files changed, 13 insertions(+), 9 deletions(-) (limited to 'arch') diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig index 491e9d6..a06c959 100644 --- a/arch/sparc/Kconfig +++ b/arch/sparc/Kconfig @@ -19,6 +19,7 @@ config SPARC bool default y select OF + select OF_PROMTREE select HAVE_IDE select HAVE_OPROFILE select HAVE_ARCH_KGDB if !SMP || SPARC64 diff --git a/arch/sparc/include/asm/prom.h b/arch/sparc/include/asm/prom.h index 291f125..56bbaad 100644 --- a/arch/sparc/include/asm/prom.h +++ b/arch/sparc/include/asm/prom.h @@ -18,6 +18,7 @@ * 2 of the License, or (at your option) any later version. */ #include +#include #include #include #include @@ -67,8 +68,8 @@ extern struct device_node *of_console_device; extern char *of_console_path; extern char *of_console_options; -extern void (*prom_build_more)(struct device_node *dp, struct device_node ***nextp); -extern char *build_full_name(struct device_node *dp); +extern void irq_trans_init(struct device_node *dp); +extern char *build_path_component(struct device_node *dp); #endif /* __KERNEL__ */ #endif /* _SPARC_PROM_H */ diff --git a/arch/sparc/kernel/prom.h b/arch/sparc/kernel/prom.h index eeb04a7..cf5fe1c 100644 --- a/arch/sparc/kernel/prom.h +++ b/arch/sparc/kernel/prom.h @@ -4,12 +4,6 @@ #include #include -extern void * prom_early_alloc(unsigned long size); -extern void irq_trans_init(struct device_node *dp); - -extern unsigned int prom_unique_id; - -extern char *build_path_component(struct device_node *dp); extern void of_console_init(void); extern unsigned int prom_early_allocated; diff --git a/arch/sparc/kernel/prom_common.c b/arch/sparc/kernel/prom_common.c index 7b454f6..fe84d56 100644 --- a/arch/sparc/kernel/prom_common.c +++ b/arch/sparc/kernel/prom_common.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -119,4 +120,11 @@ EXPORT_SYMBOL(of_find_in_proplist); unsigned int prom_early_allocated __initdata; -#include "../../../drivers/of/pdt.c" +void __init prom_build_devicetree(void) +{ + of_pdt_build_devicetree(prom_root_node); + of_console_init(); + + pr_info("PROM: Built device tree with %u bytes of memory.\n", + prom_early_allocated); +} -- cgit v1.1 From 5a30d7bfcd33c03f1f67d3e1c317eb5d6a6bc811 Mon Sep 17 00:00:00 2001 From: Kulikov Vasiliy Date: Sun, 10 Oct 2010 17:28:27 +0000 Subject: sh: boards/mach-x3proto: gpio: fix error handling code Checks for (irq < 0) and (ilsel < 0) didn't make sense since they were unsigned. Made them signed. Signed-off-by: Vasiliy Kulikov Signed-off-by: Paul Mundt --- arch/sh/boards/mach-x3proto/gpio.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/sh/boards/mach-x3proto/gpio.c b/arch/sh/boards/mach-x3proto/gpio.c index 9fcd7ce..594adf7 100644 --- a/arch/sh/boards/mach-x3proto/gpio.c +++ b/arch/sh/boards/mach-x3proto/gpio.c @@ -79,7 +79,7 @@ struct gpio_chip x3proto_gpio_chip = { int __init x3proto_gpio_setup(void) { - unsigned int ilsel; + int ilsel; int ret, i; ilsel = ilsel_enable(ILSEL_KEY); @@ -92,7 +92,7 @@ int __init x3proto_gpio_setup(void) for (i = 0; i < NR_BASEBOARD_GPIOS; i++) { unsigned long flags; - unsigned int irq = create_irq(); + int irq = create_irq(); if (unlikely(irq < 0)) { ret = -EINVAL; -- cgit v1.1 From de65815860f187cb43551bc833bf9d72720faa01 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Fri, 8 Oct 2010 22:43:45 +0000 Subject: OMAP3: PM: fix scratchpad memory accesses for off-mode Commit 914bab936fe0388a529079679e2f137aa4ff548d (OMAP: mach-omap2: Fix incorrect assignment warnings) changed a pointer from 'u32 *' to 'void *' without also fixing up the pointer arithmetic. Fix the scratchpad offsets so they are byte offsets instead of word offsets and thus work correctly with a void pointer base. Special thanks to Jean Pihet for taking the time track down this problem and propose an initial solution. Tested with off-idle and off-suspend on 36xx/Zoom3 and 34xx/omap3evm. Cc: Manjunath Kondaiah G Reported-by: Jean Pihet Signed-off-by: Kevin Hilman Tested-by: Jean Pihet Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/pm34xx.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 8c8f1acd..75c0cd1 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -50,9 +50,9 @@ #include "control.h" /* Scratchpad offsets */ -#define OMAP343X_TABLE_ADDRESS_OFFSET 0x31 -#define OMAP343X_TABLE_VALUE_OFFSET 0x30 -#define OMAP343X_CONTROL_REG_VALUE_OFFSET 0x32 +#define OMAP343X_TABLE_ADDRESS_OFFSET 0xc4 +#define OMAP343X_TABLE_VALUE_OFFSET 0xc0 +#define OMAP343X_CONTROL_REG_VALUE_OFFSET 0xc8 struct power_state { struct powerdomain *pwrdm; -- cgit v1.1 From a1b04cc197e17c47b043051becb548dc8c60c886 Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Mon, 11 Oct 2010 11:05:18 +0000 Subject: omap: serial: Fix the boot-up crash/reboot without CONFIG_PM The omap2plus_defconfig doesn't boot up when built with CONFIG_PM disabled on the latest linux-omap master. Below are the observations 1. OMAP3 reboots in the middle of boot -------------------------------------------------- [ 0.000000] Calibrating delay loop... 494.72 BogoMIPS (lpj=1933312) [ 0.000000] pid_max: default: 32768 minimum: 301 [ 0.000000] Security Framework initialized [ 0.000000] Mount-cache hash table entries: 512 [ 0.000000] CPU: Testing write buffer coherency: ok [ 0.000000] Brought up 1 CPUs [ 0.000000] SMP: Total of 1 processors activated (494.72 BogoMIPS). [ 0.000000] regulator: core version 0.5 [ 0.000000] NET: Registered protocol family 16 U-Boot 1.1.4 (Feb 11 2009 - 16:10:23) OMAP3430-GP rev 2, CPU-OPP2 L3-165MHz TI 3430SDP 1.0 Version + mDDR (Boot NOR) DRAM: 128 MB Flash: 128 MB NAND:128 MiB -------------------------------------------------- 2. OMAP4 does a kernel PANIC ------------------------------------- [ 0.000000] Calibrating delay loop... 1195.29 BogoMIPS (lpj=4669440) [ 0.000000] pid_max: default: 32768 minimum: 301 [ 0.000000] Security Framework initialized [ 0.000000] Mount-cache hash table entries: 512 [ 0.000000] CPU: Testing write buffer coherency: ok [ 0.000000] L310 cache controller enabled [ 0.000000] l2x0: 16 ways, CACHE_ID 0x410000c2, AUX_CTRL 0x0e050000 [ 0.000000] CPU1: Booted secondary processor [ 0.000000] Brought up 2 CPUs [ 0.000000] SMP: Total of 2 processors activated (2395.78 BogoMIPS). [ 0.000000] regulator: core version 0.5 [ 0.000000] NET: Registered protocol family 16 [ 0.000000] mux: Could not set signal i2c2_scl.i2c2_scl [ 0.000000] mux: Could not set signal i2c2_sda.i2c2_sda [ 0.000000] mux: Could not set signal i2c3_scl.i2c3_scl [ 0.000000] mux: Could not set signal i2c3_sda.i2c3_sda [ 0.000000] mux: Could not set signal i2c4_scl.i2c4_scl [ 0.000000] mux: Could not set signal i2c4_sda.i2c4_sda ------------------------------------- This is happening because 'omap_serial_init()' is hanging in the boot. On OMAP3 the watchdog is generating reboot because devices_init doesn't happens where as on OMAP4 it just hangs without reboot. The uart clock is not getting enabled after omap_device_idle as part of omap_serial_init. The omap_device_idle(will disable the clock) then omap_uart_block_sleep() should enable clock back disabled during the boot up phase. But omap_uart_block_sleep() stuffed version is binded only under CONFIG_PM and other version is just empty. Hence it is not enabling clock back as expected This patch adds uart clock enable code to omap_uart_block_sleep() function built with CONFIG_PM disabled. Thanks to Charulatha and Govindraj for their help on this debug. Signed-off-by: Santosh Shilimkar Signed-off-by: Charulatha V Signed-off-by: Govindraj.R Acked-by: Kevin Hilman Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/serial.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index 338e46a..ba8a5cc 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -608,7 +608,11 @@ static DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, #define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr)) #else static inline void omap_uart_idle_init(struct omap_uart_state *uart) {} -static void omap_uart_block_sleep(struct omap_uart_state *uart) {} +static void omap_uart_block_sleep(struct omap_uart_state *uart) +{ + /* Needed to enable UART clocks when built without CONFIG_PM */ + omap_uart_enable_clocks(uart); +} #define DEV_CREATE_FILE(dev, attr) #endif /* CONFIG_PM */ -- cgit v1.1 From 3e57f1626b5febe5cc99aa6870377deef3ae03cc Mon Sep 17 00:00:00 2001 From: Jarkko Nikula Date: Mon, 11 Oct 2010 14:18:45 -0700 Subject: omap: dma: Fix buffering disable bit setting for omap24xx An errata workaround for omap24xx is not setting the buffering disable bit 25 what is the purpose but channel enable bit 7 instead. Background for this fix is the DMA stalling issue with ASoC omap-mcbsp driver. Peter Ujfalusi has found an issue in recording that the DMA stall could happen if there were a buffer overrun detected by ALSA and the DMA was stopped and restarted due that. This problem is known to occur on both OMAP2420 and OMAP3. It can recover on OMAP3 after dma free, dma request and reconfiguration cycle. However, on OMAP2420 it seems that only way to recover is a reset. Problem was not visible before the commit c12abc0. That commit changed that the McBSP transmitter/receiver is released from reset only when needed. That is, only enabled McBSP transmitter without transmission was able to prevent this DMA stall problem in receiving side and underlying problem did not show up until now. McBSP transmitter itself seems to no be reason since DMA stall does not recover by enabling the transmission after stall. Debugging showed that there were a DMA write active during DMA stop time and it never completed even when restarting the DMA. Experimenting showed that the DMA buffering disable bit could be used to avoid stalling when using source synchronized transfers. However that could have performance hit and OMAP3 TRM states that buffering disable is not allowed for destination synchronized transfers so subsequent patch will implement a method to complete DMA writes when stopping. This patch is based on assumtion that complete lock-up on OMAP2420 is different but related problem. I don't have access to OMAP2420 errata but I believe this old workaround here is put for a reason but unfortunately a wrong bit was typed and problem showed up only now. Signed-off-by: Jarkko Nikula Signed-off-by: Peter Ujfalusi Acked-by: Manjunath Kondaiah G Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/dma.c | 14 ++++++++++---- arch/arm/plat-omap/include/plat/dma.h | 1 + 2 files changed, 11 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index ec7eddf..420cef3 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -996,11 +996,17 @@ void omap_start_dma(int lch) l = dma_read(CCR(lch)); /* - * Errata: On ES2.0 BUFFERING disable must be set. - * This will always fail on ES1.0 + * Errata: Inter Frame DMA buffering issue (All OMAP2420 and + * OMAP2430ES1.0): DMA will wrongly buffer elements if packing and + * bursting is enabled. This might result in data gets stalled in + * FIFO at the end of the block. + * Workaround: DMA channels must have BUFFERING_DISABLED bit set to + * guarantee no data will stay in the DMA FIFO in case inter frame + * buffering occurs. */ - if (cpu_is_omap24xx()) - l |= OMAP_DMA_CCR_EN; + if (cpu_is_omap2420() || + (cpu_is_omap2430() && (omap_type() == OMAP2430_REV_ES1_0))) + l |= OMAP_DMA_CCR_BUFFERING_DISABLE; l |= OMAP_DMA_CCR_EN; dma_write(l, CCR(lch)); diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h index 098f154..6f70f7c 100644 --- a/arch/arm/plat-omap/include/plat/dma.h +++ b/arch/arm/plat-omap/include/plat/dma.h @@ -337,6 +337,7 @@ #define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11) #define OMAP_DMA_CCR_EN (1 << 7) +#define OMAP_DMA_CCR_BUFFERING_DISABLE (1 << 25) #define OMAP_DMA_DATA_TYPE_S8 0x00 #define OMAP_DMA_DATA_TYPE_S16 0x01 -- cgit v1.1 From 0e4905c0199d683497833be60a428c784d7575b8 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Mon, 11 Oct 2010 14:18:56 -0700 Subject: OMAP3: DMA: Errata i541: sDMA FIFO draining does not finish Implement the suggested workaround for OMAP3 regarding to sDMA draining issue, when the channel is disabled on the fly. This errata affects the following configuration: sDMA transfer is source synchronized Buffering is enabled SmartStandby is selected. The issue can be easily reproduced by creating overrun situation while recording audio. Either introduce load to the CPU: nice -19 arecord -D hw:0 -M -B 10000 -F 5000 -f dat > /dev/null & \ dd if=/dev/urandom of=/dev/null or suspending the arecord, and resuming it: arecord -D hw:0 -M -B 10000 -F 5000 -f dat > /dev/null CTRL+Z; fg; CTRL+Z; fg; ... In case of overrun audio stops DMA, and restarts it (without reseting the sDMA channel). When we hit this errata in stop case (sDMA drain did not complete), at the coming start the sDMA will not going to be operational (it is still draining). This leads to DMA stall condition. On OMAP3 we can recover with sDMA channel reset, it has been observed that by introducing unrelated sDMA activity might also help (reading from MMC for example). The same errata exists for OMAP2, where the suggestion is to disable the buffering to avoid this type of error. On OMAP3 the suggestion is to set sDMA to NoStandby before disabling the channel, and wait for the drain to finish, than configure sDMA to SmartStandby again. Signed-off-by: Peter Ujfalusi Acked-by: Jarkko Nikula Acked-by : Santosh Shilimkar Acked-by : Manjunath Kondaiah G Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/dma.c | 36 +++++++++++++++++++++++++++++++++-- arch/arm/plat-omap/include/plat/dma.h | 3 +++ 2 files changed, 37 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index 420cef3..f5c5b8d 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include @@ -1024,8 +1025,39 @@ void omap_stop_dma(int lch) dma_write(0, CICR(lch)); l = dma_read(CCR(lch)); - l &= ~OMAP_DMA_CCR_EN; - dma_write(l, CCR(lch)); + /* OMAP3 Errata i541: sDMA FIFO draining does not finish */ + if (cpu_is_omap34xx() && (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) { + int i = 0; + u32 sys_cf; + + /* Configure No-Standby */ + l = dma_read(OCP_SYSCONFIG); + sys_cf = l; + l &= ~DMA_SYSCONFIG_MIDLEMODE_MASK; + l |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE); + dma_write(l , OCP_SYSCONFIG); + + l = dma_read(CCR(lch)); + l &= ~OMAP_DMA_CCR_EN; + dma_write(l, CCR(lch)); + + /* Wait for sDMA FIFO drain */ + l = dma_read(CCR(lch)); + while (i < 100 && (l & (OMAP_DMA_CCR_RD_ACTIVE | + OMAP_DMA_CCR_WR_ACTIVE))) { + udelay(5); + i++; + l = dma_read(CCR(lch)); + } + if (i >= 100) + printk(KERN_ERR "DMA drain did not complete on " + "lch %d\n", lch); + /* Restore OCP_SYSCONFIG */ + dma_write(sys_cf, OCP_SYSCONFIG); + } else { + l &= ~OMAP_DMA_CCR_EN; + dma_write(l, CCR(lch)); + } if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { int next_lch, cur_lch = lch; diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h index 6f70f7c..0cce4ca 100644 --- a/arch/arm/plat-omap/include/plat/dma.h +++ b/arch/arm/plat-omap/include/plat/dma.h @@ -337,6 +337,9 @@ #define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11) #define OMAP_DMA_CCR_EN (1 << 7) +#define OMAP_DMA_CCR_RD_ACTIVE (1 << 9) +#define OMAP_DMA_CCR_WR_ACTIVE (1 << 10) +#define OMAP_DMA_CCR_SEL_SRC_DST_SYNC (1 << 24) #define OMAP_DMA_CCR_BUFFERING_DISABLE (1 << 25) #define OMAP_DMA_DATA_TYPE_S8 0x00 -- cgit v1.1 From 50f2d7f682f9c0ed58191d0982fe77888d59d162 Mon Sep 17 00:00:00 2001 From: Nikanth Karthikesan Date: Thu, 30 Sep 2010 17:34:10 +0530 Subject: x86, numa: Assign CPUs to nodes in round-robin manner on fake NUMA commit d9c2d5ac6af87b4491bff107113aaf16f6c2b2d9 "x86, numa: Use near(er) online node instead of roundrobin for NUMA" changed NUMA initialization on Intel to choose the nearest online node or first node. Fake NUMA would be better of with round-robin initialization, instead of the all CPUS on first node. Change the choice of first node, back to round-robin. For testing NUMA kernel behaviour without cpusets and NUMA aware applications, it would be better to have cpus in different nodes, rather than all in a single node. With cpusets migration of tasks scenarios cannot not be tested. I guess having it round-robin shouldn't affect the use cases for all cpus on the first node. The code comments in arch/x86/mm/numa_64.c:759 indicate that this used to be the case, which was changed by commit d9c2d5ac6. It changed from roundrobin to nearer or first node. And I couldn't find any reason for this change in its changelog. Signed-off-by: Nikanth Karthikesan Cc: David Rientjes Signed-off-by: Andrew Morton --- arch/x86/kernel/cpu/intel.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index b438944..6d61786 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -284,9 +284,7 @@ static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c) /* Don't do the funky fallback heuristics the AMD version employs for now. */ node = apicid_to_node[apicid]; - if (node == NUMA_NO_NODE) - node = first_node(node_online_map); - else if (!node_online(node)) { + if (node == NUMA_NO_NODE || !node_online(node)) { /* reuse the value from init_cpu_to_node() */ node = cpu_to_node(cpu); } -- cgit v1.1 From dab5fff14df2cd16eb1ad4c02e83915e1063fece Mon Sep 17 00:00:00 2001 From: Zhang Rui Date: Tue, 12 Oct 2010 09:09:37 +0800 Subject: acpi-cpufreq: fix a memleak when unloading driver We didn't free per_cpu(acfreq_data, cpu)->freq_table when acpi_freq driver is unloaded. Resulting in the following messages in /sys/kernel/debug/kmemleak: unreferenced object 0xf6450e80 (size 64): comm "modprobe", pid 1066, jiffies 4294677317 (age 19290.453s) hex dump (first 32 bytes): 00 00 00 00 e8 a2 24 00 01 00 00 00 00 9f 24 00 ......$.......$. 02 00 00 00 00 6a 18 00 03 00 00 00 00 35 0c 00 .....j.......5.. backtrace: [] kmemleak_alloc+0x27/0x50 [] __kmalloc+0xcf/0x110 [] acpi_cpufreq_cpu_init+0x1ee/0x4e4 [acpi_cpufreq] [] cpufreq_add_dev+0x142/0x3a0 [] sysdev_driver_register+0x97/0x110 [] cpufreq_register_driver+0x86/0x140 [] 0xf9dad080 [] do_one_initcall+0x30/0x160 [] sys_init_module+0x99/0x1e0 [] sysenter_do_call+0x12/0x26 [] 0xffffffff https://bugzilla.kernel.org/show_bug.cgi?id=15807#c21 Tested-by: Toralf Forster Signed-off-by: Zhang Rui Signed-off-by: Len Brown --- arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c b/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c index cd8da24..a2baafb 100644 --- a/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c +++ b/arch/x86/kernel/cpu/cpufreq/acpi-cpufreq.c @@ -701,6 +701,7 @@ static int acpi_cpufreq_cpu_exit(struct cpufreq_policy *policy) per_cpu(acfreq_data, policy->cpu) = NULL; acpi_processor_unregister_performance(data->acpi_data, policy->cpu); + kfree(data->freq_table); kfree(data); } -- cgit v1.1 From f7cb8b5ffd16edad64ae16ee38c561f98cbcaa3b Mon Sep 17 00:00:00 2001 From: Andi Kleen Date: Mon, 11 Oct 2010 19:51:49 +0200 Subject: Add _addr_lsb field to ia64 siginfo The huge pages code uses the siginfo _addr_lsb field, but ia64 was missing it. Add it to ia64 too (over some padding) to avoid compilation failures. Acked-by: Tony Luck Signed-off-by: Andi Kleen --- arch/ia64/include/asm/siginfo.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/ia64/include/asm/siginfo.h b/arch/ia64/include/asm/siginfo.h index 118d429..c8fcaa2 100644 --- a/arch/ia64/include/asm/siginfo.h +++ b/arch/ia64/include/asm/siginfo.h @@ -62,6 +62,7 @@ typedef struct siginfo { int _imm; /* immediate value for "break" */ unsigned int _flags; /* see below */ unsigned long _isr; /* isr */ + short _addr_lsb; /* lsb of faulting address */ } _sigfault; /* SIGPOLL */ -- cgit v1.1 From 8939b3504dc35224cb9c88e5af925b22ea9eee71 Mon Sep 17 00:00:00 2001 From: Sekhar Nori Date: Tue, 12 Oct 2010 10:25:22 +0530 Subject: davinci: mityomapl138: make file local data static Most of the regulator data structures are local to the board file, but not made static. Fix this. Also make the nand partition table static. This gets rid of all the sparse warnings for this file. Signed-off-by: Sekhar Nori Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/board-mityomapl138.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c index 65f7501..194a15f 100644 --- a/arch/arm/mach-davinci/board-mityomapl138.c +++ b/arch/arm/mach-davinci/board-mityomapl138.c @@ -93,14 +93,14 @@ static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = { /* TPS65023 voltage regulator support */ /* 1.2V Core */ -struct regulator_consumer_supply tps65023_dcdc1_consumers[] = { +static struct regulator_consumer_supply tps65023_dcdc1_consumers[] = { { .supply = "cvdd", }, }; /* 1.8V */ -struct regulator_consumer_supply tps65023_dcdc2_consumers[] = { +static struct regulator_consumer_supply tps65023_dcdc2_consumers[] = { { .supply = "usb0_vdda18", }, @@ -116,7 +116,7 @@ struct regulator_consumer_supply tps65023_dcdc2_consumers[] = { }; /* 1.2V */ -struct regulator_consumer_supply tps65023_dcdc3_consumers[] = { +static struct regulator_consumer_supply tps65023_dcdc3_consumers[] = { { .supply = "sata_vdd", }, @@ -132,20 +132,20 @@ struct regulator_consumer_supply tps65023_dcdc3_consumers[] = { }; /* 1.8V Aux LDO, not used */ -struct regulator_consumer_supply tps65023_ldo1_consumers[] = { +static struct regulator_consumer_supply tps65023_ldo1_consumers[] = { { .supply = "1.8v_aux", }, }; /* FPGA VCC Aux (2.5 or 3.3) LDO */ -struct regulator_consumer_supply tps65023_ldo2_consumers[] = { +static struct regulator_consumer_supply tps65023_ldo2_consumers[] = { { .supply = "vccaux", }, }; -struct regulator_init_data tps65023_regulator_data[] = { +static struct regulator_init_data tps65023_regulator_data[] = { /* dcdc1 */ { .constraints = { @@ -226,7 +226,7 @@ static int __init pmic_tps65023_init(void) * MityDSP-L138 includes a 256 MByte large-page NAND flash * (128K blocks). */ -struct mtd_partition mityomapl138_nandflash_partition[] = { +static struct mtd_partition mityomapl138_nandflash_partition[] = { { .name = "rootfs", .offset = 0, -- cgit v1.1 From ace2dc7d12693545b67f15ab8cdb3d255c937713 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Wed, 13 Oct 2010 06:55:26 +0900 Subject: sh: wire up perf alignment and emulation faults. This plugs in the alignment and emulation fault reporting for perf sw events. Signed-off-by: Paul Mundt --- arch/sh/include/asm/system_32.h | 2 +- arch/sh/kernel/io_trapped.c | 2 +- arch/sh/kernel/traps_32.c | 26 +++++++++++++++++++------- arch/sh/kernel/traps_64.c | 9 +++++++++ arch/sh/math-emu/math.c | 3 +++ 5 files changed, 33 insertions(+), 9 deletions(-) (limited to 'arch') diff --git a/arch/sh/include/asm/system_32.h b/arch/sh/include/asm/system_32.h index 9bd2684..c941b27 100644 --- a/arch/sh/include/asm/system_32.h +++ b/arch/sh/include/asm/system_32.h @@ -212,7 +212,7 @@ static inline reg_size_t register_align(void *val) } int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs, - struct mem_access *ma, int); + struct mem_access *ma, int, unsigned long address); static inline void trigger_address_error(void) { diff --git a/arch/sh/kernel/io_trapped.c b/arch/sh/kernel/io_trapped.c index 2947d2b..32c385e 100644 --- a/arch/sh/kernel/io_trapped.c +++ b/arch/sh/kernel/io_trapped.c @@ -291,7 +291,7 @@ int handle_trapped_io(struct pt_regs *regs, unsigned long address) } tmp = handle_unaligned_access(instruction, regs, - &trapped_io_access, 1); + &trapped_io_access, 1, address); set_fs(oldfs); return tmp == 0; } diff --git a/arch/sh/kernel/traps_32.c b/arch/sh/kernel/traps_32.c index f561352..3484c2f 100644 --- a/arch/sh/kernel/traps_32.c +++ b/arch/sh/kernel/traps_32.c @@ -5,7 +5,7 @@ * SuperH version: Copyright (C) 1999 Niibe Yutaka * Copyright (C) 2000 Philipp Rumpf * Copyright (C) 2000 David Howells - * Copyright (C) 2002 - 2007 Paul Mundt + * Copyright (C) 2002 - 2010 Paul Mundt * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -369,7 +370,8 @@ static inline int handle_delayslot(struct pt_regs *regs, #define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4) int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs, - struct mem_access *ma, int expected) + struct mem_access *ma, int expected, + unsigned long address) { u_int rm; int ret, index; @@ -383,9 +385,18 @@ int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs, index = (instruction>>8)&15; /* 0x0F00 */ rm = regs->regs[index]; - /* shout about fixups */ - if (!expected) + /* + * Log the unexpected fixups, and then pass them on to perf. + * + * We intentionally don't report the expected cases to perf as + * otherwise the trapped I/O case will skew the results too much + * to be useful. + */ + if (!expected) { unaligned_fixups_notify(current, instruction, regs); + perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, 0, + regs, address); + } ret = -EFAULT; switch (instruction&0xF000) { @@ -574,7 +585,8 @@ fixup: set_fs(USER_DS); tmp = handle_unaligned_access(instruction, regs, - &user_mem_access, 0); + &user_mem_access, 0, + address); set_fs(oldfs); if (tmp == 0) @@ -607,8 +619,8 @@ uspace_segv: unaligned_fixups_notify(current, instruction, regs); - handle_unaligned_access(instruction, regs, - &user_mem_access, 0); + handle_unaligned_access(instruction, regs, &user_mem_access, + 0, address); set_fs(oldfs); } } diff --git a/arch/sh/kernel/traps_64.c b/arch/sh/kernel/traps_64.c index fda6355..6713ca9 100644 --- a/arch/sh/kernel/traps_64.c +++ b/arch/sh/kernel/traps_64.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -433,6 +434,8 @@ static int misaligned_load(struct pt_regs *regs, return error; } + perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, 0, regs, address); + destreg = (opcode >> 4) & 0x3f; if (user_mode(regs)) { __u64 buffer; @@ -509,6 +512,8 @@ static int misaligned_store(struct pt_regs *regs, return error; } + perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, 0, regs, address); + srcreg = (opcode >> 4) & 0x3f; if (user_mode(regs)) { __u64 buffer; @@ -583,6 +588,8 @@ static int misaligned_fpu_load(struct pt_regs *regs, return error; } + perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, 0, regs, address); + destreg = (opcode >> 4) & 0x3f; if (user_mode(regs)) { __u64 buffer; @@ -658,6 +665,8 @@ static int misaligned_fpu_store(struct pt_regs *regs, return error; } + perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, 0, regs, address); + srcreg = (opcode >> 4) & 0x3f; if (user_mode(regs)) { __u64 buffer; diff --git a/arch/sh/math-emu/math.c b/arch/sh/math-emu/math.c index 1fcdb12..f76a509 100644 --- a/arch/sh/math-emu/math.c +++ b/arch/sh/math-emu/math.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include @@ -619,6 +620,8 @@ int do_fpu_inst(unsigned short inst, struct pt_regs *regs) struct task_struct *tsk = current; struct sh_fpu_soft_struct *fpu = &(tsk->thread.xstate->softfpu); + perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, 0, regs, 0); + if (!(task_thread_info(tsk)->status & TS_USEDFPU)) { /* initialize once. */ fpu_init(fpu); -- cgit v1.1 From 5e5b3a9dc8405f6a49531a02754a6cc2a1c6cd28 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Wed, 13 Oct 2010 07:17:03 +0900 Subject: sh: perf: Support SH-X3 hardware counters. The PMCAT location has conveniently moved on newer SH-X3 parts, special case this for now with a note. This will probably want to be redone in a less visually offensive way when/if more information becomes available. Signed-off-by: Paul Mundt --- arch/sh/kernel/cpu/sh4a/perf_event.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/sh/kernel/cpu/sh4a/perf_event.c b/arch/sh/kernel/cpu/sh4a/perf_event.c index eddc219..b8b873d 100644 --- a/arch/sh/kernel/cpu/sh4a/perf_event.c +++ b/arch/sh/kernel/cpu/sh4a/perf_event.c @@ -1,7 +1,7 @@ /* * Performance events support for SH-4A performance counters * - * Copyright (C) 2009 Paul Mundt + * Copyright (C) 2009, 2010 Paul Mundt * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -22,7 +22,25 @@ #define CCBR_CMDS (1 << 1) #define CCBR_PPCE (1 << 0) +#ifdef CONFIG_CPU_SHX3 +/* + * The PMCAT location for SH-X3 CPUs was quietly moved, while the CCBR + * and PMCTR locations remains tentatively constant. This change remains + * wholly undocumented, and was simply found through trial and error. + * + * Early cuts of SH-X3 still appear to use the SH-X/SH-X2 locations, and + * it's unclear when this ceased to be the case. For now we always use + * the new location (if future parts keep up with this trend then + * scanning for them at runtime also remains a viable option.) + * + * The gap in the register space also suggests that there are other + * undocumented counters, so this will need to be revisited at a later + * point in time. + */ +#define PPC_PMCAT 0xfc100240 +#else #define PPC_PMCAT 0xfc100080 +#endif #define PMCAT_OVF3 (1 << 27) #define PMCAT_CNN3 (1 << 26) -- cgit v1.1 From 2a12400eed8be0d5790108cba3908a71d6bb9cae Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Tue, 12 Oct 2010 16:07:51 -0700 Subject: omap: Fix spotty MMC voltages MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As noted by Michał Mirosław , the voltages should cover the supported voltage range, or support only one voltage. As all these boards are using a GPIO to enable the power, chances are that only 3.3V cards are supported on these boards. Reported-by: Michał Mirosław Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/board-h2-mmc.c | 3 +-- arch/arm/mach-omap1/board-h3-mmc.c | 3 +-- arch/arm/mach-omap1/board-htcherald.c | 3 +-- arch/arm/mach-omap1/board-sx1-mmc.c | 3 +-- 4 files changed, 4 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap1/board-h2-mmc.c b/arch/arm/mach-omap1/board-h2-mmc.c index b30c499..f2fc43d 100644 --- a/arch/arm/mach-omap1/board-h2-mmc.c +++ b/arch/arm/mach-omap1/board-h2-mmc.c @@ -58,8 +58,7 @@ static struct omap_mmc_platform_data mmc1_data = { .dma_mask = 0xffffffff, .slots[0] = { .set_power = mmc_set_power, - .ocr_mask = MMC_VDD_28_29 | MMC_VDD_30_31 | - MMC_VDD_32_33 | MMC_VDD_33_34, + .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, .name = "mmcblk", }, }; diff --git a/arch/arm/mach-omap1/board-h3-mmc.c b/arch/arm/mach-omap1/board-h3-mmc.c index 54b0f06..2098525 100644 --- a/arch/arm/mach-omap1/board-h3-mmc.c +++ b/arch/arm/mach-omap1/board-h3-mmc.c @@ -40,8 +40,7 @@ static struct omap_mmc_platform_data mmc1_data = { .dma_mask = 0xffffffff, .slots[0] = { .set_power = mmc_set_power, - .ocr_mask = MMC_VDD_28_29 | MMC_VDD_30_31 | - MMC_VDD_32_33 | MMC_VDD_33_34, + .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, .name = "mmcblk", }, }; diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c index 7ea75c1..88c97e2 100644 --- a/arch/arm/mach-omap1/board-htcherald.c +++ b/arch/arm/mach-omap1/board-htcherald.c @@ -410,8 +410,7 @@ static struct omap_mmc_platform_data htc_mmc1_data = { .nr_slots = 1, .switch_slot = NULL, .slots[0] = { - .ocr_mask = MMC_VDD_28_29 | MMC_VDD_30_31 | - MMC_VDD_32_33 | MMC_VDD_33_34, + .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, .name = "mmcblk", .nomux = 1, .wires = 4, diff --git a/arch/arm/mach-omap1/board-sx1-mmc.c b/arch/arm/mach-omap1/board-sx1-mmc.c index 5b33ae8..e8ddd86 100644 --- a/arch/arm/mach-omap1/board-sx1-mmc.c +++ b/arch/arm/mach-omap1/board-sx1-mmc.c @@ -44,8 +44,7 @@ static struct omap_mmc_platform_data mmc1_data = { .nr_slots = 1, .slots[0] = { .set_power = mmc_set_power, - .ocr_mask = MMC_VDD_28_29 | MMC_VDD_30_31 | - MMC_VDD_32_33 | MMC_VDD_33_34, + .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, .name = "mmcblk", }, }; -- cgit v1.1 From f90c34bd658d240cb5ebc5fe0a17796e590c6ec8 Mon Sep 17 00:00:00 2001 From: Andres Salomon Date: Sun, 10 Oct 2010 21:49:45 -0600 Subject: of/promtree: no longer call prom_ functions directly; use an ops structure Rather than assuming an architecture defines prom_getchild and friends, define an ops struct with hooks for the various prom functions that pdt.c needs. This ops struct is filled in by the arch-(and sometimes firmware-)specific code, and passed to of_pdt_build_devicetree. Update sparc code to define the ops struct as well. Signed-off-by: Andres Salomon Acked-by: David S. Miller Signed-off-by: Grant Likely --- arch/sparc/kernel/prom_common.c | 36 +++++++++++++++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/sparc/kernel/prom_common.c b/arch/sparc/kernel/prom_common.c index fe84d56..ed25834 100644 --- a/arch/sparc/kernel/prom_common.c +++ b/arch/sparc/kernel/prom_common.c @@ -118,11 +118,45 @@ int of_find_in_proplist(const char *list, const char *match, int len) } EXPORT_SYMBOL(of_find_in_proplist); +/* + * SPARC32 and SPARC64's prom_nextprop() do things differently + * here, despite sharing the same interface. SPARC32 doesn't fill in 'buf', + * returning NULL on an error. SPARC64 fills in 'buf', but sets it to an + * empty string upon error. + */ +static int __init handle_nextprop_quirks(char *buf, const char *name) +{ + if (!name || strlen(name) == 0) + return -1; + +#ifdef CONFIG_SPARC32 + strcpy(buf, name); +#endif + return 0; +} + +static int __init prom_common_nextprop(phandle node, char *prev, char *buf) +{ + const char *name; + + buf[0] = '\0'; + name = prom_nextprop(node, prev, buf); + return handle_nextprop_quirks(buf, name); +} + unsigned int prom_early_allocated __initdata; +static struct of_pdt_ops prom_sparc_ops __initdata = { + .nextprop = prom_common_nextprop, + .getproplen = prom_getproplen, + .getproperty = prom_getproperty, + .getchild = prom_getchild, + .getsibling = prom_getsibling, +}; + void __init prom_build_devicetree(void) { - of_pdt_build_devicetree(prom_root_node); + of_pdt_build_devicetree(prom_root_node, &prom_sparc_ops); of_console_init(); pr_info("PROM: Built device tree with %u bytes of memory.\n", -- cgit v1.1 From ed41850298f7a55519de0b8573e217ed8a45c199 Mon Sep 17 00:00:00 2001 From: Andres Salomon Date: Sun, 10 Oct 2010 21:51:25 -0600 Subject: of/promtree: add of_pdt namespace to pdt code For symbols still lacking namespace qualifiers, add an of_pdt_ prefix. Signed-off-by: Andres Salomon Acked-by: David S. Miller Signed-off-by: Grant Likely --- arch/sparc/kernel/leon_kernel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/sparc/kernel/leon_kernel.c b/arch/sparc/kernel/leon_kernel.c index 6a7b4db..2d51527 100644 --- a/arch/sparc/kernel/leon_kernel.c +++ b/arch/sparc/kernel/leon_kernel.c @@ -282,5 +282,5 @@ void __init leon_init_IRQ(void) void __init leon_init(void) { - prom_build_more = &leon_node_init; + of_pdt_build_more = &leon_node_init; } -- cgit v1.1 From 51c6c9bb34fcd112d4ab8b8f5c1d1b6a10a00e71 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Wed, 13 Oct 2010 17:52:14 +0900 Subject: sh: perf: Set up perf_max_events. Presently this is uninitialized in the architecture code, so it's artificlally capped to the default initialization value. Set it up at registration time. Signed-off-by: Paul Mundt --- arch/sh/kernel/perf_event.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/sh/kernel/perf_event.c b/arch/sh/kernel/perf_event.c index 7a3dc35..ecef1fe 100644 --- a/arch/sh/kernel/perf_event.c +++ b/arch/sh/kernel/perf_event.c @@ -324,6 +324,7 @@ int __cpuinit register_sh_pmu(struct sh_pmu *pmu) pr_info("Performance Events: %s support registered\n", pmu->name); WARN_ON(pmu->num_events > MAX_HWEVENTS); + perf_max_events = pmu->num_events; perf_cpu_notifier(sh_pmu_notifier); return 0; -- cgit v1.1 From 934e40781aa92dae0b9d753d7de4a743c96b9bd2 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 13 Oct 2010 07:22:11 +0000 Subject: ARM: shmobile: break out sh7372 platform devices This patch introduces sh7372_late_devices which should include all regular processor specific platform devices. Early platform devices for console and timers should be put on the sh7372_early_devices list, all other devices should be on sh7372_late_devices. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/setup-sh7372.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c index f6cdf76..68c8d6c 100644 --- a/arch/arm/mach-shmobile/setup-sh7372.c +++ b/arch/arm/mach-shmobile/setup-sh7372.c @@ -526,6 +526,9 @@ static struct platform_device *sh7372_early_devices[] __initdata = { &scif5_device, &scif6_device, &cmt10_device, +}; + +static struct platform_device *sh7372_late_devices[] __initdata = { &iic0_device, &iic1_device, &dma0_device, @@ -537,6 +540,9 @@ void __init sh7372_add_standard_devices(void) { platform_add_devices(sh7372_early_devices, ARRAY_SIZE(sh7372_early_devices)); + + platform_add_devices(sh7372_late_devices, + ARRAY_SIZE(sh7372_late_devices)); } void __init sh7372_add_early_devices(void) -- cgit v1.1 From 0fb0834b36c2a952640883cd4b68f01d0843eca6 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 13 Oct 2010 07:39:18 +0000 Subject: ARM: shmobile: make AP4EVB MMCIF resource string consistent Just use MMCIF as name to match the sh7372 data sheet. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/board-ap4evb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c index 943cc21..aaac8b0 100644 --- a/arch/arm/mach-shmobile/board-ap4evb.c +++ b/arch/arm/mach-shmobile/board-ap4evb.c @@ -237,7 +237,7 @@ static struct platform_device smc911x_device = { /* SH_MMCIF */ static struct resource sh_mmcif_resources[] = { [0] = { - .name = "SH_MMCIF", + .name = "MMCIF", .start = 0xE6BD0000, .end = 0xE6BD00FF, .flags = IORESOURCE_MEM, -- cgit v1.1 From 90e09a59110949bda40c13b4e5925f3acd3597b0 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 13 Oct 2010 07:29:31 +0000 Subject: ARM: shmobile: use device name for timer clocks Move SH-Mobile ARM systems over from the legacy "clk" member of struct sh_timer_config to using the device name and clkdev for clock matching. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/clock-sh7367.c | 2 +- arch/arm/mach-shmobile/clock-sh7372.c | 2 +- arch/arm/mach-shmobile/clock-sh7377.c | 2 +- arch/arm/mach-shmobile/setup-sh7367.c | 1 - arch/arm/mach-shmobile/setup-sh7372.c | 1 - arch/arm/mach-shmobile/setup-sh7377.c | 1 - 6 files changed, 3 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/clock-sh7367.c b/arch/arm/mach-shmobile/clock-sh7367.c index b6454c9..9f78729 100644 --- a/arch/arm/mach-shmobile/clock-sh7367.c +++ b/arch/arm/mach-shmobile/clock-sh7367.c @@ -321,7 +321,7 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[SYMSTP001]), /* SCIFA3 */ CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[SYMSTP000]), /* SCIFA4 */ CLKDEV_DEV_ID("sh_siu", &mstp_clks[SYMSTP231]), /* SIU */ - CLKDEV_CON_ID("cmt1", &mstp_clks[SYMSTP229]), /* CMT10 */ + CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[SYMSTP229]), /* CMT10 */ CLKDEV_DEV_ID("sh_irda", &mstp_clks[SYMSTP225]), /* IRDA */ CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[SYMSTP223]), /* IIC1 */ CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[SYMSTP222]), /* USBHS */ diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c index ea384e1..3ab190a 100644 --- a/arch/arm/mach-shmobile/clock-sh7372.c +++ b/arch/arm/mach-shmobile/clock-sh7372.c @@ -516,7 +516,7 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */ CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */ CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */ - CLKDEV_CON_ID("cmt1", &mstp_clks[MSTP329]), /* CMT10 */ + CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */ CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI2 */ CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */ CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP323]), /* USB0 */ diff --git a/arch/arm/mach-shmobile/clock-sh7377.c b/arch/arm/mach-shmobile/clock-sh7377.c index e007c28..f91395a 100644 --- a/arch/arm/mach-shmobile/clock-sh7377.c +++ b/arch/arm/mach-shmobile/clock-sh7377.c @@ -333,7 +333,7 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */ CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */ CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */ - CLKDEV_CON_ID("cmt1", &mstp_clks[MSTP329]), /* CMT10 */ + CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */ CLKDEV_DEV_ID("sh_irda", &mstp_clks[MSTP325]), /* IRDA */ CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */ CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP322]), /* USBHS */ diff --git a/arch/arm/mach-shmobile/setup-sh7367.c b/arch/arm/mach-shmobile/setup-sh7367.c index 3148c11..003008c 100644 --- a/arch/arm/mach-shmobile/setup-sh7367.c +++ b/arch/arm/mach-shmobile/setup-sh7367.c @@ -154,7 +154,6 @@ static struct sh_timer_config cmt10_platform_data = { .name = "CMT10", .channel_offset = 0x10, .timer_bit = 0, - .clk = "r_clk", .clockevent_rating = 125, .clocksource_rating = 125, }; diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c index 68c8d6c..ed1324f 100644 --- a/arch/arm/mach-shmobile/setup-sh7372.c +++ b/arch/arm/mach-shmobile/setup-sh7372.c @@ -158,7 +158,6 @@ static struct sh_timer_config cmt10_platform_data = { .name = "CMT10", .channel_offset = 0x10, .timer_bit = 0, - .clk = "cmt1", .clockevent_rating = 125, .clocksource_rating = 125, }; diff --git a/arch/arm/mach-shmobile/setup-sh7377.c b/arch/arm/mach-shmobile/setup-sh7377.c index bb4adf1..575dbd6 100644 --- a/arch/arm/mach-shmobile/setup-sh7377.c +++ b/arch/arm/mach-shmobile/setup-sh7377.c @@ -172,7 +172,6 @@ static struct sh_timer_config cmt10_platform_data = { .name = "CMT10", .channel_offset = 0x10, .timer_bit = 0, - .clk = "r_clk", .clockevent_rating = 125, .clocksource_rating = 125, }; -- cgit v1.1 From 1158f0f16224068e27e384c1a27218aa00243967 Mon Sep 17 00:00:00 2001 From: Sundar Iyer Date: Wed, 29 Sep 2010 19:42:14 -0700 Subject: Input: add support for Nomadik SKE keypad controller Add support for the keypad controller in the Scroll Key Encoder (SKE) module on the Nomadik family and the DB8500 SoC. Acked-by: Linus Walleij Signed-off-by: Sundar Iyer Signed-off-by: Dmitry Torokhov --- arch/arm/plat-nomadik/include/plat/ske.h | 50 ++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 arch/arm/plat-nomadik/include/plat/ske.h (limited to 'arch') diff --git a/arch/arm/plat-nomadik/include/plat/ske.h b/arch/arm/plat-nomadik/include/plat/ske.h new file mode 100644 index 0000000..31382fb --- /dev/null +++ b/arch/arm/plat-nomadik/include/plat/ske.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * License Terms: GNU General Public License v2 + * Author: Naveen Kumar Gaddipati + * + * ux500 Scroll key and Keypad Encoder (SKE) header + */ + +#ifndef __SKE_H +#define __SKE_H + +#include + +/* register definitions for SKE peripheral */ +#define SKE_CR 0x00 +#define SKE_VAL0 0x04 +#define SKE_VAL1 0x08 +#define SKE_DBCR 0x0C +#define SKE_IMSC 0x10 +#define SKE_RIS 0x14 +#define SKE_MIS 0x18 +#define SKE_ICR 0x1C + +/* + * Keypad module + */ + +/** + * struct keypad_platform_data - structure for platform specific data + * @init: pointer to keypad init function + * @exit: pointer to keypad deinitialisation function + * @keymap_data: matrix scan code table for keycodes + * @krow: maximum number of rows + * @kcol: maximum number of columns + * @debounce_ms: platform specific debounce time + * @no_autorepeat: flag for auto repetition + * @wakeup_enable: allow waking up the system + */ +struct ske_keypad_platform_data { + int (*init)(void); + int (*exit)(void); + const struct matrix_keymap_data *keymap_data; + u8 krow; + u8 kcol; + u8 debounce_ms; + bool no_autorepeat; + bool wakeup_enable; +}; +#endif /*__SKE_KPD_H*/ -- cgit v1.1 From 4c61c8457ee92a2afc5a43aa0821971727ebd38c Mon Sep 17 00:00:00 2001 From: Sundar Iyer Date: Wed, 29 Sep 2010 19:43:09 -0700 Subject: ux500 - add platform data for Nomadik SKE keypad controller Signed-off-by: Sundar Iyer Signed-off-by: Dmitry Torokhov --- arch/arm/mach-ux500/board-mop500.c | 129 +++++++++++++++++++++++++++++ arch/arm/mach-ux500/clock.c | 1 + arch/arm/mach-ux500/devices-db8500.c | 20 +++++ arch/arm/mach-ux500/include/mach/devices.h | 1 + arch/arm/mach-ux500/pins-db8500.h | 32 +++---- 5 files changed, 167 insertions(+), 16 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index 0e8fd13..5265fb9 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c @@ -18,12 +18,14 @@ #include #include #include +#include #include #include #include #include +#include #include #include @@ -47,6 +49,24 @@ static pin_cfg_t mop500_pins[] = { GPIO11_I2C2_SCL, GPIO229_I2C3_SDA, GPIO230_I2C3_SCL, + + /* SKE keypad */ + GPIO153_KP_I7, + GPIO154_KP_I6, + GPIO155_KP_I5, + GPIO156_KP_I4, + GPIO157_KP_O7, + GPIO158_KP_O6, + GPIO159_KP_O5, + GPIO160_KP_O4, + GPIO161_KP_I3, + GPIO162_KP_I2, + GPIO163_KP_I1, + GPIO164_KP_I0, + GPIO165_KP_O3, + GPIO166_KP_O2, + GPIO167_KP_O1, + GPIO168_KP_O0, }; static void ab4500_spi_cs_control(u32 command) @@ -134,12 +154,120 @@ static struct amba_device *amba_devs[] __initdata = { &u8500_ssp0_device, }; +static const unsigned int ux500_keymap[] = { + KEY(2, 5, KEY_END), + KEY(4, 1, KEY_POWER), + KEY(3, 5, KEY_VOLUMEDOWN), + KEY(1, 3, KEY_3), + KEY(5, 2, KEY_RIGHT), + KEY(5, 0, KEY_9), + + KEY(0, 5, KEY_MENU), + KEY(7, 6, KEY_ENTER), + KEY(4, 5, KEY_0), + KEY(6, 7, KEY_2), + KEY(3, 4, KEY_UP), + KEY(3, 3, KEY_DOWN), + + KEY(6, 4, KEY_SEND), + KEY(6, 2, KEY_BACK), + KEY(4, 2, KEY_VOLUMEUP), + KEY(5, 5, KEY_1), + KEY(4, 3, KEY_LEFT), + KEY(3, 2, KEY_7), +}; + +static const struct matrix_keymap_data ux500_keymap_data = { + .keymap = ux500_keymap, + .keymap_size = ARRAY_SIZE(ux500_keymap), +}; + +/* + * Nomadik SKE keypad + */ +#define ROW_PIN_I0 164 +#define ROW_PIN_I1 163 +#define ROW_PIN_I2 162 +#define ROW_PIN_I3 161 +#define ROW_PIN_I4 156 +#define ROW_PIN_I5 155 +#define ROW_PIN_I6 154 +#define ROW_PIN_I7 153 +#define COL_PIN_O0 168 +#define COL_PIN_O1 167 +#define COL_PIN_O2 166 +#define COL_PIN_O3 165 +#define COL_PIN_O4 160 +#define COL_PIN_O5 159 +#define COL_PIN_O6 158 +#define COL_PIN_O7 157 + +#define SKE_KPD_MAX_ROWS 8 +#define SKE_KPD_MAX_COLS 8 + +static int ske_kp_rows[] = { + ROW_PIN_I0, ROW_PIN_I1, ROW_PIN_I2, ROW_PIN_I3, + ROW_PIN_I4, ROW_PIN_I5, ROW_PIN_I6, ROW_PIN_I7, +}; + +/* + * ske_set_gpio_row: request and set gpio rows + */ +static int ske_set_gpio_row(int gpio) +{ + int ret; + + ret = gpio_request(gpio, "ske-kp"); + if (ret < 0) { + pr_err("ske_set_gpio_row: gpio request failed\n"); + return ret; + } + + ret = gpio_direction_output(gpio, 1); + if (ret < 0) { + pr_err("ske_set_gpio_row: gpio direction failed\n"); + gpio_free(gpio); + } + + return ret; +} + +/* + * ske_kp_init - enable the gpio configuration + */ +static int ske_kp_init(void) +{ + int ret, i; + + for (i = 0; i < SKE_KPD_MAX_ROWS; i++) { + ret = ske_set_gpio_row(ske_kp_rows[i]); + if (ret < 0) { + pr_err("ske_kp_init: failed init\n"); + return ret; + } + } + + return 0; +} + +static struct ske_keypad_platform_data ske_keypad_board = { + .init = ske_kp_init, + .keymap_data = &ux500_keymap_data, + .no_autorepeat = true, + .krow = SKE_KPD_MAX_ROWS, /* 8x8 matrix */ + .kcol = SKE_KPD_MAX_COLS, + .debounce_ms = 40, /* in millsecs */ +}; + + + /* add any platform devices here - TODO */ static struct platform_device *platform_devs[] __initdata = { &u8500_i2c0_device, &ux500_i2c1_device, &ux500_i2c2_device, &ux500_i2c3_device, + &ux500_ske_keypad_device, }; static void __init u8500_init_machine(void) @@ -154,6 +282,7 @@ static void __init u8500_init_machine(void) ux500_i2c1_device.dev.platform_data = &u8500_i2c1_data; ux500_i2c2_device.dev.platform_data = &u8500_i2c2_data; ux500_i2c3_device.dev.platform_data = &u8500_i2c3_data; + ux500_ske_keypad_device.dev.platform_data = &ske_keypad_board; u8500_ssp0_device.dev.platform_data = &ssp0_platform_data; diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c index d8ab7f1..1675047 100644 --- a/arch/arm/mach-ux500/clock.c +++ b/arch/arm/mach-ux500/clock.c @@ -477,6 +477,7 @@ static struct clk_lookup u8500_common_clks[] = { CLK(sdi5, "sdi5", NULL), CLK(uart2, "uart2", NULL), CLK(ske, "ske", NULL), + CLK(ske, "nmk-ske-keypad", NULL), CLK(sdi2, "sdi2", NULL), CLK(i2c0, "nmk-i2c.0", NULL), CLK(fsmc, "fsmc", NULL), diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c index 9280d25..735aaee 100644 --- a/arch/arm/mach-ux500/devices-db8500.c +++ b/arch/arm/mach-ux500/devices-db8500.c @@ -216,3 +216,23 @@ void dma40_u8500ed_fixup(void) dma40_resources[1].start = U8500_DMA_LCPA_BASE_ED; dma40_resources[1].end = U8500_DMA_LCPA_BASE_ED + 2 * SZ_1K - 1; } + +struct resource keypad_resources[] = { + [0] = { + .start = U8500_SKE_BASE, + .end = U8500_SKE_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_DB8500_KB, + .end = IRQ_DB8500_KB, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device ux500_ske_keypad_device = { + .name = "nmk-ske-keypad", + .id = -1, + .num_resources = ARRAY_SIZE(keypad_resources), + .resource = keypad_resources, +}; diff --git a/arch/arm/mach-ux500/include/mach/devices.h b/arch/arm/mach-ux500/include/mach/devices.h index c2b2f25..12e6606 100644 --- a/arch/arm/mach-ux500/include/mach/devices.h +++ b/arch/arm/mach-ux500/include/mach/devices.h @@ -26,6 +26,7 @@ extern struct platform_device ux500_i2c3_device; extern struct platform_device u8500_i2c0_device; extern struct platform_device u8500_i2c4_device; extern struct platform_device u8500_dma40_device; +extern struct platform_device ux500_ske_keypad_device; void dma40_u8500ed_fixup(void); diff --git a/arch/arm/mach-ux500/pins-db8500.h b/arch/arm/mach-ux500/pins-db8500.h index 9055d5d..8cf0649 100644 --- a/arch/arm/mach-ux500/pins-db8500.h +++ b/arch/arm/mach-ux500/pins-db8500.h @@ -459,82 +459,82 @@ #define GPIO152_KP_O9 PIN_CFG(152, ALT_C) #define GPIO153_GPIO PIN_CFG(153, GPIO) -#define GPIO153_KP_I7 PIN_CFG(153, ALT_A) +#define GPIO153_KP_I7 PIN_CFG_PULL(153, ALT_A, DOWN) #define GPIO153_LCD_D24 PIN_CFG(153, ALT_B) #define GPIO153_U2_RXD PIN_CFG(153, ALT_C) #define GPIO154_GPIO PIN_CFG(154, GPIO) -#define GPIO154_KP_I6 PIN_CFG(154, ALT_A) +#define GPIO154_KP_I6 PIN_CFG_PULL(154, ALT_A, DOWN) #define GPIO154_LCD_D25 PIN_CFG(154, ALT_B) #define GPIO154_U2_TXD PIN_CFG(154, ALT_C) #define GPIO155_GPIO PIN_CFG(155, GPIO) -#define GPIO155_KP_I5 PIN_CFG(155, ALT_A) +#define GPIO155_KP_I5 PIN_CFG_PULL(155, ALT_A, DOWN) #define GPIO155_LCD_D26 PIN_CFG(155, ALT_B) #define GPIO155_STMAPE_CLK PIN_CFG(155, ALT_C) #define GPIO156_GPIO PIN_CFG(156, GPIO) -#define GPIO156_KP_I4 PIN_CFG(156, ALT_A) +#define GPIO156_KP_I4 PIN_CFG_PULL(156, ALT_A, DOWN) #define GPIO156_LCD_D27 PIN_CFG(156, ALT_B) #define GPIO156_STMAPE_DAT3 PIN_CFG(156, ALT_C) #define GPIO157_GPIO PIN_CFG(157, GPIO) -#define GPIO157_KP_O7 PIN_CFG(157, ALT_A) +#define GPIO157_KP_O7 PIN_CFG_PULL(157, ALT_A, UP) #define GPIO157_LCD_D28 PIN_CFG(157, ALT_B) #define GPIO157_STMAPE_DAT2 PIN_CFG(157, ALT_C) #define GPIO158_GPIO PIN_CFG(158, GPIO) -#define GPIO158_KP_O6 PIN_CFG(158, ALT_A) +#define GPIO158_KP_O6 PIN_CFG_PULL(158, ALT_A, UP) #define GPIO158_LCD_D29 PIN_CFG(158, ALT_B) #define GPIO158_STMAPE_DAT1 PIN_CFG(158, ALT_C) #define GPIO159_GPIO PIN_CFG(159, GPIO) -#define GPIO159_KP_O5 PIN_CFG(159, ALT_A) +#define GPIO159_KP_O5 PIN_CFG_PULL(159, ALT_A, UP) #define GPIO159_LCD_D30 PIN_CFG(159, ALT_B) #define GPIO159_STMAPE_DAT0 PIN_CFG(159, ALT_C) #define GPIO160_GPIO PIN_CFG(160, GPIO) -#define GPIO160_KP_O4 PIN_CFG(160, ALT_A) +#define GPIO160_KP_O4 PIN_CFG_PULL(160, ALT_A, UP) #define GPIO160_LCD_D31 PIN_CFG(160, ALT_B) #define GPIO160_NONE PIN_CFG(160, ALT_C) #define GPIO161_GPIO PIN_CFG(161, GPIO) -#define GPIO161_KP_I3 PIN_CFG(161, ALT_A) +#define GPIO161_KP_I3 PIN_CFG_PULL(161, ALT_A, DOWN) #define GPIO161_LCD_D32 PIN_CFG(161, ALT_B) #define GPIO161_UARTMOD_RXD PIN_CFG(161, ALT_C) #define GPIO162_GPIO PIN_CFG(162, GPIO) -#define GPIO162_KP_I2 PIN_CFG(162, ALT_A) +#define GPIO162_KP_I2 PIN_CFG_PULL(162, ALT_A, DOWN) #define GPIO162_LCD_D33 PIN_CFG(162, ALT_B) #define GPIO162_UARTMOD_TXD PIN_CFG(162, ALT_C) #define GPIO163_GPIO PIN_CFG(163, GPIO) -#define GPIO163_KP_I1 PIN_CFG(163, ALT_A) +#define GPIO163_KP_I1 PIN_CFG_PULL(163, ALT_A, DOWN) #define GPIO163_LCD_D34 PIN_CFG(163, ALT_B) #define GPIO163_STMMOD_CLK PIN_CFG(163, ALT_C) #define GPIO164_GPIO PIN_CFG(164, GPIO) -#define GPIO164_KP_I0 PIN_CFG(164, ALT_A) +#define GPIO164_KP_I0 PIN_CFG_PULL(164, ALT_A, UP) #define GPIO164_LCD_D35 PIN_CFG(164, ALT_B) #define GPIO164_STMMOD_DAT3 PIN_CFG(164, ALT_C) #define GPIO165_GPIO PIN_CFG(165, GPIO) -#define GPIO165_KP_O3 PIN_CFG(165, ALT_A) +#define GPIO165_KP_O3 PIN_CFG_PULL(165, ALT_A, UP) #define GPIO165_LCD_D36 PIN_CFG(165, ALT_B) #define GPIO165_STMMOD_DAT2 PIN_CFG(165, ALT_C) #define GPIO166_GPIO PIN_CFG(166, GPIO) -#define GPIO166_KP_O2 PIN_CFG(166, ALT_A) +#define GPIO166_KP_O2 PIN_CFG_PULL(166, ALT_A, UP) #define GPIO166_LCD_D37 PIN_CFG(166, ALT_B) #define GPIO166_STMMOD_DAT1 PIN_CFG(166, ALT_C) #define GPIO167_GPIO PIN_CFG(167, GPIO) -#define GPIO167_KP_O1 PIN_CFG(167, ALT_A) +#define GPIO167_KP_O1 PIN_CFG_PULL(167, ALT_A, UP) #define GPIO167_LCD_D38 PIN_CFG(167, ALT_B) #define GPIO167_STMMOD_DAT0 PIN_CFG(167, ALT_C) #define GPIO168_GPIO PIN_CFG(168, GPIO) -#define GPIO168_KP_O0 PIN_CFG(168, ALT_A) +#define GPIO168_KP_O0 PIN_CFG_PULL(168, ALT_A, UP) #define GPIO168_LCD_D39 PIN_CFG(168, ALT_B) #define GPIO168_NONE PIN_CFG(168, ALT_C) -- cgit v1.1 From f3a1ba60dbdbf46f2715cc4e3f8abc9d65c4d9bf Mon Sep 17 00:00:00 2001 From: Abraham Arce Date: Wed, 29 Sep 2010 23:35:57 -0700 Subject: Input: omap4-keypad - use platform device helpers Get mem and irq resources using platform helpers - platform_get_base - platform_get_irq Signed-off-by: Abraham Arce Signed-off-by: Dmitry Torokhov --- arch/arm/plat-omap/include/plat/omap4-keypad.h | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-omap/include/plat/omap4-keypad.h b/arch/arm/plat-omap/include/plat/omap4-keypad.h index 522a8ab..2b1d9bc 100644 --- a/arch/arm/plat-omap/include/plat/omap4-keypad.h +++ b/arch/arm/plat-omap/include/plat/omap4-keypad.h @@ -8,9 +8,7 @@ struct omap4_keypad_platform_data { u8 rows; u8 cols; - - u16 irq; - void __iomem *base; }; +extern int omap4_keyboard_init(struct omap4_keypad_platform_data *); #endif -- cgit v1.1 From 47da88f36639b8de57f6cdd680f8c27528ccd67c Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Thu, 14 Oct 2010 03:04:44 +0900 Subject: sh: mach-sdk7786: Add support for fpga gpios. The sdk7786 FPGA supports a number of user settable input switches that are otherwise unused. This wires up a dummy gpio chip for the switch bank to simply expose them to userspace. Signed-off-by: Paul Mundt --- arch/sh/boards/Kconfig | 1 + arch/sh/boards/mach-sdk7786/Makefile | 2 ++ arch/sh/boards/mach-sdk7786/gpio.c | 49 ++++++++++++++++++++++++++++++++++++ 3 files changed, 52 insertions(+) create mode 100644 arch/sh/boards/mach-sdk7786/gpio.c (limited to 'arch') diff --git a/arch/sh/boards/Kconfig b/arch/sh/boards/Kconfig index 90ed1ec..bb2cb27 100644 --- a/arch/sh/boards/Kconfig +++ b/arch/sh/boards/Kconfig @@ -155,6 +155,7 @@ config SH_SDK7786 depends on CPU_SUBTYPE_SH7786 select SYS_SUPPORTS_PCI select NO_IOPORT if !PCI + select ARCH_WANT_OPTIONAL_GPIOLIB help Select SDK7786 if configuring for a Renesas Technology Europe SH7786-65nm board. diff --git a/arch/sh/boards/mach-sdk7786/Makefile b/arch/sh/boards/mach-sdk7786/Makefile index a29f19e..d0f801b 100644 --- a/arch/sh/boards/mach-sdk7786/Makefile +++ b/arch/sh/boards/mach-sdk7786/Makefile @@ -1 +1,3 @@ obj-y := setup.o fpga.o irq.o + +obj-$(CONFIG_GENERIC_GPIO) += gpio.o diff --git a/arch/sh/boards/mach-sdk7786/gpio.c b/arch/sh/boards/mach-sdk7786/gpio.c new file mode 100644 index 0000000..f71ce09 --- /dev/null +++ b/arch/sh/boards/mach-sdk7786/gpio.c @@ -0,0 +1,49 @@ +/* + * SDK7786 FPGA USRGPIR Support. + * + * Copyright (C) 2010 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#define NR_FPGA_GPIOS 8 + +static const char *usrgpir_gpio_names[NR_FPGA_GPIOS] = { + "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7", +}; + +static int usrgpir_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) +{ + /* always in */ + return 0; +} + +static int usrgpir_gpio_get(struct gpio_chip *chip, unsigned gpio) +{ + return !!(fpga_read_reg(USRGPIR) & (1 << gpio)); +} + +static struct gpio_chip usrgpir_gpio_chip = { + .label = "sdk7786-fpga", + .names = usrgpir_gpio_names, + .direction_input = usrgpir_gpio_direction_input, + .get = usrgpir_gpio_get, + .base = -1, /* don't care */ + .ngpio = NR_FPGA_GPIOS, +}; + +static int __init usrgpir_gpio_setup(void) +{ + return gpiochip_add(&usrgpir_gpio_chip); +} +device_initcall(usrgpir_gpio_setup); -- cgit v1.1 From f7fcec93b619337feb9da829b8a9ab6ba86393bc Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Thu, 14 Oct 2010 03:49:15 +0900 Subject: sh: Fix up PMB locking. This first converts the PMB locking over to raw spinlocks, and secondly fixes up a nested locking issue that was triggering lockdep early on: swapper/0 is trying to acquire lock: (&pmbe->lock){......}, at: [<806be9bc>] pmb_init+0xf4/0x4dc but task is already holding lock: (&pmbe->lock){......}, at: [<806be98e>] pmb_init+0xc6/0x4dc other info that might help us debug this: 1 lock held by swapper/0: #0: (&pmbe->lock){......}, at: [<806be98e>] pmb_init+0xc6/0x4dc Signed-off-by: Paul Mundt --- arch/sh/mm/pmb.c | 31 +++++++++++++++---------------- 1 file changed, 15 insertions(+), 16 deletions(-) (limited to 'arch') diff --git a/arch/sh/mm/pmb.c b/arch/sh/mm/pmb.c index 233c011..b20b1b3 100644 --- a/arch/sh/mm/pmb.c +++ b/arch/sh/mm/pmb.c @@ -40,7 +40,7 @@ struct pmb_entry { unsigned long flags; unsigned long size; - spinlock_t lock; + raw_spinlock_t lock; /* * 0 .. NR_PMB_ENTRIES for specific entry selection, or @@ -265,7 +265,7 @@ static struct pmb_entry *pmb_alloc(unsigned long vpn, unsigned long ppn, memset(pmbe, 0, sizeof(struct pmb_entry)); - spin_lock_init(&pmbe->lock); + raw_spin_lock_init(&pmbe->lock); pmbe->vpn = vpn; pmbe->ppn = ppn; @@ -327,9 +327,9 @@ static void set_pmb_entry(struct pmb_entry *pmbe) { unsigned long flags; - spin_lock_irqsave(&pmbe->lock, flags); + raw_spin_lock_irqsave(&pmbe->lock, flags); __set_pmb_entry(pmbe); - spin_unlock_irqrestore(&pmbe->lock, flags); + raw_spin_unlock_irqrestore(&pmbe->lock, flags); } #endif /* CONFIG_PM */ @@ -368,7 +368,7 @@ int pmb_bolt_mapping(unsigned long vaddr, phys_addr_t phys, return PTR_ERR(pmbe); } - spin_lock_irqsave(&pmbe->lock, flags); + raw_spin_lock_irqsave(&pmbe->lock, flags); pmbe->size = pmb_sizes[i].size; @@ -383,9 +383,10 @@ int pmb_bolt_mapping(unsigned long vaddr, phys_addr_t phys, * entries for easier tear-down. */ if (likely(pmbp)) { - spin_lock(&pmbp->lock); + raw_spin_lock_nested(&pmbp->lock, + SINGLE_DEPTH_NESTING); pmbp->link = pmbe; - spin_unlock(&pmbp->lock); + raw_spin_unlock(&pmbp->lock); } pmbp = pmbe; @@ -398,7 +399,7 @@ int pmb_bolt_mapping(unsigned long vaddr, phys_addr_t phys, i--; mapped++; - spin_unlock_irqrestore(&pmbe->lock, flags); + raw_spin_unlock_irqrestore(&pmbe->lock, flags); } } while (size >= SZ_16M); @@ -627,15 +628,14 @@ static void __init pmb_synchronize(void) continue; } - spin_lock_irqsave(&pmbe->lock, irqflags); + raw_spin_lock_irqsave(&pmbe->lock, irqflags); for (j = 0; j < ARRAY_SIZE(pmb_sizes); j++) if (pmb_sizes[j].flag == size) pmbe->size = pmb_sizes[j].size; if (pmbp) { - spin_lock(&pmbp->lock); - + raw_spin_lock_nested(&pmbp->lock, SINGLE_DEPTH_NESTING); /* * Compare the previous entry against the current one to * see if the entries span a contiguous mapping. If so, @@ -644,13 +644,12 @@ static void __init pmb_synchronize(void) */ if (pmb_can_merge(pmbp, pmbe)) pmbp->link = pmbe; - - spin_unlock(&pmbp->lock); + raw_spin_unlock(&pmbp->lock); } pmbp = pmbe; - spin_unlock_irqrestore(&pmbe->lock, irqflags); + raw_spin_unlock_irqrestore(&pmbe->lock, irqflags); } } @@ -757,7 +756,7 @@ static void __init pmb_resize(void) /* * Found it, now resize it. */ - spin_lock_irqsave(&pmbe->lock, flags); + raw_spin_lock_irqsave(&pmbe->lock, flags); pmbe->size = SZ_16M; pmbe->flags &= ~PMB_SZ_MASK; @@ -767,7 +766,7 @@ static void __init pmb_resize(void) __set_pmb_entry(pmbe); - spin_unlock_irqrestore(&pmbe->lock, flags); + raw_spin_unlock_irqrestore(&pmbe->lock, flags); } read_unlock(&pmb_rwlock); -- cgit v1.1 From 61a46766c9d5d8fb5dad23da1b7cc4cb8b0107da Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Thu, 14 Oct 2010 07:37:01 +0900 Subject: sh: pci: Support slot 4 routing on SDK7786. SDK7786 supports connecting either slot3 or 4 to the same PCIe port by way of FPGA muxing. By default the vertical slot 3 on the baseboard is enabled, so this adds in a command line option for forcibly enabling the slot 4 edge connector. If nothing has been specified on the command line, we fall back to reading the resistor values for card presence to figure out where to route the port to. Signed-off-by: Paul Mundt --- arch/sh/drivers/pci/Makefile | 1 + arch/sh/drivers/pci/fixups-sdk7786.c | 68 ++++++++++++++++++++++++++++++++ arch/sh/drivers/pci/pci.c | 2 +- arch/sh/include/mach-sdk7786/mach/fpga.h | 9 +++++ 4 files changed, 79 insertions(+), 1 deletion(-) create mode 100644 arch/sh/drivers/pci/fixups-sdk7786.c (limited to 'arch') diff --git a/arch/sh/drivers/pci/Makefile b/arch/sh/drivers/pci/Makefile index 4a59e68..82f0a33 100644 --- a/arch/sh/drivers/pci/Makefile +++ b/arch/sh/drivers/pci/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_SH_RTS7751R2D) += fixups-rts7751r2d.o obj-$(CONFIG_SH_SH03) += fixups-sh03.o obj-$(CONFIG_SH_HIGHLANDER) += fixups-r7780rp.o obj-$(CONFIG_SH_SH7785LCR) += fixups-r7780rp.o +obj-$(CONFIG_SH_SDK7786) += fixups-sdk7786.o obj-$(CONFIG_SH_SDK7780) += fixups-sdk7780.o obj-$(CONFIG_SH_7780_SOLUTION_ENGINE) += fixups-sdk7780.o obj-$(CONFIG_SH_TITAN) += fixups-titan.o diff --git a/arch/sh/drivers/pci/fixups-sdk7786.c b/arch/sh/drivers/pci/fixups-sdk7786.c new file mode 100644 index 0000000..058a65a --- /dev/null +++ b/arch/sh/drivers/pci/fixups-sdk7786.c @@ -0,0 +1,68 @@ +/* + * SDK7786 FPGA PCIe mux handling + * + * Copyright (C) 2010 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#define pr_fmt(fmt) "PCI: " fmt + +#include +#include +#include +#include +#include + +/* + * The SDK7786 FPGA supports mangling of most of the slots in some way or + * another. Slots 3/4 are special in that only one can be supported at a + * time, and both appear on port 3 to the PCI bus scan. Enabling slot 4 + * (the horizontal edge connector) will disable slot 3 entirely. + * + * Misconfigurations can be detected through the FPGA via the slot + * resistors to determine card presence. Hotplug remains unsupported. + */ +static unsigned int slot4en __devinitdata; + +char *__devinit pcibios_setup(char *str) +{ + if (strcmp(str, "slot4en") == 0) { + slot4en = 1; + return NULL; + } + + return str; +} + +static int __init sdk7786_pci_init(void) +{ + u16 data = fpga_read_reg(PCIECR); + + /* + * Enable slot #4 if it's been specified on the command line. + * + * Optionally reroute if slot #4 has a card present while slot #3 + * does not, regardless of command line value. + * + * Card presence is logically inverted. + */ + slot4en ?: (!(data & PCIECR_PRST4) && (data & PCIECR_PRST3)); + if (slot4en) { + pr_info("Activating PCIe slot#4 (disabling slot#3)\n"); + + data &= ~PCIECR_PCIEMUX1; + fpga_write_reg(data, PCIECR); + + /* Warn about forced rerouting if slot#3 is occupied */ + if ((data & PCIECR_PRST3) == 0) { + pr_warning("Unreachable card detected in slot#3\n"); + return -EBUSY; + } + } else + pr_info("PCIe slot#4 disabled\n"); + + return 0; +} +postcore_initcall(sdk7786_pci_init); diff --git a/arch/sh/drivers/pci/pci.c b/arch/sh/drivers/pci/pci.c index af4191b..60ee09a 100644 --- a/arch/sh/drivers/pci/pci.c +++ b/arch/sh/drivers/pci/pci.c @@ -268,7 +268,7 @@ void __init pcibios_update_irq(struct pci_dev *dev, int irq) pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); } -char * __devinit pcibios_setup(char *str) +char * __devinit __weak pcibios_setup(char *str) { return str; } diff --git a/arch/sh/include/mach-sdk7786/mach/fpga.h b/arch/sh/include/mach-sdk7786/mach/fpga.h index 416b621..8cc7841 100644 --- a/arch/sh/include/mach-sdk7786/mach/fpga.h +++ b/arch/sh/include/mach-sdk7786/mach/fpga.h @@ -31,7 +31,16 @@ #define EXTASR 0x110 #define SPCAR 0x120 #define INTMSR 0x130 + #define PCIECR 0x140 +#define PCIECR_PCIEMUX1 BIT(15) +#define PCIECR_PCIEMUX0 BIT(14) +#define PCIECR_PRST4 BIT(12) /* slot 4 card present */ +#define PCIECR_PRST3 BIT(11) /* slot 3 card present */ +#define PCIECR_PRST2 BIT(10) /* slot 2 card present */ +#define PCIECR_PRST1 BIT(9) /* slot 1 card present */ +#define PCIECR_CLKEN BIT(4) + #define FAER 0x150 #define USRGPIR 0x160 /* 0x170 reserved */ -- cgit v1.1 From b6b77b2d5ffd2f8ee74fcc27661f7f4962c34705 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Thu, 14 Oct 2010 08:44:55 +0900 Subject: sh: pci: Support secondary FPGA-driven PCIe clocks on SDK7786. The SDK7786 FPGA has secondary control over the PCIe clocks, specifically relating to the slots and oscillator. This ties the FPGA clocks in to the clock framework and balances the refcounting similar to how the primary on-chip clocks are managed. While the on-chip clocks are per-port, the FPGA clock enable/disable is global for the entire block. Signed-off-by: Paul Mundt --- arch/sh/boards/mach-sdk7786/setup.c | 54 +++++++++++++++++++++++++++++++- arch/sh/drivers/pci/fixups-sdk7786.c | 1 - arch/sh/drivers/pci/pcie-sh7786.c | 23 ++++++++++++-- arch/sh/include/mach-sdk7786/mach/fpga.h | 2 +- 4 files changed, 75 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/sh/boards/mach-sdk7786/setup.c b/arch/sh/boards/mach-sdk7786/setup.c index 2ec1ea5..7e0c4e3 100644 --- a/arch/sh/boards/mach-sdk7786/setup.c +++ b/arch/sh/boards/mach-sdk7786/setup.c @@ -20,6 +20,8 @@ #include #include #include +#include +#include #include #include @@ -140,6 +142,45 @@ static int sdk7786_mode_pins(void) return fpga_read_reg(MODSWR); } +/* + * FPGA-driven PCIe clocks + * + * Historically these include the oscillator, clock B (slots 2/3/4) and + * clock A (slot 1 and the CPU clock). Newer revs of the PCB shove + * everything under a single PCIe clocks enable bit that happens to map + * to the same bit position as the oscillator bit for earlier FPGA + * versions. + * + * Given that the legacy clocks have the side-effect of shutting the CPU + * off through the FPGA along with the PCI slots, we simply leave them in + * their initial state and don't bother registering them with the clock + * framework. + */ +static int sdk7786_pcie_clk_enable(struct clk *clk) +{ + fpga_write_reg(fpga_read_reg(PCIECR) | PCIECR_CLKEN, PCIECR); + return 0; +} + +static void sdk7786_pcie_clk_disable(struct clk *clk) +{ + fpga_write_reg(fpga_read_reg(PCIECR) & ~PCIECR_CLKEN, PCIECR); +} + +static struct clk_ops sdk7786_pcie_clk_ops = { + .enable = sdk7786_pcie_clk_enable, + .disable = sdk7786_pcie_clk_disable, +}; + +static struct clk sdk7786_pcie_clk = { + .ops = &sdk7786_pcie_clk_ops, +}; + +static struct clk_lookup sdk7786_pcie_cl = { + .con_id = "pcie_plat_clk", + .clk = &sdk7786_pcie_clk, +}; + static int sdk7786_clk_init(void) { struct clk *clk; @@ -158,7 +199,18 @@ static int sdk7786_clk_init(void) ret = clk_set_rate(clk, 33333333); clk_put(clk); - return ret; + /* + * Setup the FPGA clocks. + */ + ret = clk_register(&sdk7786_pcie_clk); + if (unlikely(ret)) { + pr_err("FPGA clock registration failed\n"); + return ret; + } + + clkdev_add(&sdk7786_pcie_cl); + + return 0; } static void sdk7786_restart(char *cmd) diff --git a/arch/sh/drivers/pci/fixups-sdk7786.c b/arch/sh/drivers/pci/fixups-sdk7786.c index 058a65a..0e18ee3 100644 --- a/arch/sh/drivers/pci/fixups-sdk7786.c +++ b/arch/sh/drivers/pci/fixups-sdk7786.c @@ -10,7 +10,6 @@ #define pr_fmt(fmt) "PCI: " fmt #include -#include #include #include #include diff --git a/arch/sh/drivers/pci/pcie-sh7786.c b/arch/sh/drivers/pci/pcie-sh7786.c index 8ec4af1..ae0b2c9 100644 --- a/arch/sh/drivers/pci/pcie-sh7786.c +++ b/arch/sh/drivers/pci/pcie-sh7786.c @@ -17,7 +17,6 @@ #include #include "pcie-sh7786.h" #include -#include struct sh7786_pcie_port { struct pci_channel *hose; @@ -510,6 +509,7 @@ static struct sh7786_pcie_hwops sh7786_65nm_pcie_hwops __initdata = { static int __init sh7786_pcie_init(void) { + struct clk *platclk; int ret = 0, i; printk(KERN_NOTICE "PCI: Starting initialization.\n"); @@ -527,6 +527,22 @@ static int __init sh7786_pcie_init(void) if (unlikely(!sh7786_pcie_ports)) return -ENOMEM; + /* + * Fetch any optional platform clock associated with this block. + * + * This is a rather nasty hack for boards with spec-mocking FPGAs + * that have a secondary set of clocks outside of the on-chip + * ones that need to be accounted for before there is any chance + * of touching the existing MSTP bits or CPG clocks. + */ + platclk = clk_get(NULL, "pcie_plat_clk"); + if (IS_ERR(platclk)) { + /* Sane hardware should probably get a WARN_ON.. */ + platclk = NULL; + } + + clk_enable(platclk); + printk(KERN_NOTICE "PCI: probing %d ports.\n", nr_ports); for (i = 0; i < nr_ports; i++) { @@ -539,8 +555,11 @@ static int __init sh7786_pcie_init(void) ret |= sh7786_pcie_hwops->port_init_hw(port); } - if (unlikely(ret)) + if (unlikely(ret)) { + clk_disable(platclk); + clk_put(platclk); return ret; + } return 0; } diff --git a/arch/sh/include/mach-sdk7786/mach/fpga.h b/arch/sh/include/mach-sdk7786/mach/fpga.h index 8cc7841..b7d9369 100644 --- a/arch/sh/include/mach-sdk7786/mach/fpga.h +++ b/arch/sh/include/mach-sdk7786/mach/fpga.h @@ -39,7 +39,7 @@ #define PCIECR_PRST3 BIT(11) /* slot 3 card present */ #define PCIECR_PRST2 BIT(10) /* slot 2 card present */ #define PCIECR_PRST1 BIT(9) /* slot 1 card present */ -#define PCIECR_CLKEN BIT(4) +#define PCIECR_CLKEN BIT(4) /* oscillator enable */ #define FAER 0x150 #define USRGPIR 0x160 -- cgit v1.1 From caf96194c05cd97ce96546fbcb1f35ec06aaaac7 Mon Sep 17 00:00:00 2001 From: Kyle McMartin Date: Wed, 13 Oct 2010 20:35:56 -0400 Subject: parisc: add prlimit64 syscall Signed-off-by: Kyle McMartin --- arch/parisc/include/asm/unistd.h | 3 ++- arch/parisc/kernel/syscall_table.S | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/parisc/include/asm/unistd.h b/arch/parisc/include/asm/unistd.h index 1ce7d28..3eb82c2a 100644 --- a/arch/parisc/include/asm/unistd.h +++ b/arch/parisc/include/asm/unistd.h @@ -813,8 +813,9 @@ #define __NR_perf_event_open (__NR_Linux + 318) #define __NR_recvmmsg (__NR_Linux + 319) #define __NR_accept4 (__NR_Linux + 320) +#define __NR_prlimit64 (__NR_Linux + 321) -#define __NR_Linux_syscalls (__NR_accept4 + 1) +#define __NR_Linux_syscalls (__NR_prlimit64 + 1) #define __IGNORE_select /* newselect */ diff --git a/arch/parisc/kernel/syscall_table.S b/arch/parisc/kernel/syscall_table.S index 3d52c97..74867df 100644 --- a/arch/parisc/kernel/syscall_table.S +++ b/arch/parisc/kernel/syscall_table.S @@ -419,6 +419,7 @@ ENTRY_SAME(perf_event_open) ENTRY_COMP(recvmmsg) ENTRY_SAME(accept4) /* 320 */ + ENTRY_SAME(prlimit64) /* Nothing yet */ -- cgit v1.1 From 03f1a17cd5c69deccd3cfe1b954b9426d7a686e3 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Wed, 13 Oct 2010 21:00:23 -0700 Subject: x86/vsmp: Eliminate kconfig dependency warning Fix kconfig dependency warning to satisfy dependencies: warning: (X86_VSMP && X86_64 && PCI && X86_EXTENDED_PLATFORM || XEN && PARAVIRT_GUEST && (X86_64 || X86_32 && X86_PAE && !X86_VISWS) && X86_CMPXCHG && X86_TSC || KVM_CLOCK && PARAVIRT_GUEST || KVM_GUEST && PARAVIRT_GUEST || LGUEST_GUEST && PARAVIRT_GUEST && X86_32) selects PARAVIRT which has unmet direct dependencies (PARAVIRT_GUEST) Signed-off-by: Randy Dunlap Cc: Ravikiran Thirumalai LKML-Reference: <20101013210023.9a033222.randy.dunlap@oracle.com> Signed-off-by: Ingo Molnar --- arch/x86/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index cea0cd9..64e817e 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -372,6 +372,7 @@ endif config X86_VSMP bool "ScaleMP vSMP" + select PARAVIRT_GUEST select PARAVIRT depends on X86_64 && PCI depends on X86_EXTENDED_PLATFORM -- cgit v1.1 From ba20085c20f1c9e8af546dea6ad0efa421bdef32 Mon Sep 17 00:00:00 2001 From: Kyle McMartin Date: Wed, 13 Oct 2010 21:00:55 -0400 Subject: parisc: lay groundwork for killing __do_IRQ Use proper accessors and handlers for generic irq cleanups. We just call back into __do_IRQ through desc->handler now, and remove the explicit calls. Signed-off-by: Kyle McMartin --- arch/parisc/include/asm/irq.h | 3 +++ arch/parisc/kernel/irq.c | 26 ++++++++++++++++---------- 2 files changed, 19 insertions(+), 10 deletions(-) (limited to 'arch') diff --git a/arch/parisc/include/asm/irq.h b/arch/parisc/include/asm/irq.h index dfa26b6..47041d4 100644 --- a/arch/parisc/include/asm/irq.h +++ b/arch/parisc/include/asm/irq.h @@ -32,6 +32,9 @@ static __inline__ int irq_canonicalize(int irq) } struct irq_chip; +struct irq_desc; + +extern void parisc_do_IRQ(unsigned int irq, struct irq_desc *desc); /* * Some useful "we don't have to do anything here" handlers. Should diff --git a/arch/parisc/kernel/irq.c b/arch/parisc/kernel/irq.c index efbcee5..272c29a 100644 --- a/arch/parisc/kernel/irq.c +++ b/arch/parisc/kernel/irq.c @@ -151,7 +151,7 @@ static struct irq_chip cpu_interrupt_type = { .enable = cpu_enable_irq, .disable = cpu_disable_irq, .ack = cpu_ack_irq, - .end = cpu_end_irq, + .eoi = cpu_end_irq, #ifdef CONFIG_SMP .set_affinity = cpu_set_affinity_irq, #endif @@ -247,10 +247,11 @@ int cpu_claim_irq(unsigned int irq, struct irq_chip *type, void *data) if (irq_desc[irq].chip != &cpu_interrupt_type) return -EBUSY; + /* for iosapic interrupts */ if (type) { - irq_desc[irq].chip = type; - irq_desc[irq].chip_data = data; - cpu_interrupt_type.enable(irq); + set_irq_chip_and_handler(irq, type, parisc_do_IRQ); + set_irq_chip_data(irq, data); + cpu_enable_irq(irq); } return 0; } @@ -368,7 +369,7 @@ void do_cpu_irq_mask(struct pt_regs *regs) goto set_out; } #endif - __do_IRQ(irq); + generic_handle_irq(irq); out: irq_exit(); @@ -398,14 +399,14 @@ static void claim_cpu_irqs(void) { int i; for (i = CPU_IRQ_BASE; i <= CPU_IRQ_MAX; i++) { - irq_desc[i].chip = &cpu_interrupt_type; + set_irq_chip_and_handler(i, &cpu_interrupt_type, parisc_do_IRQ); } - irq_desc[TIMER_IRQ].action = &timer_action; - irq_desc[TIMER_IRQ].status = IRQ_PER_CPU; + set_irq_handler(TIMER_IRQ, handle_percpu_irq); + setup_irq(TIMER_IRQ, &timer_action); #ifdef CONFIG_SMP - irq_desc[IPI_IRQ].action = &ipi_action; - irq_desc[IPI_IRQ].status = IRQ_PER_CPU; + set_irq_handler(IPI_IRQ, handle_percpu_irq); + setup_irq(IPI_IRQ, &ipi_action); #endif } @@ -423,3 +424,8 @@ void __init init_IRQ(void) set_eiem(cpu_eiem); /* EIEM : enable all external intr */ } + +void parisc_do_IRQ(unsigned int irq, struct irq_desc *desc) +{ + __do_IRQ(irq); +} -- cgit v1.1 From 4d4f681dc43a06167763ec698f5de4f2b3119ad6 Mon Sep 17 00:00:00 2001 From: Kyle McMartin Date: Thu, 14 Oct 2010 00:12:23 -0400 Subject: parisc: convert cpu interrupts to proper flow handlers Only major change is renaming functions to match the conventions expected by the generic irq code. Signed-off-by: Kyle McMartin --- arch/parisc/include/asm/irq.h | 2 +- arch/parisc/kernel/irq.c | 25 +++++++++---------------- 2 files changed, 10 insertions(+), 17 deletions(-) (limited to 'arch') diff --git a/arch/parisc/include/asm/irq.h b/arch/parisc/include/asm/irq.h index 47041d4..3a9b249 100644 --- a/arch/parisc/include/asm/irq.h +++ b/arch/parisc/include/asm/irq.h @@ -43,7 +43,7 @@ extern void parisc_do_IRQ(unsigned int irq, struct irq_desc *desc); void no_ack_irq(unsigned int irq); void no_end_irq(unsigned int irq); void cpu_ack_irq(unsigned int irq); -void cpu_end_irq(unsigned int irq); +void cpu_eoi_irq(unsigned int irq); extern int txn_alloc_irq(unsigned int nbits); extern int txn_claim_irq(int); diff --git a/arch/parisc/kernel/irq.c b/arch/parisc/kernel/irq.c index 272c29a..13bfa97 100644 --- a/arch/parisc/kernel/irq.c +++ b/arch/parisc/kernel/irq.c @@ -52,7 +52,7 @@ static volatile unsigned long cpu_eiem = 0; */ static DEFINE_PER_CPU(unsigned long, local_ack_eiem) = ~0UL; -static void cpu_disable_irq(unsigned int irq) +static void cpu_mask_irq(unsigned int irq) { unsigned long eirr_bit = EIEM_MASK(irq); @@ -63,7 +63,7 @@ static void cpu_disable_irq(unsigned int irq) * then gets disabled */ } -static void cpu_enable_irq(unsigned int irq) +static void cpu_unmask_irq(unsigned int irq) { unsigned long eirr_bit = EIEM_MASK(irq); @@ -75,12 +75,6 @@ static void cpu_enable_irq(unsigned int irq) smp_send_all_nop(); } -static unsigned int cpu_startup_irq(unsigned int irq) -{ - cpu_enable_irq(irq); - return 0; -} - void no_ack_irq(unsigned int irq) { } void no_end_irq(unsigned int irq) { } @@ -99,7 +93,7 @@ void cpu_ack_irq(unsigned int irq) mtctl(mask, 23); } -void cpu_end_irq(unsigned int irq) +void cpu_eoi_irq(unsigned int irq) { unsigned long mask = EIEM_MASK(irq); int cpu = smp_processor_id(); @@ -146,12 +140,10 @@ static int cpu_set_affinity_irq(unsigned int irq, const struct cpumask *dest) static struct irq_chip cpu_interrupt_type = { .name = "CPU", - .startup = cpu_startup_irq, - .shutdown = cpu_disable_irq, - .enable = cpu_enable_irq, - .disable = cpu_disable_irq, + .mask = cpu_mask_irq, + .unmask = cpu_unmask_irq, .ack = cpu_ack_irq, - .eoi = cpu_end_irq, + .eoi = cpu_eoi_irq, #ifdef CONFIG_SMP .set_affinity = cpu_set_affinity_irq, #endif @@ -251,7 +243,7 @@ int cpu_claim_irq(unsigned int irq, struct irq_chip *type, void *data) if (type) { set_irq_chip_and_handler(irq, type, parisc_do_IRQ); set_irq_chip_data(irq, data); - cpu_enable_irq(irq); + cpu_unmask_irq(irq); } return 0; } @@ -399,7 +391,8 @@ static void claim_cpu_irqs(void) { int i; for (i = CPU_IRQ_BASE; i <= CPU_IRQ_MAX; i++) { - set_irq_chip_and_handler(i, &cpu_interrupt_type, parisc_do_IRQ); + set_irq_chip_and_handler(i, &cpu_interrupt_type, + handle_level_irq); } set_irq_handler(TIMER_IRQ, handle_percpu_irq); -- cgit v1.1 From f3d4605977f9f30993c670a85f75d8f3853144c5 Mon Sep 17 00:00:00 2001 From: Kyle McMartin Date: Thu, 14 Oct 2010 00:38:27 -0400 Subject: parisc: convert iosapic interrupts to proper flow handlers Shift the ->end call (cpu eoi) from __do_IRQ into our unmask handler. Also nuke some redundant code. Signed-off-by: Kyle McMartin --- arch/parisc/kernel/irq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/parisc/kernel/irq.c b/arch/parisc/kernel/irq.c index 13bfa97..e873eda 100644 --- a/arch/parisc/kernel/irq.c +++ b/arch/parisc/kernel/irq.c @@ -241,7 +241,7 @@ int cpu_claim_irq(unsigned int irq, struct irq_chip *type, void *data) /* for iosapic interrupts */ if (type) { - set_irq_chip_and_handler(irq, type, parisc_do_IRQ); + set_irq_chip_and_handler(irq, type, handle_level_irq); set_irq_chip_data(irq, data); cpu_unmask_irq(irq); } -- cgit v1.1 From 7da1272547ebe96982a42292dfc833457708f4da Mon Sep 17 00:00:00 2001 From: Kyle McMartin Date: Thu, 14 Oct 2010 01:02:23 -0400 Subject: parisc: kill __do_IRQ Signed-off-by: Kyle McMartin --- arch/parisc/Kconfig | 4 ++++ arch/parisc/include/asm/irq.h | 3 --- arch/parisc/kernel/irq.c | 4 ---- 3 files changed, 4 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig index 907417d..2cb6401 100644 --- a/arch/parisc/Kconfig +++ b/arch/parisc/Kconfig @@ -18,6 +18,7 @@ config PARISC select BUG select HAVE_PERF_EVENTS select GENERIC_ATOMIC64 if !64BIT + select GENERIC_HARDIRQS_NO__DO_IRQ help The PA-RISC microprocessor is designed by Hewlett-Packard and used in many of their workstations & servers (HP9000 700 and 800 series, @@ -84,6 +85,9 @@ config IRQ_PER_CPU bool default y +config GENERIC_HARDIRQS_NO__DO_IRQ + def_bool y + # unless you want to implement ACPI on PA-RISC ... ;-) config PM bool diff --git a/arch/parisc/include/asm/irq.h b/arch/parisc/include/asm/irq.h index 3a9b249..c67dccf 100644 --- a/arch/parisc/include/asm/irq.h +++ b/arch/parisc/include/asm/irq.h @@ -32,9 +32,6 @@ static __inline__ int irq_canonicalize(int irq) } struct irq_chip; -struct irq_desc; - -extern void parisc_do_IRQ(unsigned int irq, struct irq_desc *desc); /* * Some useful "we don't have to do anything here" handlers. Should diff --git a/arch/parisc/kernel/irq.c b/arch/parisc/kernel/irq.c index e873eda..5024f64 100644 --- a/arch/parisc/kernel/irq.c +++ b/arch/parisc/kernel/irq.c @@ -418,7 +418,3 @@ void __init init_IRQ(void) } -void parisc_do_IRQ(unsigned int irq, struct irq_desc *desc) -{ - __do_IRQ(irq); -} -- cgit v1.1 From c993487ec87ba6d9ea47b03dad562123d503f4a2 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 15 Oct 2010 02:09:00 +0900 Subject: sh: Provide a generic SRAM pool for tiny memories. This sets up a generic SRAM pool for CPUs and platform code to insert their otherwise unused memories into. A simple alloc/free interface is provided (lifed from avr32) for generic code. This only applies to tiny SRAMs that are otherwise unmanaged, and does not take in to account the more complex SRAMs sitting behind transfer engines, or that employ an I/D split. Signed-off-by: Paul Mundt --- arch/sh/include/asm/sram.h | 38 ++++++++++++++++++++++++++++++++++++++ arch/sh/mm/Kconfig | 4 ++++ arch/sh/mm/Makefile | 1 + arch/sh/mm/sram.c | 34 ++++++++++++++++++++++++++++++++++ 4 files changed, 77 insertions(+) create mode 100644 arch/sh/include/asm/sram.h create mode 100644 arch/sh/mm/sram.c (limited to 'arch') diff --git a/arch/sh/include/asm/sram.h b/arch/sh/include/asm/sram.h new file mode 100644 index 0000000..a2808ce --- /dev/null +++ b/arch/sh/include/asm/sram.h @@ -0,0 +1,38 @@ +#ifndef __ASM_SRAM_H +#define __ASM_SRAM_H + +#ifdef CONFIG_HAVE_SRAM_POOL + +#include +#include + +/* arch/sh/mm/sram.c */ +extern struct gen_pool *sram_pool; + +static inline unsigned long sram_alloc(size_t len) +{ + if (!sram_pool) + return 0UL; + + return gen_pool_alloc(sram_pool, len); +} + +static inline void sram_free(unsigned long addr, size_t len) +{ + return gen_pool_free(sram_pool, addr, len); +} + +#else + +static inline unsigned long sram_alloc(size_t len) +{ + return 0; +} + +static inline void sram_free(unsigned long addr, size_t len) +{ +} + +#endif /* CONFIG_HAVE_SRAM_POOL */ + +#endif /* __ASM_SRAM_H */ diff --git a/arch/sh/mm/Kconfig b/arch/sh/mm/Kconfig index 1445ca6..0937039 100644 --- a/arch/sh/mm/Kconfig +++ b/arch/sh/mm/Kconfig @@ -168,6 +168,10 @@ config IOREMAP_FIXED config UNCACHED_MAPPING bool +config HAVE_SRAM_POOL + bool + select GENERIC_ALLOCATOR + choice prompt "Kernel page size" default PAGE_SIZE_4KB diff --git a/arch/sh/mm/Makefile b/arch/sh/mm/Makefile index 939663c..ab89ea4 100644 --- a/arch/sh/mm/Makefile +++ b/arch/sh/mm/Makefile @@ -40,6 +40,7 @@ obj-$(CONFIG_PMB) += pmb.o obj-$(CONFIG_NUMA) += numa.o obj-$(CONFIG_IOREMAP_FIXED) += ioremap_fixed.o obj-$(CONFIG_UNCACHED_MAPPING) += uncached.o +obj-$(CONFIG_HAVE_SRAM_POOL) += sram.o # Special flags for fault_64.o. This puts restrictions on the number of # caller-save registers that the compiler can target when building this file. diff --git a/arch/sh/mm/sram.c b/arch/sh/mm/sram.c new file mode 100644 index 0000000..bc156ec --- /dev/null +++ b/arch/sh/mm/sram.c @@ -0,0 +1,34 @@ +/* + * SRAM pool for tiny memories not otherwise managed. + * + * Copyright (C) 2010 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include + +/* + * This provides a standard SRAM pool for tiny memories that can be + * added either by the CPU or the platform code. Typical SRAM sizes + * to be inserted in to the pool will generally be less than the page + * size, with anything more reasonably sized handled as a NUMA memory + * node. + */ +struct gen_pool *sram_pool; + +static int __init sram_pool_init(void) +{ + /* + * This is a global pool, we don't care about node locality. + */ + sram_pool = gen_pool_create(1, -1); + if (unlikely(!sram_pool)) + return -ENOMEM; + + return 0; +} +core_initcall(sram_pool_init); -- cgit v1.1 From d8d6b902b8a3b2c66151529694bb4a9a3555cf43 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 15 Oct 2010 02:13:04 +0900 Subject: sh: mach-sdk7786: Add support for the FPGA SRAM. This ties in the 2KiB of FPGA SRAM in to the generic SRAM pool. Signed-off-by: Paul Mundt --- arch/sh/boards/Kconfig | 1 + arch/sh/boards/mach-sdk7786/Makefile | 3 +- arch/sh/boards/mach-sdk7786/sram.c | 72 ++++++++++++++++++++++++++++++++ arch/sh/include/asm/sizes.h | 1 + arch/sh/include/mach-sdk7786/mach/fpga.h | 17 +++++++- 5 files changed, 92 insertions(+), 2 deletions(-) create mode 100644 arch/sh/boards/mach-sdk7786/sram.c (limited to 'arch') diff --git a/arch/sh/boards/Kconfig b/arch/sh/boards/Kconfig index bb2cb27..9c94711 100644 --- a/arch/sh/boards/Kconfig +++ b/arch/sh/boards/Kconfig @@ -156,6 +156,7 @@ config SH_SDK7786 select SYS_SUPPORTS_PCI select NO_IOPORT if !PCI select ARCH_WANT_OPTIONAL_GPIOLIB + select HAVE_SRAM_POOL help Select SDK7786 if configuring for a Renesas Technology Europe SH7786-65nm board. diff --git a/arch/sh/boards/mach-sdk7786/Makefile b/arch/sh/boards/mach-sdk7786/Makefile index d0f801b..23ff7d4 100644 --- a/arch/sh/boards/mach-sdk7786/Makefile +++ b/arch/sh/boards/mach-sdk7786/Makefile @@ -1,3 +1,4 @@ -obj-y := setup.o fpga.o irq.o +obj-y := fpga.o irq.o setup.o obj-$(CONFIG_GENERIC_GPIO) += gpio.o +obj-$(CONFIG_HAVE_SRAM_POOL) += sram.o diff --git a/arch/sh/boards/mach-sdk7786/sram.c b/arch/sh/boards/mach-sdk7786/sram.c new file mode 100644 index 0000000..c81c3ab --- /dev/null +++ b/arch/sh/boards/mach-sdk7786/sram.c @@ -0,0 +1,72 @@ +/* + * SDK7786 FPGA SRAM Support. + * + * Copyright (C) 2010 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include +#include +#include + +static int __init fpga_sram_init(void) +{ + unsigned long phys; + unsigned int area; + void __iomem *vaddr; + int ret; + u16 data; + + /* Enable FPGA SRAM */ + data = fpga_read_reg(LCLASR); + data |= LCLASR_FRAMEN; + fpga_write_reg(data, LCLASR); + + /* + * FPGA_SEL determines the area mapping + */ + area = (data & LCLASR_FPGA_SEL_MASK) >> LCLASR_FPGA_SEL_SHIFT; + if (unlikely(area == LCLASR_AREA_MASK)) { + pr_err("FPGA memory unmapped.\n"); + return -ENXIO; + } + + /* + * The memory itself occupies a 2KiB range at the top of the area + * immediately below the system registers. + */ + phys = (area << 26) + SZ_64M - SZ_4K; + + /* + * The FPGA SRAM resides in translatable physical space, so set + * up a mapping prior to inserting it in to the pool. + */ + vaddr = ioremap(phys, SZ_2K); + if (unlikely(!vaddr)) { + pr_err("Failed remapping FPGA memory.\n"); + return -ENXIO; + } + + pr_info("Adding %dKiB of FPGA memory at 0x%08lx-0x%08lx " + "(area %d) to pool.\n", + SZ_2K >> 10, phys, phys + SZ_2K - 1, area); + + ret = gen_pool_add(sram_pool, (unsigned long)vaddr, SZ_2K, -1); + if (unlikely(ret < 0)) { + pr_err("Failed adding memory\n"); + iounmap(vaddr); + return ret; + } + + return 0; +} +postcore_initcall(fpga_sram_init); diff --git a/arch/sh/include/asm/sizes.h b/arch/sh/include/asm/sizes.h index 3a1fb97..0b9fe2d 100644 --- a/arch/sh/include/asm/sizes.h +++ b/arch/sh/include/asm/sizes.h @@ -32,6 +32,7 @@ #define SZ_512 0x00000200 #define SZ_1K 0x00000400 +#define SZ_2K 0x00000800 #define SZ_4K 0x00001000 #define SZ_8K 0x00002000 #define SZ_16K 0x00004000 diff --git a/arch/sh/include/mach-sdk7786/mach/fpga.h b/arch/sh/include/mach-sdk7786/mach/fpga.h index b7d9369..40f0c2d 100644 --- a/arch/sh/include/mach-sdk7786/mach/fpga.h +++ b/arch/sh/include/mach-sdk7786/mach/fpga.h @@ -43,8 +43,23 @@ #define FAER 0x150 #define USRGPIR 0x160 + /* 0x170 reserved */ -#define LCLASR 0x180 + +#define LCLASR 0x180 +#define LCLASR_FRAMEN BIT(15) + +#define LCLASR_FPGA_SEL_SHIFT 12 +#define LCLASR_NAND_SEL_SHIFT 8 +#define LCLASR_NORB_SEL_SHIFT 4 +#define LCLASR_NORA_SEL_SHIFT 0 + +#define LCLASR_AREA_MASK 0x7 + +#define LCLASR_FPGA_SEL_MASK (LCLASR_AREA_MASK << LCLASR_FPGA_SEL_SHIFT) +#define LCLASR_NAND_SEL_MASK (LCLASR_AREA_MASK << LCLASR_NAND_SEL_SHIFT) +#define LCLASR_NORB_SEL_MASK (LCLASR_AREA_MASK << LCLASR_NORB_SEL_SHIFT) +#define LCLASR_NORA_SEL_MASK (LCLASR_AREA_MASK << LCLASR_NORA_SEL_SHIFT) #define SBCR 0x190 #define SCBR_I2CMEN BIT(0) /* FPGA I2C master enable */ -- cgit v1.1 From d929b6aeaacbe78cbfef4a80e3eed1bf0464d984 Mon Sep 17 00:00:00 2001 From: Chris Metcalf Date: Thu, 14 Oct 2010 14:34:33 -0400 Subject: arch/tile: Use With this change we now include into the "tile" version of the header. To take full advantage of the prototypes there, we also change our naming convention for "struct pt_regs *" syscalls so that, e.g., _sys_execve() is the "true" syscall entry, which sets the appropriate register to point to the pt_regs before calling sys_execve(). While doing this I realized I no longer needed the fork and vfork entry point stubs, since those functions aren't in the generic syscall ABI, so I removed them as well. Signed-off-by: Chris Metcalf --- arch/tile/include/asm/compat.h | 15 +++++++-- arch/tile/include/asm/syscalls.h | 73 ++++++++++------------------------------ arch/tile/kernel/compat.c | 6 ++++ arch/tile/kernel/compat_signal.c | 10 +++--- arch/tile/kernel/intvec_32.S | 23 +++++-------- arch/tile/kernel/process.c | 31 ++++++----------- arch/tile/kernel/signal.c | 6 ++-- arch/tile/kernel/sys.c | 9 +++++ arch/tile/mm/fault.c | 6 ++-- 9 files changed, 76 insertions(+), 103 deletions(-) (limited to 'arch') diff --git a/arch/tile/include/asm/compat.h b/arch/tile/include/asm/compat.h index 8b60ec8..c3ae570 100644 --- a/arch/tile/include/asm/compat.h +++ b/arch/tile/include/asm/compat.h @@ -216,15 +216,16 @@ struct compat_siginfo; struct compat_sigaltstack; long compat_sys_execve(const char __user *path, const compat_uptr_t __user *argv, - const compat_uptr_t __user *envp); + const compat_uptr_t __user *envp, struct pt_regs *); long compat_sys_rt_sigaction(int sig, struct compat_sigaction __user *act, struct compat_sigaction __user *oact, size_t sigsetsize); long compat_sys_rt_sigqueueinfo(int pid, int sig, struct compat_siginfo __user *uinfo); -long compat_sys_rt_sigreturn(void); +long compat_sys_rt_sigreturn(struct pt_regs *); long compat_sys_sigaltstack(const struct compat_sigaltstack __user *uss_ptr, - struct compat_sigaltstack __user *uoss_ptr); + struct compat_sigaltstack __user *uoss_ptr, + struct pt_regs *); long compat_sys_truncate64(char __user *filename, u32 dummy, u32 low, u32 high); long compat_sys_ftruncate64(unsigned int fd, u32 dummy, u32 low, u32 high); long compat_sys_pread64(unsigned int fd, char __user *ubuf, size_t count, @@ -255,4 +256,12 @@ long tile_compat_sys_ptrace(compat_long_t request, compat_long_t pid, /* Tilera Linux syscalls that don't have "compat" versions. */ #define compat_sys_flush_cache sys_flush_cache +/* These are the intvec_64.S trampolines. */ +long _compat_sys_execve(const char __user *path, + const compat_uptr_t __user *argv, + const compat_uptr_t __user *envp); +long _compat_sys_sigaltstack(const struct compat_sigaltstack __user *uss_ptr, + struct compat_sigaltstack __user *uoss_ptr); +long _compat_sys_rt_sigreturn(void); + #endif /* _ASM_TILE_COMPAT_H */ diff --git a/arch/tile/include/asm/syscalls.h b/arch/tile/include/asm/syscalls.h index ce99ffe..3b5507c 100644 --- a/arch/tile/include/asm/syscalls.h +++ b/arch/tile/include/asm/syscalls.h @@ -32,8 +32,9 @@ extern void *compat_sys_call_table[]; /* * Note that by convention, any syscall which requires the current - * register set takes an additional "struct pt_regs *" pointer; the - * sys_xxx() function just adds the pointer and tail-calls to _sys_xxx(). + * register set takes an additional "struct pt_regs *" pointer; a + * _sys_xxx() trampoline in intvec*.S just sets up the pointer and + * jumps to sys_xxx(). */ /* kernel/sys.c */ @@ -43,66 +44,17 @@ long sys32_fadvise64(int fd, u32 offset_lo, u32 offset_hi, int sys32_fadvise64_64(int fd, u32 offset_lo, u32 offset_hi, u32 len_lo, u32 len_hi, int advice); long sys_flush_cache(void); -long sys_mmap2(unsigned long addr, unsigned long len, - unsigned long prot, unsigned long flags, - unsigned long fd, unsigned long pgoff); -#ifdef __tilegx__ -long sys_mmap(unsigned long addr, unsigned long len, - unsigned long prot, unsigned long flags, - unsigned long fd, off_t pgoff); +#ifndef __tilegx__ /* No mmap() in the 32-bit kernel. */ +#define sys_mmap sys_mmap #endif -/* kernel/process.c */ -long sys_clone(unsigned long clone_flags, unsigned long newsp, - void __user *parent_tid, void __user *child_tid); -long _sys_clone(unsigned long clone_flags, unsigned long newsp, - void __user *parent_tid, void __user *child_tid, - struct pt_regs *regs); -long sys_fork(void); -long _sys_fork(struct pt_regs *regs); -long sys_vfork(void); -long _sys_vfork(struct pt_regs *regs); -long sys_execve(const char __user *filename, - const char __user *const __user *argv, - const char __user *const __user *envp); -long _sys_execve(const char __user *filename, - const char __user *const __user *argv, - const char __user *const __user *envp, struct pt_regs *regs); - -/* kernel/signal.c */ -long sys_sigaltstack(const stack_t __user *, stack_t __user *); -long _sys_sigaltstack(const stack_t __user *, stack_t __user *, - struct pt_regs *); -long sys_rt_sigreturn(void); -long _sys_rt_sigreturn(struct pt_regs *regs); - -/* platform-independent functions */ -long sys_rt_sigsuspend(sigset_t __user *unewset, size_t sigsetsize); -long sys_rt_sigaction(int sig, const struct sigaction __user *act, - struct sigaction __user *oact, size_t sigsetsize); - #ifndef __tilegx__ /* mm/fault.c */ -int sys_cmpxchg_badaddr(unsigned long address); -int _sys_cmpxchg_badaddr(unsigned long address, struct pt_regs *); +long sys_cmpxchg_badaddr(unsigned long address, struct pt_regs *); +long _sys_cmpxchg_badaddr(unsigned long address); #endif #ifdef CONFIG_COMPAT -long compat_sys_execve(const char __user *path, - const compat_uptr_t __user *argv, - const compat_uptr_t __user *envp); -long _compat_sys_execve(const char __user *path, - const compat_uptr_t __user *argv, - const compat_uptr_t __user *envp, - struct pt_regs *regs); -long compat_sys_sigaltstack(const struct compat_sigaltstack __user *uss_ptr, - struct compat_sigaltstack __user *uoss_ptr); -long _compat_sys_sigaltstack(const struct compat_sigaltstack __user *uss_ptr, - struct compat_sigaltstack __user *uoss_ptr, - struct pt_regs *regs); -long compat_sys_rt_sigreturn(void); -long _compat_sys_rt_sigreturn(struct pt_regs *regs); - /* These four are not defined for 64-bit, but serve as "compat" syscalls. */ long sys_fcntl64(unsigned int fd, unsigned int cmd, unsigned long arg); long sys_fstat64(unsigned long fd, struct stat64 __user *statbuf); @@ -110,4 +62,15 @@ long sys_truncate64(const char __user *path, loff_t length); long sys_ftruncate64(unsigned int fd, loff_t length); #endif +/* These are the intvec*.S trampolines. */ +long _sys_sigaltstack(const stack_t __user *, stack_t __user *); +long _sys_rt_sigreturn(void); +long _sys_clone(unsigned long clone_flags, unsigned long newsp, + void __user *parent_tid, void __user *child_tid); +long _sys_execve(const char __user *filename, + const char __user *const __user *argv, + const char __user *const __user *envp); + +#include + #endif /* _ASM_TILE_SYSCALLS_H */ diff --git a/arch/tile/kernel/compat.c b/arch/tile/kernel/compat.c index b1e06d0..5f24e54 100644 --- a/arch/tile/kernel/compat.c +++ b/arch/tile/kernel/compat.c @@ -157,6 +157,12 @@ long tile_compat_sys_msgrcv(int msqid, /* Pass full 64-bit values through ptrace. */ #define compat_sys_ptrace tile_compat_sys_ptrace +/* Call the trampolines to manage pt_regs where necessary. */ +#define compat_sys_execve _compat_sys_execve +#define compat_sys_sigaltstack _compat_sys_sigaltstack +#define compat_sys_rt_sigreturn _compat_sys_rt_sigreturn +#define sys_clone _sys_clone + /* * Note that we can't include here since the header * guard will defeat us; checks for __SYSCALL as well. diff --git a/arch/tile/kernel/compat_signal.c b/arch/tile/kernel/compat_signal.c index 9c710db..fb64b99 100644 --- a/arch/tile/kernel/compat_signal.c +++ b/arch/tile/kernel/compat_signal.c @@ -256,9 +256,9 @@ int copy_siginfo_from_user32(siginfo_t *to, struct compat_siginfo __user *from) return err; } -long _compat_sys_sigaltstack(const struct compat_sigaltstack __user *uss_ptr, - struct compat_sigaltstack __user *uoss_ptr, - struct pt_regs *regs) +long compat_sys_sigaltstack(const struct compat_sigaltstack __user *uss_ptr, + struct compat_sigaltstack __user *uoss_ptr, + struct pt_regs *regs) { stack_t uss, uoss; int ret; @@ -291,7 +291,7 @@ long _compat_sys_sigaltstack(const struct compat_sigaltstack __user *uss_ptr, return ret; } -long _compat_sys_rt_sigreturn(struct pt_regs *regs) +long compat_sys_rt_sigreturn(struct pt_regs *regs) { struct compat_rt_sigframe __user *frame = (struct compat_rt_sigframe __user *) compat_ptr(regs->sp); @@ -312,7 +312,7 @@ long _compat_sys_rt_sigreturn(struct pt_regs *regs) if (restore_sigcontext(regs, &frame->uc.uc_mcontext, &r0)) goto badframe; - if (_compat_sys_sigaltstack(&frame->uc.uc_stack, NULL, regs) != 0) + if (compat_sys_sigaltstack(&frame->uc.uc_stack, NULL, regs) != 0) goto badframe; return r0; diff --git a/arch/tile/kernel/intvec_32.S b/arch/tile/kernel/intvec_32.S index 8f58bdf..7c7e9ac 100644 --- a/arch/tile/kernel/intvec_32.S +++ b/arch/tile/kernel/intvec_32.S @@ -1524,28 +1524,23 @@ STD_ENTRY_LOCAL(bad_intr) /* Put address of pt_regs in reg and jump. */ #define PTREGS_SYSCALL(x, reg) \ - STD_ENTRY(x); \ + STD_ENTRY(_##x); \ { \ PTREGS_PTR(reg, PTREGS_OFFSET_BASE); \ - j _##x \ + j x \ }; \ - STD_ENDPROC(x) + STD_ENDPROC(_##x) PTREGS_SYSCALL(sys_execve, r3) PTREGS_SYSCALL(sys_sigaltstack, r2) PTREGS_SYSCALL(sys_rt_sigreturn, r0) +PTREGS_SYSCALL(sys_cmpxchg_badaddr, r1) -/* Save additional callee-saves to pt_regs, put address in reg and jump. */ -#define PTREGS_SYSCALL_ALL_REGS(x, reg) \ - STD_ENTRY(x); \ - push_extra_callee_saves reg; \ - j _##x; \ - STD_ENDPROC(x) - -PTREGS_SYSCALL_ALL_REGS(sys_fork, r0) -PTREGS_SYSCALL_ALL_REGS(sys_vfork, r0) -PTREGS_SYSCALL_ALL_REGS(sys_clone, r4) -PTREGS_SYSCALL_ALL_REGS(sys_cmpxchg_badaddr, r1) +/* Save additional callee-saves to pt_regs, put address in r4 and jump. */ +STD_ENTRY(_sys_clone) + push_extra_callee_saves r4 + j sys_clone + STD_ENDPROC(_sys_clone) /* * This entrypoint is taken for the cmpxchg and atomic_update fast diff --git a/arch/tile/kernel/process.c b/arch/tile/kernel/process.c index 84c2911..42ff73d 100644 --- a/arch/tile/kernel/process.c +++ b/arch/tile/kernel/process.c @@ -528,14 +528,9 @@ struct task_struct *__sched _switch_to(struct task_struct *prev, return __switch_to(prev, next, next_current_ksp0(next)); } -long _sys_fork(struct pt_regs *regs) -{ - return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL); -} - -long _sys_clone(unsigned long clone_flags, unsigned long newsp, - void __user *parent_tidptr, void __user *child_tidptr, - struct pt_regs *regs) +SYSCALL_DEFINE5(clone, unsigned long, clone_flags, unsigned long, newsp, + void __user *, parent_tidptr, void __user *, child_tidptr, + struct pt_regs *, regs) { if (!newsp) newsp = regs->sp; @@ -543,18 +538,13 @@ long _sys_clone(unsigned long clone_flags, unsigned long newsp, parent_tidptr, child_tidptr); } -long _sys_vfork(struct pt_regs *regs) -{ - return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, - regs, 0, NULL, NULL); -} - /* * sys_execve() executes a new program. */ -long _sys_execve(const char __user *path, - const char __user *const __user *argv, - const char __user *const __user *envp, struct pt_regs *regs) +SYSCALL_DEFINE4(execve, const char __user *, path, + const char __user *const __user *, argv, + const char __user *const __user *, envp, + struct pt_regs *, regs) { long error; char *filename; @@ -570,9 +560,10 @@ out: } #ifdef CONFIG_COMPAT -long _compat_sys_execve(const char __user *path, - const compat_uptr_t __user *argv, - const compat_uptr_t __user *envp, struct pt_regs *regs) +long compat_sys_execve(const char __user *path, + const compat_uptr_t __user *argv, + const compat_uptr_t __user *envp, + struct pt_regs *regs) { long error; char *filename; diff --git a/arch/tile/kernel/signal.c b/arch/tile/kernel/signal.c index ce183aa..fb28e85 100644 --- a/arch/tile/kernel/signal.c +++ b/arch/tile/kernel/signal.c @@ -41,8 +41,8 @@ #define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP))) -long _sys_sigaltstack(const stack_t __user *uss, - stack_t __user *uoss, struct pt_regs *regs) +SYSCALL_DEFINE3(sigaltstack, const stack_t __user *, uss, + stack_t __user *, uoss, struct pt_regs *, regs) { return do_sigaltstack(uss, uoss, regs->sp); } @@ -78,7 +78,7 @@ int restore_sigcontext(struct pt_regs *regs, } /* sigreturn() returns long since it restores r0 in the interrupted code. */ -long _sys_rt_sigreturn(struct pt_regs *regs) +SYSCALL_DEFINE1(rt_sigreturn, struct pt_regs *, regs) { struct rt_sigframe __user *frame = (struct rt_sigframe __user *)(regs->sp); diff --git a/arch/tile/kernel/sys.c b/arch/tile/kernel/sys.c index f0f87ea..7e76466 100644 --- a/arch/tile/kernel/sys.c +++ b/arch/tile/kernel/sys.c @@ -110,6 +110,15 @@ SYSCALL_DEFINE6(mmap, unsigned long, addr, unsigned long, len, #define sys_sync_file_range sys_sync_file_range2 #endif +/* Call the trampolines to manage pt_regs where necessary. */ +#define sys_execve _sys_execve +#define sys_sigaltstack _sys_sigaltstack +#define sys_rt_sigreturn _sys_rt_sigreturn +#define sys_clone _sys_clone +#ifndef __tilegx__ +#define sys_cmpxchg_badaddr _sys_cmpxchg_badaddr +#endif + /* * Note that we can't include here since the header * guard will defeat us; checks for __SYSCALL as well. diff --git a/arch/tile/mm/fault.c b/arch/tile/mm/fault.c index 704f3e8..94f579d 100644 --- a/arch/tile/mm/fault.c +++ b/arch/tile/mm/fault.c @@ -66,10 +66,10 @@ static noinline void force_sig_info_fault(int si_signo, int si_code, #ifndef __tilegx__ /* * Synthesize the fault a PL0 process would get by doing a word-load of - * an unaligned address or a high kernel address. Called indirectly - * from sys_cmpxchg() in kernel/intvec.S. + * an unaligned address or a high kernel address. */ -int _sys_cmpxchg_badaddr(unsigned long address, struct pt_regs *regs) +SYSCALL_DEFINE2(cmpxchg_badaddr, unsigned long, address, + struct pt_regs *, regs) { if (address >= PAGE_OFFSET) force_sig_info_fault(SIGSEGV, SEGV_MAPERR, address, -- cgit v1.1 From 5592840ba83c281b4df45345863b224bb290020c Mon Sep 17 00:00:00 2001 From: Chris Metcalf Date: Mon, 13 Sep 2010 08:50:09 -0400 Subject: arch/tile: use better "punctuation" for VMSPLIT_3_5G and friends Signed-off-by: Chris Metcalf --- arch/tile/Kconfig | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/tile/Kconfig b/arch/tile/Kconfig index 1eb308c..2361e3e 100644 --- a/arch/tile/Kconfig +++ b/arch/tile/Kconfig @@ -236,9 +236,9 @@ choice If you are not absolutely sure what you are doing, leave this option alone! - config VMSPLIT_375G + config VMSPLIT_3_75G bool "3.75G/0.25G user/kernel split (no kernel networking)" - config VMSPLIT_35G + config VMSPLIT_3_5G bool "3.5G/0.5G user/kernel split" config VMSPLIT_3G bool "3G/1G user/kernel split" @@ -252,8 +252,8 @@ endchoice config PAGE_OFFSET hex - default 0xF0000000 if VMSPLIT_375G - default 0xE0000000 if VMSPLIT_35G + default 0xF0000000 if VMSPLIT_3_75G + default 0xE0000000 if VMSPLIT_3_5G default 0xB0000000 if VMSPLIT_3G_OPT default 0x80000000 if VMSPLIT_2G default 0x40000000 if VMSPLIT_1G -- cgit v1.1 From d6f0f22c3c409f9ed88e64f881f8308730be76f0 Mon Sep 17 00:00:00 2001 From: Chris Metcalf Date: Thu, 14 Oct 2010 14:42:58 -0400 Subject: arch/tile: update some comments to clarify register usage. Signed-off-by: Chris Metcalf --- arch/tile/kernel/intvec_32.S | 2 ++ arch/tile/kernel/process.c | 7 ++++--- 2 files changed, 6 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/tile/kernel/intvec_32.S b/arch/tile/kernel/intvec_32.S index 7c7e9ac..c62c2f4 100644 --- a/arch/tile/kernel/intvec_32.S +++ b/arch/tile/kernel/intvec_32.S @@ -1553,6 +1553,8 @@ STD_ENTRY(_sys_clone) * to be available to it on entry. It does not modify any callee-save * registers (including "lr"). It does not check what PL it is being * called at, so you'd better not call it other than at PL0. + * The wrapper assumes it only clobbers r20-r29, so if + * it ever is necessary to use more registers, be aware. * * It does not use the stack, but since it might be re-interrupted by * a page fault which would assume the stack was valid, it does diff --git a/arch/tile/kernel/process.c b/arch/tile/kernel/process.c index 42ff73d..221f12b 100644 --- a/arch/tile/kernel/process.c +++ b/arch/tile/kernel/process.c @@ -214,9 +214,10 @@ int copy_thread(unsigned long clone_flags, unsigned long sp, /* * Copy the callee-saved registers from the passed pt_regs struct * into the context-switch callee-saved registers area. - * We have to restore the callee-saved registers since we may - * be cloning a userspace task with userspace register state, - * and we won't be unwinding the same kernel frames to restore them. + * This way when we start the interrupt-return sequence, the + * callee-save registers will be correctly in registers, which + * is how we assume the compiler leaves them as we start doing + * the normal return-from-interrupt path after calling C code. * Zero out the C ABI save area to mark the top of the stack. */ ksp = (unsigned long) childregs; -- cgit v1.1 From 77d233036ea886398770f208aa22235acf0d011c Mon Sep 17 00:00:00 2001 From: Chris Metcalf Date: Thu, 14 Oct 2010 14:47:35 -0400 Subject: arch/tile: Add a warning if we try to allocate too much vmalloc memory. Signed-off-by: Chris Metcalf --- arch/tile/kernel/setup.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/tile/kernel/setup.c b/arch/tile/kernel/setup.c index e7d54c7..c1a697e 100644 --- a/arch/tile/kernel/setup.c +++ b/arch/tile/kernel/setup.c @@ -1334,6 +1334,10 @@ static void __init pcpu_fc_populate_pte(unsigned long addr) pte_t *pte; BUG_ON(pgd_addr_invalid(addr)); + if (addr < VMALLOC_START || addr >= VMALLOC_END) + panic("PCPU addr %#lx outside vmalloc range %#lx..%#lx;" + " try increasing CONFIG_VMALLOC_RESERVE\n", + addr, VMALLOC_START, VMALLOC_END); pgd = swapper_pg_dir + pgd_index(addr); pud = pud_offset(pgd, addr); -- cgit v1.1 From bbacff94d0c38163ef01361de006797c92e69e58 Mon Sep 17 00:00:00 2001 From: Chris Metcalf Date: Thu, 14 Oct 2010 15:09:02 -0400 Subject: arch/tile: provide a definition of MAP_STACK It's convenient for userspace (in particular, glibc) to find a definition of MAP_STACK. We use MAP_GROWSDOWN as an alias since that's appropriate for the main stack, and since our current allocation of mmap flags bits is running a bit short otherwise. Signed-off-by: Chris Metcalf --- arch/tile/include/asm/mman.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/tile/include/asm/mman.h b/arch/tile/include/asm/mman.h index 4c6811e..81b8fc3 100644 --- a/arch/tile/include/asm/mman.h +++ b/arch/tile/include/asm/mman.h @@ -23,6 +23,7 @@ #define MAP_POPULATE 0x0040 /* populate (prefault) pagetables */ #define MAP_NONBLOCK 0x0080 /* do not block on IO */ #define MAP_GROWSDOWN 0x0100 /* stack-like segment */ +#define MAP_STACK MAP_GROWSDOWN /* provide convenience alias */ #define MAP_LOCKED 0x0200 /* pages are locked */ #define MAP_NORESERVE 0x0400 /* don't check for reservations */ #define MAP_DENYWRITE 0x0800 /* ETXTBSY */ -- cgit v1.1 From 13c9d5a6309763a494f7c3ed5aa45fb473985fd7 Mon Sep 17 00:00:00 2001 From: Chris Metcalf Date: Thu, 14 Oct 2010 15:12:55 -0400 Subject: arch/tile: properly export __mb_incoherent for modules Signed-off-by: Chris Metcalf --- arch/tile/include/asm/system.h | 5 ++++- arch/tile/lib/exports.c | 3 +++ 2 files changed, 7 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/tile/include/asm/system.h b/arch/tile/include/asm/system.h index f749be3..96779c8 100644 --- a/arch/tile/include/asm/system.h +++ b/arch/tile/include/asm/system.h @@ -89,6 +89,10 @@ #define get_cycles_low() __insn_mfspr(SPR_CYCLE) /* just get all 64 bits */ #endif +#if !CHIP_HAS_MF_WAITS_FOR_VICTIMS() +int __mb_incoherent(void); /* Helper routine for mb_incoherent(). */ +#endif + /* Fence to guarantee visibility of stores to incoherent memory. */ static inline void mb_incoherent(void) @@ -97,7 +101,6 @@ mb_incoherent(void) #if !CHIP_HAS_MF_WAITS_FOR_VICTIMS() { - int __mb_incoherent(void); #if CHIP_HAS_TILE_WRITE_PENDING() const unsigned long WRITE_TIMEOUT_CYCLES = 400; unsigned long start = get_cycles_low(); diff --git a/arch/tile/lib/exports.c b/arch/tile/lib/exports.c index ce5dbf5..1509c55 100644 --- a/arch/tile/lib/exports.c +++ b/arch/tile/lib/exports.c @@ -45,6 +45,9 @@ EXPORT_SYMBOL(__copy_from_user_zeroing); EXPORT_SYMBOL(__copy_in_user_inatomic); #endif +/* arch/tile/lib/mb_incoherent.S */ +EXPORT_SYMBOL(__mb_incoherent); + /* hypervisor glue */ #include EXPORT_SYMBOL(hv_dev_open); -- cgit v1.1 From a4dbc5ee52e8741522a2f87067b80116c6c7a934 Mon Sep 17 00:00:00 2001 From: Chris Metcalf Date: Thu, 14 Oct 2010 15:14:29 -0400 Subject: arch/tile: change lower bound on syscall error return to -4095 Previously we were using -1023, which is fine for normal syscall error returns, but the common value in use for other platforms is -4095, and one Tilera-specific driver does use values in the -1100 range, so tickled this bug. Signed-off-by: Chris Metcalf --- arch/tile/kernel/intvec_32.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/tile/kernel/intvec_32.S b/arch/tile/kernel/intvec_32.S index c62c2f4..f87c5c0 100644 --- a/arch/tile/kernel/intvec_32.S +++ b/arch/tile/kernel/intvec_32.S @@ -1020,7 +1020,7 @@ STD_ENTRY(interrupt_return) /* Set r1 to errno if we are returning an error, otherwise zero. */ { - moveli r29, 1024 + moveli r29, 4096 sub r1, zero, r0 } slt_u r29, r1, r29 -- cgit v1.1 From 45123f7e74e004848da765f3182cd401a38d354d Mon Sep 17 00:00:00 2001 From: Chris Metcalf Date: Thu, 14 Oct 2010 15:16:59 -0400 Subject: arch/tile: various top-level Makefile cleanups Avoid a compile failure if CONFIG_DEBUG_EXTRA_FLAGS is empty (""); provide an "install" hook as well as a matching archhelp target; and some minor whitespace cleanup. Signed-off-by: Chris Metcalf --- arch/tile/Makefile | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/tile/Makefile b/arch/tile/Makefile index fd8f6bb..a700f7f 100644 --- a/arch/tile/Makefile +++ b/arch/tile/Makefile @@ -26,8 +26,9 @@ $(error Set TILERA_ROOT or CROSS_COMPILE when building $(ARCH) on $(HOST_ARCH)) endif endif - +ifneq ($(CONFIG_DEBUG_EXTRA_FLAGS),"") KBUILD_CFLAGS += $(CONFIG_DEBUG_EXTRA_FLAGS) +endif LIBGCC_PATH := $(shell $(CC) $(KBUILD_CFLAGS) -print-libgcc-file-name) @@ -49,6 +50,18 @@ head-y := arch/tile/kernel/head_$(BITS).o libs-y += arch/tile/lib/ libs-y += $(LIBGCC_PATH) - # See arch/tile/Kbuild for content of core part of the kernel core-y += arch/tile/ + +ifdef TILERA_ROOT +INSTALL_PATH ?= $(TILERA_ROOT)/tile/boot +endif + +install: + install -D -m 755 vmlinux $(INSTALL_PATH)/vmlinux-$(KERNELRELEASE) + install -D -m 644 .config $(INSTALL_PATH)/config-$(KERNELRELEASE) + install -D -m 644 System.map $(INSTALL_PATH)/System.map-$(KERNELRELEASE) + +define archhelp + echo ' install - install kernel into $(INSTALL_PATH)' +endef -- cgit v1.1 From dabe98c972091818762e02841ab1f982e573e7d0 Mon Sep 17 00:00:00 2001 From: Chris Metcalf Date: Thu, 14 Oct 2010 15:19:04 -0400 Subject: arch/tile: prevent corrupt top frame from causing backtracer runaway The backtracer will normally cut itself off after 100 frames anyway, but it's messy. With this change we notice that the frame being reported is the same as the last one, and cut off the dump with a message similar to what gdb displays in the same circumstance. Signed-off-by: Chris Metcalf --- arch/tile/kernel/stack.c | 35 ++++++++++++++++++++++------------- 1 file changed, 22 insertions(+), 13 deletions(-) (limited to 'arch') diff --git a/arch/tile/kernel/stack.c b/arch/tile/kernel/stack.c index ea2e0ce..0d54106b 100644 --- a/arch/tile/kernel/stack.c +++ b/arch/tile/kernel/stack.c @@ -30,6 +30,10 @@ #include #include +#define KBT_ONGOING 0 /* Backtrace still ongoing */ +#define KBT_DONE 1 /* Backtrace cleanly completed */ +#define KBT_RUNNING 2 /* Can't run backtrace on a running task */ +#define KBT_LOOP 3 /* Backtrace entered a loop */ /* Is address on the specified kernel stack? */ static int in_kernel_stack(struct KBacktraceIterator *kbt, VirtualAddress sp) @@ -207,11 +211,11 @@ static int KBacktraceIterator_next_item_inclusive( for (;;) { do { if (!KBacktraceIterator_is_sigreturn(kbt)) - return 1; + return KBT_ONGOING; } while (backtrace_next(&kbt->it)); if (!KBacktraceIterator_restart(kbt)) - return 0; + return KBT_DONE; } } @@ -264,7 +268,7 @@ void KBacktraceIterator_init(struct KBacktraceIterator *kbt, kbt->pgtable = NULL; kbt->verbose = 0; /* override in caller if desired */ kbt->profile = 0; /* override in caller if desired */ - kbt->end = 0; + kbt->end = KBT_ONGOING; kbt->new_context = 0; if (is_current) { HV_PhysAddr pgdir_pa = hv_inquire_context().page_table; @@ -290,7 +294,7 @@ void KBacktraceIterator_init(struct KBacktraceIterator *kbt, if (regs == NULL) { if (is_current || t->state == TASK_RUNNING) { /* Can't do this; we need registers */ - kbt->end = 1; + kbt->end = KBT_RUNNING; return; } pc = get_switch_to_pc(); @@ -305,26 +309,29 @@ void KBacktraceIterator_init(struct KBacktraceIterator *kbt, } backtrace_init(&kbt->it, read_memory_func, kbt, pc, lr, sp, r52); - kbt->end = !KBacktraceIterator_next_item_inclusive(kbt); + kbt->end = KBacktraceIterator_next_item_inclusive(kbt); } EXPORT_SYMBOL(KBacktraceIterator_init); int KBacktraceIterator_end(struct KBacktraceIterator *kbt) { - return kbt->end; + return kbt->end != KBT_ONGOING; } EXPORT_SYMBOL(KBacktraceIterator_end); void KBacktraceIterator_next(struct KBacktraceIterator *kbt) { + VirtualAddress old_pc = kbt->it.pc, old_sp = kbt->it.sp; kbt->new_context = 0; - if (!backtrace_next(&kbt->it) && - !KBacktraceIterator_restart(kbt)) { - kbt->end = 1; - return; - } - - kbt->end = !KBacktraceIterator_next_item_inclusive(kbt); + if (!backtrace_next(&kbt->it) && !KBacktraceIterator_restart(kbt)) { + kbt->end = KBT_DONE; + return; + } + kbt->end = KBacktraceIterator_next_item_inclusive(kbt); + if (old_pc == kbt->it.pc && old_sp == kbt->it.sp) { + /* Trapped in a loop; give up. */ + kbt->end = KBT_LOOP; + } } EXPORT_SYMBOL(KBacktraceIterator_next); @@ -387,6 +394,8 @@ void tile_show_stack(struct KBacktraceIterator *kbt, int headers) break; } } + if (kbt->end == KBT_LOOP) + pr_err("Stack dump stopped; next frame identical to this one\n"); if (headers) pr_err("Stack dump complete\n"); } -- cgit v1.1 From 2c184cd393d1410bb43ac656a6480849fe886b1d Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Thu, 7 Oct 2010 09:36:43 +0000 Subject: powerpc/85xx: add DIU support to the Freecale P1022DS reference board The Freescale P1022DS has an on-chip video controller called the DIU, and a driver for this device already exists. Update the platform file for the P1022DS reference board to enable the driver, and update the defconfig for Freescale MPC85xx boards to add the driver. [Edited to resolve header add/add conflict and drop #define DEBUG. -- broonie] Signed-off-by: Timur Tabi Acked-by: Kumar Gala Signed-off-by: Mark Brown --- arch/powerpc/configs/mpc85xx_defconfig | 3 + arch/powerpc/configs/mpc85xx_smp_defconfig | 3 + arch/powerpc/platforms/85xx/p1022_ds.c | 212 ++++++++++++++++++++++++++++- 3 files changed, 216 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig index c3b113b..3aeb594 100644 --- a/arch/powerpc/configs/mpc85xx_defconfig +++ b/arch/powerpc/configs/mpc85xx_defconfig @@ -124,6 +124,9 @@ CONFIG_I2C_CPM=m CONFIG_I2C_MPC=y # CONFIG_HWMON is not set CONFIG_VIDEO_OUTPUT_CONTROL=y +CONFIG_FB=y +CONFIG_FB_FSL_DIU=y +# CONFIG_VGA_CONSOLE is not set CONFIG_SOUND=y CONFIG_SND=y # CONFIG_SND_SUPPORT_OLD_API is not set diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig index a075da2..d62c801 100644 --- a/arch/powerpc/configs/mpc85xx_smp_defconfig +++ b/arch/powerpc/configs/mpc85xx_smp_defconfig @@ -126,6 +126,9 @@ CONFIG_I2C_CPM=m CONFIG_I2C_MPC=y # CONFIG_HWMON is not set CONFIG_VIDEO_OUTPUT_CONTROL=y +CONFIG_FB=y +CONFIG_FB_FSL_DIU=y +# CONFIG_VGA_CONSOLE is not set CONFIG_SOUND=y CONFIG_SND=y # CONFIG_SND_SUPPORT_OLD_API is not set diff --git a/arch/powerpc/platforms/85xx/p1022_ds.c b/arch/powerpc/platforms/85xx/p1022_ds.c index e1467c9..e984d4e 100644 --- a/arch/powerpc/platforms/85xx/p1022_ds.c +++ b/arch/powerpc/platforms/85xx/p1022_ds.c @@ -8,7 +8,6 @@ * Copyright 2010 Freescale Semiconductor, Inc. * * This file is taken from the Freescale P1022DS BSP, with modifications: - * 1) No DIU support (pending rewrite of DIU code) * 2) No AMP support * 3) No PCI endpoint support * @@ -20,12 +19,212 @@ #include #include #include - +#include +#include #include #include #include #include +#include + +#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE) + +/* + * Board-specific initialization of the DIU. This code should probably be + * executed when the DIU is opened, rather than in arch code, but the DIU + * driver does not have a mechanism for this (yet). + * + * This is especially problematic on the P1022DS because the local bus (eLBC) + * and the DIU video signals share the same pins, which means that enabling the + * DIU will disable access to NOR flash. + */ + +/* DIU Pixel Clock bits of the CLKDVDR Global Utilities register */ +#define CLKDVDR_PXCKEN 0x80000000 +#define CLKDVDR_PXCKINV 0x10000000 +#define CLKDVDR_PXCKDLY 0x06000000 +#define CLKDVDR_PXCLK_MASK 0x00FF0000 + +/* Some ngPIXIS register definitions */ +#define PX_BRDCFG1_DVIEN 0x80 +#define PX_BRDCFG1_DFPEN 0x40 +#define PX_BRDCFG1_BACKLIGHT 0x20 +#define PX_BRDCFG1_DDCEN 0x10 + +/* + * DIU Area Descriptor + * + * Note that we need to byte-swap the value before it's written to the AD + * register. So even though the registers don't look like they're in the same + * bit positions as they are on the MPC8610, the same value is written to the + * AD register on the MPC8610 and on the P1022. + */ +#define AD_BYTE_F 0x10000000 +#define AD_ALPHA_C_MASK 0x0E000000 +#define AD_ALPHA_C_SHIFT 25 +#define AD_BLUE_C_MASK 0x01800000 +#define AD_BLUE_C_SHIFT 23 +#define AD_GREEN_C_MASK 0x00600000 +#define AD_GREEN_C_SHIFT 21 +#define AD_RED_C_MASK 0x00180000 +#define AD_RED_C_SHIFT 19 +#define AD_PALETTE 0x00040000 +#define AD_PIXEL_S_MASK 0x00030000 +#define AD_PIXEL_S_SHIFT 16 +#define AD_COMP_3_MASK 0x0000F000 +#define AD_COMP_3_SHIFT 12 +#define AD_COMP_2_MASK 0x00000F00 +#define AD_COMP_2_SHIFT 8 +#define AD_COMP_1_MASK 0x000000F0 +#define AD_COMP_1_SHIFT 4 +#define AD_COMP_0_MASK 0x0000000F +#define AD_COMP_0_SHIFT 0 + +#define MAKE_AD(alpha, red, blue, green, size, c0, c1, c2, c3) \ + cpu_to_le32(AD_BYTE_F | (alpha << AD_ALPHA_C_SHIFT) | \ + (blue << AD_BLUE_C_SHIFT) | (green << AD_GREEN_C_SHIFT) | \ + (red << AD_RED_C_SHIFT) | (c3 << AD_COMP_3_SHIFT) | \ + (c2 << AD_COMP_2_SHIFT) | (c1 << AD_COMP_1_SHIFT) | \ + (c0 << AD_COMP_0_SHIFT) | (size << AD_PIXEL_S_SHIFT)) + +/** + * p1022ds_get_pixel_format: return the Area Descriptor for a given pixel depth + * + * The Area Descriptor is a 32-bit value that determine which bits in each + * pixel are to be used for each color. + */ +static unsigned int p1022ds_get_pixel_format(unsigned int bits_per_pixel, + int monitor_port) +{ + switch (bits_per_pixel) { + case 32: + /* 0x88883316 */ + return MAKE_AD(3, 2, 0, 1, 3, 8, 8, 8, 8); + case 24: + /* 0x88082219 */ + return MAKE_AD(4, 0, 1, 2, 2, 0, 8, 8, 8); + case 16: + /* 0x65053118 */ + return MAKE_AD(4, 2, 1, 0, 1, 5, 6, 5, 0); + default: + pr_err("fsl-diu: unsupported pixel depth %u\n", bits_per_pixel); + return 0; + } +} + +/** + * p1022ds_set_gamma_table: update the gamma table, if necessary + * + * On some boards, the gamma table for some ports may need to be modified. + * This is not the case on the P1022DS, so we do nothing. +*/ +static void p1022ds_set_gamma_table(int monitor_port, char *gamma_table_base) +{ +} + +/** + * p1022ds_set_monitor_port: switch the output to a different monitor port + * + */ +static void p1022ds_set_monitor_port(int monitor_port) +{ + struct device_node *pixis_node; + u8 __iomem *brdcfg1; + + pixis_node = of_find_compatible_node(NULL, NULL, "fsl,p1022ds-pixis"); + if (!pixis_node) { + pr_err("p1022ds: missing ngPIXIS node\n"); + return; + } + + brdcfg1 = of_iomap(pixis_node, 0); + if (!brdcfg1) { + pr_err("p1022ds: could not map ngPIXIS registers\n"); + return; + } + brdcfg1 += 9; /* BRDCFG1 is at offset 9 in the ngPIXIS */ + + switch (monitor_port) { + case 0: /* DVI */ + /* Enable the DVI port, disable the DFP and the backlight */ + clrsetbits_8(brdcfg1, PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT, + PX_BRDCFG1_DVIEN); + break; + case 1: /* Single link LVDS */ + /* Enable the DFP port, disable the DVI and the backlight */ + clrsetbits_8(brdcfg1, PX_BRDCFG1_DVIEN | PX_BRDCFG1_BACKLIGHT, + PX_BRDCFG1_DFPEN); + break; + default: + pr_err("p1022ds: unsupported monitor port %i\n", monitor_port); + } +} + +/** + * p1022ds_set_pixel_clock: program the DIU's clock + * + * @pixclock: the wavelength, in picoseconds, of the clock + */ +void p1022ds_set_pixel_clock(unsigned int pixclock) +{ + struct device_node *guts_np = NULL; + struct ccsr_guts_85xx __iomem *guts; + unsigned long freq; + u64 temp; + u32 pxclk; + + /* Map the global utilities registers. */ + guts_np = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts"); + if (!guts_np) { + pr_err("p1022ds: missing global utilties device node\n"); + return; + } + + guts = of_iomap(guts_np, 0); + of_node_put(guts_np); + if (!guts) { + pr_err("p1022ds: could not map global utilties device\n"); + return; + } + + /* Convert pixclock from a wavelength to a frequency */ + temp = 1000000000000ULL; + do_div(temp, pixclock); + freq = temp; + + /* pixclk is the ratio of the platform clock to the pixel clock */ + pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq); + + /* Disable the pixel clock, and set it to non-inverted and no delay */ + clrbits32(&guts->clkdvdr, + CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK); + + /* Enable the clock and set the pxclk */ + setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16)); +} + +/** + * p1022ds_show_monitor_port: show the current monitor + * + * This function returns a string indicating whether the current monitor is + * set to DVI or LVDS. + */ +ssize_t p1022ds_show_monitor_port(int monitor_port, char *buf) +{ + return sprintf(buf, "%c0 - DVI\n%c1 - Single link LVDS\n", + monitor_port == 0 ? '*' : ' ', monitor_port == 1 ? '*' : ' '); +} + +/** + * p1022ds_set_sysfs_monitor_port: set the monitor port for sysfs + */ +int p1022ds_set_sysfs_monitor_port(int val) +{ + return val < 2 ? val : 0; +} + +#endif void __init p1022_ds_pic_init(void) { @@ -92,6 +291,15 @@ static void __init p1022_ds_setup_arch(void) } #endif +#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE) + diu_ops.get_pixel_format = p1022ds_get_pixel_format; + diu_ops.set_gamma_table = p1022ds_set_gamma_table; + diu_ops.set_monitor_port = p1022ds_set_monitor_port; + diu_ops.set_pixel_clock = p1022ds_set_pixel_clock; + diu_ops.show_monitor_port = p1022ds_show_monitor_port; + diu_ops.set_sysfs_monitor_port = p1022ds_set_sysfs_monitor_port; +#endif + #ifdef CONFIG_SMP mpc85xx_smp_init(); #endif -- cgit v1.1 From a80be1680502f99de5f9565c491208e90a9a3afe Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 15 Oct 2010 06:15:56 +0900 Subject: sh: pci: Convert to upper/lower_32_bits() helpers. Instead of hand-rolling our own, just use the generic ones instead. Signed-off-by: Paul Mundt --- arch/sh/drivers/pci/pcie-sh7786.c | 4 ++-- arch/sh/drivers/pci/pcie-sh7786.h | 7 ------- 2 files changed, 2 insertions(+), 9 deletions(-) (limited to 'arch') diff --git a/arch/sh/drivers/pci/pcie-sh7786.c b/arch/sh/drivers/pci/pcie-sh7786.c index ae0b2c9..96e9b05 100644 --- a/arch/sh/drivers/pci/pcie-sh7786.c +++ b/arch/sh/drivers/pci/pcie-sh7786.c @@ -446,9 +446,9 @@ static int __init pcie_init(struct sh7786_pcie_port *port) mask = (roundup_pow_of_two(size) / SZ_256K) - 1; pci_write_reg(chan, mask << 18, SH4A_PCIEPAMR(win)); - pci_write_reg(chan, RES_TO_U32_HIGH(res->start), + pci_write_reg(chan, upper_32_bits(res->start), SH4A_PCIEPARH(win)); - pci_write_reg(chan, RES_TO_U32_LOW(res->start), + pci_write_reg(chan, lower_32_bits(res->start), SH4A_PCIEPARL(win)); mask = MASK_PARE; diff --git a/arch/sh/drivers/pci/pcie-sh7786.h b/arch/sh/drivers/pci/pcie-sh7786.h index a2a0ca6..1ee054e 100644 --- a/arch/sh/drivers/pci/pcie-sh7786.h +++ b/arch/sh/drivers/pci/pcie-sh7786.h @@ -568,13 +568,6 @@ #define PCI_REG(x) ((x) + 0x40000) -#define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL)) -#define U64_TO_U32_HIGH(val) ((u32)((val) >> 32)) -#define RES_TO_U32_LOW(val) \ - ((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_LOW(val) : (val)) -#define RES_TO_U32_HIGH(val) \ - ((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_HIGH(val) : (0)) - static inline void pci_write_reg(struct pci_channel *chan, unsigned long val, unsigned long reg) { -- cgit v1.1 From 685e4080c62b4b5c6f67c7b088e416e98d06f7e6 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Fri, 15 Oct 2010 05:14:54 +0000 Subject: ARM: mach-shmobile: clock-sh7372: add sh7372_ prefix to global clocks This patch also registered global extal clocks to sh7372.h Signed-off-by: Kuninori Morimoto Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/board-ap4evb.c | 14 +++++++------- arch/arm/mach-shmobile/clock-sh7372.c | 24 ++++++++++++------------ arch/arm/mach-shmobile/include/mach/sh7372.h | 8 +++++--- 3 files changed, 24 insertions(+), 22 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c index aaac8b0..f879eb3 100644 --- a/arch/arm/mach-shmobile/board-ap4evb.c +++ b/arch/arm/mach-shmobile/board-ap4evb.c @@ -780,22 +780,22 @@ static int __init hdmi_init_pm_clock(void) goto out; } - ret = clk_set_parent(&pllc2_clk, &dv_clki_div2_clk); + ret = clk_set_parent(&sh7372_pllc2_clk, &sh7372_dv_clki_div2_clk); if (ret < 0) { - pr_err("Cannot set PLLC2 parent: %d, %d users\n", ret, pllc2_clk.usecount); + pr_err("Cannot set PLLC2 parent: %d, %d users\n", ret, sh7372_pllc2_clk.usecount); goto out; } - pr_debug("PLLC2 initial frequency %lu\n", clk_get_rate(&pllc2_clk)); + pr_debug("PLLC2 initial frequency %lu\n", clk_get_rate(&sh7372_pllc2_clk)); - rate = clk_round_rate(&pllc2_clk, 594000000); + rate = clk_round_rate(&sh7372_pllc2_clk, 594000000); if (rate < 0) { pr_err("Cannot get suitable rate: %ld\n", rate); ret = rate; goto out; } - ret = clk_set_rate(&pllc2_clk, rate); + ret = clk_set_rate(&sh7372_pllc2_clk, rate); if (ret < 0) { pr_err("Cannot set rate %ld: %d\n", rate, ret); goto out; @@ -803,7 +803,7 @@ static int __init hdmi_init_pm_clock(void) pr_debug("PLLC2 set frequency %lu\n", rate); - ret = clk_set_parent(hdmi_ick, &pllc2_clk); + ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk); if (ret < 0) { pr_err("Cannot set HDMI parent: %d\n", ret); goto out; @@ -1132,7 +1132,7 @@ static void __init ap4evb_timer_init(void) shmobile_timer.init(); /* External clock source */ - clk_set_rate(&dv_clki_clk, 27000000); + clk_set_rate(&sh7372_dv_clki_clk, 27000000); } static struct sys_timer ap4evb_timer = { diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c index 3ab190a..50c3971 100644 --- a/arch/arm/mach-shmobile/clock-sh7372.c +++ b/arch/arm/mach-shmobile/clock-sh7372.c @@ -51,7 +51,7 @@ #define SMSTPCR4 0xe6150140 /* Platforms must set frequency on their DV_CLKI pin */ -struct clk dv_clki_clk = { +struct clk sh7372_dv_clki_clk = { }; /* Fixed 32 KHz root clock from EXTALR pin */ @@ -86,9 +86,9 @@ static struct clk_ops div2_clk_ops = { }; /* Divide dv_clki by two */ -struct clk dv_clki_div2_clk = { +struct clk sh7372_dv_clki_div2_clk = { .ops = &div2_clk_ops, - .parent = &dv_clki_clk, + .parent = &sh7372_dv_clki_clk, }; /* Divide extal1 by two */ @@ -150,7 +150,7 @@ static struct clk pllc1_div2_clk = { static struct clk *pllc2_parent[] = { [0] = &extal1_div2_clk, [1] = &extal2_div2_clk, - [2] = &dv_clki_div2_clk, + [2] = &sh7372_dv_clki_div2_clk, }; /* Only multipliers 20 * 2 to 46 * 2 are valid, last entry for CPUFREQ_TABLE_END */ @@ -284,7 +284,7 @@ static struct clk_ops pllc2_clk_ops = { .set_parent = pllc2_set_parent, }; -struct clk pllc2_clk = { +struct clk sh7372_pllc2_clk = { .ops = &pllc2_clk_ops, .parent = &extal1_div2_clk, .freq_table = pllc2_freq_table, @@ -293,18 +293,18 @@ struct clk pllc2_clk = { }; static struct clk *main_clks[] = { - &dv_clki_clk, + &sh7372_dv_clki_clk, &r_clk, &sh7372_extal1_clk, &sh7372_extal2_clk, - &dv_clki_div2_clk, + &sh7372_dv_clki_div2_clk, &extal1_div2_clk, &extal2_div2_clk, &extal2_div4_clk, &pllc0_clk, &pllc1_clk, &pllc1_div2_clk, - &pllc2_clk, + &sh7372_pllc2_clk, }; static void div4_kick(struct clk *clk) @@ -382,8 +382,8 @@ enum { DIV6_HDMI, DIV6_REPARENT_NR }; /* Indices are important - they are the actual src selecting values */ static struct clk *hdmi_parent[] = { [0] = &pllc1_div2_clk, - [1] = &pllc2_clk, - [2] = &dv_clki_clk, + [1] = &sh7372_pllc2_clk, + [2] = &sh7372_dv_clki_clk, [3] = NULL, /* pllc2_div4 not implemented yet */ }; @@ -448,7 +448,7 @@ static struct clk mstp_clks[MSTP_NR] = { static struct clk_lookup lookups[] = { /* main clocks */ - CLKDEV_CON_ID("dv_clki_div2_clk", &dv_clki_div2_clk), + CLKDEV_CON_ID("dv_clki_div2_clk", &sh7372_dv_clki_div2_clk), CLKDEV_CON_ID("r_clk", &r_clk), CLKDEV_CON_ID("extal1", &sh7372_extal1_clk), CLKDEV_CON_ID("extal2", &sh7372_extal2_clk), @@ -458,7 +458,7 @@ static struct clk_lookup lookups[] = { CLKDEV_CON_ID("pllc0_clk", &pllc0_clk), CLKDEV_CON_ID("pllc1_clk", &pllc1_clk), CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk), - CLKDEV_CON_ID("pllc2_clk", &pllc2_clk), + CLKDEV_CON_ID("pllc2_clk", &sh7372_pllc2_clk), /* DIV4 clocks */ CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]), diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h index 33e9700..9838fcf 100644 --- a/arch/arm/mach-shmobile/include/mach/sh7372.h +++ b/arch/arm/mach-shmobile/include/mach/sh7372.h @@ -457,8 +457,10 @@ enum { SHDMA_SLAVE_SDHI2_TX, }; -extern struct clk dv_clki_clk; -extern struct clk dv_clki_div2_clk; -extern struct clk pllc2_clk; +extern struct clk sh7372_extal1_clk; +extern struct clk sh7372_extal2_clk; +extern struct clk sh7372_dv_clki_clk; +extern struct clk sh7372_dv_clki_div2_clk; +extern struct clk sh7372_pllc2_clk; #endif /* __ASM_SH7372_H__ */ -- cgit v1.1 From 69ce8aa4925a54de192cf64e99abd294586c1984 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Fri, 15 Oct 2010 05:15:05 +0000 Subject: ARM: mach-shmobile: clock-sh7372: FSI parent select support Signed-off-by: Kuninori Morimoto Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/board-ap4evb.c | 70 ++++++++++++++++------------ arch/arm/mach-shmobile/clock-sh7372.c | 45 ++++++++++++++---- arch/arm/mach-shmobile/include/mach/sh7372.h | 2 + 3 files changed, 80 insertions(+), 37 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c index f879eb3..1e7beee 100644 --- a/arch/arm/mach-shmobile/board-ap4evb.c +++ b/arch/arm/mach-shmobile/board-ap4evb.c @@ -546,27 +546,6 @@ static struct platform_device *qhd_devices[] __initdata = { /* FSI */ #define IRQ_FSI evt2irq(0x1840) -#define FSIACKCR 0xE6150018 -static void fsiackcr_init(struct clk *clk) -{ - u32 status = __raw_readl(clk->enable_reg); - - /* use external clock */ - status &= ~0x000000ff; - status |= 0x00000080; - __raw_writel(status, clk->enable_reg); -} - -static struct clk_ops fsiackcr_clk_ops = { - .init = fsiackcr_init, -}; - -static struct clk fsiackcr_clk = { - .ops = &fsiackcr_clk_ops, - .enable_reg = (void __iomem *)FSIACKCR, - .rate = 0, /* unknown */ -}; - static struct sh_fsi_platform_info fsi_info = { .porta_flags = SH_FSI_BRS_INV | SH_FSI_OUT_SLAVE_MODE | @@ -817,6 +796,47 @@ out: device_initcall(hdmi_init_pm_clock); +#define FSIACK_DUMMY_RATE 48000 +static int __init fsi_init_pm_clock(void) +{ + struct clk *fsia_ick; + int ret; + + /* + * FSIACK is connected to AK4642, + * and the rate is depend on playing sound rate. + * So, set dummy rate (= 48k) here + */ + ret = clk_set_rate(&sh7372_fsiack_clk, FSIACK_DUMMY_RATE); + if (ret < 0) { + pr_err("Cannot set FSIACK dummy rate: %d\n", ret); + return ret; + } + + fsia_ick = clk_get(&fsi_device.dev, "icka"); + if (IS_ERR(fsia_ick)) { + ret = PTR_ERR(fsia_ick); + pr_err("Cannot get FSI ICK: %d\n", ret); + return ret; + } + + ret = clk_set_parent(fsia_ick, &sh7372_fsiack_clk); + if (ret < 0) { + pr_err("Cannot set FSI-A parent: %d\n", ret); + goto out; + } + + ret = clk_set_rate(fsia_ick, FSIACK_DUMMY_RATE); + if (ret < 0) + pr_err("Cannot set FSI-A rate: %d\n", ret); + +out: + clk_put(fsia_ick); + + return ret; +} +device_initcall(fsi_init_pm_clock); + /* * FIXME !! * @@ -1007,14 +1027,6 @@ static void __init ap4evb_init(void) clk_put(clk); } - /* change parent of FSI A */ - clk = clk_get(NULL, "fsia_clk"); - if (!IS_ERR(clk)) { - clk_register(&fsiackcr_clk); - clk_set_parent(clk, &fsiackcr_clk); - clk_put(clk); - } - /* * set irq priority, to avoid sound chopping * when NFS rootfs is used diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c index 50c3971..4557084 100644 --- a/arch/arm/mach-shmobile/clock-sh7372.c +++ b/arch/arm/mach-shmobile/clock-sh7372.c @@ -292,6 +292,13 @@ struct clk sh7372_pllc2_clk = { .parent_num = ARRAY_SIZE(pllc2_parent), }; +/* External input clock (pin name: FSIACK/FSIBCK ) */ +struct clk sh7372_fsiack_clk = { +}; + +struct clk sh7372_fsibck_clk = { +}; + static struct clk *main_clks[] = { &sh7372_dv_clki_clk, &r_clk, @@ -305,6 +312,8 @@ static struct clk *main_clks[] = { &pllc1_clk, &pllc1_div2_clk, &sh7372_pllc2_clk, + &sh7372_fsiack_clk, + &sh7372_fsibck_clk, }; static void div4_kick(struct clk *clk) @@ -357,7 +366,7 @@ static struct clk div4_clks[DIV4_NR] = { }; enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_FMSI, DIV6_FMSO, - DIV6_FSIA, DIV6_FSIB, DIV6_SUB, DIV6_SPU, + DIV6_SUB, DIV6_SPU, DIV6_VOU, DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P, DIV6_NR }; @@ -367,8 +376,6 @@ static struct clk div6_clks[DIV6_NR] = { [DIV6_VCK3] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR3, 0), [DIV6_FMSI] = SH_CLK_DIV6(&pllc1_div2_clk, FMSICKCR, 0), [DIV6_FMSO] = SH_CLK_DIV6(&pllc1_div2_clk, FMSOCKCR, 0), - [DIV6_FSIA] = SH_CLK_DIV6(&pllc1_div2_clk, FSIACKCR, 0), - [DIV6_FSIB] = SH_CLK_DIV6(&pllc1_div2_clk, FSIBCKCR, 0), [DIV6_SUB] = SH_CLK_DIV6(&sh7372_extal2_clk, SUBCKCR, 0), [DIV6_SPU] = SH_CLK_DIV6(&pllc1_div2_clk, SPUCKCR, 0), [DIV6_VOU] = SH_CLK_DIV6(&pllc1_div2_clk, VOUCKCR, 0), @@ -377,7 +384,7 @@ static struct clk div6_clks[DIV6_NR] = { [DIV6_DSI1P] = SH_CLK_DIV6(&pllc1_div2_clk, DSI1PCKCR, 0), }; -enum { DIV6_HDMI, DIV6_REPARENT_NR }; +enum { DIV6_HDMI, DIV6_FSIA, DIV6_FSIB, DIV6_REPARENT_NR }; /* Indices are important - they are the actual src selecting values */ static struct clk *hdmi_parent[] = { @@ -387,9 +394,27 @@ static struct clk *hdmi_parent[] = { [3] = NULL, /* pllc2_div4 not implemented yet */ }; +static struct clk *fsiackcr_parent[] = { + [0] = &pllc1_div2_clk, + [1] = &sh7372_pllc2_clk, + [2] = &sh7372_fsiack_clk, /* external input for FSI A */ + [3] = NULL, /* setting prohibited */ +}; + +static struct clk *fsibckcr_parent[] = { + [0] = &pllc1_div2_clk, + [1] = &sh7372_pllc2_clk, + [2] = &sh7372_fsibck_clk, /* external input for FSI B */ + [3] = NULL, /* setting prohibited */ +}; + static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = { [DIV6_HDMI] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, HDMICKCR, 0, hdmi_parent, ARRAY_SIZE(hdmi_parent), 6, 2), + [DIV6_FSIA] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, FSIACKCR, 0, + fsiackcr_parent, ARRAY_SIZE(fsiackcr_parent), 6, 2), + [DIV6_FSIB] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, FSIBCKCR, 0, + fsibckcr_parent, ARRAY_SIZE(fsibckcr_parent), 6, 2), }; enum { MSTP001, @@ -429,7 +454,7 @@ static struct clk mstp_clks[MSTP_NR] = { [MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */ [MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */ [MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */ - [MSTP328] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR3, 28, 0), /* FSIA */ + [MSTP328] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR3, 28, 0), /* FSI2 */ [MSTP323] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */ [MSTP322] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 22, 0), /* USB0 */ [MSTP314] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */ @@ -445,6 +470,7 @@ static struct clk mstp_clks[MSTP_NR] = { #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } #define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk } +#define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk } static struct clk_lookup lookups[] = { /* main clocks */ @@ -483,8 +509,8 @@ static struct clk_lookup lookups[] = { CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]), CLKDEV_CON_ID("fmsi_clk", &div6_clks[DIV6_FMSI]), CLKDEV_CON_ID("fmso_clk", &div6_clks[DIV6_FMSO]), - CLKDEV_CON_ID("fsia_clk", &div6_clks[DIV6_FSIA]), - CLKDEV_CON_ID("fsib_clk", &div6_clks[DIV6_FSIB]), + CLKDEV_CON_ID("fsia_clk", &div6_reparent_clks[DIV6_FSIA]), + CLKDEV_CON_ID("fsib_clk", &div6_reparent_clks[DIV6_FSIB]), CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]), CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]), CLKDEV_CON_ID("vou_clk", &div6_clks[DIV6_VOU]), @@ -531,7 +557,10 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("r8a66597_hcd.1", &mstp_clks[MSTP406]), /* USB1 */ CLKDEV_DEV_ID("r8a66597_udc.1", &mstp_clks[MSTP406]), /* USB1 */ CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */ - {.con_id = "ick", .dev_id = "sh-mobile-hdmi", .clk = &div6_reparent_clks[DIV6_HDMI]}, + + CLKDEV_ICK_ID("ick", "sh-mobile-hdmi", &div6_reparent_clks[DIV6_HDMI]), + CLKDEV_ICK_ID("icka", "sh_fsi2", &div6_reparent_clks[DIV6_FSIA]), + CLKDEV_ICK_ID("ickb", "sh_fsi2", &div6_reparent_clks[DIV6_FSIB]), }; void __init sh7372_clock_init(void) diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h index 9838fcf..147775a 100644 --- a/arch/arm/mach-shmobile/include/mach/sh7372.h +++ b/arch/arm/mach-shmobile/include/mach/sh7372.h @@ -462,5 +462,7 @@ extern struct clk sh7372_extal2_clk; extern struct clk sh7372_dv_clki_clk; extern struct clk sh7372_dv_clki_div2_clk; extern struct clk sh7372_pllc2_clk; +extern struct clk sh7372_fsiack_clk; +extern struct clk sh7372_fsibck_clk; #endif /* __ASM_SH7372_H__ */ -- cgit v1.1 From 402f33154ee12de80fafa7f780d338d90cecbb5f Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Fri, 15 Oct 2010 07:53:56 +0000 Subject: ARM: mach-shmobile: remove videomodes from ap4evb platform data Now that HDMI videomodes have become optional, they can be safely removed from ap4evb platform data, since anyway 720p seems to be the best supported mode. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/board-ap4evb.c | 56 ----------------------------------- 1 file changed, 56 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c index 1e7beee..d21637d 100644 --- a/arch/arm/mach-shmobile/board-ap4evb.c +++ b/arch/arm/mach-shmobile/board-ap4evb.c @@ -577,60 +577,6 @@ static struct platform_device fsi_device = { }, }; -/* - * If left and right margins are not multiples of 8, - * LDHAJR will be adjusted accordingly by the LCDC - * driver. Until we start using EDID, these values - * might have to be adjusted for different monitors. - */ -const static struct fb_videomode ap4evb_hdmi_modes[] = { - { - .name = "HDMI 720p", - .xres = 1280, - .yres = 720, - - .left_margin = 200, - .right_margin = 88, - .hsync_len = 48, - - .upper_margin = 20, - .lower_margin = 5, - .vsync_len = 5, - - .pixclock = 13468, - .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT, - }, { - .name = "1280x1024", - .xres = 1280, - .yres = 1024, - - .left_margin = 144, - .right_margin = 48, - .hsync_len = 64, - - .upper_margin = 35, - .lower_margin = 5, - .vsync_len = 3, - - .pixclock = 9800, - .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT, - }, { - .name = "HDMI 480p", - .xres = 720, - .yres = 480, - - .left_margin = 36, - .right_margin = 18, - .hsync_len = 68, - - .upper_margin = 36, - .lower_margin = 3, - .vsync_len = 6, - .pixclock = 37037, - .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT, - }, -}; - static struct sh_mobile_lcdc_info sh_mobile_lcdc1_info = { .clock_source = LCDC_CLK_EXTERNAL, .ch[0] = { @@ -639,8 +585,6 @@ static struct sh_mobile_lcdc_info sh_mobile_lcdc1_info = { .interface_type = RGB24, .clock_divider = 1, .flags = LCDC_FLAGS_DWPOL, - .lcd_cfg = ap4evb_hdmi_modes, - .num_cfg = ARRAY_SIZE(ap4evb_hdmi_modes), } }; -- cgit v1.1 From 3acbf0849bcbb639fde53dc627e3b55a4c6429d2 Mon Sep 17 00:00:00 2001 From: Robert Richter Date: Tue, 31 Aug 2010 10:44:17 +0200 Subject: oprofile, x86: Add support for AMD family 12h This patch adds support for AMD family 12h (Llano) cpus. Signed-off-by: Robert Richter --- arch/x86/oprofile/nmi_int.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/x86/oprofile/nmi_int.c b/arch/x86/oprofile/nmi_int.c index bd1489c..0b0d1d6 100644 --- a/arch/x86/oprofile/nmi_int.c +++ b/arch/x86/oprofile/nmi_int.c @@ -726,6 +726,9 @@ int __init op_nmi_init(struct oprofile_operations *ops) case 0x11: cpu_type = "x86-64/family11h"; break; + case 0x12: + cpu_type = "x86-64/family12h"; + break; default: return -ENODEV; } -- cgit v1.1 From e63414740e15b4e2dc54c63fb9ea501b257fb0b5 Mon Sep 17 00:00:00 2001 From: Robert Richter Date: Thu, 26 Aug 2010 12:30:17 +0200 Subject: oprofile, x86: Add support for AMD family 14h This patch adds support for AMD family 14h (Ontario/Zacate) cpus. Signed-off-by: Robert Richter --- arch/x86/oprofile/nmi_int.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/x86/oprofile/nmi_int.c b/arch/x86/oprofile/nmi_int.c index 0b0d1d6..4e8baad 100644 --- a/arch/x86/oprofile/nmi_int.c +++ b/arch/x86/oprofile/nmi_int.c @@ -729,6 +729,9 @@ int __init op_nmi_init(struct oprofile_operations *ops) case 0x12: cpu_type = "x86-64/family12h"; break; + case 0x14: + cpu_type = "x86-64/family14h"; + break; default: return -ENODEV; } -- cgit v1.1 From 4ac945f002c0bebdeb530cbc3729e22895e64a7e Mon Sep 17 00:00:00 2001 From: Robert Richter Date: Tue, 21 Sep 2010 15:58:32 +0200 Subject: oprofile, x86: Check IBS capability bits 1 and 2 There are IBS CPUID feature flags in CPUID Fn8000_001B to detect if the cpu supports IBS fetch sampling (FetchSam) and/or IBS execution sampling (OpSam). This patch adds checks if the both features are available. Spec: http://support.amd.com/us/Processor_TechDocs/31116.pdf Signed-off-by: Robert Richter --- arch/x86/oprofile/op_model_amd.c | 59 ++++++++++++++++++++++++++-------------- 1 file changed, 38 insertions(+), 21 deletions(-) (limited to 'arch') diff --git a/arch/x86/oprofile/op_model_amd.c b/arch/x86/oprofile/op_model_amd.c index b67a6b5..96852d5 100644 --- a/arch/x86/oprofile/op_model_amd.c +++ b/arch/x86/oprofile/op_model_amd.c @@ -70,9 +70,22 @@ static u64 ibs_op_ctl; * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but * bit 0 is used to indicate the existence of IBS. */ -#define IBS_CAPS_AVAIL (1LL<<0) -#define IBS_CAPS_RDWROPCNT (1LL<<3) -#define IBS_CAPS_OPCNT (1LL<<4) +#define IBS_CAPS_AVAIL (1U<<0) +#define IBS_CAPS_FETCHSAM (1U<<1) +#define IBS_CAPS_OPSAM (1U<<2) +#define IBS_CAPS_RDWROPCNT (1U<<3) +#define IBS_CAPS_OPCNT (1U<<4) + +#define IBS_CAPS_DEFAULT (IBS_CAPS_AVAIL \ + | IBS_CAPS_FETCHSAM \ + | IBS_CAPS_OPSAM) + +/* + * IBS APIC setup + */ +#define IBSCTL 0x1cc +#define IBSCTL_LVT_OFFSET_VALID (1ULL<<8) +#define IBSCTL_LVT_OFFSET_MASK 0x0F /* * IBS randomization macros @@ -92,12 +105,12 @@ static u32 get_ibs_caps(void) /* check IBS cpuid feature flags */ max_level = cpuid_eax(0x80000000); if (max_level < IBS_CPUID_FEATURES) - return IBS_CAPS_AVAIL; + return IBS_CAPS_DEFAULT; ibs_caps = cpuid_eax(IBS_CPUID_FEATURES); if (!(ibs_caps & IBS_CAPS_AVAIL)) /* cpuid flags not valid */ - return IBS_CAPS_AVAIL; + return IBS_CAPS_DEFAULT; return ibs_caps; } @@ -527,22 +540,26 @@ static int setup_ibs_files(struct super_block *sb, struct dentry *root) ibs_config.op_enabled = 0; ibs_config.dispatched_ops = 0; - dir = oprofilefs_mkdir(sb, root, "ibs_fetch"); - oprofilefs_create_ulong(sb, dir, "enable", - &ibs_config.fetch_enabled); - oprofilefs_create_ulong(sb, dir, "max_count", - &ibs_config.max_cnt_fetch); - oprofilefs_create_ulong(sb, dir, "rand_enable", - &ibs_config.rand_en); - - dir = oprofilefs_mkdir(sb, root, "ibs_op"); - oprofilefs_create_ulong(sb, dir, "enable", - &ibs_config.op_enabled); - oprofilefs_create_ulong(sb, dir, "max_count", - &ibs_config.max_cnt_op); - if (ibs_caps & IBS_CAPS_OPCNT) - oprofilefs_create_ulong(sb, dir, "dispatched_ops", - &ibs_config.dispatched_ops); + if (ibs_caps & IBS_CAPS_FETCHSAM) { + dir = oprofilefs_mkdir(sb, root, "ibs_fetch"); + oprofilefs_create_ulong(sb, dir, "enable", + &ibs_config.fetch_enabled); + oprofilefs_create_ulong(sb, dir, "max_count", + &ibs_config.max_cnt_fetch); + oprofilefs_create_ulong(sb, dir, "rand_enable", + &ibs_config.rand_en); + } + + if (ibs_caps & IBS_CAPS_OPSAM) { + dir = oprofilefs_mkdir(sb, root, "ibs_op"); + oprofilefs_create_ulong(sb, dir, "enable", + &ibs_config.op_enabled); + oprofilefs_create_ulong(sb, dir, "max_count", + &ibs_config.max_cnt_op); + if (ibs_caps & IBS_CAPS_OPCNT) + oprofilefs_create_ulong(sb, dir, "dispatched_ops", + &ibs_config.dispatched_ops); + } return 0; } -- cgit v1.1 From fc889aa23f4767c1c3f77fce11e17bb0a638971f Mon Sep 17 00:00:00 2001 From: Robert Richter Date: Tue, 21 Sep 2010 18:09:00 +0200 Subject: oprofile, x86: Remove duplicate check for IBS_CAPS_OPCNT Since oprofile is setting up ibs_op/dispatched_ops in the fs only if the feature is available, its corresponding variable ibs_config.dispatched_ops is only set, if the feature is available. Thus the check is duplicate and can be removed. Signed-off-by: Robert Richter --- arch/x86/oprofile/op_model_amd.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/x86/oprofile/op_model_amd.c b/arch/x86/oprofile/op_model_amd.c index 96852d5..d5e9dab 100644 --- a/arch/x86/oprofile/op_model_amd.c +++ b/arch/x86/oprofile/op_model_amd.c @@ -257,8 +257,7 @@ static inline void op_amd_start_ibs(void) ibs_op_ctl = min(ibs_op_ctl + IBS_RANDOM_MAXCNT_OFFSET, IBS_OP_MAX_CNT); } - if (ibs_caps & IBS_CAPS_OPCNT && ibs_config.dispatched_ops) - ibs_op_ctl |= IBS_OP_CNT_CTL; + ibs_op_ctl |= ibs_config.dispatched_ops ? IBS_OP_CNT_CTL : 0; ibs_op_ctl |= IBS_OP_ENABLE; val = op_amd_randomize_ibs_op(ibs_op_ctl); wrmsrl(MSR_AMD64_IBSOPCTL, val); -- cgit v1.1 From 53b39e9480ef8a286cef9899c455a979acd0eed9 Mon Sep 17 00:00:00 2001 From: Robert Richter Date: Tue, 21 Sep 2010 17:58:15 +0200 Subject: oprofile, x86: Introduce struct ibs_state This patch introduces struct ibs_state that will extended by additinal members in follow-on patches. Signed-off-by: Robert Richter --- arch/x86/oprofile/op_model_amd.c | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) (limited to 'arch') diff --git a/arch/x86/oprofile/op_model_amd.c b/arch/x86/oprofile/op_model_amd.c index d5e9dab..9d45097 100644 --- a/arch/x86/oprofile/op_model_amd.c +++ b/arch/x86/oprofile/op_model_amd.c @@ -48,7 +48,7 @@ static unsigned long reset_value[NUM_VIRT_COUNTERS]; static u32 ibs_caps; -struct op_ibs_config { +struct ibs_config { unsigned long op_enabled; unsigned long fetch_enabled; unsigned long max_cnt_fetch; @@ -57,8 +57,12 @@ struct op_ibs_config { unsigned long dispatched_ops; }; -static struct op_ibs_config ibs_config; -static u64 ibs_op_ctl; +struct ibs_state { + u64 ibs_op_ctl; +}; + +static struct ibs_config ibs_config; +static struct ibs_state ibs_state; /* * IBS cpuid feature detection @@ -219,7 +223,7 @@ op_amd_handle_ibs(struct pt_regs * const regs, oprofile_write_commit(&entry); /* reenable the IRQ */ - ctl = op_amd_randomize_ibs_op(ibs_op_ctl); + ctl = op_amd_randomize_ibs_op(ibs_state.ibs_op_ctl); wrmsrl(MSR_AMD64_IBSOPCTL, ctl); } } @@ -232,6 +236,8 @@ static inline void op_amd_start_ibs(void) if (!ibs_caps) return; + memset(&ibs_state, 0, sizeof(ibs_state)); + if (ibs_config.fetch_enabled) { val = (ibs_config.max_cnt_fetch >> 4) & IBS_FETCH_MAX_CNT; val |= ibs_config.rand_en ? IBS_FETCH_RAND_EN : 0; @@ -240,13 +246,13 @@ static inline void op_amd_start_ibs(void) } if (ibs_config.op_enabled) { - ibs_op_ctl = ibs_config.max_cnt_op >> 4; + val = ibs_config.max_cnt_op >> 4; if (!(ibs_caps & IBS_CAPS_RDWROPCNT)) { /* * IbsOpCurCnt not supported. See * op_amd_randomize_ibs_op() for details. */ - ibs_op_ctl = clamp(ibs_op_ctl, 0x0081ULL, 0xFF80ULL); + val = clamp(val, 0x0081ULL, 0xFF80ULL); } else { /* * The start value is randomized with a @@ -254,12 +260,13 @@ static inline void op_amd_start_ibs(void) * with the half of the randomized range. Also * avoid underflows. */ - ibs_op_ctl = min(ibs_op_ctl + IBS_RANDOM_MAXCNT_OFFSET, - IBS_OP_MAX_CNT); + val = min(val + IBS_RANDOM_MAXCNT_OFFSET, + IBS_OP_MAX_CNT); } - ibs_op_ctl |= ibs_config.dispatched_ops ? IBS_OP_CNT_CTL : 0; - ibs_op_ctl |= IBS_OP_ENABLE; - val = op_amd_randomize_ibs_op(ibs_op_ctl); + val |= ibs_config.dispatched_ops ? IBS_OP_CNT_CTL : 0; + val |= IBS_OP_ENABLE; + ibs_state.ibs_op_ctl = val; + val = op_amd_randomize_ibs_op(ibs_state.ibs_op_ctl); wrmsrl(MSR_AMD64_IBSOPCTL, val); } } -- cgit v1.1 From 25da6950475becb35d7a3bb3b5fbdc715a76887e Mon Sep 17 00:00:00 2001 From: Robert Richter Date: Tue, 21 Sep 2010 15:49:31 +0200 Subject: oprofile, x86: Add support for IBS branch target address reporting This patch adds support for IBS branch target address reporting. A new MSR (MSRC001_103B IBS Branch Target Address) has been added that provides the logical address in canonical form for the branch target. The size of the IBS sample that is transferred to the userland has been increased. For backward compatibility, the userland daemon must explicit enable the feature by writing to the oprofilefs file ibs_op/branch_target After enabling branch target address reporting, the userland daemon must handle the extended size of the IBS sample. Signed-off-by: Robert Richter --- arch/x86/include/asm/msr-index.h | 1 + arch/x86/oprofile/op_model_amd.c | 26 ++++++++++++++++++++------ 2 files changed, 21 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 986f779..91ba8e6 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -121,6 +121,7 @@ #define MSR_AMD64_IBSDCLINAD 0xc0011038 #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 #define MSR_AMD64_IBSCTL 0xc001103a +#define MSR_AMD64_IBSBRTARGET 0xc001103b /* Fam 10h MSRs */ #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 diff --git a/arch/x86/oprofile/op_model_amd.c b/arch/x86/oprofile/op_model_amd.c index 9d45097..9de33fa 100644 --- a/arch/x86/oprofile/op_model_amd.c +++ b/arch/x86/oprofile/op_model_amd.c @@ -55,10 +55,13 @@ struct ibs_config { unsigned long max_cnt_op; unsigned long rand_en; unsigned long dispatched_ops; + unsigned long branch_target; }; struct ibs_state { - u64 ibs_op_ctl; + u64 ibs_op_ctl; + int branch_target; + unsigned long sample_size; }; static struct ibs_config ibs_config; @@ -79,6 +82,7 @@ static struct ibs_state ibs_state; #define IBS_CAPS_OPSAM (1U<<2) #define IBS_CAPS_RDWROPCNT (1U<<3) #define IBS_CAPS_OPCNT (1U<<4) +#define IBS_CAPS_BRNTRGT (1U<<5) #define IBS_CAPS_DEFAULT (IBS_CAPS_AVAIL \ | IBS_CAPS_FETCHSAM \ @@ -207,8 +211,8 @@ op_amd_handle_ibs(struct pt_regs * const regs, rdmsrl(MSR_AMD64_IBSOPCTL, ctl); if (ctl & IBS_OP_VAL) { rdmsrl(MSR_AMD64_IBSOPRIP, val); - oprofile_write_reserve(&entry, regs, val, - IBS_OP_CODE, IBS_OP_SIZE); + oprofile_write_reserve(&entry, regs, val, IBS_OP_CODE, + ibs_state.sample_size); oprofile_add_data64(&entry, val); rdmsrl(MSR_AMD64_IBSOPDATA, val); oprofile_add_data64(&entry, val); @@ -220,6 +224,10 @@ op_amd_handle_ibs(struct pt_regs * const regs, oprofile_add_data64(&entry, val); rdmsrl(MSR_AMD64_IBSDCPHYSAD, val); oprofile_add_data64(&entry, val); + if (ibs_state.branch_target) { + rdmsrl(MSR_AMD64_IBSBRTARGET, val); + oprofile_add_data(&entry, (unsigned long)val); + } oprofile_write_commit(&entry); /* reenable the IRQ */ @@ -266,6 +274,11 @@ static inline void op_amd_start_ibs(void) val |= ibs_config.dispatched_ops ? IBS_OP_CNT_CTL : 0; val |= IBS_OP_ENABLE; ibs_state.ibs_op_ctl = val; + ibs_state.sample_size = IBS_OP_SIZE; + if (ibs_config.branch_target) { + ibs_state.branch_target = 1; + ibs_state.sample_size++; + } val = op_amd_randomize_ibs_op(ibs_state.ibs_op_ctl); wrmsrl(MSR_AMD64_IBSOPCTL, val); } @@ -540,11 +553,9 @@ static int setup_ibs_files(struct super_block *sb, struct dentry *root) /* model specific files */ /* setup some reasonable defaults */ + memset(&ibs_config, 0, sizeof(ibs_config)); ibs_config.max_cnt_fetch = 250000; - ibs_config.fetch_enabled = 0; ibs_config.max_cnt_op = 250000; - ibs_config.op_enabled = 0; - ibs_config.dispatched_ops = 0; if (ibs_caps & IBS_CAPS_FETCHSAM) { dir = oprofilefs_mkdir(sb, root, "ibs_fetch"); @@ -565,6 +576,9 @@ static int setup_ibs_files(struct super_block *sb, struct dentry *root) if (ibs_caps & IBS_CAPS_OPCNT) oprofilefs_create_ulong(sb, dir, "dispatched_ops", &ibs_config.dispatched_ops); + if (ibs_caps & IBS_CAPS_BRNTRGT) + oprofilefs_create_ulong(sb, dir, "branch_target", + &ibs_config.branch_target); } return 0; -- cgit v1.1 From b47fad3bfb5940cc3e28a1c69716f6dc44e4b7e6 Mon Sep 17 00:00:00 2001 From: Robert Richter Date: Wed, 22 Sep 2010 17:45:39 +0200 Subject: oprofile, x86: Add support for IBS periodic op counter extension The count value for IBS op sampling has been extended by 7 bits. The feature is reflected in bit 6 (OpCntExt) of the IBS capability register (CPUID Fn8000_001B_EAX). Signed-off-by: Robert Richter --- arch/x86/include/asm/perf_event.h | 19 ++++++++++--------- arch/x86/oprofile/op_model_amd.c | 22 +++++++++++++++++++--- 2 files changed, 29 insertions(+), 12 deletions(-) (limited to 'arch') diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h index 6e742cc..550e26b1 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -111,17 +111,18 @@ union cpuid10_edx { #define X86_PMC_IDX_FIXED_BTS (X86_PMC_IDX_FIXED + 16) /* IbsFetchCtl bits/masks */ -#define IBS_FETCH_RAND_EN (1ULL<<57) -#define IBS_FETCH_VAL (1ULL<<49) -#define IBS_FETCH_ENABLE (1ULL<<48) -#define IBS_FETCH_CNT 0xFFFF0000ULL -#define IBS_FETCH_MAX_CNT 0x0000FFFFULL +#define IBS_FETCH_RAND_EN (1ULL<<57) +#define IBS_FETCH_VAL (1ULL<<49) +#define IBS_FETCH_ENABLE (1ULL<<48) +#define IBS_FETCH_CNT 0xFFFF0000ULL +#define IBS_FETCH_MAX_CNT 0x0000FFFFULL /* IbsOpCtl bits */ -#define IBS_OP_CNT_CTL (1ULL<<19) -#define IBS_OP_VAL (1ULL<<18) -#define IBS_OP_ENABLE (1ULL<<17) -#define IBS_OP_MAX_CNT 0x0000FFFFULL +#define IBS_OP_CNT_CTL (1ULL<<19) +#define IBS_OP_VAL (1ULL<<18) +#define IBS_OP_ENABLE (1ULL<<17) +#define IBS_OP_MAX_CNT 0x0000FFFFULL +#define IBS_OP_MAX_CNT_EXT 0x007FFFFFULL /* not a register bit mask */ #ifdef CONFIG_PERF_EVENTS extern void init_hw_perf_events(void); diff --git a/arch/x86/oprofile/op_model_amd.c b/arch/x86/oprofile/op_model_amd.c index 9de33fa..65f0a1e 100644 --- a/arch/x86/oprofile/op_model_amd.c +++ b/arch/x86/oprofile/op_model_amd.c @@ -83,6 +83,7 @@ static struct ibs_state ibs_state; #define IBS_CAPS_RDWROPCNT (1U<<3) #define IBS_CAPS_OPCNT (1U<<4) #define IBS_CAPS_BRNTRGT (1U<<5) +#define IBS_CAPS_OPCNTEXT (1U<<6) #define IBS_CAPS_DEFAULT (IBS_CAPS_AVAIL \ | IBS_CAPS_FETCHSAM \ @@ -246,8 +247,16 @@ static inline void op_amd_start_ibs(void) memset(&ibs_state, 0, sizeof(ibs_state)); + /* + * Note: Since the max count settings may out of range we + * write back the actual used values so that userland can read + * it. + */ + if (ibs_config.fetch_enabled) { - val = (ibs_config.max_cnt_fetch >> 4) & IBS_FETCH_MAX_CNT; + val = ibs_config.max_cnt_fetch >> 4; + val = min(val, IBS_FETCH_MAX_CNT); + ibs_config.max_cnt_fetch = val << 4; val |= ibs_config.rand_en ? IBS_FETCH_RAND_EN : 0; val |= IBS_FETCH_ENABLE; wrmsrl(MSR_AMD64_IBSFETCHCTL, val); @@ -261,6 +270,7 @@ static inline void op_amd_start_ibs(void) * op_amd_randomize_ibs_op() for details. */ val = clamp(val, 0x0081ULL, 0xFF80ULL); + ibs_config.max_cnt_op = val << 4; } else { /* * The start value is randomized with a @@ -268,9 +278,15 @@ static inline void op_amd_start_ibs(void) * with the half of the randomized range. Also * avoid underflows. */ - val = min(val + IBS_RANDOM_MAXCNT_OFFSET, - IBS_OP_MAX_CNT); + val += IBS_RANDOM_MAXCNT_OFFSET; + if (ibs_caps & IBS_CAPS_OPCNTEXT) + val = min(val, IBS_OP_MAX_CNT_EXT); + else + val = min(val, IBS_OP_MAX_CNT); + ibs_config.max_cnt_op = + (val - IBS_RANDOM_MAXCNT_OFFSET) << 4; } + val = ((val & ~IBS_OP_MAX_CNT) << 4) | (val & IBS_OP_MAX_CNT); val |= ibs_config.dispatched_ops ? IBS_OP_CNT_CTL : 0; val |= IBS_OP_ENABLE; ibs_state.ibs_op_ctl = val; -- cgit v1.1 From 534bc7fa3c0a9084e7a2db33898d92577c64e4eb Mon Sep 17 00:00:00 2001 From: Mika Westerberg Date: Thu, 14 Oct 2010 17:49:07 +0300 Subject: ARM: ep93xx: add AC97 platform support Add platform support for the EP93xx AC97 controller driver. Signed-off-by: Mika Westerberg Acked-by: H Hartley Sweeten Acked-by: Ryan Mallon Signed-off-by: Mark Brown --- arch/arm/mach-ep93xx/core.c | 34 +++++++++++++++++++++++++ arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h | 1 + arch/arm/mach-ep93xx/include/mach/platform.h | 1 + 3 files changed, 36 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c index 1990e22..ffdf87b 100644 --- a/arch/arm/mach-ep93xx/core.c +++ b/arch/arm/mach-ep93xx/core.c @@ -832,6 +832,40 @@ void ep93xx_i2s_release(void) } EXPORT_SYMBOL(ep93xx_i2s_release); +/************************************************************************* + * EP93xx AC97 audio peripheral handling + *************************************************************************/ +static struct resource ep93xx_ac97_resources[] = { + { + .start = EP93XX_AAC_PHYS_BASE, + .end = EP93XX_AAC_PHYS_BASE + 0xb0 - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = IRQ_EP93XX_AACINTR, + .end = IRQ_EP93XX_AACINTR, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device ep93xx_ac97_device = { + .name = "ep93xx-ac97", + .id = -1, + .num_resources = ARRAY_SIZE(ep93xx_ac97_resources), + .resource = ep93xx_ac97_resources, +}; + +void __init ep93xx_register_ac97(void) +{ + /* + * Make sure that the AC97 pins are not used by I2S. + */ + ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2SONAC97); + + platform_device_register(&ep93xx_ac97_device); + platform_device_register(&ep93xx_pcm_device); +} + extern void ep93xx_gpio_init(void); void __init ep93xx_init_devices(void) diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h index c54b3e5..9ac4d10 100644 --- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h +++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h @@ -105,6 +105,7 @@ #define EP93XX_GPIO_B_INT_STATUS EP93XX_GPIO_REG(0xbc) #define EP93XX_GPIO_EEDRIVE EP93XX_GPIO_REG(0xc8) +#define EP93XX_AAC_PHYS_BASE EP93XX_APB_PHYS(0x00080000) #define EP93XX_AAC_BASE EP93XX_APB_IOMEM(0x00080000) #define EP93XX_SPI_PHYS_BASE EP93XX_APB_PHYS(0x000a0000) diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h index 3330b36..5066045 100644 --- a/arch/arm/mach-ep93xx/include/mach/platform.h +++ b/arch/arm/mach-ep93xx/include/mach/platform.h @@ -61,6 +61,7 @@ void ep93xx_keypad_release_gpio(struct platform_device *pdev); void ep93xx_register_i2s(void); int ep93xx_i2s_acquire(unsigned i2s_pins, unsigned i2s_config); void ep93xx_i2s_release(void); +void ep93xx_register_ac97(void); void ep93xx_init_devices(void); extern struct sys_timer ep93xx_timer; -- cgit v1.1 From d42a280dc76c04f39d1f9a374cf5c23318c49004 Mon Sep 17 00:00:00 2001 From: Mika Westerberg Date: Thu, 14 Oct 2010 17:49:08 +0300 Subject: ASoC: ep93xx: add Simplemachines Sim.One AC97 audio support Add AC97 audio support for Simplemachines Sim.One board. Signed-off-by: Mika Westerberg Acked-by: Liam Girdwood Signed-off-by: Mark Brown --- arch/arm/mach-ep93xx/simone.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c index 5dded58..f5f81f9 100644 --- a/arch/arm/mach-ep93xx/simone.c +++ b/arch/arm/mach-ep93xx/simone.c @@ -61,6 +61,7 @@ static void __init simone_init_machine(void) ep93xx_register_fb(&simone_fb_info); ep93xx_register_i2c(&simone_i2c_gpio_data, simone_i2c_board_info, ARRAY_SIZE(simone_i2c_board_info)); + ep93xx_register_ac97(); } MACHINE_START(SIM_ONE, "Simplemachines Sim.One Board") -- cgit v1.1 From c6c049ecbccd61fae2e58fe5e2fdd369d87f3716 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Thu, 14 Oct 2010 06:57:25 +0000 Subject: ARM: mach-shmobile: add TMU platform data for sh7372 This patch adds support for the two first channels of the TMU0 timer block on sh7372. One channel is used for clock event, the other for clock source. Signed-off-by: Magnus Damm Tested-by: Kuninori Morimoto Signed-off-by: Paul Mundt --- arch/arm/mach-shmobile/clock-sh7372.c | 5 ++- arch/arm/mach-shmobile/setup-sh7372.c | 63 +++++++++++++++++++++++++++++++++++ 2 files changed, 67 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c index 4557084..8565aef 100644 --- a/arch/arm/mach-shmobile/clock-sh7372.c +++ b/arch/arm/mach-shmobile/clock-sh7372.c @@ -419,7 +419,7 @@ static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = { enum { MSTP001, MSTP131, MSTP130, - MSTP129, MSTP128, MSTP127, MSTP126, + MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP117, MSTP116, MSTP106, MSTP101, MSTP100, MSTP223, @@ -439,6 +439,7 @@ static struct clk mstp_clks[MSTP_NR] = { [MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* VEU0 */ [MSTP127] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 27, 0), /* CEU */ [MSTP126] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 26, 0), /* CSI2 */ + [MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */ [MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX */ [MSTP117] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */ [MSTP116] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */ @@ -527,6 +528,8 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[MSTP128]), /* VEU0 */ CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[MSTP127]), /* CEU */ CLKDEV_DEV_ID("sh-mobile-csi2.0", &mstp_clks[MSTP126]), /* CSI2 */ + CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]), /* TMU00 */ + CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]), /* TMU01 */ CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX */ CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]), /* LCDC1 */ CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */ diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c index ed1324f..564a6d0 100644 --- a/arch/arm/mach-shmobile/setup-sh7372.c +++ b/arch/arm/mach-shmobile/setup-sh7372.c @@ -185,6 +185,67 @@ static struct platform_device cmt10_device = { .num_resources = ARRAY_SIZE(cmt10_resources), }; +/* TMU */ +static struct sh_timer_config tmu00_platform_data = { + .name = "TMU00", + .channel_offset = 0x4, + .timer_bit = 0, + .clockevent_rating = 200, +}; + +static struct resource tmu00_resources[] = { + [0] = { + .name = "TMU00", + .start = 0xfff60008, + .end = 0xfff60013, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = intcs_evt2irq(0xe80), /* TMU_TUNI0 */ + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device tmu00_device = { + .name = "sh_tmu", + .id = 0, + .dev = { + .platform_data = &tmu00_platform_data, + }, + .resource = tmu00_resources, + .num_resources = ARRAY_SIZE(tmu00_resources), +}; + +static struct sh_timer_config tmu01_platform_data = { + .name = "TMU01", + .channel_offset = 0x10, + .timer_bit = 1, + .clocksource_rating = 200, +}; + +static struct resource tmu01_resources[] = { + [0] = { + .name = "TMU01", + .start = 0xfff60014, + .end = 0xfff6001f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = intcs_evt2irq(0xea0), /* TMU_TUNI1 */ + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device tmu01_device = { + .name = "sh_tmu", + .id = 1, + .dev = { + .platform_data = &tmu01_platform_data, + }, + .resource = tmu01_resources, + .num_resources = ARRAY_SIZE(tmu01_resources), +}; + /* I2C */ static struct resource iic0_resources[] = { [0] = { @@ -525,6 +586,8 @@ static struct platform_device *sh7372_early_devices[] __initdata = { &scif5_device, &scif6_device, &cmt10_device, + &tmu00_device, + &tmu01_device, }; static struct platform_device *sh7372_late_devices[] __initdata = { -- cgit v1.1 From 6038f373a3dc1f1c26496e60b6c40b164716f07e Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Sun, 15 Aug 2010 18:52:59 +0200 Subject: llseek: automatically add .llseek fop All file_operations should get a .llseek operation so we can make nonseekable_open the default for future file operations without a .llseek pointer. The three cases that we can automatically detect are no_llseek, seq_lseek and default_llseek. For cases where we can we can automatically prove that the file offset is always ignored, we use noop_llseek, which maintains the current behavior of not returning an error from a seek. New drivers should normally not use noop_llseek but instead use no_llseek and call nonseekable_open at open time. Existing drivers can be converted to do the same when the maintainer knows for certain that no user code relies on calling seek on the device file. The generated code is often incorrectly indented and right now contains comments that clarify for each added line why a specific variant was chosen. In the version that gets submitted upstream, the comments will be gone and I will manually fix the indentation, because there does not seem to be a way to do that using coccinelle. Some amount of new code is currently sitting in linux-next that should get the same modifications, which I will do at the end of the merge window. Many thanks to Julia Lawall for helping me learn to write a semantic patch that does all this. ===== begin semantic patch ===== // This adds an llseek= method to all file operations, // as a preparation for making no_llseek the default. // // The rules are // - use no_llseek explicitly if we do nonseekable_open // - use seq_lseek for sequential files // - use default_llseek if we know we access f_pos // - use noop_llseek if we know we don't access f_pos, // but we still want to allow users to call lseek // @ open1 exists @ identifier nested_open; @@ nested_open(...) { <+... nonseekable_open(...) ...+> } @ open exists@ identifier open_f; identifier i, f; identifier open1.nested_open; @@ int open_f(struct inode *i, struct file *f) { <+... ( nonseekable_open(...) | nested_open(...) ) ...+> } @ read disable optional_qualifier exists @ identifier read_f; identifier f, p, s, off; type ssize_t, size_t, loff_t; expression E; identifier func; @@ ssize_t read_f(struct file *f, char *p, size_t s, loff_t *off) { <+... ( *off = E | *off += E | func(..., off, ...) | E = *off ) ...+> } @ read_no_fpos disable optional_qualifier exists @ identifier read_f; identifier f, p, s, off; type ssize_t, size_t, loff_t; @@ ssize_t read_f(struct file *f, char *p, size_t s, loff_t *off) { ... when != off } @ write @ identifier write_f; identifier f, p, s, off; type ssize_t, size_t, loff_t; expression E; identifier func; @@ ssize_t write_f(struct file *f, const char *p, size_t s, loff_t *off) { <+... ( *off = E | *off += E | func(..., off, ...) | E = *off ) ...+> } @ write_no_fpos @ identifier write_f; identifier f, p, s, off; type ssize_t, size_t, loff_t; @@ ssize_t write_f(struct file *f, const char *p, size_t s, loff_t *off) { ... when != off } @ fops0 @ identifier fops; @@ struct file_operations fops = { ... }; @ has_llseek depends on fops0 @ identifier fops0.fops; identifier llseek_f; @@ struct file_operations fops = { ... .llseek = llseek_f, ... }; @ has_read depends on fops0 @ identifier fops0.fops; identifier read_f; @@ struct file_operations fops = { ... .read = read_f, ... }; @ has_write depends on fops0 @ identifier fops0.fops; identifier write_f; @@ struct file_operations fops = { ... .write = write_f, ... }; @ has_open depends on fops0 @ identifier fops0.fops; identifier open_f; @@ struct file_operations fops = { ... .open = open_f, ... }; // use no_llseek if we call nonseekable_open //////////////////////////////////////////// @ nonseekable1 depends on !has_llseek && has_open @ identifier fops0.fops; identifier nso ~= "nonseekable_open"; @@ struct file_operations fops = { ... .open = nso, ... +.llseek = no_llseek, /* nonseekable */ }; @ nonseekable2 depends on !has_llseek @ identifier fops0.fops; identifier open.open_f; @@ struct file_operations fops = { ... .open = open_f, ... +.llseek = no_llseek, /* open uses nonseekable */ }; // use seq_lseek for sequential files ///////////////////////////////////// @ seq depends on !has_llseek @ identifier fops0.fops; identifier sr ~= "seq_read"; @@ struct file_operations fops = { ... .read = sr, ... +.llseek = seq_lseek, /* we have seq_read */ }; // use default_llseek if there is a readdir /////////////////////////////////////////// @ fops1 depends on !has_llseek && !nonseekable1 && !nonseekable2 && !seq @ identifier fops0.fops; identifier readdir_e; @@ // any other fop is used that changes pos struct file_operations fops = { ... .readdir = readdir_e, ... +.llseek = default_llseek, /* readdir is present */ }; // use default_llseek if at least one of read/write touches f_pos ///////////////////////////////////////////////////////////////// @ fops2 depends on !fops1 && !has_llseek && !nonseekable1 && !nonseekable2 && !seq @ identifier fops0.fops; identifier read.read_f; @@ // read fops use offset struct file_operations fops = { ... .read = read_f, ... +.llseek = default_llseek, /* read accesses f_pos */ }; @ fops3 depends on !fops1 && !fops2 && !has_llseek && !nonseekable1 && !nonseekable2 && !seq @ identifier fops0.fops; identifier write.write_f; @@ // write fops use offset struct file_operations fops = { ... .write = write_f, ... + .llseek = default_llseek, /* write accesses f_pos */ }; // Use noop_llseek if neither read nor write accesses f_pos /////////////////////////////////////////////////////////// @ fops4 depends on !fops1 && !fops2 && !fops3 && !has_llseek && !nonseekable1 && !nonseekable2 && !seq @ identifier fops0.fops; identifier read_no_fpos.read_f; identifier write_no_fpos.write_f; @@ // write fops use offset struct file_operations fops = { ... .write = write_f, .read = read_f, ... +.llseek = noop_llseek, /* read and write both use no f_pos */ }; @ depends on has_write && !has_read && !fops1 && !fops2 && !has_llseek && !nonseekable1 && !nonseekable2 && !seq @ identifier fops0.fops; identifier write_no_fpos.write_f; @@ struct file_operations fops = { ... .write = write_f, ... +.llseek = noop_llseek, /* write uses no f_pos */ }; @ depends on has_read && !has_write && !fops1 && !fops2 && !has_llseek && !nonseekable1 && !nonseekable2 && !seq @ identifier fops0.fops; identifier read_no_fpos.read_f; @@ struct file_operations fops = { ... .read = read_f, ... +.llseek = noop_llseek, /* read uses no f_pos */ }; @ depends on !has_read && !has_write && !fops1 && !fops2 && !has_llseek && !nonseekable1 && !nonseekable2 && !seq @ identifier fops0.fops; @@ struct file_operations fops = { ... +.llseek = noop_llseek, /* no read or write fn */ }; ===== End semantic patch ===== Signed-off-by: Arnd Bergmann Cc: Julia Lawall Cc: Christoph Hellwig --- arch/arm/kernel/etm.c | 1 + arch/arm/mach-msm/last_radio_log.c | 3 ++- arch/arm/mach-msm/smd_debug.c | 1 + arch/arm/plat-mxc/audmux-v2.c | 1 + arch/avr32/boards/mimc200/fram.c | 1 + arch/blackfin/kernel/kgdb_test.c | 1 + arch/blackfin/mach-bf561/coreb.c | 1 + arch/cris/arch-v10/drivers/ds1302.c | 1 + arch/cris/arch-v10/drivers/gpio.c | 1 + arch/cris/arch-v10/drivers/i2c.c | 1 + arch/cris/arch-v10/drivers/pcf8563.c | 1 + arch/cris/arch-v10/drivers/sync_serial.c | 3 ++- arch/cris/arch-v32/drivers/cryptocop.c | 3 ++- arch/cris/arch-v32/drivers/i2c.c | 1 + arch/cris/arch-v32/drivers/mach-a3/gpio.c | 1 + arch/cris/arch-v32/drivers/mach-fs/gpio.c | 1 + arch/cris/arch-v32/drivers/pcf8563.c | 1 + arch/cris/arch-v32/drivers/sync_serial.c | 3 ++- arch/cris/kernel/profile.c | 1 + arch/ia64/kernel/salinfo.c | 2 ++ arch/ia64/sn/kernel/sn2/sn_hwperf.c | 1 + arch/m68k/bvme6000/rtc.c | 1 + arch/m68k/mvme16x/rtc.c | 1 + arch/mips/kernel/rtlx.c | 3 ++- arch/mips/kernel/vpe.c | 3 ++- arch/mips/sibyte/common/sb_tbprof.c | 1 + arch/powerpc/kernel/lparcfg.c | 1 + arch/powerpc/kernel/rtas_flash.c | 3 +++ arch/powerpc/kernel/rtasd.c | 1 + arch/powerpc/platforms/iseries/mf.c | 1 + arch/powerpc/platforms/pseries/reconfig.c | 3 ++- arch/powerpc/platforms/pseries/scanlog.c | 1 + arch/s390/crypto/prng.c | 1 + arch/s390/hypfs/hypfs_diag.c | 1 + arch/s390/hypfs/hypfs_vm.c | 1 + arch/s390/hypfs/inode.c | 1 + arch/s390/kernel/debug.c | 1 + arch/sh/boards/mach-landisk/gio.c | 1 + arch/sparc/kernel/apc.c | 1 + arch/sparc/kernel/mdesc.c | 1 + arch/tile/kernel/hardwall.c | 1 + arch/um/drivers/harddog_kern.c | 1 + arch/um/drivers/mconsole_kern.c | 1 + arch/um/drivers/mmapper_kern.c | 1 + arch/um/drivers/random.c | 1 + arch/x86/kernel/apm_32.c | 1 + arch/x86/kernel/cpu/mcheck/mce-severity.c | 1 + arch/x86/kernel/cpu/mcheck/mce.c | 1 + arch/x86/kernel/kdebugfs.c | 1 + arch/x86/kernel/microcode_core.c | 1 + arch/x86/kernel/tlb_uv.c | 1 + arch/x86/xen/debugfs.c | 1 + 52 files changed, 62 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/kernel/etm.c b/arch/arm/kernel/etm.c index 33c7077..30b8878 100644 --- a/arch/arm/kernel/etm.c +++ b/arch/arm/kernel/etm.c @@ -314,6 +314,7 @@ static const struct file_operations etb_fops = { .read = etb_read, .open = etb_open, .release = etb_release, + .llseek = no_llseek, }; static struct miscdevice etb_miscdev = { diff --git a/arch/arm/mach-msm/last_radio_log.c b/arch/arm/mach-msm/last_radio_log.c index b64ba5a..1e243f4 100644 --- a/arch/arm/mach-msm/last_radio_log.c +++ b/arch/arm/mach-msm/last_radio_log.c @@ -48,7 +48,8 @@ static ssize_t last_radio_log_read(struct file *file, char __user *buf, } static struct file_operations last_radio_log_fops = { - .read = last_radio_log_read + .read = last_radio_log_read, + .llseek = default_llseek, }; void msm_init_last_radio_log(struct module *owner) diff --git a/arch/arm/mach-msm/smd_debug.c b/arch/arm/mach-msm/smd_debug.c index 3b2dd71..f91c3b7 100644 --- a/arch/arm/mach-msm/smd_debug.c +++ b/arch/arm/mach-msm/smd_debug.c @@ -212,6 +212,7 @@ static int debug_open(struct inode *inode, struct file *file) static const struct file_operations debug_ops = { .read = debug_read, .open = debug_open, + .llseek = default_llseek, }; static void debug_create(const char *name, mode_t mode, diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c index f9e7cdb..25ad95b 100644 --- a/arch/arm/plat-mxc/audmux-v2.c +++ b/arch/arm/plat-mxc/audmux-v2.c @@ -137,6 +137,7 @@ static ssize_t audmux_read_file(struct file *file, char __user *user_buf, static const struct file_operations audmux_debugfs_fops = { .open = audmux_open_file, .read = audmux_read_file, + .llseek = default_llseek, }; static void audmux_debugfs_init(void) diff --git a/arch/avr32/boards/mimc200/fram.c b/arch/avr32/boards/mimc200/fram.c index 54fbd95..9764a1a 100644 --- a/arch/avr32/boards/mimc200/fram.c +++ b/arch/avr32/boards/mimc200/fram.c @@ -41,6 +41,7 @@ static int fram_mmap(struct file *filp, struct vm_area_struct *vma) static const struct file_operations fram_fops = { .owner = THIS_MODULE, .mmap = fram_mmap, + .llseek = noop_llseek, }; #define FRAM_MINOR 0 diff --git a/arch/blackfin/kernel/kgdb_test.c b/arch/blackfin/kernel/kgdb_test.c index 9a4b075..08c0236 100644 --- a/arch/blackfin/kernel/kgdb_test.c +++ b/arch/blackfin/kernel/kgdb_test.c @@ -88,6 +88,7 @@ static const struct file_operations kgdb_test_proc_fops = { .owner = THIS_MODULE, .read = kgdb_test_proc_read, .write = kgdb_test_proc_write, + .llseek = noop_llseek, }; static int __init kgdbtest_init(void) diff --git a/arch/blackfin/mach-bf561/coreb.c b/arch/blackfin/mach-bf561/coreb.c index deb2271..c6a4c8f 100644 --- a/arch/blackfin/mach-bf561/coreb.c +++ b/arch/blackfin/mach-bf561/coreb.c @@ -51,6 +51,7 @@ coreb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) static const struct file_operations coreb_fops = { .owner = THIS_MODULE, .unlocked_ioctl = coreb_ioctl, + .llseek = noop_llseek, }; static struct miscdevice coreb_dev = { diff --git a/arch/cris/arch-v10/drivers/ds1302.c b/arch/cris/arch-v10/drivers/ds1302.c index 8842756..95aadb4 100644 --- a/arch/cris/arch-v10/drivers/ds1302.c +++ b/arch/cris/arch-v10/drivers/ds1302.c @@ -387,6 +387,7 @@ print_rtc_status(void) static const struct file_operations rtc_fops = { .owner = THIS_MODULE, .unlocked_ioctl = rtc_unlocked_ioctl, + .llseek = noop_llseek, }; /* Probe for the chip by writing something to its RAM and try reading it back. */ diff --git a/arch/cris/arch-v10/drivers/gpio.c b/arch/cris/arch-v10/drivers/gpio.c index a07b6d2..a276f08 100644 --- a/arch/cris/arch-v10/drivers/gpio.c +++ b/arch/cris/arch-v10/drivers/gpio.c @@ -745,6 +745,7 @@ static const struct file_operations gpio_fops = { .write = gpio_write, .open = gpio_open, .release = gpio_release, + .llseek = noop_llseek, }; static void ioif_watcher(const unsigned int gpio_in_available, diff --git a/arch/cris/arch-v10/drivers/i2c.c b/arch/cris/arch-v10/drivers/i2c.c index 77a9418..c413539 100644 --- a/arch/cris/arch-v10/drivers/i2c.c +++ b/arch/cris/arch-v10/drivers/i2c.c @@ -617,6 +617,7 @@ static const struct file_operations i2c_fops = { .unlocked_ioctl = i2c_ioctl, .open = i2c_open, .release = i2c_release, + .llseek = noop_llseek, }; int __init diff --git a/arch/cris/arch-v10/drivers/pcf8563.c b/arch/cris/arch-v10/drivers/pcf8563.c index 7dcb1f8..7aa6ff0 100644 --- a/arch/cris/arch-v10/drivers/pcf8563.c +++ b/arch/cris/arch-v10/drivers/pcf8563.c @@ -64,6 +64,7 @@ static int voltage_low; static const struct file_operations pcf8563_fops = { .owner = THIS_MODULE, .unlocked_ioctl = pcf8563_unlocked_ioctl, + .llseek = noop_llseek, }; unsigned char diff --git a/arch/cris/arch-v10/drivers/sync_serial.c b/arch/cris/arch-v10/drivers/sync_serial.c index ee2dd43..e501632 100644 --- a/arch/cris/arch-v10/drivers/sync_serial.c +++ b/arch/cris/arch-v10/drivers/sync_serial.c @@ -250,7 +250,8 @@ static const struct file_operations sync_serial_fops = { .poll = sync_serial_poll, .unlocked_ioctl = sync_serial_ioctl, .open = sync_serial_open, - .release = sync_serial_release + .release = sync_serial_release, + .llseek = noop_llseek, }; static int __init etrax_sync_serial_init(void) diff --git a/arch/cris/arch-v32/drivers/cryptocop.c b/arch/cris/arch-v32/drivers/cryptocop.c index b07646a..dcb43fd 100644 --- a/arch/cris/arch-v32/drivers/cryptocop.c +++ b/arch/cris/arch-v32/drivers/cryptocop.c @@ -281,7 +281,8 @@ const struct file_operations cryptocop_fops = { .owner = THIS_MODULE, .open = cryptocop_open, .release = cryptocop_release, - .unlocked_ioctl = cryptocop_ioctl + .unlocked_ioctl = cryptocop_ioctl, + .llseek = noop_llseek, }; diff --git a/arch/cris/arch-v32/drivers/i2c.c b/arch/cris/arch-v32/drivers/i2c.c index 5a3e900..ddb2399 100644 --- a/arch/cris/arch-v32/drivers/i2c.c +++ b/arch/cris/arch-v32/drivers/i2c.c @@ -698,6 +698,7 @@ static const struct file_operations i2c_fops = { .unlocked_ioctl = i2c_ioctl, .open = i2c_open, .release = i2c_release, + .llseek = noop_llseek, }; static int __init i2c_init(void) diff --git a/arch/cris/arch-v32/drivers/mach-a3/gpio.c b/arch/cris/arch-v32/drivers/mach-a3/gpio.c index 2dcd27a..06b24eb 100644 --- a/arch/cris/arch-v32/drivers/mach-a3/gpio.c +++ b/arch/cris/arch-v32/drivers/mach-a3/gpio.c @@ -893,6 +893,7 @@ static const struct file_operations gpio_fops = { .write = gpio_write, .open = gpio_open, .release = gpio_release, + .llseek = noop_llseek, }; #ifdef CONFIG_ETRAX_VIRTUAL_GPIO diff --git a/arch/cris/arch-v32/drivers/mach-fs/gpio.c b/arch/cris/arch-v32/drivers/mach-fs/gpio.c index 5ec8a7d..0649c8b 100644 --- a/arch/cris/arch-v32/drivers/mach-fs/gpio.c +++ b/arch/cris/arch-v32/drivers/mach-fs/gpio.c @@ -870,6 +870,7 @@ static const struct file_operations gpio_fops = { .write = gpio_write, .open = gpio_open, .release = gpio_release, + .llseek = noop_llseek, }; #ifdef CONFIG_ETRAX_VIRTUAL_GPIO diff --git a/arch/cris/arch-v32/drivers/pcf8563.c b/arch/cris/arch-v32/drivers/pcf8563.c index bef6eb5..0f7b101 100644 --- a/arch/cris/arch-v32/drivers/pcf8563.c +++ b/arch/cris/arch-v32/drivers/pcf8563.c @@ -60,6 +60,7 @@ static int voltage_low; static const struct file_operations pcf8563_fops = { .owner = THIS_MODULE, .unlocked_ioctl = pcf8563_unlocked_ioctl, + .llseek = noop_llseek, }; unsigned char diff --git a/arch/cris/arch-v32/drivers/sync_serial.c b/arch/cris/arch-v32/drivers/sync_serial.c index ca248f3..a2e8a8c 100644 --- a/arch/cris/arch-v32/drivers/sync_serial.c +++ b/arch/cris/arch-v32/drivers/sync_serial.c @@ -247,7 +247,8 @@ static const struct file_operations sync_serial_fops = { .poll = sync_serial_poll, .unlocked_ioctl = sync_serial_ioctl, .open = sync_serial_open, - .release = sync_serial_release + .release = sync_serial_release, + .llseek = noop_llseek, }; static int __init etrax_sync_serial_init(void) diff --git a/arch/cris/kernel/profile.c b/arch/cris/kernel/profile.c index 195ec5f..b82e086 100644 --- a/arch/cris/kernel/profile.c +++ b/arch/cris/kernel/profile.c @@ -59,6 +59,7 @@ write_cris_profile(struct file *file, const char __user *buf, static const struct file_operations cris_proc_profile_operations = { .read = read_cris_profile, .write = write_cris_profile, + .llseek = default_llseek, }; static int __init init_cris_profile(void) diff --git a/arch/ia64/kernel/salinfo.c b/arch/ia64/kernel/salinfo.c index aa8b5fa..6f22c40 100644 --- a/arch/ia64/kernel/salinfo.c +++ b/arch/ia64/kernel/salinfo.c @@ -354,6 +354,7 @@ retry: static const struct file_operations salinfo_event_fops = { .open = salinfo_event_open, .read = salinfo_event_read, + .llseek = noop_llseek, }; static int @@ -571,6 +572,7 @@ static const struct file_operations salinfo_data_fops = { .release = salinfo_log_release, .read = salinfo_log_read, .write = salinfo_log_write, + .llseek = default_llseek, }; static int __cpuinit diff --git a/arch/ia64/sn/kernel/sn2/sn_hwperf.c b/arch/ia64/sn/kernel/sn2/sn_hwperf.c index fa1ecee..30862c0 100644 --- a/arch/ia64/sn/kernel/sn2/sn_hwperf.c +++ b/arch/ia64/sn/kernel/sn2/sn_hwperf.c @@ -860,6 +860,7 @@ error: static const struct file_operations sn_hwperf_fops = { .unlocked_ioctl = sn_hwperf_ioctl, + .llseek = noop_llseek, }; static struct miscdevice sn_hwperf_dev = { diff --git a/arch/m68k/bvme6000/rtc.c b/arch/m68k/bvme6000/rtc.c index cb8617b..1c4d4c7 100644 --- a/arch/m68k/bvme6000/rtc.c +++ b/arch/m68k/bvme6000/rtc.c @@ -155,6 +155,7 @@ static const struct file_operations rtc_fops = { .unlocked_ioctl = rtc_ioctl, .open = rtc_open, .release = rtc_release, + .llseek = noop_llseek, }; static struct miscdevice rtc_dev = { diff --git a/arch/m68k/mvme16x/rtc.c b/arch/m68k/mvme16x/rtc.c index 11ac6f6..39c79eb 100644 --- a/arch/m68k/mvme16x/rtc.c +++ b/arch/m68k/mvme16x/rtc.c @@ -144,6 +144,7 @@ static const struct file_operations rtc_fops = { .unlocked_ioctl = rtc_ioctl, .open = rtc_open, .release = rtc_release, + .llseek = noop_llseek, }; static struct miscdevice rtc_dev= diff --git a/arch/mips/kernel/rtlx.c b/arch/mips/kernel/rtlx.c index 26f9b9a..557ef72 100644 --- a/arch/mips/kernel/rtlx.c +++ b/arch/mips/kernel/rtlx.c @@ -468,7 +468,8 @@ static const struct file_operations rtlx_fops = { .release = file_release, .write = file_write, .read = file_read, - .poll = file_poll + .poll = file_poll, + .llseek = noop_llseek, }; static struct irqaction rtlx_irq = { diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c index 2bd2151..3eb3cde 100644 --- a/arch/mips/kernel/vpe.c +++ b/arch/mips/kernel/vpe.c @@ -1192,7 +1192,8 @@ static const struct file_operations vpe_fops = { .owner = THIS_MODULE, .open = vpe_open, .release = vpe_release, - .write = vpe_write + .write = vpe_write, + .llseek = noop_llseek, }; /* module wrapper entry points */ diff --git a/arch/mips/sibyte/common/sb_tbprof.c b/arch/mips/sibyte/common/sb_tbprof.c index d4ed7a9..ca35b73 100644 --- a/arch/mips/sibyte/common/sb_tbprof.c +++ b/arch/mips/sibyte/common/sb_tbprof.c @@ -545,6 +545,7 @@ static const struct file_operations sbprof_tb_fops = { .unlocked_ioctl = sbprof_tb_ioctl, .compat_ioctl = sbprof_tb_ioctl, .mmap = NULL, + .llseek = default_llseek, }; static struct class *tb_class; diff --git a/arch/powerpc/kernel/lparcfg.c b/arch/powerpc/kernel/lparcfg.c index 50362b6..b1dd962 100644 --- a/arch/powerpc/kernel/lparcfg.c +++ b/arch/powerpc/kernel/lparcfg.c @@ -780,6 +780,7 @@ static const struct file_operations lparcfg_fops = { .write = lparcfg_write, .open = lparcfg_open, .release = single_release, + .llseek = seq_lseek, }; static int __init lparcfg_init(void) diff --git a/arch/powerpc/kernel/rtas_flash.c b/arch/powerpc/kernel/rtas_flash.c index 67a84d8..2b442e6 100644 --- a/arch/powerpc/kernel/rtas_flash.c +++ b/arch/powerpc/kernel/rtas_flash.c @@ -716,6 +716,7 @@ static const struct file_operations rtas_flash_operations = { .write = rtas_flash_write, .open = rtas_excl_open, .release = rtas_flash_release, + .llseek = default_llseek, }; static const struct file_operations manage_flash_operations = { @@ -724,6 +725,7 @@ static const struct file_operations manage_flash_operations = { .write = manage_flash_write, .open = rtas_excl_open, .release = rtas_excl_release, + .llseek = default_llseek, }; static const struct file_operations validate_flash_operations = { @@ -732,6 +734,7 @@ static const struct file_operations validate_flash_operations = { .write = validate_flash_write, .open = rtas_excl_open, .release = validate_flash_release, + .llseek = default_llseek, }; static int __init rtas_flash_init(void) diff --git a/arch/powerpc/kernel/rtasd.c b/arch/powerpc/kernel/rtasd.c index 638883e..0438f81 100644 --- a/arch/powerpc/kernel/rtasd.c +++ b/arch/powerpc/kernel/rtasd.c @@ -354,6 +354,7 @@ static const struct file_operations proc_rtas_log_operations = { .poll = rtas_log_poll, .open = rtas_log_open, .release = rtas_log_release, + .llseek = noop_llseek, }; static int enable_surveillance(int timeout) diff --git a/arch/powerpc/platforms/iseries/mf.c b/arch/powerpc/platforms/iseries/mf.c index 33e5fc7..42d0a88 100644 --- a/arch/powerpc/platforms/iseries/mf.c +++ b/arch/powerpc/platforms/iseries/mf.c @@ -1249,6 +1249,7 @@ out: static const struct file_operations proc_vmlinux_operations = { .write = proc_mf_change_vmlinux, + .llseek = default_llseek, }; static int __init mf_proc_init(void) diff --git a/arch/powerpc/platforms/pseries/reconfig.c b/arch/powerpc/platforms/pseries/reconfig.c index 57ddbb4..1de2cbb 100644 --- a/arch/powerpc/platforms/pseries/reconfig.c +++ b/arch/powerpc/platforms/pseries/reconfig.c @@ -539,7 +539,8 @@ out: } static const struct file_operations ofdt_fops = { - .write = ofdt_write + .write = ofdt_write, + .llseek = noop_llseek, }; /* create /proc/powerpc/ofdt write-only by root */ diff --git a/arch/powerpc/platforms/pseries/scanlog.c b/arch/powerpc/platforms/pseries/scanlog.c index 80e9e76..5544572 100644 --- a/arch/powerpc/platforms/pseries/scanlog.c +++ b/arch/powerpc/platforms/pseries/scanlog.c @@ -170,6 +170,7 @@ const struct file_operations scanlog_fops = { .write = scanlog_write, .open = scanlog_open, .release = scanlog_release, + .llseek = noop_llseek, }; static int __init scanlog_init(void) diff --git a/arch/s390/crypto/prng.c b/arch/s390/crypto/prng.c index aa819da..975e3ab 100644 --- a/arch/s390/crypto/prng.c +++ b/arch/s390/crypto/prng.c @@ -152,6 +152,7 @@ static const struct file_operations prng_fops = { .open = &prng_open, .release = NULL, .read = &prng_read, + .llseek = noop_llseek, }; static struct miscdevice prng_dev = { diff --git a/arch/s390/hypfs/hypfs_diag.c b/arch/s390/hypfs/hypfs_diag.c index 1211bb1..020e51c 100644 --- a/arch/s390/hypfs/hypfs_diag.c +++ b/arch/s390/hypfs/hypfs_diag.c @@ -618,6 +618,7 @@ static const struct file_operations dbfs_d204_ops = { .open = dbfs_d204_open, .read = dbfs_d204_read, .release = dbfs_d204_release, + .llseek = no_llseek, }; static int hypfs_dbfs_init(void) diff --git a/arch/s390/hypfs/hypfs_vm.c b/arch/s390/hypfs/hypfs_vm.c index ee5ab1a..26cf177 100644 --- a/arch/s390/hypfs/hypfs_vm.c +++ b/arch/s390/hypfs/hypfs_vm.c @@ -275,6 +275,7 @@ static const struct file_operations dbfs_d2fc_ops = { .open = dbfs_d2fc_open, .read = dbfs_d2fc_read, .release = dbfs_d2fc_release, + .llseek = no_llseek, }; int hypfs_vm_init(void) diff --git a/arch/s390/hypfs/inode.c b/arch/s390/hypfs/inode.c index 98a4a4c..74d9867 100644 --- a/arch/s390/hypfs/inode.c +++ b/arch/s390/hypfs/inode.c @@ -449,6 +449,7 @@ static const struct file_operations hypfs_file_ops = { .write = do_sync_write, .aio_read = hypfs_aio_read, .aio_write = hypfs_aio_write, + .llseek = no_llseek, }; static struct file_system_type hypfs_type = { diff --git a/arch/s390/kernel/debug.c b/arch/s390/kernel/debug.c index 9819226..5ad6bc0 100644 --- a/arch/s390/kernel/debug.c +++ b/arch/s390/kernel/debug.c @@ -174,6 +174,7 @@ static const struct file_operations debug_file_ops = { .write = debug_input, .open = debug_open, .release = debug_close, + .llseek = no_llseek, }; static struct dentry *debug_debugfs_root_entry; diff --git a/arch/sh/boards/mach-landisk/gio.c b/arch/sh/boards/mach-landisk/gio.c index 01e6abb..8132dff 100644 --- a/arch/sh/boards/mach-landisk/gio.c +++ b/arch/sh/boards/mach-landisk/gio.c @@ -128,6 +128,7 @@ static const struct file_operations gio_fops = { .open = gio_open, /* open */ .release = gio_close, /* release */ .unlocked_ioctl = gio_ioctl, + .llseek = noop_llseek, }; static int __init gio_init(void) diff --git a/arch/sparc/kernel/apc.c b/arch/sparc/kernel/apc.c index 2c0046e..52de4a9 100644 --- a/arch/sparc/kernel/apc.c +++ b/arch/sparc/kernel/apc.c @@ -132,6 +132,7 @@ static const struct file_operations apc_fops = { .unlocked_ioctl = apc_ioctl, .open = apc_open, .release = apc_release, + .llseek = noop_llseek, }; static struct miscdevice apc_miscdev = { APC_MINOR, APC_DEVNAME, &apc_fops }; diff --git a/arch/sparc/kernel/mdesc.c b/arch/sparc/kernel/mdesc.c index 83e85c2..6addb91 100644 --- a/arch/sparc/kernel/mdesc.c +++ b/arch/sparc/kernel/mdesc.c @@ -890,6 +890,7 @@ static ssize_t mdesc_read(struct file *file, char __user *buf, static const struct file_operations mdesc_fops = { .read = mdesc_read, .owner = THIS_MODULE, + .llseek = noop_llseek, }; static struct miscdevice mdesc_misc = { diff --git a/arch/tile/kernel/hardwall.c b/arch/tile/kernel/hardwall.c index 584b965..1e54a78 100644 --- a/arch/tile/kernel/hardwall.c +++ b/arch/tile/kernel/hardwall.c @@ -774,6 +774,7 @@ static const struct file_operations dev_hardwall_fops = { #endif .flush = hardwall_flush, .release = hardwall_release, + .llseek = noop_llseek, }; static struct cdev hardwall_dev; diff --git a/arch/um/drivers/harddog_kern.c b/arch/um/drivers/harddog_kern.c index cfcac1f..dd1e6f8 100644 --- a/arch/um/drivers/harddog_kern.c +++ b/arch/um/drivers/harddog_kern.c @@ -166,6 +166,7 @@ static const struct file_operations harddog_fops = { .unlocked_ioctl = harddog_ioctl, .open = harddog_open, .release = harddog_release, + .llseek = no_llseek, }; static struct miscdevice harddog_miscdev = { diff --git a/arch/um/drivers/mconsole_kern.c b/arch/um/drivers/mconsole_kern.c index ebc6807..975613b 100644 --- a/arch/um/drivers/mconsole_kern.c +++ b/arch/um/drivers/mconsole_kern.c @@ -843,6 +843,7 @@ static ssize_t mconsole_proc_write(struct file *file, static const struct file_operations mconsole_proc_fops = { .owner = THIS_MODULE, .write = mconsole_proc_write, + .llseek = noop_llseek, }; static int create_proc_mconsole(void) diff --git a/arch/um/drivers/mmapper_kern.c b/arch/um/drivers/mmapper_kern.c index 7158393..8501e7d 100644 --- a/arch/um/drivers/mmapper_kern.c +++ b/arch/um/drivers/mmapper_kern.c @@ -93,6 +93,7 @@ static const struct file_operations mmapper_fops = { .mmap = mmapper_mmap, .open = mmapper_open, .release = mmapper_release, + .llseek = default_llseek, }; /* diff --git a/arch/um/drivers/random.c b/arch/um/drivers/random.c index 4949044..981085a 100644 --- a/arch/um/drivers/random.c +++ b/arch/um/drivers/random.c @@ -100,6 +100,7 @@ static const struct file_operations rng_chrdev_ops = { .owner = THIS_MODULE, .open = rng_dev_open, .read = rng_dev_read, + .llseek = noop_llseek, }; /* rng_init shouldn't be called more than once at boot time */ diff --git a/arch/x86/kernel/apm_32.c b/arch/x86/kernel/apm_32.c index 4c9c67b..fbbc4da 100644 --- a/arch/x86/kernel/apm_32.c +++ b/arch/x86/kernel/apm_32.c @@ -1926,6 +1926,7 @@ static const struct file_operations apm_bios_fops = { .unlocked_ioctl = do_ioctl, .open = do_open, .release = do_release, + .llseek = noop_llseek, }; static struct miscdevice apm_device = { diff --git a/arch/x86/kernel/cpu/mcheck/mce-severity.c b/arch/x86/kernel/cpu/mcheck/mce-severity.c index 8a85dd1..1e8d66c 100644 --- a/arch/x86/kernel/cpu/mcheck/mce-severity.c +++ b/arch/x86/kernel/cpu/mcheck/mce-severity.c @@ -192,6 +192,7 @@ static const struct file_operations severities_coverage_fops = { .release = seq_release, .read = seq_read, .write = severities_coverage_write, + .llseek = seq_lseek, }; static int __init severities_debugfs_init(void) diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c index ed41562..7a35b72 100644 --- a/arch/x86/kernel/cpu/mcheck/mce.c +++ b/arch/x86/kernel/cpu/mcheck/mce.c @@ -1665,6 +1665,7 @@ struct file_operations mce_chrdev_ops = { .read = mce_read, .poll = mce_poll, .unlocked_ioctl = mce_ioctl, + .llseek = no_llseek, }; EXPORT_SYMBOL_GPL(mce_chrdev_ops); diff --git a/arch/x86/kernel/kdebugfs.c b/arch/x86/kernel/kdebugfs.c index 8afd9f3..90fcf62 100644 --- a/arch/x86/kernel/kdebugfs.c +++ b/arch/x86/kernel/kdebugfs.c @@ -78,6 +78,7 @@ static int setup_data_open(struct inode *inode, struct file *file) static const struct file_operations fops_setup_data = { .read = setup_data_read, .open = setup_data_open, + .llseek = default_llseek, }; static int __init diff --git a/arch/x86/kernel/microcode_core.c b/arch/x86/kernel/microcode_core.c index fa6551d..0b3d37e 100644 --- a/arch/x86/kernel/microcode_core.c +++ b/arch/x86/kernel/microcode_core.c @@ -232,6 +232,7 @@ static const struct file_operations microcode_fops = { .owner = THIS_MODULE, .write = microcode_write, .open = microcode_open, + .llseek = no_llseek, }; static struct miscdevice microcode_dev = { diff --git a/arch/x86/kernel/tlb_uv.c b/arch/x86/kernel/tlb_uv.c index 312ef02..50ac949 100644 --- a/arch/x86/kernel/tlb_uv.c +++ b/arch/x86/kernel/tlb_uv.c @@ -1285,6 +1285,7 @@ static const struct file_operations tunables_fops = { .open = tunables_open, .read = tunables_read, .write = tunables_write, + .llseek = default_llseek, }; static int __init uv_ptc_init(void) diff --git a/arch/x86/xen/debugfs.c b/arch/x86/xen/debugfs.c index 1304bce..7c0fedd 100644 --- a/arch/x86/xen/debugfs.c +++ b/arch/x86/xen/debugfs.c @@ -106,6 +106,7 @@ static const struct file_operations u32_array_fops = { .open = u32_array_open, .release= xen_array_release, .read = u32_array_read, + .llseek = no_llseek, }; struct dentry *xen_debugfs_create_u32_array(const char *name, mode_t mode, -- cgit v1.1 From 4fe938c5134fce1f25e1261eef6252fb47634962 Mon Sep 17 00:00:00 2001 From: Chris Metcalf Date: Thu, 14 Oct 2010 15:57:59 -0400 Subject: arch/tile: Bomb C99 comments to C89 comments in tile's Also, sync the file up the upstream version (an additional #define). Signed-off-by: Chris Metcalf --- arch/tile/include/arch/sim_def.h | 548 +++++++++++++++++++-------------------- 1 file changed, 269 insertions(+), 279 deletions(-) (limited to 'arch') diff --git a/arch/tile/include/arch/sim_def.h b/arch/tile/include/arch/sim_def.h index 6418fbd..7a17082 100644 --- a/arch/tile/include/arch/sim_def.h +++ b/arch/tile/include/arch/sim_def.h @@ -1,477 +1,461 @@ -// Copyright 2010 Tilera Corporation. All Rights Reserved. -// -// This program is free software; you can redistribute it and/or -// modify it under the terms of the GNU General Public License -// as published by the Free Software Foundation, version 2. -// -// This program is distributed in the hope that it will be useful, but -// WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or -// NON INFRINGEMENT. See the GNU General Public License for -// more details. - -//! @file -//! -//! Some low-level simulator definitions. -//! +/* + * Copyright 2010 Tilera Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation, version 2. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or + * NON INFRINGEMENT. See the GNU General Public License for + * more details. + */ + +/** + * @file + * + * Some low-level simulator definitions. + */ #ifndef __ARCH_SIM_DEF_H__ #define __ARCH_SIM_DEF_H__ -//! Internal: the low bits of the SIM_CONTROL_* SPR values specify -//! the operation to perform, and the remaining bits are -//! an operation-specific parameter (often unused). -//! +/** + * Internal: the low bits of the SIM_CONTROL_* SPR values specify + * the operation to perform, and the remaining bits are + * an operation-specific parameter (often unused). + */ #define _SIM_CONTROL_OPERATOR_BITS 8 -//== Values which can be written to SPR_SIM_CONTROL. +/* + * Values which can be written to SPR_SIM_CONTROL. + */ -//! If written to SPR_SIM_CONTROL, stops profiling. -//! +/** If written to SPR_SIM_CONTROL, stops profiling. */ #define SIM_CONTROL_PROFILER_DISABLE 0 -//! If written to SPR_SIM_CONTROL, starts profiling. -//! +/** If written to SPR_SIM_CONTROL, starts profiling. */ #define SIM_CONTROL_PROFILER_ENABLE 1 -//! If written to SPR_SIM_CONTROL, clears profiling counters. -//! +/** If written to SPR_SIM_CONTROL, clears profiling counters. */ #define SIM_CONTROL_PROFILER_CLEAR 2 -//! If written to SPR_SIM_CONTROL, checkpoints the simulator. -//! +/** If written to SPR_SIM_CONTROL, checkpoints the simulator. */ #define SIM_CONTROL_CHECKPOINT 3 -//! If written to SPR_SIM_CONTROL, combined with a mask (shifted by 8), -//! sets the tracing mask to the given mask. See "sim_set_tracing()". -//! +/** + * If written to SPR_SIM_CONTROL, combined with a mask (shifted by 8), + * sets the tracing mask to the given mask. See "sim_set_tracing()". + */ #define SIM_CONTROL_SET_TRACING 4 -//! If written to SPR_SIM_CONTROL, combined with a mask (shifted by 8), -//! dumps the requested items of machine state to the log. -//! +/** + * If written to SPR_SIM_CONTROL, combined with a mask (shifted by 8), + * dumps the requested items of machine state to the log. + */ #define SIM_CONTROL_DUMP 5 -//! If written to SPR_SIM_CONTROL, clears chip-level profiling counters. -//! +/** If written to SPR_SIM_CONTROL, clears chip-level profiling counters. */ #define SIM_CONTROL_PROFILER_CHIP_CLEAR 6 -//! If written to SPR_SIM_CONTROL, disables chip-level profiling. -//! +/** If written to SPR_SIM_CONTROL, disables chip-level profiling. */ #define SIM_CONTROL_PROFILER_CHIP_DISABLE 7 -//! If written to SPR_SIM_CONTROL, enables chip-level profiling. -//! +/** If written to SPR_SIM_CONTROL, enables chip-level profiling. */ #define SIM_CONTROL_PROFILER_CHIP_ENABLE 8 -//! If written to SPR_SIM_CONTROL, enables chip-level functional mode -//! +/** If written to SPR_SIM_CONTROL, enables chip-level functional mode */ #define SIM_CONTROL_ENABLE_FUNCTIONAL 9 -//! If written to SPR_SIM_CONTROL, disables chip-level functional mode. -//! +/** If written to SPR_SIM_CONTROL, disables chip-level functional mode. */ #define SIM_CONTROL_DISABLE_FUNCTIONAL 10 -//! If written to SPR_SIM_CONTROL, enables chip-level functional mode. -//! All tiles must perform this write for functional mode to be enabled. -//! Ignored in naked boot mode unless --functional is specified. -//! WARNING: Only the hypervisor startup code should use this! -//! +/** + * If written to SPR_SIM_CONTROL, enables chip-level functional mode. + * All tiles must perform this write for functional mode to be enabled. + * Ignored in naked boot mode unless --functional is specified. + * WARNING: Only the hypervisor startup code should use this! + */ #define SIM_CONTROL_ENABLE_FUNCTIONAL_BARRIER 11 -//! If written to SPR_SIM_CONTROL, combined with a character (shifted by 8), -//! writes a string directly to the simulator output. Written to once for -//! each character in the string, plus a final NUL. Instead of NUL, -//! you can also use "SIM_PUTC_FLUSH_STRING" or "SIM_PUTC_FLUSH_BINARY". -//! -// ISSUE: Document the meaning of "newline", and the handling of NUL. -// +/** + * If written to SPR_SIM_CONTROL, combined with a character (shifted by 8), + * writes a string directly to the simulator output. Written to once for + * each character in the string, plus a final NUL. Instead of NUL, + * you can also use "SIM_PUTC_FLUSH_STRING" or "SIM_PUTC_FLUSH_BINARY". + */ +/* ISSUE: Document the meaning of "newline", and the handling of NUL. */ #define SIM_CONTROL_PUTC 12 -//! If written to SPR_SIM_CONTROL, clears the --grind-coherence state for -//! this core. This is intended to be used before a loop that will -//! invalidate the cache by loading new data and evicting all current data. -//! Generally speaking, this API should only be used by system code. -//! +/** + * If written to SPR_SIM_CONTROL, clears the --grind-coherence state for + * this core. This is intended to be used before a loop that will + * invalidate the cache by loading new data and evicting all current data. + * Generally speaking, this API should only be used by system code. + */ #define SIM_CONTROL_GRINDER_CLEAR 13 -//! If written to SPR_SIM_CONTROL, shuts down the simulator. -//! +/** If written to SPR_SIM_CONTROL, shuts down the simulator. */ #define SIM_CONTROL_SHUTDOWN 14 -//! If written to SPR_SIM_CONTROL, combined with a pid (shifted by 8), -//! indicates that a fork syscall just created the given process. -//! +/** + * If written to SPR_SIM_CONTROL, combined with a pid (shifted by 8), + * indicates that a fork syscall just created the given process. + */ #define SIM_CONTROL_OS_FORK 15 -//! If written to SPR_SIM_CONTROL, combined with a pid (shifted by 8), -//! indicates that an exit syscall was just executed by the given process. -//! +/** + * If written to SPR_SIM_CONTROL, combined with a pid (shifted by 8), + * indicates that an exit syscall was just executed by the given process. + */ #define SIM_CONTROL_OS_EXIT 16 -//! If written to SPR_SIM_CONTROL, combined with a pid (shifted by 8), -//! indicates that the OS just switched to the given process. -//! +/** + * If written to SPR_SIM_CONTROL, combined with a pid (shifted by 8), + * indicates that the OS just switched to the given process. + */ #define SIM_CONTROL_OS_SWITCH 17 -//! If written to SPR_SIM_CONTROL, combined with a character (shifted by 8), -//! indicates that an exec syscall was just executed. Written to once for -//! each character in the executable name, plus a final NUL. -//! +/** + * If written to SPR_SIM_CONTROL, combined with a character (shifted by 8), + * indicates that an exec syscall was just executed. Written to once for + * each character in the executable name, plus a final NUL. + */ #define SIM_CONTROL_OS_EXEC 18 -//! If written to SPR_SIM_CONTROL, combined with a character (shifted by 8), -//! indicates that an interpreter (PT_INTERP) was loaded. Written to once -//! for each character in "ADDR:PATH", plus a final NUL, where "ADDR" is a -//! hex load address starting with "0x", and "PATH" is the executable name. -//! +/** + * If written to SPR_SIM_CONTROL, combined with a character (shifted by 8), + * indicates that an interpreter (PT_INTERP) was loaded. Written to once + * for each character in "ADDR:PATH", plus a final NUL, where "ADDR" is a + * hex load address starting with "0x", and "PATH" is the executable name. + */ #define SIM_CONTROL_OS_INTERP 19 -//! If written to SPR_SIM_CONTROL, combined with a character (shifted by 8), -//! indicates that a dll was loaded. Written to once for each character -//! in "ADDR:PATH", plus a final NUL, where "ADDR" is a hexadecimal load -//! address starting with "0x", and "PATH" is the executable name. -//! +/** + * If written to SPR_SIM_CONTROL, combined with a character (shifted by 8), + * indicates that a dll was loaded. Written to once for each character + * in "ADDR:PATH", plus a final NUL, where "ADDR" is a hexadecimal load + * address starting with "0x", and "PATH" is the executable name. + */ #define SIM_CONTROL_DLOPEN 20 -//! If written to SPR_SIM_CONTROL, combined with a character (shifted by 8), -//! indicates that a dll was unloaded. Written to once for each character -//! in "ADDR", plus a final NUL, where "ADDR" is a hexadecimal load -//! address starting with "0x". -//! +/** + * If written to SPR_SIM_CONTROL, combined with a character (shifted by 8), + * indicates that a dll was unloaded. Written to once for each character + * in "ADDR", plus a final NUL, where "ADDR" is a hexadecimal load + * address starting with "0x". + */ #define SIM_CONTROL_DLCLOSE 21 -//! If written to SPR_SIM_CONTROL, combined with a flag (shifted by 8), -//! indicates whether to allow data reads to remotely-cached -//! dirty cache lines to be cached locally without grinder warnings or -//! assertions (used by Linux kernel fast memcpy). -//! +/** + * If written to SPR_SIM_CONTROL, combined with a flag (shifted by 8), + * indicates whether to allow data reads to remotely-cached + * dirty cache lines to be cached locally without grinder warnings or + * assertions (used by Linux kernel fast memcpy). + */ #define SIM_CONTROL_ALLOW_MULTIPLE_CACHING 22 -//! If written to SPR_SIM_CONTROL, enables memory tracing. -//! +/** If written to SPR_SIM_CONTROL, enables memory tracing. */ #define SIM_CONTROL_ENABLE_MEM_LOGGING 23 -//! If written to SPR_SIM_CONTROL, disables memory tracing. -//! +/** If written to SPR_SIM_CONTROL, disables memory tracing. */ #define SIM_CONTROL_DISABLE_MEM_LOGGING 24 -//! If written to SPR_SIM_CONTROL, changes the shaping parameters of one of -//! the gbe or xgbe shims. Must specify the shim id, the type, the units, and -//! the rate, as defined in SIM_SHAPING_SPR_ARG. -//! +/** + * If written to SPR_SIM_CONTROL, changes the shaping parameters of one of + * the gbe or xgbe shims. Must specify the shim id, the type, the units, and + * the rate, as defined in SIM_SHAPING_SPR_ARG. + */ #define SIM_CONTROL_SHAPING 25 -//! If written to SPR_SIM_CONTROL, combined with character (shifted by 8), -//! requests that a simulator command be executed. Written to once for each -//! character in the command, plus a final NUL. -//! +/** + * If written to SPR_SIM_CONTROL, combined with character (shifted by 8), + * requests that a simulator command be executed. Written to once for each + * character in the command, plus a final NUL. + */ #define SIM_CONTROL_COMMAND 26 -//! If written to SPR_SIM_CONTROL, indicates that the simulated system -//! is panicking, to allow debugging via --debug-on-panic. -//! +/** + * If written to SPR_SIM_CONTROL, indicates that the simulated system + * is panicking, to allow debugging via --debug-on-panic. + */ #define SIM_CONTROL_PANIC 27 -//! If written to SPR_SIM_CONTROL, triggers a simulator syscall. -//! See "sim_syscall()" for more info. -//! +/** + * If written to SPR_SIM_CONTROL, triggers a simulator syscall. + * See "sim_syscall()" for more info. + */ #define SIM_CONTROL_SYSCALL 32 -//! If written to SPR_SIM_CONTROL, combined with a pid (shifted by 8), -//! provides the pid that subsequent SIM_CONTROL_OS_FORK writes should -//! use as the pid, rather than the default previous SIM_CONTROL_OS_SWITCH. -//! +/** + * If written to SPR_SIM_CONTROL, combined with a pid (shifted by 8), + * provides the pid that subsequent SIM_CONTROL_OS_FORK writes should + * use as the pid, rather than the default previous SIM_CONTROL_OS_SWITCH. + */ #define SIM_CONTROL_OS_FORK_PARENT 33 -//! If written to SPR_SIM_CONTROL, combined with a mPIPE shim number -//! (shifted by 8), clears the pending magic data section. The cleared -//! pending magic data section and any subsequently appended magic bytes -//! will only take effect when the classifier blast programmer is run. +/** + * If written to SPR_SIM_CONTROL, combined with a mPIPE shim number + * (shifted by 8), clears the pending magic data section. The cleared + * pending magic data section and any subsequently appended magic bytes + * will only take effect when the classifier blast programmer is run. + */ #define SIM_CONTROL_CLEAR_MPIPE_MAGIC_BYTES 34 -//! If written to SPR_SIM_CONTROL, combined with a mPIPE shim number -//! (shifted by 8) and a byte of data (shifted by 16), appends that byte -//! to the shim's pending magic data section. The pending magic data -//! section takes effect when the classifier blast programmer is run. +/** + * If written to SPR_SIM_CONTROL, combined with a mPIPE shim number + * (shifted by 8) and a byte of data (shifted by 16), appends that byte + * to the shim's pending magic data section. The pending magic data + * section takes effect when the classifier blast programmer is run. + */ #define SIM_CONTROL_APPEND_MPIPE_MAGIC_BYTE 35 -//! If written to SPR_SIM_CONTROL, combined with a mPIPE shim number -//! (shifted by 8), an enable=1/disable=0 bit (shifted by 16), and a -//! mask of links (shifted by 32), enable or disable the corresponding -//! mPIPE links. +/** + * If written to SPR_SIM_CONTROL, combined with a mPIPE shim number + * (shifted by 8), an enable=1/disable=0 bit (shifted by 16), and a + * mask of links (shifted by 32), enable or disable the corresponding + * mPIPE links. + */ #define SIM_CONTROL_ENABLE_MPIPE_LINK_MAGIC_BYTE 36 -//== Syscall numbers for use with "sim_syscall()". -//! Syscall number for sim_add_watchpoint(). -//! +/* + * Syscall numbers for use with "sim_syscall()". + */ + +/** Syscall number for sim_add_watchpoint(). */ #define SIM_SYSCALL_ADD_WATCHPOINT 2 -//! Syscall number for sim_remove_watchpoint(). -//! +/** Syscall number for sim_remove_watchpoint(). */ #define SIM_SYSCALL_REMOVE_WATCHPOINT 3 -//! Syscall number for sim_query_watchpoint(). -//! +/** Syscall number for sim_query_watchpoint(). */ #define SIM_SYSCALL_QUERY_WATCHPOINT 4 -//! Syscall number that asserts that the cache lines whose 64-bit PA -//! is passed as the second argument to sim_syscall(), and over a -//! range passed as the third argument, are no longer in cache. -//! The simulator raises an error if this is not the case. -//! +/** + * Syscall number that asserts that the cache lines whose 64-bit PA + * is passed as the second argument to sim_syscall(), and over a + * range passed as the third argument, are no longer in cache. + * The simulator raises an error if this is not the case. + */ #define SIM_SYSCALL_VALIDATE_LINES_EVICTED 5 -//== Bit masks which can be shifted by 8, combined with -//== SIM_CONTROL_SET_TRACING, and written to SPR_SIM_CONTROL. +/* + * Bit masks which can be shifted by 8, combined with + * SIM_CONTROL_SET_TRACING, and written to SPR_SIM_CONTROL. + */ -//! @addtogroup arch_sim -//! @{ +/** + * @addtogroup arch_sim + * @{ + */ -//! Enable --trace-cycle when passed to simulator_set_tracing(). -//! +/** Enable --trace-cycle when passed to simulator_set_tracing(). */ #define SIM_TRACE_CYCLES 0x01 -//! Enable --trace-router when passed to simulator_set_tracing(). -//! +/** Enable --trace-router when passed to simulator_set_tracing(). */ #define SIM_TRACE_ROUTER 0x02 -//! Enable --trace-register-writes when passed to simulator_set_tracing(). -//! +/** Enable --trace-register-writes when passed to simulator_set_tracing(). */ #define SIM_TRACE_REGISTER_WRITES 0x04 -//! Enable --trace-disasm when passed to simulator_set_tracing(). -//! +/** Enable --trace-disasm when passed to simulator_set_tracing(). */ #define SIM_TRACE_DISASM 0x08 -//! Enable --trace-stall-info when passed to simulator_set_tracing(). -//! +/** Enable --trace-stall-info when passed to simulator_set_tracing(). */ #define SIM_TRACE_STALL_INFO 0x10 -//! Enable --trace-memory-controller when passed to simulator_set_tracing(). -//! +/** Enable --trace-memory-controller when passed to simulator_set_tracing(). */ #define SIM_TRACE_MEMORY_CONTROLLER 0x20 -//! Enable --trace-l2 when passed to simulator_set_tracing(). -//! +/** Enable --trace-l2 when passed to simulator_set_tracing(). */ #define SIM_TRACE_L2_CACHE 0x40 -//! Enable --trace-lines when passed to simulator_set_tracing(). -//! +/** Enable --trace-lines when passed to simulator_set_tracing(). */ #define SIM_TRACE_LINES 0x80 -//! Turn off all tracing when passed to simulator_set_tracing(). -//! +/** Turn off all tracing when passed to simulator_set_tracing(). */ #define SIM_TRACE_NONE 0 -//! Turn on all tracing when passed to simulator_set_tracing(). -//! +/** Turn on all tracing when passed to simulator_set_tracing(). */ #define SIM_TRACE_ALL (-1) -//! @} +/** @} */ -//! Computes the value to write to SPR_SIM_CONTROL to set tracing flags. -//! +/** Computes the value to write to SPR_SIM_CONTROL to set tracing flags. */ #define SIM_TRACE_SPR_ARG(mask) \ (SIM_CONTROL_SET_TRACING | ((mask) << _SIM_CONTROL_OPERATOR_BITS)) -//== Bit masks which can be shifted by 8, combined with -//== SIM_CONTROL_DUMP, and written to SPR_SIM_CONTROL. +/* + * Bit masks which can be shifted by 8, combined with + * SIM_CONTROL_DUMP, and written to SPR_SIM_CONTROL. + */ -//! @addtogroup arch_sim -//! @{ +/** + * @addtogroup arch_sim + * @{ + */ -//! Dump the general-purpose registers. -//! +/** Dump the general-purpose registers. */ #define SIM_DUMP_REGS 0x001 -//! Dump the SPRs. -//! +/** Dump the SPRs. */ #define SIM_DUMP_SPRS 0x002 -//! Dump the ITLB. -//! +/** Dump the ITLB. */ #define SIM_DUMP_ITLB 0x004 -//! Dump the DTLB. -//! +/** Dump the DTLB. */ #define SIM_DUMP_DTLB 0x008 -//! Dump the L1 I-cache. -//! +/** Dump the L1 I-cache. */ #define SIM_DUMP_L1I 0x010 -//! Dump the L1 D-cache. -//! +/** Dump the L1 D-cache. */ #define SIM_DUMP_L1D 0x020 -//! Dump the L2 cache. -//! +/** Dump the L2 cache. */ #define SIM_DUMP_L2 0x040 -//! Dump the switch registers. -//! +/** Dump the switch registers. */ #define SIM_DUMP_SNREGS 0x080 -//! Dump the switch ITLB. -//! +/** Dump the switch ITLB. */ #define SIM_DUMP_SNITLB 0x100 -//! Dump the switch L1 I-cache. -//! +/** Dump the switch L1 I-cache. */ #define SIM_DUMP_SNL1I 0x200 -//! Dump the current backtrace. -//! +/** Dump the current backtrace. */ #define SIM_DUMP_BACKTRACE 0x400 -//! Only dump valid lines in caches. -//! +/** Only dump valid lines in caches. */ #define SIM_DUMP_VALID_LINES 0x800 -//! Dump everything that is dumpable. -//! +/** Dump everything that is dumpable. */ #define SIM_DUMP_ALL (-1 & ~SIM_DUMP_VALID_LINES) -// @} +/** @} */ -//! Computes the value to write to SPR_SIM_CONTROL to dump machine state. -//! +/** Computes the value to write to SPR_SIM_CONTROL to dump machine state. */ #define SIM_DUMP_SPR_ARG(mask) \ (SIM_CONTROL_DUMP | ((mask) << _SIM_CONTROL_OPERATOR_BITS)) -//== Bit masks which can be shifted by 8, combined with -//== SIM_CONTROL_PROFILER_CHIP_xxx, and written to SPR_SIM_CONTROL. +/* + * Bit masks which can be shifted by 8, combined with + * SIM_CONTROL_PROFILER_CHIP_xxx, and written to SPR_SIM_CONTROL. + */ -//! @addtogroup arch_sim -//! @{ +/** + * @addtogroup arch_sim + * @{ + */ -//! Use with with SIM_PROFILER_CHIP_xxx to control the memory controllers. -//! +/** Use with with SIM_PROFILER_CHIP_xxx to control the memory controllers. */ #define SIM_CHIP_MEMCTL 0x001 -//! Use with with SIM_PROFILER_CHIP_xxx to control the XAUI interface. -//! +/** Use with with SIM_PROFILER_CHIP_xxx to control the XAUI interface. */ #define SIM_CHIP_XAUI 0x002 -//! Use with with SIM_PROFILER_CHIP_xxx to control the PCIe interface. -//! +/** Use with with SIM_PROFILER_CHIP_xxx to control the PCIe interface. */ #define SIM_CHIP_PCIE 0x004 -//! Use with with SIM_PROFILER_CHIP_xxx to control the MPIPE interface. -//! +/** Use with with SIM_PROFILER_CHIP_xxx to control the MPIPE interface. */ #define SIM_CHIP_MPIPE 0x008 -//! Reference all chip devices. -//! +/** Use with with SIM_PROFILER_CHIP_xxx to control the TRIO interface. */ +#define SIM_CHIP_TRIO 0x010 + +/** Reference all chip devices. */ #define SIM_CHIP_ALL (-1) -//! @} +/** @} */ -//! Computes the value to write to SPR_SIM_CONTROL to clear chip statistics. -//! +/** Computes the value to write to SPR_SIM_CONTROL to clear chip statistics. */ #define SIM_PROFILER_CHIP_CLEAR_SPR_ARG(mask) \ (SIM_CONTROL_PROFILER_CHIP_CLEAR | ((mask) << _SIM_CONTROL_OPERATOR_BITS)) -//! Computes the value to write to SPR_SIM_CONTROL to disable chip statistics. -//! +/** Computes the value to write to SPR_SIM_CONTROL to disable chip statistics.*/ #define SIM_PROFILER_CHIP_DISABLE_SPR_ARG(mask) \ (SIM_CONTROL_PROFILER_CHIP_DISABLE | ((mask) << _SIM_CONTROL_OPERATOR_BITS)) -//! Computes the value to write to SPR_SIM_CONTROL to enable chip statistics. -//! +/** Computes the value to write to SPR_SIM_CONTROL to enable chip statistics. */ #define SIM_PROFILER_CHIP_ENABLE_SPR_ARG(mask) \ (SIM_CONTROL_PROFILER_CHIP_ENABLE | ((mask) << _SIM_CONTROL_OPERATOR_BITS)) -// Shim bitrate controls. +/* Shim bitrate controls. */ -//! The number of bits used to store the shim id. -//! +/** The number of bits used to store the shim id. */ #define SIM_CONTROL_SHAPING_SHIM_ID_BITS 3 -//! @addtogroup arch_sim -//! @{ +/** + * @addtogroup arch_sim + * @{ + */ -//! Change the gbe 0 bitrate. -//! +/** Change the gbe 0 bitrate. */ #define SIM_CONTROL_SHAPING_GBE_0 0x0 -//! Change the gbe 1 bitrate. -//! +/** Change the gbe 1 bitrate. */ #define SIM_CONTROL_SHAPING_GBE_1 0x1 -//! Change the gbe 2 bitrate. -//! +/** Change the gbe 2 bitrate. */ #define SIM_CONTROL_SHAPING_GBE_2 0x2 -//! Change the gbe 3 bitrate. -//! +/** Change the gbe 3 bitrate. */ #define SIM_CONTROL_SHAPING_GBE_3 0x3 -//! Change the xgbe 0 bitrate. -//! +/** Change the xgbe 0 bitrate. */ #define SIM_CONTROL_SHAPING_XGBE_0 0x4 -//! Change the xgbe 1 bitrate. -//! +/** Change the xgbe 1 bitrate. */ #define SIM_CONTROL_SHAPING_XGBE_1 0x5 -//! The type of shaping to do. -//! +/** The type of shaping to do. */ #define SIM_CONTROL_SHAPING_TYPE_BITS 2 -//! Control the multiplier. -//! +/** Control the multiplier. */ #define SIM_CONTROL_SHAPING_MULTIPLIER 0 -//! Control the PPS. -//! +/** Control the PPS. */ #define SIM_CONTROL_SHAPING_PPS 1 -//! Control the BPS. -//! +/** Control the BPS. */ #define SIM_CONTROL_SHAPING_BPS 2 -//! The number of bits for the units for the shaping parameter. -//! +/** The number of bits for the units for the shaping parameter. */ #define SIM_CONTROL_SHAPING_UNITS_BITS 2 -//! Provide a number in single units. -//! +/** Provide a number in single units. */ #define SIM_CONTROL_SHAPING_UNITS_SINGLE 0 -//! Provide a number in kilo units. -//! +/** Provide a number in kilo units. */ #define SIM_CONTROL_SHAPING_UNITS_KILO 1 -//! Provide a number in mega units. -//! +/** Provide a number in mega units. */ #define SIM_CONTROL_SHAPING_UNITS_MEGA 2 -//! Provide a number in giga units. -//! +/** Provide a number in giga units. */ #define SIM_CONTROL_SHAPING_UNITS_GIGA 3 -// @} +/** @} */ -//! How many bits are available for the rate. -//! +/** How many bits are available for the rate. */ #define SIM_CONTROL_SHAPING_RATE_BITS \ (32 - (_SIM_CONTROL_OPERATOR_BITS + \ SIM_CONTROL_SHAPING_SHIM_ID_BITS + \ SIM_CONTROL_SHAPING_TYPE_BITS + \ SIM_CONTROL_SHAPING_UNITS_BITS)) -//! Computes the value to write to SPR_SIM_CONTROL to change a bitrate. -//! +/** Computes the value to write to SPR_SIM_CONTROL to change a bitrate. */ #define SIM_SHAPING_SPR_ARG(shim, type, units, rate) \ (SIM_CONTROL_SHAPING | \ ((shim) | \ @@ -483,30 +467,36 @@ SIM_CONTROL_SHAPING_UNITS_BITS))) << _SIM_CONTROL_OPERATOR_BITS) -//== Values returned when reading SPR_SIM_CONTROL. -// ISSUE: These names should share a longer common prefix. +/* + * Values returned when reading SPR_SIM_CONTROL. + * ISSUE: These names should share a longer common prefix. + */ -//! When reading SPR_SIM_CONTROL, the mask of simulator tracing bits -//! (SIM_TRACE_xxx values). -//! +/** + * When reading SPR_SIM_CONTROL, the mask of simulator tracing bits + * (SIM_TRACE_xxx values). + */ #define SIM_TRACE_FLAG_MASK 0xFFFF -//! When reading SPR_SIM_CONTROL, the mask for whether profiling is enabled. -//! +/** When reading SPR_SIM_CONTROL, the mask for whether profiling is enabled. */ #define SIM_PROFILER_ENABLED_MASK 0x10000 -//== Special arguments for "SIM_CONTROL_PUTC". +/* + * Special arguments for "SIM_CONTROL_PUTC". + */ -//! Flag value for forcing a PUTC string-flush, including -//! coordinate/cycle prefix and newline. -//! +/** + * Flag value for forcing a PUTC string-flush, including + * coordinate/cycle prefix and newline. + */ #define SIM_PUTC_FLUSH_STRING 0x100 -//! Flag value for forcing a PUTC binary-data-flush, which skips the -//! prefix and does not append a newline. -//! +/** + * Flag value for forcing a PUTC binary-data-flush, which skips the + * prefix and does not append a newline. + */ #define SIM_PUTC_FLUSH_BINARY 0x101 -#endif //__ARCH_SIM_DEF_H__ +#endif /* __ARCH_SIM_DEF_H__ */ -- cgit v1.1 From bf65e440e8248f22b2eacf8d47961bb9d52260f7 Mon Sep 17 00:00:00 2001 From: Chris Metcalf Date: Thu, 14 Oct 2010 16:00:11 -0400 Subject: arch/tile: add Tilera's header as an open-source header This change adds one of the Tilera standard headers to the set of headers shipped with Linux. The header provides methods for programmatically interacting with the Tilera simulator. The current provides inline assembly for the _sim_syscall function, so the declaration and definition previously provided manually in Linux are no longer needed. We now use the standard sim_validate_lines_evicted() method from rather than rolling our own direct call to sim_syscall(). Signed-off-by: Chris Metcalf --- arch/tile/include/arch/sim.h | 619 +++++++++++++++++++++++++++++++++++++++++ arch/tile/include/asm/system.h | 7 - arch/tile/kernel/entry.S | 22 -- arch/tile/mm/homecache.c | 11 +- 4 files changed, 622 insertions(+), 37 deletions(-) create mode 100644 arch/tile/include/arch/sim.h (limited to 'arch') diff --git a/arch/tile/include/arch/sim.h b/arch/tile/include/arch/sim.h new file mode 100644 index 0000000..74b7c16 --- /dev/null +++ b/arch/tile/include/arch/sim.h @@ -0,0 +1,619 @@ +/* + * Copyright 2010 Tilera Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation, version 2. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or + * NON INFRINGEMENT. See the GNU General Public License for + * more details. + */ + +/** + * @file + * + * Provides an API for controlling the simulator at runtime. + */ + +/** + * @addtogroup arch_sim + * @{ + * + * An API for controlling the simulator at runtime. + * + * The simulator's behavior can be modified while it is running. + * For example, human-readable trace output can be enabled and disabled + * around code of interest. + * + * There are two ways to modify simulator behavior: + * programmatically, by calling various sim_* functions, and + * interactively, by entering commands like "sim set functional true" + * at the tile-monitor prompt. Typing "sim help" at that prompt provides + * a list of interactive commands. + * + * All interactive commands can also be executed programmatically by + * passing a string to the sim_command function. + */ + +#ifndef __ARCH_SIM_H__ +#define __ARCH_SIM_H__ + +#include +#include + +#ifndef __ASSEMBLER__ + +#include + + +/** + * Return true if the current program is running under a simulator, + * rather than on real hardware. If running on hardware, other "sim_xxx()" + * calls have no useful effect. + */ +static inline int +sim_is_simulator(void) +{ + return __insn_mfspr(SPR_SIM_CONTROL) != 0; +} + + +/** + * Checkpoint the simulator state to a checkpoint file. + * + * The checkpoint file name is either the default or the name specified + * on the command line with "--checkpoint-file". + */ +static __inline void +sim_checkpoint(void) +{ + __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_CHECKPOINT); +} + + +/** + * Report whether or not various kinds of simulator tracing are enabled. + * + * @return The bitwise OR of these values: + * + * SIM_TRACE_CYCLES (--trace-cycles), + * SIM_TRACE_ROUTER (--trace-router), + * SIM_TRACE_REGISTER_WRITES (--trace-register-writes), + * SIM_TRACE_DISASM (--trace-disasm), + * SIM_TRACE_STALL_INFO (--trace-stall-info) + * SIM_TRACE_MEMORY_CONTROLLER (--trace-memory-controller) + * SIM_TRACE_L2_CACHE (--trace-l2) + * SIM_TRACE_LINES (--trace-lines) + */ +static __inline unsigned int +sim_get_tracing(void) +{ + return __insn_mfspr(SPR_SIM_CONTROL) & SIM_TRACE_FLAG_MASK; +} + + +/** + * Turn on or off different kinds of simulator tracing. + * + * @param mask Either one of these special values: + * + * SIM_TRACE_NONE (turns off tracing), + * SIM_TRACE_ALL (turns on all possible tracing). + * + * or the bitwise OR of these values: + * + * SIM_TRACE_CYCLES (--trace-cycles), + * SIM_TRACE_ROUTER (--trace-router), + * SIM_TRACE_REGISTER_WRITES (--trace-register-writes), + * SIM_TRACE_DISASM (--trace-disasm), + * SIM_TRACE_STALL_INFO (--trace-stall-info) + * SIM_TRACE_MEMORY_CONTROLLER (--trace-memory-controller) + * SIM_TRACE_L2_CACHE (--trace-l2) + * SIM_TRACE_LINES (--trace-lines) + */ +static __inline void +sim_set_tracing(unsigned int mask) +{ + __insn_mtspr(SPR_SIM_CONTROL, SIM_TRACE_SPR_ARG(mask)); +} + + +/** + * Request dumping of different kinds of simulator state. + * + * @param mask Either this special value: + * + * SIM_DUMP_ALL (dump all known state) + * + * or the bitwise OR of these values: + * + * SIM_DUMP_REGS (the register file), + * SIM_DUMP_SPRS (the SPRs), + * SIM_DUMP_ITLB (the iTLB), + * SIM_DUMP_DTLB (the dTLB), + * SIM_DUMP_L1I (the L1 I-cache), + * SIM_DUMP_L1D (the L1 D-cache), + * SIM_DUMP_L2 (the L2 cache), + * SIM_DUMP_SNREGS (the switch register file), + * SIM_DUMP_SNITLB (the switch iTLB), + * SIM_DUMP_SNL1I (the switch L1 I-cache), + * SIM_DUMP_BACKTRACE (the current backtrace) + */ +static __inline void +sim_dump(unsigned int mask) +{ + __insn_mtspr(SPR_SIM_CONTROL, SIM_DUMP_SPR_ARG(mask)); +} + + +/** + * Print a string to the simulator stdout. + * + * @param str The string to be written; a newline is automatically added. + */ +static __inline void +sim_print_string(const char* str) +{ + int i; + for (i = 0; str[i] != 0; i++) + { + __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PUTC | + (str[i] << _SIM_CONTROL_OPERATOR_BITS)); + } + __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PUTC | + (SIM_PUTC_FLUSH_STRING << _SIM_CONTROL_OPERATOR_BITS)); +} + + +/** + * Execute a simulator command string. + * + * Type 'sim help' at the tile-monitor prompt to learn what commands + * are available. Note the use of the tile-monitor "sim" command to + * pass commands to the simulator. + * + * The argument to sim_command() does not include the leading "sim" + * prefix used at the tile-monitor prompt; for example, you might call + * sim_command("trace disasm"). + */ +static __inline void +sim_command(const char* str) +{ + int c; + do + { + c = *str++; + __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_COMMAND | + (c << _SIM_CONTROL_OPERATOR_BITS)); + } + while (c); +} + + + +#ifndef __DOXYGEN__ + +/** + * The underlying implementation of "_sim_syscall()". + * + * We use extra "and" instructions to ensure that all the values + * we are passing to the simulator are actually valid in the registers + * (i.e. returned from memory) prior to the SIM_CONTROL spr. + */ +static __inline int _sim_syscall0(int val) +{ + long result; + __asm__ __volatile__ ("mtspr SIM_CONTROL, r0" + : "=R00" (result) : "R00" (val)); + return result; +} + +static __inline int _sim_syscall1(int val, long arg1) +{ + long result; + __asm__ __volatile__ ("{ and zero, r1, r1; mtspr SIM_CONTROL, r0 }" + : "=R00" (result) : "R00" (val), "R01" (arg1)); + return result; +} + +static __inline int _sim_syscall2(int val, long arg1, long arg2) +{ + long result; + __asm__ __volatile__ ("{ and zero, r1, r2; mtspr SIM_CONTROL, r0 }" + : "=R00" (result) + : "R00" (val), "R01" (arg1), "R02" (arg2)); + return result; +} + +/* Note that _sim_syscall3() and higher are technically at risk of + receiving an interrupt right before the mtspr bundle, in which case + the register values for arguments 3 and up may still be in flight + to the core from a stack frame reload. */ + +static __inline int _sim_syscall3(int val, long arg1, long arg2, long arg3) +{ + long result; + __asm__ __volatile__ ("{ and zero, r3, r3 };" + "{ and zero, r1, r2; mtspr SIM_CONTROL, r0 }" + : "=R00" (result) + : "R00" (val), "R01" (arg1), "R02" (arg2), + "R03" (arg3)); + return result; +} + +static __inline int _sim_syscall4(int val, long arg1, long arg2, long arg3, + long arg4) +{ + long result; + __asm__ __volatile__ ("{ and zero, r3, r4 };" + "{ and zero, r1, r2; mtspr SIM_CONTROL, r0 }" + : "=R00" (result) + : "R00" (val), "R01" (arg1), "R02" (arg2), + "R03" (arg3), "R04" (arg4)); + return result; +} + +static __inline int _sim_syscall5(int val, long arg1, long arg2, long arg3, + long arg4, long arg5) +{ + long result; + __asm__ __volatile__ ("{ and zero, r3, r4; and zero, r5, r5 };" + "{ and zero, r1, r2; mtspr SIM_CONTROL, r0 }" + : "=R00" (result) + : "R00" (val), "R01" (arg1), "R02" (arg2), + "R03" (arg3), "R04" (arg4), "R05" (arg5)); + return result; +} + + +/** + * Make a special syscall to the simulator itself, if running under + * simulation. This is used as the implementation of other functions + * and should not be used outside this file. + * + * @param syscall_num The simulator syscall number. + * @param nr The number of additional arguments provided. + * + * @return Varies by syscall. + */ +#define _sim_syscall(syscall_num, nr, args...) \ + _sim_syscall##nr( \ + ((syscall_num) << _SIM_CONTROL_OPERATOR_BITS) | SIM_CONTROL_SYSCALL, args) + + +/* Values for the "access_mask" parameters below. */ +#define SIM_WATCHPOINT_READ 1 +#define SIM_WATCHPOINT_WRITE 2 +#define SIM_WATCHPOINT_EXECUTE 4 + + +static __inline int +sim_add_watchpoint(unsigned int process_id, + unsigned long address, + unsigned long size, + unsigned int access_mask, + unsigned long user_data) +{ + return _sim_syscall(SIM_SYSCALL_ADD_WATCHPOINT, 5, process_id, + address, size, access_mask, user_data); +} + + +static __inline int +sim_remove_watchpoint(unsigned int process_id, + unsigned long address, + unsigned long size, + unsigned int access_mask, + unsigned long user_data) +{ + return _sim_syscall(SIM_SYSCALL_REMOVE_WATCHPOINT, 5, process_id, + address, size, access_mask, user_data); +} + + +/** + * Return value from sim_query_watchpoint. + */ +struct SimQueryWatchpointStatus +{ + /** + * 0 if a watchpoint fired, 1 if no watchpoint fired, or -1 for + * error (meaning a bad process_id). + */ + int syscall_status; + + /** + * The address of the watchpoint that fired (this is the address + * passed to sim_add_watchpoint, not an address within that range + * that actually triggered the watchpoint). + */ + unsigned long address; + + /** The arbitrary user_data installed by sim_add_watchpoint. */ + unsigned long user_data; +}; + + +static __inline struct SimQueryWatchpointStatus +sim_query_watchpoint(unsigned int process_id) +{ + struct SimQueryWatchpointStatus status; + long val = SIM_CONTROL_SYSCALL | + (SIM_SYSCALL_QUERY_WATCHPOINT << _SIM_CONTROL_OPERATOR_BITS); + __asm__ __volatile__ ("{ and zero, r1, r1; mtspr SIM_CONTROL, r0 }" + : "=R00" (status.syscall_status), + "=R01" (status.address), + "=R02" (status.user_data) + : "R00" (val), "R01" (process_id)); + return status; +} + + +/* On the simulator, confirm lines have been evicted everywhere. */ +static __inline void +sim_validate_lines_evicted(unsigned long long pa, unsigned long length) +{ +#ifdef __LP64__ + _sim_syscall(SIM_SYSCALL_VALIDATE_LINES_EVICTED, 2, pa, length); +#else + _sim_syscall(SIM_SYSCALL_VALIDATE_LINES_EVICTED, 4, + 0 /* dummy */, (long)(pa), (long)(pa >> 32), length); +#endif +} + + +#endif /* !__DOXYGEN__ */ + + + + +/** + * Modify the shaping parameters of a shim. + * + * @param shim The shim to modify. One of: + * SIM_CONTROL_SHAPING_GBE_0 + * SIM_CONTROL_SHAPING_GBE_1 + * SIM_CONTROL_SHAPING_GBE_2 + * SIM_CONTROL_SHAPING_GBE_3 + * SIM_CONTROL_SHAPING_XGBE_0 + * SIM_CONTROL_SHAPING_XGBE_1 + * + * @param type The type of shaping. This should be the same type of + * shaping that is already in place on the shim. One of: + * SIM_CONTROL_SHAPING_MULTIPLIER + * SIM_CONTROL_SHAPING_PPS + * SIM_CONTROL_SHAPING_BPS + * + * @param units The magnitude of the rate. One of: + * SIM_CONTROL_SHAPING_UNITS_SINGLE + * SIM_CONTROL_SHAPING_UNITS_KILO + * SIM_CONTROL_SHAPING_UNITS_MEGA + * SIM_CONTROL_SHAPING_UNITS_GIGA + * + * @param rate The rate to which to change it. This must fit in + * SIM_CONTROL_SHAPING_RATE_BITS bits or a warning is issued and + * the shaping is not changed. + * + * @return 0 if no problems were detected in the arguments to sim_set_shaping + * or 1 if problems were detected (for example, rate does not fit in 17 bits). + */ +static __inline int +sim_set_shaping(unsigned shim, + unsigned type, + unsigned units, + unsigned rate) +{ + if ((rate & ~((1 << SIM_CONTROL_SHAPING_RATE_BITS) - 1)) != 0) + return 1; + + __insn_mtspr(SPR_SIM_CONTROL, SIM_SHAPING_SPR_ARG(shim, type, units, rate)); + return 0; +} + +#ifdef __tilegx__ + +/** Enable a set of mPIPE links. Pass a -1 link_mask to enable all links. */ +static __inline void +sim_enable_mpipe_links(unsigned mpipe, unsigned long link_mask) +{ + __insn_mtspr(SPR_SIM_CONTROL, + (SIM_CONTROL_ENABLE_MPIPE_LINK_MAGIC_BYTE | + (mpipe << 8) | (1 << 16) | ((uint_reg_t)link_mask << 32))); +} + +/** Disable a set of mPIPE links. Pass a -1 link_mask to disable all links. */ +static __inline void +sim_disable_mpipe_links(unsigned mpipe, unsigned long link_mask) +{ + __insn_mtspr(SPR_SIM_CONTROL, + (SIM_CONTROL_ENABLE_MPIPE_LINK_MAGIC_BYTE | + (mpipe << 8) | (0 << 16) | ((uint_reg_t)link_mask << 32))); +} + +#endif /* __tilegx__ */ + + +/* + * An API for changing "functional" mode. + */ + +#ifndef __DOXYGEN__ + +#define sim_enable_functional() \ + __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_ENABLE_FUNCTIONAL) + +#define sim_disable_functional() \ + __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_DISABLE_FUNCTIONAL) + +#endif /* __DOXYGEN__ */ + + +/* + * Profiler support. + */ + +/** + * Turn profiling on for the current task. + * + * Note that this has no effect if run in an environment without + * profiling support (thus, the proper flags to the simulator must + * be supplied). + */ +static __inline void +sim_profiler_enable(void) +{ + __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PROFILER_ENABLE); +} + + +/** Turn profiling off for the current task. */ +static __inline void +sim_profiler_disable(void) +{ + __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PROFILER_DISABLE); +} + + +/** + * Turn profiling on or off for the current task. + * + * @param enabled If true, turns on profiling. If false, turns it off. + * + * Note that this has no effect if run in an environment without + * profiling support (thus, the proper flags to the simulator must + * be supplied). + */ +static __inline void +sim_profiler_set_enabled(int enabled) +{ + int val = + enabled ? SIM_CONTROL_PROFILER_ENABLE : SIM_CONTROL_PROFILER_DISABLE; + __insn_mtspr(SPR_SIM_CONTROL, val); +} + + +/** + * Return true if and only if profiling is currently enabled + * for the current task. + * + * This returns false even if sim_profiler_enable() was called + * if the current execution environment does not support profiling. + */ +static __inline int +sim_profiler_is_enabled(void) +{ + return ((__insn_mfspr(SPR_SIM_CONTROL) & SIM_PROFILER_ENABLED_MASK) != 0); +} + + +/** + * Reset profiling counters to zero for the current task. + * + * Resetting can be done while profiling is enabled. It does not affect + * the chip-wide profiling counters. + */ +static __inline void +sim_profiler_clear(void) +{ + __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PROFILER_CLEAR); +} + + +/** + * Enable specified chip-level profiling counters. + * + * Does not affect the per-task profiling counters. + * + * @param mask Either this special value: + * + * SIM_CHIP_ALL (enables all chip-level components). + * + * or the bitwise OR of these values: + * + * SIM_CHIP_MEMCTL (enable all memory controllers) + * SIM_CHIP_XAUI (enable all XAUI controllers) + * SIM_CHIP_MPIPE (enable all MPIPE controllers) + */ +static __inline void +sim_profiler_chip_enable(unsigned int mask) +{ + __insn_mtspr(SPR_SIM_CONTROL, SIM_PROFILER_CHIP_ENABLE_SPR_ARG(mask)); +} + + +/** + * Disable specified chip-level profiling counters. + * + * Does not affect the per-task profiling counters. + * + * @param mask Either this special value: + * + * SIM_CHIP_ALL (disables all chip-level components). + * + * or the bitwise OR of these values: + * + * SIM_CHIP_MEMCTL (disable all memory controllers) + * SIM_CHIP_XAUI (disable all XAUI controllers) + * SIM_CHIP_MPIPE (disable all MPIPE controllers) + */ +static __inline void +sim_profiler_chip_disable(unsigned int mask) +{ + __insn_mtspr(SPR_SIM_CONTROL, SIM_PROFILER_CHIP_DISABLE_SPR_ARG(mask)); +} + + +/** + * Reset specified chip-level profiling counters to zero. + * + * Does not affect the per-task profiling counters. + * + * @param mask Either this special value: + * + * SIM_CHIP_ALL (clears all chip-level components). + * + * or the bitwise OR of these values: + * + * SIM_CHIP_MEMCTL (clear all memory controllers) + * SIM_CHIP_XAUI (clear all XAUI controllers) + * SIM_CHIP_MPIPE (clear all MPIPE controllers) + */ +static __inline void +sim_profiler_chip_clear(unsigned int mask) +{ + __insn_mtspr(SPR_SIM_CONTROL, SIM_PROFILER_CHIP_CLEAR_SPR_ARG(mask)); +} + + +/* + * Event support. + */ + +#ifndef __DOXYGEN__ + +static __inline void +sim_event_begin(unsigned int x) +{ +#if defined(__tile__) && !defined(__NO_EVENT_SPR__) + __insn_mtspr(SPR_EVENT_BEGIN, x); +#endif +} + +static __inline void +sim_event_end(unsigned int x) +{ +#if defined(__tile__) && !defined(__NO_EVENT_SPR__) + __insn_mtspr(SPR_EVENT_END, x); +#endif +} + +#endif /* !__DOXYGEN__ */ + +#endif /* !__ASSEMBLER__ */ + +#endif /* !__ARCH_SIM_H__ */ + +/** @} */ diff --git a/arch/tile/include/asm/system.h b/arch/tile/include/asm/system.h index 96779c8..fb7ff95 100644 --- a/arch/tile/include/asm/system.h +++ b/arch/tile/include/asm/system.h @@ -217,13 +217,6 @@ int hardwall_deactivate(struct task_struct *task); } while (0) #endif -/* Invoke the simulator "syscall" mechanism (see arch/tile/kernel/entry.S). */ -extern int _sim_syscall(int syscall_num, ...); -#define sim_syscall(syscall_num, ...) \ - _sim_syscall(SIM_CONTROL_SYSCALL + \ - ((syscall_num) << _SIM_CONTROL_OPERATOR_BITS), \ - ## __VA_ARGS__) - /* * Kernel threads can check to see if they need to migrate their * stack whenever they return from a context switch; for user diff --git a/arch/tile/kernel/entry.S b/arch/tile/kernel/entry.S index 3d01383..80d13f0 100644 --- a/arch/tile/kernel/entry.S +++ b/arch/tile/kernel/entry.S @@ -25,28 +25,6 @@ STD_ENTRY(current_text_addr) { move r0, lr; jrp lr } STD_ENDPROC(current_text_addr) -STD_ENTRY(_sim_syscall) - /* - * Wait for r0-r9 to be ready (and lr on the off chance we - * want the syscall to locate its caller), then make a magic - * simulator syscall. - * - * We carefully stall until the registers are readable in case they - * are the target of a slow load, etc. so that tile-sim will - * definitely be able to read all of them inside the magic syscall. - * - * Technically this is wrong for r3-r9 and lr, since an interrupt - * could come in and restore the registers with a slow load right - * before executing the mtspr. We may need to modify tile-sim to - * explicitly stall for this case, but we do not yet have - * a way to implement such a stall. - */ - { and zero, lr, r9 ; and zero, r8, r7 } - { and zero, r6, r5 ; and zero, r4, r3 } - { and zero, r2, r1 ; mtspr SIM_CONTROL, r0 } - { jrp lr } - STD_ENDPROC(_sim_syscall) - /* * Implement execve(). The i386 code has a note that forking from kernel * space results in no copy on write until the execve, so we should be diff --git a/arch/tile/mm/homecache.c b/arch/tile/mm/homecache.c index fb3b4a5..d78df3a 100644 --- a/arch/tile/mm/homecache.c +++ b/arch/tile/mm/homecache.c @@ -37,6 +37,8 @@ #include #include +#include + #include "migrate.h" @@ -217,13 +219,6 @@ static unsigned long cache_flush_length(unsigned long length) return (length >= CHIP_L2_CACHE_SIZE()) ? HV_FLUSH_EVICT_L2 : length; } -/* On the simulator, confirm lines have been evicted everywhere. */ -static void validate_lines_evicted(unsigned long pfn, size_t length) -{ - sim_syscall(SIM_SYSCALL_VALIDATE_LINES_EVICTED, - (HV_PhysAddr)pfn << PAGE_SHIFT, length); -} - /* Flush a page out of whatever cache(s) it is in. */ void homecache_flush_cache(struct page *page, int order) { @@ -234,7 +229,7 @@ void homecache_flush_cache(struct page *page, int order) homecache_mask(page, pages, &home_mask); flush_remote(pfn, length, &home_mask, 0, 0, 0, NULL, NULL, 0); - validate_lines_evicted(pfn, pages * PAGE_SIZE); + sim_validate_lines_evicted(PFN_PHYS(pfn), pages * PAGE_SIZE); } -- cgit v1.1 From a78c942df64ef4cf495fd4d8715e48501bd7f8a4 Mon Sep 17 00:00:00 2001 From: Chris Metcalf Date: Thu, 14 Oct 2010 16:23:03 -0400 Subject: arch/tile: parameterize system PLs to support KVM port While not a port to KVM (yet), this change modifies the kernel to be able to build either at PL1 or at PL2 with a suitable config switch. Pushing up this change avoids handling branch merge issues going forward with the KVM work. Signed-off-by: Chris Metcalf --- arch/tile/Kconfig | 12 ++++++ arch/tile/Makefile | 2 + arch/tile/include/arch/spr_def.h | 85 +++++++++++++++++++++++++++++++++++++ arch/tile/include/arch/spr_def_32.h | 39 +++++++++++++++++ arch/tile/include/asm/irqflags.h | 64 ++++++++++++++-------------- arch/tile/include/asm/page.h | 27 +++++++----- arch/tile/include/asm/processor.h | 11 +++-- arch/tile/include/asm/ptrace.h | 4 +- arch/tile/include/asm/system.h | 2 +- arch/tile/include/hv/hypervisor.h | 30 ++++++------- arch/tile/kernel/entry.S | 12 +++--- arch/tile/kernel/head_32.S | 5 ++- arch/tile/kernel/intvec_32.S | 67 +++++++++++++++-------------- arch/tile/kernel/irq.c | 16 +++---- arch/tile/kernel/messaging.c | 2 +- arch/tile/kernel/process.c | 12 +++++- arch/tile/kernel/regs_32.S | 2 +- arch/tile/kernel/setup.c | 28 ++++++------ arch/tile/kernel/smp.c | 2 +- arch/tile/kernel/traps.c | 2 +- arch/tile/kvm/Kconfig | 38 +++++++++++++++++ arch/tile/mm/fault.c | 6 +-- arch/tile/mm/init.c | 2 +- 23 files changed, 338 insertions(+), 132 deletions(-) create mode 100644 arch/tile/kvm/Kconfig (limited to 'arch') diff --git a/arch/tile/Kconfig b/arch/tile/Kconfig index 2361e3e..89cfee0 100644 --- a/arch/tile/Kconfig +++ b/arch/tile/Kconfig @@ -96,6 +96,7 @@ config HVC_TILE config TILE def_bool y + select HAVE_KVM if !TILEGX select GENERIC_FIND_FIRST_BIT select GENERIC_FIND_NEXT_BIT select USE_GENERIC_SMP_HELPERS @@ -314,6 +315,15 @@ config HARDWALL bool "Hardwall support to allow access to user dynamic network" default y +config KERNEL_PL + int "Processor protection level for kernel" + range 1 2 + default "1" + ---help--- + This setting determines the processor protection level the + kernel will be built to run at. Generally you should use + the default value here. + endmenu # Tilera-specific configuration menu "Bus options" @@ -354,3 +364,5 @@ source "security/Kconfig" source "crypto/Kconfig" source "lib/Kconfig" + +source "arch/tile/kvm/Kconfig" diff --git a/arch/tile/Makefile b/arch/tile/Makefile index a700f7f..17acce7 100644 --- a/arch/tile/Makefile +++ b/arch/tile/Makefile @@ -53,6 +53,8 @@ libs-y += $(LIBGCC_PATH) # See arch/tile/Kbuild for content of core part of the kernel core-y += arch/tile/ +core-$(CONFIG_KVM) += arch/tile/kvm/ + ifdef TILERA_ROOT INSTALL_PATH ?= $(TILERA_ROOT)/tile/boot endif diff --git a/arch/tile/include/arch/spr_def.h b/arch/tile/include/arch/spr_def.h index c8fdbd9..442fcba0 100644 --- a/arch/tile/include/arch/spr_def.h +++ b/arch/tile/include/arch/spr_def.h @@ -12,8 +12,93 @@ * more details. */ +/* + * In addition to including the proper base SPR definition file, depending + * on machine architecture, this file defines several macros which allow + * kernel code to use protection-level dependent SPRs without worrying + * about which PL it's running at. In these macros, the PL that the SPR + * or interrupt number applies to is replaced by K. + */ + +#if CONFIG_KERNEL_PL != 1 && CONFIG_KERNEL_PL != 2 +#error CONFIG_KERNEL_PL must be 1 or 2 +#endif + +/* Concatenate 4 strings. */ +#define __concat4(a, b, c, d) a ## b ## c ## d +#define _concat4(a, b, c, d) __concat4(a, b, c, d) + #ifdef __tilegx__ #include + +/* TILE-Gx dependent, protection-level dependent SPRs. */ + +#define SPR_INTERRUPT_MASK_K \ + _concat4(SPR_INTERRUPT_MASK_, CONFIG_KERNEL_PL,,) +#define SPR_INTERRUPT_MASK_SET_K \ + _concat4(SPR_INTERRUPT_MASK_SET_, CONFIG_KERNEL_PL,,) +#define SPR_INTERRUPT_MASK_RESET_K \ + _concat4(SPR_INTERRUPT_MASK_RESET_, CONFIG_KERNEL_PL,,) +#define SPR_INTERRUPT_VECTOR_BASE_K \ + _concat4(SPR_INTERRUPT_VECTOR_BASE_, CONFIG_KERNEL_PL,,) + +#define SPR_IPI_MASK_K \ + _concat4(SPR_IPI_MASK_, CONFIG_KERNEL_PL,,) +#define SPR_IPI_MASK_RESET_K \ + _concat4(SPR_IPI_MASK_RESET_, CONFIG_KERNEL_PL,,) +#define SPR_IPI_MASK_SET_K \ + _concat4(SPR_IPI_MASK_SET_, CONFIG_KERNEL_PL,,) +#define SPR_IPI_EVENT_K \ + _concat4(SPR_IPI_EVENT_, CONFIG_KERNEL_PL,,) +#define SPR_IPI_EVENT_RESET_K \ + _concat4(SPR_IPI_EVENT_RESET_, CONFIG_KERNEL_PL,,) +#define SPR_IPI_MASK_SET_K \ + _concat4(SPR_IPI_MASK_SET_, CONFIG_KERNEL_PL,,) +#define INT_IPI_K \ + _concat4(INT_IPI_, CONFIG_KERNEL_PL,,) + +#define SPR_SINGLE_STEP_CONTROL_K \ + _concat4(SPR_SINGLE_STEP_CONTROL_, CONFIG_KERNEL_PL,,) +#define SPR_SINGLE_STEP_EN_K_K \ + _concat4(SPR_SINGLE_STEP_EN_, CONFIG_KERNEL_PL, _, CONFIG_KERNEL_PL) +#define INT_SINGLE_STEP_K \ + _concat4(INT_SINGLE_STEP_, CONFIG_KERNEL_PL,,) + #else #include + +/* TILEPro dependent, protection-level dependent SPRs. */ + +#define SPR_INTERRUPT_MASK_K_0 \ + _concat4(SPR_INTERRUPT_MASK_, CONFIG_KERNEL_PL, _0,) +#define SPR_INTERRUPT_MASK_K_1 \ + _concat4(SPR_INTERRUPT_MASK_, CONFIG_KERNEL_PL, _1,) +#define SPR_INTERRUPT_MASK_SET_K_0 \ + _concat4(SPR_INTERRUPT_MASK_SET_, CONFIG_KERNEL_PL, _0,) +#define SPR_INTERRUPT_MASK_SET_K_1 \ + _concat4(SPR_INTERRUPT_MASK_SET_, CONFIG_KERNEL_PL, _1,) +#define SPR_INTERRUPT_MASK_RESET_K_0 \ + _concat4(SPR_INTERRUPT_MASK_RESET_, CONFIG_KERNEL_PL, _0,) +#define SPR_INTERRUPT_MASK_RESET_K_1 \ + _concat4(SPR_INTERRUPT_MASK_RESET_, CONFIG_KERNEL_PL, _1,) + #endif + +/* Generic protection-level dependent SPRs. */ + +#define SPR_SYSTEM_SAVE_K_0 \ + _concat4(SPR_SYSTEM_SAVE_, CONFIG_KERNEL_PL, _0,) +#define SPR_SYSTEM_SAVE_K_1 \ + _concat4(SPR_SYSTEM_SAVE_, CONFIG_KERNEL_PL, _1,) +#define SPR_SYSTEM_SAVE_K_2 \ + _concat4(SPR_SYSTEM_SAVE_, CONFIG_KERNEL_PL, _2,) +#define SPR_SYSTEM_SAVE_K_3 \ + _concat4(SPR_SYSTEM_SAVE_, CONFIG_KERNEL_PL, _3,) +#define SPR_EX_CONTEXT_K_0 \ + _concat4(SPR_EX_CONTEXT_, CONFIG_KERNEL_PL, _0,) +#define SPR_EX_CONTEXT_K_1 \ + _concat4(SPR_EX_CONTEXT_, CONFIG_KERNEL_PL, _1,) +#define SPR_INTCTRL_K_STATUS \ + _concat4(SPR_INTCTRL_, CONFIG_KERNEL_PL, _STATUS,) +#define INT_INTCTRL_K \ + _concat4(INT_INTCTRL_, CONFIG_KERNEL_PL,,) diff --git a/arch/tile/include/arch/spr_def_32.h b/arch/tile/include/arch/spr_def_32.h index b4fc068..bbc1f4c 100644 --- a/arch/tile/include/arch/spr_def_32.h +++ b/arch/tile/include/arch/spr_def_32.h @@ -56,58 +56,93 @@ #define SPR_EX_CONTEXT_1_1__ICS_SHIFT 2 #define SPR_EX_CONTEXT_1_1__ICS_RMASK 0x1 #define SPR_EX_CONTEXT_1_1__ICS_MASK 0x4 +#define SPR_EX_CONTEXT_2_0 0x4605 +#define SPR_EX_CONTEXT_2_1 0x4606 +#define SPR_EX_CONTEXT_2_1__PL_SHIFT 0 +#define SPR_EX_CONTEXT_2_1__PL_RMASK 0x3 +#define SPR_EX_CONTEXT_2_1__PL_MASK 0x3 +#define SPR_EX_CONTEXT_2_1__ICS_SHIFT 2 +#define SPR_EX_CONTEXT_2_1__ICS_RMASK 0x1 +#define SPR_EX_CONTEXT_2_1__ICS_MASK 0x4 #define SPR_FAIL 0x4e09 #define SPR_INTCTRL_0_STATUS 0x4a07 #define SPR_INTCTRL_1_STATUS 0x4807 +#define SPR_INTCTRL_2_STATUS 0x4607 #define SPR_INTERRUPT_CRITICAL_SECTION 0x4e0a #define SPR_INTERRUPT_MASK_0_0 0x4a08 #define SPR_INTERRUPT_MASK_0_1 0x4a09 #define SPR_INTERRUPT_MASK_1_0 0x4809 #define SPR_INTERRUPT_MASK_1_1 0x480a +#define SPR_INTERRUPT_MASK_2_0 0x4608 +#define SPR_INTERRUPT_MASK_2_1 0x4609 #define SPR_INTERRUPT_MASK_RESET_0_0 0x4a0a #define SPR_INTERRUPT_MASK_RESET_0_1 0x4a0b #define SPR_INTERRUPT_MASK_RESET_1_0 0x480b #define SPR_INTERRUPT_MASK_RESET_1_1 0x480c +#define SPR_INTERRUPT_MASK_RESET_2_0 0x460a +#define SPR_INTERRUPT_MASK_RESET_2_1 0x460b #define SPR_INTERRUPT_MASK_SET_0_0 0x4a0c #define SPR_INTERRUPT_MASK_SET_0_1 0x4a0d #define SPR_INTERRUPT_MASK_SET_1_0 0x480d #define SPR_INTERRUPT_MASK_SET_1_1 0x480e +#define SPR_INTERRUPT_MASK_SET_2_0 0x460c +#define SPR_INTERRUPT_MASK_SET_2_1 0x460d #define SPR_MPL_DMA_CPL_SET_0 0x5800 #define SPR_MPL_DMA_CPL_SET_1 0x5801 +#define SPR_MPL_DMA_CPL_SET_2 0x5802 #define SPR_MPL_DMA_NOTIFY_SET_0 0x3800 #define SPR_MPL_DMA_NOTIFY_SET_1 0x3801 +#define SPR_MPL_DMA_NOTIFY_SET_2 0x3802 #define SPR_MPL_INTCTRL_0_SET_0 0x4a00 #define SPR_MPL_INTCTRL_0_SET_1 0x4a01 +#define SPR_MPL_INTCTRL_0_SET_2 0x4a02 #define SPR_MPL_INTCTRL_1_SET_0 0x4800 #define SPR_MPL_INTCTRL_1_SET_1 0x4801 +#define SPR_MPL_INTCTRL_1_SET_2 0x4802 +#define SPR_MPL_INTCTRL_2_SET_0 0x4600 +#define SPR_MPL_INTCTRL_2_SET_1 0x4601 +#define SPR_MPL_INTCTRL_2_SET_2 0x4602 #define SPR_MPL_SN_ACCESS_SET_0 0x0800 #define SPR_MPL_SN_ACCESS_SET_1 0x0801 +#define SPR_MPL_SN_ACCESS_SET_2 0x0802 #define SPR_MPL_SN_CPL_SET_0 0x5a00 #define SPR_MPL_SN_CPL_SET_1 0x5a01 +#define SPR_MPL_SN_CPL_SET_2 0x5a02 #define SPR_MPL_SN_FIREWALL_SET_0 0x2c00 #define SPR_MPL_SN_FIREWALL_SET_1 0x2c01 +#define SPR_MPL_SN_FIREWALL_SET_2 0x2c02 #define SPR_MPL_SN_NOTIFY_SET_0 0x2a00 #define SPR_MPL_SN_NOTIFY_SET_1 0x2a01 +#define SPR_MPL_SN_NOTIFY_SET_2 0x2a02 #define SPR_MPL_UDN_ACCESS_SET_0 0x0c00 #define SPR_MPL_UDN_ACCESS_SET_1 0x0c01 +#define SPR_MPL_UDN_ACCESS_SET_2 0x0c02 #define SPR_MPL_UDN_AVAIL_SET_0 0x4000 #define SPR_MPL_UDN_AVAIL_SET_1 0x4001 +#define SPR_MPL_UDN_AVAIL_SET_2 0x4002 #define SPR_MPL_UDN_CA_SET_0 0x3c00 #define SPR_MPL_UDN_CA_SET_1 0x3c01 +#define SPR_MPL_UDN_CA_SET_2 0x3c02 #define SPR_MPL_UDN_COMPLETE_SET_0 0x1400 #define SPR_MPL_UDN_COMPLETE_SET_1 0x1401 +#define SPR_MPL_UDN_COMPLETE_SET_2 0x1402 #define SPR_MPL_UDN_FIREWALL_SET_0 0x3000 #define SPR_MPL_UDN_FIREWALL_SET_1 0x3001 +#define SPR_MPL_UDN_FIREWALL_SET_2 0x3002 #define SPR_MPL_UDN_REFILL_SET_0 0x1000 #define SPR_MPL_UDN_REFILL_SET_1 0x1001 +#define SPR_MPL_UDN_REFILL_SET_2 0x1002 #define SPR_MPL_UDN_TIMER_SET_0 0x3600 #define SPR_MPL_UDN_TIMER_SET_1 0x3601 +#define SPR_MPL_UDN_TIMER_SET_2 0x3602 #define SPR_MPL_WORLD_ACCESS_SET_0 0x4e00 #define SPR_MPL_WORLD_ACCESS_SET_1 0x4e01 +#define SPR_MPL_WORLD_ACCESS_SET_2 0x4e02 #define SPR_PASS 0x4e0b #define SPR_PERF_COUNT_0 0x4205 #define SPR_PERF_COUNT_1 0x4206 #define SPR_PERF_COUNT_CTL 0x4207 +#define SPR_PERF_COUNT_DN_CTL 0x4210 #define SPR_PERF_COUNT_STS 0x4208 #define SPR_PROC_STATUS 0x4f00 #define SPR_SIM_CONTROL 0x4e0c @@ -124,6 +159,10 @@ #define SPR_SYSTEM_SAVE_1_1 0x4901 #define SPR_SYSTEM_SAVE_1_2 0x4902 #define SPR_SYSTEM_SAVE_1_3 0x4903 +#define SPR_SYSTEM_SAVE_2_0 0x4700 +#define SPR_SYSTEM_SAVE_2_1 0x4701 +#define SPR_SYSTEM_SAVE_2_2 0x4702 +#define SPR_SYSTEM_SAVE_2_3 0x4703 #define SPR_TILE_COORD 0x4c17 #define SPR_TILE_RTF_HWM 0x4e10 #define SPR_TILE_TIMER_CONTROL 0x3205 diff --git a/arch/tile/include/asm/irqflags.h b/arch/tile/include/asm/irqflags.h index 45cf67c..6ebdd7d 100644 --- a/arch/tile/include/asm/irqflags.h +++ b/arch/tile/include/asm/irqflags.h @@ -47,53 +47,53 @@ int __n = (n); \ int __mask = 1 << (__n & 0x1f); \ if (__n < 32) \ - __insn_mtspr(SPR_INTERRUPT_MASK_SET_1_0, __mask); \ + __insn_mtspr(SPR_INTERRUPT_MASK_SET_K_0, __mask); \ else \ - __insn_mtspr(SPR_INTERRUPT_MASK_SET_1_1, __mask); \ + __insn_mtspr(SPR_INTERRUPT_MASK_SET_K_1, __mask); \ } while (0) #define interrupt_mask_reset(n) do { \ int __n = (n); \ int __mask = 1 << (__n & 0x1f); \ if (__n < 32) \ - __insn_mtspr(SPR_INTERRUPT_MASK_RESET_1_0, __mask); \ + __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K_0, __mask); \ else \ - __insn_mtspr(SPR_INTERRUPT_MASK_RESET_1_1, __mask); \ + __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K_1, __mask); \ } while (0) #define interrupt_mask_check(n) ({ \ int __n = (n); \ (((__n < 32) ? \ - __insn_mfspr(SPR_INTERRUPT_MASK_1_0) : \ - __insn_mfspr(SPR_INTERRUPT_MASK_1_1)) \ + __insn_mfspr(SPR_INTERRUPT_MASK_K_0) : \ + __insn_mfspr(SPR_INTERRUPT_MASK_K_1)) \ >> (__n & 0x1f)) & 1; \ }) #define interrupt_mask_set_mask(mask) do { \ unsigned long long __m = (mask); \ - __insn_mtspr(SPR_INTERRUPT_MASK_SET_1_0, (unsigned long)(__m)); \ - __insn_mtspr(SPR_INTERRUPT_MASK_SET_1_1, (unsigned long)(__m>>32)); \ + __insn_mtspr(SPR_INTERRUPT_MASK_SET_K_0, (unsigned long)(__m)); \ + __insn_mtspr(SPR_INTERRUPT_MASK_SET_K_1, (unsigned long)(__m>>32)); \ } while (0) #define interrupt_mask_reset_mask(mask) do { \ unsigned long long __m = (mask); \ - __insn_mtspr(SPR_INTERRUPT_MASK_RESET_1_0, (unsigned long)(__m)); \ - __insn_mtspr(SPR_INTERRUPT_MASK_RESET_1_1, (unsigned long)(__m>>32)); \ + __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K_0, (unsigned long)(__m)); \ + __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K_1, (unsigned long)(__m>>32)); \ } while (0) #else #define interrupt_mask_set(n) \ - __insn_mtspr(SPR_INTERRUPT_MASK_SET_1, (1UL << (n))) + __insn_mtspr(SPR_INTERRUPT_MASK_SET_K, (1UL << (n))) #define interrupt_mask_reset(n) \ - __insn_mtspr(SPR_INTERRUPT_MASK_RESET_1, (1UL << (n))) + __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K, (1UL << (n))) #define interrupt_mask_check(n) \ - ((__insn_mfspr(SPR_INTERRUPT_MASK_1) >> (n)) & 1) + ((__insn_mfspr(SPR_INTERRUPT_MASK_K) >> (n)) & 1) #define interrupt_mask_set_mask(mask) \ - __insn_mtspr(SPR_INTERRUPT_MASK_SET_1, (mask)) + __insn_mtspr(SPR_INTERRUPT_MASK_SET_K, (mask)) #define interrupt_mask_reset_mask(mask) \ - __insn_mtspr(SPR_INTERRUPT_MASK_RESET_1, (mask)) + __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K, (mask)) #endif /* * The set of interrupts we want active if irqs are enabled. * Note that in particular, the tile timer interrupt comes and goes * from this set, since we have no other way to turn off the timer. - * Likewise, INTCTRL_1 is removed and re-added during device + * Likewise, INTCTRL_K is removed and re-added during device * interrupts, as is the the hardwall UDN_FIREWALL interrupt. * We use a low bit (MEM_ERROR) as our sentinel value and make sure it * is always claimed as an "active interrupt" so we can query that bit @@ -168,14 +168,14 @@ DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask); /* Return 0 or 1 to indicate whether interrupts are currently disabled. */ #define IRQS_DISABLED(tmp) \ - mfspr tmp, INTERRUPT_MASK_1; \ + mfspr tmp, SPR_INTERRUPT_MASK_K; \ andi tmp, tmp, 1 /* Load up a pointer to &interrupts_enabled_mask. */ #define GET_INTERRUPTS_ENABLED_MASK_PTR(reg) \ - moveli reg, hw2_last(interrupts_enabled_mask); \ - shl16insli reg, reg, hw1(interrupts_enabled_mask); \ - shl16insli reg, reg, hw0(interrupts_enabled_mask); \ + moveli reg, hw2_last(interrupts_enabled_mask); \ + shl16insli reg, reg, hw1(interrupts_enabled_mask); \ + shl16insli reg, reg, hw0(interrupts_enabled_mask); \ add reg, reg, tp /* Disable interrupts. */ @@ -183,18 +183,18 @@ DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask); moveli tmp0, hw2_last(LINUX_MASKABLE_INTERRUPTS); \ shl16insli tmp0, tmp0, hw1(LINUX_MASKABLE_INTERRUPTS); \ shl16insli tmp0, tmp0, hw0(LINUX_MASKABLE_INTERRUPTS); \ - mtspr INTERRUPT_MASK_SET_1, tmp0 + mtspr SPR_INTERRUPT_MASK_SET_K, tmp0 /* Disable ALL synchronous interrupts (used by NMI entry). */ #define IRQ_DISABLE_ALL(tmp) \ movei tmp, -1; \ - mtspr INTERRUPT_MASK_SET_1, tmp + mtspr SPR_INTERRUPT_MASK_SET_K, tmp /* Enable interrupts. */ #define IRQ_ENABLE(tmp0, tmp1) \ GET_INTERRUPTS_ENABLED_MASK_PTR(tmp0); \ ld tmp0, tmp0; \ - mtspr INTERRUPT_MASK_RESET_1, tmp0 + mtspr SPR_INTERRUPT_MASK_RESET_K, tmp0 #else /* !__tilegx__ */ @@ -208,14 +208,14 @@ DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask); * (making the original code's write of the "high" mask word idempotent). */ #define IRQS_DISABLED(tmp) \ - mfspr tmp, INTERRUPT_MASK_1_0; \ + mfspr tmp, SPR_INTERRUPT_MASK_K_0; \ shri tmp, tmp, INT_MEM_ERROR; \ andi tmp, tmp, 1 /* Load up a pointer to &interrupts_enabled_mask. */ #define GET_INTERRUPTS_ENABLED_MASK_PTR(reg) \ - moveli reg, lo16(interrupts_enabled_mask); \ - auli reg, reg, ha16(interrupts_enabled_mask);\ + moveli reg, lo16(interrupts_enabled_mask); \ + auli reg, reg, ha16(interrupts_enabled_mask); \ add reg, reg, tp /* Disable interrupts. */ @@ -225,16 +225,16 @@ DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask); moveli tmp1, lo16(LINUX_MASKABLE_INTERRUPTS) \ }; \ { \ - mtspr INTERRUPT_MASK_SET_1_0, tmp0; \ + mtspr SPR_INTERRUPT_MASK_SET_K_0, tmp0; \ auli tmp1, tmp1, ha16(LINUX_MASKABLE_INTERRUPTS) \ }; \ - mtspr INTERRUPT_MASK_SET_1_1, tmp1 + mtspr SPR_INTERRUPT_MASK_SET_K_1, tmp1 /* Disable ALL synchronous interrupts (used by NMI entry). */ #define IRQ_DISABLE_ALL(tmp) \ movei tmp, -1; \ - mtspr INTERRUPT_MASK_SET_1_0, tmp; \ - mtspr INTERRUPT_MASK_SET_1_1, tmp + mtspr SPR_INTERRUPT_MASK_SET_K_0, tmp; \ + mtspr SPR_INTERRUPT_MASK_SET_K_1, tmp /* Enable interrupts. */ #define IRQ_ENABLE(tmp0, tmp1) \ @@ -244,8 +244,8 @@ DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask); addi tmp1, tmp0, 4 \ }; \ lw tmp1, tmp1; \ - mtspr INTERRUPT_MASK_RESET_1_0, tmp0; \ - mtspr INTERRUPT_MASK_RESET_1_1, tmp1 + mtspr SPR_INTERRUPT_MASK_RESET_K_0, tmp0; \ + mtspr SPR_INTERRUPT_MASK_RESET_K_1, tmp1 #endif /* diff --git a/arch/tile/include/asm/page.h b/arch/tile/include/asm/page.h index 7d90641..7979a45 100644 --- a/arch/tile/include/asm/page.h +++ b/arch/tile/include/asm/page.h @@ -199,17 +199,17 @@ static inline __attribute_const__ int get_order(unsigned long size) * If you want more physical memory than this then see the CONFIG_HIGHMEM * option in the kernel configuration. * - * The top two 16MB chunks in the table below (VIRT and HV) are - * unavailable to Linux. Since the kernel interrupt vectors must live - * at 0xfd000000, we map all of the bottom of RAM at this address with - * a huge page table entry to minimize its ITLB footprint (as well as - * at PAGE_OFFSET). The last architected requirement is that user - * interrupt vectors live at 0xfc000000, so we make that range of - * memory available to user processes. The remaining regions are sized - * as shown; after the first four addresses, we show "typical" values, - * since the actual addresses depend on kernel #defines. + * The top 16MB chunk in the table below is unavailable to Linux. Since + * the kernel interrupt vectors must live at ether 0xfe000000 or 0xfd000000 + * (depending on whether the kernel is at PL2 or Pl1), we map all of the + * bottom of RAM at this address with a huge page table entry to minimize + * its ITLB footprint (as well as at PAGE_OFFSET). The last architected + * requirement is that user interrupt vectors live at 0xfc000000, so we + * make that range of memory available to user processes. The remaining + * regions are sized as shown; the first four addresses use the PL 1 + * values, and after that, we show "typical" values, since the actual + * addresses depend on kernel #defines. * - * MEM_VIRT_INTRPT 0xff000000 * MEM_HV_INTRPT 0xfe000000 * MEM_SV_INTRPT (kernel code) 0xfd000000 * MEM_USER_INTRPT (user vector) 0xfc000000 @@ -221,9 +221,14 @@ static inline __attribute_const__ int get_order(unsigned long size) */ #define MEM_USER_INTRPT _AC(0xfc000000, UL) +#if CONFIG_KERNEL_PL == 1 #define MEM_SV_INTRPT _AC(0xfd000000, UL) #define MEM_HV_INTRPT _AC(0xfe000000, UL) -#define MEM_VIRT_INTRPT _AC(0xff000000, UL) +#else +#define MEM_GUEST_INTRPT _AC(0xfd000000, UL) +#define MEM_SV_INTRPT _AC(0xfe000000, UL) +#define MEM_HV_INTRPT _AC(0xff000000, UL) +#endif #define INTRPT_SIZE 0x4000 diff --git a/arch/tile/include/asm/processor.h b/arch/tile/include/asm/processor.h index ccd5f84..1747ff3 100644 --- a/arch/tile/include/asm/processor.h +++ b/arch/tile/include/asm/processor.h @@ -328,18 +328,21 @@ extern int kdata_huge; * Note that assembly code assumes that USER_PL is zero. */ #define USER_PL 0 -#define KERNEL_PL 1 +#if CONFIG_KERNEL_PL == 2 +#define GUEST_PL 1 +#endif +#define KERNEL_PL CONFIG_KERNEL_PL -/* SYSTEM_SAVE_1_0 holds the current cpu number ORed with ksp0. */ +/* SYSTEM_SAVE_K_0 holds the current cpu number ORed with ksp0. */ #define CPU_LOG_MASK_VALUE 12 #define CPU_MASK_VALUE ((1 << CPU_LOG_MASK_VALUE) - 1) #if CONFIG_NR_CPUS > CPU_MASK_VALUE # error Too many cpus! #endif #define raw_smp_processor_id() \ - ((int)__insn_mfspr(SPR_SYSTEM_SAVE_1_0) & CPU_MASK_VALUE) + ((int)__insn_mfspr(SPR_SYSTEM_SAVE_K_0) & CPU_MASK_VALUE) #define get_current_ksp0() \ - (__insn_mfspr(SPR_SYSTEM_SAVE_1_0) & ~CPU_MASK_VALUE) + (__insn_mfspr(SPR_SYSTEM_SAVE_K_0) & ~CPU_MASK_VALUE) #define next_current_ksp0(task) ({ \ unsigned long __ksp0 = task_ksp0(task); \ int __cpu = raw_smp_processor_id(); \ diff --git a/arch/tile/include/asm/ptrace.h b/arch/tile/include/asm/ptrace.h index 4a02bb0..ac6d343 100644 --- a/arch/tile/include/asm/ptrace.h +++ b/arch/tile/include/asm/ptrace.h @@ -62,8 +62,8 @@ struct pt_regs { pt_reg_t lr; /* aliases regs[TREG_LR] */ /* Saved special registers. */ - pt_reg_t pc; /* stored in EX_CONTEXT_1_0 */ - pt_reg_t ex1; /* stored in EX_CONTEXT_1_1 (PL and ICS bit) */ + pt_reg_t pc; /* stored in EX_CONTEXT_K_0 */ + pt_reg_t ex1; /* stored in EX_CONTEXT_K_1 (PL and ICS bit) */ pt_reg_t faultnum; /* fault number (INT_SWINT_1 for syscall) */ pt_reg_t orig_r0; /* r0 at syscall entry, else zero */ pt_reg_t flags; /* flags (see below) */ diff --git a/arch/tile/include/asm/system.h b/arch/tile/include/asm/system.h index fb7ff95..5388850 100644 --- a/arch/tile/include/asm/system.h +++ b/arch/tile/include/asm/system.h @@ -164,7 +164,7 @@ extern struct task_struct *_switch_to(struct task_struct *prev, /* Helper function for _switch_to(). */ extern struct task_struct *__switch_to(struct task_struct *prev, struct task_struct *next, - unsigned long new_system_save_1_0); + unsigned long new_system_save_k_0); /* Address that switched-away from tasks are at. */ extern unsigned long get_switch_to_pc(void); diff --git a/arch/tile/include/hv/hypervisor.h b/arch/tile/include/hv/hypervisor.h index 9bd303a..f672544 100644 --- a/arch/tile/include/hv/hypervisor.h +++ b/arch/tile/include/hv/hypervisor.h @@ -1003,37 +1003,37 @@ int hv_console_write(HV_VirtAddr bytes, int len); * when these occur in a client's interrupt critical section, they must * be delivered through the downcall mechanism. * - * A downcall is initially delivered to the client as an INTCTRL_1 - * interrupt. Upon entry to the INTCTRL_1 vector, the client must - * immediately invoke the hv_downcall_dispatch service. This service - * will not return; instead it will cause one of the client's actual - * downcall-handling interrupt vectors to be entered. The EX_CONTEXT - * registers in the client will be set so that when the client irets, - * it will return to the code which was interrupted by the INTCTRL_1 - * interrupt. - * - * Under some circumstances, the firing of INTCTRL_1 can race with + * A downcall is initially delivered to the client as an INTCTRL_CL + * interrupt, where CL is the client's PL. Upon entry to the INTCTRL_CL + * vector, the client must immediately invoke the hv_downcall_dispatch + * service. This service will not return; instead it will cause one of + * the client's actual downcall-handling interrupt vectors to be entered. + * The EX_CONTEXT registers in the client will be set so that when the + * client irets, it will return to the code which was interrupted by the + * INTCTRL_CL interrupt. + * + * Under some circumstances, the firing of INTCTRL_CL can race with * the lowering of a device interrupt. In such a case, the * hv_downcall_dispatch service may issue an iret instruction instead * of entering one of the client's actual downcall-handling interrupt * vectors. This will return execution to the location that was - * interrupted by INTCTRL_1. + * interrupted by INTCTRL_CL. * * Any saving of registers should be done by the actual handling - * vectors; no registers should be changed by the INTCTRL_1 handler. + * vectors; no registers should be changed by the INTCTRL_CL handler. * In particular, the client should not use a jal instruction to invoke * the hv_downcall_dispatch service, as that would overwrite the client's * lr register. Note that the hv_downcall_dispatch service may overwrite * one or more of the client's system save registers. * - * The client must not modify the INTCTRL_1_STATUS SPR. The hypervisor + * The client must not modify the INTCTRL_CL_STATUS SPR. The hypervisor * will set this register to cause a downcall to happen, and will clear * it when no further downcalls are pending. * - * When a downcall vector is entered, the INTCTRL_1 interrupt will be + * When a downcall vector is entered, the INTCTRL_CL interrupt will be * masked. When the client is done processing a downcall, and is ready * to accept another, it must unmask this interrupt; if more downcalls - * are pending, this will cause the INTCTRL_1 vector to be reentered. + * are pending, this will cause the INTCTRL_CL vector to be reentered. * Currently the following interrupt vectors can be entered through a * downcall: * diff --git a/arch/tile/kernel/entry.S b/arch/tile/kernel/entry.S index 80d13f0..fd8dc42 100644 --- a/arch/tile/kernel/entry.S +++ b/arch/tile/kernel/entry.S @@ -15,7 +15,9 @@ #include #include #include +#include #include +#include #ifdef __tilegx__ #define bnzt bnezt @@ -80,7 +82,7 @@ STD_ENTRY(KBacktraceIterator_init_current) STD_ENTRY(cpu_idle_on_new_stack) { move sp, r1 - mtspr SYSTEM_SAVE_1_0, r2 + mtspr SPR_SYSTEM_SAVE_K_0, r2 } jal free_thread_info j cpu_idle @@ -102,15 +104,15 @@ STD_ENTRY(smp_nap) STD_ENTRY(_cpu_idle) { lnk r0 - movei r1, 1 + movei r1, KERNEL_PL } { addli r0, r0, _cpu_idle_nap - . mtspr INTERRUPT_CRITICAL_SECTION, r1 } - IRQ_ENABLE(r2, r3) /* unmask, but still with ICS set */ - mtspr EX_CONTEXT_1_1, r1 /* PL1, ICS clear */ - mtspr EX_CONTEXT_1_0, r0 + IRQ_ENABLE(r2, r3) /* unmask, but still with ICS set */ + mtspr SPR_EX_CONTEXT_K_1, r1 /* Kernel PL, ICS clear */ + mtspr SPR_EX_CONTEXT_K_0, r0 iret .global _cpu_idle_nap _cpu_idle_nap: diff --git a/arch/tile/kernel/head_32.S b/arch/tile/kernel/head_32.S index 2b4f6c0..90e7c44 100644 --- a/arch/tile/kernel/head_32.S +++ b/arch/tile/kernel/head_32.S @@ -23,6 +23,7 @@ #include #include #include +#include /* * This module contains the entry code for kernel images. It performs the @@ -76,7 +77,7 @@ ENTRY(_start) } 1: - /* Get our processor number and save it away in SAVE_1_0. */ + /* Get our processor number and save it away in SAVE_K_0. */ jal hv_inquire_topology mulll_uu r4, r1, r2 /* r1 == y, r2 == width */ add r4, r4, r0 /* r0 == x, so r4 == cpu == y*width + x */ @@ -124,7 +125,7 @@ ENTRY(_start) lw r0, r0 lw sp, r1 or r4, sp, r4 - mtspr SYSTEM_SAVE_1_0, r4 /* save ksp0 + cpu */ + mtspr SPR_SYSTEM_SAVE_K_0, r4 /* save ksp0 + cpu */ addi sp, sp, -STACK_TOP_DELTA { move lr, zero /* stop backtraces in the called function */ diff --git a/arch/tile/kernel/intvec_32.S b/arch/tile/kernel/intvec_32.S index f87c5c0..206dc7e 100644 --- a/arch/tile/kernel/intvec_32.S +++ b/arch/tile/kernel/intvec_32.S @@ -32,8 +32,8 @@ # error "No support for kernel preemption currently" #endif -#if INT_INTCTRL_1 < 32 || INT_INTCTRL_1 >= 48 -# error INT_INTCTRL_1 coded to set high interrupt mask +#if INT_INTCTRL_K < 32 || INT_INTCTRL_K >= 48 +# error INT_INTCTRL_K coded to set high interrupt mask #endif #define PTREGS_PTR(reg, ptreg) addli reg, sp, C_ABI_SAVE_AREA_SIZE + (ptreg) @@ -132,8 +132,8 @@ intvec_\vecname: /* Temporarily save a register so we have somewhere to work. */ - mtspr SYSTEM_SAVE_1_1, r0 - mfspr r0, EX_CONTEXT_1_1 + mtspr SPR_SYSTEM_SAVE_K_1, r0 + mfspr r0, SPR_EX_CONTEXT_K_1 /* The cmpxchg code clears sp to force us to reset it here on fault. */ { @@ -167,18 +167,18 @@ intvec_\vecname: * The page_fault handler may be downcalled directly by the * hypervisor even when Linux is running and has ICS set. * - * In this case the contents of EX_CONTEXT_1_1 reflect the + * In this case the contents of EX_CONTEXT_K_1 reflect the * previous fault and can't be relied on to choose whether or * not to reinitialize the stack pointer. So we add a test - * to see whether SYSTEM_SAVE_1_2 has the high bit set, + * to see whether SYSTEM_SAVE_K_2 has the high bit set, * and if so we don't reinitialize sp, since we must be coming * from Linux. (In fact the precise case is !(val & ~1), * but any Linux PC has to have the high bit set.) * - * Note that the hypervisor *always* sets SYSTEM_SAVE_1_2 for + * Note that the hypervisor *always* sets SYSTEM_SAVE_K_2 for * any path that turns into a downcall to one of our TLB handlers. */ - mfspr r0, SYSTEM_SAVE_1_2 + mfspr r0, SPR_SYSTEM_SAVE_K_2 { blz r0, 0f /* high bit in S_S_1_2 is for a PC to use */ move r0, sp @@ -187,12 +187,12 @@ intvec_\vecname: 2: /* - * SYSTEM_SAVE_1_0 holds the cpu number in the low bits, and + * SYSTEM_SAVE_K_0 holds the cpu number in the low bits, and * the current stack top in the higher bits. So we recover * our stack top by just masking off the low bits, then * point sp at the top aligned address on the actual stack page. */ - mfspr r0, SYSTEM_SAVE_1_0 + mfspr r0, SPR_SYSTEM_SAVE_K_0 mm r0, r0, zero, LOG2_THREAD_SIZE, 31 0: @@ -254,7 +254,7 @@ intvec_\vecname: sw sp, r3 addli sp, sp, PTREGS_OFFSET_PC - PTREGS_OFFSET_REG(3) } - mfspr r0, EX_CONTEXT_1_0 + mfspr r0, SPR_EX_CONTEXT_K_0 .ifc \processing,handle_syscall /* * Bump the saved PC by one bundle so that when we return, we won't @@ -267,7 +267,7 @@ intvec_\vecname: sw sp, r0 addli sp, sp, PTREGS_OFFSET_EX1 - PTREGS_OFFSET_PC } - mfspr r0, EX_CONTEXT_1_1 + mfspr r0, SPR_EX_CONTEXT_K_1 { sw sp, r0 addi sp, sp, PTREGS_OFFSET_FAULTNUM - PTREGS_OFFSET_EX1 @@ -289,7 +289,7 @@ intvec_\vecname: .endif addli sp, sp, PTREGS_OFFSET_REG(0) - PTREGS_OFFSET_FAULTNUM } - mfspr r0, SYSTEM_SAVE_1_1 /* Original r0 */ + mfspr r0, SPR_SYSTEM_SAVE_K_1 /* Original r0 */ { sw sp, r0 addi sp, sp, -PTREGS_OFFSET_REG(0) - 4 @@ -309,12 +309,12 @@ intvec_\vecname: * See discussion below at "finish_interrupt_save". */ .ifc \c_routine, do_page_fault - mfspr r2, SYSTEM_SAVE_1_3 /* address of page fault */ - mfspr r3, SYSTEM_SAVE_1_2 /* info about page fault */ + mfspr r2, SPR_SYSTEM_SAVE_K_3 /* address of page fault */ + mfspr r3, SPR_SYSTEM_SAVE_K_2 /* info about page fault */ .else .ifc \vecnum, INT_DOUBLE_FAULT { - mfspr r2, SYSTEM_SAVE_1_2 /* double fault info from HV */ + mfspr r2, SPR_SYSTEM_SAVE_K_2 /* double fault info from HV */ movei r3, 0 } .else @@ -467,7 +467,7 @@ intvec_\vecname: /* Load tp with our per-cpu offset. */ #ifdef CONFIG_SMP { - mfspr r20, SYSTEM_SAVE_1_0 + mfspr r20, SPR_SYSTEM_SAVE_K_0 moveli r21, lo16(__per_cpu_offset) } { @@ -487,7 +487,7 @@ intvec_\vecname: * We load flags in r32 here so we can jump to .Lrestore_regs * directly after do_page_fault_ics() if necessary. */ - mfspr r32, EX_CONTEXT_1_1 + mfspr r32, SPR_EX_CONTEXT_K_1 { andi r32, r32, SPR_EX_CONTEXT_1_1__PL_MASK /* mask off ICS */ PTREGS_PTR(r21, PTREGS_OFFSET_FLAGS) @@ -957,11 +957,11 @@ STD_ENTRY(interrupt_return) pop_reg_zero r21, r3, sp, PTREGS_OFFSET_EX1 - PTREGS_OFFSET_PC pop_reg_zero lr, r4, sp, PTREGS_OFFSET_REG(52) - PTREGS_OFFSET_EX1 { - mtspr EX_CONTEXT_1_0, r21 + mtspr SPR_EX_CONTEXT_K_0, r21 move r5, zero } { - mtspr EX_CONTEXT_1_1, lr + mtspr SPR_EX_CONTEXT_K_1, lr andi lr, lr, SPR_EX_CONTEXT_1_1__PL_MASK /* mask off ICS */ } @@ -1199,7 +1199,7 @@ STD_ENTRY(interrupt_return) STD_ENDPROC(interrupt_return) /* - * This interrupt variant clears the INT_INTCTRL_1 interrupt mask bit + * This interrupt variant clears the INT_INTCTRL_K interrupt mask bit * before returning, so we can properly get more downcalls. */ .pushsection .text.handle_interrupt_downcall,"ax" @@ -1208,11 +1208,11 @@ handle_interrupt_downcall: check_single_stepping normal, .Ldispatch_downcall .Ldispatch_downcall: - /* Clear INTCTRL_1 from the set of interrupts we ever enable. */ + /* Clear INTCTRL_K from the set of interrupts we ever enable. */ GET_INTERRUPTS_ENABLED_MASK_PTR(r30) { addi r30, r30, 4 - movei r31, INT_MASK(INT_INTCTRL_1) + movei r31, INT_MASK(INT_INTCTRL_K) } { lw r20, r30 @@ -1227,7 +1227,7 @@ handle_interrupt_downcall: } FEEDBACK_REENTER(handle_interrupt_downcall) - /* Allow INTCTRL_1 to be enabled next time we enable interrupts. */ + /* Allow INTCTRL_K to be enabled next time we enable interrupts. */ lw r20, r30 or r20, r20, r31 sw r30, r20 @@ -1509,7 +1509,7 @@ handle_ill: /* Various stub interrupt handlers and syscall handlers */ STD_ENTRY_LOCAL(_kernel_double_fault) - mfspr r1, EX_CONTEXT_1_0 + mfspr r1, SPR_EX_CONTEXT_K_0 move r2, lr move r3, sp move r4, r52 @@ -1518,7 +1518,7 @@ STD_ENTRY_LOCAL(_kernel_double_fault) STD_ENDPROC(_kernel_double_fault) STD_ENTRY_LOCAL(bad_intr) - mfspr r2, EX_CONTEXT_1_0 + mfspr r2, SPR_EX_CONTEXT_K_0 panic "Unhandled interrupt %#x: PC %#lx" STD_ENDPROC(bad_intr) @@ -1560,7 +1560,7 @@ STD_ENTRY(_sys_clone) * a page fault which would assume the stack was valid, it does * save/restore the stack pointer and zero it out to make sure it gets reset. * Since we always keep interrupts disabled, the hypervisor won't - * clobber our EX_CONTEXT_1_x registers, so we don't save/restore them + * clobber our EX_CONTEXT_K_x registers, so we don't save/restore them * (other than to advance the PC on return). * * We have to manually validate the user vs kernel address range @@ -1766,7 +1766,7 @@ ENTRY(sys_cmpxchg) /* Do slow mtspr here so the following "mf" waits less. */ { move sp, r27 - mtspr EX_CONTEXT_1_0, r28 + mtspr SPR_EX_CONTEXT_K_0, r28 } mf @@ -1785,7 +1785,7 @@ ENTRY(sys_cmpxchg) } { move sp, r27 - mtspr EX_CONTEXT_1_0, r28 + mtspr SPR_EX_CONTEXT_K_0, r28 } iret @@ -1813,7 +1813,7 @@ ENTRY(sys_cmpxchg) #endif /* Issue the slow SPR here while the tns result is in flight. */ - mfspr r28, EX_CONTEXT_1_0 + mfspr r28, SPR_EX_CONTEXT_K_0 { addi r28, r28, 8 /* return to the instruction after the swint1 */ @@ -1901,7 +1901,7 @@ ENTRY(sys_cmpxchg) .Lcmpxchg64_mismatch: { move sp, r27 - mtspr EX_CONTEXT_1_0, r28 + mtspr SPR_EX_CONTEXT_K_0, r28 } mf { @@ -1982,8 +1982,13 @@ int_unalign: int_hand INT_PERF_COUNT, PERF_COUNT, \ op_handle_perf_interrupt, handle_nmi int_hand INT_INTCTRL_3, INTCTRL_3, bad_intr +#if CONFIG_KERNEL_PL == 2 + dc_dispatch INT_INTCTRL_2, INTCTRL_2 + int_hand INT_INTCTRL_1, INTCTRL_1, bad_intr +#else int_hand INT_INTCTRL_2, INTCTRL_2, bad_intr dc_dispatch INT_INTCTRL_1, INTCTRL_1 +#endif int_hand INT_INTCTRL_0, INTCTRL_0, bad_intr int_hand INT_MESSAGE_RCV_DWNCL, MESSAGE_RCV_DWNCL, \ hv_message_intr, handle_interrupt_downcall diff --git a/arch/tile/kernel/irq.c b/arch/tile/kernel/irq.c index 596c600..394d554 100644 --- a/arch/tile/kernel/irq.c +++ b/arch/tile/kernel/irq.c @@ -61,9 +61,9 @@ static DEFINE_SPINLOCK(available_irqs_lock); #if CHIP_HAS_IPI() /* Use SPRs to manipulate device interrupts. */ -#define mask_irqs(irq_mask) __insn_mtspr(SPR_IPI_MASK_SET_1, irq_mask) -#define unmask_irqs(irq_mask) __insn_mtspr(SPR_IPI_MASK_RESET_1, irq_mask) -#define clear_irqs(irq_mask) __insn_mtspr(SPR_IPI_EVENT_RESET_1, irq_mask) +#define mask_irqs(irq_mask) __insn_mtspr(SPR_IPI_MASK_SET_K, irq_mask) +#define unmask_irqs(irq_mask) __insn_mtspr(SPR_IPI_MASK_RESET_K, irq_mask) +#define clear_irqs(irq_mask) __insn_mtspr(SPR_IPI_EVENT_RESET_K, irq_mask) #else /* Use HV to manipulate device interrupts. */ #define mask_irqs(irq_mask) hv_disable_intr(irq_mask) @@ -89,16 +89,16 @@ void tile_dev_intr(struct pt_regs *regs, int intnum) * masked by a previous interrupt. Then, mask out the ones * we're going to handle. */ - unsigned long masked = __insn_mfspr(SPR_IPI_MASK_1); - original_irqs = __insn_mfspr(SPR_IPI_EVENT_1) & ~masked; - __insn_mtspr(SPR_IPI_MASK_SET_1, original_irqs); + unsigned long masked = __insn_mfspr(SPR_IPI_MASK_K); + original_irqs = __insn_mfspr(SPR_IPI_EVENT_K) & ~masked; + __insn_mtspr(SPR_IPI_MASK_SET_K, original_irqs); #else /* * Hypervisor performs the equivalent of the Gx code above and * then puts the pending interrupt mask into a system save reg * for us to find. */ - original_irqs = __insn_mfspr(SPR_SYSTEM_SAVE_1_3); + original_irqs = __insn_mfspr(SPR_SYSTEM_SAVE_K_3); #endif remaining_irqs = original_irqs; @@ -225,7 +225,7 @@ void __cpuinit setup_irq_regs(void) /* Enable interrupt delivery. */ unmask_irqs(~0UL); #if CHIP_HAS_IPI() - raw_local_irq_unmask(INT_IPI_1); + raw_local_irq_unmask(INT_IPI_K); #endif } diff --git a/arch/tile/kernel/messaging.c b/arch/tile/kernel/messaging.c index 6d23ed2..997e393 100644 --- a/arch/tile/kernel/messaging.c +++ b/arch/tile/kernel/messaging.c @@ -34,7 +34,7 @@ void __cpuinit init_messaging(void) panic("hv_register_message_state: error %d", rc); /* Make sure downcall interrupts will be enabled. */ - raw_local_irq_unmask(INT_INTCTRL_1); + raw_local_irq_unmask(INT_INTCTRL_K); } void hv_message_intr(struct pt_regs *regs, int intnum) diff --git a/arch/tile/kernel/process.c b/arch/tile/kernel/process.c index 221f12b..8430f45 100644 --- a/arch/tile/kernel/process.c +++ b/arch/tile/kernel/process.c @@ -305,15 +305,25 @@ int dump_task_regs(struct task_struct *tsk, elf_gregset_t *regs) /* Allow user processes to access the DMA SPRs */ void grant_dma_mpls(void) { +#if CONFIG_KERNEL_PL == 2 + __insn_mtspr(SPR_MPL_DMA_CPL_SET_1, 1); + __insn_mtspr(SPR_MPL_DMA_NOTIFY_SET_1, 1); +#else __insn_mtspr(SPR_MPL_DMA_CPL_SET_0, 1); __insn_mtspr(SPR_MPL_DMA_NOTIFY_SET_0, 1); +#endif } /* Forbid user processes from accessing the DMA SPRs */ void restrict_dma_mpls(void) { +#if CONFIG_KERNEL_PL == 2 + __insn_mtspr(SPR_MPL_DMA_CPL_SET_2, 1); + __insn_mtspr(SPR_MPL_DMA_NOTIFY_SET_2, 1); +#else __insn_mtspr(SPR_MPL_DMA_CPL_SET_1, 1); __insn_mtspr(SPR_MPL_DMA_NOTIFY_SET_1, 1); +#endif } /* Pause the DMA engine, then save off its state registers. */ @@ -524,7 +534,7 @@ struct task_struct *__sched _switch_to(struct task_struct *prev, * Switch kernel SP, PC, and callee-saved registers. * In the context of the new task, return the old task pointer * (i.e. the task that actually called __switch_to). - * Pass the value to use for SYSTEM_SAVE_1_0 when we reset our sp. + * Pass the value to use for SYSTEM_SAVE_K_0 when we reset our sp. */ return __switch_to(prev, next, next_current_ksp0(next)); } diff --git a/arch/tile/kernel/regs_32.S b/arch/tile/kernel/regs_32.S index e88d6e12..caa1310 100644 --- a/arch/tile/kernel/regs_32.S +++ b/arch/tile/kernel/regs_32.S @@ -85,7 +85,7 @@ STD_ENTRY_SECTION(__switch_to, .sched.text) { /* Update sp and ksp0 simultaneously to avoid backtracer warnings. */ move sp, r13 - mtspr SYSTEM_SAVE_1_0, r2 + mtspr SPR_SYSTEM_SAVE_K_0, r2 } FOR_EACH_CALLEE_SAVED_REG(LOAD_REG) .L__switch_to_pc: diff --git a/arch/tile/kernel/setup.c b/arch/tile/kernel/setup.c index c1a697e..6444a2b 100644 --- a/arch/tile/kernel/setup.c +++ b/arch/tile/kernel/setup.c @@ -187,11 +187,11 @@ early_param("vmalloc", parse_vmalloc); #ifdef CONFIG_HIGHMEM /* - * Determine for each controller where its lowmem is mapped and how - * much of it is mapped there. On controller zero, the first few - * megabytes are mapped at 0xfd000000 as code, so in principle we - * could start our data mappings higher up, but for now we don't - * bother, to avoid additional confusion. + * Determine for each controller where its lowmem is mapped and how much of + * it is mapped there. On controller zero, the first few megabytes are + * already mapped in as code at MEM_SV_INTRPT, so in principle we could + * start our data mappings higher up, but for now we don't bother, to avoid + * additional confusion. * * One question is whether, on systems with more than 768 Mb and * controllers of different sizes, to map in a proportionate amount of @@ -876,6 +876,9 @@ void __cpuinit setup_cpu(int boot) #if CHIP_HAS_SN_PROC() raw_local_irq_unmask(INT_SNITLB_MISS); #endif +#ifdef __tilegx__ + raw_local_irq_unmask(INT_SINGLE_STEP_K); +#endif /* * Allow user access to many generic SPRs, like the cycle @@ -893,11 +896,12 @@ void __cpuinit setup_cpu(int boot) #endif /* - * Set the MPL for interrupt control 0 to user level. - * This includes access to the SYSTEM_SAVE and EX_CONTEXT SPRs, - * as well as the PL 0 interrupt mask. + * Set the MPL for interrupt control 0 & 1 to the corresponding + * values. This includes access to the SYSTEM_SAVE and EX_CONTEXT + * SPRs, as well as the interrupt mask. */ __insn_mtspr(SPR_MPL_INTCTRL_0_SET_0, 1); + __insn_mtspr(SPR_MPL_INTCTRL_1_SET_1, 1); /* Initialize IRQ support for this cpu. */ setup_irq_regs(); @@ -1033,7 +1037,7 @@ static void __init validate_va(void) * In addition, make sure we CAN'T use the end of memory, since * we use the last chunk of each pgd for the pgd_list. */ - int i, fc_fd_ok = 0; + int i, user_kernel_ok = 0; unsigned long max_va = 0; unsigned long list_va = ((PGD_LIST_OFFSET / sizeof(pgd_t)) << PGDIR_SHIFT); @@ -1044,13 +1048,13 @@ static void __init validate_va(void) break; if (range.start <= MEM_USER_INTRPT && range.start + range.size >= MEM_HV_INTRPT) - fc_fd_ok = 1; + user_kernel_ok = 1; if (range.start == 0) max_va = range.size; BUG_ON(range.start + range.size > list_va); } - if (!fc_fd_ok) - early_panic("Hypervisor not configured for VAs 0xfc/0xfd\n"); + if (!user_kernel_ok) + early_panic("Hypervisor not configured for user/kernel VAs\n"); if (max_va == 0) early_panic("Hypervisor not configured for low VAs\n"); if (max_va < KERNEL_HIGH_VADDR) diff --git a/arch/tile/kernel/smp.c b/arch/tile/kernel/smp.c index 1cb5ec7..75255d9 100644 --- a/arch/tile/kernel/smp.c +++ b/arch/tile/kernel/smp.c @@ -212,7 +212,7 @@ void __init ipi_init(void) tile.x = cpu_x(cpu); tile.y = cpu_y(cpu); - if (hv_get_ipi_pte(tile, 1, &pte) != 0) + if (hv_get_ipi_pte(tile, KERNEL_PL, &pte) != 0) panic("Failed to initialize IPI for cpu %d\n", cpu); offset = hv_pte_get_pfn(pte) << PAGE_SHIFT; diff --git a/arch/tile/kernel/traps.c b/arch/tile/kernel/traps.c index 0f362dc..7826a8b1 100644 --- a/arch/tile/kernel/traps.c +++ b/arch/tile/kernel/traps.c @@ -278,7 +278,7 @@ void __kprobes do_trap(struct pt_regs *regs, int fault_num, case INT_DOUBLE_FAULT: /* * For double fault, "reason" is actually passed as - * SYSTEM_SAVE_1_2, the hypervisor's double-fault info, so + * SYSTEM_SAVE_K_2, the hypervisor's double-fault info, so * we can provide the original fault number rather than * the uninteresting "INT_DOUBLE_FAULT" so the user can * learn what actually struck while PL0 ICS was set. diff --git a/arch/tile/kvm/Kconfig b/arch/tile/kvm/Kconfig new file mode 100644 index 0000000..b88f9c0 --- /dev/null +++ b/arch/tile/kvm/Kconfig @@ -0,0 +1,38 @@ +# +# KVM configuration +# + +source "virt/kvm/Kconfig" + +menuconfig VIRTUALIZATION + bool "Virtualization" + ---help--- + Say Y here to get to see options for using your Linux host to run + other operating systems inside virtual machines (guests). + This option alone does not add any kernel code. + + If you say N, all options in this submenu will be skipped and + disabled. + +if VIRTUALIZATION + +config KVM + tristate "Kernel-based Virtual Machine (KVM) support" + depends on HAVE_KVM && MODULES && EXPERIMENTAL + select PREEMPT_NOTIFIERS + select ANON_INODES + ---help--- + Support hosting paravirtualized guest machines. + + This module provides access to the hardware capabilities through + a character device node named /dev/kvm. + + To compile this as a module, choose M here: the module + will be called kvm. + + If unsure, say N. + +source drivers/vhost/Kconfig +source drivers/virtio/Kconfig + +endif # VIRTUALIZATION diff --git a/arch/tile/mm/fault.c b/arch/tile/mm/fault.c index 94f579d..f295b4a 100644 --- a/arch/tile/mm/fault.c +++ b/arch/tile/mm/fault.c @@ -563,10 +563,10 @@ do_sigbus: /* * When we take an ITLB or DTLB fault or access violation in the * supervisor while the critical section bit is set, the hypervisor is - * reluctant to write new values into the EX_CONTEXT_1_x registers, + * reluctant to write new values into the EX_CONTEXT_K_x registers, * since that might indicate we have not yet squirreled the SPR * contents away and can thus safely take a recursive interrupt. - * Accordingly, the hypervisor passes us the PC via SYSTEM_SAVE_1_2. + * Accordingly, the hypervisor passes us the PC via SYSTEM_SAVE_K_2. * * Note that this routine is called before homecache_tlb_defer_enter(), * which means that we can properly unlock any atomics that might @@ -610,7 +610,7 @@ struct intvec_state do_page_fault_ics(struct pt_regs *regs, int fault_num, * fault. We didn't set up a kernel stack on initial entry to * sys_cmpxchg, but instead had one set up by the fault, which * (because sys_cmpxchg never releases ICS) came to us via the - * SYSTEM_SAVE_1_2 mechanism, and thus EX_CONTEXT_1_[01] are + * SYSTEM_SAVE_K_2 mechanism, and thus EX_CONTEXT_K_[01] are * still referencing the original user code. We release the * atomic lock and rewrite pt_regs so that it appears that we * came from user-space directly, and after we finish the diff --git a/arch/tile/mm/init.c b/arch/tile/mm/init.c index d89c9ea..78e1982 100644 --- a/arch/tile/mm/init.c +++ b/arch/tile/mm/init.c @@ -1060,7 +1060,7 @@ void free_initmem(void) /* * Free the pages mapped from 0xc0000000 that correspond to code - * pages from 0xfd000000 that we won't use again after init. + * pages from MEM_SV_INTRPT that we won't use again after init. */ free_init_pages("unused kernel text", (unsigned long)_sinittext - text_delta, -- cgit v1.1 From 233325b94999d4bb8df227bb39904a57509e4995 Mon Sep 17 00:00:00 2001 From: Chris Metcalf Date: Thu, 14 Oct 2010 16:32:41 -0400 Subject: arch/tile: enable single-step support for TILE-Gx This is not quite the complete support, since we're not yet shipping intvec_64.S, but it is the support relevant to the set of files we are currently shipping, and makes it easier to track changes between our internal sources and our public GIT repository. Signed-off-by: Chris Metcalf --- arch/tile/include/asm/traps.h | 4 +++ arch/tile/kernel/intvec_32.S | 7 +++- arch/tile/kernel/single_step.c | 73 +++++++++++++++++++++++++++++++++++++++++- arch/tile/kernel/traps.c | 2 +- 4 files changed, 83 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/tile/include/asm/traps.h b/arch/tile/include/asm/traps.h index 432a9c1..d06e35f 100644 --- a/arch/tile/include/asm/traps.h +++ b/arch/tile/include/asm/traps.h @@ -59,4 +59,8 @@ void do_hardwall_trap(struct pt_regs *, int fault_num); void do_breakpoint(struct pt_regs *, int fault_num); +#ifdef __tilegx__ +void gx_singlestep_handle(struct pt_regs *, int fault_num); +#endif + #endif /* _ASM_TILE_SYSCALLS_H */ diff --git a/arch/tile/kernel/intvec_32.S b/arch/tile/kernel/intvec_32.S index 206dc7e..f5821626 100644 --- a/arch/tile/kernel/intvec_32.S +++ b/arch/tile/kernel/intvec_32.S @@ -1472,7 +1472,12 @@ handle_ill: lw r26, r24 sw r28, r26 - /* Clear TIF_SINGLESTEP */ + /* + * Clear TIF_SINGLESTEP to prevent recursion if we execute an ill. + * The normal non-arch flow redundantly clears TIF_SINGLESTEP, but we + * need to clear it here and can't really impose on all other arches. + * So what's another write between friends? + */ GET_THREAD_INFO(r0) addi r1, r0, THREAD_INFO_FLAGS_OFFSET diff --git a/arch/tile/kernel/single_step.c b/arch/tile/kernel/single_step.c index 5ec4b9c..1eb3b39 100644 --- a/arch/tile/kernel/single_step.c +++ b/arch/tile/kernel/single_step.c @@ -15,7 +15,7 @@ * Derived from iLib's single-stepping code. */ -#ifndef __tilegx__ /* No support for single-step yet. */ +#ifndef __tilegx__ /* Hardware support for single step unavailable. */ /* These functions are only used on the TILE platform */ #include @@ -660,4 +660,75 @@ void single_step_once(struct pt_regs *regs) regs->pc += 8; } +#else +#include +#include +#include + +static DEFINE_PER_CPU(unsigned long, ss_saved_pc); + + +/* + * Called directly on the occasion of an interrupt. + * + * If the process doesn't have single step set, then we use this as an + * opportunity to turn single step off. + * + * It has been mentioned that we could conditionally turn off single stepping + * on each entry into the kernel and rely on single_step_once to turn it + * on for the processes that matter (as we already do), but this + * implementation is somewhat more efficient in that we muck with registers + * once on a bum interrupt rather than on every entry into the kernel. + * + * If SINGLE_STEP_CONTROL_K has CANCELED set, then an interrupt occurred, + * so we have to run through this process again before we can say that an + * instruction has executed. + * + * swint will set CANCELED, but it's a legitimate instruction. Fortunately + * it changes the PC. If it hasn't changed, then we know that the interrupt + * wasn't generated by swint and we'll need to run this process again before + * we can say an instruction has executed. + * + * If either CANCELED == 0 or the PC's changed, we send out SIGTRAPs and get + * on with our lives. + */ + +void gx_singlestep_handle(struct pt_regs *regs, int fault_num) +{ + unsigned long *ss_pc = &__get_cpu_var(ss_saved_pc); + struct thread_info *info = (void *)current_thread_info(); + int is_single_step = test_ti_thread_flag(info, TIF_SINGLESTEP); + unsigned long control = __insn_mfspr(SPR_SINGLE_STEP_CONTROL_K); + + if (is_single_step == 0) { + __insn_mtspr(SPR_SINGLE_STEP_EN_K_K, 0); + + } else if ((*ss_pc != regs->pc) || + (!(control & SPR_SINGLE_STEP_CONTROL_1__CANCELED_MASK))) { + + ptrace_notify(SIGTRAP); + control |= SPR_SINGLE_STEP_CONTROL_1__CANCELED_MASK; + control |= SPR_SINGLE_STEP_CONTROL_1__INHIBIT_MASK; + __insn_mtspr(SPR_SINGLE_STEP_CONTROL_K, control); + } +} + + +/* + * Called from need_singlestep. Set up the control registers and the enable + * register, then return back. + */ + +void single_step_once(struct pt_regs *regs) +{ + unsigned long *ss_pc = &__get_cpu_var(ss_saved_pc); + unsigned long control = __insn_mfspr(SPR_SINGLE_STEP_CONTROL_K); + + *ss_pc = regs->pc; + control |= SPR_SINGLE_STEP_CONTROL_1__CANCELED_MASK; + control |= SPR_SINGLE_STEP_CONTROL_1__INHIBIT_MASK; + __insn_mtspr(SPR_SINGLE_STEP_CONTROL_K, control); + __insn_mtspr(SPR_SINGLE_STEP_EN_K_K, 1 << USER_PL); +} + #endif /* !__tilegx__ */ diff --git a/arch/tile/kernel/traps.c b/arch/tile/kernel/traps.c index 7826a8b1..5474fc2 100644 --- a/arch/tile/kernel/traps.c +++ b/arch/tile/kernel/traps.c @@ -260,7 +260,7 @@ void __kprobes do_trap(struct pt_regs *regs, int fault_num, address = regs->pc; break; case INT_UNALIGN_DATA: -#ifndef __tilegx__ /* FIXME: GX: no single-step yet */ +#ifndef __tilegx__ /* Emulated support for single step debugging */ if (unaligned_fixup >= 0) { struct single_step_state *state = current_thread_info()->step_state; -- cgit v1.1 From 29507663dfa2590647a1ef66f3652a0cac033eca Mon Sep 17 00:00:00 2001 From: Chris Metcalf Date: Thu, 14 Oct 2010 16:39:42 -0400 Subject: arch/tile: minor whitespace/naming changes for string support files Our internal process shares memcpy, memset, etc., with libc, and we did some minor tweaking as part of moving from uclibc to glibc, which is now reflected in the kernel versions of these files. There are no semantic changes in this commit, just whitespace (memcpy_32.S now properly uses tabs), naming (memmove.c instead of memmove_32.c, since TILE-Gx shares the file with TILEPro), and a couple of other minor tweaks. Signed-off-by: Chris Metcalf --- arch/tile/lib/Makefile | 4 +- arch/tile/lib/memcpy_32.S | 206 +++++++++++++++++++++++---------------------- arch/tile/lib/memmove.c | 63 ++++++++++++++ arch/tile/lib/memmove_32.c | 63 -------------- arch/tile/lib/memset_32.c | 1 + arch/tile/lib/strlen_32.c | 2 + 6 files changed, 172 insertions(+), 167 deletions(-) create mode 100644 arch/tile/lib/memmove.c delete mode 100644 arch/tile/lib/memmove_32.c (limited to 'arch') diff --git a/arch/tile/lib/Makefile b/arch/tile/lib/Makefile index 746dc81..93122d5 100644 --- a/arch/tile/lib/Makefile +++ b/arch/tile/lib/Makefile @@ -3,8 +3,8 @@ # lib-y = cacheflush.o checksum.o cpumask.o delay.o \ - mb_incoherent.o uaccess.o \ - memcpy_$(BITS).o memchr_$(BITS).o memmove_$(BITS).o memset_$(BITS).o \ + mb_incoherent.o uaccess.o memmove.o \ + memcpy_$(BITS).o memchr_$(BITS).o memset_$(BITS).o \ strchr_$(BITS).o strlen_$(BITS).o ifeq ($(CONFIG_TILEGX),y) diff --git a/arch/tile/lib/memcpy_32.S b/arch/tile/lib/memcpy_32.S index 30c3b7e..2a419a6 100644 --- a/arch/tile/lib/memcpy_32.S +++ b/arch/tile/lib/memcpy_32.S @@ -10,14 +10,16 @@ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or * NON INFRINGEMENT. See the GNU General Public License for * more details. - * - * This file shares the implementation of the userspace memcpy and - * the kernel's memcpy, copy_to_user and copy_from_user. */ #include +/* + * This file shares the implementation of the userspace memcpy and + * the kernel's memcpy, copy_to_user and copy_from_user. + */ + #include /* On TILE64, we wrap these functions via arch/tile/lib/memcpy_tile64.c */ @@ -53,9 +55,9 @@ */ ENTRY(__copy_from_user_inatomic) .type __copy_from_user_inatomic, @function - FEEDBACK_ENTER_EXPLICIT(__copy_from_user_inatomic, \ + FEEDBACK_ENTER_EXPLICIT(__copy_from_user_inatomic, \ .text.memcpy_common, \ - .Lend_memcpy_common - __copy_from_user_inatomic) + .Lend_memcpy_common - __copy_from_user_inatomic) { movei r29, IS_COPY_FROM_USER; j memcpy_common } .size __copy_from_user_inatomic, . - __copy_from_user_inatomic @@ -64,7 +66,7 @@ ENTRY(__copy_from_user_inatomic) */ ENTRY(__copy_from_user_zeroing) .type __copy_from_user_zeroing, @function - FEEDBACK_REENTER(__copy_from_user_inatomic) + FEEDBACK_REENTER(__copy_from_user_inatomic) { movei r29, IS_COPY_FROM_USER_ZEROING; j memcpy_common } .size __copy_from_user_zeroing, . - __copy_from_user_zeroing @@ -74,13 +76,13 @@ ENTRY(__copy_from_user_zeroing) */ ENTRY(__copy_to_user_inatomic) .type __copy_to_user_inatomic, @function - FEEDBACK_REENTER(__copy_from_user_inatomic) + FEEDBACK_REENTER(__copy_from_user_inatomic) { movei r29, IS_COPY_TO_USER; j memcpy_common } .size __copy_to_user_inatomic, . - __copy_to_user_inatomic ENTRY(memcpy) .type memcpy, @function - FEEDBACK_REENTER(__copy_from_user_inatomic) + FEEDBACK_REENTER(__copy_from_user_inatomic) { movei r29, IS_MEMCPY } .size memcpy, . - memcpy /* Fall through */ @@ -157,35 +159,35 @@ EX: { sw r0, r3; addi r0, r0, 4; addi r2, r2, -4 } { addi r3, r1, 60; andi r9, r9, -64 } #if CHIP_HAS_WH64() - /* No need to prefetch dst, we'll just do the wh64 - * right before we copy a line. + /* No need to prefetch dst, we'll just do the wh64 + * right before we copy a line. */ #endif EX: { lw r5, r3; addi r3, r3, 64; movei r4, 1 } - /* Intentionally stall for a few cycles to leave L2 cache alone. */ - { bnzt zero, .; move r27, lr } + /* Intentionally stall for a few cycles to leave L2 cache alone. */ + { bnzt zero, .; move r27, lr } EX: { lw r6, r3; addi r3, r3, 64 } - /* Intentionally stall for a few cycles to leave L2 cache alone. */ - { bnzt zero, . } + /* Intentionally stall for a few cycles to leave L2 cache alone. */ + { bnzt zero, . } EX: { lw r7, r3; addi r3, r3, 64 } #if !CHIP_HAS_WH64() - /* Prefetch the dest */ - /* Intentionally stall for a few cycles to leave L2 cache alone. */ - { bnzt zero, . } - /* Use a real load to cause a TLB miss if necessary. We aren't using - * r28, so this should be fine. - */ + /* Prefetch the dest */ + /* Intentionally stall for a few cycles to leave L2 cache alone. */ + { bnzt zero, . } + /* Use a real load to cause a TLB miss if necessary. We aren't using + * r28, so this should be fine. + */ EX: { lw r28, r9; addi r9, r9, 64 } - /* Intentionally stall for a few cycles to leave L2 cache alone. */ - { bnzt zero, . } - { prefetch r9; addi r9, r9, 64 } - /* Intentionally stall for a few cycles to leave L2 cache alone. */ - { bnzt zero, . } - { prefetch r9; addi r9, r9, 64 } + /* Intentionally stall for a few cycles to leave L2 cache alone. */ + { bnzt zero, . } + { prefetch r9; addi r9, r9, 64 } + /* Intentionally stall for a few cycles to leave L2 cache alone. */ + { bnzt zero, . } + { prefetch r9; addi r9, r9, 64 } #endif - /* Intentionally stall for a few cycles to leave L2 cache alone. */ - { bz zero, .Lbig_loop2 } + /* Intentionally stall for a few cycles to leave L2 cache alone. */ + { bz zero, .Lbig_loop2 } /* On entry to this loop: * - r0 points to the start of dst line 0 @@ -197,7 +199,7 @@ EX: { lw r28, r9; addi r9, r9, 64 } * to some "safe" recently loaded address. * - r5 contains *(r1 + 60) [i.e. last word of source line 0] * - r6 contains *(r1 + 64 + 60) [i.e. last word of source line 1] - * - r9 contains ((r0 + 63) & -64) + * - r9 contains ((r0 + 63) & -64) * [start of next dst cache line.] */ @@ -208,137 +210,137 @@ EX: { lw r28, r9; addi r9, r9, 64 } /* Copy line 0, first stalling until r5 is ready. */ EX: { move r12, r5; lw r16, r1 } { bz r4, .Lcopy_8_check; slti_u r8, r2, 8 } - /* Prefetch several lines ahead. */ + /* Prefetch several lines ahead. */ EX: { lw r5, r3; addi r3, r3, 64 } - { jal .Lcopy_line } + { jal .Lcopy_line } /* Copy line 1, first stalling until r6 is ready. */ EX: { move r12, r6; lw r16, r1 } { bz r4, .Lcopy_8_check; slti_u r8, r2, 8 } - /* Prefetch several lines ahead. */ + /* Prefetch several lines ahead. */ EX: { lw r6, r3; addi r3, r3, 64 } { jal .Lcopy_line } /* Copy line 2, first stalling until r7 is ready. */ EX: { move r12, r7; lw r16, r1 } { bz r4, .Lcopy_8_check; slti_u r8, r2, 8 } - /* Prefetch several lines ahead. */ + /* Prefetch several lines ahead. */ EX: { lw r7, r3; addi r3, r3, 64 } - /* Use up a caches-busy cycle by jumping back to the top of the - * loop. Might as well get it out of the way now. - */ - { j .Lbig_loop } + /* Use up a caches-busy cycle by jumping back to the top of the + * loop. Might as well get it out of the way now. + */ + { j .Lbig_loop } /* On entry: * - r0 points to the destination line. * - r1 points to the source line. - * - r3 is the next prefetch address. + * - r3 is the next prefetch address. * - r9 holds the last address used for wh64. * - r12 = WORD_15 - * - r16 = WORD_0. - * - r17 == r1 + 16. - * - r27 holds saved lr to restore. + * - r16 = WORD_0. + * - r17 == r1 + 16. + * - r27 holds saved lr to restore. * * On exit: * - r0 is incremented by 64. * - r1 is incremented by 64, unless that would point to a word - * beyond the end of the source array, in which case it is redirected - * to point to an arbitrary word already in the cache. + * beyond the end of the source array, in which case it is redirected + * to point to an arbitrary word already in the cache. * - r2 is decremented by 64. - * - r3 is unchanged, unless it points to a word beyond the - * end of the source array, in which case it is redirected - * to point to an arbitrary word already in the cache. - * Redirecting is OK since if we are that close to the end - * of the array we will not come back to this subroutine - * and use the contents of the prefetched address. + * - r3 is unchanged, unless it points to a word beyond the + * end of the source array, in which case it is redirected + * to point to an arbitrary word already in the cache. + * Redirecting is OK since if we are that close to the end + * of the array we will not come back to this subroutine + * and use the contents of the prefetched address. * - r4 is nonzero iff r2 >= 64. - * - r9 is incremented by 64, unless it points beyond the - * end of the last full destination cache line, in which - * case it is redirected to a "safe address" that can be - * clobbered (sp - 64) + * - r9 is incremented by 64, unless it points beyond the + * end of the last full destination cache line, in which + * case it is redirected to a "safe address" that can be + * clobbered (sp - 64) * - lr contains the value in r27. */ /* r26 unused */ .Lcopy_line: - /* TODO: when r3 goes past the end, we would like to redirect it - * to prefetch the last partial cache line (if any) just once, for the - * benefit of the final cleanup loop. But we don't want to - * prefetch that line more than once, or subsequent prefetches - * will go into the RTF. But then .Lbig_loop should unconditionally - * branch to top of loop to execute final prefetch, and its - * nop should become a conditional branch. - */ - - /* We need two non-memory cycles here to cover the resources - * used by the loads initiated by the caller. - */ - { add r15, r1, r2 } + /* TODO: when r3 goes past the end, we would like to redirect it + * to prefetch the last partial cache line (if any) just once, for the + * benefit of the final cleanup loop. But we don't want to + * prefetch that line more than once, or subsequent prefetches + * will go into the RTF. But then .Lbig_loop should unconditionally + * branch to top of loop to execute final prefetch, and its + * nop should become a conditional branch. + */ + + /* We need two non-memory cycles here to cover the resources + * used by the loads initiated by the caller. + */ + { add r15, r1, r2 } .Lcopy_line2: - { slt_u r13, r3, r15; addi r17, r1, 16 } + { slt_u r13, r3, r15; addi r17, r1, 16 } - /* NOTE: this will stall for one cycle as L1 is busy. */ + /* NOTE: this will stall for one cycle as L1 is busy. */ - /* Fill second L1D line. */ + /* Fill second L1D line. */ EX: { lw r17, r17; addi r1, r1, 48; mvz r3, r13, r1 } /* r17 = WORD_4 */ #if CHIP_HAS_WH64() - /* Prepare destination line for writing. */ + /* Prepare destination line for writing. */ EX: { wh64 r9; addi r9, r9, 64 } #else - /* Prefetch dest line */ + /* Prefetch dest line */ { prefetch r9; addi r9, r9, 64 } #endif - /* Load seven words that are L1D hits to cover wh64 L2 usage. */ + /* Load seven words that are L1D hits to cover wh64 L2 usage. */ - /* Load the three remaining words from the last L1D line, which - * we know has already filled the L1D. - */ + /* Load the three remaining words from the last L1D line, which + * we know has already filled the L1D. + */ EX: { lw r4, r1; addi r1, r1, 4; addi r20, r1, 16 } /* r4 = WORD_12 */ EX: { lw r8, r1; addi r1, r1, 4; slt_u r13, r20, r15 }/* r8 = WORD_13 */ EX: { lw r11, r1; addi r1, r1, -52; mvz r20, r13, r1 } /* r11 = WORD_14 */ - /* Load the three remaining words from the first L1D line, first - * stalling until it has filled by "looking at" r16. - */ + /* Load the three remaining words from the first L1D line, first + * stalling until it has filled by "looking at" r16. + */ EX: { lw r13, r1; addi r1, r1, 4; move zero, r16 } /* r13 = WORD_1 */ EX: { lw r14, r1; addi r1, r1, 4 } /* r14 = WORD_2 */ EX: { lw r15, r1; addi r1, r1, 8; addi r10, r0, 60 } /* r15 = WORD_3 */ - /* Load second word from the second L1D line, first - * stalling until it has filled by "looking at" r17. - */ + /* Load second word from the second L1D line, first + * stalling until it has filled by "looking at" r17. + */ EX: { lw r19, r1; addi r1, r1, 4; move zero, r17 } /* r19 = WORD_5 */ - /* Store last word to the destination line, potentially dirtying it - * for the first time, which keeps the L2 busy for two cycles. - */ + /* Store last word to the destination line, potentially dirtying it + * for the first time, which keeps the L2 busy for two cycles. + */ EX: { sw r10, r12 } /* store(WORD_15) */ - /* Use two L1D hits to cover the sw L2 access above. */ + /* Use two L1D hits to cover the sw L2 access above. */ EX: { lw r10, r1; addi r1, r1, 4 } /* r10 = WORD_6 */ EX: { lw r12, r1; addi r1, r1, 4 } /* r12 = WORD_7 */ - /* Fill third L1D line. */ + /* Fill third L1D line. */ EX: { lw r18, r1; addi r1, r1, 4 } /* r18 = WORD_8 */ - /* Store first L1D line. */ + /* Store first L1D line. */ EX: { sw r0, r16; addi r0, r0, 4; add r16, r0, r2 } /* store(WORD_0) */ EX: { sw r0, r13; addi r0, r0, 4; andi r16, r16, -64 } /* store(WORD_1) */ EX: { sw r0, r14; addi r0, r0, 4; slt_u r16, r9, r16 } /* store(WORD_2) */ #if CHIP_HAS_WH64() EX: { sw r0, r15; addi r0, r0, 4; addi r13, sp, -64 } /* store(WORD_3) */ #else - /* Back up the r9 to a cache line we are already storing to + /* Back up the r9 to a cache line we are already storing to * if it gets past the end of the dest vector. Strictly speaking, * we don't need to back up to the start of a cache line, but it's free * and tidy, so why not? - */ + */ EX: { sw r0, r15; addi r0, r0, 4; andi r13, r0, -64 } /* store(WORD_3) */ #endif - /* Store second L1D line. */ + /* Store second L1D line. */ EX: { sw r0, r17; addi r0, r0, 4; mvz r9, r16, r13 }/* store(WORD_4) */ EX: { sw r0, r19; addi r0, r0, 4 } /* store(WORD_5) */ EX: { sw r0, r10; addi r0, r0, 4 } /* store(WORD_6) */ @@ -348,30 +350,30 @@ EX: { lw r13, r1; addi r1, r1, 4; move zero, r18 } /* r13 = WORD_9 */ EX: { lw r14, r1; addi r1, r1, 4 } /* r14 = WORD_10 */ EX: { lw r15, r1; move r1, r20 } /* r15 = WORD_11 */ - /* Store third L1D line. */ + /* Store third L1D line. */ EX: { sw r0, r18; addi r0, r0, 4 } /* store(WORD_8) */ EX: { sw r0, r13; addi r0, r0, 4 } /* store(WORD_9) */ EX: { sw r0, r14; addi r0, r0, 4 } /* store(WORD_10) */ EX: { sw r0, r15; addi r0, r0, 4 } /* store(WORD_11) */ - /* Store rest of fourth L1D line. */ + /* Store rest of fourth L1D line. */ EX: { sw r0, r4; addi r0, r0, 4 } /* store(WORD_12) */ - { + { EX: sw r0, r8 /* store(WORD_13) */ - addi r0, r0, 4 + addi r0, r0, 4 /* Will r2 be > 64 after we subtract 64 below? */ - shri r4, r2, 7 - } - { + shri r4, r2, 7 + } + { EX: sw r0, r11 /* store(WORD_14) */ - addi r0, r0, 8 - /* Record 64 bytes successfully copied. */ - addi r2, r2, -64 - } + addi r0, r0, 8 + /* Record 64 bytes successfully copied. */ + addi r2, r2, -64 + } { jrp lr; move lr, r27 } - /* Convey to the backtrace library that the stack frame is size + /* Convey to the backtrace library that the stack frame is size * zero, and the real return address is on the stack rather than * in 'lr'. */ diff --git a/arch/tile/lib/memmove.c b/arch/tile/lib/memmove.c new file mode 100644 index 0000000..fd615ae --- /dev/null +++ b/arch/tile/lib/memmove.c @@ -0,0 +1,63 @@ +/* + * Copyright 2010 Tilera Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation, version 2. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or + * NON INFRINGEMENT. See the GNU General Public License for + * more details. + */ + +#include +#include +#include + +void *memmove(void *dest, const void *src, size_t n) +{ + if ((const char *)src >= (char *)dest + n + || (char *)dest >= (const char *)src + n) { + /* We found no overlap, so let memcpy do all the heavy + * lifting (prefetching, etc.) + */ + return memcpy(dest, src, n); + } + + if (n != 0) { + const uint8_t *in; + uint8_t x; + uint8_t *out; + int stride; + + if (src < dest) { + /* copy backwards */ + in = (const uint8_t *)src + n - 1; + out = (uint8_t *)dest + n - 1; + stride = -1; + } else { + /* copy forwards */ + in = (const uint8_t *)src; + out = (uint8_t *)dest; + stride = 1; + } + + /* Manually software-pipeline this loop. */ + x = *in; + in += stride; + + while (--n != 0) { + *out = x; + out += stride; + x = *in; + in += stride; + } + + *out = x; + } + + return dest; +} +EXPORT_SYMBOL(memmove); diff --git a/arch/tile/lib/memmove_32.c b/arch/tile/lib/memmove_32.c deleted file mode 100644 index fd615ae..0000000 --- a/arch/tile/lib/memmove_32.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright 2010 Tilera Corporation. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation, version 2. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or - * NON INFRINGEMENT. See the GNU General Public License for - * more details. - */ - -#include -#include -#include - -void *memmove(void *dest, const void *src, size_t n) -{ - if ((const char *)src >= (char *)dest + n - || (char *)dest >= (const char *)src + n) { - /* We found no overlap, so let memcpy do all the heavy - * lifting (prefetching, etc.) - */ - return memcpy(dest, src, n); - } - - if (n != 0) { - const uint8_t *in; - uint8_t x; - uint8_t *out; - int stride; - - if (src < dest) { - /* copy backwards */ - in = (const uint8_t *)src + n - 1; - out = (uint8_t *)dest + n - 1; - stride = -1; - } else { - /* copy forwards */ - in = (const uint8_t *)src; - out = (uint8_t *)dest; - stride = 1; - } - - /* Manually software-pipeline this loop. */ - x = *in; - in += stride; - - while (--n != 0) { - *out = x; - out += stride; - x = *in; - in += stride; - } - - *out = x; - } - - return dest; -} -EXPORT_SYMBOL(memmove); diff --git a/arch/tile/lib/memset_32.c b/arch/tile/lib/memset_32.c index d014c1f..57dbb3a 100644 --- a/arch/tile/lib/memset_32.c +++ b/arch/tile/lib/memset_32.c @@ -18,6 +18,7 @@ #include #include +#undef memset void *memset(void *s, int c, size_t n) { diff --git a/arch/tile/lib/strlen_32.c b/arch/tile/lib/strlen_32.c index f26f88e..4974292 100644 --- a/arch/tile/lib/strlen_32.c +++ b/arch/tile/lib/strlen_32.c @@ -16,6 +16,8 @@ #include #include +#undef strlen + size_t strlen(const char *s) { /* Get an aligned pointer. */ -- cgit v1.1 From c569cac8b69397d8bc80f95bc6edf13ed902e28b Mon Sep 17 00:00:00 2001 From: Chris Metcalf Date: Thu, 14 Oct 2010 16:46:22 -0400 Subject: arch/tile: support new info op generated by compiler This just syncs the backtracing support in the kernel to the upstream backtrace library. Signed-off-by: Chris Metcalf --- arch/tile/include/asm/backtrace.h | 5 ++++- arch/tile/kernel/backtrace.c | 4 ++++ 2 files changed, 8 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/tile/include/asm/backtrace.h b/arch/tile/include/asm/backtrace.h index 758ca46..f18887d 100644 --- a/arch/tile/include/asm/backtrace.h +++ b/arch/tile/include/asm/backtrace.h @@ -146,7 +146,10 @@ enum { CALLER_SP_IN_R52_BASE = 4, - CALLER_SP_OFFSET_BASE = 8 + CALLER_SP_OFFSET_BASE = 8, + + /* Marks the entry point of certain functions. */ + ENTRY_POINT_INFO_OP = 16 }; diff --git a/arch/tile/kernel/backtrace.c b/arch/tile/kernel/backtrace.c index d3c41c1..55a6a74 100644 --- a/arch/tile/kernel/backtrace.c +++ b/arch/tile/kernel/backtrace.c @@ -369,6 +369,10 @@ static void find_caller_pc_and_caller_sp(CallerLocation *location, /* Weird; reserved value, ignore it. */ continue; } + if (info_operand & ENTRY_POINT_INFO_OP) { + /* This info op is ignored by the backtracer. */ + continue; + } /* Skip info ops which are not in the * "one_ago" mode we want right now. -- cgit v1.1 From ce7f2a39675ea5e8e27b3f3bb03e5041c7d10412 Mon Sep 17 00:00:00 2001 From: Chris Metcalf Date: Thu, 14 Oct 2010 16:48:00 -0400 Subject: arch/tile: make ptrace() work properly for TILE-Gx COMPAT mode Previously, we tried to pass 64-bit arguments through the "COMPAT" mode 32-bit syscall API, which turned out not to work well. Now we just use straight 32-bit arguments in COMPAT mode, thus requiring individual registers to be read/written with two syscalls. Of course this is uncommon, since usually all the registers are read or written at once. The restructuring applies to all the tile platforms, but is plausibly better than the original code in any case. Signed-off-by: Chris Metcalf --- arch/tile/kernel/compat.c | 4 +-- arch/tile/kernel/ptrace.c | 78 ++++++++++++++++++++++------------------------- 2 files changed, 38 insertions(+), 44 deletions(-) (limited to 'arch') diff --git a/arch/tile/kernel/compat.c b/arch/tile/kernel/compat.c index 5f24e54..77739cd 100644 --- a/arch/tile/kernel/compat.c +++ b/arch/tile/kernel/compat.c @@ -154,8 +154,8 @@ long tile_compat_sys_msgrcv(int msqid, #define compat_sys_fstat64 sys_newfstat #define compat_sys_fstatat64 sys_newfstatat -/* Pass full 64-bit values through ptrace. */ -#define compat_sys_ptrace tile_compat_sys_ptrace +/* The native sys_ptrace dynamically handles compat binaries. */ +#define compat_sys_ptrace sys_ptrace /* Call the trampolines to manage pt_regs where necessary. */ #define compat_sys_execve _compat_sys_execve diff --git a/arch/tile/kernel/ptrace.c b/arch/tile/kernel/ptrace.c index 7161bd0..5b20c28 100644 --- a/arch/tile/kernel/ptrace.c +++ b/arch/tile/kernel/ptrace.c @@ -32,25 +32,6 @@ void user_disable_single_step(struct task_struct *child) } /* - * This routine will put a word on the process's privileged stack. - */ -static void putreg(struct task_struct *task, - unsigned long addr, unsigned long value) -{ - unsigned int regno = addr / sizeof(unsigned long); - struct pt_regs *childregs = task_pt_regs(task); - childregs->regs[regno] = value; - childregs->flags |= PT_FLAGS_RESTORE_REGS; -} - -static unsigned long getreg(struct task_struct *task, unsigned long addr) -{ - unsigned int regno = addr / sizeof(unsigned long); - struct pt_regs *childregs = task_pt_regs(task); - return childregs->regs[regno]; -} - -/* * Called by kernel/ptrace.c when detaching.. */ void ptrace_disable(struct task_struct *child) @@ -66,59 +47,72 @@ void ptrace_disable(struct task_struct *child) long arch_ptrace(struct task_struct *child, long request, long addr, long data) { - unsigned long __user *datap; + unsigned long __user *datap = (long __user __force *)data; unsigned long tmp; int i; long ret = -EIO; - -#ifdef CONFIG_COMPAT - if (task_thread_info(current)->status & TS_COMPAT) - data = (u32)data; - if (task_thread_info(child)->status & TS_COMPAT) - addr = (u32)addr; -#endif - datap = (unsigned long __user __force *)data; + unsigned long *childregs; + char *childreg; switch (request) { case PTRACE_PEEKUSR: /* Read register from pt_regs. */ - if (addr & (sizeof(data)-1)) - break; if (addr < 0 || addr >= PTREGS_SIZE) break; - tmp = getreg(child, addr); /* Read register */ - ret = put_user(tmp, datap); + childreg = (char *)task_pt_regs(child) + addr; +#ifdef CONFIG_COMPAT + if (is_compat_task()) { + if (addr & (sizeof(compat_long_t)-1)) + break; + ret = put_user(*(compat_long_t *)childreg, + (compat_long_t __user *)datap); + } else +#endif + { + if (addr & (sizeof(long)-1)) + break; + ret = put_user(*(long *)childreg, datap); + } break; case PTRACE_POKEUSR: /* Write register in pt_regs. */ - if (addr & (sizeof(data)-1)) - break; if (addr < 0 || addr >= PTREGS_SIZE) break; - putreg(child, addr, data); /* Write register */ + childreg = (char *)task_pt_regs(child) + addr; +#ifdef CONFIG_COMPAT + if (is_compat_task()) { + if (addr & (sizeof(compat_long_t)-1)) + break; + *(compat_long_t *)childreg = data; + } else +#endif + { + if (addr & (sizeof(long)-1)) + break; + *(long *)childreg = data; + } ret = 0; break; case PTRACE_GETREGS: /* Get all registers from the child. */ if (!access_ok(VERIFY_WRITE, datap, PTREGS_SIZE)) break; - for (i = 0; i < PTREGS_SIZE; i += sizeof(long)) { - ret = __put_user(getreg(child, i), datap); + childregs = (long *)task_pt_regs(child); + for (i = 0; i < sizeof(struct pt_regs)/sizeof(long); ++i) { + ret = __put_user(childregs[i], &datap[i]); if (ret != 0) break; - datap++; } break; case PTRACE_SETREGS: /* Set all registers in the child. */ if (!access_ok(VERIFY_READ, datap, PTREGS_SIZE)) break; - for (i = 0; i < PTREGS_SIZE; i += sizeof(long)) { - ret = __get_user(tmp, datap); + childregs = (long *)task_pt_regs(child); + for (i = 0; i < sizeof(struct pt_regs)/sizeof(long); ++i) { + ret = __get_user(childregs[i], &datap[i]); if (ret != 0) break; - putreg(child, i, tmp); - datap++; } break; -- cgit v1.1 From e18105c128734b1671739ad4d85e216ebec28c61 Mon Sep 17 00:00:00 2001 From: Chris Metcalf Date: Thu, 14 Oct 2010 16:50:26 -0400 Subject: arch/tile: convert a BUG_ON to BUILD_BUG_ON Inspired by Akinobu Mita's cleanup work. Signed-off-by: Chris Metcalf --- arch/tile/kernel/setup.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/tile/kernel/setup.c b/arch/tile/kernel/setup.c index 6444a2b..f3a50e7 100644 --- a/arch/tile/kernel/setup.c +++ b/arch/tile/kernel/setup.c @@ -311,7 +311,7 @@ static void __init setup_memory(void) #endif /* We are using a char to hold the cpu_2_node[] mapping */ - BUG_ON(MAX_NUMNODES > 127); + BUILD_BUG_ON(MAX_NUMNODES > 127); /* Discover the ranges of memory available to us */ for (i = 0; ; ++i) { -- cgit v1.1 From 80e7b19ae167197e84f378809b8ccddd0f99c1fd Mon Sep 17 00:00:00 2001 From: Daniel Drake Date: Thu, 23 Sep 2010 17:28:04 +0100 Subject: PCI: OLPC: Only enable PCI configuration type override on XO-1 This configuration type override is for XO-1 only and must not happen on XO-1.5. Acked-by: Andres Salomon Signed-off-by: Daniel Drake Signed-off-by: Jesse Barnes --- arch/x86/Kconfig | 2 +- arch/x86/kernel/olpc.c | 6 ++++-- arch/x86/pci/olpc.c | 2 +- 3 files changed, 6 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index cea0cd9..0ed4c9b 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1900,7 +1900,7 @@ config PCI_GODIRECT bool "Direct" config PCI_GOOLPC - bool "OLPC" + bool "OLPC XO-1" depends on OLPC config PCI_GOANY diff --git a/arch/x86/kernel/olpc.c b/arch/x86/kernel/olpc.c index 0e0cdde..635888c 100644 --- a/arch/x86/kernel/olpc.c +++ b/arch/x86/kernel/olpc.c @@ -242,8 +242,10 @@ static int __init olpc_init(void) (unsigned char *) &olpc_platform_info.ecver, 1); #ifdef CONFIG_PCI_OLPC - /* If the VSA exists let it emulate PCI, if not emulate in kernel */ - if (!cs5535_has_vsa2()) + /* If the VSA exists let it emulate PCI, if not emulate in kernel. + * XO-1 only. */ + if (olpc_platform_info.boardrev < olpc_board_pre(0xd0) && + !cs5535_has_vsa2()) x86_init.pci.arch_init = pci_olpc_init; #endif diff --git a/arch/x86/pci/olpc.c b/arch/x86/pci/olpc.c index b348154..13700ec 100644 --- a/arch/x86/pci/olpc.c +++ b/arch/x86/pci/olpc.c @@ -304,7 +304,7 @@ static struct pci_raw_ops pci_olpc_conf = { int __init pci_olpc_init(void) { - printk(KERN_INFO "PCI: Using configuration type OLPC\n"); + printk(KERN_INFO "PCI: Using configuration type OLPC XO-1\n"); raw_pci_ops = &pci_olpc_conf; is_lx = is_geode_lx(); return 0; -- cgit v1.1 From 25143fd1270d28782ae0620aa86ef5f8c14030fd Mon Sep 17 00:00:00 2001 From: Seth Heasley Date: Fri, 10 Sep 2010 16:36:39 -0700 Subject: x86/PCI: irq and pci_ids patch for Intel Patsburg DeviceIDs This patch adds the LPC Controller DeviceIDs for the Intel Patsburg PCH. Signed-off-by: Seth Heasley Signed-off-by: Jesse Barnes --- arch/x86/pci/irq.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/x86/pci/irq.c b/arch/x86/pci/irq.c index f547ee0..ee7fc8f 100644 --- a/arch/x86/pci/irq.c +++ b/arch/x86/pci/irq.c @@ -589,6 +589,7 @@ static __init int intel_router_probe(struct irq_router *r, struct pci_dev *route case PCI_DEVICE_ID_INTEL_ICH10_1: case PCI_DEVICE_ID_INTEL_ICH10_2: case PCI_DEVICE_ID_INTEL_ICH10_3: + case PCI_DEVICE_ID_INTEL_PBG_LPC: r->name = "PIIX/ICH"; r->get = pirq_piix_get; r->set = pirq_piix_set; -- cgit v1.1 From fa0d4c26be9f989816b30626f6c67d9e7ef867f8 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Sat, 11 Sep 2010 18:24:46 +0200 Subject: parisc: remove big kernel lock The parisc version of the perf code is sufficiently protected by its own spinlock, no need to use the BKL. Signed-off-by: Arnd Bergmann Cc: Kyle McMartin Cc: Helge Deller Cc: "James E.J. Bottomley" Cc: linux-parisc@vger.kernel.org --- arch/parisc/kernel/perf.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch') diff --git a/arch/parisc/kernel/perf.c b/arch/parisc/kernel/perf.c index f9f6783..ba0c053 100644 --- a/arch/parisc/kernel/perf.c +++ b/arch/parisc/kernel/perf.c @@ -46,7 +46,6 @@ #include #include #include -#include #include #include @@ -261,16 +260,13 @@ printk("Preparing to start counters\n"); */ static int perf_open(struct inode *inode, struct file *file) { - lock_kernel(); spin_lock(&perf_lock); if (perf_enabled) { spin_unlock(&perf_lock); - unlock_kernel(); return -EBUSY; } perf_enabled = 1; spin_unlock(&perf_lock); - unlock_kernel(); return 0; } -- cgit v1.1 From cb04e95bdd0bfd618ab731c84a3ab56b56974df8 Mon Sep 17 00:00:00 2001 From: Seth Heasley Date: Mon, 4 Oct 2010 13:27:14 -0700 Subject: PCI: update Intel chipset names and defines This patch updates the defines for Intel devices in include/linux/pci_ids.h, referenced in arch/x86/pci/irq.c and drivers/i2c/busses/i2c-i801.c, reflecting approved legal branding, and using fuller code-names for products under development. Acked-by: Jean Delvare Signed-off-by: Seth Heasley Signed-off-by: Jesse Barnes --- arch/x86/pci/irq.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/x86/pci/irq.c b/arch/x86/pci/irq.c index ee7fc8f..9f9bfb7 100644 --- a/arch/x86/pci/irq.c +++ b/arch/x86/pci/irq.c @@ -584,28 +584,28 @@ static __init int intel_router_probe(struct irq_router *r, struct pci_dev *route case PCI_DEVICE_ID_INTEL_ICH9_3: case PCI_DEVICE_ID_INTEL_ICH9_4: case PCI_DEVICE_ID_INTEL_ICH9_5: - case PCI_DEVICE_ID_INTEL_TOLAPAI_0: + case PCI_DEVICE_ID_INTEL_EP80579_0: case PCI_DEVICE_ID_INTEL_ICH10_0: case PCI_DEVICE_ID_INTEL_ICH10_1: case PCI_DEVICE_ID_INTEL_ICH10_2: case PCI_DEVICE_ID_INTEL_ICH10_3: - case PCI_DEVICE_ID_INTEL_PBG_LPC: + case PCI_DEVICE_ID_INTEL_PATSBURG_LPC: r->name = "PIIX/ICH"; r->get = pirq_piix_get; r->set = pirq_piix_set; return 1; } - if ((device >= PCI_DEVICE_ID_INTEL_PCH_LPC_MIN) && - (device <= PCI_DEVICE_ID_INTEL_PCH_LPC_MAX)) { + if ((device >= PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MIN) && + (device <= PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MAX)) { r->name = "PIIX/ICH"; r->get = pirq_piix_get; r->set = pirq_piix_set; return 1; } - if ((device >= PCI_DEVICE_ID_INTEL_CPT_LPC_MIN) && - (device <= PCI_DEVICE_ID_INTEL_CPT_LPC_MAX)) { + if ((device >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN) && + (device <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX)) { r->name = "PIIX/ICH"; r->get = pirq_piix_get; r->set = pirq_piix_set; -- cgit v1.1 From 1ca98fa652bb5dc3c8793335db9ccc5d0f2e1f65 Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Mon, 4 Oct 2010 12:49:24 -0600 Subject: x86/PCI: MMCONFIG: fix region end calculation The end of an MMCONFIG region depends on the ending bus number, not on the number of buses the region covers. We previously computed the wrong ending address whenever the starting bus number was non-zero, e.g.,: MMCONFIG for [bus 00-1f] at [mem 0xe0000000-0xe1ffffff] (base 0xe0000000) MMCONFIG for [bus 20-3f] at [mem 0xe2000000-0xe1ffffff] (base 0xe0000000) The correct regions are: MMCONFIG for [bus 00-1f] at [mem 0xe0000000-0xe1ffffff] (base 0xe0000000) MMCONFIG for [bus 20-3f] at [mem 0xe2000000-0xe3ffffff] (base 0xe0000000) Signed-off-by: Bjorn Helgaas Signed-off-by: Jesse Barnes --- arch/x86/pci/mmconfig-shared.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/x86/pci/mmconfig-shared.c b/arch/x86/pci/mmconfig-shared.c index a918553..e282886 100644 --- a/arch/x86/pci/mmconfig-shared.c +++ b/arch/x86/pci/mmconfig-shared.c @@ -65,7 +65,6 @@ static __init struct pci_mmcfg_region *pci_mmconfig_add(int segment, int start, int end, u64 addr) { struct pci_mmcfg_region *new; - int num_buses; struct resource *res; if (addr == 0) @@ -82,10 +81,9 @@ static __init struct pci_mmcfg_region *pci_mmconfig_add(int segment, int start, list_add_sorted(new); - num_buses = end - start + 1; res = &new->res; res->start = addr + PCI_MMCFG_BUS_OFFSET(start); - res->end = addr + PCI_MMCFG_BUS_OFFSET(num_buses) - 1; + res->end = addr + PCI_MMCFG_BUS_OFFSET(end + 1) - 1; res->flags = IORESOURCE_MEM | IORESOURCE_BUSY; snprintf(new->name, PCI_MMCFG_RESOURCE_NAME_LEN, "PCI MMCONFIG %04x [bus %02x-%02x]", segment, start, end); -- cgit v1.1 From 50a23e6eec6f20d55a3a920e47adb455bff6046e Mon Sep 17 00:00:00 2001 From: "Justin P. Mattock" Date: Sat, 16 Oct 2010 10:36:23 -0700 Subject: Update broken web addresses in arch directory. The patch below updates broken web addresses in the arch directory. Signed-off-by: Justin P. Mattock Signed-off-by: Maciej W. Rozycki Cc: Finn Thain Cc: Randy Dunlap Reviewed-by: Finn Thain Signed-off-by: Jiri Kosina --- arch/arm/Kconfig | 2 +- arch/arm/common/icst.c | 2 +- arch/arm/include/asm/hardware/icst.h | 2 +- arch/arm/mach-at91/Kconfig | 6 +++--- arch/arm/mach-omap1/Kconfig | 2 +- arch/arm/mach-s3c2440/mach-at2440evb.c | 2 +- arch/arm/mach-sa1100/Kconfig | 6 +++--- arch/arm/mach-sa1100/cpu-sa1100.c | 2 +- arch/arm/nwfpe/milieu.h | 4 ++-- arch/arm/nwfpe/softfloat-macros | 4 ++-- arch/arm/nwfpe/softfloat-specialize | 4 ++-- arch/arm/nwfpe/softfloat.c | 4 ++-- arch/arm/nwfpe/softfloat.h | 4 ++-- arch/arm/plat-samsung/include/plat/adc.h | 2 +- arch/avr32/Kconfig | 2 +- arch/h8300/Kconfig.cpu | 8 ++++---- arch/h8300/README | 1 + arch/m32r/Kconfig | 2 +- arch/m68k/mac/macboing.c | 3 ++- arch/m68k/q40/README | 2 +- arch/mips/Kconfig | 12 ++++++++---- arch/mips/math-emu/cp1emu.c | 1 - arch/mips/math-emu/dp_add.c | 1 - arch/mips/math-emu/dp_cmp.c | 1 - arch/mips/math-emu/dp_div.c | 1 - arch/mips/math-emu/dp_fint.c | 1 - arch/mips/math-emu/dp_flong.c | 1 - arch/mips/math-emu/dp_frexp.c | 1 - arch/mips/math-emu/dp_fsp.c | 1 - arch/mips/math-emu/dp_logb.c | 1 - arch/mips/math-emu/dp_modf.c | 1 - arch/mips/math-emu/dp_mul.c | 1 - arch/mips/math-emu/dp_scalb.c | 1 - arch/mips/math-emu/dp_simple.c | 1 - arch/mips/math-emu/dp_sqrt.c | 1 - arch/mips/math-emu/dp_sub.c | 1 - arch/mips/math-emu/dp_tint.c | 1 - arch/mips/math-emu/dp_tlong.c | 1 - arch/mips/math-emu/ieee754.c | 1 - arch/mips/math-emu/ieee754.h | 1 - arch/mips/math-emu/ieee754d.c | 1 - arch/mips/math-emu/ieee754dp.c | 1 - arch/mips/math-emu/ieee754dp.h | 1 - arch/mips/math-emu/ieee754int.h | 1 - arch/mips/math-emu/ieee754m.c | 1 - arch/mips/math-emu/ieee754sp.c | 1 - arch/mips/math-emu/ieee754sp.h | 1 - arch/mips/math-emu/ieee754xcpt.c | 1 - arch/mips/math-emu/sp_add.c | 1 - arch/mips/math-emu/sp_cmp.c | 1 - arch/mips/math-emu/sp_div.c | 1 - arch/mips/math-emu/sp_fdp.c | 1 - arch/mips/math-emu/sp_fint.c | 1 - arch/mips/math-emu/sp_flong.c | 1 - arch/mips/math-emu/sp_frexp.c | 1 - arch/mips/math-emu/sp_logb.c | 1 - arch/mips/math-emu/sp_modf.c | 1 - arch/mips/math-emu/sp_mul.c | 1 - arch/mips/math-emu/sp_scalb.c | 1 - arch/mips/math-emu/sp_simple.c | 1 - arch/mips/math-emu/sp_sqrt.c | 1 - arch/mips/math-emu/sp_sub.c | 1 - arch/mips/math-emu/sp_tint.c | 1 - arch/mips/math-emu/sp_tlong.c | 1 - arch/powerpc/include/asm/hydra.h | 2 +- arch/x86/kernel/apm_32.c | 4 ++-- arch/x86/kernel/microcode_core.c | 2 +- arch/x86/kernel/microcode_intel.c | 2 +- 68 files changed, 46 insertions(+), 83 deletions(-) (limited to 'arch') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 232f0c7..4971b2a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1126,7 +1126,7 @@ config SMP See also , and the SMP-HOWTO available at - . + . If you don't know what to do here, say N. diff --git a/arch/arm/common/icst.c b/arch/arm/common/icst.c index 9a7f09c..2dc6da70 100644 --- a/arch/arm/common/icst.c +++ b/arch/arm/common/icst.c @@ -8,7 +8,7 @@ * published by the Free Software Foundation. * * Support functions for calculating clocks/divisors for the ICST307 - * clock generators. See http://www.icst.com/ for more information + * clock generators. See http://www.idt.com/ for more information * on these devices. * * This is an almost identical implementation to the ICST525 clock generator. diff --git a/arch/arm/include/asm/hardware/icst.h b/arch/arm/include/asm/hardware/icst.h index 10382a3..794220b 100644 --- a/arch/arm/include/asm/hardware/icst.h +++ b/arch/arm/include/asm/hardware/icst.h @@ -8,7 +8,7 @@ * published by the Free Software Foundation. * * Support functions for calculating clocks/divisors for the ICST - * clock generators. See http://www.icst.com/ for more information + * clock generators. See http://www.idt.com/ for more information * on these devices. */ #ifndef ASMARM_HARDWARE_ICST_H diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 939bccd..e5be994 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -105,7 +105,7 @@ config MACH_ONEARM bool "Ajeco 1ARM Single Board Computer" help Select this if you are using Ajeco's 1ARM Single Board Computer. - + config ARCH_AT91RM9200DK bool "Atmel AT91RM9200-DK Development board" @@ -137,7 +137,7 @@ config MACH_CARMEVA bool "Conitec ARM&EVA" help Select this if you are using Conitec's AT91RM9200-MCU-Module. - + config MACH_ATEB9200 bool "Embest ATEB9200" @@ -149,7 +149,7 @@ config MACH_KB9200 bool "KwikByte KB920x" help Select this if you are using KwikByte's KB920x board. - + config MACH_PICOTUX2XX bool "picotux 200" diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig index 3b02d3b..5f64963 100644 --- a/arch/arm/mach-omap1/Kconfig +++ b/arch/arm/mach-omap1/Kconfig @@ -128,7 +128,7 @@ config MACH_OMAP_PALMTT help Support for the Palm Tungsten|T PDA. To boot the kernel, you'll need a PalmOS compatible bootloader (Garux); check out - http://www.hackndev.com/palm/tt/ for more information. + http://garux.sourceforge.net/ for more information. Say Y here if you have this PDA model, say N otherwise. config MACH_SX1 diff --git a/arch/arm/mach-s3c2440/mach-at2440evb.c b/arch/arm/mach-s3c2440/mach-at2440evb.c index 8472579..67b6ba0 100644 --- a/arch/arm/mach-s3c2440/mach-at2440evb.c +++ b/arch/arm/mach-s3c2440/mach-at2440evb.c @@ -5,7 +5,7 @@ * and modifications by SBZ and * Weibing * - * For product information, visit http://www.arm9e.com/ + * For product information, visit http://www.arm.com/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/arch/arm/mach-sa1100/Kconfig b/arch/arm/mach-sa1100/Kconfig index fd4c52b..5da8c35 100644 --- a/arch/arm/mach-sa1100/Kconfig +++ b/arch/arm/mach-sa1100/Kconfig @@ -90,8 +90,8 @@ config SA1100_JORNADA720 # FIXME: select CPU_FREQ_SA11x0 help Say Y here if you want to build a kernel for the HP Jornada 720 - handheld computer. See - for details. + handheld computer. See + config SA1100_JORNADA720_SSP bool "HP Jornada 720 Extended SSP driver" @@ -145,7 +145,7 @@ config SA1100_SIMPAD FLASH. The SL4 version got 64 MB RAM and 32 MB FLASH and a PCMCIA-Slot. The version for the Germany Telecom (DTAG) is the same like CL4 in additional it has a PCMCIA-Slot. For more information - visit or . + visit or . config SA1100_SSP tristate "Generic PIO SSP" diff --git a/arch/arm/mach-sa1100/cpu-sa1100.c b/arch/arm/mach-sa1100/cpu-sa1100.c index ef81787..c0a13ef 100644 --- a/arch/arm/mach-sa1100/cpu-sa1100.c +++ b/arch/arm/mach-sa1100/cpu-sa1100.c @@ -13,7 +13,7 @@ * This software has been developed while working on the LART * computing board (http://www.lartmaker.nl/), which is * sponsored by the Mobile Multi-media Communications - * (http://www.mmc.tudelft.nl/) and Ubiquitous Communications + * (http://www.mobimedia.org/) and Ubiquitous Communications * (http://www.ubicom.tudelft.nl/) projects. * * The authors can be reached at: diff --git a/arch/arm/nwfpe/milieu.h b/arch/arm/nwfpe/milieu.h index a3892ab..09a4f2d 100644 --- a/arch/arm/nwfpe/milieu.h +++ b/arch/arm/nwfpe/milieu.h @@ -12,8 +12,8 @@ National Science Foundation under grant MIP-9311980. The original version of this code was written as part of a project to build a fixed-point vector processor in collaboration with the University of California at Berkeley, overseen by Profs. Nelson Morgan and John Wawrzynek. More information -is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/ -arithmetic/softfloat.html'. +is available through the Web page +http://www.jhauser.us/arithmetic/SoftFloat-2b/SoftFloat-source.txt THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT diff --git a/arch/arm/nwfpe/softfloat-macros b/arch/arm/nwfpe/softfloat-macros index 5a060f9..cf2a617 100644 --- a/arch/arm/nwfpe/softfloat-macros +++ b/arch/arm/nwfpe/softfloat-macros @@ -12,8 +12,8 @@ National Science Foundation under grant MIP-9311980. The original version of this code was written as part of a project to build a fixed-point vector processor in collaboration with the University of California at Berkeley, overseen by Profs. Nelson Morgan and John Wawrzynek. More information -is available through the web page `http://HTTP.CS.Berkeley.EDU/~jhauser/ -arithmetic/softfloat.html'. +is available through the web page +http://www.jhauser.us/arithmetic/SoftFloat-2b/SoftFloat-source.txt THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT diff --git a/arch/arm/nwfpe/softfloat-specialize b/arch/arm/nwfpe/softfloat-specialize index d4a4c8e..679a026 100644 --- a/arch/arm/nwfpe/softfloat-specialize +++ b/arch/arm/nwfpe/softfloat-specialize @@ -12,8 +12,8 @@ National Science Foundation under grant MIP-9311980. The original version of this code was written as part of a project to build a fixed-point vector processor in collaboration with the University of California at Berkeley, overseen by Profs. Nelson Morgan and John Wawrzynek. More information -is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/ -arithmetic/softfloat.html'. +is available through the Web page +http://www.jhauser.us/arithmetic/SoftFloat-2b/SoftFloat-source.txt THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT diff --git a/arch/arm/nwfpe/softfloat.c b/arch/arm/nwfpe/softfloat.c index 0f9656e..ffa6b43 100644 --- a/arch/arm/nwfpe/softfloat.c +++ b/arch/arm/nwfpe/softfloat.c @@ -11,8 +11,8 @@ National Science Foundation under grant MIP-9311980. The original version of this code was written as part of a project to build a fixed-point vector processor in collaboration with the University of California at Berkeley, overseen by Profs. Nelson Morgan and John Wawrzynek. More information -is available through the web page `http://HTTP.CS.Berkeley.EDU/~jhauser/ -arithmetic/softfloat.html'. +is available through the web page +http://www.jhauser.us/arithmetic/SoftFloat-2b/SoftFloat-source.txt THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT diff --git a/arch/arm/nwfpe/softfloat.h b/arch/arm/nwfpe/softfloat.h index 13e479c..df4d243 100644 --- a/arch/arm/nwfpe/softfloat.h +++ b/arch/arm/nwfpe/softfloat.h @@ -12,8 +12,8 @@ National Science Foundation under grant MIP-9311980. The original version of this code was written as part of a project to build a fixed-point vector processor in collaboration with the University of California at Berkeley, overseen by Profs. Nelson Morgan and John Wawrzynek. More information -is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/ -arithmetic/softfloat.html'. +is available through the Web page +http://www.jhauser.us/arithmetic/SoftFloat-2b/SoftFloat-source.txt THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT diff --git a/arch/arm/plat-samsung/include/plat/adc.h b/arch/arm/plat-samsung/include/plat/adc.h index e8382c7..b258a08 100644 --- a/arch/arm/plat-samsung/include/plat/adc.h +++ b/arch/arm/plat-samsung/include/plat/adc.h @@ -1,7 +1,7 @@ /* arch/arm/plat-samsung/include/plat/adc.h * * Copyright (c) 2008 Simtec Electronics - * http://armlinux.simnte.co.uk/ + * http://armlinux.simtec.co.uk/ * Ben Dooks * * S3C ADC driver information diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig index f515727..559aca8 100644 --- a/arch/avr32/Kconfig +++ b/arch/avr32/Kconfig @@ -145,7 +145,7 @@ config BOARD_HAMMERHEAD will cover even the most exceptional need of memory bandwidth. Together with the onboard video decoder the board is ready for video processing. - For more information see: http://www.miromico.com/hammerhead + For more information see: http://www.miromico.ch/index.php/hammerhead.html config BOARD_FAVR_32 bool "Favr-32 LCD-board" diff --git a/arch/h8300/Kconfig.cpu b/arch/h8300/Kconfig.cpu index 6e2ecff..d236ab4 100644 --- a/arch/h8300/Kconfig.cpu +++ b/arch/h8300/Kconfig.cpu @@ -17,7 +17,7 @@ config H8300H_AKI3068NET help AKI-H8/3068F / AKI-H8/3069F Flashmicom LAN Board Support More Information. (Japanese Only) - + AE-3068/69 Evaluation Board Support More Information. @@ -36,7 +36,7 @@ config H8300H_SIM help GDB Simulator Support More Information. - arch/h8300/Doc/simulator.txt + config H8S_GENERIC bool "H8S Generic" @@ -50,14 +50,14 @@ config H8S_EDOSK2674 Renesas EDOSK-2674 Evaluation Board Support More Information. - + config H8S_SIM bool "H8S Simulator" help GDB Simulator Support More Information. - arch/h8300/Doc/simulator.txt + endchoice diff --git a/arch/h8300/README b/arch/h8300/README index 2fd6f6d..637f5a0 100644 --- a/arch/h8300/README +++ b/arch/h8300/README @@ -18,6 +18,7 @@ H8/300H and H8S 4.EDOSK2674 see http://www.eu.renesas.com/products/mpumcu/tool/edk/support/edosk2674.html + http://www.uclinux.org/pub/uClinux/ports/h8/HITACHI-EDOSK2674-HOWTO http://www.azpower.com/H8-uClinux/ * Toolchain Version diff --git a/arch/m32r/Kconfig b/arch/m32r/Kconfig index 836abbb..3867fd2 100644 --- a/arch/m32r/Kconfig +++ b/arch/m32r/Kconfig @@ -315,7 +315,7 @@ config SMP Management" code will be disabled if you say Y here. See also the SMP-HOWTO available at - . + . If you don't know what to do here, say N. diff --git a/arch/m68k/mac/macboing.c b/arch/m68k/mac/macboing.c index 8f06408..f8810c7 100644 --- a/arch/m68k/mac/macboing.c +++ b/arch/m68k/mac/macboing.c @@ -114,7 +114,8 @@ static void mac_init_asc( void ) * 16-bit I/O functionality. The PowerBook 500 series computers * support 16-bit stereo output, but only mono input." * - * http://til.info.apple.com/techinfo.nsf/artnum/n16405 + * Technical Information Library (TIL) article number 16405. + * http://support.apple.com/kb/TA32601 * * --David Kilzer */ diff --git a/arch/m68k/q40/README b/arch/m68k/q40/README index 6bdbf48..f877b72 100644 --- a/arch/m68k/q40/README +++ b/arch/m68k/q40/README @@ -3,7 +3,7 @@ Linux for the Q40 You may try http://www.geocities.com/SiliconValley/Bay/2602/ for some up to date information. Booter and other tools will be also -available from this place or ftp.uni-erlangen.de/linux/680x0/q40/ +available from this place or http://ftp.uni-erlangen.de/pub/unix/Linux/680x0/q40/ and mirrors. Hints to documentation usually refer to the linux source tree in diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 3ad59dd..4606248 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2175,10 +2175,14 @@ config TC bool "TURBOchannel support" depends on MACH_DECSTATION help - TurboChannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS - processors. Documentation on writing device drivers for TurboChannel - is available at: - . + TURBOchannel is a DEC (now Compaq (now HP)) bus for Alpha and MIPS + processors. TURBOchannel programming specifications are available + at: + + and: + + Linux driver support status is documented at: + #config ACCESSBUS # bool "Access.Bus support" diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c index 47842b7..ec3faa4 100644 --- a/arch/mips/math-emu/cp1emu.c +++ b/arch/mips/math-emu/cp1emu.c @@ -3,7 +3,6 @@ * * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com * Copyright (C) 2000 MIPS Technologies, Inc. diff --git a/arch/mips/math-emu/dp_add.c b/arch/mips/math-emu/dp_add.c index bcf73bb..b422fca 100644 --- a/arch/mips/math-emu/dp_add.c +++ b/arch/mips/math-emu/dp_add.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/dp_cmp.c b/arch/mips/math-emu/dp_cmp.c index 8ab4f32..0f32486 100644 --- a/arch/mips/math-emu/dp_cmp.c +++ b/arch/mips/math-emu/dp_cmp.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/dp_div.c b/arch/mips/math-emu/dp_div.c index 6acedce..a1bce1b 100644 --- a/arch/mips/math-emu/dp_div.c +++ b/arch/mips/math-emu/dp_div.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/dp_fint.c b/arch/mips/math-emu/dp_fint.c index 39a71de1..8857128 100644 --- a/arch/mips/math-emu/dp_fint.c +++ b/arch/mips/math-emu/dp_fint.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/dp_flong.c b/arch/mips/math-emu/dp_flong.c index f08f223..14fc01e 100644 --- a/arch/mips/math-emu/dp_flong.c +++ b/arch/mips/math-emu/dp_flong.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/dp_frexp.c b/arch/mips/math-emu/dp_frexp.c index e650cb1..cb15a5e 100644 --- a/arch/mips/math-emu/dp_frexp.c +++ b/arch/mips/math-emu/dp_frexp.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/dp_fsp.c b/arch/mips/math-emu/dp_fsp.c index 494d19a..1dfbd92 100644 --- a/arch/mips/math-emu/dp_fsp.c +++ b/arch/mips/math-emu/dp_fsp.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/dp_logb.c b/arch/mips/math-emu/dp_logb.c index 6033886..151127e 100644 --- a/arch/mips/math-emu/dp_logb.c +++ b/arch/mips/math-emu/dp_logb.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/dp_modf.c b/arch/mips/math-emu/dp_modf.c index a8570e5..b01f9cf 100644 --- a/arch/mips/math-emu/dp_modf.c +++ b/arch/mips/math-emu/dp_modf.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/dp_mul.c b/arch/mips/math-emu/dp_mul.c index 48908a8..aa566e7 100644 --- a/arch/mips/math-emu/dp_mul.c +++ b/arch/mips/math-emu/dp_mul.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/dp_scalb.c b/arch/mips/math-emu/dp_scalb.c index b84e633..6f5df43 100644 --- a/arch/mips/math-emu/dp_scalb.c +++ b/arch/mips/math-emu/dp_scalb.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/dp_simple.c b/arch/mips/math-emu/dp_simple.c index b909742..79ce267 100644 --- a/arch/mips/math-emu/dp_simple.c +++ b/arch/mips/math-emu/dp_simple.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/dp_sqrt.c b/arch/mips/math-emu/dp_sqrt.c index 032328c..a2a51b8 100644 --- a/arch/mips/math-emu/dp_sqrt.c +++ b/arch/mips/math-emu/dp_sqrt.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/dp_sub.c b/arch/mips/math-emu/dp_sub.c index a2127d6..0de098c 100644 --- a/arch/mips/math-emu/dp_sub.c +++ b/arch/mips/math-emu/dp_sub.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/dp_tint.c b/arch/mips/math-emu/dp_tint.c index 2447862..0ebe859 100644 --- a/arch/mips/math-emu/dp_tint.c +++ b/arch/mips/math-emu/dp_tint.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/dp_tlong.c b/arch/mips/math-emu/dp_tlong.c index 0f07ec2..133ce2b 100644 --- a/arch/mips/math-emu/dp_tlong.c +++ b/arch/mips/math-emu/dp_tlong.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/ieee754.c b/arch/mips/math-emu/ieee754.c index cb1b682..30554e1 100644 --- a/arch/mips/math-emu/ieee754.c +++ b/arch/mips/math-emu/ieee754.c @@ -9,7 +9,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/ieee754.h b/arch/mips/math-emu/ieee754.h index dd91733..22796e0 100644 --- a/arch/mips/math-emu/ieee754.h +++ b/arch/mips/math-emu/ieee754.h @@ -1,7 +1,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as diff --git a/arch/mips/math-emu/ieee754d.c b/arch/mips/math-emu/ieee754d.c index a032533..9599bdd 100644 --- a/arch/mips/math-emu/ieee754d.c +++ b/arch/mips/math-emu/ieee754d.c @@ -4,7 +4,6 @@ * MIPS floating point support * * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as diff --git a/arch/mips/math-emu/ieee754dp.c b/arch/mips/math-emu/ieee754dp.c index 2f22fd7..080b5ca 100644 --- a/arch/mips/math-emu/ieee754dp.c +++ b/arch/mips/math-emu/ieee754dp.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/ieee754dp.h b/arch/mips/math-emu/ieee754dp.h index 7627865..f139c72 100644 --- a/arch/mips/math-emu/ieee754dp.h +++ b/arch/mips/math-emu/ieee754dp.h @@ -5,7 +5,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/ieee754int.h b/arch/mips/math-emu/ieee754int.h index 1a846c5..2701d95 100644 --- a/arch/mips/math-emu/ieee754int.h +++ b/arch/mips/math-emu/ieee754int.h @@ -5,7 +5,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/ieee754m.c b/arch/mips/math-emu/ieee754m.c index d66896c..24190f3 100644 --- a/arch/mips/math-emu/ieee754m.c +++ b/arch/mips/math-emu/ieee754m.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/ieee754sp.c b/arch/mips/math-emu/ieee754sp.c index a19b721..271d00d 100644 --- a/arch/mips/math-emu/ieee754sp.c +++ b/arch/mips/math-emu/ieee754sp.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/ieee754sp.h b/arch/mips/math-emu/ieee754sp.h index d9e3586..754fd54 100644 --- a/arch/mips/math-emu/ieee754sp.h +++ b/arch/mips/math-emu/ieee754sp.h @@ -5,7 +5,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/ieee754xcpt.c b/arch/mips/math-emu/ieee754xcpt.c index e02423a..b99a693 100644 --- a/arch/mips/math-emu/ieee754xcpt.c +++ b/arch/mips/math-emu/ieee754xcpt.c @@ -1,7 +1,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/sp_add.c b/arch/mips/math-emu/sp_add.c index d8c4211..ae1a327 100644 --- a/arch/mips/math-emu/sp_add.c +++ b/arch/mips/math-emu/sp_add.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/sp_cmp.c b/arch/mips/math-emu/sp_cmp.c index d3eff6b..716cf37 100644 --- a/arch/mips/math-emu/sp_cmp.c +++ b/arch/mips/math-emu/sp_cmp.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/sp_div.c b/arch/mips/math-emu/sp_div.c index 2b437fc..d774792 100644 --- a/arch/mips/math-emu/sp_div.c +++ b/arch/mips/math-emu/sp_div.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/sp_fdp.c b/arch/mips/math-emu/sp_fdp.c index 4093723..e1515aa 100644 --- a/arch/mips/math-emu/sp_fdp.c +++ b/arch/mips/math-emu/sp_fdp.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/sp_fint.c b/arch/mips/math-emu/sp_fint.c index e88e125..9694d6c 100644 --- a/arch/mips/math-emu/sp_fint.c +++ b/arch/mips/math-emu/sp_fint.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/sp_flong.c b/arch/mips/math-emu/sp_flong.c index 26d6919..16a651f 100644 --- a/arch/mips/math-emu/sp_flong.c +++ b/arch/mips/math-emu/sp_flong.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/sp_frexp.c b/arch/mips/math-emu/sp_frexp.c index 359c648..5bc993c 100644 --- a/arch/mips/math-emu/sp_frexp.c +++ b/arch/mips/math-emu/sp_frexp.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/sp_logb.c b/arch/mips/math-emu/sp_logb.c index 3c33721..9c14e0c 100644 --- a/arch/mips/math-emu/sp_logb.c +++ b/arch/mips/math-emu/sp_logb.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/sp_modf.c b/arch/mips/math-emu/sp_modf.c index 7656894..25a0fba 100644 --- a/arch/mips/math-emu/sp_modf.c +++ b/arch/mips/math-emu/sp_modf.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/sp_mul.c b/arch/mips/math-emu/sp_mul.c index 3f070f8..c06bb402 100644 --- a/arch/mips/math-emu/sp_mul.c +++ b/arch/mips/math-emu/sp_mul.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/sp_scalb.c b/arch/mips/math-emu/sp_scalb.c index 44ceb87..dd76196 100644 --- a/arch/mips/math-emu/sp_scalb.c +++ b/arch/mips/math-emu/sp_scalb.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/sp_simple.c b/arch/mips/math-emu/sp_simple.c index 2fd53c9..ae4fcfa 100644 --- a/arch/mips/math-emu/sp_simple.c +++ b/arch/mips/math-emu/sp_simple.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/sp_sqrt.c b/arch/mips/math-emu/sp_sqrt.c index 8a934b9..fed2017 100644 --- a/arch/mips/math-emu/sp_sqrt.c +++ b/arch/mips/math-emu/sp_sqrt.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/sp_sub.c b/arch/mips/math-emu/sp_sub.c index dbb802c..886ed5b 100644 --- a/arch/mips/math-emu/sp_sub.c +++ b/arch/mips/math-emu/sp_sub.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/sp_tint.c b/arch/mips/math-emu/sp_tint.c index 352dc3a..0fe9acc 100644 --- a/arch/mips/math-emu/sp_tint.c +++ b/arch/mips/math-emu/sp_tint.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/mips/math-emu/sp_tlong.c b/arch/mips/math-emu/sp_tlong.c index 92cd9c5..d0ca6e2 100644 --- a/arch/mips/math-emu/sp_tlong.c +++ b/arch/mips/math-emu/sp_tlong.c @@ -4,7 +4,6 @@ /* * MIPS floating point support * Copyright (C) 1994-2000 Algorithmics Ltd. - * http://www.algor.co.uk * * ######################################################################## * diff --git a/arch/powerpc/include/asm/hydra.h b/arch/powerpc/include/asm/hydra.h index 1ad4eed..5b0c98bd 100644 --- a/arch/powerpc/include/asm/hydra.h +++ b/arch/powerpc/include/asm/hydra.h @@ -10,7 +10,7 @@ * * © Copyright 1995 Apple Computer, Inc. All rights reserved. * - * It's available online from http://chrp.apple.com/MacTech.pdf. + * It's available online from http://www.cpu.lu/~mlan/ftp/MacTech.pdf * You can obtain paper copies of this book from computer bookstores or by * writing Morgan Kaufmann Publishers, Inc., 340 Pine Street, Sixth Floor, San * Francisco, CA 94104. Reference ISBN 1-55860-393-X. diff --git a/arch/x86/kernel/apm_32.c b/arch/x86/kernel/apm_32.c index 4c9c67b..9fed1cc 100644 --- a/arch/x86/kernel/apm_32.c +++ b/arch/x86/kernel/apm_32.c @@ -189,8 +189,8 @@ * Intel Order Number 241704-001. Microsoft Part Number 781-110-X01. * * [This document is available free from Intel by calling 800.628.8686 (fax - * 916.356.6100) or 800.548.4725; or via anonymous ftp from - * ftp://ftp.intel.com/pub/IAL/software_specs/apmv11.doc. It is also + * 916.356.6100) or 800.548.4725; or from + * http://www.microsoft.com/whdc/archive/amp_12.mspx It is also * available from Microsoft by calling 206.882.8080.] * * APM 1.2 Reference: diff --git a/arch/x86/kernel/microcode_core.c b/arch/x86/kernel/microcode_core.c index fa6551d..b9c5c54 100644 --- a/arch/x86/kernel/microcode_core.c +++ b/arch/x86/kernel/microcode_core.c @@ -12,7 +12,7 @@ * Software Developer's Manual * Order Number 253668 or free download from: * - * http://developer.intel.com/design/pentium4/manuals/253668.htm + * http://developer.intel.com/Assets/PDF/manual/253668.pdf * * For more information, go to http://www.urbanmyth.org/microcode * diff --git a/arch/x86/kernel/microcode_intel.c b/arch/x86/kernel/microcode_intel.c index 3561702..dcb65cc 100644 --- a/arch/x86/kernel/microcode_intel.c +++ b/arch/x86/kernel/microcode_intel.c @@ -12,7 +12,7 @@ * Software Developer's Manual * Order Number 253668 or free download from: * - * http://developer.intel.com/design/pentium4/manuals/253668.htm + * http://developer.intel.com/Assets/PDF/manual/253668.pdf * * For more information, go to http://www.urbanmyth.org/microcode * -- cgit v1.1 From 66ad4eea7ec50fe131755c80058b1157d160294d Mon Sep 17 00:00:00 2001 From: Atul Dahiya Date: Mon, 18 Oct 2010 19:53:34 +0900 Subject: ARM: S3C24XX: Fix nand partition table for s3c24XX This patch fixes the partition table as existing partition table have last partition size fixed and can't utilize available memory proprly if size is more than 64M. Signed-off-by: Atul Dahiya Signed-off-by: Sangbeom Kim Signed-off-by: Kukjin Kim --- arch/arm/plat-s3c24xx/common-smdk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/plat-s3c24xx/common-smdk.c b/arch/arm/plat-s3c24xx/common-smdk.c index 7b44d0c..bcc43f3 100644 --- a/arch/arm/plat-s3c24xx/common-smdk.c +++ b/arch/arm/plat-s3c24xx/common-smdk.c @@ -147,7 +147,7 @@ static struct mtd_partition smdk_default_nand_part[] = { [7] = { .name = "S3C2410 flash partition 7", .offset = SZ_1M * 48, - .size = SZ_16M, + .size = MTDPART_SIZ_FULL, } }; -- cgit v1.1 From ef3f2dd4810cca5bf5b1d3648968b50fb267d5e2 Mon Sep 17 00:00:00 2001 From: Atul Dahiya Date: Mon, 18 Oct 2010 19:56:45 +0900 Subject: ARM: SAMSUNG: Add setname core function for S3C24XX NAND This patch replaces the device name assignment method from string assignment to set_name method for all s3c24xx machines and adds device core file. Signed-off-by: Atul Dahiya Signed-off-by: Sangbeom Kim Signed-off-by: Kukjin Kim --- arch/arm/mach-s3c2412/s3c2412.c | 3 ++- arch/arm/mach-s3c2416/s3c2416.c | 3 ++- arch/arm/mach-s3c2440/s3c244x.c | 3 ++- arch/arm/mach-s3c2443/s3c2443.c | 3 ++- arch/arm/plat-samsung/include/plat/nand-core.h | 28 ++++++++++++++++++++++++++ 5 files changed, 36 insertions(+), 4 deletions(-) create mode 100644 arch/arm/plat-samsung/include/plat/nand-core.h (limited to 'arch') diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c2412/s3c2412.c index bef39f7..4c6df51 100644 --- a/arch/arm/mach-s3c2412/s3c2412.c +++ b/arch/arm/mach-s3c2412/s3c2412.c @@ -51,6 +51,7 @@ #include #include #include +#include #ifndef CONFIG_CPU_S3C2412_ONLY void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO; @@ -92,7 +93,7 @@ void __init s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no) /* rename devices that are s3c2412/s3c2413 specific */ s3c_device_sdi.name = "s3c2412-sdi"; s3c_device_lcd.name = "s3c2412-lcd"; - s3c_device_nand.name = "s3c2412-nand"; + s3c_nand_setname("s3c2412-nand"); /* alter IRQ of SDI controller */ diff --git a/arch/arm/mach-s3c2416/s3c2416.c b/arch/arm/mach-s3c2416/s3c2416.c index bc30245..6207189 100644 --- a/arch/arm/mach-s3c2416/s3c2416.c +++ b/arch/arm/mach-s3c2416/s3c2416.c @@ -56,6 +56,7 @@ #include #include +#include static struct map_desc s3c2416_iodesc[] __initdata = { IODESC_ENT(WATCHDOG), @@ -100,7 +101,7 @@ void __init s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no) { s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no); - s3c_device_nand.name = "s3c2416-nand"; + s3c_nand_setname("s3c2416-nand"); } /* s3c2416_map_io diff --git a/arch/arm/mach-s3c2440/s3c244x.c b/arch/arm/mach-s3c2440/s3c244x.c index 5e4a97e..90c1707 100644 --- a/arch/arm/mach-s3c2440/s3c244x.c +++ b/arch/arm/mach-s3c2440/s3c244x.c @@ -44,6 +44,7 @@ #include #include #include +#include static struct map_desc s3c244x_iodesc[] __initdata = { IODESC_ENT(CLKPWR), @@ -68,7 +69,7 @@ void __init s3c244x_map_io(void) s3c_device_sdi.name = "s3c2440-sdi"; s3c_device_i2c0.name = "s3c2440-i2c"; - s3c_device_nand.name = "s3c2440-nand"; + s3c_nand_setname("s3c2440-nand"); s3c_device_ts.name = "s3c2440-ts"; s3c_device_usbgadget.name = "s3c2440-usbgadget"; } diff --git a/arch/arm/mach-s3c2443/s3c2443.c b/arch/arm/mach-s3c2443/s3c2443.c index 839b6b2..33d18dd 100644 --- a/arch/arm/mach-s3c2443/s3c2443.c +++ b/arch/arm/mach-s3c2443/s3c2443.c @@ -36,6 +36,7 @@ #include #include #include +#include static struct map_desc s3c2443_iodesc[] __initdata = { IODESC_ENT(WATCHDOG), @@ -62,7 +63,7 @@ int __init s3c2443_init(void) s3c24xx_reset_hook = s3c2443_hard_reset; - s3c_device_nand.name = "s3c2412-nand"; + s3c_nand_setname("s3c2412-nand"); s3c_fb_setname("s3c2443-fb"); /* change WDT IRQ number */ diff --git a/arch/arm/plat-samsung/include/plat/nand-core.h b/arch/arm/plat-samsung/include/plat/nand-core.h new file mode 100644 index 0000000..6de2078 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/nand-core.h @@ -0,0 +1,28 @@ +/* arch/arm/plat-samsung/include/plat/nand-core.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S3C - Nand Controller core functions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_NAND_CORE_H +#define __ASM_ARCH_NAND_CORE_H __FILE__ + +/* These functions are only for use with the core support code, such as + * the cpu specific initialisation code + */ + +/* re-define device name depending on support. */ +static inline void s3c_nand_setname(char *name) +{ +#ifdef CONFIG_S3C_DEV_NAND + s3c_device_nand.name = name; +#endif +} + +#endif /* __ASM_ARCH_NAND_CORE_H */ -- cgit v1.1 From 4bc778661a86722b2c1128dd03851fa013ef26de Mon Sep 17 00:00:00 2001 From: Atul Dahiya Date: Mon, 18 Oct 2010 19:56:49 +0900 Subject: ARM: S3C2416: Change S3C2416 NAND platform device name This patch changes the platform device name from 's3c2416-nand' to 's3c2412-nand' so that S3C2416 can reuse the nand functionality available on S3C2412. Signed-off-by: Atul Dahiya Signed-off-by: Sangbeom Kim Signed-off-by: Kukjin Kim --- arch/arm/mach-s3c2416/s3c2416.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-s3c2416/s3c2416.c b/arch/arm/mach-s3c2416/s3c2416.c index 6207189..63f39cd 100644 --- a/arch/arm/mach-s3c2416/s3c2416.c +++ b/arch/arm/mach-s3c2416/s3c2416.c @@ -101,7 +101,7 @@ void __init s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no) { s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no); - s3c_nand_setname("s3c2416-nand"); + s3c_nand_setname("s3c2412-nand"); } /* s3c2416_map_io -- cgit v1.1 From 56ea510962ec690ede2be2064de72e51a33011d9 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Fri, 15 Oct 2010 14:37:24 +0000 Subject: sh: fix clk_get() error handling clk_get() returns an ERR_PTR(errno) on error and not NULL. Signed-off-by: Guennadi Liakhovetski Signed-off-by: Paul Mundt --- arch/sh/boards/mach-ecovec24/setup.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/sh/boards/mach-ecovec24/setup.c b/arch/sh/boards/mach-ecovec24/setup.c index 1d7b495..71a3368 100644 --- a/arch/sh/boards/mach-ecovec24/setup.c +++ b/arch/sh/boards/mach-ecovec24/setup.c @@ -1248,14 +1248,14 @@ static int __init arch_setup(void) /* set SPU2 clock to 83.4 MHz */ clk = clk_get(NULL, "spu_clk"); - if (clk) { + if (!IS_ERR(clk)) { clk_set_rate(clk, clk_round_rate(clk, 83333333)); clk_put(clk); } /* change parent of FSI B */ clk = clk_get(NULL, "fsib_clk"); - if (clk) { + if (!IS_ERR(clk)) { clk_register(&fsimckb_clk); clk_set_parent(clk, &fsimckb_clk); clk_set_rate(clk, 11000); @@ -1273,7 +1273,7 @@ static int __init arch_setup(void) /* set VPU clock to 166 MHz */ clk = clk_get(NULL, "vpu_clk"); - if (clk) { + if (!IS_ERR(clk)) { clk_set_rate(clk, clk_round_rate(clk, 166000000)); clk_put(clk); } -- cgit v1.1 From 23ace955c22cb9bdf703e4bdc9bf7379166113cd Mon Sep 17 00:00:00 2001 From: Alex Nixon Date: Mon, 9 Feb 2009 12:05:46 -0800 Subject: xen: Don't disable the I/O space If a guest domain wants to access PCI devices through the frontend driver (coming later in the patch series), it will need access to the I/O space. [ Impact: Allow for domU IO access, preparing for pci passthrough ] Signed-off-by: Alex Nixon Signed-off-by: Jeremy Fitzhardinge Signed-off-by: Konrad Rzeszutek Wilk --- arch/x86/xen/setup.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch') diff --git a/arch/x86/xen/setup.c b/arch/x86/xen/setup.c index 328b003..c413132 100644 --- a/arch/x86/xen/setup.c +++ b/arch/x86/xen/setup.c @@ -260,7 +260,5 @@ void __init xen_arch_setup(void) pm_idle = xen_idle; - paravirt_disable_iospace(); - fiddle_vdso(); } -- cgit v1.1 From d8e0420603cf1ce9cb459c00ea0b7337de41b968 Mon Sep 17 00:00:00 2001 From: Jeremy Fitzhardinge Date: Mon, 9 Feb 2009 12:05:46 -0800 Subject: xen: define BIOVEC_PHYS_MERGEABLE() Impact: allow Xen control of bio merging When running in Xen domain with device access, we need to make sure the block subsystem doesn't merge requests across pages which aren't machine physically contiguous. To do this, we define our own BIOVEC_PHYS_MERGEABLE. When CONFIG_XEN isn't enabled, or we're not running in a Xen domain, this has identical behaviour to the normal implementation. When running under Xen, we also make sure the underlying machine pages are the same or adjacent. Signed-off-by: Jeremy Fitzhardinge Signed-off-by: Konrad Rzeszutek Wilk --- arch/x86/include/asm/io.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch') diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h index 30a3e97..0ad29d4 100644 --- a/arch/x86/include/asm/io.h +++ b/arch/x86/include/asm/io.h @@ -41,6 +41,8 @@ #include #include +#include + #define build_mmio_read(name, size, type, reg, barrier) \ static inline type name(const volatile void __iomem *addr) \ { type ret; asm volatile("mov" size " %1,%0":reg (ret) \ @@ -349,6 +351,17 @@ extern void __iomem *early_memremap(resource_size_t phys_addr, extern void early_iounmap(void __iomem *addr, unsigned long size); extern void fixup_early_ioremap(void); +#ifdef CONFIG_XEN +struct bio_vec; + +extern bool xen_biovec_phys_mergeable(const struct bio_vec *vec1, + const struct bio_vec *vec2); + +#define BIOVEC_PHYS_MERGEABLE(vec1, vec2) \ + (__BIOVEC_PHYS_MERGEABLE(vec1, vec2) && \ + (!xen_domain() || xen_biovec_phys_mergeable(vec1, vec2))) +#endif /* CONFIG_XEN */ + #define IO_SPACE_LIMIT 0xffff #endif /* _ASM_X86_IO_H */ -- cgit v1.1 From 7b586d71858091f0958e5808b7e3d5390c2ae47d Mon Sep 17 00:00:00 2001 From: Jeremy Fitzhardinge Date: Thu, 12 Feb 2009 17:22:49 -0800 Subject: x86/io_apic: add get_nr_irqs_gsi() Impact: new interface to get max GSI Add get_nr_irqs_gsi() to return nr_irqs_gsi. Xen will use this to determine how many irqs it needs to reserve for hardware irqs. Signed-off-by: Jeremy Fitzhardinge Signed-off-by: Konrad Rzeszutek Wilk Reviewed-by: "H. Peter Anvin" Acked-by: Thomas Gleixner Cc: x86@kernel.org Cc: Jesse Barnes --- arch/x86/include/asm/io_apic.h | 1 + arch/x86/kernel/apic/io_apic.c | 5 +++++ 2 files changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/x86/include/asm/io_apic.h b/arch/x86/include/asm/io_apic.h index c8be456..a6b28d0 100644 --- a/arch/x86/include/asm/io_apic.h +++ b/arch/x86/include/asm/io_apic.h @@ -169,6 +169,7 @@ extern void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries); extern int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries); extern void probe_nr_irqs_gsi(void); +extern int get_nr_irqs_gsi(void); extern void setup_ioapic_ids_from_mpc(void); diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c index 20e47e0..44bb914 100644 --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -3649,6 +3649,11 @@ void __init probe_nr_irqs_gsi(void) printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi); } +int get_nr_irqs_gsi(void) +{ + return nr_irqs_gsi; +} + #ifdef CONFIG_SPARSE_IRQ int __init arch_probe_nr_irqs(void) { -- cgit v1.1 From 44de3395a4bb61341dfb7b3b7c94edfddeabae4b Mon Sep 17 00:00:00 2001 From: Alex Nixon Date: Thu, 18 Mar 2010 14:28:12 -0400 Subject: x86/PCI: Clean up pci_cache_line_size Separate out x86 cache_line_size initialisation code into its own function (so it can be shared by Xen later in this patch series) [ Impact: cleanup ] Signed-off-by: Alex Nixon Signed-off-by: Jeremy Fitzhardinge Signed-off-by: Konrad Rzeszutek Wilk Reviewed-by: "H. Peter Anvin" Reviewed-by: Matthew Wilcox Reviewed-by: Jesse Barnes Cc: x86@kernel.org --- arch/x86/include/asm/pci_x86.h | 1 + arch/x86/pci/common.c | 17 ++++++++++------- 2 files changed, 11 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/include/asm/pci_x86.h index 49c7219..7045267 100644 --- a/arch/x86/include/asm/pci_x86.h +++ b/arch/x86/include/asm/pci_x86.h @@ -47,6 +47,7 @@ enum pci_bf_sort_state { extern unsigned int pcibios_max_latency; void pcibios_resource_survey(void); +void pcibios_set_cache_line_size(void); /* pci-pc.c */ diff --git a/arch/x86/pci/common.c b/arch/x86/pci/common.c index a0772af..f7c8a39 100644 --- a/arch/x86/pci/common.c +++ b/arch/x86/pci/common.c @@ -421,16 +421,10 @@ struct pci_bus * __devinit pcibios_scan_root(int busnum) return bus; } - -int __init pcibios_init(void) +void __init pcibios_set_cache_line_size(void) { struct cpuinfo_x86 *c = &boot_cpu_data; - if (!raw_pci_ops) { - printk(KERN_WARNING "PCI: System does not support PCI\n"); - return 0; - } - /* * Set PCI cacheline size to that of the CPU if the CPU has reported it. * (For older CPUs that don't support cpuid, we se it to 32 bytes @@ -445,7 +439,16 @@ int __init pcibios_init(void) pci_dfl_cache_line_size = 32 >> 2; printk(KERN_DEBUG "PCI: Unknown cacheline size. Setting to 32 bytes\n"); } +} + +int __init pcibios_init(void) +{ + if (!raw_pci_ops) { + printk(KERN_WARNING "PCI: System does not support PCI\n"); + return 0; + } + pcibios_set_cache_line_size(); pcibios_resource_survey(); if (pci_bf_sort >= pci_force_bf) -- cgit v1.1 From 5ee01f49c963d5e0b530344f86535ecb7f672064 Mon Sep 17 00:00:00 2001 From: Jeremy Fitzhardinge Date: Thu, 18 Mar 2010 14:31:30 -0400 Subject: x86/PCI: make sure _PAGE_IOMAP it set on pci mappings When mapping pci space via /sys or /proc, make sure we're really doing a hardware mapping by setting _PAGE_IOMAP. [ Impact: bugfix; make PCI mappings map the right pages ] Signed-off-by: Jeremy Fitzhardinge Reviewed-by: Konrad Rzeszutek Wilk Reviewed-by: "H. Peter Anvin" Reviewed-by: Matthew Wilcox Acked-by: Jesse Barnes Cc: x86@kernel.org --- arch/x86/pci/i386.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/x86/pci/i386.c b/arch/x86/pci/i386.c index 5525309..8379c2c 100644 --- a/arch/x86/pci/i386.c +++ b/arch/x86/pci/i386.c @@ -311,6 +311,8 @@ int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, */ prot |= _PAGE_CACHE_UC_MINUS; + prot |= _PAGE_IOMAP; /* creating a mapping for IO */ + vma->vm_page_prot = __pgprot(prot); if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, -- cgit v1.1 From 294ee6f89cfd629e276f632a6003a0fad7785dce Mon Sep 17 00:00:00 2001 From: Stefano Stabellini Date: Wed, 6 Oct 2010 16:12:28 -0400 Subject: x86: Introduce x86_msi_ops Introduce an x86 specific indirect mechanism to setup MSIs. The MSI setup functions become function pointers in an x86_msi_ops struct, that defaults to the implementation in io_apic.c and msi.c. [v2: Use HAVE_DEFAULT_* knobs] Signed-off-by: Stefano Stabellini Reviewed-by: Konrad Rzeszutek Wilk Cc: Thomas Gleixner Cc: "H. Peter Anvin" Cc: x86@kernel.org Cc: Jesse Barnes --- arch/x86/include/asm/pci.h | 33 +++++++++++++++++++++++++++++++-- arch/x86/include/asm/x86_init.h | 9 +++++++++ arch/x86/kernel/apic/io_apic.c | 4 ++-- arch/x86/kernel/x86_init.c | 7 +++++++ 4 files changed, 49 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h index d395540..ca0437c 100644 --- a/arch/x86/include/asm/pci.h +++ b/arch/x86/include/asm/pci.h @@ -7,6 +7,7 @@ #include #include #include +#include #ifdef __KERNEL__ @@ -94,8 +95,36 @@ static inline void early_quirks(void) { } extern void pci_iommu_alloc(void); -/* MSI arch hook */ -#define arch_setup_msi_irqs arch_setup_msi_irqs +#ifdef CONFIG_PCI_MSI +/* MSI arch specific hooks */ +static inline int x86_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) +{ + return x86_msi.setup_msi_irqs(dev, nvec, type); +} + +static inline void x86_teardown_msi_irqs(struct pci_dev *dev) +{ + x86_msi.teardown_msi_irqs(dev); +} + +static inline void x86_teardown_msi_irq(unsigned int irq) +{ + x86_msi.teardown_msi_irq(irq); +} +#define arch_setup_msi_irqs x86_setup_msi_irqs +#define arch_teardown_msi_irqs x86_teardown_msi_irqs +#define arch_teardown_msi_irq x86_teardown_msi_irq +/* implemented in arch/x86/kernel/apic/io_apic. */ +int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type); +void native_teardown_msi_irq(unsigned int irq); +/* default to the implementation in drivers/lib/msi.c */ +#define HAVE_DEFAULT_MSI_TEARDOWN_IRQS +void default_teardown_msi_irqs(struct pci_dev *dev); +#else +#define native_setup_msi_irqs NULL +#define native_teardown_msi_irq NULL +#define default_teardown_msi_irqs NULL +#endif #define PCI_DMA_BUS_IS_PHYS (dma_ops->is_phys) diff --git a/arch/x86/include/asm/x86_init.h b/arch/x86/include/asm/x86_init.h index baa579c..64642ad 100644 --- a/arch/x86/include/asm/x86_init.h +++ b/arch/x86/include/asm/x86_init.h @@ -154,9 +154,18 @@ struct x86_platform_ops { int (*i8042_detect)(void); }; +struct pci_dev; + +struct x86_msi_ops { + int (*setup_msi_irqs)(struct pci_dev *dev, int nvec, int type); + void (*teardown_msi_irq)(unsigned int irq); + void (*teardown_msi_irqs)(struct pci_dev *dev); +}; + extern struct x86_init_ops x86_init; extern struct x86_cpuinit_ops x86_cpuinit; extern struct x86_platform_ops x86_platform; +extern struct x86_msi_ops x86_msi; extern void x86_init_noop(void); extern void x86_init_uint_noop(unsigned int unused); diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c index 44bb914..0885a41 100644 --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -3330,7 +3330,7 @@ static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq) return 0; } -int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) +int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) { int node, ret, sub_handle, index = 0; unsigned int irq, irq_want; @@ -3388,7 +3388,7 @@ error: return ret; } -void arch_teardown_msi_irq(unsigned int irq) +void native_teardown_msi_irq(unsigned int irq) { destroy_irq(irq); } diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c index cd6da6b..ceb2911 100644 --- a/arch/x86/kernel/x86_init.c +++ b/arch/x86/kernel/x86_init.c @@ -6,10 +6,12 @@ #include #include #include +#include #include #include #include +#include #include #include #include @@ -99,3 +101,8 @@ struct x86_platform_ops x86_platform = { }; EXPORT_SYMBOL_GPL(x86_platform); +struct x86_msi_ops x86_msi = { + .setup_msi_irqs = native_setup_msi_irqs, + .teardown_msi_irq = native_teardown_msi_irq, + .teardown_msi_irqs = default_teardown_msi_irqs, +}; -- cgit v1.1 From b5401a96b59475c1c878439caecb8c521bdfd4ad Mon Sep 17 00:00:00 2001 From: Alex Nixon Date: Thu, 18 Mar 2010 16:31:34 -0400 Subject: xen/x86/PCI: Add support for the Xen PCI subsystem The frontend stub lives in arch/x86/pci/xen.c, alongside other sub-arch PCI init code (e.g. olpc.c). It provides a mechanism for Xen PCI frontend to setup/destroy legacy interrupts, MSI/MSI-X, and PCI configuration operations. [ Impact: add core of Xen PCI support ] [ v2: Removed the IOMMU code and only focusing on PCI.] [ v3: removed usage of pci_scan_all_fns as that does not exist] [ v4: introduced pci_xen value to fix compile warnings] [ v5: squished fixes+features in one patch, changed Reviewed-by to Ccs] [ v7: added Acked-by] Signed-off-by: Alex Nixon Signed-off-by: Jeremy Fitzhardinge Signed-off-by: Ian Campbell Signed-off-by: Konrad Rzeszutek Wilk Signed-off-by: Stefano Stabellini Acked-by: Jesse Barnes Cc: "H. Peter Anvin" Cc: Matthew Wilcox Cc: Qing He Cc: Thomas Gleixner Cc: x86@kernel.org --- arch/x86/Kconfig | 5 ++ arch/x86/include/asm/xen/pci.h | 53 +++++++++++++++ arch/x86/pci/Makefile | 1 + arch/x86/pci/xen.c | 147 +++++++++++++++++++++++++++++++++++++++++ arch/x86/xen/enlighten.c | 3 + 5 files changed, 209 insertions(+) create mode 100644 arch/x86/include/asm/xen/pci.h create mode 100644 arch/x86/pci/xen.c (limited to 'arch') diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 8cc5108..74ea59d 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1898,6 +1898,11 @@ config PCI_OLPC def_bool y depends on PCI && OLPC && (PCI_GOOLPC || PCI_GOANY) +config PCI_XEN + def_bool y + depends on PCI && XEN + select SWIOTLB_XEN + config PCI_DOMAINS def_bool y depends on PCI diff --git a/arch/x86/include/asm/xen/pci.h b/arch/x86/include/asm/xen/pci.h new file mode 100644 index 0000000..449c82f --- /dev/null +++ b/arch/x86/include/asm/xen/pci.h @@ -0,0 +1,53 @@ +#ifndef _ASM_X86_XEN_PCI_H +#define _ASM_X86_XEN_PCI_H + +#if defined(CONFIG_PCI_XEN) +extern int __init pci_xen_init(void); +#define pci_xen 1 +#else +#define pci_xen 0 +#define pci_xen_init (0) +#endif + +#if defined(CONFIG_PCI_MSI) +#if defined(CONFIG_PCI_XEN) +/* The drivers/pci/xen-pcifront.c sets this structure to + * its own functions. + */ +struct xen_pci_frontend_ops { + int (*enable_msi)(struct pci_dev *dev, int **vectors); + void (*disable_msi)(struct pci_dev *dev); + int (*enable_msix)(struct pci_dev *dev, int **vectors, int nvec); + void (*disable_msix)(struct pci_dev *dev); +}; + +extern struct xen_pci_frontend_ops *xen_pci_frontend; + +static inline int xen_pci_frontend_enable_msi(struct pci_dev *dev, + int **vectors) +{ + if (xen_pci_frontend && xen_pci_frontend->enable_msi) + return xen_pci_frontend->enable_msi(dev, vectors); + return -ENODEV; +} +static inline void xen_pci_frontend_disable_msi(struct pci_dev *dev) +{ + if (xen_pci_frontend && xen_pci_frontend->disable_msi) + xen_pci_frontend->disable_msi(dev); +} +static inline int xen_pci_frontend_enable_msix(struct pci_dev *dev, + int **vectors, int nvec) +{ + if (xen_pci_frontend && xen_pci_frontend->enable_msix) + return xen_pci_frontend->enable_msix(dev, vectors, nvec); + return -ENODEV; +} +static inline void xen_pci_frontend_disable_msix(struct pci_dev *dev) +{ + if (xen_pci_frontend && xen_pci_frontend->disable_msix) + xen_pci_frontend->disable_msix(dev); +} +#endif /* CONFIG_PCI_XEN */ +#endif /* CONFIG_PCI_MSI */ + +#endif /* _ASM_X86_XEN_PCI_H */ diff --git a/arch/x86/pci/Makefile b/arch/x86/pci/Makefile index a0207a7..effd96e 100644 --- a/arch/x86/pci/Makefile +++ b/arch/x86/pci/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_PCI_BIOS) += pcbios.o obj-$(CONFIG_PCI_MMCONFIG) += mmconfig_$(BITS).o direct.o mmconfig-shared.o obj-$(CONFIG_PCI_DIRECT) += direct.o obj-$(CONFIG_PCI_OLPC) += olpc.o +obj-$(CONFIG_PCI_XEN) += xen.o obj-y += fixup.o obj-$(CONFIG_ACPI) += acpi.o diff --git a/arch/x86/pci/xen.c b/arch/x86/pci/xen.c new file mode 100644 index 0000000..b19c873 --- /dev/null +++ b/arch/x86/pci/xen.c @@ -0,0 +1,147 @@ +/* + * Xen PCI Frontend Stub - puts some "dummy" functions in to the Linux + * x86 PCI core to support the Xen PCI Frontend + * + * Author: Ryan Wilson + */ +#include +#include +#include +#include + +#include +#include + +#include + +#include +#include + +#if defined(CONFIG_PCI_MSI) +#include + +struct xen_pci_frontend_ops *xen_pci_frontend; +EXPORT_SYMBOL_GPL(xen_pci_frontend); + +/* + * For MSI interrupts we have to use drivers/xen/event.s functions to + * allocate an irq_desc and setup the right */ + + +static int xen_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) +{ + int irq, ret, i; + struct msi_desc *msidesc; + int *v; + + v = kzalloc(sizeof(int) * max(1, nvec), GFP_KERNEL); + if (!v) + return -ENOMEM; + + if (!xen_initial_domain()) { + if (type == PCI_CAP_ID_MSIX) + ret = xen_pci_frontend_enable_msix(dev, &v, nvec); + else + ret = xen_pci_frontend_enable_msi(dev, &v); + if (ret) + goto error; + } + i = 0; + list_for_each_entry(msidesc, &dev->msi_list, list) { + irq = xen_allocate_pirq(v[i], 0, /* not sharable */ + (type == PCI_CAP_ID_MSIX) ? + "pcifront-msi-x" : "pcifront-msi"); + if (irq < 0) + return -1; + + ret = set_irq_msi(irq, msidesc); + if (ret) + goto error_while; + i++; + } + kfree(v); + return 0; + +error_while: + unbind_from_irqhandler(irq, NULL); +error: + if (ret == -ENODEV) + dev_err(&dev->dev, "Xen PCI frontend has not registered" \ + " MSI/MSI-X support!\n"); + + kfree(v); + return ret; +} + +static void xen_teardown_msi_irqs(struct pci_dev *dev) +{ + /* Only do this when were are in non-privileged mode.*/ + if (!xen_initial_domain()) { + struct msi_desc *msidesc; + + msidesc = list_entry(dev->msi_list.next, struct msi_desc, list); + if (msidesc->msi_attrib.is_msix) + xen_pci_frontend_disable_msix(dev); + else + xen_pci_frontend_disable_msi(dev); + } + +} + +static void xen_teardown_msi_irq(unsigned int irq) +{ + xen_destroy_irq(irq); +} +#endif + +static int xen_pcifront_enable_irq(struct pci_dev *dev) +{ + int rc; + int share = 1; + + dev_info(&dev->dev, "Xen PCI enabling IRQ: %d\n", dev->irq); + + if (dev->irq < 0) + return -EINVAL; + + if (dev->irq < NR_IRQS_LEGACY) + share = 0; + + rc = xen_allocate_pirq(dev->irq, share, "pcifront"); + if (rc < 0) { + dev_warn(&dev->dev, "Xen PCI IRQ: %d, failed to register:%d\n", + dev->irq, rc); + return rc; + } + return 0; +} + +int __init pci_xen_init(void) +{ + if (!xen_pv_domain() || xen_initial_domain()) + return -ENODEV; + + printk(KERN_INFO "PCI: setting up Xen PCI frontend stub\n"); + + pcibios_set_cache_line_size(); + + pcibios_enable_irq = xen_pcifront_enable_irq; + pcibios_disable_irq = NULL; + +#ifdef CONFIG_ACPI + /* Keep ACPI out of the picture */ + acpi_noirq = 1; +#endif + +#ifdef CONFIG_ISAPNP + /* Stop isapnp from probing */ + isapnp_disable = 1; +#endif + +#ifdef CONFIG_PCI_MSI + x86_msi.setup_msi_irqs = xen_setup_msi_irqs; + x86_msi.teardown_msi_irq = xen_teardown_msi_irq; + x86_msi.teardown_msi_irqs = xen_teardown_msi_irqs; +#endif + return 0; +} diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c index 7d46c84..1ccfa1b 100644 --- a/arch/x86/xen/enlighten.c +++ b/arch/x86/xen/enlighten.c @@ -45,6 +45,7 @@ #include #include #include +#include #include #include #include @@ -1220,6 +1221,8 @@ asmlinkage void __init xen_start_kernel(void) add_preferred_console("xenboot", 0, NULL); add_preferred_console("tty", 0, NULL); add_preferred_console("hvc", 0, NULL); + if (pci_xen) + x86_init.pci.arch_init = pci_xen_init; } else { /* Make sure ACS will be enabled */ pci_request_acs(); -- cgit v1.1 From 74226b8c8a0b10841129916191205095af928da5 Mon Sep 17 00:00:00 2001 From: Konrad Rzeszutek Wilk Date: Thu, 19 Aug 2010 13:34:58 -0400 Subject: xen/pci: Request ACS when Xen-SWIOTLB is activated. It used to done in the Xen startup code but that is not really appropiate. [v2: Update Kconfig with PCI requirement] Signed-off-by: Konrad Rzeszutek Wilk --- arch/x86/xen/pci-swiotlb-xen.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/x86/xen/pci-swiotlb-xen.c b/arch/x86/xen/pci-swiotlb-xen.c index a013ec9..be4d80a 100644 --- a/arch/x86/xen/pci-swiotlb-xen.c +++ b/arch/x86/xen/pci-swiotlb-xen.c @@ -1,6 +1,7 @@ /* Glue code to lib/swiotlb-xen.c */ #include +#include #include #include @@ -54,5 +55,8 @@ void __init pci_xen_swiotlb_init(void) if (xen_swiotlb) { xen_swiotlb_init(1); dma_ops = &xen_swiotlb_dma_ops; + + /* Make sure ACS will be enabled */ + pci_request_acs(); } } -- cgit v1.1 From c115f67c03e468f18431840a97279cd3bfee8ad7 Mon Sep 17 00:00:00 2001 From: Darius Augulis Date: Tue, 19 Oct 2010 13:52:29 +0900 Subject: ARM: S3C64XX: add frame buffer support for mach-real6410 Add support for frame buffer device for mach-real6410. Patch also adds support for feature string parsing for real6410. The feature string is kernel command line passed and currently lets select only LCD configuration. At the moment there is support for two LCD configurations - 4.3" and 7.0". Feature parser is mach-mini2440 based. Signed-off-by: Darius Augulis Signed-off-by: Kukjin Kim --- arch/arm/mach-s3c64xx/Kconfig | 2 + arch/arm/mach-s3c64xx/mach-real6410.c | 146 ++++++++++++++++++++++++++++++++-- 2 files changed, 143 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig index 1e4d78a..3bbd418 100644 --- a/arch/arm/mach-s3c64xx/Kconfig +++ b/arch/arm/mach-s3c64xx/Kconfig @@ -104,6 +104,8 @@ config MACH_REAL6410 select S3C_DEV_HSMMC select S3C_DEV_HSMMC1 select S3C64XX_SETUP_SDHCI + select S3C_DEV_FB + select S3C64XX_SETUP_FB_24BPP help Machine support for the CoreWind REAL6410 diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c index e130379..bed75d2 100644 --- a/arch/arm/mach-s3c64xx/mach-real6410.c +++ b/arch/arm/mach-s3c64xx/mach-real6410.c @@ -12,24 +12,35 @@ * */ -#include -#include +#include #include +#include +#include +#include #include -#include #include -#include #include +#include +#include + #include #include #include + #include -#include +#include +#include +#include #include +#include + #include #include +#include #include +#include