From b5d905c79a3f26bfe2ba755135b4d41e5b364572 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Wed, 16 Oct 2013 20:30:26 +0200 Subject: ARM: dts: sun4i/sun7i: add RTC node Add the RTC node to DTS for Allwinner A10 and Allwinner A20. Signed-off-by: Carlo Caione Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10.dtsi | 6 ++++++ arch/arm/boot/dts/sun7i-a20.dtsi | 6 ++++++ 2 files changed, 12 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 319cc6b..f11f292 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -266,6 +266,12 @@ reg = <0x01c20c90 0x10>; }; + rtc: rtc@01c20d00 { + compatible = "allwinner,sun4i-rtc"; + reg = <0x01c20d00 0x20>; + interrupts = <24>; + }; + sid: eeprom@01c23800 { compatible = "allwinner,sun4i-sid"; reg = <0x01c23800 0x10>; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index e46cfed..830fcd5 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -265,6 +265,12 @@ reg = <0x01c20c90 0x10>; }; + rtc: rtc@01c20d00 { + compatible = "allwinner,sun7i-a20-rtc"; + reg = <0x01c20d00 0x20>; + interrupts = <0 24 1>; + }; + sid: eeprom@01c23800 { compatible = "allwinner,sun7i-a20-sid"; reg = <0x01c23800 0x200>; -- cgit v1.1 From e751cce9b7b106b62c6d2c4f098c28c7feb10ef6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= Date: Sat, 16 Nov 2013 15:17:29 -0300 Subject: ARM: sunxi: dt: add EMAC aliases MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit U-Boot uses the ethernet0 alias to locate the right node to fill in the MAC address of the first ethernet interface. This patch adds the alias on all the sunxi SoCs with EMAC. In this way, people using ethernet in U-Boot (eg, for tftp) can keep a consistent address on both U-Boot and Linux with no additional effort. Signed-off-by: Emilio López Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10.dtsi | 4 ++++ arch/arm/boot/dts/sun5i-a10s.dtsi | 4 ++++ arch/arm/boot/dts/sun7i-a20.dtsi | 4 ++++ 3 files changed, 12 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index f11f292..0bf70ee 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -15,6 +15,10 @@ / { interrupt-parent = <&intc>; + aliases { + ethernet0 = &emac; + }; + cpus { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index 5247674..b4764be 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@ -16,6 +16,10 @@ / { interrupt-parent = <&intc>; + aliases { + ethernet0 = &emac; + }; + cpus { cpu@0 { compatible = "arm,cortex-a8"; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 830fcd5..74bf906 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -16,6 +16,10 @@ / { interrupt-parent = <&gic>; + aliases { + ethernet0 = &emac; + }; + cpus { #address-cells = <1>; #size-cells = <0>; -- cgit v1.1 From 24a661e9945bae764853c98ea0e4f6b3de11a8ea Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 24 Sep 2013 11:10:41 +0300 Subject: ARM: sun6i: Add the reset controller to the DTSI The A31 has a reset controller IP that maintains a few other IPs in reset, among which we can find the UARTs, high speed timers or the I2C. Now that we have support for them, add the reset controllers to the DTSI. Signed-off-by: Maxime Ripard Acked-by: Philipp Zabel --- arch/arm/boot/dts/sun6i-a31.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index c1751a6..7e8d630 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -209,6 +209,24 @@ }; }; + ahb1_rst: reset@01c202c0 { + #reset-cells = <1>; + compatible = "allwinner,sun6i-a31-ahb1-reset"; + reg = <0x01c202c0 0xc>; + }; + + apb1_rst: reset@01c202d0 { + #reset-cells = <1>; + compatible = "allwinner,sun6i-a31-clock-reset"; + reg = <0x01c202d0 0x4>; + }; + + apb2_rst: reset@01c202d8 { + #reset-cells = <1>; + compatible = "allwinner,sun6i-a31-clock-reset"; + reg = <0x01c202d8 0x4>; + }; + timer@01c20c00 { compatible = "allwinner,sun4i-timer"; reg = <0x01c20c00 0xa0>; @@ -232,6 +250,7 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&apb2_gates 16>; + resets = <&apb2_rst 16>; status = "disabled"; }; @@ -242,6 +261,7 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&apb2_gates 17>; + resets = <&apb2_rst 17>; status = "disabled"; }; @@ -252,6 +272,7 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&apb2_gates 18>; + resets = <&apb2_rst 18>; status = "disabled"; }; @@ -262,6 +283,7 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&apb2_gates 19>; + resets = <&apb2_rst 19>; status = "disabled"; }; @@ -272,6 +294,7 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&apb2_gates 20>; + resets = <&apb2_rst 20>; status = "disabled"; }; @@ -282,6 +305,7 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&apb2_gates 21>; + resets = <&apb2_rst 21>; status = "disabled"; }; -- cgit v1.1 From dcdf14c729cb0e9d444a3ebdf76a88fb4f325309 Mon Sep 17 00:00:00 2001 From: Jason Cooper Date: Mon, 14 Oct 2013 17:37:55 +0000 Subject: ARM: mvebu: dts: remove unneeded linux,default-state from led nodes Generally, power LEDs should indicate when power is applied, and go out once power is removed. _Not_ annoy the developer with migraine-inducing blinking reminicent of some badly animated television series designed to sell sugar to children. On a more serious note, most of these OS-specific properties aren't necessary and should be removed. I left two that are legitimately tying disk LEDs to disk activity. Other than that, we keep the state the bootloader left them in until userspace changes the state via sysfs. Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-370-mirabox.dts | 4 ++-- arch/arm/boot/dts/armada-370-netgear-rn102.dts | 2 +- arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 3 +-- arch/arm/boot/dts/dove-cubox.dts | 2 +- arch/arm/boot/dts/kirkwood-dns320.dts | 2 +- arch/arm/boot/dts/kirkwood-dns325.dts | 2 +- arch/arm/boot/dts/kirkwood-dockstar.dts | 2 +- arch/arm/boot/dts/kirkwood-goflexnet.dts | 2 +- arch/arm/boot/dts/kirkwood-ib62x0.dts | 2 +- arch/arm/boot/dts/kirkwood-iconnect.dts | 4 ++-- arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts | 2 +- arch/arm/boot/dts/kirkwood-lsxl.dtsi | 2 +- arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts | 2 +- arch/arm/boot/dts/kirkwood-ns2lite.dts | 2 +- arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts | 2 +- arch/arm/boot/dts/kirkwood-sheevaplug.dts | 2 +- 16 files changed, 18 insertions(+), 19 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts index 2471d9d..41457e5 100644 --- a/arch/arm/boot/dts/armada-370-mirabox.dts +++ b/arch/arm/boot/dts/armada-370-mirabox.dts @@ -74,13 +74,13 @@ green_pwr_led { label = "mirabox:green:pwr"; gpios = <&gpio1 31 1>; - linux,default-trigger = "heartbeat"; + default-state = "keep"; }; blue_stat_led { label = "mirabox:blue:stat"; gpios = <&gpio2 0 1>; - linux,default-trigger = "cpu0"; + default-state = "off"; }; green_stat_led { diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts index 8ac2ac1..df1a1e0 100644 --- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts +++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts @@ -138,7 +138,7 @@ blue_power_led { label = "rn102:blue:pwr"; gpios = <&gpio1 25 1>; /* GPIO 57 Active Low */ - linux,default-trigger = "heartbeat"; + default-state = "keep"; }; green_sata1_led { diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts index 5695afc..99bcf76 100644 --- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts +++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts @@ -103,8 +103,7 @@ green_led { label = "green_led"; gpios = <&gpio1 21 1>; - default-state = "off"; - linux,default-trigger = "heartbeat"; + default-state = "keep"; }; }; diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts index 8349a24..7a70f4ca 100644 --- a/arch/arm/boot/dts/dove-cubox.dts +++ b/arch/arm/boot/dts/dove-cubox.dts @@ -23,7 +23,7 @@ power { label = "Power"; gpios = <&gpio0 18 1>; - linux,default-trigger = "default-on"; + default-state = "keep"; }; }; diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts b/arch/arm/boot/dts/kirkwood-dns320.dts index e112ca6..ff13b93 100644 --- a/arch/arm/boot/dts/kirkwood-dns320.dts +++ b/arch/arm/boot/dts/kirkwood-dns320.dts @@ -25,7 +25,7 @@ blue-power { label = "dns320:blue:power"; gpios = <&gpio0 26 1>; /* GPIO 26 Active Low */ - linux,default-trigger = "default-on"; + default-state = "keep"; }; blue-usb { label = "dns320:blue:usb"; diff --git a/arch/arm/boot/dts/kirkwood-dns325.dts b/arch/arm/boot/dts/kirkwood-dns325.dts index 5119fb8..f433043 100644 --- a/arch/arm/boot/dts/kirkwood-dns325.dts +++ b/arch/arm/boot/dts/kirkwood-dns325.dts @@ -25,7 +25,7 @@ white-power { label = "dns325:white:power"; gpios = <&gpio0 26 1>; /* GPIO 26 Active Low */ - linux,default-trigger = "default-on"; + default-state = "keep"; }; white-usb { label = "dns325:white:usb"; diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts index 33ff368..a5f1e39 100644 --- a/arch/arm/boot/dts/kirkwood-dockstar.dts +++ b/arch/arm/boot/dts/kirkwood-dockstar.dts @@ -43,7 +43,7 @@ health { label = "status:green:health"; gpios = <&gpio1 14 1>; - linux,default-trigger = "default-on"; + default-state = "keep"; }; fault { label = "status:orange:fault"; diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts index a43bebb..a9e98c9 100644 --- a/arch/arm/boot/dts/kirkwood-goflexnet.dts +++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts @@ -86,7 +86,7 @@ health { label = "status:green:health"; gpios = <&gpio1 14 1>; - linux,default-trigger = "default-on"; + default-state = "keep"; }; fault { label = "status:orange:fault"; diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts index c5fb02f..dbc9033 100644 --- a/arch/arm/boot/dts/kirkwood-ib62x0.dts +++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts @@ -82,7 +82,7 @@ green-os { label = "ib62x0:green:os"; gpios = <&gpio0 25 0>; - linux,default-trigger = "default-on"; + default-state = "keep"; }; red-os { label = "ib62x0:red:os"; diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts index 4a62b20..399fb0c 100644 --- a/arch/arm/boot/dts/kirkwood-iconnect.dts +++ b/arch/arm/boot/dts/kirkwood-iconnect.dts @@ -95,12 +95,12 @@ led-level { label = "led_level"; gpios = <&gpio1 9 0>; - linux,default-trigger = "default-on"; + default-state = "on"; }; power-blue { label = "power:blue"; gpios = <&gpio1 10 0>; - linux,default-trigger = "timer"; + default-state = "keep"; }; power-red { label = "power:red"; diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts index d15395d..b9de441 100644 --- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts +++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts @@ -128,7 +128,7 @@ power_led { label = "status:white:power_led"; gpios = <&gpio0 16 0>; - linux,default-trigger = "default-on"; + default-state = "keep"; }; rebuild_led { label = "status:white:rebuild_led"; diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi index 4e8f9e4..bc34a60 100644 --- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi +++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi @@ -150,7 +150,7 @@ led@4 { label = "lsxl:blue:power"; gpios = <&gpio1 7 1>; - linux,default-trigger = "default-on"; + default-state = "keep"; }; led@5 { diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts index e6a102c..6b96e85 100644 --- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts +++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts @@ -113,7 +113,7 @@ power_led { label = "status:blue:power_led"; gpios = <&gpio0 31 1>; /* GPIO 31 Active Low */ - linux,default-trigger = "default-on"; + default-state = "keep"; }; activity_led { label = "status:blue:activity_led"; diff --git a/arch/arm/boot/dts/kirkwood-ns2lite.dts b/arch/arm/boot/dts/kirkwood-ns2lite.dts index 2796070..7cea2a4 100644 --- a/arch/arm/boot/dts/kirkwood-ns2lite.dts +++ b/arch/arm/boot/dts/kirkwood-ns2lite.dts @@ -26,7 +26,7 @@ blue-sata { label = "ns2:blue:sata"; gpios = <&gpio0 30 1>; - linux,default-trigger = "default-on"; + linux,default-trigger = "ide-disk"; }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts b/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts index eac6a21..ce9b3be 100644 --- a/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts +++ b/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts @@ -37,7 +37,7 @@ health { label = "sheevaplug:blue:health"; gpios = <&gpio1 17 1>; - linux,default-trigger = "default-on"; + default-state = "keep"; }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug.dts b/arch/arm/boot/dts/kirkwood-sheevaplug.dts index bb61918..1eff4f6 100644 --- a/arch/arm/boot/dts/kirkwood-sheevaplug.dts +++ b/arch/arm/boot/dts/kirkwood-sheevaplug.dts @@ -32,7 +32,7 @@ health { label = "sheevaplug:blue:health"; gpios = <&gpio1 17 1>; - linux,default-trigger = "default-on"; + default-state = "keep"; }; misc { -- cgit v1.1 From 140790113e1212a6a63fd6cc99fdd7ef697cb480 Mon Sep 17 00:00:00 2001 From: Simon Baatz Date: Thu, 31 Oct 2013 20:35:19 +0100 Subject: ARM: kirkwood: Cleanup comments in Sheevaplug dts files Change the file names given in the comments of the Sheevaplug dts files to actually match the real file names. Signed-off-by: Simon Baatz Acked-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi | 2 +- arch/arm/boot/dts/kirkwood-sheevaplug.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi index 1173d7f..7b1cd99 100644 --- a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi +++ b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi @@ -1,5 +1,5 @@ /* - * kirkwood-sheevaplug-common.dts - Common parts for Sheevaplugs + * kirkwood-sheevaplug-common.dtsi - Common parts for Sheevaplugs * * Copyright (C) 2013 Simon Baatz * diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug.dts b/arch/arm/boot/dts/kirkwood-sheevaplug.dts index 1eff4f6..c01f9c7 100644 --- a/arch/arm/boot/dts/kirkwood-sheevaplug.dts +++ b/arch/arm/boot/dts/kirkwood-sheevaplug.dts @@ -1,5 +1,5 @@ /* - * kirkwood-sheevaplug-esata.dts - Device tree file for Sheevaplug + * kirkwood-sheevaplug.dts - Device tree file for Sheevaplug * * Copyright (C) 2013 Simon Baatz * -- cgit v1.1 From cb28e2537a6f074f21f77ce181c90b6eb56c1516 Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Thu, 7 Nov 2013 12:17:33 -0300 Subject: ARM: mvebu: Add support for NAND controller in Armada 370/XP The Armada 370 and Armada XP SoC have a NAND controller (aka NFCv2). This commit adds support for it in Armada 370 and Armada XP SoC common devicetree. Signed-off-by: Ezequiel Garcia Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-370-xp.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 00d6a79..f2b6ae4 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -257,6 +257,15 @@ status = "disabled"; }; + nand@d0000 { + compatible = "marvell,armada370-nand"; + reg = <0xd0000 0x54>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = <113>; + clocks = <&coredivclk 0>; + status = "disabled"; + }; }; }; -- cgit v1.1 From 2be2bc39c6f0a2b0079e288c7e781759aef08457 Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Thu, 7 Nov 2013 12:17:34 -0300 Subject: ARM: mvebu: Enable NAND controller in Armada XP GP board The Armada XP GP board has a NAND flash, so enable it in the devicetree. In order to skip the driver's custom device detection and use only ONFI detection, the "marvell,keep-config" parameter is used. This is needed because we haven't support for setting the timings parameters yet and must rely in bootloader's. Signed-off-by: Ezequiel Garcia Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-xp-gp.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts index 2298e4a..274e2ad 100644 --- a/arch/arm/boot/dts/armada-xp-gp.dts +++ b/arch/arm/boot/dts/armada-xp-gp.dts @@ -175,6 +175,14 @@ spi-max-frequency = <108000000>; }; }; + + nand@d0000 { + status = "okay"; + num-cs = <1>; + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + }; }; }; }; -- cgit v1.1 From d8c552dddfbf1ceadee93496eb40638654f767fc Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Thu, 7 Nov 2013 12:17:35 -0300 Subject: ARM: mvebu: Enable NAND controller in Armada 370 Mirabox The Armada 370 Mirabox has a NAND flash, so enable it in the devicetree and add the partitions as prepared in the factory images. In order to skip the driver's custom device detection and use only ONFI detection, the "marvell,keep-config" parameter is used. This is needed because we have no support for setting the timings parameters yet. Signed-off-by: Ezequiel Garcia Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-370-mirabox.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts index 41457e5..944e878 100644 --- a/arch/arm/boot/dts/armada-370-mirabox.dts +++ b/arch/arm/boot/dts/armada-370-mirabox.dts @@ -139,6 +139,27 @@ reg = <0x25>; }; }; + + nand@d0000 { + status = "okay"; + num-cs = <1>; + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + + partition@0 { + label = "U-Boot"; + reg = <0 0x400000>; + }; + partition@400000 { + label = "Linux"; + reg = <0x400000 0x400000>; + }; + partition@800000 { + label = "Filesystem"; + reg = <0x800000 0x3f800000>; + }; + }; }; }; }; -- cgit v1.1 From 6b6430e82331e5508d6476b4c4d447f3d03ec381 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Thu, 14 Nov 2013 14:53:08 +0000 Subject: ARM: orion5x: Fix typo in device_type property of phy node This patch fixes a typo for device_type property of phy node. This can work as of today but once a checks are added in generic code this typo will stop phy from working. Signed-off-by: Srinivas Kandagatla Acked-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts index aed83de..fcc5bb6 100644 --- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts +++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts @@ -58,7 +58,7 @@ status = "okay"; ethphy: ethernet-phy { - device-type = "ethernet-phy"; + device_type = "ethernet-phy"; reg = <8>; }; }; -- cgit v1.1 From 9e52c63992c19b1d2e9a6b6b8ba61aaf35e9fd17 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Sun, 24 Nov 2013 16:47:51 +0000 Subject: ARM: dove: Fix typo in device_type property of phy node This patch fixes a typo for device_type property of phy node. This can work as of today but once a checks are added in generic code this typo will stop phy from working. Acked-by: Andrew Lunn Signed-off-by: Srinivas Kandagatla --- arch/arm/boot/dts/dove.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index 113a8bc..abd7a6f 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -559,7 +559,7 @@ status = "disabled"; ethphy: ethernet-phy { - device-type = "ethernet-phy"; + device_type = "ethernet-phy"; /* set phy address in board file */ }; }; -- cgit v1.1 From 0242399e4ee419334b55662be12b10dafa362658 Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Fri, 15 Nov 2013 15:20:24 +0100 Subject: ARM: kirkwood: provide pinctrl default to sdio nodes SDIO controllers found on Marvell Kirkwood 6281/6282 SoCs require pins to be muxed by pinctrl. As there is only one sane pinctrl setting for this, provide default pinctrl properties to the controller nodes. Signed-off-by: Sebastian Hesselbarth Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood-6281.dtsi | 2 ++ arch/arm/boot/dts/kirkwood-6282.dtsi | 2 ++ 2 files changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi index 650ef30..e4e1968 100644 --- a/arch/arm/boot/dts/kirkwood-6281.dtsi +++ b/arch/arm/boot/dts/kirkwood-6281.dtsi @@ -97,6 +97,8 @@ reg = <0x90000 0x200>; interrupts = <28>; clocks = <&gate_clk 4>; + pinctrl-0 = <&pmx_sdio>; + pinctrl-names = "default"; bus-width = <4>; cap-sdio-irq; cap-sd-highspeed; diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi index 3933a33..f010c21 100644 --- a/arch/arm/boot/dts/kirkwood-6282.dtsi +++ b/arch/arm/boot/dts/kirkwood-6282.dtsi @@ -125,6 +125,8 @@ reg = <0x90000 0x200>; interrupts = <28>; clocks = <&gate_clk 4>; + pinctrl-0 = <&pmx_sdio>; + pinctrl-names = "default"; bus-width = <4>; cap-sdio-irq; cap-sd-highspeed; -- cgit v1.1 From 0932f1499fcebc52c8764419d63cdb1a00dac08f Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Fri, 15 Nov 2013 15:20:25 +0100 Subject: ARM: kirkwood: mark guruplug sdio as non-removable Globalscale Guruplug has AW-GH381 WiFi/BT on sdio which is always present and cannot be detected in any way. Therefore, mark the node as non-removable instead of broken-cd. While at it, also put a note about connected WiFi/BT chip above. Signed-off-by: Sebastian Hesselbarth Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts index d30a91a..4d2a70f 100644 --- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts +++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts @@ -45,10 +45,10 @@ nr-ports = <1>; }; + /* AzureWave AW-GH381 WiFi/BT */ mvsdio@90000 { status = "okay"; - /* No CD or WP GPIOs */ - broken-cd; + non-removable; }; }; -- cgit v1.1 From 100a5fa9752149213204f095c37323fc4ee1b246 Mon Sep 17 00:00:00 2001 From: Arnaud Ebalard Date: Fri, 22 Nov 2013 00:00:12 +0100 Subject: ARM: mvebu: Add RN104 SATA LEDs driven via NXP PCA9554 I2C to GPIO muxer NETGEAR ReadyNAS 104 has a NXP PCA9554 I2C to GPIO chip. Among the 8 GPIO lines the chip makes available, four are used on the device to control the SATA LEDs (the four remaining ones are used for SATA disk presence). This patch adds DT entries for NXP PCA9554 and the four SATA GPIO LEDs. Signed-off-by: Arnaud Ebalard Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-370-netgear-rn104.dts | 32 ++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/armada-370-netgear-rn104.dts index b0b32f5..50b5150 100644 --- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts +++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts @@ -12,6 +12,7 @@ /dts-v1/; #include "armada-370.dtsi" +#include / { model = "NETGEAR ReadyNAS 104"; @@ -123,6 +124,13 @@ fan_startv = <1>; pwm_polarity = <0>; }; + + pca9554: pca9554@23 { + compatible = "nxp,pca9554"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x23>; + }; }; }; }; @@ -154,6 +162,30 @@ gpios = <&gpio2 0 1>; /* GPIO 64 Active Low */ linux,default-trigger = "keep"; }; + + sata1_led { + label = "rn104:blue:sata1"; + gpios = <&pca9554 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + sata2_led { + label = "rn104:blue:sata2"; + gpios = <&pca9554 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + sata3_led { + label = "rn104:blue:sata3"; + gpios = <&pca9554 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + sata4_led { + label = "rn104:blue:sata4"; + gpios = <&pca9554 3 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; }; gpio_keys { -- cgit v1.1 From bfc2e5f560c7af89ee1cece8a0018a44011c24b2 Mon Sep 17 00:00:00 2001 From: Arnaud Ebalard Date: Fri, 22 Nov 2013 15:58:04 +0100 Subject: ARM: mvebu: Add DT entry for ReadyNAS Duo v2 to use gpio-poweroff driver Without that fix, at the end of the shutdown process, the board is still powered (led glowing, fan running, ...). Signed-off-by: Arnaud Ebalard Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts index 6b96e85..3627702 100644 --- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts +++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts @@ -1,5 +1,6 @@ /dts-v1/; +#include #include "kirkwood.dtsi" #include "kirkwood-6282.dtsi" @@ -60,6 +61,10 @@ marvell,pins = "mpp29"; marvell,function = "gpio"; }; + pmx_poweroff: pmx-poweroff { + marvell,pins = "mpp30"; + marvell,function = "gpio"; + }; }; clocks { @@ -158,6 +163,13 @@ }; }; + gpio-poweroff { + compatible = "gpio-poweroff"; + pinctrl-0 = <&pmx_poweroff>; + pinctrl-names = "default"; + gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; -- cgit v1.1 From 5b67cd630d06078c3d6f8dd6ccf552c78f08c497 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Tue, 26 Nov 2013 16:07:52 +0000 Subject: ARM: Dove: Add DT node for PMU interrupt controller. Instantiate the PMU interrupt controller which Dove has. Signed-off-by: Andrew Lunn Tested-by: Sebastian Hesselbarth Signed-off-by: Jason Cooper --- arch/arm/boot/dts/dove.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index abd7a6f..56e5d37 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -136,6 +136,15 @@ marvell,#interrupts = <5>; }; + pmu_intc: pmu-interrupt-ctrl@d0050 { + compatible = "marvell,dove-pmu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xd0050 0x8>; + interrupts = <33>; + marvell,#interrupts = <7>; + }; + core_clk: core-clocks@d0214 { compatible = "marvell,dove-core-clock"; reg = <0xd0214 0x4>; -- cgit v1.1 From bd22bb23919e6727967e90eb89bb41ab790bcd2d Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Tue, 26 Nov 2013 16:10:49 +0000 Subject: ARM: Dove: Add RTC interrupt via PMU interrupt controller. The RTC on Dove has an interrupt on the PMU interrupt controller. Add this interrupt to the RTC node. Tested using the "RTC Driver Test Example" Signed-off-by: Andrew Lunn Tested-by: Sebastian Hesselbarth Signed-off-by: Jason Cooper --- arch/arm/boot/dts/dove.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index 56e5d37..db24b41 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -506,6 +506,8 @@ rtc: real-time-clock@d8500 { compatible = "marvell,orion-rtc"; reg = <0xd8500 0x20>; + interrupt-parent = <&pmu_intc>; + interrupts = <5>; }; crypto: crypto-engine@30000 { -- cgit v1.1 From 7e0a51a0312da5d1f7cb164355924c5cdf39082d Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 15 Oct 2013 23:00:10 +0200 Subject: ARM: ux500: adjust the TC3589x devices to the binding The TC3589x devices appearing in the ST Ericsson device trees are adjusted to use the new binding so this is in a good shape, and we add the keypad on the TVK1281618 UIB so this is working again. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-href-tvk1281618.dtsi | 39 +++++++++++++++++++++++++----- arch/arm/boot/dts/ste-hrefprev60.dtsi | 8 +++--- 2 files changed, 37 insertions(+), 10 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi index 76d3ef1..61b180e 100644 --- a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi +++ b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi @@ -15,26 +15,53 @@ / { soc { - /* Add Synaptics touch screen, TC35892 keypad etc here */ + /* Add Synaptics touch screen, TC35893 keypad etc here */ i2c@80004000 { - tc3589x@44 { - compatible = "tc3589x"; + tc35893@44 { + compatible = "toshiba,tc35893"; reg = <0x44>; interrupt-parent = <&gpio6>; interrupts = <26 IRQ_TYPE_EDGE_RISING>; interrupt-controller; - #interrupt-cells = <2>; + #interrupt-cells = <1>; tc3589x_gpio { - compatible = "tc3589x-gpio"; - interrupts = <0 IRQ_TYPE_EDGE_RISING>; + compatible = "toshiba,tc3589x-gpio"; + interrupts = <0>; interrupt-controller; #interrupt-cells = <2>; gpio-controller; #gpio-cells = <2>; }; + tc3589x_keypad { + compatible = "toshiba,tc3589x-keypad"; + interrupts = <6>; + debounce-delay-ms = <4>; + keypad,num-columns = <8>; + keypad,num-rows = <8>; + linux,no-autorepeat; + linux,wakeup; + linux,keymap = <0x0301006b + 0x04010066 + 0x06040072 + 0x040200d7 + 0x0303006a + 0x0205000e + 0x0607008b + 0x0500001c + 0x0403000b + 0x03040034 + 0x05020067 + 0x0305006c + 0x040500e7 + 0x0005009e + 0x06020073 + 0x01030039 + 0x07060069 + 0x050500d9>; + }; }; }; }; diff --git a/arch/arm/boot/dts/ste-hrefprev60.dtsi b/arch/arm/boot/dts/ste-hrefprev60.dtsi index b2cd7bc..6b271a4 100644 --- a/arch/arm/boot/dts/ste-hrefprev60.dtsi +++ b/arch/arm/boot/dts/ste-hrefprev60.dtsi @@ -28,18 +28,18 @@ reg = <0x33>; }; - tc3589x@42 { - compatible = "tc3589x"; + tc35892@42 { + compatible = "toshiba,tc35892"; reg = <0x42>; interrupt-parent = <&gpio6>; interrupts = <25 IRQ_TYPE_EDGE_RISING>; interrupt-controller; - #interrupt-cells = <2>; + #interrupt-cells = <1>; tc3589x_gpio: tc3589x_gpio { compatible = "tc3589x-gpio"; - interrupts = <0 IRQ_TYPE_EDGE_RISING>; + interrupts = <0>; interrupt-controller; #interrupt-cells = <2>; -- cgit v1.1 From d4033047bb07efd6377c45b7b92c308e3b52a6a0 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 6 Nov 2013 10:05:42 +0000 Subject: ARM: ux500: Remove legacy ATAG SSP support This hasn't been used since we converted the platform to DT only. Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/mach-ux500/board-mop500.c | 30 ------------------------------ arch/arm/mach-ux500/board-mop500.h | 1 - 2 files changed, 31 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index 514d40b..d552163 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c @@ -46,33 +46,3 @@ struct ab8500_platform_data ab8500_platdata = { .irq_base = MOP500_AB8500_IRQ_BASE, .regulator = &ab8500_regulator_plat_data, }; - -#ifdef CONFIG_STE_DMA40 -static struct stedma40_chan_cfg ssp0_dma_cfg_rx = { - .mode = STEDMA40_MODE_LOGICAL, - .dir = DMA_DEV_TO_MEM, - .dev_type = DB8500_DMA_DEV8_SSP0, -}; - -static struct stedma40_chan_cfg ssp0_dma_cfg_tx = { - .mode = STEDMA40_MODE_LOGICAL, - .dir = DMA_MEM_TO_DEV, - .dev_type = DB8500_DMA_DEV8_SSP0, -}; -#endif - -struct pl022_ssp_controller ssp0_plat = { - .bus_id = 0, -#ifdef CONFIG_STE_DMA40 - .enable_dma = 1, - .dma_filter = stedma40_filter, - .dma_rx_param = &ssp0_dma_cfg_rx, - .dma_tx_param = &ssp0_dma_cfg_tx, -#else - .enable_dma = 0, -#endif - /* on this platform, gpio 31,142,144,214 & - * 224 are connected as chip selects - */ - .num_chipselect = 5, -}; diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h index 511d6fe..d48e866 100644 --- a/arch/arm/mach-ux500/board-mop500.h +++ b/arch/arm/mach-ux500/board-mop500.h @@ -87,7 +87,6 @@ extern struct msp_i2s_platform_data msp0_platform_data; extern struct msp_i2s_platform_data msp1_platform_data; extern struct msp_i2s_platform_data msp2_platform_data; extern struct msp_i2s_platform_data msp3_platform_data; -extern struct pl022_ssp_controller ssp0_plat; void __init mop500_pinmaps_init(void); void __init snowball_pinmaps_init(void); -- cgit v1.1 From 6f6d6433c08089e033756f55aecbd07d693536c4 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 6 Nov 2013 10:05:43 +0000 Subject: ARM: ux500: Consolidate [A|D]B8500 platform data Move the platform data from all these files into one, delete empty files and remove all references to them. Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/mach-ux500/Makefile | 4 +-- arch/arm/mach-ux500/board-mop500-audio.c | 2 -- arch/arm/mach-ux500/board-mop500-sdi.c | 2 -- arch/arm/mach-ux500/board-mop500.c | 48 -------------------------------- arch/arm/mach-ux500/cpu-db8500.c | 18 ++++++++++-- arch/arm/mach-ux500/cpu.c | 1 - arch/arm/mach-ux500/devices-db8500.c | 28 ------------------- arch/arm/mach-ux500/devices-db8500.h | 19 ------------- arch/arm/mach-ux500/devices.h | 15 ---------- 9 files changed, 17 insertions(+), 120 deletions(-) delete mode 100644 arch/arm/mach-ux500/board-mop500.c delete mode 100644 arch/arm/mach-ux500/devices-db8500.c delete mode 100644 arch/arm/mach-ux500/devices-db8500.h delete mode 100644 arch/arm/mach-ux500/devices.h (limited to 'arch') diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile index 616b96e..66f351f 100644 --- a/arch/arm/mach-ux500/Makefile +++ b/arch/arm/mach-ux500/Makefile @@ -4,8 +4,8 @@ obj-y := cpu.o devices.o id.o timer.o pm.o obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o -obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o -obj-$(CONFIG_MACH_MOP500) += board-mop500.o board-mop500-sdi.o \ +obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o +obj-$(CONFIG_MACH_MOP500) += board-mop500-sdi.o \ board-mop500-regulators.o \ board-mop500-pins.o \ board-mop500-audio.o diff --git a/arch/arm/mach-ux500/board-mop500-audio.c b/arch/arm/mach-ux500/board-mop500-audio.c index 154e15f..d528059 100644 --- a/arch/arm/mach-ux500/board-mop500-audio.c +++ b/arch/arm/mach-ux500/board-mop500-audio.c @@ -10,13 +10,11 @@ #include #include -#include "devices.h" #include "irqs.h" #include #include "ste-dma40-db8500.h" #include "board-mop500.h" -#include "devices-db8500.h" static struct stedma40_chan_cfg msp0_dma_rx = { .high_priority = true, diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c index 26600a1..fcbf3a1 100644 --- a/arch/arm/mach-ux500/board-mop500-sdi.c +++ b/arch/arm/mach-ux500/board-mop500-sdi.c @@ -14,10 +14,8 @@ #include #include -#include "devices.h" #include "db8500-regs.h" -#include "devices-db8500.h" #include "board-mop500.h" #include "ste-dma40-db8500.h" diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c deleted file mode 100644 index d552163..0000000 --- a/arch/arm/mach-ux500/board-mop500.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (C) 2008-2012 ST-Ericsson - * - * Author: Srinidhi KASAGAR - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2, as - * published by the Free Software Foundation. - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "setup.h" -#include "devices.h" -#include "irqs.h" - -#include "ste-dma40-db8500.h" -#include "db8500-regs.h" -#include "devices-db8500.h" -#include "board-mop500.h" -#include "board-mop500-regulators.h" - -struct ab8500_platform_data ab8500_platdata = { - .irq_base = MOP500_AB8500_IRQ_BASE, - .regulator = &ab8500_regulator_plat_data, -}; diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index 2e85c1e..0b5b27b 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c @@ -28,14 +28,26 @@ #include #include "setup.h" -#include "devices.h" #include "irqs.h" -#include "devices-db8500.h" -#include "db8500-regs.h" +#include "board-mop500-regulators.h" #include "board-mop500.h" +#include "db8500-regs.h" #include "id.h" +struct ab8500_platform_data ab8500_platdata = { + .irq_base = MOP500_AB8500_IRQ_BASE, + .regulator = &ab8500_regulator_plat_data, +}; + +struct prcmu_pdata db8500_prcmu_pdata = { + .ab_platdata = &ab8500_platdata, + .ab_irq = IRQ_DB8500_AB8500, + .irq_base = IRQ_PRCMU_BASE, + .version_offset = DB8500_PRCMU_FW_VERSION_OFFSET, + .legacy_offset = DB8500_PRCMU_LEGACY_OFFSET, +}; + /* minimum static i/o mapping required to boot U8500 platforms */ static struct map_desc u8500_uart_io_desc[] __initdata = { __IO_DEV_DESC(U8500_UART0_BASE, SZ_4K), diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c index f84d439..8f8004f 100644 --- a/arch/arm/mach-ux500/cpu.c +++ b/arch/arm/mach-ux500/cpu.c @@ -25,7 +25,6 @@ #include #include "setup.h" -#include "devices.h" #include "board-mop500.h" #include "db8500-regs.h" diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c deleted file mode 100644 index c59f89d..0000000 --- a/arch/arm/mach-ux500/devices-db8500.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Rabin Vincent for ST-Ericsson - * License terms: GNU General Public License (GPL) version 2 - */ - -#include -#include -#include -#include -#include -#include -#include - -#include "setup.h" -#include "irqs.h" - -#include "db8500-regs.h" -#include "devices-db8500.h" - -struct prcmu_pdata db8500_prcmu_pdata = { - .ab_platdata = &ab8500_platdata, - .ab_irq = IRQ_DB8500_AB8500, - .irq_base = IRQ_PRCMU_BASE, - .version_offset = DB8500_PRCMU_FW_VERSION_OFFSET, - .legacy_offset = DB8500_PRCMU_LEGACY_OFFSET, -}; diff --git a/arch/arm/mach-ux500/devices-db8500.h b/arch/arm/mach-ux500/devices-db8500.h deleted file mode 100644 index b8ffc99..0000000 --- a/arch/arm/mach-ux500/devices-db8500.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Rabin Vincent for ST-Ericsson - * License terms: GNU General Public License (GPL), version 2. - */ - -#ifndef __DEVICES_DB8500_H -#define __DEVICES_DB8500_H - -#include "irqs.h" -#include "db8500-regs.h" - -struct platform_device; - -extern struct ab8500_platform_data ab8500_platdata; -extern struct prcmu_pdata db8500_prcmu_pdata; - -#endif diff --git a/arch/arm/mach-ux500/devices.h b/arch/arm/mach-ux500/devices.h deleted file mode 100644 index 5bca7c6..0000000 --- a/arch/arm/mach-ux500/devices.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * License terms: GNU General Public License (GPL) version 2 - */ - -#ifndef __ASM_ARCH_DEVICES_H__ -#define __ASM_ARCH_DEVICES_H__ - -struct platform_device; -struct amba_device; - -extern struct amba_device ux500_pl031_device; - -#endif -- cgit v1.1 From 618111ca9adc1a871ddcbfd953342e94975c3b34 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 6 Nov 2013 10:16:16 +0000 Subject: ARM: ux500: Add DMA config bindings for MSP devices Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-dbx5x0.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index 7da99fe..50ff5ab 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -913,6 +913,10 @@ interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; v-ape-supply = <&db8500_vape_reg>; + dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */ + <&dma 31 0 0x10>; /* Logical - MemToDev - HighPrio */ + dma-names = "rx", "tx"; + clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>; clock-names = "msp", "apb_pclk"; @@ -925,6 +929,9 @@ interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>; v-ape-supply = <&db8500_vape_reg>; + dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */ + dma-names = "tx"; + clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>; clock-names = "msp", "apb_pclk"; @@ -938,6 +945,11 @@ interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; v-ape-supply = <&db8500_vape_reg>; + dmas = <&dma 14 0 0x12>, /* Logical - DevToMem - HighPrio */ + <&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev + HighPrio - Fixed */ + dma-names = "rx", "tx"; + clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>; clock-names = "msp", "apb_pclk"; @@ -950,6 +962,9 @@ interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>; v-ape-supply = <&db8500_vape_reg>; + dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */ + dma-names = "rx"; + clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>; clock-names = "msp", "apb_pclk"; -- cgit v1.1 From 3bfdebbaebed8238ac7fb7934791b0231e0f1e65 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 13 Nov 2013 10:32:20 +0100 Subject: ARM: ux500: move UART pin control to the device tree This moves the static, device-tied pin control configuration out of the board file board-mop500-pins.c and into the device tree. We create a new .dtsi-file to be shared between all the MOP500-related boards, that include all HREF variants and the Snowball board. Assign pin states for HREF and Snowball boards alike. Cc: Lee Jones Cc: Patrice Chotard Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-href-family-pinctrl.dtsi | 114 +++++++++++++++++++++++++ arch/arm/boot/dts/ste-href.dtsi | 10 +++ arch/arm/boot/dts/ste-snowball.dts | 10 +++ arch/arm/mach-ux500/board-mop500-pins.c | 52 ----------- 4 files changed, 134 insertions(+), 52 deletions(-) create mode 100644 arch/arm/boot/dts/ste-href-family-pinctrl.dtsi (limited to 'arch') diff --git a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi new file mode 100644 index 0000000..d979de2 --- /dev/null +++ b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi @@ -0,0 +1,114 @@ +/* + * Copyright 2013 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include "ste-nomadik-pinctrl.dtsi" + +/ { + soc { + pinctrl { + /* Settings for all UART default and sleep states */ + uart0 { + uart0_default_mode: uart0_default { + default_mux { + ste,function = "u0"; + ste,pins = "u0_a_1"; + }; + default_cfg1 { + ste,pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */ + ste,config = <&in_pu>; + }; + + default_cfg2 { + ste,pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */ + ste,config = <&out_hi>; + }; + }; + + uart0_sleep_mode: uart0_sleep { + sleep_cfg1 { + ste,pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */ + ste,config = <&slpm_in_wkup_pdis>; + }; + + sleep_cfg2 { + ste,pins = "GPIO1_AJ3"; /* RTS */ + ste,config = <&slpm_out_hi_wkup_pdis>; + }; + + sleep_cfg3 { + ste,pins = "GPIO3_AH3"; /* TXD */ + ste,config = <&slpm_out_wkup_pdis>; + }; + }; + }; + + uart1 { + uart1_default_mode: uart1_default { + default_mux { + ste,function = "u1"; + ste,pins = "u1rxtx_a_1"; + }; + default_cfg1 { + ste,pins = "GPIO4_AH6"; /* RXD */ + ste,config = <&in_pu>; + }; + + default_cfg2 { + ste,pins = "GPIO5_AG6"; /* TXD */ + ste,config = <&out_hi>; + }; + }; + + uart1_sleep_mode: uart1_sleep { + sleep_cfg1 { + ste,pins = "GPIO4_AH6"; /* RXD */ + ste,config = <&slpm_in_wkup_pdis>; + }; + + sleep_cfg2 { + ste,pins = "GPIO5_AG6"; /* TXD */ + ste,config = <&slpm_out_wkup_pdis>; + }; + }; + }; + + uart2 { + uart2_default_mode: uart2_default { + default_mux { + ste,function = "u2"; + ste,pins = "u2rxtx_c_1"; + }; + default_cfg1 { + ste,pins = "GPIO29_W2"; /* RXD */ + ste,config = <&in_pu>; + }; + + default_cfg2 { + ste,pins = "GPIO30_W3"; /* TXD */ + ste,config = <&out_hi>; + }; + }; + + uart2_sleep_mode: uart2_sleep { + sleep_cfg1 { + ste,pins = "GPIO29_W2"; /* RXD */ + ste,config = <&in_wkup_pdis>; + }; + + sleep_cfg2 { + ste,pins = "GPIO30_W3"; /* TXD */ + ste,config = <&out_wkup_pdis>; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi index aa3f020..914a5f4 100644 --- a/arch/arm/boot/dts/ste-href.dtsi +++ b/arch/arm/boot/dts/ste-href.dtsi @@ -11,6 +11,7 @@ #include #include "ste-dbx5x0.dtsi" +#include "ste-href-family-pinctrl.dtsi" / { memory { @@ -30,14 +31,23 @@ soc { uart@80120000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart0_default_mode>; + pinctrl-1 = <&uart0_sleep_mode>; status = "okay"; }; uart@80121000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart1_default_mode>; + pinctrl-1 = <&uart1_sleep_mode>; status = "okay"; }; uart@80007000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart2_default_mode>; + pinctrl-1 = <&uart2_sleep_mode>; status = "okay"; }; diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts index f0b39f8..16d2886 100644 --- a/arch/arm/boot/dts/ste-snowball.dts +++ b/arch/arm/boot/dts/ste-snowball.dts @@ -11,6 +11,7 @@ /dts-v1/; #include "ste-dbx5x0.dtsi" +#include "ste-href-family-pinctrl.dtsi" / { model = "Calao Systems Snowball platform with device tree"; @@ -155,14 +156,23 @@ }; uart@80120000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart0_default_mode>; + pinctrl-1 = <&uart0_sleep_mode>; status = "okay"; }; uart@80121000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart1_default_mode>; + pinctrl-1 = <&uart1_sleep_mode>; status = "okay"; }; uart@80007000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart2_default_mode>; + pinctrl-1 = <&uart2_sleep_mode>; status = "okay"; }; diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c index 0efb156..c622519 100644 --- a/arch/arm/mach-ux500/board-mop500-pins.c +++ b/arch/arm/mach-ux500/board-mop500-pins.c @@ -65,16 +65,12 @@ BIAS(slpm_in_nopull_wkup_pdis, PIN_SLEEPMODE_ENABLED| PIN_SLPM_INPUT_NOPULL|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED); BIAS(slpm_in_pu_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|PIN_SLPM_INPUT_PULLUP| PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED); -BIAS(slpm_out_wkup_pdis, PIN_SLEEPMODE_ENABLED| - PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED); BIAS(out_lo_wkup_pdis, PIN_SLPM_OUTPUT_LOW| PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED); BIAS(in_wkup_pdis_en, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE| PIN_SLPM_PDIS_ENABLED); BIAS(in_wkup_pdis, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE| PIN_SLPM_PDIS_DISABLED); -BIAS(out_wkup_pdis, PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE| - PIN_SLPM_PDIS_DISABLED); /* We use these to define hog settings that are always done on boot */ #define DB8500_MUX_HOG(group,func) \ @@ -376,50 +372,10 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = { */ DB8500_PIN_HOG("GPIO218_AH11", gpio_in_pu), /* - * UART0, we do not mux in u0 here. - * uart-0 pins gpio configuration should be kept intact to prevent - * a glitch in tx line when the tty dev is opened. Later these pins - * are configured by uart driver - */ - DB8500_PIN_HOG("GPIO0_AJ5", in_pu), /* CTS */ - DB8500_PIN_HOG("GPIO1_AJ3", out_hi), /* RTS */ - DB8500_PIN_HOG("GPIO2_AH4", in_pu), /* RXD */ - DB8500_PIN_HOG("GPIO3_AH3", out_hi), /* TXD */ - /* - * Mux in UART2 on altfunction C and set pull-ups. - * TODO: is this used on U8500 variants and Snowball really? - * The setting on GPIO31 conflicts with magnetometer use on hrefv60 - */ - /* default state for UART2 */ - DB8500_MUX("u2rxtx_c_1", "u2", "uart2"), - DB8500_PIN("GPIO29_W2", in_pu, "uart2"), /* RXD */ - DB8500_PIN("GPIO30_W3", out_hi, "uart2"), /* TXD */ - /* Sleep state for UART2 */ - DB8500_PIN_SLEEP("GPIO29_W2", in_wkup_pdis, "uart2"), - DB8500_PIN_SLEEP("GPIO30_W3", out_wkup_pdis, "uart2"), - /* * The following pin sets were known as "runtime pins" before being * converted to the pinctrl model. Here we model them as "default" * states. */ - /* Mux in UART0 after initialization */ - DB8500_MUX("u0_a_1", "u0", "uart0"), - DB8500_PIN("GPIO0_AJ5", in_pu, "uart0"), /* CTS */ - DB8500_PIN("GPIO1_AJ3", out_hi, "uart0"), /* RTS */ - DB8500_PIN("GPIO2_AH4", in_pu, "uart0"), /* RXD */ - DB8500_PIN("GPIO3_AH3", out_hi, "uart0"), /* TXD */ - /* Sleep state for UART0 */ - DB8500_PIN_SLEEP("GPIO0_AJ5", slpm_in_wkup_pdis, "uart0"), - DB8500_PIN_SLEEP("GPIO1_AJ3", slpm_out_hi_wkup_pdis, "uart0"), - DB8500_PIN_SLEEP("GPIO2_AH4", slpm_in_wkup_pdis, "uart0"), - DB8500_PIN_SLEEP("GPIO3_AH3", slpm_out_wkup_pdis, "uart0"), - /* Mux in UART1 after initialization */ - DB8500_MUX("u1rxtx_a_1", "u1", "uart1"), - DB8500_PIN("GPIO4_AH6", in_pu, "uart1"), /* RXD */ - DB8500_PIN("GPIO5_AG6", out_hi, "uart1"), /* TXD */ - /* Sleep state for UART1 */ - DB8500_PIN_SLEEP("GPIO4_AH6", slpm_in_wkup_pdis, "uart1"), - DB8500_PIN_SLEEP("GPIO5_AG6", slpm_out_wkup_pdis, "uart1"), /* MSP1 for ALSA codec */ DB8500_MUX_HOG("msp1txrx_a_1", "msp1"), DB8500_MUX_HOG("msp1_a_1", "msp1"), @@ -822,10 +778,6 @@ static struct pinctrl_map __initdata mop500_pinmap[] = { DB8500_PIN_HOG("GPIO7_AG5", in_pu), /* TC35892 IRQ, pull up the line, let the driver mux in the pin */ DB8500_PIN_HOG("GPIO217_AH12", gpio_in_pu), - /* Mux in UART1 and set the pull-ups */ - DB8500_MUX_HOG("u1rxtx_a_1", "u1"), - DB8500_PIN_HOG("GPIO4_AH6", in_pu), /* RXD */ - DB8500_PIN_HOG("GPIO5_AG6", out_hi), /* TXD */ /* * Runtime stuff: make it possible to mux in the SKE keypad * and bias the pins @@ -971,10 +923,6 @@ static struct pinctrl_map __initdata hrefv60_pinmap[] = { }; static struct pinctrl_map __initdata u9500_pinmap[] = { - /* Mux in UART1 (just RX/TX) and set the pull-ups */ - DB8500_MUX_HOG("u1rxtx_a_1", "u1"), - DB8500_PIN_HOG("GPIO4_AH6", in_pu), - DB8500_PIN_HOG("GPIO5_AG6", out_hi), /* WLAN_IRQ line */ DB8500_PIN_HOG("GPIO144_B13", gpio_in_pu), /* HSI */ -- cgit v1.1 From 96fee13f0f11a7479a06e4c44aaa89ee77b9fafb Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 13 Nov 2013 11:10:07 +0100 Subject: ARM: ux500: move I2C pin control to the device tree This moves the static, device-tied pin control configuration out of the board file board-mop500-pins.c and into the device tree. Define possible states also for I2C4 even if it's not used by any board file at this time. Cc: Lee Jones Cc: Patrice Chotard Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-href-family-pinctrl.dtsi | 105 +++++++++++++++++++++++++ arch/arm/boot/dts/ste-href.dtsi | 21 +++++ arch/arm/boot/dts/ste-snowball.dts | 24 ++++++ arch/arm/mach-ux500/board-mop500-pins.c | 22 ------ 4 files changed, 150 insertions(+), 22 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi index d979de2..d2e63f3 100644 --- a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi +++ b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi @@ -109,6 +109,111 @@ }; }; }; + + /* Settings for all I2C default and sleep states */ + i2c0 { + i2c0_default_mode: i2c_default { + default_mux { + ste,function = "i2c0"; + ste,pins = "i2c0_a_1"; + }; + default_cfg1 { + ste,pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */ + ste,config = <&in_pu>; + }; + }; + + i2c0_sleep_mode: i2c_sleep { + sleep_cfg1 { + ste,pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */ + ste,config = <&slpm_in_wkup_pdis>; + }; + }; + }; + + i2c1 { + i2c1_default_mode: i2c_default { + default_mux { + ste,function = "i2c1"; + ste,pins = "i2c1_b_2"; + }; + default_cfg1 { + ste,pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */ + ste,config = <&in_pu>; + }; + }; + + i2c1_sleep_mode: i2c_sleep { + sleep_cfg1 { + ste,pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */ + ste,config = <&slpm_in_wkup_pdis>; + }; + }; + }; + + i2c2 { + i2c2_default_mode: i2c_default { + default_mux { + ste,function = "i2c2"; + ste,pins = "i2c2_b_2"; + }; + default_cfg1 { + ste,pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */ + ste,config = <&in_pu>; + }; + }; + + i2c2_sleep_mode: i2c_sleep { + sleep_cfg1 { + ste,pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */ + ste,config = <&slpm_in_wkup_pdis>; + }; + }; + }; + + i2c3 { + i2c3_default_mode: i2c_default { + default_mux { + ste,function = "i2c3"; + ste,pins = "i2c3_c_2"; + }; + default_cfg1 { + ste,pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */ + ste,config = <&in_pu>; + }; + }; + + i2c3_sleep_mode: i2c_sleep { + sleep_cfg1 { + ste,pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */ + ste,config = <&slpm_in_wkup_pdis>; + }; + }; + }; + + /* + * Activating I2C4 will conflict with UART1 about the same pins so do not + * enable I2C4 and UART1 at the same time. + */ + i2c4 { + i2c4_default_mode: i2c_default { + default_mux { + ste,function = "i2c4"; + ste,pins = "i2c4_b_1"; + }; + default_cfg1 { + ste,pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */ + ste,config = <&in_pu>; + }; + }; + + i2c4_sleep_mode: i2c_sleep { + sleep_cfg1 { + ste,pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */ + ste,config = <&slpm_in_wkup_pdis>; + }; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi index 914a5f4..1863241 100644 --- a/arch/arm/boot/dts/ste-href.dtsi +++ b/arch/arm/boot/dts/ste-href.dtsi @@ -51,7 +51,22 @@ status = "okay"; }; + i2c@80004000 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&i2c0_default_mode>; + pinctrl-1 = <&i2c0_sleep_mode>; + }; + + i2c@80122000 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&i2c1_default_mode>; + pinctrl-1 = <&i2c1_sleep_mode>; + }; + i2c@80128000 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&i2c2_default_mode>; + pinctrl-1 = <&i2c2_sleep_mode>; lp5521@33 { compatible = "national,lp5521"; reg = <0x33>; @@ -95,6 +110,12 @@ }; }; + i2c@80110000 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&i2c3_default_mode>; + pinctrl-1 = <&i2c3_sleep_mode>; + }; + // External Micro SD slot sdi0_per1@80126000 { arm,primecell-periphid = <0x10480180>; diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts index 16d2886..f8df43e 100644 --- a/arch/arm/boot/dts/ste-snowball.dts +++ b/arch/arm/boot/dts/ste-snowball.dts @@ -176,6 +176,30 @@ status = "okay"; }; + i2c@80004000 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&i2c0_default_mode>; + pinctrl-1 = <&i2c0_sleep_mode>; + }; + + i2c@80122000 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&i2c1_default_mode>; + pinctrl-1 = <&i2c1_sleep_mode>; + }; + + i2c@80128000 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&i2c2_default_mode>; + pinctrl-1 = <&i2c2_sleep_mode>; + }; + + i2c@80110000 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&i2c3_default_mode>; + pinctrl-1 = <&i2c3_sleep_mode>; + }; + cpufreq-cooling { status = "okay"; }; diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c index c622519..1f1e539 100644 --- a/arch/arm/mach-ux500/board-mop500-pins.c +++ b/arch/arm/mach-ux500/board-mop500-pins.c @@ -61,8 +61,6 @@ BIAS(slpm_out_lo_wkup_pdis, PIN_SLEEPMODE_ENABLED| PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED); BIAS(slpm_out_hi_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_OUTPUT_HIGH| PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED); -BIAS(slpm_in_nopull_wkup_pdis, PIN_SLEEPMODE_ENABLED| - PIN_SLPM_INPUT_NOPULL|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED); BIAS(slpm_in_pu_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|PIN_SLPM_INPUT_PULLUP| PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED); BIAS(out_lo_wkup_pdis, PIN_SLPM_OUTPUT_LOW| @@ -391,26 +389,6 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = { DB8500_PIN("GPIO69_E2", in_pu, "0-0070"), /* LCD VSI1 sleep state */ DB8500_PIN_SLEEP("GPIO69_E2", slpm_in_wkup_pdis, "0-0070"), - /* Mux in i2c0 block, default state */ - DB8500_MUX("i2c0_a_1", "i2c0", "nmk-i2c.0"), - /* i2c0 sleep state */ - DB8500_PIN_SLEEP("GPIO147_C15", slpm_in_nopull_wkup_pdis, "nmk-i2c.0"), /* SDA */ - DB8500_PIN_SLEEP("GPIO148_B16", slpm_in_nopull_wkup_pdis, "nmk-i2c.0"), /* SCL */ - /* Mux in i2c1 block, default state */ - DB8500_MUX("i2c1_b_2", "i2c1", "nmk-i2c.1"), - /* i2c1 sleep state */ - DB8500_PIN_SLEEP("GPIO16_AD3", slpm_in_nopull_wkup_pdis, "nmk-i2c.1"), /* SDA */ - DB8500_PIN_SLEEP("GPIO17_AD4", slpm_in_nopull_wkup_pdis, "nmk-i2c.1"), /* SCL */ - /* Mux in i2c2 block, default state */ - DB8500_MUX("i2c2_b_2", "i2c2", "nmk-i2c.2"), - /* i2c2 sleep state */ - DB8500_PIN_SLEEP("GPIO10_AF5", slpm_in_nopull_wkup_pdis, "nmk-i2c.2"), /* SDA */ - DB8500_PIN_SLEEP("GPIO11_AG4", slpm_in_nopull_wkup_pdis, "nmk-i2c.2"), /* SCL */ - /* Mux in i2c3 block, default state */ - DB8500_MUX("i2c3_c_2", "i2c3", "nmk-i2c.3"), - /* i2c3 sleep state */ - DB8500_PIN_SLEEP("GPIO229_AG7", slpm_in_nopull_wkup_pdis, "nmk-i2c.3"), /* SDA */ - DB8500_PIN_SLEEP("GPIO230_AF7", slpm_in_nopull_wkup_pdis, "nmk-i2c.3"), /* SCL */ /* Mux in SDI0 (here called MC0) used for removable MMC/SD/SDIO cards */ DB8500_MUX("mc0_a_1", "mc0", "sdi0"), DB8500_PIN("GPIO18_AC2", out_hi, "sdi0"), /* CMDDIR */ -- cgit v1.1 From 1e66235330ff1bdc372647f47a414a3d3952dffb Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 13 Nov 2013 13:46:57 +0100 Subject: ARM: ux500: move MMC/SD/SDIO pin control to the device tree This moves the static, device-tied pin control configuration out of the board file board-mop500-pins.c and into the device tree. Add entries for SDI1 and SDI2 on the Snowball so that the WLAN pins on SDI1 can be used further on, and the unused pins on SDI2 can be put to sleep. Cc: Lee Jones Cc: Patrice Chotard Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-href-family-pinctrl.dtsi | 211 +++++++++++++++++++++++++ arch/arm/boot/dts/ste-href.dtsi | 12 ++ arch/arm/boot/dts/ste-hrefprev60.dtsi | 17 ++ arch/arm/boot/dts/ste-hrefv60plus.dtsi | 12 ++ arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi | 19 +++ arch/arm/boot/dts/ste-snowball.dts | 43 +++++ arch/arm/mach-ux500/board-mop500-pins.c | 107 ------------- 7 files changed, 314 insertions(+), 107 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi index d2e63f3..23583b0 100644 --- a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi +++ b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi @@ -214,6 +214,217 @@ }; }; }; + + /* Settings for all MMC/SD/SDIO default and sleep states */ + sdi0 { + /* This is the external SD card slot, 4 bits wide */ + sdi0_default_mode: sdi0_default { + default_mux { + ste,function = "mc0"; + ste,pins = "mc0_a_1"; + }; + default_cfg1 { + ste,pins = + "GPIO18_AC2", /* CMDDIR */ + "GPIO19_AC1", /* DAT0DIR */ + "GPIO20_AB4"; /* DAT2DIR */ + ste,config = <&out_hi>; + }; + default_cfg2 { + ste,pins = "GPIO22_AA3"; /* FBCLK */ + ste,config = <&in_nopull>; + }; + default_cfg3 { + ste,pins = "GPIO23_AA4"; /* CLK */ + ste,config = <&out_lo>; + }; + default_cfg4 { + ste,pins = + "GPIO24_AB2", /* CMD */ + "GPIO25_Y4", /* DAT0 */ + "GPIO26_Y2", /* DAT1 */ + "GPIO27_AA2", /* DAT2 */ + "GPIO28_AA1"; /* DAT3 */ + ste,config = <&in_pu>; + }; + }; + + sdi0_sleep_mode: sdi0_sleep { + sleep_cfg1 { + ste,pins = + "GPIO18_AC2", /* CMDDIR */ + "GPIO19_AC1", /* DAT0DIR */ + "GPIO20_AB4"; /* DAT2DIR */ + ste,config = <&slpm_out_hi_wkup_pdis>; + }; + sleep_cfg2 { + ste,pins = + "GPIO22_AA3", /* FBCLK */ + "GPIO24_AB2", /* CMD */ + "GPIO25_Y4", /* DAT0 */ + "GPIO26_Y2", /* DAT1 */ + "GPIO27_AA2", /* DAT2 */ + "GPIO28_AA1"; /* DAT3 */ + ste,config = <&slpm_in_wkup_pdis>; + }; + sleep_cfg3 { + ste,pins = "GPIO23_AA4"; /* CLK */ + ste,config = <&slpm_out_lo_wkup_pdis>; + }; + }; + }; + + sdi1 { + /* This is the WLAN SDIO 4 bits wide */ + sdi1_default_mode: sdi1_default { + default_mux { + ste,function = "mc1"; + ste,pins = "mc1_a_1"; + }; + default_cfg1 { + ste,pins = "GPIO208_AH16"; /* CLK */ + ste,config = <&out_lo>; + }; + default_cfg2 { + ste,pins = "GPIO209_AG15"; /* FBCLK */ + ste,config = <&in_nopull>; + }; + default_cfg3 { + ste,pins = + "GPIO210_AJ15", /* CMD */ + "GPIO211_AG14", /* DAT0 */ + "GPIO212_AF13", /* DAT1 */ + "GPIO213_AG13", /* DAT2 */ + "GPIO214_AH15"; /* DAT3 */ + ste,config = <&in_pu>; + }; + }; + + sdi1_sleep_mode: sdi1_sleep { + sleep_cfg1 { + ste,pins = "GPIO208_AH16"; /* CLK */ + ste,config = <&slpm_out_lo_wkup_pdis>; + }; + sleep_cfg2 { + ste,pins = + "GPIO209_AG15", /* FBCLK */ + "GPIO210_AJ15", /* CMD */ + "GPIO211_AG14", /* DAT0 */ + "GPIO212_AF13", /* DAT1 */ + "GPIO213_AG13", /* DAT2 */ + "GPIO214_AH15"; /* DAT3 */ + ste,config = <&slpm_in_wkup_pdis>; + }; + }; + }; + + sdi2 { + /* This is the eMMC 8 bits wide, usually PoP eMMC */ + sdi2_default_mode: sdi2_default { + default_mux { + ste,function = "mc2"; + ste,pins = "mc2_a_1"; + }; + default_cfg1 { + ste,pins = "GPIO128_A5"; /* CLK */ + ste,config = <&out_lo>; + }; + default_cfg2 { + ste,pins = "GPIO130_C8"; /* FBCLK */ + ste,config = <&in_nopull>; + }; + default_cfg3 { + ste,pins = + "GPIO129_B4", /* CMD */ + "GPIO131_A12", /* DAT0 */ + "GPIO132_C10", /* DAT1 */ + "GPIO133_B10", /* DAT2 */ + "GPIO134_B9", /* DAT3 */ + "GPIO135_A9", /* DAT4 */ + "GPIO136_C7", /* DAT5 */ + "GPIO137_A7", /* DAT6 */ + "GPIO138_C5"; /* DAT7 */ + ste,config = <&in_pu>; + }; + }; + + sdi2_sleep_mode: sdi2_sleep { + sleep_cfg1 { + ste,pins = "GPIO128_A5"; /* CLK */ + ste,config = <&out_lo_wkup_pdis>; + }; + sleep_cfg2 { + ste,pins = + "GPIO130_C8", /* FBCLK */ + "GPIO129_B4"; /* CMD */ + ste,config = <&in_wkup_pdis_en>; + }; + sleep_cfg3 { + ste,pins = + "GPIO131_A12", /* DAT0 */ + "GPIO132_C10", /* DAT1 */ + "GPIO133_B10", /* DAT2 */ + "GPIO134_B9", /* DAT3 */ + "GPIO135_A9", /* DAT4 */ + "GPIO136_C7", /* DAT5 */ + "GPIO137_A7", /* DAT6 */ + "GPIO138_C5"; /* DAT7 */ + ste,config = <&in_wkup_pdis>; + }; + }; + }; + + sdi4 { + /* This is the eMMC 8 bits wide, usually PCB-mounted eMMC */ + sdi4_default_mode: sdi4_default { + default_mux { + ste,function = "mc4"; + ste,pins = "mc4_a_1"; + }; + default_cfg1 { + ste,pins = "GPIO203_AE23"; /* CLK */ + ste,config = <&out_lo>; + }; + default_cfg2 { + ste,pins = "GPIO202_AF25"; /* FBCLK */ + ste,config = <&in_nopull>; + }; + default_cfg3 { + ste,pins = + "GPIO201_AF24", /* CMD */ + "GPIO200_AH26", /* DAT0 */ + "GPIO199_AH23", /* DAT1 */ + "GPIO198_AG25", /* DAT2 */ + "GPIO197_AH24", /* DAT3 */ + "GPIO207_AJ23", /* DAT4 */ + "GPIO206_AG24", /* DAT5 */ + "GPIO205_AG23", /* DAT6 */ + "GPIO204_AF23"; /* DAT7 */ + ste,config = <&in_pu>; + }; + }; + + sdi4_sleep_mode: sdi4_sleep { + sleep_cfg1 { + ste,pins = "GPIO203_AE23"; /* CLK */ + ste,config = <&out_lo_wkup_pdis>; + }; + sleep_cfg2 { + ste,pins = + "GPIO202_AF25", /* FBCLK */ + "GPIO201_AF24", /* CMD */ + "GPIO200_AH26", /* DAT0 */ + "GPIO199_AH23", /* DAT1 */ + "GPIO198_AG25", /* DAT2 */ + "GPIO197_AH24", /* DAT3 */ + "GPIO207_AJ23", /* DAT4 */ + "GPIO206_AG24", /* DAT5 */ + "GPIO205_AG23", /* DAT6 */ + "GPIO204_AF23"; /* DAT7 */ + ste,config = <&slpm_in_wkup_pdis>; + }; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi index 1863241..845eb25 100644 --- a/arch/arm/boot/dts/ste-href.dtsi +++ b/arch/arm/boot/dts/ste-href.dtsi @@ -125,6 +125,9 @@ mmc-cap-mmc-highspeed; vmmc-supply = <&ab8500_ldo_aux3_reg>; vqmmc-supply = <&vmmci>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdi0_default_mode>; + pinctrl-1 = <&sdi0_sleep_mode>; cd-gpios = <&tc3589x_gpio 3 0x4>; @@ -136,6 +139,9 @@ arm,primecell-periphid = <0x10480180>; max-frequency = <100000000>; bus-width = <4>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdi1_default_mode>; + pinctrl-1 = <&sdi1_sleep_mode>; status = "okay"; }; @@ -146,6 +152,9 @@ max-frequency = <100000000>; bus-width = <8>; mmc-cap-mmc-highspeed; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdi2_default_mode>; + pinctrl-1 = <&sdi2_sleep_mode>; status = "okay"; }; @@ -157,6 +166,9 @@ bus-width = <8>; mmc-cap-mmc-highspeed; vmmc-supply = <&ab8500_ldo_aux2_reg>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdi4_default_mode>; + pinctrl-1 = <&sdi4_sleep_mode>; status = "okay"; }; diff --git a/arch/arm/boot/dts/ste-hrefprev60.dtsi b/arch/arm/boot/dts/ste-hrefprev60.dtsi index 6b271a4..cfd7ef3 100644 --- a/arch/arm/boot/dts/ste-hrefprev60.dtsi +++ b/arch/arm/boot/dts/ste-hrefprev60.dtsi @@ -55,5 +55,22 @@ status = "okay"; }; + + pinctrl { + sdi0 { + /* This additional pin needed on early MOP500 and HREFs previous to v60 */ + sdi0_default_mode: sdi0_default { + hrefprev60_mux { + ste,function = "mc0"; + ste,pins = "mc0dat31dir_a_1"; + }; + hrefprev60_cfg1 { + ste,pins = "GPIO21_AB3"; /* DAT31DIR */ + ste,config = <&out_hi>; + }; + + }; + }; + }; }; }; diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dtsi b/arch/arm/boot/dts/ste-hrefv60plus.dtsi index aed511b..452f00c 100644 --- a/arch/arm/boot/dts/ste-hrefv60plus.dtsi +++ b/arch/arm/boot/dts/ste-hrefv60plus.dtsi @@ -66,5 +66,17 @@ status = "okay"; }; + + pinctrl { + sdi0 { + /* SD card detect GPIO pin, extend default state */ + sdi0_default_mode: sdi0_default { + default_hrefv60_cfg1 { + ste,pins = "GPIO95_E8"; + ste,config = <&gpio_in_pu>; + }; + }; + }; + }; }; }; diff --git a/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi b/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi index efddee9..f213222 100644 --- a/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi +++ b/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi @@ -68,6 +68,13 @@ ste,sleep-pull-disable = ; }; + slpm_out_lo_wkup_pdis: slpm_out_lo_wkup_pdis { + ste,sleep = ; + ste,sleep-output = ; + ste,sleep-wakeup = ; + ste,sleep-pull-disable = ; + }; + slpm_out_wkup_pdis: slpm_out_wkup_pdis { ste,sleep = ; ste,sleep-output = ; @@ -81,6 +88,18 @@ ste,sleep-pull-disable = ; }; + in_wkup_pdis_en: in_wkup_pdis_en { + ste,sleep-input = ; + ste,sleep-wakeup = ; + ste,sleep-pull-disable = ; + }; + + out_lo_wkup_pdis: out_lo_wkup_pdis { + ste,sleep-output = ; + ste,sleep-wakeup = ; + ste,sleep-pull-disable = ; + }; + out_hi_wkup_pdis: out_hi_wkup_pdis { ste,sleep-output = ; ste,sleep-wakeup = ; diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts index f8df43e..c2cb3ea 100644 --- a/arch/arm/boot/dts/ste-snowball.dts +++ b/arch/arm/boot/dts/ste-snowball.dts @@ -137,6 +137,9 @@ mmc-cap-mmc-highspeed; vmmc-supply = <&ab8500_ldo_aux3_reg>; vqmmc-supply = <&vmmci>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdi0_default_mode>; + pinctrl-1 = <&sdi0_sleep_mode>; cd-gpios = <&gpio6 26 0x4>; // 218 cd-inverted; @@ -144,6 +147,27 @@ status = "okay"; }; + // WLAN SDIO channel + sdi1_per2@80118000 { + arm,primecell-periphid = <0x10480180>; + max-frequency = <100000000>; + bus-width = <4>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdi1_default_mode>; + pinctrl-1 = <&sdi1_sleep_mode>; + + status = "okay"; + }; + + // Unused PoP eMMC - register and put it to sleep by default */ + sdi2_per3@80005000 { + arm,primecell-periphid = <0x10480180>; + pinctrl-names = "default"; + pinctrl-0 = <&sdi2_sleep_mode>; + + status = "okay"; + }; + // On-board eMMC sdi4_per2@80114000 { arm,primecell-periphid = <0x10480180>; @@ -151,6 +175,9 @@ bus-width = <8>; mmc-cap-mmc-highspeed; vmmc-supply = <&ab8500_ldo_aux2_reg>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdi4_default_mode>; + pinctrl-1 = <&sdi4_sleep_mode>; status = "okay"; }; @@ -300,5 +327,21 @@ }; }; }; + + pinctrl { + sdi0 { + sdi0_default_mode: sdi0_default { + snowball_mux { + ste,function = "mc0"; + ste,pins = "mc0dat31dir_a_1"; + }; + snowball_cfg1 { + ste,pins = "GPIO21_AB3"; /* DAT31DIR */ + ste,config = <&out_hi>; + }; + + }; + }; + }; }; }; diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c index 1f1e539..0f9a077 100644 --- a/arch/arm/mach-ux500/board-mop500-pins.c +++ b/arch/arm/mach-ux500/board-mop500-pins.c @@ -63,12 +63,6 @@ BIAS(slpm_out_hi_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_OUTPUT_HIGH| PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED); BIAS(slpm_in_pu_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|PIN_SLPM_INPUT_PULLUP| PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED); -BIAS(out_lo_wkup_pdis, PIN_SLPM_OUTPUT_LOW| - PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED); -BIAS(in_wkup_pdis_en, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE| - PIN_SLPM_PDIS_ENABLED); -BIAS(in_wkup_pdis, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE| - PIN_SLPM_PDIS_DISABLED); /* We use these to define hog settings that are always done on boot */ #define DB8500_MUX_HOG(group,func) \ @@ -389,99 +383,6 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = { DB8500_PIN("GPIO69_E2", in_pu, "0-0070"), /* LCD VSI1 sleep state */ DB8500_PIN_SLEEP("GPIO69_E2", slpm_in_wkup_pdis, "0-0070"), - /* Mux in SDI0 (here called MC0) used for removable MMC/SD/SDIO cards */ - DB8500_MUX("mc0_a_1", "mc0", "sdi0"), - DB8500_PIN("GPIO18_AC2", out_hi, "sdi0"), /* CMDDIR */ - DB8500_PIN("GPIO19_AC1", out_hi, "sdi0"), /* DAT0DIR */ - DB8500_PIN("GPIO20_AB4", out_hi, "sdi0"), /* DAT2DIR */ - DB8500_PIN("GPIO22_AA3", in_nopull, "sdi0"), /* FBCLK */ - DB8500_PIN("GPIO23_AA4", out_lo, "sdi0"), /* CLK */ - DB8500_PIN("GPIO24_AB2", in_pu, "sdi0"), /* CMD */ - DB8500_PIN("GPIO25_Y4", in_pu, "sdi0"), /* DAT0 */ - DB8500_PIN("GPIO26_Y2", in_pu, "sdi0"), /* DAT1 */ - DB8500_PIN("GPIO27_AA2", in_pu, "sdi0"), /* DAT2 */ - DB8500_PIN("GPIO28_AA1", in_pu, "sdi0"), /* DAT3 */ - /* SDI0 sleep state */ - DB8500_PIN_SLEEP("GPIO18_AC2", slpm_out_hi_wkup_pdis, "sdi0"), - DB8500_PIN_SLEEP("GPIO19_AC1", slpm_out_hi_wkup_pdis, "sdi0"), - DB8500_PIN_SLEEP("GPIO20_AB4", slpm_out_hi_wkup_pdis, "sdi0"), - DB8500_PIN_SLEEP("GPIO22_AA3", slpm_in_wkup_pdis, "sdi0"), - DB8500_PIN_SLEEP("GPIO23_AA4", slpm_out_lo_wkup_pdis, "sdi0"), - DB8500_PIN_SLEEP("GPIO24_AB2", slpm_in_wkup_pdis, "sdi0"), - DB8500_PIN_SLEEP("GPIO25_Y4", slpm_in_wkup_pdis, "sdi0"), - DB8500_PIN_SLEEP("GPIO26_Y2", slpm_in_wkup_pdis, "sdi0"), - DB8500_PIN_SLEEP("GPIO27_AA2", slpm_in_wkup_pdis, "sdi0"), - DB8500_PIN_SLEEP("GPIO28_AA1", slpm_in_wkup_pdis, "sdi0"), - - /* Mux in SDI1 (here called MC1) used for SDIO for CW1200 WLAN */ - DB8500_MUX("mc1_a_1", "mc1", "sdi1"), - DB8500_PIN("GPIO208_AH16", out_lo, "sdi1"), /* CLK */ - DB8500_PIN("GPIO209_AG15", in_nopull, "sdi1"), /* FBCLK */ - DB8500_PIN("GPIO210_AJ15", in_pu, "sdi1"), /* CMD */ - DB8500_PIN("GPIO211_AG14", in_pu, "sdi1"), /* DAT0 */ - DB8500_PIN("GPIO212_AF13", in_pu, "sdi1"), /* DAT1 */ - DB8500_PIN("GPIO213_AG13", in_pu, "sdi1"), /* DAT2 */ - DB8500_PIN("GPIO214_AH15", in_pu, "sdi1"), /* DAT3 */ - /* SDI1 sleep state */ - DB8500_PIN_SLEEP("GPIO208_AH16", slpm_out_lo_wkup_pdis, "sdi1"), /* CLK */ - DB8500_PIN_SLEEP("GPIO209_AG15", slpm_in_wkup_pdis, "sdi1"), /* FBCLK */ - DB8500_PIN_SLEEP("GPIO210_AJ15", slpm_in_wkup_pdis, "sdi1"), /* CMD */ - DB8500_PIN_SLEEP("GPIO211_AG14", slpm_in_wkup_pdis, "sdi1"), /* DAT0 */ - DB8500_PIN_SLEEP("GPIO212_AF13", slpm_in_wkup_pdis, "sdi1"), /* DAT1 */ - DB8500_PIN_SLEEP("GPIO213_AG13", slpm_in_wkup_pdis, "sdi1"), /* DAT2 */ - DB8500_PIN_SLEEP("GPIO214_AH15", slpm_in_wkup_pdis, "sdi1"), /* DAT3 */ - - /* Mux in SDI2 (here called MC2) used for for PoP eMMC */ - DB8500_MUX("mc2_a_1", "mc2", "sdi2"), - DB8500_PIN("GPIO128_A5", out_lo, "sdi2"), /* CLK */ - DB8500_PIN("GPIO129_B4", in_pu, "sdi2"), /* CMD */ - DB8500_PIN("GPIO130_C8", in_nopull, "sdi2"), /* FBCLK */ - DB8500_PIN("GPIO131_A12", in_pu, "sdi2"), /* DAT0 */ - DB8500_PIN("GPIO132_C10", in_pu, "sdi2"), /* DAT1 */ - DB8500_PIN("GPIO133_B10", in_pu, "sdi2"), /* DAT2 */ - DB8500_PIN("GPIO134_B9", in_pu, "sdi2"), /* DAT3 */ - DB8500_PIN("GPIO135_A9", in_pu, "sdi2"), /* DAT4 */ - DB8500_PIN("GPIO136_C7", in_pu, "sdi2"), /* DAT5 */ - DB8500_PIN("GPIO137_A7", in_pu, "sdi2"), /* DAT6 */ - DB8500_PIN("GPIO138_C5", in_pu, "sdi2"), /* DAT7 */ - /* SDI2 sleep state */ - DB8500_PIN_SLEEP("GPIO128_A5", out_lo_wkup_pdis, "sdi2"), /* CLK */ - DB8500_PIN_SLEEP("GPIO129_B4", in_wkup_pdis_en, "sdi2"), /* CMD */ - DB8500_PIN_SLEEP("GPIO130_C8", in_wkup_pdis_en, "sdi2"), /* FBCLK */ - DB8500_PIN_SLEEP("GPIO131_A12", in_wkup_pdis, "sdi2"), /* DAT0 */ - DB8500_PIN_SLEEP("GPIO132_C10", in_wkup_pdis, "sdi2"), /* DAT1 */ - DB8500_PIN_SLEEP("GPIO133_B10", in_wkup_pdis, "sdi2"), /* DAT2 */ - DB8500_PIN_SLEEP("GPIO134_B9", in_wkup_pdis, "sdi2"), /* DAT3 */ - DB8500_PIN_SLEEP("GPIO135_A9", in_wkup_pdis, "sdi2"), /* DAT4 */ - DB8500_PIN_SLEEP("GPIO136_C7", in_wkup_pdis, "sdi2"), /* DAT5 */ - DB8500_PIN_SLEEP("GPIO137_A7", in_wkup_pdis, "sdi2"), /* DAT6 */ - DB8500_PIN_SLEEP("GPIO138_C5", in_wkup_pdis, "sdi2"), /* DAT7 */ - - /* Mux in SDI4 (here called MC4) used for for PCB-mounted eMMC */ - DB8500_MUX("mc4_a_1", "mc4", "sdi4"), - DB8500_PIN("GPIO197_AH24", in_pu, "sdi4"), /* DAT3 */ - DB8500_PIN("GPIO198_AG25", in_pu, "sdi4"), /* DAT2 */ - DB8500_PIN("GPIO199_AH23", in_pu, "sdi4"), /* DAT1 */ - DB8500_PIN("GPIO200_AH26", in_pu, "sdi4"), /* DAT0 */ - DB8500_PIN("GPIO201_AF24", in_pu, "sdi4"), /* CMD */ - DB8500_PIN("GPIO202_AF25", in_nopull, "sdi4"), /* FBCLK */ - DB8500_PIN("GPIO203_AE23", out_lo, "sdi4"), /* CLK */ - DB8500_PIN("GPIO204_AF23", in_pu, "sdi4"), /* DAT7 */ - DB8500_PIN("GPIO205_AG23", in_pu, "sdi4"), /* DAT6 */ - DB8500_PIN("GPIO206_AG24", in_pu, "sdi4"), /* DAT5 */ - DB8500_PIN("GPIO207_AJ23", in_pu, "sdi4"), /* DAT4 */ - /*SDI4 sleep state */ - DB8500_PIN_SLEEP("GPIO197_AH24", slpm_in_wkup_pdis, "sdi4"), /* DAT3 */ - DB8500_PIN_SLEEP("GPIO198_AG25", slpm_in_wkup_pdis, "sdi4"), /* DAT2 */ - DB8500_PIN_SLEEP("GPIO199_AH23", slpm_in_wkup_pdis, "sdi4"), /* DAT1 */ - DB8500_PIN_SLEEP("GPIO200_AH26", slpm_in_wkup_pdis, "sdi4"), /* DAT0 */ - DB8500_PIN_SLEEP("GPIO201_AF24", slpm_in_wkup_pdis, "sdi4"), /* CMD */ - DB8500_PIN_SLEEP("GPIO202_AF25", slpm_in_wkup_pdis, "sdi4"), /* FBCLK */ - DB8500_PIN_SLEEP("GPIO203_AE23", slpm_out_lo_wkup_pdis, "sdi4"), /* CLK */ - DB8500_PIN_SLEEP("GPIO204_AF23", slpm_in_wkup_pdis, "sdi4"), /* DAT7 */ - DB8500_PIN_SLEEP("GPIO205_AG23", slpm_in_wkup_pdis, "sdi4"), /* DAT6 */ - DB8500_PIN_SLEEP("GPIO206_AG24", slpm_in_wkup_pdis, "sdi4"), /* DAT5 */ - DB8500_PIN_SLEEP("GPIO207_AJ23", slpm_in_wkup_pdis, "sdi4"), /* DAT4 */ /* Mux in USB pins, drive STP high */ /* USB default state */ @@ -795,10 +696,6 @@ static struct pinctrl_map __initdata mop500_pinmap[] = { DB8500_PIN_SLEEP("GPIO166_A22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O2 */ DB8500_PIN_SLEEP("GPIO167_B24", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O1 */ DB8500_PIN_SLEEP("GPIO168_C22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O0 */ - - /* Mux in and drive the SDI0 DAT31DIR line high at runtime */ - DB8500_MUX("mc0dat31dir_a_1", "mc0", "sdi0"), - DB8500_PIN("GPIO21_AB3", out_hi, "sdi0"), }; /* @@ -888,8 +785,6 @@ static struct pinctrl_map __initdata hrefv60_pinmap[] = { /* Accelerometer interrupt lines */ DB8500_PIN_HOG("GPIO82_C1", gpio_in_pu), /* ACC_INT1 */ DB8500_PIN_HOG("GPIO83_D3", gpio_in_pu), /* ACC_INT2 */ - /* SD card detect GPIO pin */ - DB8500_PIN_HOG("GPIO95_E8", gpio_in_pu), /* * Runtime stuff * Pull up/down of some sensor GPIO pins, for proximity, HAL sensor @@ -925,8 +820,6 @@ static struct pinctrl_map __initdata snowball_pinmap[] = { /* Mux in SSP0 connected to AB8500, pull down RXD pin */ DB8500_MUX_HOG("ssp0_a_1", "ssp0"), DB8500_PIN_HOG("GPIO145_C13", pd), - /* Always drive the MC0 DAT31DIR line high on these boards */ - DB8500_PIN_HOG("GPIO21_AB3", out_hi), /* Mux in "SM" which is used for the SMSC911x Ethernet adapter */ DB8500_MUX_HOG("sm_b_1", "sm"), /* User LED */ -- cgit v1.1 From 70b41abc151f9cd06cfb2f7f6cd726753db99484 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 13 Nov 2013 14:45:06 +0100 Subject: ARM: ux500: move MSP pin control to the device tree This moves the static, device-tied pin control configuration out of the board file board-mop500-pins.c and into the device tree. Add nodes for MSP0 and MSP2 on the HREF and Snowball so we can reference the pins properly. Cc: Lee Jones Cc: Patrice Chotard Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-href-family-pinctrl.dtsi | 63 ++++++++++++++++++++++++++ arch/arm/boot/dts/ste-href.dtsi | 14 ++++++ arch/arm/boot/dts/ste-snowball.dts | 14 ++++++ arch/arm/mach-ux500/board-mop500-pins.c | 30 ------------ 4 files changed, 91 insertions(+), 30 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi index 23583b0..7408d3a 100644 --- a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi +++ b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi @@ -425,6 +425,69 @@ }; }; }; + + /* + * Multi-rate serial ports (MSPs) - MSP3 output is internal and + * cannot be muxed onto any pins. + */ + msp0 { + msp0_default_mode: msp0_default { + default_msp0_mux { + ste,function = "msp0"; + ste,pins = "msp0txrx_a_1", "msp0tfstck_a_1"; + }; + default_msp0_cfg { + ste,pins = + "GPIO12_AC4", /* TXD */ + "GPIO15_AC3", /* RXD */ + "GPIO13_AF3", /* TFS */ + "GPIO14_AE3"; /* TCK */ + ste,config = <&in_nopull>; + }; + }; + }; + + msp1 { + msp1_default_mode: msp1_default { + default_mux { + ste,function = "msp1"; + ste,pins = "msp1txrx_a_1", "msp1_a_1"; + }; + default_cfg1 { + ste,pins = "GPIO33_AF2"; + ste,config = <&out_lo>; + }; + default_cfg2 { + ste,pins = + "GPIO34_AE1", + "GPIO35_AE2", + "GPIO36_AG2"; + ste,config = <&in_nopull>; + }; + + }; + }; + + msp2 { + msp2_default_mode: msp2_default { + /* MSP2 usually used for HDMI audio */ + default_mux { + ste,function = "msp2"; + ste,pins = "msp2_a_1"; + }; + default_cfg1 { + ste,pins = + "GPIO193_AH27", /* TXD */ + "GPIO194_AF27", /* TCK */ + "GPIO195_AG28"; /* TFS */ + ste,config = <&in_pd>; + }; + default_cfg2 { + ste,pins = "GPIO196_AG26"; /* RXD */ + ste,config = <&out_lo>; + }; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi index 845eb25..8526084 100644 --- a/arch/arm/boot/dts/ste-href.dtsi +++ b/arch/arm/boot/dts/ste-href.dtsi @@ -180,7 +180,21 @@ stericsson,audio-codec = <&codec>; }; + msp0: msp@80123000 { + pinctrl-names = "default"; + pinctrl-0 = <&msp0_default_mode>; + status = "okay"; + }; + msp1: msp@80124000 { + pinctrl-names = "default"; + pinctrl-0 = <&msp1_default_mode>; + status = "okay"; + }; + + msp2: msp@80117000 { + pinctrl-names = "default"; + pinctrl-0 = <&msp2_default_mode>; status = "okay"; }; diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts index c2cb3ea..65180b2 100644 --- a/arch/arm/boot/dts/ste-snowball.dts +++ b/arch/arm/boot/dts/ste-snowball.dts @@ -93,7 +93,21 @@ stericsson,audio-codec = <&codec>; }; + msp0: msp@80123000 { + pinctrl-names = "default"; + pinctrl-0 = <&msp0_default_mode>; + status = "okay"; + }; + msp1: msp@80124000 { + pinctrl-names = "default"; + pinctrl-0 = <&msp1_default_mode>; + status = "okay"; + }; + + msp2: msp@80117000 { + pinctrl-names = "default"; + pinctrl-0 = <&msp2_default_mode>; status = "okay"; }; diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c index 0f9a077..f7034cb 100644 --- a/arch/arm/mach-ux500/board-mop500-pins.c +++ b/arch/arm/mach-ux500/board-mop500-pins.c @@ -28,12 +28,10 @@ static enum custom_pin_cfg_t pinsfor; BIAS(pd, PIN_PULL_DOWN); BIAS(in_nopull, PIN_INPUT_NOPULL); -BIAS(in_nopull_slpm_nowkup, PIN_INPUT_NOPULL|PIN_SLPM_WAKEUP_DISABLE); BIAS(in_pu, PIN_INPUT_PULLUP); BIAS(in_pd, PIN_INPUT_PULLDOWN); BIAS(out_hi, PIN_OUTPUT_HIGH); BIAS(out_lo, PIN_OUTPUT_LOW); -BIAS(out_lo_slpm_nowkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE); BIAS(abx500_out_lo, PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0)); BIAS(abx500_in_pd, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 1)); @@ -335,22 +333,6 @@ static struct pinctrl_map __initdata ab8505_pinmap[] = { /* Pin control settings */ static struct pinctrl_map __initdata mop500_family_pinmap[] = { /* - * uMSP0, mux in 4 pins, regular placement of RX/TX - * explicitly set the pins to no pull - */ - DB8500_MUX_HOG("msp0txrx_a_1", "msp0"), - DB8500_MUX_HOG("msp0tfstck_a_1", "msp0"), - DB8500_PIN_HOG("GPIO12_AC4", in_nopull), /* TXD */ - DB8500_PIN_HOG("GPIO15_AC3", in_nopull), /* RXD */ - DB8500_PIN_HOG("GPIO13_AF3", in_nopull), /* TFS */ - DB8500_PIN_HOG("GPIO14_AE3", in_nopull), /* TCK */ - /* MSP2 for HDMI, pull down TXD, TCK, TFS */ - DB8500_MUX_HOG("msp2_a_1", "msp2"), - DB8500_PIN_HOG("GPIO193_AH27", in_pd), /* TXD */ - DB8500_PIN_HOG("GPIO194_AF27", in_pd), /* TCK */ - DB8500_PIN_HOG("GPIO195_AG28", in_pd), /* TFS */ - DB8500_PIN_HOG("GPIO196_AG26", out_lo), /* RXD */ - /* * LCD, set TE0 (using LCD VSI0) and D14 (touch screen interrupt) to * pull-up * TODO: is this really correct? Snowball doesn't have a LCD. @@ -363,18 +345,6 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = { * TODO: set for snowball and HREF really?? */ DB8500_PIN_HOG("GPIO218_AH11", gpio_in_pu), - /* - * The following pin sets were known as "runtime pins" before being - * converted to the pinctrl model. Here we model them as "default" - * states. - */ - /* MSP1 for ALSA codec */ - DB8500_MUX_HOG("msp1txrx_a_1", "msp1"), - DB8500_MUX_HOG("msp1_a_1", "msp1"), - DB8500_PIN_HOG("GPIO33_AF2", out_lo_slpm_nowkup), - DB8500_PIN_HOG("GPIO34_AE1", in_nopull_slpm_nowkup), - DB8500_PIN_HOG("GPIO35_AE2", in_nopull_slpm_nowkup), - DB8500_PIN_HOG("GPIO36_AG2", in_nopull_slpm_nowkup), /* Mux in LCD data lines 8 thru 11 and LCDA CLK for MCDE TVOUT */ DB8500_MUX("lcd_d8_d11_a_1", "lcd", "mcde-tvout"), DB8500_MUX("lcdaclk_b_1", "lcda", "mcde-tvout"), -- cgit v1.1 From a45cb698a7db6c623214a5345a32a4ce724ca560 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 13 Nov 2013 14:57:49 +0100 Subject: ARM: ux500: move GPIO217/218 config to device tree This moves the input-pulled-up setting for GPIO217 as used on the HREFs prior to v60 from the boardfile to the device tree. GPIO218 is only used with the TVK UIB so move it to that .dtsi file. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-href-tvk1281618.dtsi | 13 +++++++++++++ arch/arm/boot/dts/ste-hrefprev60.dtsi | 10 ++++++++++ arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi | 5 +++++ arch/arm/mach-ux500/board-mop500-pins.c | 7 ------- 4 files changed, 28 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi index 61b180e..3f31f92 100644 --- a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi +++ b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi @@ -22,6 +22,8 @@ reg = <0x44>; interrupt-parent = <&gpio6>; interrupts = <26 IRQ_TYPE_EDGE_RISING>; + pinctrl-names = "default"; + pinctrl-0 = <&tc35893_tvk_mode>; interrupt-controller; #interrupt-cells = <1>; @@ -64,5 +66,16 @@ }; }; }; + pinctrl { + /* Pull up this GPIO pin */ + tc35893 { + tc35893_tvk_mode: tc35893_tvk { + tvk_cfg { + ste,pins = "GPIO218_AH11"; + ste,config = <&gpio_in_pu>; + }; + }; + }; + }; }; }; diff --git a/arch/arm/boot/dts/ste-hrefprev60.dtsi b/arch/arm/boot/dts/ste-hrefprev60.dtsi index cfd7ef3..6fc94ea 100644 --- a/arch/arm/boot/dts/ste-hrefprev60.dtsi +++ b/arch/arm/boot/dts/ste-hrefprev60.dtsi @@ -33,6 +33,8 @@ reg = <0x42>; interrupt-parent = <&gpio6>; interrupts = <25 IRQ_TYPE_EDGE_RISING>; + pinctrl-names = "default"; + pinctrl-0 = <&tc35892_hrefprev60_mode>; interrupt-controller; #interrupt-cells = <1>; @@ -71,6 +73,14 @@ }; }; + tc35892 { + tc35892_hrefprev60_mode: tc35892_hrefprev60 { + hrefprev60_cfg { + ste,pins = "GPIO217_AH12"; + ste,config = <&gpio_in_pu>; + }; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi b/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi index f213222..9aea983 100644 --- a/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi +++ b/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi @@ -31,6 +31,11 @@ ste,output = ; }; + gpio_in_pu: gpio_input_pull_up { + ste,gpio = ; + ste,input = ; + }; + gpio_out_lo: gpio_output_low { ste,gpio = ; ste,output = ; diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c index f7034cb..c032392 100644 --- a/arch/arm/mach-ux500/board-mop500-pins.c +++ b/arch/arm/mach-ux500/board-mop500-pins.c @@ -340,11 +340,6 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = { DB8500_MUX_HOG("lcdvsi0_a_1", "lcd"), DB8500_PIN_HOG("GPIO68_E1", in_pu), DB8500_PIN_HOG("GPIO84_C2", gpio_in_pu), - /* - * STMPE1601/tc35893 keypad IRQ GPIO 218 - * TODO: set for snowball and HREF really?? - */ - DB8500_PIN_HOG("GPIO218_AH11", gpio_in_pu), /* Mux in LCD data lines 8 thru 11 and LCDA CLK for MCDE TVOUT */ DB8500_MUX("lcd_d8_d11_a_1", "lcd", "mcde-tvout"), DB8500_MUX("lcdaclk_b_1", "lcda", "mcde-tvout"), @@ -625,8 +620,6 @@ static struct pinctrl_map __initdata mop500_pinmap[] = { DB8500_MUX_HOG("ipgpio1_c_1", "ipgpio"), DB8500_PIN_HOG("GPIO6_AF6", in_pu), DB8500_PIN_HOG("GPIO7_AG5", in_pu), - /* TC35892 IRQ, pull up the line, let the driver mux in the pin */ - DB8500_PIN_HOG("GPIO217_AH12", gpio_in_pu), /* * Runtime stuff: make it possible to mux in the SKE keypad * and bias the pins -- cgit v1.1 From a12f703c5a27e2061fd0ea77200e5e2f8cfee54b Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 13 Nov 2013 15:59:40 +0100 Subject: ARM: ux500: move MUSB pin config to device tree This moves the MUSB pin control table out of the board file and into the device tree. Tie the config to the on-chip MUSB device rather than the ab8500-usb device which is off-chip. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-href-family-pinctrl.dtsi | 55 ++++++++++++++++++++++++++ arch/arm/boot/dts/ste-href.dtsi | 6 +++ arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi | 13 ++++++ arch/arm/boot/dts/ste-snowball.dts | 5 +++ arch/arm/mach-ux500/board-mop500-pins.c | 25 ------------ 5 files changed, 79 insertions(+), 25 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi index 7408d3a..6868fec 100644 --- a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi +++ b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi @@ -488,6 +488,61 @@ }; }; }; + + + musb { + musb_default_mode: musb_default { + default_mux { + ste,function = "usb"; + ste,pins = "usb_a_1"; + }; + default_cfg1 { + ste,pins = + "GPIO256_AF28", /* NXT */ + "GPIO258_AD29", /* XCLK */ + "GPIO259_AC29", /* DIR */ + "GPIO260_AD28", /* DAT7 */ + "GPIO261_AD26", /* DAT6 */ + "GPIO262_AE26", /* DAT5 */ + "GPIO263_AG29", /* DAT4 */ + "GPIO264_AE27", /* DAT3 */ + "GPIO265_AD27", /* DAT2 */ + "GPIO266_AC28", /* DAT1 */ + "GPIO267_AC27"; /* DAT0 */ + ste,config = <&in_nopull>; + }; + default_cfg2 { + ste,pins = "GPIO257_AE29"; /* STP */ + ste,config = <&out_hi>; + }; + }; + + musb_sleep_mode: musb_sleep { + sleep_cfg1 { + ste,pins = + "GPIO256_AF28", /* NXT */ + "GPIO258_AD29", /* XCLK */ + "GPIO259_AC29"; /* DIR */ + ste,config = <&slpm_wkup_pdis_en>; + }; + sleep_cfg2 { + ste,pins = "GPIO257_AE29"; /* STP */ + ste,config = <&slpm_out_hi_wkup_pdis>; + }; + sleep_cfg3 { + ste,pins = + "GPIO260_AD28", /* DAT7 */ + "GPIO261_AD26", /* DAT6 */ + "GPIO262_AE26", /* DAT5 */ + "GPIO263_AG29", /* DAT4 */ + "GPIO264_AE27", /* DAT3 */ + "GPIO265_AD27", /* DAT2 */ + "GPIO266_AC28", /* DAT1 */ + "GPIO267_AC27"; /* DAT0 */ + ste,config = <&slpm_in_wkup_pdis_en>; + }; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi index 8526084..4fda2d9 100644 --- a/arch/arm/boot/dts/ste-href.dtsi +++ b/arch/arm/boot/dts/ste-href.dtsi @@ -30,6 +30,12 @@ }; soc { + usb_per5@a03e0000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&musb_default_mode>; + pinctrl-1 = <&musb_sleep_mode>; + }; + uart@80120000 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&uart0_default_mode>; diff --git a/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi b/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi index 9aea983..9f3e875 100644 --- a/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi +++ b/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi @@ -41,6 +41,12 @@ ste,output = ; }; + slpm_wkup_pdis_en: slpm_wkup_pdis_en { + ste,sleep = ; + ste,sleep-wakeup = ; + ste,sleep-pull-disable = ; + }; + slpm_in_pu: slpm_in_pu { ste,sleep = ; ste,sleep-input = ; @@ -54,6 +60,13 @@ ste,sleep-pull-disable = ; }; + slpm_in_wkup_pdis_en: slpm_in_wkup_pdis_en { + ste,sleep = ; + ste,sleep-input = ; + ste,sleep-wakeup = ; + ste,sleep-pull-disable = ; + }; + slpm_out_lo: slpm_out_lo { ste,sleep = ; ste,sleep-output = ; diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts index 65180b2..4763b80 100644 --- a/arch/arm/boot/dts/ste-snowball.dts +++ b/arch/arm/boot/dts/ste-snowball.dts @@ -85,6 +85,11 @@ }; soc { + usb_per5@a03e0000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&musb_default_mode>; + pinctrl-1 = <&musb_sleep_mode>; + }; sound { compatible = "stericsson,snd-soc-mop500"; diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c index c032392..a6d431b 100644 --- a/arch/arm/mach-ux500/board-mop500-pins.c +++ b/arch/arm/mach-ux500/board-mop500-pins.c @@ -30,7 +30,6 @@ BIAS(pd, PIN_PULL_DOWN); BIAS(in_nopull, PIN_INPUT_NOPULL); BIAS(in_pu, PIN_INPUT_PULLUP); BIAS(in_pd, PIN_INPUT_PULLDOWN); -BIAS(out_hi, PIN_OUTPUT_HIGH); BIAS(out_lo, PIN_OUTPUT_LOW); BIAS(abx500_out_lo, PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0)); @@ -47,18 +46,12 @@ BIAS(gpio_out_lo, PIN_OUTPUT_LOW|PIN_GPIOMODE_ENABLED); /* Sleep modes */ BIAS(slpm_in_wkup_pdis, PIN_SLEEPMODE_ENABLED| PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED); -BIAS(slpm_in_wkup_pdis_en, PIN_SLEEPMODE_ENABLED| - PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED); BIAS(slpm_wkup_pdis, PIN_SLEEPMODE_ENABLED| PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED); -BIAS(slpm_wkup_pdis_en, PIN_SLEEPMODE_ENABLED| - PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED); BIAS(slpm_out_lo_pdis, PIN_SLEEPMODE_ENABLED| PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE|PIN_SLPM_PDIS_DISABLED); BIAS(slpm_out_lo_wkup_pdis, PIN_SLEEPMODE_ENABLED| PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED); -BIAS(slpm_out_hi_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_OUTPUT_HIGH| - PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED); BIAS(slpm_in_pu_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|PIN_SLPM_INPUT_PULLUP| PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED); @@ -349,24 +342,6 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = { /* LCD VSI1 sleep state */ DB8500_PIN_SLEEP("GPIO69_E2", slpm_in_wkup_pdis, "0-0070"), - /* Mux in USB pins, drive STP high */ - /* USB default state */ - DB8500_MUX("usb_a_1", "usb", "ab8500-usb.0"), - DB8500_PIN("GPIO257_AE29", out_hi, "ab8500-usb.0"), /* STP */ - /* USB sleep state */ - DB8500_PIN_SLEEP("GPIO256_AF28", slpm_wkup_pdis_en, "ab8500-usb.0"), /* NXT */ - DB8500_PIN_SLEEP("GPIO257_AE29", slpm_out_hi_wkup_pdis, "ab8500-usb.0"), /* STP */ - DB8500_PIN_SLEEP("GPIO258_AD29", slpm_wkup_pdis_en, "ab8500-usb.0"), /* XCLK */ - DB8500_PIN_SLEEP("GPIO259_AC29", slpm_wkup_pdis_en, "ab8500-usb.0"), /* DIR */ - DB8500_PIN_SLEEP("GPIO260_AD28", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT7 */ - DB8500_PIN_SLEEP("GPIO261_AD26", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT6 */ - DB8500_PIN_SLEEP("GPIO262_AE26", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT5 */ - DB8500_PIN_SLEEP("GPIO263_AG29", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT4 */ - DB8500_PIN_SLEEP("GPIO264_AE27", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT3 */ - DB8500_PIN_SLEEP("GPIO265_AD27", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT2 */ - DB8500_PIN_SLEEP("GPIO266_AC28", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT1 */ - DB8500_PIN_SLEEP("GPIO267_AC27", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT0 */ - /* Mux in SPI2 pins on the "other C1" altfunction */ DB8500_MUX("spi2_oc1_2", "spi2", "spi2"), DB8500_PIN("GPIO216_AG12", gpio_out_hi, "spi2"), /* FRM */ -- cgit v1.1 From 38656820aa31e853c7bfbe2658cc8a78e303583b Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 14 Nov 2013 10:27:40 +0100 Subject: ARM: ux500: move SPI pin config to device tree This moves the SPI pin control table out of the board file and into the device tree. Move the specific setting for SSP0 on the HREFprev60 into the prev60-specific DTS file. The SPI2 configuration is not really connected to any device, as it will conflict with GPIO218 which is used on all HREFs. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-href-family-pinctrl.dtsi | 61 ++++++++++++++++++++++++++ arch/arm/boot/dts/ste-hrefprev60.dtsi | 22 ++++++++++ arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi | 31 +++++++++++++ arch/arm/mach-ux500/board-mop500-pins.c | 19 -------- 4 files changed, 114 insertions(+), 19 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi index 6868fec..ec990d8 100644 --- a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi +++ b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi @@ -215,6 +215,67 @@ }; }; + /* Settings for all SPI default and sleep states */ + spi2 { + spi2_default_mode: spi_default { + default_mux { + ste,function = "spi2"; + ste,pins = "spi2_oc1_2"; + }; + default_cfg1 { + ste,pins = "GPIO216_AG12"; /* FRM */ + ste,config = <&gpio_out_hi>; + }; + default_cfg2 { + ste,pins = "GPIO218_AH11"; /* RXD */ + ste,config = <&in_pd>; + }; + default_cfg3 { + ste,pins = + "GPIO215_AH13", /* TXD */ + "GPIO217_AH12"; /* CLK */ + ste,config = <&out_lo>; + }; + }; + + spi2_idle_mode: spi_idle { + /* + * The idle mode is basically sleep mode sans wakeups. Also + * note that we have muxes the pins off the function here + * as we do not state any muxing. + */ + idle_cfg1 { + ste,pins = "GPIO218_AH11"; /* RXD */ + ste,config = <&slpm_in_pdis>; + }; + idle_cfg2 { + ste,pins = "GPIO215_AH13"; /* TXD */ + ste,config = <&slpm_out_lo_pdis>; + }; + idle_cfg3 { + ste,pins = "GPIO217_AH12"; /* CLK */ + ste,config = <&slpm_pdis>; + }; + }; + + spi2_sleep_mode: spi_sleep { + sleep_cfg1 { + ste,pins = + "GPIO216_AG12", /* FRM */ + "GPIO218_AH11"; /* RXD */ + ste,config = <&slpm_in_wkup_pdis>; + }; + sleep_cfg2 { + ste,pins = "GPIO215_AH13"; /* TXD */ + ste,config = <&slpm_out_lo_wkup_pdis>; + }; + sleep_cfg3 { + ste,pins = "GPIO217_AH12"; /* CLK */ + ste,config = <&slpm_wkup_pdis>; + }; + }; + }; + /* Settings for all MMC/SD/SDIO default and sleep states */ sdi0 { /* This is the external SD card slot, 4 bits wide */ diff --git a/arch/arm/boot/dts/ste-hrefprev60.dtsi b/arch/arm/boot/dts/ste-hrefprev60.dtsi index 6fc94ea..32295e3 100644 --- a/arch/arm/boot/dts/ste-hrefprev60.dtsi +++ b/arch/arm/boot/dts/ste-hrefprev60.dtsi @@ -51,6 +51,15 @@ }; }; + ssp@80002000 { + /* + * On the first generation boards, this SSP/SPI port was connected + * to the AB8500. + */ + pinctrl-names = "default"; + pinctrl-0 = <&ssp0_hrefprev60_mode>; + }; + vmmci: regulator-gpio { gpios = <&tc3589x_gpio 18 0x4>; enable-gpio = <&tc3589x_gpio 17 0x4>; @@ -59,6 +68,19 @@ }; pinctrl { + ssp0 { + ssp0_hrefprev60_mode: ssp0_hrefprev60_default { + hrefprev60_mux { + ste,function = "ssp0"; + ste,pins = "ssp0_a_1"; + }; + hrefprev60_cfg1 { + ste,pins = "GPIO145_C13"; /* RXD */ + ste,config = <&in_pd>; + }; + + }; + }; sdi0 { /* This additional pin needed on early MOP500 and HREFs previous to v60 */ sdi0_default_mode: sdi0_default { diff --git a/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi b/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi index 9f3e875..456a25f 100644 --- a/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi +++ b/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi @@ -41,6 +41,23 @@ ste,output = ; }; + gpio_out_hi: gpio_output_high { + ste,gpio = ; + ste,output = ; + }; + + slpm_pdis: slpm_pdis { + ste,sleep = ; + ste,sleep-wakeup = ; + ste,sleep-pull-disable = ; + }; + + slpm_wkup_pdis: slpm_wkup_pdis { + ste,sleep = ; + ste,sleep-wakeup = ; + ste,sleep-pull-disable = ; + }; + slpm_wkup_pdis_en: slpm_wkup_pdis_en { ste,sleep = ; ste,sleep-wakeup = ; @@ -53,6 +70,13 @@ ste,sleep-wakeup = ; }; + slpm_in_pdis: slpm_in_pdis { + ste,sleep = ; + ste,sleep-input = ; + ste,sleep-wakeup = ; + ste,sleep-pull-disable = ; + }; + slpm_in_wkup_pdis: slpm_in_wkup_pdis { ste,sleep = ; ste,sleep-input = ; @@ -86,6 +110,13 @@ ste,sleep-pull-disable = ; }; + slpm_out_lo_pdis: slpm_out_lo_pdis { + ste,sleep = ; + ste,sleep-output = ; + ste,sleep-wakeup = ; + ste,sleep-pull-disable = ; + }; + slpm_out_lo_wkup_pdis: slpm_out_lo_wkup_pdis { ste,sleep = ; ste,sleep-output = ; diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c index a6d431b..8fba58c 100644 --- a/arch/arm/mach-ux500/board-mop500-pins.c +++ b/arch/arm/mach-ux500/board-mop500-pins.c @@ -342,22 +342,6 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = { /* LCD VSI1 sleep state */ DB8500_PIN_SLEEP("GPIO69_E2", slpm_in_wkup_pdis, "0-0070"), - /* Mux in SPI2 pins on the "other C1" altfunction */ - DB8500_MUX("spi2_oc1_2", "spi2", "spi2"), - DB8500_PIN("GPIO216_AG12", gpio_out_hi, "spi2"), /* FRM */ - DB8500_PIN("GPIO218_AH11", in_pd, "spi2"), /* RXD */ - DB8500_PIN("GPIO215_AH13", out_lo, "spi2"), /* TXD */ - DB8500_PIN("GPIO217_AH12", out_lo, "spi2"), /* CLK */ - /* SPI2 idle state */ - DB8500_PIN_IDLE("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */ - DB8500_PIN_IDLE("GPIO215_AH13", slpm_out_lo_wkup_pdis, "spi2"), /* TXD */ - DB8500_PIN_IDLE("GPIO217_AH12", slpm_wkup_pdis, "spi2"), /* CLK */ - /* SPI2 sleep state */ - DB8500_PIN_SLEEP("GPIO216_AG12", slpm_in_wkup_pdis, "spi2"), /* FRM */ - DB8500_PIN_SLEEP("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */ - DB8500_PIN_SLEEP("GPIO215_AH13", slpm_out_lo_wkup_pdis, "spi2"), /* TXD */ - DB8500_PIN_SLEEP("GPIO217_AH12", slpm_wkup_pdis, "spi2"), /* CLK */ - /* ske default state */ DB8500_MUX("kp_a_2", "kp", "nmk-ske-keypad"), DB8500_PIN("GPIO153_B17", in_pd, "nmk-ske-keypad"), /* I7 */ @@ -582,9 +566,6 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = { * on-chip pins as the HREFv60 and later does. */ static struct pinctrl_map __initdata mop500_pinmap[] = { - /* Mux in SSP0, pull down RXD pin */ - DB8500_MUX_HOG("ssp0_a_1", "ssp0"), - DB8500_PIN_HOG("GPIO145_C13", pd), /* * XENON Flashgun on image processor GPIO (controlled from image * processor firmware), mux in these image processor GPIO lines 0 -- cgit v1.1 From 6e9a88a0e5397e5e7811f5526c9771e799978b56 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 14 Nov 2013 15:21:00 +0100 Subject: ARM: ux500: create MCDE node to collect resources As we need to connect resources such as pin mappings and clocks when deleting board files, we create a MCDE node even though there is no driver for it. As it is only using standard bindings right now, this does not matter much. When a proper driver is written for the MCDE, it can augment this node with custom properties. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-dbx5x0.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index 50ff5ab..e0853ea 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -1002,6 +1002,23 @@ status = "disabled"; }; + mcde@a0350000 { + compatible = "stericsson,mcde"; + reg = <0xa0350000 0x1000>, /* MCDE */ + <0xa0351000 0x1000>, /* DSI link 1 */ + <0xa0352000 0x1000>, /* DSI link 2 */ + <0xa0353000 0x1000>; /* DSI link 3 */ + interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */ + <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */ + <&prcmu_clk PRCMU_PLLDSI>, /* HDMI clock */ + <&prcmu_clk PRCMU_DSI0CLK>, /* DSI 0 */ + <&prcmu_clk PRCMU_DSI1CLK>, /* DSI 1 */ + <&prcmu_clk PRCMU_DSI0ESCCLK>, /* TVout clock 0 */ + <&prcmu_clk PRCMU_DSI1ESCCLK>, /* TVout clock 1 */ + <&prcmu_clk PRCMU_DSI2ESCCLK>; /* TVout clock 2 */ + }; + cryp@a03cb000 { compatible = "stericsson,ux500-cryp"; reg = <0xa03cb000 0x1000>; -- cgit v1.1 From 817a5b967d5f2c78e9ab41ec91fc44f872201fc6 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 14 Nov 2013 15:23:20 +0100 Subject: ARM: ux500: move MCDE pin config to device tree This moves the MCDE pin control table out of the board file and into the device tree. Some pins and configs have been marked as used by sub-devices or slaves to the MCDE, such as I2C device 0-070 which is the HDMI interface circuit AV8100, but the pins rather belong to the MCDE SOC block as they come out of the main ASIC. The touch screen GPIO is not related to MCDE so this gets deleted and need to be tied to the respective touch screen (I2C) device once that device is added instead. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-href-family-pinctrl.dtsi | 27 ++++++++++++++++++++++++++ arch/arm/boot/dts/ste-href.dtsi | 6 ++++++ arch/arm/boot/dts/ste-snowball.dts | 6 ++++++ arch/arm/mach-ux500/board-mop500-pins.c | 19 ------------------ 4 files changed, 39 insertions(+), 19 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi index ec990d8..779829a 100644 --- a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi +++ b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi @@ -604,6 +604,33 @@ }; }; }; + + mcde { + lcd_default_mode: lcd_default { + default_mux { + /* Mux in VSI0 and all the data lines */ + ste,function = "lcd"; + ste,pins = + "lcdvsi0_a_1", /* VSI0 for LCD */ + "lcd_d0_d7_a_1", /* Data lines */ + "lcd_d8_d11_a_1", /* TV-out */ + "lcdaclk_b_1", /* Clock line for TV-out */ + "lcdvsi1_a_1"; /* VSI1 for HDMI */ + }; + default_cfg1 { + ste,pins = + "GPIO68_E1", /* VSI0 */ + "GPIO69_E2"; /* VSI1 */ + ste,config = <&in_pu>; + }; + }; + lcd_sleep_mode: lcd_sleep { + sleep_cfg1 { + ste,pins = "GPIO69_E2"; /* VSI1 */ + ste,config = <&slpm_in_wkup_pdis>; + }; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi index 4fda2d9..56772c3 100644 --- a/arch/arm/boot/dts/ste-href.dtsi +++ b/arch/arm/boot/dts/ste-href.dtsi @@ -261,5 +261,11 @@ }; }; }; + + mcde@a0350000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&lcd_default_mode>; + pinctrl-1 = <&lcd_sleep_mode>; + }; }; }; diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts index 4763b80..53febe5 100644 --- a/arch/arm/boot/dts/ste-snowball.dts +++ b/arch/arm/boot/dts/ste-snowball.dts @@ -362,5 +362,11 @@ }; }; }; + + mcde@a0350000 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&lcd_default_mode>; + pinctrl-1 = <&lcd_sleep_mode>; + }; }; }; diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c index 8fba58c..4cc4cb1 100644 --- a/arch/arm/mach-ux500/board-mop500-pins.c +++ b/arch/arm/mach-ux500/board-mop500-pins.c @@ -46,8 +46,6 @@ BIAS(gpio_out_lo, PIN_OUTPUT_LOW|PIN_GPIOMODE_ENABLED); /* Sleep modes */ BIAS(slpm_in_wkup_pdis, PIN_SLEEPMODE_ENABLED| PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED); -BIAS(slpm_wkup_pdis, PIN_SLEEPMODE_ENABLED| - PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED); BIAS(slpm_out_lo_pdis, PIN_SLEEPMODE_ENABLED| PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE|PIN_SLPM_PDIS_DISABLED); BIAS(slpm_out_lo_wkup_pdis, PIN_SLEEPMODE_ENABLED| @@ -325,23 +323,6 @@ static struct pinctrl_map __initdata ab8505_pinmap[] = { /* Pin control settings */ static struct pinctrl_map __initdata mop500_family_pinmap[] = { - /* - * LCD, set TE0 (using LCD VSI0) and D14 (touch screen interrupt) to - * pull-up - * TODO: is this really correct? Snowball doesn't have a LCD. - */ - DB8500_MUX_HOG("lcdvsi0_a_1", "lcd"), - DB8500_PIN_HOG("GPIO68_E1", in_pu), - DB8500_PIN_HOG("GPIO84_C2", gpio_in_pu), - /* Mux in LCD data lines 8 thru 11 and LCDA CLK for MCDE TVOUT */ - DB8500_MUX("lcd_d8_d11_a_1", "lcd", "mcde-tvout"), - DB8500_MUX("lcdaclk_b_1", "lcda", "mcde-tvout"), - /* Mux in LCD VSI1 and pull it up for MCDE HDMI output */ - DB8500_MUX("lcdvsi1_a_1", "lcd", "0-0070"), - DB8500_PIN("GPIO69_E2", in_pu, "0-0070"), - /* LCD VSI1 sleep state */ - DB8500_PIN_SLEEP("GPIO69_E2", slpm_in_wkup_pdis, "0-0070"), - /* ske default state */ DB8500_MUX("kp_a_2", "kp", "nmk-ske-keypad"), DB8500_PIN("GPIO153_B17", in_pd, "nmk-ske-keypad"), /* I7 */ -- cgit v1.1 From 279571358df1e3f9788f1095d73b777fdb68c7e0 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 15 Nov 2013 09:20:28 +0100 Subject: ARM: ux500: move SKE pin config to device tree This moves the SKE keypad pin control table out of the board file and into the device tree. This was previously set to be active on all MOP500 and HREF boards but after reading the schematic this seems incorrect: the HREFv60 and later uses one of these for MC5 and no reference designs have the SKE connected to any hardware so just leave the pins alone in the power-on state. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-href-family-pinctrl.dtsi | 90 ++++++++++++++++++++++++++ arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi | 7 ++ arch/arm/mach-ux500/board-mop500-pins.c | 87 ------------------------- 3 files changed, 97 insertions(+), 87 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi index 779829a..854a4a6 100644 --- a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi +++ b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi @@ -631,6 +631,96 @@ }; }; }; + + ske { + /* SKE keys on position 2 in an 8x8 matrix */ + ske_kpa2_default_mode: ske_kpa2_default { + default_mux { + ste,function = "kp"; + ste,pins = "kp_a_2"; + }; + default_cfg1 { + ste,pins = + "GPIO153_B17", /* I7 */ + "GPIO154_C16", /* I6 */ + "GPIO155_C19", /* I5 */ + "GPIO156_C17", /* I4 */ + "GPIO161_D21", /* I3 */ + "GPIO162_D20", /* I2 */ + "GPIO163_C20", /* I1 */ + "GPIO164_B21"; /* I0 */ + ste,config = <&in_pd>; + }; + default_cfg2 { + ste,pins = + "GPIO157_A18", /* O7 */ + "GPIO158_C18", /* O6 */ + "GPIO159_B19", /* O5 */ + "GPIO160_B20", /* O4 */ + "GPIO165_C21", /* O3 */ + "GPIO166_A22", /* O2 */ + "GPIO167_B24", /* O1 */ + "GPIO168_C22"; /* O0 */ + ste,config = <&out_lo>; + }; + }; + ske_kpa2_sleep_mode: ske_kpa2_sleep { + sleep_cfg1 { + ste,pins = + "GPIO153_B17", /* I7 */ + "GPIO154_C16", /* I6 */ + "GPIO155_C19", /* I5 */ + "GPIO156_C17", /* I4 */ + "GPIO161_D21", /* I3 */ + "GPIO162_D20", /* I2 */ + "GPIO163_C20", /* I1 */ + "GPIO164_B21"; /* I0 */ + ste,config = <&slpm_in_pu_wkup_pdis_en>; + }; + sleep_cfg2 { + ste,pins = + "GPIO157_A18", /* O7 */ + "GPIO158_C18", /* O6 */ + "GPIO159_B19", /* O5 */ + "GPIO160_B20", /* O4 */ + "GPIO165_C21", /* O3 */ + "GPIO166_A22", /* O2 */ + "GPIO167_B24", /* O1 */ + "GPIO168_C22"; /* O0 */ + ste,config = <&slpm_out_lo_pdis>; + }; + }; + /* + * SKE keys on position 1 and "other C1" combi giving + * six rows of six keys. + */ + ske_kpaoc1_default_mode: ske_kpaoc1_default { + default_mux { + ste,function = "kp"; + ste,pins = "kp_a_1", "kp_oc1_1"; + }; + default_cfg1 { + ste,pins = + "GPIO91_B6", /* KP_O0 */ + "GPIO90_A3", /* KP_O1 */ + "GPIO87_B3", /* KP_O2 */ + "GPIO86_C6", /* KP_O3 */ + "GPIO96_D8", /* KP_O6 */ + "GPIO94_D7"; /* KP_O7 */ + ste,config = <&out_lo>; + }; + default_cfg2 { + ste,pins = + "GPIO93_B7", /* KP_I0 */ + "GPIO92_D6", /* KP_I1 */ + "GPIO89_E6", /* KP_I2 */ + "GPIO88_C4", /* KP_I3 */ + "GPIO97_D9", /* KP_I6 */ + "GPIO95_E8"; /* KP_I7 */ + ste,config = <&in_pu>; + }; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi b/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi index 456a25f..ee143b0 100644 --- a/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi +++ b/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi @@ -91,6 +91,13 @@ ste,sleep-pull-disable = ; }; + slpm_in_pu_wkup_pdis_en: slpm_in_wkup_pdis_en { + ste,sleep = ; + ste,sleep-input = ; + ste,sleep-wakeup = ; + ste,sleep-pull-disable = ; + }; + slpm_out_lo: slpm_out_lo { ste,sleep = ; ste,sleep-output = ; diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c index 4cc4cb1..07ddb89 100644 --- a/arch/arm/mach-ux500/board-mop500-pins.c +++ b/arch/arm/mach-ux500/board-mop500-pins.c @@ -323,42 +323,6 @@ static struct pinctrl_map __initdata ab8505_pinmap[] = { /* Pin control settings */ static struct pinctrl_map __initdata mop500_family_pinmap[] = { - /* ske default state */ - DB8500_MUX("kp_a_2", "kp", "nmk-ske-keypad"), - DB8500_PIN("GPIO153_B17", in_pd, "nmk-ske-keypad"), /* I7 */ - DB8500_PIN("GPIO154_C16", in_pd, "nmk-ske-keypad"), /* I6 */ - DB8500_PIN("GPIO155_C19", in_pd, "nmk-ske-keypad"), /* I5 */ - DB8500_PIN("GPIO156_C17", in_pd, "nmk-ske-keypad"), /* I4 */ - DB8500_PIN("GPIO161_D21", in_pd, "nmk-ske-keypad"), /* I3 */ - DB8500_PIN("GPIO162_D20", in_pd, "nmk-ske-keypad"), /* I2 */ - DB8500_PIN("GPIO163_C20", in_pd, "nmk-ske-keypad"), /* I1 */ - DB8500_PIN("GPIO164_B21", in_pd, "nmk-ske-keypad"), /* I0 */ - DB8500_PIN("GPIO157_A18", out_lo, "nmk-ske-keypad"), /* O7 */ - DB8500_PIN("GPIO158_C18", out_lo, "nmk-ske-keypad"), /* O6 */ - DB8500_PIN("GPIO159_B19", out_lo, "nmk-ske-keypad"), /* O5 */ - DB8500_PIN("GPIO160_B20", out_lo, "nmk-ske-keypad"), /* O4 */ - DB8500_PIN("GPIO165_C21", out_lo, "nmk-ske-keypad"), /* O3 */ - DB8500_PIN("GPIO166_A22", out_lo, "nmk-ske-keypad"), /* O2 */ - DB8500_PIN("GPIO167_B24", out_lo, "nmk-ske-keypad"), /* O1 */ - DB8500_PIN("GPIO168_C22", out_lo, "nmk-ske-keypad"), /* O0 */ - /* ske sleep state */ - DB8500_PIN_SLEEP("GPIO153_B17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I7 */ - DB8500_PIN_SLEEP("GPIO154_C16", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I6 */ - DB8500_PIN_SLEEP("GPIO155_C19", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I5 */ - DB8500_PIN_SLEEP("GPIO156_C17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I4 */ - DB8500_PIN_SLEEP("GPIO161_D21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I3 */ - DB8500_PIN_SLEEP("GPIO162_D20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I2 */ - DB8500_PIN_SLEEP("GPIO163_C20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I1 */ - DB8500_PIN_SLEEP("GPIO164_B21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I0 */ - DB8500_PIN_SLEEP("GPIO157_A18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O7 */ - DB8500_PIN_SLEEP("GPIO158_C18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O6 */ - DB8500_PIN_SLEEP("GPIO159_B19", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O5 */ - DB8500_PIN_SLEEP("GPIO160_B20", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O4 */ - DB8500_PIN_SLEEP("GPIO165_C21", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O3 */ - DB8500_PIN_SLEEP("GPIO166_A22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O2 */ - DB8500_PIN_SLEEP("GPIO167_B24", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O1 */ - DB8500_PIN_SLEEP("GPIO168_C22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O0 */ - /* STM APE pins states */ DB8500_MUX_STATE("stmape_c_1", "stmape", "stm", "ape_mipi34"), @@ -561,41 +525,6 @@ static struct pinctrl_map __initdata mop500_pinmap[] = { * Runtime stuff: make it possible to mux in the SKE keypad * and bias the pins */ - /* ske default state */ - DB8500_MUX("kp_a_2", "kp", "nmk-ske-keypad"), - DB8500_PIN("GPIO153_B17", in_pu, "nmk-ske-keypad"), /* I7 */ - DB8500_PIN("GPIO154_C16", in_pu, "nmk-ske-keypad"), /* I6 */ - DB8500_PIN("GPIO155_C19", in_pu, "nmk-ske-keypad"), /* I5 */ - DB8500_PIN("GPIO156_C17", in_pu, "nmk-ske-keypad"), /* I4 */ - DB8500_PIN("GPIO161_D21", in_pu, "nmk-ske-keypad"), /* I3 */ - DB8500_PIN("GPIO162_D20", in_pu, "nmk-ske-keypad"), /* I2 */ - DB8500_PIN("GPIO163_C20", in_pu, "nmk-ske-keypad"), /* I1 */ - DB8500_PIN("GPIO164_B21", in_pu, "nmk-ske-keypad"), /* I0 */ - DB8500_PIN("GPIO157_A18", out_lo, "nmk-ske-keypad"), /* O7 */ - DB8500_PIN("GPIO158_C18", out_lo, "nmk-ske-keypad"), /* O6 */ - DB8500_PIN("GPIO159_B19", out_lo, "nmk-ske-keypad"), /* O5 */ - DB8500_PIN("GPIO160_B20", out_lo, "nmk-ske-keypad"), /* O4 */ - DB8500_PIN("GPIO165_C21", out_lo, "nmk-ske-keypad"), /* O3 */ - DB8500_PIN("GPIO166_A22", out_lo, "nmk-ske-keypad"), /* O2 */ - DB8500_PIN("GPIO167_B24", out_lo, "nmk-ske-keypad"), /* O1 */ - DB8500_PIN("GPIO168_C22", out_lo, "nmk-ske-keypad"), /* O0 */ - /* ske sleep state */ - DB8500_PIN_SLEEP("GPIO153_B17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I7 */ - DB8500_PIN_SLEEP("GPIO154_C16", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I6 */ - DB8500_PIN_SLEEP("GPIO155_C19", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I5 */ - DB8500_PIN_SLEEP("GPIO156_C17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I4 */ - DB8500_PIN_SLEEP("GPIO161_D21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I3 */ - DB8500_PIN_SLEEP("GPIO162_D20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I2 */ - DB8500_PIN_SLEEP("GPIO163_C20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I1 */ - DB8500_PIN_SLEEP("GPIO164_B21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I0 */ - DB8500_PIN_SLEEP("GPIO157_A18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O7 */ - DB8500_PIN_SLEEP("GPIO158_C18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O6 */ - DB8500_PIN_SLEEP("GPIO159_B19", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O5 */ - DB8500_PIN_SLEEP("GPIO160_B20", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O4 */ - DB8500_PIN_SLEEP("GPIO165_C21", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O3 */ - DB8500_PIN_SLEEP("GPIO166_A22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O2 */ - DB8500_PIN_SLEEP("GPIO167_B24", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O1 */ - DB8500_PIN_SLEEP("GPIO168_C22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O0 */ }; /* @@ -655,22 +584,6 @@ static struct pinctrl_map __initdata hrefv60_pinmap[] = { DB8500_PIN_HOG("GPIO77_H1", gpio_out_lo), /* NFC_ENA */ DB8500_PIN_HOG("GPIO144_B13", gpio_in_pd), /* NFC_IRQ */ DB8500_PIN_HOG("GPIO142_C11", gpio_out_lo), /* NFC_RESET */ - /* - * SKE keyboard partly on alt A and partly on "Other alt C1" - * Driver KP_O1,2,3,6,7 low and pull up KP_I 0,2,3 for three - * rows of 6 keys, then pull up force sensing interrup and - * drive reset and force sensing WU low. - */ - DB8500_MUX_HOG("kp_a_1", "kp"), - DB8500_MUX_HOG("kp_oc1_1", "kp"), - DB8500_PIN_HOG("GPIO90_A3", out_lo), /* KP_O1 */ - DB8500_PIN_HOG("GPIO87_B3", out_lo), /* KP_O2 */ - DB8500_PIN_HOG("GPIO86_C6", out_lo), /* KP_O3 */ - DB8500_PIN_HOG("GPIO96_D8", out_lo), /* KP_O6 */ - DB8500_PIN_HOG("GPIO94_D7", out_lo), /* KP_O7 */ - DB8500_PIN_HOG("GPIO93_B7", in_pu), /* KP_I0 */ - DB8500_PIN_HOG("GPIO89_E6", in_pu), /* KP_I2 */ - DB8500_PIN_HOG("GPIO88_C4", in_pu), /* KP_I3 */ DB8500_PIN_HOG("GPIO91_B6", gpio_in_pu), /* FORCE_SENSING_INT */ DB8500_PIN_HOG("GPIO92_D6", gpio_out_lo), /* FORCE_SENSING_RST */ DB8500_PIN_HOG("GPIO97_D9", gpio_out_lo), /* FORCE_SENSING_WU */ -- cgit v1.1 From fda989c0b51a563d23d3cf3d4c20dd3405268644 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 15 Nov 2013 09:28:39 +0100 Subject: ARM: ux500: drop STM pinmap settings The pin mappings for the STM (System Trace Macrocell) are not really used by anything: we have no driver for is and the settings are not connected to any device. We can recreate the different mux outputs in the device tree the day we need them. Drop these for now. Signed-off-by: Linus Walleij --- arch/arm/mach-ux500/board-mop500-pins.c | 200 -------------------------------- 1 file changed, 200 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c index 07ddb89..c311d11 100644 --- a/arch/arm/mach-ux500/board-mop500-pins.c +++ b/arch/arm/mach-ux500/board-mop500-pins.c @@ -27,7 +27,6 @@ static enum custom_pin_cfg_t pinsfor; #define BIAS(a,b) static unsigned long a[] = { b } BIAS(pd, PIN_PULL_DOWN); -BIAS(in_nopull, PIN_INPUT_NOPULL); BIAS(in_pu, PIN_INPUT_PULLUP); BIAS(in_pd, PIN_INPUT_PULLDOWN); BIAS(out_lo, PIN_OUTPUT_LOW); @@ -43,15 +42,6 @@ BIAS(gpio_in_pu_slpm_gpio_nopull, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED|PIN_SLPM BIAS(gpio_in_pd_slpm_gpio_nopull, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL); BIAS(gpio_out_hi, PIN_OUTPUT_HIGH|PIN_GPIOMODE_ENABLED); BIAS(gpio_out_lo, PIN_OUTPUT_LOW|PIN_GPIOMODE_ENABLED); -/* Sleep modes */ -BIAS(slpm_in_wkup_pdis, PIN_SLEEPMODE_ENABLED| - PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED); -BIAS(slpm_out_lo_pdis, PIN_SLEEPMODE_ENABLED| - PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE|PIN_SLPM_PDIS_DISABLED); -BIAS(slpm_out_lo_wkup_pdis, PIN_SLEEPMODE_ENABLED| - PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED); -BIAS(slpm_in_pu_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|PIN_SLPM_INPUT_PULLUP| - PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED); /* We use these to define hog settings that are always done on boot */ #define DB8500_MUX_HOG(group,func) \ @@ -321,190 +311,6 @@ static struct pinctrl_map __initdata ab8505_pinmap[] = { AB8505_PIN_HOG("GPIO53_D15", in_pd), }; -/* Pin control settings */ -static struct pinctrl_map __initdata mop500_family_pinmap[] = { - /* STM APE pins states */ - DB8500_MUX_STATE("stmape_c_1", "stmape", - "stm", "ape_mipi34"), - DB8500_PIN_STATE("GPIO70_G5", in_nopull, - "stm", "ape_mipi34"), /* clk */ - DB8500_PIN_STATE("GPIO71_G4", in_nopull, - "stm", "ape_mipi34"), /* dat3 */ - DB8500_PIN_STATE("GPIO72_H4", in_nopull, - "stm", "ape_mipi34"), /* dat2 */ - DB8500_PIN_STATE("GPIO73_H3", in_nopull, - "stm", "ape_mipi34"), /* dat1 */ - DB8500_PIN_STATE("GPIO74_J3", in_nopull, - "stm", "ape_mipi34"), /* dat0 */ - - DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis, - "stm", "ape_mipi34_sleep"), /* clk */ - DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis, - "stm", "ape_mipi34_sleep"), /* dat3 */ - DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis, - "stm", "ape_mipi34_sleep"), /* dat2 */ - DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis, - "stm", "ape_mipi34_sleep"), /* dat1 */ - DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis, - "stm", "ape_mipi34_sleep"), /* dat0 */ - - DB8500_MUX_STATE("stmape_oc1_1", "stmape", - "stm", "ape_microsd"), - DB8500_PIN_STATE("GPIO23_AA4", in_nopull, - "stm", "ape_microsd"), /* clk */ - DB8500_PIN_STATE("GPIO25_Y4", in_nopull, - "stm", "ape_microsd"), /* dat0 */ - DB8500_PIN_STATE("GPIO26_Y2", in_nopull, - "stm", "ape_microsd"), /* dat1 */ - DB8500_PIN_STATE("GPIO27_AA2", in_nopull, - "stm", "ape_microsd"), /* dat2 */ - DB8500_PIN_STATE("GPIO28_AA1", in_nopull, - "stm", "ape_microsd"), /* dat3 */ - - DB8500_PIN_STATE("GPIO23_AA4", slpm_out_lo_wkup_pdis, - "stm", "ape_microsd_sleep"), /* clk */ - DB8500_PIN_STATE("GPIO25_Y4", slpm_in_wkup_pdis, - "stm", "ape_microsd_sleep"), /* dat0 */ - DB8500_PIN_STATE("GPIO26_Y2", slpm_in_wkup_pdis, - "stm", "ape_microsd_sleep"), /* dat1 */ - DB8500_PIN_STATE("GPIO27_AA2", slpm_in_wkup_pdis, - "stm", "ape_microsd_sleep"), /* dat2 */ - DB8500_PIN_STATE("GPIO28_AA1", slpm_in_wkup_pdis, - "stm", "ape_microsd_sleep"), /* dat3 */ - - /* STM Modem pins states */ - DB8500_MUX_STATE("stmmod_oc3_2", "stmmod", - "stm", "mod_mipi34"), - DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod", - "stm", "mod_mipi34"), - DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod", - "stm", "mod_mipi34"), - DB8500_PIN_STATE("GPIO70_G5", in_nopull, - "stm", "mod_mipi34"), /* clk */ - DB8500_PIN_STATE("GPIO71_G4", in_nopull, - "stm", "mod_mipi34"), /* dat3 */ - DB8500_PIN_STATE("GPIO72_H4", in_nopull, - "stm", "mod_mipi34"), /* dat2 */ - DB8500_PIN_STATE("GPIO73_H3", in_nopull, - "stm", "mod_mipi34"), /* dat1 */ - DB8500_PIN_STATE("GPIO74_J3", in_nopull, - "stm", "mod_mipi34"), /* dat0 */ - DB8500_PIN_STATE("GPIO75_H2", in_pu, - "stm", "mod_mipi34"), /* uartmod rx */ - DB8500_PIN_STATE("GPIO76_J2", out_lo, - "stm", "mod_mipi34"), /* uartmod tx */ - - DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis, - "stm", "mod_mipi34_sleep"), /* clk */ - DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis, - "stm", "mod_mipi34_sleep"), /* dat3 */ - DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis, - "stm", "mod_mipi34_sleep"), /* dat2 */ - DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis, - "stm", "mod_mipi34_sleep"), /* dat1 */ - DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis, - "stm", "mod_mipi34_sleep"), /* dat0 */ - DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis, - "stm", "mod_mipi34_sleep"), /* uartmod rx */ - DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis, - "stm", "mod_mipi34_sleep"), /* uartmod tx */ - - DB8500_MUX_STATE("stmmod_b_1", "stmmod", - "stm", "mod_microsd"), - DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod", - "stm", "mod_microsd"), - DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod", - "stm", "mod_microsd"), - DB8500_PIN_STATE("GPIO23_AA4", in_nopull, - "stm", "mod_microsd"), /* clk */ - DB8500_PIN_STATE("GPIO25_Y4", in_nopull, - "stm", "mod_microsd"), /* dat0 */ - DB8500_PIN_STATE("GPIO26_Y2", in_nopull, - "stm", "mod_microsd"), /* dat1 */ - DB8500_PIN_STATE("GPIO27_AA2", in_nopull, - "stm", "mod_microsd"), /* dat2 */ - DB8500_PIN_STATE("GPIO28_AA1", in_nopull, - "stm", "mod_microsd"), /* dat3 */ - DB8500_PIN_STATE("GPIO75_H2", in_pu, - "stm", "mod_microsd"), /* uartmod rx */ - DB8500_PIN_STATE("GPIO76_J2", out_lo, - "stm", "mod_microsd"), /* uartmod tx */ - - DB8500_PIN_STATE("GPIO23_AA4", slpm_out_lo_wkup_pdis, - "stm", "mod_microsd_sleep"), /* clk */ - DB8500_PIN_STATE("GPIO25_Y4", slpm_in_wkup_pdis, - "stm", "mod_microsd_sleep"), /* dat0 */ - DB8500_PIN_STATE("GPIO26_Y2", slpm_in_wkup_pdis, - "stm", "mod_microsd_sleep"), /* dat1 */ - DB8500_PIN_STATE("GPIO27_AA2", slpm_in_wkup_pdis, - "stm", "mod_microsd_sleep"), /* dat2 */ - DB8500_PIN_STATE("GPIO28_AA1", slpm_in_wkup_pdis, - "stm", "mod_microsd_sleep"), /* dat3 */ - DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis, - "stm", "mod_microsd_sleep"), /* uartmod rx */ - DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis, - "stm", "mod_microsd_sleep"), /* uartmod tx */ - - /* STM dual Modem/APE pins state */ - DB8500_MUX_STATE("stmmod_oc3_2", "stmmod", - "stm", "mod_mipi34_ape_mipi60"), - DB8500_MUX_STATE("stmape_c_2", "stmape", - "stm", "mod_mipi34_ape_mipi60"), - DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod", - "stm", "mod_mipi34_ape_mipi60"), - DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod", - "stm", "mod_mipi34_ape_mipi60"), - DB8500_PIN_STATE("GPIO70_G5", in_nopull, - "stm", "mod_mipi34_ape_mipi60"), /* clk */ - DB8500_PIN_STATE("GPIO71_G4", in_nopull, - "stm", "mod_mipi34_ape_mipi60"), /* dat3 */ - DB8500_PIN_STATE("GPIO72_H4", in_nopull, - "stm", "mod_mipi34_ape_mipi60"), /* dat2 */ - DB8500_PIN_STATE("GPIO73_H3", in_nopull, - "stm", "mod_mipi34_ape_mipi60"), /* dat1 */ - DB8500_PIN_STATE("GPIO74_J3", in_nopull, - "stm", "mod_mipi34_ape_mipi60"), /* dat0 */ - DB8500_PIN_STATE("GPIO75_H2", in_pu, - "stm", "mod_mipi34_ape_mipi60"), /* uartmod rx */ - DB8500_PIN_STATE("GPIO76_J2", out_lo, - "stm", "mod_mipi34_ape_mipi60"), /* uartmod tx */ - DB8500_PIN_STATE("GPIO155_C19", in_nopull, - "stm", "mod_mipi34_ape_mipi60"), /* clk */ - DB8500_PIN_STATE("GPIO156_C17", in_nopull, - "stm", "mod_mipi34_ape_mipi60"), /* dat3 */ - DB8500_PIN_STATE("GPIO157_A18", in_nopull, - "stm", "mod_mipi34_ape_mipi60"), /* dat2 */ - DB8500_PIN_STATE("GPIO158_C18", in_nopull, - "stm", "mod_mipi34_ape_mipi60"), /* dat1 */ - DB8500_PIN_STATE("GPIO159_B19", in_nopull, - "stm", "mod_mipi34_ape_mipi60"), /* dat0 */ - - DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis, - "stm", "mod_mipi34_ape_mipi60_sleep"), /* clk */ - DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis, - "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat3 */ - DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis, - "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat2 */ - DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis, - "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat1 */ - DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis, - "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat0 */ - DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis, - "stm", "mod_mipi34_ape_mipi60_sleep"), /* uartmod rx */ - DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis, - "stm", "mod_mipi34_ape_mipi60_sleep"), /* uartmod tx */ - DB8500_PIN_STATE("GPIO155_C19", slpm_in_wkup_pdis, - "stm", "mod_mipi34_ape_mipi60_sleep"), /* clk */ - DB8500_PIN_STATE("GPIO156_C17", slpm_in_wkup_pdis, - "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat3 */ - DB8500_PIN_STATE("GPIO157_A18", slpm_in_wkup_pdis, - "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat2 */ - DB8500_PIN_STATE("GPIO158_C18", slpm_in_wkup_pdis, - "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat1 */ - DB8500_PIN_STATE("GPIO159_B19", slpm_in_wkup_pdis, - "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat0 */ -}; - /* * These are specifically for the MOP500 and HREFP (pre-v60) version of the * board, which utilized a TC35892 GPIO expander instead of using a lot of @@ -690,8 +496,6 @@ static void __init mop500_href_family_pinmaps_init(void) void __init mop500_pinmaps_init(void) { - pinctrl_register_mappings(mop500_family_pinmap, - ARRAY_SIZE(mop500_family_pinmap)); pinctrl_register_mappings(mop500_pinmap, ARRAY_SIZE(mop500_pinmap)); mop500_href_family_pinmaps_init(); @@ -705,8 +509,6 @@ void __init mop500_pinmaps_init(void) void __init snowball_pinmaps_init(void) { - pinctrl_register_mappings(mop500_family_pinmap, - ARRAY_SIZE(mop500_family_pinmap)); pinctrl_register_mappings(snowball_pinmap, ARRAY_SIZE(snowball_pinmap)); pinctrl_register_mappings(u8500_pinmap, @@ -717,8 +519,6 @@ void __init snowball_pinmaps_init(void) void __init hrefv60_pinmaps_init(void) { - pinctrl_register_mappings(mop500_family_pinmap, - ARRAY_SIZE(mop500_family_pinmap)); pinctrl_register_mappings(hrefv60_pinmap, ARRAY_SIZE(hrefv60_pinmap)); mop500_href_family_pinmaps_init(); -- cgit v1.1 From 3ae2750a8c7112b83697dda5ef915886cb2a38cf Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 15 Nov 2013 10:07:48 +0100 Subject: ARM: ux500: move old HREF ipgpio to the device tree The old HREFs (MOP500) were controlling an image-processor GPIO (IPGPIO) by using hogs. Do the same thing with device tree and get rid of the mop500_pins setting. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-hrefprev60.dtsi | 16 ++++++++++++++++ arch/arm/mach-ux500/board-mop500-pins.c | 24 ------------------------ 2 files changed, 16 insertions(+), 24 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/ste-hrefprev60.dtsi b/arch/arm/boot/dts/ste-hrefprev60.dtsi index 32295e3..b0f5def 100644 --- a/arch/arm/boot/dts/ste-hrefprev60.dtsi +++ b/arch/arm/boot/dts/ste-hrefprev60.dtsi @@ -68,6 +68,10 @@ }; pinctrl { + /* Set this up using hogs */ + pinctrl-names = "default"; + pinctrl-0 = <&ipgpio_hrefprev60_mode>; + ssp0 { ssp0_hrefprev60_mode: ssp0_hrefprev60_default { hrefprev60_mux { @@ -103,6 +107,18 @@ }; }; }; + ipgpio { + ipgpio_hrefprev60_mode: ipgpio_hrefprev60 { + hrefprev60_mux { + ste,function = "ipgpio"; + ste,pins = "ipgpio0_c_1", "ipgpio1_c_1"; + }; + hrefprev60_cfg1 { + ste,pins = "GPIO6_AF6", "GPIO7_AG5"; + ste,config = <&in_pu>; + }; + }; + }; }; }; }; diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c index c311d11..257c97a 100644 --- a/arch/arm/mach-ux500/board-mop500-pins.c +++ b/arch/arm/mach-ux500/board-mop500-pins.c @@ -312,28 +312,6 @@ static struct pinctrl_map __initdata ab8505_pinmap[] = { }; /* - * These are specifically for the MOP500 and HREFP (pre-v60) version of the - * board, which utilized a TC35892 GPIO expander instead of using a lot of - * on-chip pins as the HREFv60 and later does. - */ -static struct pinctrl_map __initdata mop500_pinmap[] = { - /* - * XENON Flashgun on image processor GPIO (controlled from image - * processor firmware), mux in these image processor GPIO lines 0 - * (XENON_FLASH_ID) and 1 (XENON_READY) on altfunction C and pull up - * the pins. - */ - DB8500_MUX_HOG("ipgpio0_c_1", "ipgpio"), - DB8500_MUX_HOG("ipgpio1_c_1", "ipgpio"), - DB8500_PIN_HOG("GPIO6_AF6", in_pu), - DB8500_PIN_HOG("GPIO7_AG5", in_pu), - /* - * Runtime stuff: make it possible to mux in the SKE keypad - * and bias the pins - */ -}; - -/* * The HREFv60 series of platforms is using available pins on the DB8500 * insteaf of the Toshiba I2C GPIO expander, reusing some pins like the SSP0 * and SSP1 ports (previously connected to the AB8500) as generic GPIO lines. @@ -496,8 +474,6 @@ static void __init mop500_href_family_pinmaps_init(void) void __init mop500_pinmaps_init(void) { - pinctrl_register_mappings(mop500_pinmap, - ARRAY_SIZE(mop500_pinmap)); mop500_href_family_pinmaps_init(); if (machine_is_u8520()) pinctrl_register_mappings(ab8505_pinmap, -- cgit v1.1 From 1a780d45b10eb904be6a923fa09365255b5e733b Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 15 Nov 2013 13:43:02 +0100 Subject: ARM: ux500: move GPIO key configuration to device tree This moves over the configuration of the GPIO keys (used for proximity sensor and Hall effect sensor) from the static pin configuration file to the device tree. As part of the exercise, implement the GPIO keys properly in a per-UIB file as this setup actually differs with each UIB. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-href-stuib.dtsi | 41 ++++++++++++++++++++++++++++++ arch/arm/boot/dts/ste-href-tvk1281618.dtsi | 38 +++++++++++++++++++++++++++ arch/arm/boot/dts/ste-href.dtsi | 11 -------- arch/arm/boot/dts/ste-hrefv60plus.dtsi | 6 ----- arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi | 5 ++++ arch/arm/mach-ux500/board-mop500-pins.c | 8 ------ 6 files changed, 84 insertions(+), 25 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/ste-href-stuib.dtsi b/arch/arm/boot/dts/ste-href-stuib.dtsi index 76704ec..1c35744 100644 --- a/arch/arm/boot/dts/ste-href-stuib.dtsi +++ b/arch/arm/boot/dts/ste-href-stuib.dtsi @@ -12,6 +12,28 @@ #include / { + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + vdd-supply = <&ab8500_ldo_aux1_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&prox_stuib_mode>, <&hall_stuib_mode>; + + button@139 { + /* Proximity sensor */ + gpios = <&gpio6 25 0x4>; + linux,code = <11>; /* SW_FRONT_PROXIMITY */ + label = "SFH7741 Proximity Sensor"; + }; + button@145 { + /* Hall sensor */ + gpios = <&gpio4 17 0x4>; + linux,code = <0>; /* SW_LID */ + label = "HED54XXU11 Hall Effect Sensor"; + }; + }; + soc { i2c@80004000 { stmpe1601: stmpe1601@40 { @@ -74,5 +96,24 @@ rohm,flip-y; }; }; + + pinctrl { + prox { + prox_stuib_mode: prox_stuib { + stuib_cfg { + ste,pins = "GPIO217_AH12"; + ste,config = <&gpio_in_pu>; + }; + }; + }; + hall { + hall_stuib_mode: stuib_tvk { + stuib_cfg { + ste,pins = "GPIO145_C13"; + ste,config = <&gpio_in_pu>; + }; + }; + }; + }; }; }; diff --git a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi index 3f31f92..c405653 100644 --- a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi +++ b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi @@ -14,6 +14,28 @@ #include / { + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + vdd-supply = <&ab8500_ldo_aux1_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&prox_tvk_mode>, <&hall_tvk_mode>; + + button@139 { + /* Proximity sensor */ + gpios = <&gpio6 25 0x4>; + linux,code = <11>; /* SW_FRONT_PROXIMITY */ + label = "SFH7741 Proximity Sensor"; + }; + button@145 { + /* Hall sensor */ + gpios = <&gpio4 17 0x4>; + linux,code = <0>; /* SW_LID */ + label = "HED54XXU11 Hall Effect Sensor"; + }; + }; + soc { /* Add Synaptics touch screen, TC35893 keypad etc here */ i2c@80004000 { @@ -76,6 +98,22 @@ }; }; }; + prox { + prox_tvk_mode: prox_tvk { + tvk_cfg { + ste,pins = "GPIO217_AH12"; + ste,config = <&gpio_in_pu>; + }; + }; + }; + hall { + hall_tvk_mode: hall_tvk { + tvk_cfg { + ste,pins = "GPIO145_C13"; + ste,config = <&gpio_in_pu>; + }; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi index 56772c3..e282421 100644 --- a/arch/arm/boot/dts/ste-href.dtsi +++ b/arch/arm/boot/dts/ste-href.dtsi @@ -18,17 +18,6 @@ reg = <0x00000000 0x20000000>; }; - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - button@1 { - linux,code = <11>; - label = "SFH7741 Proximity Sensor"; - }; - }; - soc { usb_per5@a03e0000 { pinctrl-names = "default", "sleep"; diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dtsi b/arch/arm/boot/dts/ste-hrefv60plus.dtsi index 452f00c..6e0105d 100644 --- a/arch/arm/boot/dts/ste-hrefv60plus.dtsi +++ b/arch/arm/boot/dts/ste-hrefv60plus.dtsi @@ -16,12 +16,6 @@ model = "ST-Ericsson HREF (v60+) platform with Device Tree"; compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500"; - gpio_keys { - button@1 { - gpios = <&gpio5 25 0x4>; - }; - }; - soc { // External Micro SD slot sdi0_per1@80126000 { diff --git a/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi b/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi index ee143b0..e6f22b2 100644 --- a/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi +++ b/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi @@ -36,6 +36,11 @@ ste,input = ; }; + gpio_in_pd: gpio_input_pull_down { + ste,gpio = ; + ste,input = ; + }; + gpio_out_lo: gpio_output_low { ste,gpio = ; ste,output = ; diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c index 257c97a..4535702 100644 --- a/arch/arm/mach-ux500/board-mop500-pins.c +++ b/arch/arm/mach-ux500/board-mop500-pins.c @@ -382,14 +382,6 @@ static struct pinctrl_map __initdata hrefv60_pinmap[] = { /* Accelerometer interrupt lines */ DB8500_PIN_HOG("GPIO82_C1", gpio_in_pu), /* ACC_INT1 */ DB8500_PIN_HOG("GPIO83_D3", gpio_in_pu), /* ACC_INT2 */ - /* - * Runtime stuff - * Pull up/down of some sensor GPIO pins, for proximity, HAL sensor - * etc. - */ - DB8500_PIN("GPIO217_AH12", gpio_in_pu_slpm_gpio_nopull, "gpio-keys.0"), - DB8500_PIN("GPIO145_C13", gpio_in_pd_slpm_gpio_nopull, "gpio-keys.0"), - DB8500_PIN("GPIO139_C9", gpio_in_pu_slpm_gpio_nopull, "gpio-keys.0"), }; static struct pinctrl_map __initdata u9500_pinmap[] = { -- cgit v1.1 From 5026119fbef49ce64fc5469c5d3c2d7c313469fb Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 15 Nov 2013 14:06:00 +0100 Subject: ARM: ux500: move the WLAN GPIO pin setup to the device tree This moves some of the pin setup related to the CW1200 WLAN module over to the device tree. As the driver is not yet activated for the CW1200 WLAN we do not assign this pinctrl state to any device node yet. Get rid of the cmdline argument passing of a certain U9500 platform variant, as this is not supported by the kernel or any device tree. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-href-family-pinctrl.dtsi | 19 +++++++ arch/arm/mach-ux500/board-mop500-pins.c | 75 -------------------------- 2 files changed, 19 insertions(+), 75 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi index 854a4a6..addfcc7 100644 --- a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi +++ b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi @@ -721,6 +721,25 @@ }; }; }; + + wlan { + wlan_default_mode: wlan_default { + /* + * Activate this mode with the WLAN chip. + * These are plain GPIO pins used by WLAN + */ + default_cfg1 { + ste,pins = + "GPIO226_AF8", /* WLAN_PMU_EN */ + "GPIO85_D5"; /* WLAN_ENA */ + ste,config = <&gpio_out_lo>; + }; + default_cfg2 { + ste,pins = "GPIO4_AH6"; /* WLAN_IRQ on UART1 */ + ste,config = <&gpio_in_pu>; + }; + }; + }; }; }; }; diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c index 4535702..d0d527a 100644 --- a/arch/arm/mach-ux500/board-mop500-pins.c +++ b/arch/arm/mach-ux500/board-mop500-pins.c @@ -16,19 +16,11 @@ #include "board-mop500.h" -enum custom_pin_cfg_t { - PINS_FOR_DEFAULT, - PINS_FOR_U9500, -}; - -static enum custom_pin_cfg_t pinsfor; - /* These simply sets bias for pins */ #define BIAS(a,b) static unsigned long a[] = { b } BIAS(pd, PIN_PULL_DOWN); BIAS(in_pu, PIN_INPUT_PULLUP); -BIAS(in_pd, PIN_INPUT_PULLDOWN); BIAS(out_lo, PIN_OUTPUT_LOW); BIAS(abx500_out_lo, PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0)); @@ -38,8 +30,6 @@ BIAS(abx500_in_nopull, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 0)); /* These also force them into GPIO mode */ BIAS(gpio_in_pu, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED); BIAS(gpio_in_pd, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED); -BIAS(gpio_in_pu_slpm_gpio_nopull, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL); -BIAS(gpio_in_pd_slpm_gpio_nopull, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL); BIAS(gpio_out_hi, PIN_OUTPUT_HIGH|PIN_GPIOMODE_ENABLED); BIAS(gpio_out_lo, PIN_OUTPUT_LOW|PIN_GPIOMODE_ENABLED); @@ -317,8 +307,6 @@ static struct pinctrl_map __initdata ab8505_pinmap[] = { * and SSP1 ports (previously connected to the AB8500) as generic GPIO lines. */ static struct pinctrl_map __initdata hrefv60_pinmap[] = { - /* Drive WLAN_ENA low */ - DB8500_PIN_HOG("GPIO85_D5", gpio_out_lo), /* WLAN_ENA */ /* * XENON Flashgun on image processor GPIO (controlled from image * processor firmware), mux in these image processor GPIO lines 0 @@ -384,27 +372,6 @@ static struct pinctrl_map __initdata hrefv60_pinmap[] = { DB8500_PIN_HOG("GPIO83_D3", gpio_in_pu), /* ACC_INT2 */ }; -static struct pinctrl_map __initdata u9500_pinmap[] = { - /* WLAN_IRQ line */ - DB8500_PIN_HOG("GPIO144_B13", gpio_in_pu), - /* HSI */ - DB8500_MUX_HOG("hsir_a_1", "hsi"), - DB8500_MUX_HOG("hsit_a_2", "hsi"), - DB8500_PIN_HOG("GPIO219_AG10", in_pd), /* RX FLA0 */ - DB8500_PIN_HOG("GPIO220_AH10", in_pd), /* RX DAT0 */ - DB8500_PIN_HOG("GPIO221_AJ11", out_lo), /* RX RDY0 */ - DB8500_PIN_HOG("GPIO222_AJ9", out_lo), /* TX FLA0 */ - DB8500_PIN_HOG("GPIO223_AH9", out_lo), /* TX DAT0 */ - DB8500_PIN_HOG("GPIO224_AG9", in_pd), /* TX RDY0 */ - DB8500_PIN_HOG("GPIO225_AG8", in_pd), /* CAWAKE0 */ - DB8500_PIN_HOG("GPIO226_AF8", gpio_out_hi), /* ACWAKE0 */ -}; - -static struct pinctrl_map __initdata u8500_pinmap[] = { - DB8500_PIN_HOG("GPIO226_AF8", gpio_out_lo), /* WLAN_PMU_EN */ - DB8500_PIN_HOG("GPIO4_AH6", gpio_in_pu), /* WLAN_IRQ */ -}; - static struct pinctrl_map __initdata snowball_pinmap[] = { /* Mux in SSP0 connected to AB8500, pull down RXD pin */ DB8500_MUX_HOG("ssp0_a_1", "ssp0"), @@ -426,47 +393,8 @@ static struct pinctrl_map __initdata snowball_pinmap[] = { DB8500_PIN_HOG("GPIO216_AG12", gpio_in_pu), /* WLAN_IRQ */ }; -/* - * passing "pinsfor=" in kernel cmdline allows for custom - * configuration of GPIOs on u8500 derived boards. - */ -static int __init early_pinsfor(char *p) -{ - pinsfor = PINS_FOR_DEFAULT; - - if (strcmp(p, "u9500-21") == 0) - pinsfor = PINS_FOR_U9500; - - return 0; -} -early_param("pinsfor", early_pinsfor); - -int pins_for_u9500(void) -{ - if (pinsfor == PINS_FOR_U9500) - return 1; - - return 0; -} - -static void __init mop500_href_family_pinmaps_init(void) -{ - switch (pinsfor) { - case PINS_FOR_U9500: - pinctrl_register_mappings(u9500_pinmap, - ARRAY_SIZE(u9500_pinmap)); - break; - case PINS_FOR_DEFAULT: - pinctrl_register_mappings(u8500_pinmap, - ARRAY_SIZE(u8500_pinmap)); - default: - break; - } -} - void __init mop500_pinmaps_init(void) { - mop500_href_family_pinmaps_init(); if (machine_is_u8520()) pinctrl_register_mappings(ab8505_pinmap, ARRAY_SIZE(ab8505_pinmap)); @@ -479,8 +407,6 @@ void __init snowball_pinmaps_init(void) { pinctrl_register_mappings(snowball_pinmap, ARRAY_SIZE(snowball_pinmap)); - pinctrl_register_mappings(u8500_pinmap, - ARRAY_SIZE(u8500_pinmap)); pinctrl_register_mappings(ab8500_pinmap, ARRAY_SIZE(ab8500_pinmap)); } @@ -489,7 +415,6 @@ void __init hrefv60_pinmaps_init(void) { pinctrl_register_mappings(hrefv60_pinmap, ARRAY_SIZE(hrefv60_pinmap)); - mop500_href_family_pinmaps_init(); pinctrl_register_mappings(ab8500_pinmap, ARRAY_SIZE(ab8500_pinmap)); } -- cgit v1.1 From 1c850e4a8ff518eb7877772755a1237b85c2fac7 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 15 Nov 2013 14:44:59 +0100 Subject: ARM: ux500: move the HREFv60plus IPGPIO pins to device tree Move the control of muxing and enabling the IPGPIO (image processor GPIO) from the static set-up to the device tree. Use a hog as we have no device for the flash controller yet. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-hrefv60plus.dtsi | 31 +++++++++++++++++++++++++++++++ arch/arm/mach-ux500/board-mop500-pins.c | 16 ---------------- 2 files changed, 31 insertions(+), 16 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dtsi b/arch/arm/boot/dts/ste-hrefv60plus.dtsi index 6e0105d..ecd2684 100644 --- a/arch/arm/boot/dts/ste-hrefv60plus.dtsi +++ b/arch/arm/boot/dts/ste-hrefv60plus.dtsi @@ -62,6 +62,10 @@ }; pinctrl { + /* Set this up using hogs */ + pinctrl-names = "default"; + pinctrl-0 = <&ipgpio_hrefv60_mode>; + sdi0 { /* SD card detect GPIO pin, extend default state */ sdi0_default_mode: sdi0_default { @@ -71,6 +75,33 @@ }; }; }; + ipgpio { + /* + * XENON Flashgun on image processor GPIO (controlled from image + * processor firmware), mux in these image processor GPIO lines 0 + * (XENON_FLASH_ID), 1 (XENON_READY) and there is an assistant + * LED on IP GPIO 4 (XENON_EN2) on altfunction C, that need bias + * from GPIO21 so pull up 0, 1 and drive 4 and GPIO21 low as output. + */ + ipgpio_hrefv60_mode: ipgpio_hrefv60 { + hrefv60_mux { + ste,function = "ipgpio"; + ste,pins = "ipgpio0_c_1", "ipgpio1_c_1", "ipgpio4_c_1"; + }; + hrefv60_cfg1 { + ste,pins = "GPIO6_AF6", "GPIO7_AG5"; + ste,config = <&in_pu>; + }; + hrefv60_cfg2 { + ste,pins = "GPIO21_AB3"; + ste,config = <&gpio_out_lo>; + }; + hrefv60_cfg3 { + ste,pins = "GPIO64_F3"; + ste,config = <&out_lo>; + }; + }; + }; }; }; }; diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c index d0d527a..e208ddd 100644 --- a/arch/arm/mach-ux500/board-mop500-pins.c +++ b/arch/arm/mach-ux500/board-mop500-pins.c @@ -20,8 +20,6 @@ #define BIAS(a,b) static unsigned long a[] = { b } BIAS(pd, PIN_PULL_DOWN); -BIAS(in_pu, PIN_INPUT_PULLUP); -BIAS(out_lo, PIN_OUTPUT_LOW); BIAS(abx500_out_lo, PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0)); BIAS(abx500_in_pd, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 1)); @@ -307,20 +305,6 @@ static struct pinctrl_map __initdata ab8505_pinmap[] = { * and SSP1 ports (previously connected to the AB8500) as generic GPIO lines. */ static struct pinctrl_map __initdata hrefv60_pinmap[] = { - /* - * XENON Flashgun on image processor GPIO (controlled from image - * processor firmware), mux in these image processor GPIO lines 0 - * (XENON_FLASH_ID), 1 (XENON_READY) and there is an assistant - * LED on IP GPIO 4 (XENON_EN2) on altfunction C, that need bias - * from GPIO21 so pull up 0, 1 and drive 4 and GPIO21 low as output. - */ - DB8500_MUX_HOG("ipgpio0_c_1", "ipgpio"), - DB8500_MUX_HOG("ipgpio1_c_1", "ipgpio"), - DB8500_MUX_HOG("ipgpio4_c_1", "ipgpio"), - DB8500_PIN_HOG("GPIO6_AF6", in_pu), /* XENON_FLASH_ID */ - DB8500_PIN_HOG("GPIO7_AG5", in_pu), /* XENON_READY */ - DB8500_PIN_HOG("GPIO21_AB3", gpio_out_lo), /* XENON_EN1 */ - DB8500_PIN_HOG("GPIO64_F3", out_lo), /* XENON_EN2 */ /* Magnetometer uses GPIO 31 and 32, pull these up/down respectively */ DB8500_PIN_HOG("GPIO31_V3", gpio_in_pu), /* EN1 */ DB8500_PIN_HOG("GPIO32_V2", gpio_in_pd), /* DRDY */ -- cgit v1.1 From 17afa716e63453f5ac7e24370dae38d1e8c7cac2 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 15 Nov 2013 14:55:30 +0100 Subject: ARM: ux500: move final HREFv60 LCD pins to device tree Put two extra configs into the device tree to handle the default configuration of the display reset signals on the HREFv60plus, move this over from the board file to the device tree. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-hrefv60plus.dtsi | 17 +++++++++++++++++ arch/arm/mach-ux500/board-mop500-pins.c | 7 ------- 2 files changed, 17 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dtsi b/arch/arm/boot/dts/ste-hrefv60plus.dtsi index ecd2684..25b4848 100644 --- a/arch/arm/boot/dts/ste-hrefv60plus.dtsi +++ b/arch/arm/boot/dts/ste-hrefv60plus.dtsi @@ -102,6 +102,23 @@ }; }; }; + mcde { + lcd_hrefv60_mode: lcd_hrefv60 { + /* + * Display Interface 1 uses GPIO 65 for RST (reset). + * Display Interface 2 uses GPIO 66 for RST (reset). + * Drive DISP1 reset high (not reset), driver DISP2 reset low (reset) + */ + hrefv60_cfg1 { + ste,pins ="GPIO65_F1"; + ste,config = <&gpio_out_hi>; + }; + hrefv60_cfg2 { + ste,pins ="GPIO66_G3"; + ste,config = <&gpio_out_lo>; + }; + }; + }; }; }; }; diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c index e208ddd..6cc71d0 100644 --- a/arch/arm/mach-ux500/board-mop500-pins.c +++ b/arch/arm/mach-ux500/board-mop500-pins.c @@ -309,13 +309,6 @@ static struct pinctrl_map __initdata hrefv60_pinmap[] = { DB8500_PIN_HOG("GPIO31_V3", gpio_in_pu), /* EN1 */ DB8500_PIN_HOG("GPIO32_V2", gpio_in_pd), /* DRDY */ /* - * Display Interface 1 uses GPIO 65 for RST (reset). - * Display Interface 2 uses GPIO 66 for RST (reset). - * Drive DISP1 reset high (not reset), driver DISP2 reset low (reset) - */ - DB8500_PIN_HOG("GPIO65_F1", gpio_out_hi), /* DISP1 NO RST */ - DB8500_PIN_HOG("GPIO66_G3", gpio_out_lo), /* DISP2 RST */ - /* * Touch screen uses GPIO 143 for RST1, GPIO 146 for RST2 and * GPIO 67 for interrupts. Pull-up the IRQ line and drive both * reset signals low. -- cgit v1.1 From 7ab05bd165873f8561c15fbcce5b1edc55314c83 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 15 Nov 2013 15:50:11 +0100 Subject: ARM: ux500: move HREFv60plus pin configs to device tree Move the few remaining HREFv60 pin configurations to the device tree, reference these as hogs to the pin controller until there are real devices that can make use of them. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-hrefv60plus.dtsi | 155 +++++++++++++++++++++++++++++++- arch/arm/mach-ux500/board-mop500-pins.c | 53 ----------- 2 files changed, 153 insertions(+), 55 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dtsi b/arch/arm/boot/dts/ste-hrefv60plus.dtsi index 25b4848..941bf9a 100644 --- a/arch/arm/boot/dts/ste-hrefv60plus.dtsi +++ b/arch/arm/boot/dts/ste-hrefv60plus.dtsi @@ -62,9 +62,23 @@ }; pinctrl { - /* Set this up using hogs */ + /* + * Set this up using hogs, as time goes by and as seems fit, these + * can be moved over to being controlled by respective device. + */ pinctrl-names = "default"; - pinctrl-0 = <&ipgpio_hrefv60_mode>; + pinctrl-0 = <&ipgpio_hrefv60_mode>, + <&accel_hrefv60_mode>, + <&magneto_hrefv60_mode>, + <&etm_hrefv60_mode>, + <&nahj_hrefv60_mode>, + <&nfc_hrefv60_mode>, + <&force_hrefv60_mode>, + <&dipro_hrefv60_mode>, + <&vaudio_hf_hrefv60_mode>, + <&gbf_hrefv60_mode>, + <&hdtv_hrefv60_mode>, + <&touch_hrefv60_mode>; sdi0 { /* SD card detect GPIO pin, extend default state */ @@ -100,8 +114,145 @@ ste,pins = "GPIO64_F3"; ste,config = <&out_lo>; }; + }; + }; + accelerometer { + accel_hrefv60_mode: accel_hrefv60 { + /* Accelerometer interrupt lines 1 & 2 */ + hrefv60_cfg1 { + ste,pins = "GPIO82_C1", "GPIO83_D3"; + ste,config = <&gpio_in_pu>; + }; + }; + }; + magnetometer { + magneto_hrefv60_mode: magneto_hrefv60 { + /* Magnetometer uses GPIO 31 and 32, pull these up/down respectively */ + hrefv60_cfg1 { + ste,pins = "GPIO31_V3"; + ste,config = <&gpio_in_pu>; + }; + hrefv60_cfg2 { + ste,pins = "GPIO32_V2"; + ste,config = <&gpio_in_pd>; + }; + }; + }; + etm { + /* + * Drive D19-D23 for the ETM PTM trace interface low, + * (presumably pins are unconnected therefore grounded here, + * the "other alt C1" setting enables these pins) + */ + etm_hrefv60_mode: etm_hrefv60 { + hrefv60_cfg1 { + ste,pins = + "GPIO70_G5", + "GPIO71_G4", + "GPIO72_H4", + "GPIO73_H3", + "GPIO74_J3"; + ste,config = <&gpio_out_lo>; + }; }; }; + nahj { + nahj_hrefv60_mode: nahj_hrefv60 { + /* NAHJ CTRL on GPIO76 to low, CTRL_INV on GPIO216 to high */ + hrefv60_cfg1 { + ste,pins = "GPIO76_J2"; + ste,config = <&gpio_out_lo>; + }; + hrefv60_cfg2 { + ste,pins = "GPIO216_AG12"; + ste,config = <&gpio_out_hi>; + }; + }; + }; + nfc { + nfc_hrefv60_mode: nfc_hrefv60 { + /* NFC ENA and RESET to low, pulldown IRQ line */ + hrefv60_cfg1 { + ste,pins = + "GPIO77_H1", /* NFC_ENA */ + "GPIO142_C11"; /* NFC_RESET */ + ste,config = <&gpio_out_lo>; + }; + hrefv60_cfg2 { + ste,pins = "GPIO144_B13"; /* NFC_IRQ */ + ste,config = <&gpio_in_pd>; + }; + }; + }; + force { + force_hrefv60_mode: force_hrefv60 { + hrefv60_cfg1 { + ste,pins = "GPIO91_B6"; /* FORCE_SENSING_INT */ + ste,config = <&gpio_in_pu>; + }; + hrefv60_cfg2 { + ste,pins = + "GPIO92_D6", /* FORCE_SENSING_RST */ + "GPIO97_D9"; /* FORCE_SENSING_WU */ + ste,config = <&gpio_out_lo>; + }; + }; + }; + dipro { + dipro_hrefv60_mode: dipro_hrefv60 { + hrefv60_cfg1 { + ste,pins = "GPIO139_C9"; /* DIPRO_INT */ + ste,config = <&gpio_in_pu>; + }; + }; + }; + vaudio_hf { + vaudio_hf_hrefv60_mode: vaudio_hf_hrefv60 { + /* Audio Amplifier HF enable GPIO */ + hrefv60_cfg1 { + ste,pins = "GPIO149_B14"; /* VAUDIO_HF_EN, enable MAX8968 */ + ste,config = <&gpio_out_hi>; + }; + }; + }; + gbf { + gbf_hrefv60_mode: gbf_hrefv60 { + /* + * GBF (GPS, Bluetooth, FM-radio) interface, + * pull low to reset state + */ + hrefv60_cfg1 { + ste,pins = "GPIO171_D23"; /* GBF_ENA_RESET */ + ste,config = <&gpio_out_lo>; + }; + }; + }; + hdtv { + hdtv_hrefv60_mode: hdtv_hrefv60 { + /* MSP : HDTV INTERFACE GPIO line */ + hrefv60_cfg1 { + ste,pins = "GPIO192_AJ27"; + ste,config = <&gpio_in_pd>; + }; + }; + }; + touch { + touch_hrefv60_mode: touch_hrefv60 { + /* + * Touch screen uses GPIO 143 for RST1, GPIO 146 for RST2 and + * GPIO 67 for interrupts. Pull-up the IRQ line and drive both + * reset signals low. + */ + hrefv60_cfg1 { + ste,pins = "GPIO143_D12", "GPIO146_D13"; + ste,config = <&gpio_out_lo>; + }; + hrefv60_cfg2 { + ste,pins = "GPIO67_G2"; + ste,config = <&gpio_in_pu>; + }; + }; + }; mcde { lcd_hrefv60_mode: lcd_hrefv60 { /* diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c index 6cc71d0..71ee944 100644 --- a/arch/arm/mach-ux500/board-mop500-pins.c +++ b/arch/arm/mach-ux500/board-mop500-pins.c @@ -27,7 +27,6 @@ BIAS(abx500_in_nopull, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 0)); /* These also force them into GPIO mode */ BIAS(gpio_in_pu, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED); -BIAS(gpio_in_pd, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED); BIAS(gpio_out_hi, PIN_OUTPUT_HIGH|PIN_GPIOMODE_ENABLED); BIAS(gpio_out_lo, PIN_OUTPUT_LOW|PIN_GPIOMODE_ENABLED); @@ -299,56 +298,6 @@ static struct pinctrl_map __initdata ab8505_pinmap[] = { AB8505_PIN_HOG("GPIO53_D15", in_pd), }; -/* - * The HREFv60 series of platforms is using available pins on the DB8500 - * insteaf of the Toshiba I2C GPIO expander, reusing some pins like the SSP0 - * and SSP1 ports (previously connected to the AB8500) as generic GPIO lines. - */ -static struct pinctrl_map __initdata hrefv60_pinmap[] = { - /* Magnetometer uses GPIO 31 and 32, pull these up/down respectively */ - DB8500_PIN_HOG("GPIO31_V3", gpio_in_pu), /* EN1 */ - DB8500_PIN_HOG("GPIO32_V2", gpio_in_pd), /* DRDY */ - /* - * Touch screen uses GPIO 143 for RST1, GPIO 146 for RST2 and - * GPIO 67 for interrupts. Pull-up the IRQ line and drive both - * reset signals low. - */ - DB8500_PIN_HOG("GPIO143_D12", gpio_out_lo), /* TOUCH_RST1 */ - DB8500_PIN_HOG("GPIO67_G2", gpio_in_pu), /* TOUCH_INT2 */ - DB8500_PIN_HOG("GPIO146_D13", gpio_out_lo), /* TOUCH_RST2 */ - /* - * Drive D19-D23 for the ETM PTM trace interface low, - * (presumably pins are unconnected therefore grounded here, - * the "other alt C1" setting enables these pins) - */ - DB8500_PIN_HOG("GPIO70_G5", gpio_out_lo), - DB8500_PIN_HOG("GPIO71_G4", gpio_out_lo), - DB8500_PIN_HOG("GPIO72_H4", gpio_out_lo), - DB8500_PIN_HOG("GPIO73_H3", gpio_out_lo), - DB8500_PIN_HOG("GPIO74_J3", gpio_out_lo), - /* NAHJ CTRL on GPIO 76 to low, CTRL_INV on GPIO216 to high */ - DB8500_PIN_HOG("GPIO76_J2", gpio_out_lo), /* CTRL */ - DB8500_PIN_HOG("GPIO216_AG12", gpio_out_hi), /* CTRL_INV */ - /* NFC ENA and RESET to low, pulldown IRQ line */ - DB8500_PIN_HOG("GPIO77_H1", gpio_out_lo), /* NFC_ENA */ - DB8500_PIN_HOG("GPIO144_B13", gpio_in_pd), /* NFC_IRQ */ - DB8500_PIN_HOG("GPIO142_C11", gpio_out_lo), /* NFC_RESET */ - DB8500_PIN_HOG("GPIO91_B6", gpio_in_pu), /* FORCE_SENSING_INT */ - DB8500_PIN_HOG("GPIO92_D6", gpio_out_lo), /* FORCE_SENSING_RST */ - DB8500_PIN_HOG("GPIO97_D9", gpio_out_lo), /* FORCE_SENSING_WU */ - /* DiPro Sensor interrupt */ - DB8500_PIN_HOG("GPIO139_C9", gpio_in_pu), /* DIPRO_INT */ - /* Audio Amplifier HF enable */ - DB8500_PIN_HOG("GPIO149_B14", gpio_out_hi), /* VAUDIO_HF_EN, enable MAX8968 */ - /* GBF interface, pull low to reset state */ - DB8500_PIN_HOG("GPIO171_D23", gpio_out_lo), /* GBF_ENA_RESET */ - /* MSP : HDTV INTERFACE GPIO line */ - DB8500_PIN_HOG("GPIO192_AJ27", gpio_in_pd), - /* Accelerometer interrupt lines */ - DB8500_PIN_HOG("GPIO82_C1", gpio_in_pu), /* ACC_INT1 */ - DB8500_PIN_HOG("GPIO83_D3", gpio_in_pu), /* ACC_INT2 */ -}; - static struct pinctrl_map __initdata snowball_pinmap[] = { /* Mux in SSP0 connected to AB8500, pull down RXD pin */ DB8500_MUX_HOG("ssp0_a_1", "ssp0"), @@ -390,8 +339,6 @@ void __init snowball_pinmaps_init(void) void __init hrefv60_pinmaps_init(void) { - pinctrl_register_mappings(hrefv60_pinmap, - ARRAY_SIZE(hrefv60_pinmap)); pinctrl_register_mappings(ab8500_pinmap, ARRAY_SIZE(ab8500_pinmap)); } -- cgit v1.1 From a48bf4b9fcf63a43e10f3c784d7349bb868ccc45 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 17 Nov 2013 10:02:22 +0100 Subject: ARM: ux500: move snowball ethernet config to device tree This transfers the muxing and biasing of the ethernet-related pins on the snowball over to the device tree. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-snowball.dts | 25 +++++++++++++++++++++++++ arch/arm/mach-ux500/board-mop500-pins.c | 4 ---- 2 files changed, 25 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts index 53febe5..4f5457a 100644 --- a/arch/arm/boot/dts/ste-snowball.dts +++ b/arch/arm/boot/dts/ste-snowball.dts @@ -130,6 +130,8 @@ interrupt-parent = <&gpio4>; vdd33a-supply = <&en_3v3_reg>; vddvario-supply = <&db8500_vape_reg>; + pinctrl-names = "default"; + pinctrl-0 = <ð_snowball_mode>; reg-shift = <1>; reg-io-width = <2>; @@ -348,6 +350,29 @@ }; pinctrl { + ethernet { + /* + * Mux in "SM" which is used for the + * SMSC911x Ethernet adapter + */ + eth_snowball_mode: eth_snowball { + snowball_mux { + ste,function = "sm"; + ste,pins = "sm_b_1"; + }; + /* LAN IRQ pin */ + snowball_cfg1 { + ste,pins = "GPIO140_B11"; + ste,config = <&in_nopull>; + }; + /* LAN reset pin */ + snowball_cfg2 { + ste,pins = "GPIO141_C12"; + ste,config = <&gpio_out_hi>; + }; + + }; + }; sdi0 { sdi0_default_mode: sdi0_default { snowball_mux { diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c index 71ee944..55da56e 100644 --- a/arch/arm/mach-ux500/board-mop500-pins.c +++ b/arch/arm/mach-ux500/board-mop500-pins.c @@ -302,12 +302,8 @@ static struct pinctrl_map __initdata snowball_pinmap[] = { /* Mux in SSP0 connected to AB8500, pull down RXD pin */ DB8500_MUX_HOG("ssp0_a_1", "ssp0"), DB8500_PIN_HOG("GPIO145_C13", pd), - /* Mux in "SM" which is used for the SMSC911x Ethernet adapter */ - DB8500_MUX_HOG("sm_b_1", "sm"), /* User LED */ DB8500_PIN_HOG("GPIO142_C11", gpio_out_hi), - /* Drive RSTn_LAN high */ - DB8500_PIN_HOG("GPIO141_C12", gpio_out_hi), /* Accelerometer/Magnetometer */ DB8500_PIN_HOG("GPIO163_C20", gpio_in_pu), /* ACCEL_IRQ1 */ DB8500_PIN_HOG("GPIO164_B21", gpio_in_pu), /* ACCEL_IRQ2 */ -- cgit v1.1 From fd8f9eac9dca386f54dfeff94afd03c84ec72ca1 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 17 Nov 2013 11:13:21 +0100 Subject: ARM: ux500: convert Snowball SPI pin reference The SPI0 block is not at all connected to the AB8500 on the Snowball: it is connected to the external header. These pins on the header may also be used for GPIO, but let's assume that SPI is a probable usecase on the Snowball and mux in the SPI block and use these for SPI. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-snowball.dts | 28 ++++++++++++++++++++++++++++ arch/arm/mach-ux500/board-mop500-pins.c | 5 ----- 2 files changed, 28 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts index 4f5457a..744ab95 100644 --- a/arch/arm/boot/dts/ste-snowball.dts +++ b/arch/arm/boot/dts/ste-snowball.dts @@ -248,6 +248,11 @@ pinctrl-1 = <&i2c3_sleep_mode>; }; + ssp@80002000 { + pinctrl-names = "default"; + pinctrl-0 = <&ssp0_snowball_mode>; + }; + cpufreq-cooling { status = "okay"; }; @@ -386,6 +391,29 @@ }; }; + ssp0 { + ssp0_snowball_mode: ssp0_snowball_default { + snowball_mux { + ste,function = "ssp0"; + ste,pins = "ssp0_a_1"; + }; + snowball_cfg1 { + ste,pins = "GPIO144_B13"; /* FRM */ + ste,config = <&gpio_out_hi>; + }; + snowball_cfg2 { + ste,pins = "GPIO145_C13"; /* RXD */ + ste,config = <&in_pd>; + }; + snowball_cfg3 { + ste,pins = + "GPIO146_D13", /* TXD */ + "GPIO143_D12"; /* CLK */ + ste,config = <&out_lo>; + }; + + }; + }; }; mcde@a0350000 { diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c index 55da56e..0e5d268 100644 --- a/arch/arm/mach-ux500/board-mop500-pins.c +++ b/arch/arm/mach-ux500/board-mop500-pins.c @@ -19,8 +19,6 @@ /* These simply sets bias for pins */ #define BIAS(a,b) static unsigned long a[] = { b } -BIAS(pd, PIN_PULL_DOWN); - BIAS(abx500_out_lo, PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0)); BIAS(abx500_in_pd, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 1)); BIAS(abx500_in_nopull, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 0)); @@ -299,9 +297,6 @@ static struct pinctrl_map __initdata ab8505_pinmap[] = { }; static struct pinctrl_map __initdata snowball_pinmap[] = { - /* Mux in SSP0 connected to AB8500, pull down RXD pin */ - DB8500_MUX_HOG("ssp0_a_1", "ssp0"), - DB8500_PIN_HOG("GPIO145_C13", pd), /* User LED */ DB8500_PIN_HOG("GPIO142_C11", gpio_out_hi), /* Accelerometer/Magnetometer */ -- cgit v1.1 From 2f4b84f8ecd2e4680a2e205e78d5ccdf56bd87d7 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 17 Nov 2013 11:33:19 +0100 Subject: ARM: ux500: move snowball LED pin control to device tree This moves the Snowball LED pin config to the device tree. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-snowball.dts | 11 +++++++++++ arch/arm/mach-ux500/board-mop500-pins.c | 2 -- 2 files changed, 11 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts index 744ab95..605188b 100644 --- a/arch/arm/boot/dts/ste-snowball.dts +++ b/arch/arm/boot/dts/ste-snowball.dts @@ -76,6 +76,8 @@ leds { compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&gpioled_snowball_mode>; used-led { label = "user_led"; gpios = <&gpio4 14 0x4>; @@ -414,6 +416,15 @@ }; }; + gpio_led { + gpioled_snowball_mode: gpioled_default { + snowball_cfg1 { + ste,pins = "GPIO142_C11"; + ste,config = <&gpio_out_hi>; + }; + + }; + }; }; mcde@a0350000 { diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c index 0e5d268..aae9cfc 100644 --- a/arch/arm/mach-ux500/board-mop500-pins.c +++ b/arch/arm/mach-ux500/board-mop500-pins.c @@ -297,8 +297,6 @@ static struct pinctrl_map __initdata ab8505_pinmap[] = { }; static struct pinctrl_map __initdata snowball_pinmap[] = { - /* User LED */ - DB8500_PIN_HOG("GPIO142_C11", gpio_out_hi), /* Accelerometer/Magnetometer */ DB8500_PIN_HOG("GPIO163_C20", gpio_in_pu), /* ACCEL_IRQ1 */ DB8500_PIN_HOG("GPIO164_B21", gpio_in_pu), /* ACCEL_IRQ2 */ -- cgit v1.1 From 4d4629fcc264ff532801f4fb66032ff3c4df48f0 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 17 Nov 2013 11:52:32 +0100 Subject: ARM: ux500: move snowball pin configs to device tree Move the few remaining snowball pin configurations to the device tree, reference these as hogs to the pin controller until there are real devices that can make use of them. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-snowball.dts | 59 +++++++++++++++++++++++++++++++++ arch/arm/mach-ux500/board-mop500-pins.c | 19 ----------- 2 files changed, 59 insertions(+), 19 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts index 605188b..9070c37 100644 --- a/arch/arm/boot/dts/ste-snowball.dts +++ b/arch/arm/boot/dts/ste-snowball.dts @@ -357,6 +357,16 @@ }; pinctrl { + /* + * Set this up using hogs, as time goes by and as seems fit, these + * can be moved over to being controlled by respective device. + */ + pinctrl-names = "default"; + pinctrl-0 = <&accel_snowball_mode>, + <&magneto_snowball_mode>, + <&gbf_snowball_mode>, + <&wlan_snowball_mode>; + ethernet { /* * Mux in "SM" which is used for the @@ -425,6 +435,55 @@ }; }; + accelerometer { + accel_snowball_mode: accel_snowball { + /* Accelerometer lines */ + snowball_cfg1 { + ste,pins = + "GPIO163_C20", /* ACCEL_IRQ1 */ + "GPIO164_B21"; /* ACCEL_IRQ2 */ + ste,config = <&gpio_in_pu>; + }; + }; + }; + magnetometer { + magneto_snowball_mode: magneto_snowball { + snowball_cfg1 { + ste,pins = "GPIO165_C21"; /* MAG_DRDY */ + ste,config = <&gpio_in_pu>; + }; + }; + }; + gbf { + gbf_snowball_mode: gbf_snowball { + /* + * GBF (GPS, Bluetooth, FM-radio) interface, + * pull low to reset state + */ + snowball_cfg1 { + ste,pins = "GPIO171_D23"; /* GBF_ENA_RESET */ + ste,config = <&gpio_out_lo>; + }; + }; + }; + wlan { + wlan_snowball_mode: wlan_snowball { + /* + * Activate this mode with the WLAN chip. + * These are plain GPIO pins used by WLAN + */ + snowball_cfg1 { + ste,pins = + "GPIO161_D21", /* WLAN_PMU_EN */ + "GPIO215_AH13"; /* WLAN_ENA */ + ste,config = <&gpio_out_lo>; + }; + snowball_cfg2 { + ste,pins = "GPIO216_AG12"; /* WLAN_IRQ */ + ste,config = <&gpio_in_pu>; + }; + }; + }; }; mcde@a0350000 { diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c index aae9cfc..ff532ba 100644 --- a/arch/arm/mach-ux500/board-mop500-pins.c +++ b/arch/arm/mach-ux500/board-mop500-pins.c @@ -23,11 +23,6 @@ BIAS(abx500_out_lo, PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0)); BIAS(abx500_in_pd, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 1)); BIAS(abx500_in_nopull, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 0)); -/* These also force them into GPIO mode */ -BIAS(gpio_in_pu, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED); -BIAS(gpio_out_hi, PIN_OUTPUT_HIGH|PIN_GPIOMODE_ENABLED); -BIAS(gpio_out_lo, PIN_OUTPUT_LOW|PIN_GPIOMODE_ENABLED); - /* We use these to define hog settings that are always done on boot */ #define DB8500_MUX_HOG(group,func) \ PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-db8500", group, func) @@ -296,18 +291,6 @@ static struct pinctrl_map __initdata ab8505_pinmap[] = { AB8505_PIN_HOG("GPIO53_D15", in_pd), }; -static struct pinctrl_map __initdata snowball_pinmap[] = { - /* Accelerometer/Magnetometer */ - DB8500_PIN_HOG("GPIO163_C20", gpio_in_pu), /* ACCEL_IRQ1 */ - DB8500_PIN_HOG("GPIO164_B21", gpio_in_pu), /* ACCEL_IRQ2 */ - DB8500_PIN_HOG("GPIO165_C21", gpio_in_pu), /* MAG_DRDY */ - /* WLAN/GBF */ - DB8500_PIN_HOG("GPIO161_D21", gpio_out_lo), /* WLAN_PMU_EN */ - DB8500_PIN_HOG("GPIO171_D23", gpio_out_hi), /* GBF_ENA */ - DB8500_PIN_HOG("GPIO215_AH13", gpio_out_lo), /* WLAN_ENA */ - DB8500_PIN_HOG("GPIO216_AG12", gpio_in_pu), /* WLAN_IRQ */ -}; - void __init mop500_pinmaps_init(void) { if (machine_is_u8520()) @@ -320,8 +303,6 @@ void __init mop500_pinmaps_init(void) void __init snowball_pinmaps_init(void) { - pinctrl_register_mappings(snowball_pinmap, - ARRAY_SIZE(snowball_pinmap)); pinctrl_register_mappings(ab8500_pinmap, ARRAY_SIZE(ab8500_pinmap)); } -- cgit v1.1 From 7e0632a5262f0a23644df7aad7132ec46530aff9 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 19 Nov 2013 22:43:30 +0100 Subject: ARM: ux500: delete remnant pin config macros This deletes a few final pin configuration macros from the ux500. Acked-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/mach-ux500/board-mop500-pins.c | 23 ----------------------- 1 file changed, 23 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c index ff532ba..f63619b 100644 --- a/arch/arm/mach-ux500/board-mop500-pins.c +++ b/arch/arm/mach-ux500/board-mop500-pins.c @@ -10,7 +10,6 @@ #include #include #include -#include #include @@ -23,28 +22,6 @@ BIAS(abx500_out_lo, PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0)); BIAS(abx500_in_pd, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 1)); BIAS(abx500_in_nopull, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 0)); -/* We use these to define hog settings that are always done on boot */ -#define DB8500_MUX_HOG(group,func) \ - PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-db8500", group, func) -#define DB8500_PIN_HOG(pin,conf) \ - PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-db8500", pin, conf) - -/* These are default states associated with device and changed runtime */ -#define DB8500_MUX(group,func,dev) \ - PIN_MAP_MUX_GROUP_DEFAULT(dev, "pinctrl-db8500", group, func) -#define DB8500_PIN(pin,conf,dev) \ - PIN_MAP_CONFIGS_PIN_DEFAULT(dev, "pinctrl-db8500", pin, conf) -#define DB8500_PIN_IDLE(pin, conf, dev) \ - PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_IDLE, "pinctrl-db8500", \ - pin, conf) -#define DB8500_PIN_SLEEP(pin, conf, dev) \ - PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \ - pin, conf) -#define DB8500_MUX_STATE(group, func, dev, state) \ - PIN_MAP_MUX_GROUP(dev, state, "pinctrl-db8500", group, func) -#define DB8500_PIN_STATE(pin, conf, dev, state) \ - PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-db8500", pin, conf) - #define AB8500_MUX_HOG(group, func) \ PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-ab8500.0", group, func) #define AB8500_PIN_HOG(pin, conf) \ -- cgit v1.1 From 8cf50a245152ae9294ccc2a24e51641a842c2c24 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 19 Nov 2013 22:46:33 +0100 Subject: ARM: ux500: delete Nomadik pinctrl AUXDATA This deletes the AUXDATA hammering down the Nomadik pin controller name to "pinctrl-db8500". We have removed all dependencies on this name. Acked-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/mach-ux500/cpu-db8500.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index 0b5b27b..840452b 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include @@ -167,9 +166,6 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("stericsson,ux500-hash", 0xa03c2000, "hash1", NULL), OF_DEV_AUXDATA("stericsson,snd-soc-mop500", 0, "snd-soc-mop500.0", NULL), - /* Requires device name bindings. */ - OF_DEV_AUXDATA("stericsson,db8500-pinctrl", U8500_PRCMU_BASE, - "pinctrl-db8500", NULL), {}, }; -- cgit v1.1 From 01e9da7d754fb638752a544fb62fc8c942946654 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 19 Nov 2013 22:54:56 +0100 Subject: ARM: ux500: get rid of unused header This removes the unused inclusion of which is the last user in the entire kernel of this platform data header. Acked-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/mach-ux500/board-mop500-audio.c | 1 - 1 file changed, 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-ux500/board-mop500-audio.c b/arch/arm/mach-ux500/board-mop500-audio.c index d528059..dc7f901 100644 --- a/arch/arm/mach-ux500/board-mop500-audio.c +++ b/arch/arm/mach-ux500/board-mop500-audio.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include "irqs.h" -- cgit v1.1 From e937274f4268923c5220843cadddb7b78a51ecac Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 6 Nov 2013 10:05:45 +0000 Subject: ARM: ux500: Clean-up non-DT IRQ initialisation Decommission the non-DT boot path. Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/mach-ux500/cpu.c | 22 ++++++---------------- 1 file changed, 6 insertions(+), 16 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c index 8f8004f..d11ac4b 100644 --- a/arch/arm/mach-ux500/cpu.c +++ b/arch/arm/mach-ux500/cpu.c @@ -63,12 +63,7 @@ void __init ux500_init_irq(void) } else ux500_unknown_soc(); -#ifdef CONFIG_OF - if (of_have_populated_dt()) - irqchip_init(); - else -#endif - gic_init(0, 29, dist_base, cpu_base); + irqchip_init(); /* * Init clocks here so that they are available for system timer @@ -78,16 +73,11 @@ void __init ux500_init_irq(void) prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1); ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1); - if (of_have_populated_dt()) - u8500_of_clk_init(U8500_CLKRST1_BASE, - U8500_CLKRST2_BASE, - U8500_CLKRST3_BASE, - U8500_CLKRST5_BASE, - U8500_CLKRST6_BASE); - else - u8500_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE, - U8500_CLKRST3_BASE, U8500_CLKRST5_BASE, - U8500_CLKRST6_BASE); + u8500_of_clk_init(U8500_CLKRST1_BASE, + U8500_CLKRST2_BASE, + U8500_CLKRST3_BASE, + U8500_CLKRST5_BASE, + U8500_CLKRST6_BASE); } else if (cpu_is_u9540()) { prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1); ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1); -- cgit v1.1 From cef2e06cf4184cadbfeb459a8a5ab7205f526f78 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 6 Nov 2013 10:05:46 +0000 Subject: ARM: ux500: Remove unused call to register AMBA devices Decomission the AMBA device register functions. Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/mach-ux500/Makefile | 2 +- arch/arm/mach-ux500/devices.c | 26 -------------------------- arch/arm/mach-ux500/setup.h | 3 --- 3 files changed, 1 insertion(+), 30 deletions(-) delete mode 100644 arch/arm/mach-ux500/devices.c (limited to 'arch') diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile index 66f351f..d05ba75 100644 --- a/arch/arm/mach-ux500/Makefile +++ b/arch/arm/mach-ux500/Makefile @@ -2,7 +2,7 @@ # Makefile for the linux kernel, U8500 machine. # -obj-y := cpu.o devices.o id.o timer.o pm.o +obj-y := cpu.o id.o timer.o pm.o obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o obj-$(CONFIG_MACH_MOP500) += board-mop500-sdi.o \ diff --git a/arch/arm/mach-ux500/devices.c b/arch/arm/mach-ux500/devices.c deleted file mode 100644 index 0f9e52b..0000000 --- a/arch/arm/mach-ux500/devices.c +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Rabin Vincent for ST-Ericsson - * License terms: GNU General Public License (GPL) version 2 - */ - -#include -#include -#include -#include -#include - -#include "setup.h" - -#include "db8500-regs.h" - -void __init amba_add_devices(struct amba_device *devs[], int num) -{ - int i; - - for (i = 0; i < num; i++) { - struct amba_device *d = devs[i]; - amba_device_register(d, &iomem_resource); - } -} diff --git a/arch/arm/mach-ux500/setup.h b/arch/arm/mach-ux500/setup.h index bdb3564..e5682da 100644 --- a/arch/arm/mach-ux500/setup.h +++ b/arch/arm/mach-ux500/setup.h @@ -27,9 +27,6 @@ extern void __init ux500_init_irq(void); extern struct device *ux500_soc_device_init(const char *soc_id); -struct amba_device; -extern void __init amba_add_devices(struct amba_device *devs[], int num); - extern void ux500_timer_init(void); #define __IO_DEV_DESC(x, sz) { \ -- cgit v1.1 From c96e476816393ef9c1dfe35d59203824da998cb4 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 6 Nov 2013 10:05:47 +0000 Subject: ARM: ux500: Clean-up legacy extern prototype Decomission io_mapping() and device init calls from non-DT boot path. Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/mach-ux500/setup.h | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-ux500/setup.h b/arch/arm/mach-ux500/setup.h index e5682da..7164cfd 100644 --- a/arch/arm/mach-ux500/setup.h +++ b/arch/arm/mach-ux500/setup.h @@ -19,9 +19,6 @@ void ux500_restart(enum reboot_mode mode, const char *cmd); void __init ux500_map_io(void); -extern void __init u8500_map_io(void); - -extern struct device * __init u8500_init_devices(void); extern void __init ux500_init_irq(void); -- cgit v1.1 From ac9c0cf1194f547cc9975fbd7e80e1f0643dfb97 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 6 Nov 2013 10:05:48 +0000 Subject: ARM: ux500: Remove checking for DT during timer init Decomission the non-DT boot path as we are now DT only Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/mach-ux500/timer.c | 28 ++++++++-------------------- 1 file changed, 8 insertions(+), 20 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c index 05a4ff7..ca60bbd 100644 --- a/arch/arm/mach-ux500/timer.c +++ b/arch/arm/mach-ux500/timer.c @@ -27,18 +27,11 @@ static DEFINE_TWD_LOCAL_TIMER(u8500_twd_local_timer, static void __init ux500_twd_init(void) { struct twd_local_timer *twd_local_timer; - int err; /* Use this to switch local timer base if changed in new ASICs */ twd_local_timer = &u8500_twd_local_timer; - if (of_have_populated_dt()) - clocksource_of_init(); - else { - err = twd_local_timer_register(twd_local_timer); - if (err) - pr_err("twd_local_timer_register failed %d\n", err); - } + clocksource_of_init(); } #else #define ux500_twd_init() do { } while(0) @@ -63,20 +56,15 @@ void __init ux500_timer_init(void) ux500_unknown_soc(); } - /* TODO: Once MTU has been DT:ed place code above into else. */ - if (of_have_populated_dt()) { -#ifdef CONFIG_OF - np = of_find_matching_node(NULL, prcmu_timer_of_match); - if (!np) -#endif - goto dt_fail; + np = of_find_matching_node(NULL, prcmu_timer_of_match); + if (!np) + goto dt_fail; - tmp_base = of_iomap(np, 0); - if (!tmp_base) - goto dt_fail; + tmp_base = of_iomap(np, 0); + if (!tmp_base) + goto dt_fail; - prcmu_timer_base = tmp_base; - } + prcmu_timer_base = tmp_base; dt_fail: /* Doing it the old fashioned way. */ -- cgit v1.1 From 8da15e17408c58ff45dc8e01dad8775246ef2220 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 19 Nov 2013 22:17:06 +0100 Subject: ARM: ux500: decomission the non-DT MTU init sequence The MTU is now only initialized using the native clocksource device tree matching. Signed-off-by: Linus Walleij --- arch/arm/mach-ux500/timer.c | 28 ++-------------------------- 1 file changed, 2 insertions(+), 26 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c index ca60bbd..1a9051b 100644 --- a/arch/arm/mach-ux500/timer.c +++ b/arch/arm/mach-ux500/timer.c @@ -10,7 +10,6 @@ #include #include #include -#include #include @@ -44,17 +43,14 @@ const static struct of_device_id prcmu_timer_of_match[] __initconst = { void __init ux500_timer_init(void) { - void __iomem *mtu_timer_base; void __iomem *prcmu_timer_base; void __iomem *tmp_base; struct device_node *np; - if (cpu_is_u8500_family() || cpu_is_ux540_family()) { - mtu_timer_base = __io_address(U8500_MTU0_BASE); + if (cpu_is_u8500_family() || cpu_is_ux540_family()) prcmu_timer_base = __io_address(U8500_PRCMU_TIMER_4_BASE); - } else { + else ux500_unknown_soc(); - } np = of_find_matching_node(NULL, prcmu_timer_of_match); if (!np) @@ -67,26 +63,6 @@ void __init ux500_timer_init(void) prcmu_timer_base = tmp_base; dt_fail: - /* Doing it the old fashioned way. */ - - /* - * Here we register the timerblocks active in the system. - * Localtimers (twd) is started when both cpu is up and running. - * MTU register a clocksource, clockevent and sched_clock. - * Since the MTU is located in the VAPE power domain - * it will be cleared in sleep which makes it unsuitable. - * We however need it as a timer tick (clockevent) - * during boot to calibrate delay until twd is started. - * RTC-RTT have problems as timer tick during boot since it is - * depending on delay which is not yet calibrated. RTC-RTT is in the - * always-on powerdomain and is used as clockevent instead of twd when - * sleeping. - * The PRCMU timer 4 register a clocksource and - * sched_clock with higher rating then MTU since is always-on. - * - */ - if (!of_have_populated_dt()) - nmdk_timer_init(mtu_timer_base, IRQ_MTU0); clksrc_dbx500_prcmu_init(prcmu_timer_base); ux500_twd_init(); } -- cgit v1.1 From 089b5c9595eb3c516ab6af12802f16505cde271b Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 19 Nov 2013 22:37:55 +0100 Subject: ARM: ux500: decomission custom SMP TWD timer init Rely solely on device tree matching to detect and probe the SMP TWD timer and remove this custom hack. Signed-off-by: Linus Walleij --- arch/arm/mach-ux500/timer.c | 22 +--------------------- 1 file changed, 1 insertion(+), 21 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c index 1a9051b..87efda0 100644 --- a/arch/arm/mach-ux500/timer.c +++ b/arch/arm/mach-ux500/timer.c @@ -11,31 +11,11 @@ #include #include -#include - #include "setup.h" -#include "irqs.h" #include "db8500-regs.h" #include "id.h" -#ifdef CONFIG_HAVE_ARM_TWD -static DEFINE_TWD_LOCAL_TIMER(u8500_twd_local_timer, - U8500_TWD_BASE, IRQ_LOCALTIMER); - -static void __init ux500_twd_init(void) -{ - struct twd_local_timer *twd_local_timer; - - /* Use this to switch local timer base if changed in new ASICs */ - twd_local_timer = &u8500_twd_local_timer; - - clocksource_of_init(); -} -#else -#define ux500_twd_init() do { } while(0) -#endif - const static struct of_device_id prcmu_timer_of_match[] __initconst = { { .compatible = "stericsson,db8500-prcmu-timer-4", }, { }, @@ -64,5 +44,5 @@ void __init ux500_timer_init(void) dt_fail: clksrc_dbx500_prcmu_init(prcmu_timer_base); - ux500_twd_init(); + clocksource_of_init(); } -- cgit v1.1 From 30e34001c8f676c72498c3e8a690e08684d2f32a Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Mon, 22 Jul 2013 11:52:21 +0100 Subject: ARM: nomadik: Remove '0x's from nomadik stn8815 DTS file Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-nomadik-stn8815.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi index 79425e3..5acc044 100644 --- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi +++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi @@ -769,14 +769,14 @@ #size-cells = <1>; ranges; - vica: intc@0x10140000 { + vica: intc@10140000 { compatible = "arm,versatile-vic"; interrupt-controller; #interrupt-cells = <1>; reg = <0x10140000 0x20>; }; - vicb: intc@0x10140020 { + vicb: intc@10140020 { compatible = "arm,versatile-vic"; interrupt-controller; #interrupt-cells = <1>; -- cgit v1.1 From 6568eccd10f6d417f7e40160ca29c965a34b6254 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 14 Nov 2013 19:41:40 +0100 Subject: ARM: nomadik: get rid of explicit ethernet GPIO management We used to set up the GPIO used for the SMC ethernet IRQ by requesting the GPIO line explicitly. As we recently established that specifying the GPIO controller as interrupt parent and requesting one of its interrupts by reference should be enough, we do away with this. Incidentally, the Nomadik GPIO chip driver handles this just fine: the IRQ is set up and fired as expected. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-nomadik-s8815.dts | 4 ---- arch/arm/mach-nomadik/cpu-8815.c | 32 -------------------------------- 2 files changed, 36 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/ste-nomadik-s8815.dts b/arch/arm/boot/dts/ste-nomadik-s8815.dts index 16c3888..f557feb 100644 --- a/arch/arm/boot/dts/ste-nomadik-s8815.dts +++ b/arch/arm/boot/dts/ste-nomadik-s8815.dts @@ -67,10 +67,6 @@ /* Custom board node with GPIO pins to active etc */ usb-s8815 { - /* The S8815 is using this very GPIO pin for the SMSC91x IRQs */ - ethernet-gpio { - gpios = <&gpio3 8 0x1>; - }; /* This will bias the MMC/SD card detect line */ mmcsd-gpio { gpios = <&gpio3 16 0x1>; diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c index cce2c9d..4a1065e 100644 --- a/arch/arm/mach-nomadik/cpu-8815.c +++ b/arch/arm/mach-nomadik/cpu-8815.c @@ -110,38 +110,6 @@ static void cpu8815_restart(enum reboot_mode mode, const char *cmd) } /* - * The SMSC911x IRQ is connected to a GPIO pin, but the driver expects - * to simply request an IRQ passed as a resource. So the GPIO pin needs - * to be requested by this hog and set as input. - */ -static int __init cpu8815_eth_init(void) -{ - struct device_node *eth; - int gpio, irq, err; - - eth = of_find_node_by_path("/usb-s8815/ethernet-gpio"); - if (!eth) { - pr_info("could not find any ethernet GPIO\n"); - return 0; - } - gpio = of_get_gpio(eth, 0); - err = gpio_request(gpio, "eth_irq"); - if (err) { - pr_info("failed to request ethernet GPIO\n"); - return -ENODEV; - } - err = gpio_direction_input(gpio); - if (err) { - pr_info("failed to set ethernet GPIO as input\n"); - return -ENODEV; - } - irq = gpio_to_irq(gpio); - pr_info("enabled USB-S8815 ethernet GPIO %d, IRQ %d\n", gpio, irq); - return 0; -} -device_initcall(cpu8815_eth_init); - -/* * This GPIO pin turns on a line that is used to detect card insertion * on this board. */ -- cgit v1.1 From 261e7735d0ed0f0916b3edc528e206af5196688d Mon Sep 17 00:00:00 2001 From: Arnaud Ebalard Date: Fri, 29 Nov 2013 21:27:25 +0100 Subject: ARM: kirkwood: NETGEAR ReadyNAS Duo v2 .dts cleanup The patch does some cleanup work on NETGEAR ReadyNAS Duo v2 .dts file. Changes are listed below: - Converted from value to macros for GPIO voltage level - Converted all numeric input key values to macros - Made button names more explicit - Document ethernet PHY (Marvell 88E1318) via a comment - Added header for the file to describe content and author - Made G762 clock node name unique by including g762 in it - Fixed all node names and labels to use respectively '-' and '_' - Changed order of included files from general to local - Removed useless clocks and gpio-keys properties Signed-off-by: Arnaud Ebalard Signed-off-by: Jason Cooper --- .../boot/dts/kirkwood-netgear_readynas_duo_v2.dts | 51 ++++++++++++---------- 1 file changed, 29 insertions(+), 22 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts index 3627702..d408adc 100644 --- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts +++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts @@ -1,5 +1,17 @@ +/* + * Device Tree file for NETGEAR ReadyNAS Duo v2 + * + * Copyright (C) 2013, Arnaud EBALARD + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + /dts-v1/; +#include #include #include "kirkwood.dtsi" #include "kirkwood-6282.dtsi" @@ -68,10 +80,7 @@ }; clocks { - #address-cells = <1>; - #size-cells = <0>; - - g762_clk: fixedclk { + g762_clk: g762-oscillator { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <8192>; @@ -117,49 +126,47 @@ power_led { label = "status:blue:power_led"; - gpios = <&gpio0 31 1>; /* GPIO 31 Active Low */ + gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; default-state = "keep"; }; activity_led { label = "status:blue:activity_led"; - gpios = <&gpio1 6 1>; /* GPIO 38 Active Low */ + gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; }; disk1_led { label = "status:blue:disk1_led"; - gpios = <&gpio0 23 1>; /* GPIO 23 Active Low */ + gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; }; disk2_led { label = "status:blue:disk2_led"; - gpios = <&gpio0 22 1>; /* GPIO 22 Active Low */ + gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; }; backup_led { label = "status:blue:backup_led"; - gpios = <&gpio0 29 1>; /* GPIO 29 Active Low*/ + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-0 = <&pmx_button_power &pmx_button_backup &pmx_button_reset>; pinctrl-names = "default"; - button@1 { + power-button { label = "Power Button"; - linux,code = <116>; /* KEY_POWER */ - gpios = <&gpio1 15 1>; + linux,code = ; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; }; - button@2 { + reset-button { label = "Reset Button"; - linux,code = <0x198>; /* KEY_RESTART */ - gpios = <&gpio0 13 1>; + linux,code = ; + gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; }; - button@3 { + backup-button { label = "Backup Button"; - linux,code = <133>; /* KEY_COPY */ - gpios = <&gpio1 13 1>; + linux,code = ; + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; }; }; @@ -222,7 +229,7 @@ &mdio { status = "okay"; - ethphy0: ethernet-phy@0 { + ethphy0: ethernet-phy@0 { /* Marvell 88E1318 */ device_type = "ethernet-phy"; reg = <0>; }; -- cgit v1.1 From b8f18162402005e8f954641abee2a16248750595 Mon Sep 17 00:00:00 2001 From: Arnaud Ebalard Date: Fri, 29 Nov 2013 21:27:38 +0100 Subject: ARM: mvebu: NETGEAR ReadyNAS 102 .dts cleanup The patch does some cleanup work on NETGEAR ReadyNAS 102 .dts file. Changes are listed below - Added missing button mpp in pinctrl - Converted from value to macros for GPIO voltage level - Converted all numeric input key values to macros - Added GPIO keys pins to pinctrl - Made button names more explicit - Document ethernet PHY (Marvell 88E1318) via a comment - Made G762 clock node name unique by including g762 in it - Fixed all node names and labels to use respectively '-' and '_' - Changed order of included files from general to local - Removed useless clocks and gpio-keys properties Signed-off-by: Arnaud Ebalard Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-370-netgear-rn102.dts | 81 +++++++++++++++----------- 1 file changed, 48 insertions(+), 33 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts index df1a1e0..41c54b1 100644 --- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts +++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts @@ -11,6 +11,8 @@ /dts-v1/; +#include +#include #include "armada-370.dtsi" / { @@ -77,6 +79,21 @@ marvell,function = "gpio"; }; + backup_button_pin: backup-button-pin { + marvell,pins = "mpp58"; + marvell,function = "gpio"; + }; + + power_button_pin: power-button-pin { + marvell,pins = "mpp62"; + marvell,function = "gpio"; + }; + + reset_button_pin: reset-button-pin { + marvell,pins = "mpp6"; + marvell,function = "gpio"; + }; + poweroff: poweroff { marvell,pins = "mpp8"; marvell,function = "gpio"; @@ -84,7 +101,7 @@ }; mdio { - phy0: ethernet-phy@0 { + phy0: ethernet-phy@0 { /* Marvell 88E1318 */ reg = <0>; }; }; @@ -117,78 +134,76 @@ }; clocks { - #address-cells = <1>; - #size-cells = <0>; - - g762_clk: fixedclk { + g762_clk: g762-oscillator { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <8192>; }; }; - gpio_leds { + gpio-leds { compatible = "gpio-leds"; - pinctrl-0 = < &power_led_pin - &sata1_led_pin - &sata2_led_pin - &backup_led_pin >; + pinctrl-0 = <&power_led_pin + &sata1_led_pin + &sata2_led_pin + &backup_led_pin>; pinctrl-names = "default"; - blue_power_led { + blue-power-led { label = "rn102:blue:pwr"; - gpios = <&gpio1 25 1>; /* GPIO 57 Active Low */ + gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; default-state = "keep"; }; - green_sata1_led { + green-sata1-led { label = "rn102:green:sata1"; - gpios = <&gpio0 15 1>; /* GPIO 15 Active Low */ + gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; default-state = "on"; }; - green_sata2_led { + green-sata2-led { label = "rn102:green:sata2"; - gpios = <&gpio0 14 1>; /* GPIO 14 Active Low */ + gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; default-state = "on"; }; - green_backup_led { + green-backup-led { label = "rn102:green:backup"; - gpios = <&gpio1 24 1>; /* GPIO 56 Active Low */ + gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; default-state = "on"; }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; + pinctrl-0 = <&power_button_pin + &reset_button_pin + &backup_button_pin>; + pinctrl-names = "default"; - button@1 { + power-button { label = "Power Button"; - linux,code = <116>; /* KEY_POWER */ - gpios = <&gpio1 30 0>; + linux,code = ; + gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; }; - button@2 { + reset-button { label = "Reset Button"; - linux,code = <0x198>; /* KEY_RESTART */ - gpios = <&gpio0 6 1>; + linux,code = ; + gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; }; - button@3 { + backup-button { label = "Backup Button"; - linux,code = <133>; /* KEY_COPY */ - gpios = <&gpio1 26 1>; + linux,code = ; + gpios = <&gpio1 26 GPIO_ACTIVE_LOW>; }; }; - gpio_poweroff { + gpio-poweroff { compatible = "gpio-poweroff"; pinctrl-0 = <&poweroff>; pinctrl-names = "default"; - gpios = <&gpio0 8 1>; + gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; }; - }; -- cgit v1.1 From 96b09e3e6caef30c962cb9da406f1112a5ae58f5 Mon Sep 17 00:00:00 2001 From: Arnaud Ebalard Date: Fri, 29 Nov 2013 21:27:48 +0100 Subject: ARM: mvebu: NETGEAR ReadyNAS 104 .dts cleanup The patch does some cleanup work on NETGEAR ReadyNAS 104 .dts file. Changes are listed below: - Completed conversion from value to macros for GPIO voltage level - Converted all numeric input key values to macros - Fixed all node names and labels to use respectively '-' and '_' - Made button names more explicit - Changed order of included files from general to local - Removed useless clocks and gpio-keys properties - Document ethernet PHY (Marvell 88E1318) via a comment - Made G762 clock node name unique by including g762 in it Signed-off-by: Arnaud Ebalard Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-370-netgear-rn104.dts | 68 ++++++++++++-------------- 1 file changed, 32 insertions(+), 36 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/armada-370-netgear-rn104.dts index 50b5150..e48e5fb 100644 --- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts +++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts @@ -11,8 +11,9 @@ /dts-v1/; -#include "armada-370.dtsi" +#include #include +#include "armada-370.dtsi" / { model = "NETGEAR ReadyNAS 104"; @@ -59,12 +60,12 @@ marvell,function = "gpio"; }; - backup_key_pin: backup-key-pin { + backup_button_pin: backup-button-pin { marvell,pins = "mpp52"; marvell,function = "gpio"; }; - power_key_pin: power-key-pin { + power_button_pin: power-button-pin { marvell,pins = "mpp62"; marvell,function = "gpio"; }; @@ -79,18 +80,18 @@ marvell,function = "gpio"; }; - reset_key_pin: reset-key-pin { + reset_button_pin: reset-button-pin { marvell,pins = "mpp65"; marvell,function = "gpio"; }; }; mdio { - phy0: ethernet-phy@0 { + phy0: ethernet-phy@0 { /* Marvell 88E1318 */ reg = <0>; }; - phy1: ethernet-phy@1 { + phy1: ethernet-phy@1 { /* Marvell 88E1318 */ reg = <1>; }; }; @@ -136,90 +137,85 @@ }; clocks { - #address-cells = <1>; - #size-cells = <0>; - - g762_clk: fixedclk { + g762_clk: g762-oscillator { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <8192>; }; }; - gpio_leds { + gpio-leds { compatible = "gpio-leds"; pinctrl-0 = <&backup_led_pin &power_led_pin>; pinctrl-names = "default"; - blue_backup_led { + blue-backup-led { label = "rn104:blue:backup"; - gpios = <&gpio1 31 0>; /* GPIO 63 Active High */ + gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - blue_power_led { + blue-power-led { label = "rn104:blue:pwr"; - gpios = <&gpio2 0 1>; /* GPIO 64 Active Low */ + gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; linux,default-trigger = "keep"; }; - sata1_led { + blue-sata1-led { label = "rn104:blue:sata1"; gpios = <&pca9554 0 GPIO_ACTIVE_LOW>; default-state = "off"; }; - sata2_led { + blue-sata2-led { label = "rn104:blue:sata2"; gpios = <&pca9554 1 GPIO_ACTIVE_LOW>; default-state = "off"; }; - sata3_led { + blue-sata3-led { label = "rn104:blue:sata3"; gpios = <&pca9554 2 GPIO_ACTIVE_LOW>; default-state = "off"; }; - sata4_led { + blue-sata4-led { label = "rn104:blue:sata4"; gpios = <&pca9554 3 GPIO_ACTIVE_LOW>; default-state = "off"; }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&backup_key_pin - &power_key_pin - &reset_key_pin>; + pinctrl-0 = <&backup_button_pin + &power_button_pin + &reset_button_pin>; pinctrl-names = "default"; - button@1 { + backup-button { label = "Backup Button"; - linux,code = <133>; /* KEY_COPY */ - gpios = <&gpio1 20 1>; + linux,code = ; + gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; }; - button@2 { + power-button { label = "Power Button"; - linux,code = <116>; /* KEY_POWER */ - gpios = <&gpio1 30 0>; + linux,code = ; + gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; }; - button@3 { + reset-button { label = "Reset Button"; - linux,code = <0x198>; /* KEY_RESTART */ - gpios = <&gpio2 1 1>; + linux,code = ; + gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; }; }; - gpio_poweroff { + gpio-poweroff { compatible = "gpio-poweroff"; pinctrl-0 = <&poweroff>; pinctrl-names = "default"; - gpios = <&gpio1 28 1>; + gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; }; }; -- cgit v1.1 From 906fd84ee7c1080240a4aa687449d18fd83939c7 Mon Sep 17 00:00:00 2001 From: Yuvaraj Kumar C D Date: Mon, 21 Oct 2013 05:47:14 +0900 Subject: ARM: dts: Move dwmmc nodes from exynos5.dtsi to exynos5250.dtsi Exynos5 series SOC's 5250 and 5420 have different versions of DWMMC controller.So there is a new compatible string to distinguish between them.So these nodes should be moved out of Exynos5 series common device tree source to SOC specific device tree source. Signed-off-by: Yuvaraj Kumar C D Reviewed-by: Tomasz Figa Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5.dtsi | 21 --------------------- arch/arm/boot/dts/exynos5250.dtsi | 12 ++++++++++++ 2 files changed, 12 insertions(+), 21 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi index 074739d..e52b038 100644 --- a/arch/arm/boot/dts/exynos5.dtsi +++ b/arch/arm/boot/dts/exynos5.dtsi @@ -50,27 +50,6 @@ interrupts = <1 9 0xf04>; }; - dwmmc_0: dwmmc0@12200000 { - compatible = "samsung,exynos5250-dw-mshc"; - interrupts = <0 75 0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - dwmmc_1: dwmmc1@12210000 { - compatible = "samsung,exynos5250-dw-mshc"; - interrupts = <0 76 0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - dwmmc_2: dwmmc2@12220000 { - compatible = "samsung,exynos5250-dw-mshc"; - interrupts = <0 77 0>; - #address-cells = <1>; - #size-cells = <0>; - }; - serial@12C00000 { compatible = "samsung,exynos4210-uart"; reg = <0x12C00000 0x100>; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 9db5047..e613da1 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -393,18 +393,30 @@ }; dwmmc_0: dwmmc0@12200000 { + compatible = "samsung,exynos5250-dw-mshc"; + interrupts = <0 75 0>; + #address-cells = <1>; + #size-cells = <0>; reg = <0x12200000 0x1000>; clocks = <&clock 280>, <&clock 139>; clock-names = "biu", "ciu"; }; dwmmc_1: dwmmc1@12210000 { + compatible = "samsung,exynos5250-dw-mshc"; + interrupts = <0 76 0>; + #address-cells = <1>; + #size-cells = <0>; reg = <0x12210000 0x1000>; clocks = <&clock 281>, <&clock 140>; clock-names = "biu", "ciu"; }; dwmmc_2: dwmmc2@12220000 { + compatible = "samsung,exynos5250-dw-mshc"; + interrupts = <0 77 0>; + #address-cells = <1>; + #size-cells = <0>; reg = <0x12220000 0x1000>; clocks = <&clock 282>, <&clock 141>; clock-names = "biu", "ciu"; -- cgit v1.1 From ece19e2b6bee4ef04627ae9dfc4f2360d978fc3d Mon Sep 17 00:00:00 2001 From: Arnaud Ebalard Date: Fri, 29 Nov 2013 21:27:58 +0100 Subject: ARM: mvebu: Fix whitespace in NETGEAR ReadyNAS .dts files This patch provides some whitespace cleanup for NETGEAR ReadyNAS Duo v2 and 102 .dts files: - Fixed bad spaces - Added some space between nodes to improve readability Signed-off-by: Arnaud Ebalard Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-370-netgear-rn102.dts | 1 + .../boot/dts/kirkwood-netgear_readynas_duo_v2.dts | 48 ++++++++++++++-------- 2 files changed, 32 insertions(+), 17 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts index 41c54b1..1c2d13d 100644 --- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts +++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts @@ -64,6 +64,7 @@ marvell,pins = "mpp57"; marvell,function = "gpio"; }; + sata1_led_pin: sata1-led-pin { marvell,pins = "mpp15"; marvell,function = "gpio"; diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts index d408adc..3b1a365 100644 --- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts +++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts @@ -45,34 +45,42 @@ marvell,pins = "mpp47"; marvell,function = "gpio"; }; + pmx_button_backup: pmx-button-backup { marvell,pins = "mpp45"; marvell,function = "gpio"; }; + pmx_button_reset: pmx-button-reset { marvell,pins = "mpp13"; marvell,function = "gpio"; }; + pmx_led_blue_power: pmx-led-blue-power { marvell,pins = "mpp31"; marvell,function = "gpio"; }; + pmx_led_blue_activity: pmx-led-blue-activity { marvell,pins = "mpp38"; marvell,function = "gpio"; }; + pmx_led_blue_disk1: pmx-led-blue-disk1 { marvell,pins = "mpp23"; marvell,function = "gpio"; }; + pmx_led_blue_disk2: pmx-led-blue-disk2 { marvell,pins = "mpp22"; marvell,function = "gpio"; }; + pmx_led_blue_backup: pmx-led-blue-backup { marvell,pins = "mpp29"; marvell,function = "gpio"; }; + pmx_poweroff: pmx-poweroff { marvell,pins = "mpp30"; marvell,function = "gpio"; @@ -129,18 +137,22 @@ gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; default-state = "keep"; }; + activity_led { label = "status:blue:activity_led"; gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; }; + disk1_led { label = "status:blue:disk1_led"; gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; }; + disk2_led { label = "status:blue:disk2_led"; gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; }; + backup_led { label = "status:blue:backup_led"; gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; @@ -158,11 +170,13 @@ linux,code = ; gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; }; + reset-button { label = "Reset Button"; linux,code = ; gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; }; + backup-button { label = "Backup Button"; linux,code = ; @@ -177,23 +191,23 @@ gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB 3.0 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 14 0>; - }; - }; + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + usb3_regulator: usb3-regulator { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "USB 3.0 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + }; + }; }; &nand { -- cgit v1.1 From 8aa0b019fe1400cc8861ead9ff4cd0ba9f4e11ce Mon Sep 17 00:00:00 2001 From: Arnaud Ebalard Date: Fri, 29 Nov 2013 22:29:03 +0100 Subject: ARM: mvebu: Add Netgear ReadyNAS 2120 board All hardware parts of the (mv78230 Armada XP based) NETGEAR ReadyNAS 2120 are supported by mainline kernel (USB 3.0 and eSATA rear ports, USB 2.0 front port, Gigabit controller and PHYs for the two rear ports, serial port, LEDs, Buttons, 88SE9170 SATA controllers, three G762 fan controllers, G751 temperature sensor) except for: - the Intersil ISL12057 I2C RTC Chip, - the Armada NAND controller. Support for both of those is currently work in progress and does not prevent boot. Signed-off-by: Arnaud Ebalard Signed-off-by: Jason Cooper --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/armada-xp-netgear-rn2120.dts | 286 +++++++++++++++++++++++++ 2 files changed, 287 insertions(+) create mode 100644 arch/arm/boot/dts/armada-xp-netgear-rn2120.dts (limited to 'arch') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index d57c1a6..6881b6c 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -114,6 +114,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \ armada-xp-axpwifiap.dtb \ armada-xp-db.dtb \ armada-xp-gp.dtb \ + armada-xp-netgear-rn2120.dtb \ armada-xp-matrix.dtb \ armada-xp-openblocks-ax3-4.dtb dtb-$(CONFIG_ARCH_MXC) += \ diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts new file mode 100644 index 0000000..8b2a787 --- /dev/null +++ b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts @@ -0,0 +1,286 @@ +/* + * Device Tree file for NETGEAR ReadyNAS 2120 + * + * Copyright (C) 2013, Arnaud EBALARD + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +/dts-v1/; + +#include +#include +#include "armada-xp-mv78230.dtsi" + +/ { + model = "NETGEAR ReadyNAS 2120"; + compatible = "netgear,readynas-2120", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp"; + + chosen { + bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { + device_type = "memory"; + reg = <0 0x00000000 0 0x80000000>; /* 2GB */ + }; + + soc { + ranges = ; + + pcie-controller { + status = "okay"; + + /* Connected to first Marvell 88SE9170 SATA controller */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* Connected to second Marvell 88SE9170 SATA controller */ + pcie@2,0 { + /* Port 0, Lane 1 */ + status = "okay"; + }; + + /* Connected to Fresco Logic FL1009 USB 3.0 controller */ + pcie@5,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; + }; + + internal-regs { + pinctrl { + poweroff: poweroff { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + + power_button_pin: power-button-pin { + marvell,pins = "mpp27"; + marvell,function = "gpio"; + }; + + reset_button_pin: reset-button-pin { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + + sata1_led_pin: sata1-led-pin { + marvell,pins = "mpp31"; + marvell,function = "gpio"; + }; + + sata2_led_pin: sata2-led-pin { + marvell,pins = "mpp40"; + marvell,function = "gpio"; + }; + + sata3_led_pin: sata3-led-pin { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + + sata4_led_pin: sata4-led-pin { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + + sata1_power_pin: sata1-power-pin { + marvell,pins = "mpp24"; + marvell,function = "gpio"; + }; + + sata2_power_pin: sata2-power-pin { + marvell,pins = "mpp25"; + marvell,function = "gpio"; + }; + + sata3_power_pin: sata3-power-pin { + marvell,pins = "mpp26"; + marvell,function = "gpio"; + }; + + sata4_power_pin: sata4-power-pin { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + + sata1_pres_pin: sata1-pres-pin { + marvell,pins = "mpp32"; + marvell,function = "gpio"; + }; + + sata2_pres_pin: sata2-pres-pin { + marvell,pins = "mpp33"; + marvell,function = "gpio"; + }; + + sata3_pres_pin: sata3-pres-pin { + marvell,pins = "mpp34"; + marvell,function = "gpio"; + }; + + sata4_pres_pin: sata4-pres-pin { + marvell,pins = "mpp35"; + marvell,function = "gpio"; + }; + + err_led_pin: err-led-pin { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + }; + + serial@12000 { + clocks = <&coreclk 0>; + status = "okay"; + }; + + mdio { + phy0: ethernet-phy@0 { /* Marvell 88E1318 */ + reg = <0>; + }; + + phy1: ethernet-phy@1 { /* Marvell 88E1318 */ + reg = <1>; + }; + }; + + ethernet@70000 { + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; + + ethernet@74000 { + status = "okay"; + phy = <&phy1>; + phy-mode = "rgmii-id"; + }; + + /* Front USB 2.0 port */ + usb@50000 { + status = "okay"; + }; + + i2c@11000 { + compatible = "marvell,mv64xxx-i2c"; + clock-frequency = <400000>; + status = "okay"; + + /* Controller for rear fan #1 of 3 (Protechnic + * MGT4012XB-O20, 8000RPM) near eSATA port */ + g762_fan1: g762@3e { + compatible = "gmt,g762"; + reg = <0x3e>; + clocks = <&g762_clk>; /* input clock */ + fan_gear_mode = <0>; + fan_startv = <1>; + pwm_polarity = <0>; + }; + + /* Controller for rear (center) fan #2 of 3 */ + g762_fan2: g762@48 { + compatible = "gmt,g762"; + reg = <0x48>; + clocks = <&g762_clk>; /* input clock */ + fan_gear_mode = <0>; + fan_startv = <1>; + pwm_polarity = <0>; + }; + + /* Controller for rear fan #3 of 3 */ + g762_fan3: g762@49 { + compatible = "gmt,g762"; + reg = <0x49>; + clocks = <&g762_clk>; /* input clock */ + fan_gear_mode = <0>; + fan_startv = <1>; + pwm_polarity = <0>; + }; + + /* Temperature sensor */ + g751: g751@4c { + compatible = "gmt,g751"; + reg = <0x4c>; + }; + }; + }; + }; + + clocks { + g762_clk: g762-oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&sata1_led_pin &sata2_led_pin &err_led_pin + &sata3_led_pin &sata4_led_pin>; + pinctrl-names = "default"; + + red-sata1-led { + label = "rn2120:red:sata1"; + gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + red-sata2-led { + label = "rn2120:red:sata2"; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + red-sata3-led { + label = "rn2120:red:sata3"; + gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + red-sata4-led { + label = "rn2120:red:sata4"; + gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + red-err-led { + label = "rn2120:red:err"; + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&power_button_pin &reset_button_pin>; + pinctrl-names = "default"; + + power-button { + label = "Power Button"; + linux,code = ; + gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>; + }; + + reset-button { + label = "Reset Button"; + linux,code = ; + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + pinctrl-0 = <&poweroff>; + pinctrl-names = "default"; + gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + }; +}; -- cgit v1.1 From 46ca506c43d64e11257a0a113701e9bcccf52416 Mon Sep 17 00:00:00 2001 From: Arnaud Ebalard Date: Sat, 30 Nov 2013 16:13:44 +0100 Subject: ARM: kirkwood: Add support for NETGEAR ReadyNAS NV+ v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Almost all hardware parts of the NETGEAR ReadyNAS NV+ v2 ([1] for more details) are supported by mainline kernel. The only missing elements in provided .dts file are: - the front LCD module (Winstar WINSTAR WH1602): driver development is ongoing. This is the same LCD module as on ReadyNAS 104. - the Macronix MX25L512 512Kbit SPI flash: no time to play with it yet. The device is the big brother (4 vs 2 bay) of the ReadyNAS Duo v2. The main differences are some additional LEDs for the disks, a Marvell 88SM4140 SATA Port multiplier (no driver required to access the disk) and previously described LCD module. Otherwise, it shares the same SoC (kirkwood 88F6282), RAM (256MB), NAND (128MB), RTC chip (Ricoh rs5c372a), fan controller (GMT G762), XHCI controller (NEC/Renesas µPD720200). [1]: http://natisbad.org/NAS5/ Signed-off-by: Arnaud Ebalard Signed-off-by: Jason Cooper --- arch/arm/boot/dts/Makefile | 1 + .../boot/dts/kirkwood-netgear_readynas_nv+_v2.dts | 270 +++++++++++++++++++++ 2 files changed, 271 insertions(+) create mode 100644 arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts (limited to 'arch') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 6881b6c..adcc606 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -90,6 +90,7 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \ kirkwood-mplcec4.dtb \ kirkwood-mv88f6281gtw-ge.dtb \ kirkwood-netgear_readynas_duo_v2.dtb \ + kirkwood-netgear_readynas_nv+_v2.dtb \ kirkwood-ns2.dtb \ kirkwood-ns2lite.dtb \ kirkwood-ns2max.dtb \ diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts new file mode 100644 index 0000000..72a3883 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts @@ -0,0 +1,270 @@ +/* + * Device Tree file for NETGEAR ReadyNAS NV+ v2 + * + * Copyright (C) 2013, Arnaud EBALARD + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +/dts-v1/; + +#include +#include +#include "kirkwood.dtsi" +#include "kirkwood-6282.dtsi" + +/ { + model = "NETGEAR ReadyNAS NV+ v2"; + compatible = "netgear,readynas-nv+-v2", "netgear,readynas", "marvell,kirkwood-88f6282", "marvell,kirkwood"; + + memory { /* 256 MB */ + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + }; + + mbus { + pcie-controller { + status = "okay"; + + /* Connected to NEC uPD720200 USB 3.0 controller */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + }; + }; + + ocp@f1000000 { + pinctrl: pinctrl@10000 { + pmx_button_power: pmx-button-power { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + + pmx_button_backup: pmx-button-backup { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + + pmx_button_reset: pmx-button-reset { + marvell,pins = "mpp13"; + marvell,function = "gpio"; + }; + + pmx_led_blue_power: pmx-led-blue-power { + marvell,pins = "mpp31"; + marvell,function = "gpio"; + }; + + pmx_led_blue_backup: pmx-led-blue-backup { + marvell,pins = "mpp22"; + marvell,function = "gpio"; + }; + + pmx_led_blue_disk1: pmx-led-blue-disk1 { + marvell,pins = "mpp20"; + marvell,function = "gpio"; + }; + + pmx_led_blue_disk2: pmx-led-blue-disk2 { + marvell,pins = "mpp23"; + marvell,function = "gpio"; + }; + + pmx_led_blue_disk3: pmx-led-blue-disk3 { + marvell,pins = "mpp24"; + marvell,function = "gpio"; + }; + + pmx_led_blue_disk4: pmx-led-blue-disk4 { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + + pmx_poweroff: pmx-poweroff { + marvell,pins = "mpp30"; + marvell,function = "gpio"; + }; + }; + + clocks { + g762_clk: g762-oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <8192>; + }; + }; + + i2c@11000 { + status = "okay"; + + rs5c372a: rs5c372a@32 { + compatible = "ricoh,rs5c372a"; + reg = <0x32>; + }; + + g762: g762@3e { + compatible = "gmt,g762"; + reg = <0x3e>; + clocks = <&g762_clk>; /* input clock */ + fan_gear_mode = <0>; + fan_startv = <1>; + pwm_polarity = <0>; + }; + }; + + serial@12000 { + pinctrl-0 = <&pmx_uart0>; + pinctrl-names = "default"; + status = "okay"; + }; + + sata@80000 { /* Connected to Marvell 88SM4140 SATA port multiplier */ + status = "okay"; + nr-ports = <1>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = < &pmx_led_blue_power &pmx_led_blue_backup + &pmx_led_blue_disk1 &pmx_led_blue_disk2 + &pmx_led_blue_disk3 &pmx_led_blue_disk3 >; + pinctrl-names = "default"; + + power_led { + label = "status:blue:power_led"; + gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + backup_led { + label = "status:blue:backup_led"; + gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; + }; + + disk1_led { + label = "status:blue:disk1_led"; + gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; + }; + + disk2_led { + label = "status:blue:disk2_led"; + gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; + }; + + disk3_led { + label = "status:blue:disk3_led"; + gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; + }; + + disk4_led { + label = "status:blue:disk4_led"; + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pmx_button_power &pmx_button_backup + &pmx_button_reset>; + pinctrl-names = "default"; + + power-button { + label = "Power Button"; + linux,code = ; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; + + reset-button { + label = "Reset Button"; + linux,code = ; + gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; + }; + + backup-button { + label = "Backup Button"; + linux,code = ; + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + pinctrl-0 = <&pmx_poweroff>; + pinctrl-names = "default"; + gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + usb3_regulator: usb3-regulator { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "USB 3.0 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&nand { + status = "okay"; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x180000>; + read-only; + }; + + partition@180000 { + label = "u-boot-env"; + reg = <0x180000 0x20000>; + }; + + partition@200000 { + label = "uImage"; + reg = <0x0200000 0x600000>; + }; + + partition@800000 { + label = "minirootfs"; + reg = <0x0800000 0x1000000>; + }; + + partition@1800000 { + label = "jffs2"; + reg = <0x1800000 0x6800000>; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { /* Marvell 88E1318 */ + device_type = "ethernet-phy"; + reg = <0>; + }; +}; + +ð0 { + status = "okay"; + + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; -- cgit v1.1 From 1bf17b828e45e3baf758b18e2ec104a347a31055 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Mon, 16 Sep 2013 12:02:30 +0100 Subject: ARM: STi: OF: Fix a typo in pincfg header This patch fixes a typo for OD define in st-pincfg header file. Reported-by: Maxime Coquelin Signed-off-by: Srinivas Kandagatla --- arch/arm/boot/dts/st-pincfg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/st-pincfg.h b/arch/arm/boot/dts/st-pincfg.h index 8c45d85..4851c38 100644 --- a/arch/arm/boot/dts/st-pincfg.h +++ b/arch/arm/boot/dts/st-pincfg.h @@ -15,7 +15,7 @@ /* Pull Up */ #define PU (1 << 26) /* Open Drain */ -#define OD (1 << 26) +#define OD (1 << 25) #define RT (1 << 23) #define INVERTCLK (1 << 22) #define CLKNOTDATA (1 << 21) -- cgit v1.1 From f53e99a9b4f09fe39336547c7a6a9e1cb7a25907 Mon Sep 17 00:00:00 2001 From: Maxime COQUELIN Date: Wed, 6 Nov 2013 09:25:13 +0100 Subject: ARM: STi: Supply I2C configuration to STiH416 SoC This patch supplies I2C configuration to STiH416 SoC. Signed-off-by: Maxime Coquelin Acked-by: Srinivas Kandagatla --- arch/arm/boot/dts/stih416-pinctrl.dtsi | 35 ++++++++++++++++++++++ arch/arm/boot/dts/stih416.dtsi | 53 ++++++++++++++++++++++++++++++++++ 2 files changed, 88 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi index 0f246c9..b29ff4b 100644 --- a/arch/arm/boot/dts/stih416-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi @@ -97,6 +97,24 @@ }; }; }; + + sbc_i2c0 { + pinctrl_sbc_i2c0_default: sbc_i2c0-default { + st,pins { + sda = <&PIO4 6 ALT1 BIDIR>; + scl = <&PIO4 5 ALT1 BIDIR>; + }; + }; + }; + + sbc_i2c1 { + pinctrl_sbc_i2c1_default: sbc_i2c1-default { + st,pins { + sda = <&PIO3 2 ALT2 BIDIR>; + scl = <&PIO3 1 ALT2 BIDIR>; + }; + }; + }; }; pin-controller-front { @@ -175,6 +193,23 @@ }; }; + i2c0 { + pinctrl_i2c0_default: i2c0-default { + st,pins { + sda = <&PIO9 3 ALT1 BIDIR>; + scl = <&PIO9 2 ALT1 BIDIR>; + }; + }; + }; + + i2c1 { + pinctrl_i2c1_default: i2c1-default { + st,pins { + sda = <&PIO12 1 ALT1 BIDIR>; + scl = <&PIO12 0 ALT1 BIDIR>; + }; + }; + }; }; pin-controller-rear { diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi index 1a0326e..b7ab47b 100644 --- a/arch/arm/boot/dts/stih416.dtsi +++ b/arch/arm/boot/dts/stih416.dtsi @@ -9,6 +9,7 @@ #include "stih41x.dtsi" #include "stih416-clock.dtsi" #include "stih416-pinctrl.dtsi" +#include / { L2: cache-controller { compatible = "arm,pl310-cache"; @@ -92,5 +93,57 @@ pinctrl-0 = <&pinctrl_sbc_serial1>; clocks = <&CLK_SYSIN>; }; + + i2c@fed40000 { + compatible = "st,comms-ssc4-i2c"; + reg = <0xfed40000 0x110>; + interrupts = ; + clocks = <&CLK_S_ICN_REG_0>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_default>; + + status = "disabled"; + }; + + i2c@fed41000 { + compatible = "st,comms-ssc4-i2c"; + reg = <0xfed41000 0x110>; + interrupts = ; + clocks = <&CLK_S_ICN_REG_0>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_default>; + + status = "disabled"; + }; + + i2c@fe540000 { + compatible = "st,comms-ssc4-i2c"; + reg = <0xfe540000 0x110>; + interrupts = ; + clocks = <&CLK_SYSIN>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sbc_i2c0_default>; + + status = "disabled"; + }; + + i2c@fe541000 { + compatible = "st,comms-ssc4-i2c"; + reg = <0xfe541000 0x110>; + interrupts = ; + clocks = <&CLK_SYSIN>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sbc_i2c1_default>; + + status = "disabled"; + }; }; }; -- cgit v1.1 From 5bbb75273f3f26392d82acdfc2cde8c34f51033b Mon Sep 17 00:00:00 2001 From: Maxime COQUELIN Date: Wed, 6 Nov 2013 09:25:14 +0100 Subject: ARM: STi: Supply I2C configuration to STiH415 SoC This patch supplies I2C configuration to STiH415 SoC. Signed-off-by: Maxime Coquelin Acked-by: Srinivas Kandagatla --- arch/arm/boot/dts/stih415-pinctrl.dtsi | 36 +++++++++++++++++++++++ arch/arm/boot/dts/stih415.dtsi | 53 ++++++++++++++++++++++++++++++++++ 2 files changed, 89 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi index 1d322b2..e56449d 100644 --- a/arch/arm/boot/dts/stih415-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih415-pinctrl.dtsi @@ -86,6 +86,24 @@ }; }; }; + + sbc_i2c0 { + pinctrl_sbc_i2c0_default: sbc_i2c0-default { + st,pins { + sda = <&PIO4 6 ALT1 BIDIR>; + scl = <&PIO4 5 ALT1 BIDIR>; + }; + }; + }; + + sbc_i2c1 { + pinctrl_sbc_i2c1_default: sbc_i2c1-default { + st,pins { + sda = <&PIO3 2 ALT2 BIDIR>; + scl = <&PIO3 1 ALT2 BIDIR>; + }; + }; + }; }; pin-controller-front { @@ -143,6 +161,24 @@ reg = <0x7000 0x100>; st,bank-name = "PIO12"; }; + + i2c0 { + pinctrl_i2c0_default: i2c0-default { + st,pins { + sda = <&PIO9 3 ALT1 BIDIR>; + scl = <&PIO9 2 ALT1 BIDIR>; + }; + }; + }; + + i2c1 { + pinctrl_i2c1_default: i2c1-default { + st,pins { + sda = <&PIO12 1 ALT1 BIDIR>; + scl = <&PIO12 0 ALT1 BIDIR>; + }; + }; + }; }; pin-controller-rear { diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi index 74ab8de..d9c7dd1 100644 --- a/arch/arm/boot/dts/stih415.dtsi +++ b/arch/arm/boot/dts/stih415.dtsi @@ -9,6 +9,7 @@ #include "stih41x.dtsi" #include "stih415-clock.dtsi" #include "stih415-pinctrl.dtsi" +#include / { L2: cache-controller { @@ -83,5 +84,57 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sbc_serial1>; }; + + i2c@fed40000 { + compatible = "st,comms-ssc4-i2c"; + reg = <0xfed40000 0x110>; + interrupts = ; + clocks = <&CLKS_ICN_REG_0>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_default>; + + status = "disabled"; + }; + + i2c@fed41000 { + compatible = "st,comms-ssc4-i2c"; + reg = <0xfed41000 0x110>; + interrupts = ; + clocks = <&CLKS_ICN_REG_0>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_default>; + + status = "disabled"; + }; + + i2c@fe540000 { + compatible = "st,comms-ssc4-i2c"; + reg = <0xfe540000 0x110>; + interrupts = ; + clocks = <&CLK_SYSIN>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sbc_i2c0_default>; + + status = "disabled"; + }; + + i2c@fe541000 { + compatible = "st,comms-ssc4-i2c"; + reg = <0xfe541000 0x110>; + interrupts = ; + clocks = <&CLK_SYSIN>; + clock-names = "ssc"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sbc_i2c1_default>; + + status = "disabled"; + }; }; }; -- cgit v1.1 From c6fddbd47f04ba40122000bb3cc6f7eff71f2b6a Mon Sep 17 00:00:00 2001 From: Maxime COQUELIN Date: Wed, 6 Nov 2013 09:25:15 +0100 Subject: ARM: STi: Add I2C config to B2000 and B2020 boards This patch supplies I2C configuration to B2000 and B2020 based on either STiH415 or STiH416 SoCs. Signed-off-by: Maxime Coquelin Acked-by: Srinivas Kandagatla --- arch/arm/boot/dts/stih41x-b2000.dtsi | 9 +++++++++ arch/arm/boot/dts/stih41x-b2020.dtsi | 22 ++++++++++++++++++++++ 2 files changed, 31 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/stih41x-b2000.dtsi b/arch/arm/boot/dts/stih41x-b2000.dtsi index 8e694d2..1e6aa92 100644 --- a/arch/arm/boot/dts/stih41x-b2000.dtsi +++ b/arch/arm/boot/dts/stih41x-b2000.dtsi @@ -37,5 +37,14 @@ }; }; + /* HDMI Tx I2C */ + i2c@fed41000 { + /* HDMI V1.3a supports Standard mode only */ + clock-frequency = <100000>; + i2c-min-scl-pulse-width-us = <0>; + i2c-min-sda-pulse-width-us = <5>; + + status = "okay"; + }; }; }; diff --git a/arch/arm/boot/dts/stih41x-b2020.dtsi b/arch/arm/boot/dts/stih41x-b2020.dtsi index 133e181..0ef0a69 100644 --- a/arch/arm/boot/dts/stih41x-b2020.dtsi +++ b/arch/arm/boot/dts/stih41x-b2020.dtsi @@ -38,5 +38,27 @@ default-state = "off"; }; }; + + i2c@fed40000 { + status = "okay"; + }; + + /* HDMI Tx I2C */ + i2c@fed41000 { + /* HDMI V1.3a supports Standard mode only */ + clock-frequency = <100000>; + i2c-min-scl-pulse-width-us = <0>; + i2c-min-sda-pulse-width-us = <5>; + + status = "okay"; + }; + + i2c@fe540000 { + status = "okay"; + }; + + i2c@fe541000 { + status = "okay"; + }; }; }; -- cgit v1.1 From 78d1632183454dba46ca8295484a5e7603acdc18 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 17 Jun 2013 23:34:27 +0200 Subject: ARM: integrator: delete static core module mappings Now that the core module base is taken from the device tree both for platform initialization and cpufreq, let's delete the static mappings. Signed-off-by: Linus Walleij --- arch/arm/mach-integrator/integrator_ap.c | 8 +------- arch/arm/mach-integrator/integrator_cp.c | 8 -------- 2 files changed, 1 insertion(+), 15 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c index d50dc2d..a762712 100644 --- a/arch/arm/mach-integrator/integrator_ap.c +++ b/arch/arm/mach-integrator/integrator_ap.c @@ -64,6 +64,7 @@ /* Base address to the AP system controller */ void __iomem *ap_syscon_base; + /* * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx * is the (PA >> 12). @@ -73,12 +74,10 @@ void __iomem *ap_syscon_base; */ #define VA_IC_BASE __io_address(INTEGRATOR_IC_BASE) #define VA_EBI_BASE __io_address(INTEGRATOR_EBI_BASE) -#define VA_CMIC_BASE __io_address(INTEGRATOR_HDR_IC) /* * Logical Physical * ef000000 Cache flush - * f1000000 10000000 Core module registers * f1100000 11000000 System controller registers * f1200000 12000000 EBI registers * f1300000 13000000 Counter/Timer @@ -91,11 +90,6 @@ void __iomem *ap_syscon_base; static struct map_desc ap_io_desc[] __initdata __maybe_unused = { { - .virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE), - .pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE), - .length = SZ_4K, - .type = MT_DEVICE - }, { .virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE), .pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE), .length = SZ_4K, diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c index 4fc0a19..916c0f3 100644 --- a/arch/arm/mach-integrator/integrator_cp.c +++ b/arch/arm/mach-integrator/integrator_cp.c @@ -64,8 +64,6 @@ static void __iomem *intcp_con_base; /* * Logical Physical - * f1000000 10000000 Core module registers - * f1100000 11000000 System controller registers * f1200000 12000000 EBI registers * f1300000 13000000 Counter/Timer * f1400000 14000000 Interrupt controller @@ -74,16 +72,10 @@ static void __iomem *intcp_con_base; * f1a00000 1a000000 Debug LEDs * fc900000 c9000000 GPIO * fca00000 ca000000 SIC - * fcb00000 cb000000 CP system control */ static struct map_desc intcp_io_desc[] __initdata __maybe_unused = { { - .virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE), - .pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE), - .length = SZ_4K, - .type = MT_DEVICE - }, { .virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE), .pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE), .length = SZ_4K, -- cgit v1.1 From 307b96677c98bc444262e3d1a7d26c0ca8a1c6e0 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 17 Jun 2013 23:58:25 +0200 Subject: ARM: integrator: move EBI to the device tree This moves the External Bus Interface (EBI) over to a device tree node and deletes the static mappings from the platform. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/integrator.dtsi | 5 +++ arch/arm/mach-integrator/integrator_ap.c | 52 ++++++++++++++++++-------------- arch/arm/mach-integrator/integrator_cp.c | 6 ---- 3 files changed, 35 insertions(+), 28 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/integrator.dtsi b/arch/arm/boot/dts/integrator.dtsi index 0f06f86..88e3d477 100644 --- a/arch/arm/boot/dts/integrator.dtsi +++ b/arch/arm/boot/dts/integrator.dtsi @@ -10,6 +10,11 @@ reg = <0x10000000 0x200>; }; + ebi@12000000 { + compatible = "arm,external-bus-interface"; + reg = <0x12000000 0x100>; + }; + timer@13000000 { reg = <0x13000000 0x100>; interrupt-parent = <&pic>; diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c index a762712..cc1d3fe 100644 --- a/arch/arm/mach-integrator/integrator_ap.c +++ b/arch/arm/mach-integrator/integrator_ap.c @@ -63,6 +63,8 @@ /* Base address to the AP system controller */ void __iomem *ap_syscon_base; +/* Base address to the external bus interface */ +static void __iomem *ebi_base; /* @@ -73,13 +75,11 @@ void __iomem *ap_syscon_base; * just for now). */ #define VA_IC_BASE __io_address(INTEGRATOR_IC_BASE) -#define VA_EBI_BASE __io_address(INTEGRATOR_EBI_BASE) /* * Logical Physical * ef000000 Cache flush * f1100000 11000000 System controller registers - * f1200000 12000000 EBI registers * f1300000 13000000 Counter/Timer * f1400000 14000000 Interrupt controller * f1600000 16000000 UART 0 @@ -90,11 +90,6 @@ void __iomem *ap_syscon_base; static struct map_desc ap_io_desc[] __initdata __maybe_unused = { { - .virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE), - .pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE), - .length = SZ_4K, - .type = MT_DEVICE - }, { .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE), .pfn = __phys_to_pfn(INTEGRATOR_CT_BASE), .length = SZ_4K, @@ -168,9 +163,6 @@ device_initcall(irq_syscore_init); /* * Flash handling. */ -#define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET) -#define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET) - static int ap_flash_init(struct platform_device *dev) { u32 tmp; @@ -178,13 +170,15 @@ static int ap_flash_init(struct platform_device *dev) writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET); - tmp = readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE; - writel(tmp, EBI_CSR1); + tmp = readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) | + INTEGRATOR_EBI_WRITE_ENABLE; + writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET); - if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) { - writel(0xa05f, EBI_LOCK); - writel(tmp, EBI_CSR1); - writel(0, EBI_LOCK); + if (!(readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) + & INTEGRATOR_EBI_WRITE_ENABLE)) { + writel(0xa05f, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET); + writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET); + writel(0, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET); } return 0; } @@ -196,13 +190,15 @@ static void ap_flash_exit(struct platform_device *dev) writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET); - tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE; - writel(tmp, EBI_CSR1); + tmp = readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) & + ~INTEGRATOR_EBI_WRITE_ENABLE; + writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET); - if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) { - writel(0xa05f, EBI_LOCK); - writel(tmp, EBI_CSR1); - writel(0, EBI_LOCK); + if (readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) & + INTEGRATOR_EBI_WRITE_ENABLE) { + writel(0xa05f, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET); + writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET); + writel(0, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET); } } @@ -469,11 +465,17 @@ static const struct of_device_id ap_syscon_match[] = { { }, }; +static const struct of_device_id ebi_match[] = { + { .compatible = "arm,external-bus-interface"}, + { }, +}; + static void __init ap_init_of(void) { unsigned long sc_dec; struct device_node *root; struct device_node *syscon; + struct device_node *ebi; struct device *parent; struct soc_device *soc_dev; struct soc_device_attribute *soc_dev_attr; @@ -489,10 +491,16 @@ static void __init ap_init_of(void) syscon = of_find_matching_node(root, ap_syscon_match); if (!syscon) return; + ebi = of_find_matching_node(root, ebi_match); + if (!ebi) + return; ap_syscon_base = of_iomap(syscon, 0); if (!ap_syscon_base) return; + ebi_base = of_iomap(ebi, 0); + if (!ebi_base) + return; ap_sc_id = readl(ap_syscon_base); diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c index 916c0f3..5e84149 100644 --- a/arch/arm/mach-integrator/integrator_cp.c +++ b/arch/arm/mach-integrator/integrator_cp.c @@ -64,7 +64,6 @@ static void __iomem *intcp_con_base; /* * Logical Physical - * f1200000 12000000 EBI registers * f1300000 13000000 Counter/Timer * f1400000 14000000 Interrupt controller * f1600000 16000000 UART 0 @@ -76,11 +75,6 @@ static void __iomem *intcp_con_base; static struct map_desc intcp_io_desc[] __initdata __maybe_unused = { { - .virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE), - .pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE), - .length = SZ_4K, - .type = MT_DEVICE - }, { .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE), .pfn = __phys_to_pfn(INTEGRATOR_CT_BASE), .length = SZ_4K, -- cgit v1.1 From 23301190d2a9a8c41a3d9f626791fa7a65f8ccfa Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Wed, 4 Dec 2013 16:51:38 +0100 Subject: ARM: DT: Kirkwood: Use symbolic names from input.h Replace the numeric key value with a symbolic name from Signed-off-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood-cloudbox.dts | 2 +- arch/arm/boot/dts/kirkwood-dnskw.dtsi | 6 +++--- arch/arm/boot/dts/kirkwood-ib62x0.dts | 4 ++-- arch/arm/boot/dts/kirkwood-iconnect.dts | 4 ++-- arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts | 6 +++--- arch/arm/boot/dts/kirkwood-lsxl.dtsi | 6 +++--- arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts | 4 ++-- arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts | 1 - arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts | 1 - arch/arm/boot/dts/kirkwood-ns2-common.dtsi | 2 +- arch/arm/boot/dts/kirkwood-nsa310.dts | 6 +++--- arch/arm/boot/dts/kirkwood-nsa310a.dts | 6 +++--- arch/arm/boot/dts/kirkwood-openblocks_a6.dts | 2 +- arch/arm/boot/dts/kirkwood-openblocks_a7.dts | 2 +- arch/arm/boot/dts/kirkwood-ts219-6281.dts | 4 ++-- arch/arm/boot/dts/kirkwood-ts219-6282.dts | 4 ++-- arch/arm/boot/dts/kirkwood.dtsi | 1 + 17 files changed, 30 insertions(+), 31 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/kirkwood-cloudbox.dts b/arch/arm/boot/dts/kirkwood-cloudbox.dts index 142b9cd..17123f2 100644 --- a/arch/arm/boot/dts/kirkwood-cloudbox.dts +++ b/arch/arm/boot/dts/kirkwood-cloudbox.dts @@ -66,7 +66,7 @@ button@1 { label = "Power push button"; - linux,code = <116>; + linux,code = ; gpios = <&gpio0 16 1>; }; }; diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi index aefa375..1d680d1 100644 --- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi +++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi @@ -15,17 +15,17 @@ button@1 { label = "Power button"; - linux,code = <116>; + linux,code = ; gpios = <&gpio1 2 1>; }; button@2 { label = "USB unmount button"; - linux,code = <161>; + linux,code = ; gpios = <&gpio1 15 1>; }; button@3 { label = "Reset button"; - linux,code = <0x198>; + linux,code = ; gpios = <&gpio1 16 1>; }; }; diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts index dbc9033..c376b75 100644 --- a/arch/arm/boot/dts/kirkwood-ib62x0.dts +++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts @@ -63,12 +63,12 @@ button@1 { label = "USB Copy"; - linux,code = <133>; + linux,code = ; gpios = <&gpio0 29 1>; }; button@2 { label = "Reset"; - linux,code = <0x198>; + linux,code = ; gpios = <&gpio0 28 1>; }; }; diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts index 399fb0c..52ed751 100644 --- a/arch/arm/boot/dts/kirkwood-iconnect.dts +++ b/arch/arm/boot/dts/kirkwood-iconnect.dts @@ -137,13 +137,13 @@ button@1 { label = "OTB Button"; - linux,code = <133>; + linux,code = ; gpios = <&gpio1 3 1>; debounce-interval = <100>; }; button@2 { label = "Reset"; - linux,code = <0x198>; + linux,code = ; gpios = <&gpio0 12 1>; debounce-interval = <100>; }; diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts index b9de441..cdee769 100644 --- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts +++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts @@ -154,17 +154,17 @@ Power { label = "Power Button"; - linux,code = <116>; + linux,code = ; gpios = <&gpio0 14 1>; }; Reset { label = "Reset Button"; - linux,code = <0x198>; + linux,code = ; gpios = <&gpio0 12 1>; }; OTB { label = "OTB Button"; - linux,code = <133>; + linux,code = ; gpios = <&gpio1 3 1>; }; }; diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi index bc34a60..b284474 100644 --- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi +++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi @@ -108,18 +108,18 @@ button@1 { label = "Function Button"; - linux,code = <357>; + linux,code = ; gpios = <&gpio1 9 1>; }; button@2 { label = "Power-on Switch"; - linux,code = <0>; + linux,code = ; linux,input-type = <5>; gpios = <&gpio1 10 1>; }; button@3 { label = "Power-auto Switch"; - linux,code = <1>; + linux,code = ; linux,input-type = <5>; gpios = <&gpio1 11 1>; }; diff --git a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts index 6317e1d..ade4324 100644 --- a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts +++ b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts @@ -113,12 +113,12 @@ button@1 { label = "SWR Button"; - linux,code = <0x198>; /* KEY_RESTART */ + linux,code = ; gpios = <&gpio1 15 1>; }; button@2 { label = "WPS Button"; - linux,code = <0x211>; /* KEY_WPS_BUTTON */ + linux,code = ; gpios = <&gpio1 14 1>; }; }; diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts index 3b1a365..57e08b3 100644 --- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts +++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts @@ -11,7 +11,6 @@ /dts-v1/; -#include #include #include "kirkwood.dtsi" #include "kirkwood-6282.dtsi" diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts index 72a3883..3ce9f63 100644 --- a/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts +++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts @@ -11,7 +11,6 @@ /dts-v1/; -#include #include #include "kirkwood.dtsi" #include "kirkwood-6282.dtsi" diff --git a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi index 2fcb82e..3101aec 100644 --- a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi +++ b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi @@ -64,7 +64,7 @@ button@1 { label = "Power push button"; - linux,code = <116>; + linux,code = ; gpios = <&gpio1 0 0>; }; }; diff --git a/arch/arm/boot/dts/kirkwood-nsa310.dts b/arch/arm/boot/dts/kirkwood-nsa310.dts index b5418bc..c45a26c 100644 --- a/arch/arm/boot/dts/kirkwood-nsa310.dts +++ b/arch/arm/boot/dts/kirkwood-nsa310.dts @@ -119,17 +119,17 @@ button@1 { label = "Power Button"; - linux,code = <116>; + linux,code = ; gpios = <&gpio1 14 0>; }; button@2 { label = "Copy Button"; - linux,code = <133>; + linux,code = ; gpios = <&gpio1 5 1>; }; button@3 { label = "Reset Button"; - linux,code = <0x198>; + linux,code = ; gpios = <&gpio1 4 1>; }; }; diff --git a/arch/arm/boot/dts/kirkwood-nsa310a.dts b/arch/arm/boot/dts/kirkwood-nsa310a.dts index ab0212b..874df7d 100644 --- a/arch/arm/boot/dts/kirkwood-nsa310a.dts +++ b/arch/arm/boot/dts/kirkwood-nsa310a.dts @@ -107,17 +107,17 @@ button@1 { label = "Power Button"; - linux,code = <116>; + linux,code = ; gpios = <&gpio1 14 0>; }; button@2 { label = "Copy Button"; - linux,code = <133>; + linux,code = ; gpios = <&gpio1 5 1>; }; button@3 { label = "Reset Button"; - linux,code = <0x198>; + linux,code = ; gpios = <&gpio1 4 1>; }; }; diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts index f0e3d21..6c171e0 100644 --- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts +++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts @@ -124,7 +124,7 @@ button@1 { label = "Init Button"; - linux,code = <116>; + linux,code = ; gpios = <&gpio1 6 0>; }; }; diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a7.dts b/arch/arm/boot/dts/kirkwood-openblocks_a7.dts index 851fb2a..c97bad4 100644 --- a/arch/arm/boot/dts/kirkwood-openblocks_a7.dts +++ b/arch/arm/boot/dts/kirkwood-openblocks_a7.dts @@ -149,7 +149,7 @@ button@1 { label = "Init Button"; - linux,code = <116>; + linux,code = ; gpios = <&gpio1 6 0>; }; }; diff --git a/arch/arm/boot/dts/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/kirkwood-ts219-6281.dts index f755bc1..89f7094 100644 --- a/arch/arm/boot/dts/kirkwood-ts219-6281.dts +++ b/arch/arm/boot/dts/kirkwood-ts219-6281.dts @@ -41,12 +41,12 @@ button@1 { label = "USB Copy"; - linux,code = <133>; + linux,code = ; gpios = <&gpio0 15 1>; }; button@2 { label = "Reset"; - linux,code = <0x198>; + linux,code = ; gpios = <&gpio0 16 1>; }; }; diff --git a/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/kirkwood-ts219-6282.dts index 345562f..6976afb 100644 --- a/arch/arm/boot/dts/kirkwood-ts219-6282.dts +++ b/arch/arm/boot/dts/kirkwood-ts219-6282.dts @@ -51,12 +51,12 @@ button@1 { label = "USB Copy"; - linux,code = <133>; + linux,code = ; gpios = <&gpio1 11 1>; }; button@2 { label = "Reset"; - linux,code = <0x198>; + linux,code = ; gpios = <&gpio1 5 1>; }; }; diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index 8b73c80..477c0b5 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -1,4 +1,5 @@ /include/ "skeleton.dtsi" +#include #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) -- cgit v1.1 From 3a31f2d7fce39f3bca0106e69d21119eafb28c85 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Wed, 4 Dec 2013 16:51:39 +0100 Subject: ARM: DT: Kirkwood: Use symbolic names from gpio.h Use GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW instead of 0 and 1. Signed-off-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood-cloudbox.dts | 8 +++---- arch/arm/boot/dts/kirkwood-db.dtsi | 4 ++-- arch/arm/boot/dts/kirkwood-dns320.dts | 10 ++++----- arch/arm/boot/dts/kirkwood-dns325.dts | 10 ++++----- arch/arm/boot/dts/kirkwood-dnskw.dtsi | 12 +++++----- arch/arm/boot/dts/kirkwood-dockstar.dts | 4 ++-- arch/arm/boot/dts/kirkwood-dreamplug.dts | 6 ++--- arch/arm/boot/dts/kirkwood-goflexnet.dts | 22 +++++++++--------- .../arm/boot/dts/kirkwood-guruplug-server-plus.dts | 8 +++---- arch/arm/boot/dts/kirkwood-ib62x0.dts | 12 +++++----- arch/arm/boot/dts/kirkwood-iconnect.dts | 20 ++++++++--------- arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts | 14 ++++++------ arch/arm/boot/dts/kirkwood-km_kirkwood.dts | 4 ++-- arch/arm/boot/dts/kirkwood-lsxl.dtsi | 22 +++++++++--------- arch/arm/boot/dts/kirkwood-mplcec4.dts | 14 ++++++------ arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts | 10 ++++----- .../boot/dts/kirkwood-netgear_readynas_duo_v2.dts | 1 - .../boot/dts/kirkwood-netgear_readynas_nv+_v2.dts | 1 - arch/arm/boot/dts/kirkwood-ns2-common.dtsi | 6 ++--- arch/arm/boot/dts/kirkwood-ns2lite.dts | 2 +- arch/arm/boot/dts/kirkwood-ns2max.dts | 10 ++++----- arch/arm/boot/dts/kirkwood-ns2mini.dts | 10 ++++----- arch/arm/boot/dts/kirkwood-nsa310-common.dtsi | 4 ++-- arch/arm/boot/dts/kirkwood-nsa310.dts | 26 +++++++++++----------- arch/arm/boot/dts/kirkwood-nsa310a.dts | 24 ++++++++++---------- arch/arm/boot/dts/kirkwood-openblocks_a6.dts | 8 +++---- arch/arm/boot/dts/kirkwood-openblocks_a7.dts | 8 +++---- arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts | 6 ++--- arch/arm/boot/dts/kirkwood-sheevaplug.dts | 4 ++-- arch/arm/boot/dts/kirkwood-topkick.dts | 10 ++++----- arch/arm/boot/dts/kirkwood-ts219-6281.dts | 4 ++-- arch/arm/boot/dts/kirkwood-ts219-6282.dts | 4 ++-- arch/arm/boot/dts/kirkwood.dtsi | 1 + 33 files changed, 154 insertions(+), 155 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/kirkwood-cloudbox.dts b/arch/arm/boot/dts/kirkwood-cloudbox.dts index 17123f2..bb4df40 100644 --- a/arch/arm/boot/dts/kirkwood-cloudbox.dts +++ b/arch/arm/boot/dts/kirkwood-cloudbox.dts @@ -67,7 +67,7 @@ button@1 { label = "Power push button"; linux,code = ; - gpios = <&gpio0 16 1>; + gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; }; }; @@ -76,17 +76,17 @@ red-fail { label = "cloudbox:red:fail"; - gpios = <&gpio0 14 0>; + gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; }; blue-sata { label = "cloudbox:blue:sata"; - gpios = <&gpio0 15 0>; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; }; }; gpio_poweroff { compatible = "gpio-poweroff"; - gpios = <&gpio0 17 0>; + gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm/boot/dts/kirkwood-db.dtsi b/arch/arm/boot/dts/kirkwood-db.dtsi index 053aa20..afebc15 100644 --- a/arch/arm/boot/dts/kirkwood-db.dtsi +++ b/arch/arm/boot/dts/kirkwood-db.dtsi @@ -51,8 +51,8 @@ mvsdio@90000 { pinctrl-0 = <&pmx_sdio_gpios>; pinctrl-names = "default"; - wp-gpios = <&gpio1 5 0>; - cd-gpios = <&gpio1 6 0>; + wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + cd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; status = "okay"; }; }; diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts b/arch/arm/boot/dts/kirkwood-dns320.dts index ff13b93..bf7fe8a 100644 --- a/arch/arm/boot/dts/kirkwood-dns320.dts +++ b/arch/arm/boot/dts/kirkwood-dns320.dts @@ -24,24 +24,24 @@ blue-power { label = "dns320:blue:power"; - gpios = <&gpio0 26 1>; /* GPIO 26 Active Low */ + gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; default-state = "keep"; }; blue-usb { label = "dns320:blue:usb"; - gpios = <&gpio1 11 1>; /* GPIO 43 Active Low */ + gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; }; orange-l_hdd { label = "dns320:orange:l_hdd"; - gpios = <&gpio0 28 1>; /* GPIO 28 Active Low */ + gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; }; orange-r_hdd { label = "dns320:orange:r_hdd"; - gpios = <&gpio0 27 1>; /* GPIO 27 Active Low */ + gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; }; orange-usb { label = "dns320:orange:usb"; - gpios = <&gpio1 3 1>; /* GPIO 35 Active Low */ + gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; /* GPIO 35 */ }; }; diff --git a/arch/arm/boot/dts/kirkwood-dns325.dts b/arch/arm/boot/dts/kirkwood-dns325.dts index f433043..cb9978c 100644 --- a/arch/arm/boot/dts/kirkwood-dns325.dts +++ b/arch/arm/boot/dts/kirkwood-dns325.dts @@ -24,24 +24,24 @@ white-power { label = "dns325:white:power"; - gpios = <&gpio0 26 1>; /* GPIO 26 Active Low */ + gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; default-state = "keep"; }; white-usb { label = "dns325:white:usb"; - gpios = <&gpio1 11 1>; /* GPIO 43 Active Low */ + gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; /* GPIO 43 */ }; red-l_hdd { label = "dns325:red:l_hdd"; - gpios = <&gpio0 28 1>; /* GPIO 28 Active Low */ + gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; }; red-r_hdd { label = "dns325:red:r_hdd"; - gpios = <&gpio0 27 1>; /* GPIO 27 Active Low */ + gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; }; red-usb { label = "dns325:red:usb"; - gpios = <&gpio0 29 1>; /* GPIO 29 Active Low */ + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; }; }; diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi index 1d680d1..1208756 100644 --- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi +++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi @@ -16,17 +16,17 @@ button@1 { label = "Power button"; linux,code = ; - gpios = <&gpio1 2 1>; + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; }; button@2 { label = "USB unmount button"; linux,code = ; - gpios = <&gpio1 15 1>; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; }; button@3 { label = "Reset button"; linux,code = ; - gpios = <&gpio1 16 1>; + gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; }; }; @@ -35,8 +35,8 @@ compatible = "gpio-fan"; pinctrl-0 = <&pmx_fan_high_speed &pmx_fan_low_speed>; pinctrl-names = "default"; - gpios = <&gpio1 14 1 - &gpio1 13 1>; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW + &gpio1 13 GPIO_ACTIVE_LOW>; gpio-fan,speed-map = <0 0 3000 1 6000 2>; @@ -46,7 +46,7 @@ compatible = "gpio-poweroff"; pinctrl-0 = <&pmx_power_off>; pinctrl-names = "default"; - gpios = <&gpio1 4 0>; + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; }; ocp@f1000000 { diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts index a5f1e39..2a41c75 100644 --- a/arch/arm/boot/dts/kirkwood-dockstar.dts +++ b/arch/arm/boot/dts/kirkwood-dockstar.dts @@ -42,12 +42,12 @@ health { label = "status:green:health"; - gpios = <&gpio1 14 1>; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; default-state = "keep"; }; fault { label = "status:orange:fault"; - gpios = <&gpio1 15 1>; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; }; }; regulators { diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts index 6f62af9..a755837 100644 --- a/arch/arm/boot/dts/kirkwood-dreamplug.dts +++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts @@ -87,15 +87,15 @@ bluetooth { label = "dreamplug:blue:bluetooth"; - gpios = <&gpio1 15 1>; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; }; wifi { label = "dreamplug:green:wifi"; - gpios = <&gpio1 16 1>; + gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; }; wifi-ap { label = "dreamplug:green:wifi_ap"; - gpios = <&gpio1 17 1>; + gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts index a9e98c9..c2e5129 100644 --- a/arch/arm/boot/dts/kirkwood-goflexnet.dts +++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts @@ -85,44 +85,44 @@ health { label = "status:green:health"; - gpios = <&gpio1 14 1>; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; default-state = "keep"; }; fault { label = "status:orange:fault"; - gpios = <&gpio1 15 1>; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; }; left0 { label = "status:white:left0"; - gpios = <&gpio1 10 0>; + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; }; left1 { label = "status:white:left1"; - gpios = <&gpio1 11 0>; + gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; }; left2 { label = "status:white:left2"; - gpios = <&gpio1 12 0>; + gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; }; left3 { label = "status:white:left3"; - gpios = <&gpio1 13 0>; + gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; }; right0 { label = "status:white:right0"; - gpios = <&gpio1 6 0>; + gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; }; right1 { label = "status:white:right1"; - gpios = <&gpio1 7 0>; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; }; right2 { label = "status:white:right2"; - gpios = <&gpio1 8 0>; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; }; right3 { label = "status:white:right3"; - gpios = <&gpio1 9 0>; + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; }; }; regulators { @@ -141,7 +141,7 @@ enable-active-high; regulator-always-on; regulator-boot-on; - gpio = <&gpio0 29 0>; + gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>; }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts index 4d2a70f..0b557d5 100644 --- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts +++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts @@ -60,19 +60,19 @@ health-r { label = "guruplug:red:health"; - gpios = <&gpio1 14 1>; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; }; health-g { label = "guruplug:green:health"; - gpios = <&gpio1 15 1>; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; }; wmode-r { label = "guruplug:red:wmode"; - gpios = <&gpio1 16 1>; + gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; }; wmode-g { label = "guruplug:green:wmode"; - gpios = <&gpio1 17 1>; + gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts index c376b75..6ccc788 100644 --- a/arch/arm/boot/dts/kirkwood-ib62x0.dts +++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts @@ -64,12 +64,12 @@ button@1 { label = "USB Copy"; linux,code = ; - gpios = <&gpio0 29 1>; + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; }; button@2 { label = "Reset"; linux,code = ; - gpios = <&gpio0 28 1>; + gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; }; }; @@ -81,16 +81,16 @@ green-os { label = "ib62x0:green:os"; - gpios = <&gpio0 25 0>; + gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; default-state = "keep"; }; red-os { label = "ib62x0:red:os"; - gpios = <&gpio0 22 0>; + gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; }; usb-copy { label = "ib62x0:red:usb_copy"; - gpios = <&gpio0 27 0>; + gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>; }; }; @@ -98,7 +98,7 @@ compatible = "gpio-poweroff"; pinctrl-0 = <&pmx_power_off>; pinctrl-names = "default"; - gpios = <&gpio0 24 0>; + gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts index 52ed751..f763629 100644 --- a/arch/arm/boot/dts/kirkwood-iconnect.dts +++ b/arch/arm/boot/dts/kirkwood-iconnect.dts @@ -94,37 +94,37 @@ led-level { label = "led_level"; - gpios = <&gpio1 9 0>; + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; default-state = "on"; }; power-blue { label = "power:blue"; - gpios = <&gpio1 10 0>; + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; default-state = "keep"; }; power-red { label = "power:red"; - gpios = <&gpio1 11 0>; + gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; }; usb1 { label = "usb1:blue"; - gpios = <&gpio1 12 0>; + gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; }; usb2 { label = "usb2:blue"; - gpios = <&gpio1 13 0>; + gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; }; usb3 { label = "usb3:blue"; - gpios = <&gpio1 14 0>; + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; }; usb4 { label = "usb4:blue"; - gpios = <&gpio1 15 0>; + gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; }; otb { label = "otb:blue"; - gpios = <&gpio1 16 0>; + gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; }; }; @@ -138,13 +138,13 @@ button@1 { label = "OTB Button"; linux,code = ; - gpios = <&gpio1 3 1>; + gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; debounce-interval = <100>; }; button@2 { label = "Reset"; linux,code = ; - gpios = <&gpio0 12 1>; + gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; debounce-interval = <100>; }; }; diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts index cdee769..5890006 100644 --- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts +++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts @@ -127,20 +127,20 @@ power_led { label = "status:white:power_led"; - gpios = <&gpio0 16 0>; + gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; default-state = "keep"; }; rebuild_led { label = "status:white:rebuild_led"; - gpios = <&gpio1 4 0>; + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; }; health_led { label = "status:red:health_led"; - gpios = <&gpio1 5 0>; + gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; }; backup_led { label = "status:blue:backup_led"; - gpios = <&gpio0 15 0>; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; }; }; gpio-keys { @@ -155,17 +155,17 @@ Power { label = "Power Button"; linux,code = ; - gpios = <&gpio0 14 1>; + gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; }; Reset { label = "Reset Button"; linux,code = ; - gpios = <&gpio0 12 1>; + gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; }; OTB { label = "OTB Button"; linux,code = ; - gpios = <&gpio1 3 1>; + gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts index cd44f37..5b5808e 100644 --- a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts +++ b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts @@ -38,8 +38,8 @@ i2c@0 { compatible = "i2c-gpio"; - gpios = < &gpio0 8 0 /* sda */ - &gpio0 9 0 >; /* scl */ + gpios = < &gpio0 8 GPIO_ACTIVE_HIGH /* sda */ + &gpio0 9 GPIO_ACTIVE_HIGH>; /* scl */ i2c-gpio,delay-us = <2>; /* ~100 kHz */ }; }; diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi index b284474..fc1cd3b 100644 --- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi +++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi @@ -109,19 +109,19 @@ button@1 { label = "Function Button"; linux,code = ; - gpios = <&gpio1 9 1>; + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; }; button@2 { label = "Power-on Switch"; linux,code = ; linux,input-type = <5>; - gpios = <&gpio1 10 1>; + gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; }; button@3 { label = "Power-auto Switch"; linux,code = ; linux,input-type = <5>; - gpios = <&gpio1 11 1>; + gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; }; }; @@ -134,28 +134,28 @@ led@1 { label = "lsxl:blue:func"; - gpios = <&gpio1 4 1>; + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; }; led@2 { label = "lsxl:red:alarm"; - gpios = <&gpio1 5 1>; + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; }; led@3 { label = "lsxl:amber:info"; - gpios = <&gpio1 6 1>; + gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; }; led@4 { label = "lsxl:blue:power"; - gpios = <&gpio1 7 1>; + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; default-state = "keep"; }; led@5 { label = "lsxl:red:func"; - gpios = <&gpio1 16 1>; + gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; }; }; @@ -163,13 +163,13 @@ compatible = "gpio-fan"; pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>; pinctrl-names = "default"; - gpios = <&gpio0 19 1 - &gpio0 18 1>; + gpios = <&gpio0 19 GPIO_ACTIVE_LOW + &gpio0 18 GPIO_ACTIVE_LOW>; gpio-fan,speed-map = <0 3 1500 2 3250 1 5000 0>; - alarm-gpios = <&gpio1 8 0>; + alarm-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; }; restart_poweroff { diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts index 6c1ec27..c20607c 100644 --- a/arch/arm/boot/dts/kirkwood-mplcec4.dts +++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts @@ -110,7 +110,7 @@ pinctrl-0 = <&pmx_sdio &pmx_sdio_cd>; pinctrl-names = "default"; status = "okay"; - cd-gpios = <&gpio1 15 1>; + cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; /* No WP GPIO */ }; }; @@ -126,36 +126,36 @@ health { label = "status:green:health"; - gpios = <&gpio0 7 1>; + gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; }; user1o { label = "user1:orange"; - gpios = <&gpio1 8 1>; + gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; default-state = "on"; }; user1g { label = "user1:green"; - gpios = <&gpio1 9 1>; + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; default-state = "on"; }; user0o { label = "user0:orange"; - gpios = <&gpio1 12 1>; + gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; default-state = "on"; }; user0g { label = "user0:green"; - gpios = <&gpio1 13 1>; + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; default-state = "on"; }; misc { label = "status:orange:misc"; - gpios = <&gpio1 14 1>; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; default-state = "on"; }; diff --git a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts index ade4324..dc86429 100644 --- a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts +++ b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts @@ -90,17 +90,17 @@ green-status { label = "gtw:green:Status"; - gpios = <&gpio0 20 0>; + gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; }; red-status { label = "gtw:red:Status"; - gpios = <&gpio0 21 0>; + gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; }; green-usb { label = "gtw:green:USB"; - gpios = <&gpio0 12 0>; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; }; }; @@ -114,12 +114,12 @@ button@1 { label = "SWR Button"; linux,code = ; - gpios = <&gpio1 15 1>; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; }; button@2 { label = "WPS Button"; linux,code = ; - gpios = <&gpio1 14 1>; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts index 57e08b3..4d2a8db 100644 --- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts +++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts @@ -11,7 +11,6 @@ /dts-v1/; -#include #include "kirkwood.dtsi" #include "kirkwood-6282.dtsi" diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts index 3ce9f63..7c8a0d9 100644 --- a/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts +++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts @@ -11,7 +11,6 @@ /dts-v1/; -#include #include "kirkwood.dtsi" #include "kirkwood-6282.dtsi" diff --git a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi index 3101aec..ae1ccbe 100644 --- a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi +++ b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi @@ -65,7 +65,7 @@ button@1 { label = "Power push button"; linux,code = ; - gpios = <&gpio1 0 0>; + gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; }; }; @@ -74,13 +74,13 @@ red-fail { label = "ns2:red:fail"; - gpios = <&gpio0 12 0>; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; }; }; gpio_poweroff { compatible = "gpio-poweroff"; - gpios = <&gpio0 31 0>; + gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm/boot/dts/kirkwood-ns2lite.dts b/arch/arm/boot/dts/kirkwood-ns2lite.dts index 7cea2a4..1f2ca60 100644 --- a/arch/arm/boot/dts/kirkwood-ns2lite.dts +++ b/arch/arm/boot/dts/kirkwood-ns2lite.dts @@ -25,7 +25,7 @@ blue-sata { label = "ns2:blue:sata"; - gpios = <&gpio0 30 1>; + gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; linux,default-trigger = "ide-disk"; }; }; diff --git a/arch/arm/boot/dts/kirkwood-ns2max.dts b/arch/arm/boot/dts/kirkwood-ns2max.dts index defdc77..72c78d0 100644 --- a/arch/arm/boot/dts/kirkwood-ns2max.dts +++ b/arch/arm/boot/dts/kirkwood-ns2max.dts @@ -22,10 +22,10 @@ gpio_fan { compatible = "gpio-fan"; - gpios = <&gpio0 22 1 - &gpio0 7 1 - &gpio1 1 1 - &gpio0 23 1>; + gpios = <&gpio0 22 GPIO_ACTIVE_LOW + &gpio0 7 GPIO_ACTIVE_LOW + &gpio1 1 GPIO_ACTIVE_LOW + &gpio0 23 GPIO_ACTIVE_LOW>; gpio-fan,speed-map = < 0 0 1500 15 @@ -36,7 +36,7 @@ 3300 10 4300 9 5500 8>; - alarm-gpios = <&gpio0 25 1>; + alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; }; ns2-leds { diff --git a/arch/arm/boot/dts/kirkwood-ns2mini.dts b/arch/arm/boot/dts/kirkwood-ns2mini.dts index adbafdd..c441bf6 100644 --- a/arch/arm/boot/dts/kirkwood-ns2mini.dts +++ b/arch/arm/boot/dts/kirkwood-ns2mini.dts @@ -23,10 +23,10 @@ gpio_fan { compatible = "gpio-fan"; - gpios = <&gpio0 22 1 - &gpio0 7 1 - &gpio1 1 1 - &gpio0 23 1>; + gpios = <&gpio0 22 GPIO_ACTIVE_LOW + &gpio0 7 GPIO_ACTIVE_LOW + &gpio1 1 GPIO_ACTIVE_LOW + &gpio0 23 GPIO_ACTIVE_LOW>; gpio-fan,speed-map = < 0 0 3000 15 @@ -37,7 +37,7 @@ 7140 10 7980 9 9200 8>; - alarm-gpios = <&gpio0 25 1>; + alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; }; ns2-leds { diff --git a/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi b/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi index e3f915d..aa78c2d 100644 --- a/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi +++ b/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi @@ -40,7 +40,7 @@ compatible = "gpio-poweroff"; pinctrl-0 = <&pmx_pwr_off>; pinctrl-names = "default"; - gpios = <&gpio1 16 0>; + gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; }; regulators { @@ -58,7 +58,7 @@ regulator-max-microvolt = <5000000>; regulator-always-on; regulator-boot-on; - gpio = <&gpio0 21 0>; + gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>; }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-nsa310.dts b/arch/arm/boot/dts/kirkwood-nsa310.dts index c45a26c..03fa24c 100644 --- a/arch/arm/boot/dts/kirkwood-nsa310.dts +++ b/arch/arm/boot/dts/kirkwood-nsa310.dts @@ -120,17 +120,17 @@ button@1 { label = "Power Button"; linux,code = ; - gpios = <&gpio1 14 0>; + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; }; button@2 { label = "Copy Button"; linux,code = ; - gpios = <&gpio1 5 1>; + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; }; button@3 { label = "Reset Button"; linux,code = ; - gpios = <&gpio1 4 1>; + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; }; }; @@ -145,43 +145,43 @@ green-sys { label = "nsa310:green:sys"; - gpios = <&gpio0 28 0>; + gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; }; red-sys { label = "nsa310:red:sys"; - gpios = <&gpio0 29 0>; + gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; }; green-hdd { label = "nsa310:green:hdd"; - gpios = <&gpio1 9 0>; + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; }; red-hdd { label = "nsa310:red:hdd"; - gpios = <&gpio1 10 0>; + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; }; green-esata { label = "nsa310:green:esata"; - gpios = <&gpio0 12 0>; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; }; red-esata { label = "nsa310:red:esata"; - gpios = <&gpio0 13 0>; + gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; }; green-usb { label = "nsa310:green:usb"; - gpios = <&gpio0 15 0>; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; }; red-usb { label = "nsa310:red:usb"; - gpios = <&gpio0 16 0>; + gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; }; green-copy { label = "nsa310:green:copy"; - gpios = <&gpio1 7 0>; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; }; red-copy { label = "nsa310:red:copy"; - gpios = <&gpio1 8 0>; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-nsa310a.dts b/arch/arm/boot/dts/kirkwood-nsa310a.dts index 874df7d..a5e7794 100644 --- a/arch/arm/boot/dts/kirkwood-nsa310a.dts +++ b/arch/arm/boot/dts/kirkwood-nsa310a.dts @@ -108,17 +108,17 @@ button@1 { label = "Power Button"; linux,code = ; - gpios = <&gpio1 14 0>; + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; }; button@2 { label = "Copy Button"; linux,code = ; - gpios = <&gpio1 5 1>; + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; }; button@3 { label = "Reset Button"; linux,code = ; - gpios = <&gpio1 4 1>; + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; }; }; @@ -127,39 +127,39 @@ green-sys { label = "nsa310:green:sys"; - gpios = <&gpio0 28 0>; + gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; }; red-sys { label = "nsa310:red:sys"; - gpios = <&gpio0 29 0>; + gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; }; green-hdd { label = "nsa310:green:hdd"; - gpios = <&gpio1 9 0>; + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; }; red-hdd { label = "nsa310:red:hdd"; - gpios = <&gpio1 10 0>; + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; }; green-esata { label = "nsa310:green:esata"; - gpios = <&gpio0 12 0>; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; }; red-esata { label = "nsa310:red:esata"; - gpios = <&gpio0 13 0>; + gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; }; green-usb { label = "nsa310:green:usb"; - gpios = <&gpio0 15 0>; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; }; green-copy { label = "nsa310:green:copy"; - gpios = <&gpio1 7 0>; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; }; red-copy { label = "nsa310:red:copy"; - gpios = <&gpio1 8 0>; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts index 6c171e0..5c6a4f1 100644 --- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts +++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts @@ -101,17 +101,17 @@ led-red { label = "obsa6:red:stat"; - gpios = <&gpio1 9 1>; + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; }; led-green { label = "obsa6:green:stat"; - gpios = <&gpio1 10 1>; + gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; }; led-yellow { label = "obsa6:yellow:stat"; - gpios = <&gpio1 11 1>; + gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; }; }; @@ -125,7 +125,7 @@ button@1 { label = "Init Button"; linux,code = ; - gpios = <&gpio1 6 0>; + gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a7.dts b/arch/arm/boot/dts/kirkwood-openblocks_a7.dts index c97bad4..c054ef6 100644 --- a/arch/arm/boot/dts/kirkwood-openblocks_a7.dts +++ b/arch/arm/boot/dts/kirkwood-openblocks_a7.dts @@ -126,17 +126,17 @@ led-red { label = "obsa7:red:stat"; - gpios = <&gpio1 9 1>; + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; }; led-green { label = "obsa7:green:stat"; - gpios = <&gpio1 10 1>; + gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; }; led-yellow { label = "obsa7:yellow:stat"; - gpios = <&gpio1 11 1>; + gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; }; }; @@ -150,7 +150,7 @@ button@1 { label = "Init Button"; linux,code = ; - gpios = <&gpio1 6 0>; + gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts b/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts index ce9b3be..e2b4ea4 100644 --- a/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts +++ b/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts @@ -24,8 +24,8 @@ pinctrl-0 = <&pmx_sdio &pmx_sdio_cd &pmx_sdio_wp>; pinctrl-names = "default"; status = "okay"; - cd-gpios = <&gpio1 12 1>; - wp-gpios = <&gpio1 15 0>; + cd-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; }; }; @@ -36,7 +36,7 @@ health { label = "sheevaplug:blue:health"; - gpios = <&gpio1 17 1>; + gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; default-state = "keep"; }; }; diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug.dts b/arch/arm/boot/dts/kirkwood-sheevaplug.dts index c01f9c7..82f6abf 100644 --- a/arch/arm/boot/dts/kirkwood-sheevaplug.dts +++ b/arch/arm/boot/dts/kirkwood-sheevaplug.dts @@ -31,13 +31,13 @@ health { label = "sheevaplug:blue:health"; - gpios = <&gpio1 17 1>; + gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; default-state = "keep"; }; misc { label = "sheevaplug:red:misc"; - gpios = <&gpio1 14 1>; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/kirkwood-topkick.dts index 320da67..40d6adf 100644 --- a/arch/arm/boot/dts/kirkwood-topkick.dts +++ b/arch/arm/boot/dts/kirkwood-topkick.dts @@ -131,25 +131,25 @@ disk { label = "topkick:yellow:disk"; - gpios = <&gpio0 21 1>; + gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; linux,default-trigger = "ide-disk"; }; system2 { label = "topkick:red:system"; - gpios = <&gpio1 5 1>; + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; }; system { label = "topkick:blue:system"; - gpios = <&gpio1 6 1>; + gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; default-state = "on"; }; wifi { label = "topkick:green:wifi"; - gpios = <&gpio1 7 1>; + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; }; wifi2 { label = "topkick:yellow:wifi"; - gpios = <&gpio1 16 1>; + gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; }; }; regulators { diff --git a/arch/arm/boot/dts/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/kirkwood-ts219-6281.dts index 89f7094..c17ae45 100644 --- a/arch/arm/boot/dts/kirkwood-ts219-6281.dts +++ b/arch/arm/boot/dts/kirkwood-ts219-6281.dts @@ -42,12 +42,12 @@ button@1 { label = "USB Copy"; linux,code = ; - gpios = <&gpio0 15 1>; + gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; }; button@2 { label = "Reset"; linux,code = ; - gpios = <&gpio0 16 1>; + gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/kirkwood-ts219-6282.dts index 6976afb..0713d072 100644 --- a/arch/arm/boot/dts/kirkwood-ts219-6282.dts +++ b/arch/arm/boot/dts/kirkwood-ts219-6282.dts @@ -52,12 +52,12 @@ button@1 { label = "USB Copy"; linux,code = ; - gpios = <&gpio1 11 1>; + gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; }; button@2 { label = "Reset"; linux,code = ; - gpios = <&gpio1 5 1>; + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; }; }; }; diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index 477c0b5..dd58a25 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -1,5 +1,6 @@ /include/ "skeleton.dtsi" #include +#include #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) -- cgit v1.1 From 92beaccd8b4988d13851edc985ac4c3481644e07 Mon Sep 17 00:00:00 2001 From: Arnaud Ebalard Date: Sat, 7 Dec 2013 00:13:37 +0100 Subject: ARM: mvebu: Enable NAND controller in ReadyNAS 102 .dts file Now that NAND controller support is available for Armada 370 (cb28e2537a6f: ARM: mvebu: Add support for NAND controller in Armada 370/XP), this patch enables support for ReadyNAS 102 and defines default partition layout as delivered by NETGEAR. As described in similar commits 2be2bc39c6f0 (ARM: mvebu: Enable NAND controller in Armada XP GP board) and d8c552dddfbf (ARM: mvebu: Enable NAND controller in Armada 370 Mirabox), "marvell,keep-config" parameter is used as current support does not allow for setting of timing parameters yet. Signed-off-by: Arnaud Ebalard Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-370-netgear-rn102.dts | 36 ++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts index 1c2d13d..6a7383f 100644 --- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts +++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts @@ -131,6 +131,42 @@ pwm_polarity = <0>; }; }; + + nand@d0000 { + status = "okay"; + num-cs = <1>; + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x180000>; /* 1.5MB */ + read-only; + }; + + partition@180000 { + label = "u-boot-env"; + reg = <0x180000 0x20000>; /* 128KB */ + read-only; + }; + + partition@200000 { + label = "uImage"; + reg = <0x0200000 0x600000>; /* 6MB */ + }; + + partition@800000 { + label = "minirootfs"; + reg = <0x0800000 0x400000>; /* 4MB */ + }; + + /* Last MB is for the BBT, i.e. not writable */ + partition@c00000 { + label = "ubifs"; + reg = <0x0c00000 0x7400000>; /* 116MB */ + }; + }; }; }; -- cgit v1.1 From 0373a558bd794ff3829791d33e25a6b82c2ec676 Mon Sep 17 00:00:00 2001 From: Arnaud Ebalard Date: Sat, 7 Dec 2013 00:13:18 +0100 Subject: ARM: mvebu: Enable NAND controller in ReadyNAS 104 .dts file Now that NAND controller support is available for Armada 370 (cb28e2537a6f: ARM: mvebu: Add support for NAND controller in Armada 370/XP), this patch enables support for ReadyNAS 104 and defines default partition layout as delivered by NETGEAR. As described in similar commits 2be2bc39c6f0 (ARM: mvebu: Enable NAND controller in Armada XP GP board) and d8c552dddfbf (ARM: mvebu: Enable NAND controller in Armada 370 Mirabox), "marvell,keep-config" parameter is used as current support does not allow for setting of timing parameters yet. Signed-off-by: Arnaud Ebalard Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-370-netgear-rn104.dts | 36 ++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/armada-370-netgear-rn104.dts index e48e5fb..272e2e2 100644 --- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts +++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts @@ -133,6 +133,42 @@ reg = <0x23>; }; }; + + nand@d0000 { + status = "okay"; + num-cs = <1>; + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x180000>; /* 1.5MB */ + read-only; + }; + + partition@180000 { + label = "u-boot-env"; + reg = <0x180000 0x20000>; /* 128KB */ + read-only; + }; + + partition@200000 { + label = "uImage"; + reg = <0x0200000 0x600000>; /* 6MB */ + }; + + partition@800000 { + label = "minirootfs"; + reg = <0x0800000 0x400000>; /* 4MB */ + }; + + /* Last MB is for the BBT, i.e. not writable */ + partition@c00000 { + label = "ubifs"; + reg = <0x0c00000 0x7400000>; /* 116MB */ + }; + }; }; }; -- cgit v1.1 From ad51eddd95adaeaa767aca22736003d3b2662963 Mon Sep 17 00:00:00 2001 From: Arnaud Ebalard Date: Sat, 7 Dec 2013 00:13:53 +0100 Subject: ARM: mvebu: Enable NAND controller in ReadyNAS 2120 .dts file Now that NAND controller support is available for Armada XP (cb28e2537a6f: ARM: mvebu: Add support for NAND controller in Armada 370/XP), this patch enables support for ReadyNAS 2120 and defines default partition layout as delivered by NETGEAR. As described in similar commits 2be2bc39c6f0 (ARM: mvebu: Enable NAND controller in Armada XP GP board) and d8c552dddfbf (ARM: mvebu: Enable NAND controller in Armada 370 Mirabox), "marvell,keep-config" parameter is used as current support does not allow for setting of timing parameters yet. Signed-off-by: Arnaud Ebalard Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-xp-netgear-rn2120.dts | 36 ++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts index 8b2a787..f048b4e 100644 --- a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts +++ b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts @@ -211,6 +211,42 @@ reg = <0x4c>; }; }; + + nand@d0000 { + status = "okay"; + num-cs = <1>; + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x180000>; /* 1.5MB */ + read-only; + }; + + partition@180000 { + label = "u-boot-env"; + reg = <0x180000 0x20000>; /* 128KB */ + read-only; + }; + + partition@200000 { + label = "uImage"; + reg = <0x0200000 0x600000>; /* 6MB */ + }; + + partition@800000 { + label = "minirootfs"; + reg = <0x0800000 0x400000>; /* 4MB */ + }; + + /* Last MB is for the BBT, i.e. not writable */ + partition@c00000 { + label = "ubifs"; + reg = <0x0c00000 0x7400000>; /* 116MB */ + }; + }; }; }; -- cgit v1.1 From 5cffba20f09a4c4684a3edb9e4e18e98d2802ca1 Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Tue, 5 Nov 2013 16:40:09 +0100 Subject: ARM: at91/trivial: fix at91rm9200 rts/cts pinctrl definitions Swap names as they were improperly defined. Signed-off-by: Nicolas Ferre Acked-by: Jean-Christophe PLAGNIOL-VILLARD --- arch/arm/boot/dts/at91rm9200.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi index f770655..c61b16f 100644 --- a/arch/arm/boot/dts/at91rm9200.dtsi +++ b/arch/arm/boot/dts/at91rm9200.dtsi @@ -191,12 +191,12 @@ AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA18 periph A */ }; - pinctrl_uart0_rts: uart0_rts-0 { + pinctrl_uart0_cts: uart0_cts-0 { atmel,pins = ; /* PA20 periph A */ }; - pinctrl_uart0_cts: uart0_cts-0 { + pinctrl_uart0_rts: uart0_rts-0 { atmel,pins = ; /* PA21 periph A */ }; -- cgit v1.1 From 44fa054e08434623fe413cb043f6cd88191ded9e Mon Sep 17 00:00:00 2001 From: Boris BREZILLON Date: Wed, 28 Aug 2013 13:03:39 +0200 Subject: ARM: at91/dt: add ethernet phy to at91rm9200ek board Add ethernet phy node in at91rm9200ek.dts. The reg register is not specified, as it may differ depending on the init process of the board: ADDR0/1 phy pins are connected to PA13/14 rm9200 pins. Which means the phy will take its address from these pins during the reset process. The macb driver will launch a full scan on the mdio bus to discover the phy address. Signed-off-by: Boris BREZILLON [nicolas.ferre@atmel.com: changed to IRQ_TYPE_EDGE_BOTH as asked by Boris] Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/at91rm9200ek.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/at91rm9200ek.dts b/arch/arm/boot/dts/at91rm9200ek.dts index d2d72c3..e6fd0f8 100644 --- a/arch/arm/boot/dts/at91rm9200ek.dts +++ b/arch/arm/boot/dts/at91rm9200ek.dts @@ -47,6 +47,11 @@ macb0: ethernet@fffbc000 { phy-mode = "rmii"; status = "okay"; + + phy0: ethernet-phy { + interrupt-parent = <&pioC>; + interrupts = <4 IRQ_TYPE_EDGE_BOTH>; + }; }; usb1: gadget@fffb0000 { -- cgit v1.1 From a7704b7ffcf8b371bc651de9f176c3c9c7fc8629 Mon Sep 17 00:00:00 2001 From: Boris BREZILLON Date: Mon, 2 Dec 2013 11:44:05 +0100 Subject: ARM: at91/dt: add atmel,pullup-gpio to at91rm9200ek usb1 definition Signed-off-by: Boris BREZILLON Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/at91rm9200ek.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/at91rm9200ek.dts b/arch/arm/boot/dts/at91rm9200ek.dts index e6fd0f8..e40b6a5 100644 --- a/arch/arm/boot/dts/at91rm9200ek.dts +++ b/arch/arm/boot/dts/at91rm9200ek.dts @@ -56,6 +56,7 @@ usb1: gadget@fffb0000 { atmel,vbus-gpio = <&pioD 4 GPIO_ACTIVE_HIGH>; + atmel,pullup-gpio = <&pioD 5 GPIO_ACTIVE_HIGH>; status = "okay"; }; -- cgit v1.1 From ddee65b331e16c11837c83e95dceb3936cbd2e69 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Fri, 29 Mar 2013 02:10:47 +0800 Subject: ARM: at91: sam9g45: add fb dt support Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/at91sam9g45.dtsi | 45 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index c3e5148..c2021d1 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -425,6 +425,42 @@ }; }; + fb { + pinctrl_fb: fb-0 { + atmel,pins = + ; /* PE30 periph A */ + }; + }; + pioA: gpio@fffff200 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffff200 0x200>; @@ -727,6 +763,15 @@ }; }; + fb0: fb@0x00500000 { + compatible = "atmel,at91sam9g45-lcdc"; + reg = <0x00500000 0x1000>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fb>; + status = "disabled"; + }; + nand0: nand@40000000 { compatible = "atmel,at91rm9200-nand"; #address-cells = <1>; -- cgit v1.1 From f8a0d7937682fcbb30e6049794272494f85b31f8 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Fri, 29 Mar 2013 04:50:46 +0800 Subject: ARM: at91: sam9263: add fb dt support Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/at91sam9263.dtsi | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index d5bd65f..22e255a 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi @@ -366,6 +366,34 @@ }; }; + fb { + pinctrl_fb: fb-0 { + atmel,pins = + ; /* PC27 periph A */ + }; + }; + pioA: gpio@fffff200 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffff200 0x200>; @@ -549,6 +577,15 @@ }; }; + fb0: fb@0x00700000 { + compatible = "atmel,at91sam9263-lcdc"; + reg = <0x00700000 0x1000>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fb>; + status = "disabled"; + }; + nand0: nand@40000000 { compatible = "atmel,at91rm9200-nand"; #address-cells = <1>; -- cgit v1.1 From f4390a798f8d145948717d25192dcee4732c2c38 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Fri, 29 Mar 2013 02:11:22 +0800 Subject: ARM: at91: at9sam9m10g45ek: add dt lcd support Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/at91sam9m10g45ek.dts | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts index a4b00e5..7b76dbd 100644 --- a/arch/arm/boot/dts/at91sam9m10g45ek.dts +++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts @@ -123,6 +123,35 @@ }; }; + fb0: fb@0x00500000 { + display = <&display0>; + status = "okay"; + + display0: display { + bits-per-pixel = <32>; + atmel,lcdcon-backlight; + atmel,dmacon = <0x1>; + atmel,lcdcon2 = <0x80008002>; + atmel,guard-time = <9>; + atmel,lcd-wiring-mode = "RGB"; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <9000000>; + hactive = <480>; + vactive = <272>; + hback-porch = <1>; + hfront-porch = <1>; + vback-porch = <40>; + vfront-porch = <1>; + hsync-len = <45>; + vsync-len = <1>; + }; + }; + }; + }; + nand0: nand@40000000 { nand-bus-width = <8>; nand-ecc-mode = "soft"; -- cgit v1.1 From 510e37831ea91aea4b2bcb2054f173f174e1f834 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Fri, 29 Mar 2013 05:09:00 +0800 Subject: ARM: at91: sam9263ek: add dt lcd support Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/at91sam9263ek.dts | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts index 70f835b..15009c9 100644 --- a/arch/arm/boot/dts/at91sam9263ek.dts +++ b/arch/arm/boot/dts/at91sam9263ek.dts @@ -95,6 +95,36 @@ }; }; + fb0: fb@0x00700000 { + display = <&display0>; + status = "okay"; + + display0: display { + bits-per-pixel = <16>; + atmel,lcdcon-backlight; + atmel,dmacon = <0x1>; + atmel,lcdcon2 = <0x80008002>; + atmel,guard-time = <1>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <4965000>; + hactive = <240>; + vactive = <320>; + hback-porch = <1>; + hfront-porch = <33>; + vback-porch = <1>; + vfront-porch = <0>; + hsync-len = <5>; + vsync-len = <1>; + hsync-active = <1>; + vsync-active = <1>; + }; + }; + }; + }; + nand0: nand@40000000 { nand-bus-width = <8>; nand-ecc-mode = "soft"; -- cgit v1.1 From 07f7d503e3a77a5890694a9c0b878d89d6a38dae Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Fri, 11 Oct 2013 14:45:44 +0200 Subject: ARM: at91/dt/trivial: use macro for AES irq type Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/sama5d3.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index de9fece..b4dead3 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -341,7 +341,7 @@ aes@f8038000 { compatible = "atmel,sam9g46-aes"; reg = <0xf8038000 0x100>; - interrupts = <43 4 0>; + interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>; }; tdes@f803c000 { -- cgit v1.1 From c76f266d972ef98abb0d7589411a8a5ad87d3267 Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Fri, 11 Oct 2013 16:57:57 +0200 Subject: ARM: at91/dt/trivial: before sama5d3, Atmel MPU were using at91 prefix Change the sha/aes/tdes compatibility string to match common case for the at91sam9g45 family which is to keep the at91 prefix. Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/sama5d3.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index b4dead3..bcec910 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -333,19 +333,19 @@ }; sha@f8034000 { - compatible = "atmel,sam9g46-sha"; + compatible = "atmel,at91sam9g46-sha"; reg = <0xf8034000 0x100>; interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>; }; aes@f8038000 { - compatible = "atmel,sam9g46-aes"; + compatible = "atmel,at91sam9g46-aes"; reg = <0xf8038000 0x100>; interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>; }; tdes@f803c000 { - compatible = "atmel,sam9g46-tdes"; + compatible = "atmel,at91sam9g46-tdes"; reg = <0xf803c000 0x100>; interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>; }; -- cgit v1.1 From 9860c515c1145d578e01ff521e21f358d2ce2996 Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Fri, 11 Oct 2013 16:59:46 +0200 Subject: ARM: at91/dt/sama5d3: add DMA information to SHA/AES/TDES nodes Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/sama5d3.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index bcec910..951fa2c 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -336,18 +336,26 @@ compatible = "atmel,at91sam9g46-sha"; reg = <0xf8034000 0x100>; interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(17)>; + dma-names = "tx"; }; aes@f8038000 { compatible = "atmel,at91sam9g46-aes"; reg = <0xf8038000 0x100>; interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(18)>, + <&dma1 2 AT91_DMA_CFG_PER_ID(19)>; + dma-names = "tx", "rx"; }; tdes@f803c000 { compatible = "atmel,at91sam9g46-tdes"; reg = <0xf803c000 0x100>; interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(20)>, + <&dma1 2 AT91_DMA_CFG_PER_ID(21)>; + dma-names = "tx", "rx"; }; dma0: dma-controller@ffffe600 { -- cgit v1.1 From 470e891b06b2971037b38020cb4b9e7e496500e6 Mon Sep 17 00:00:00 2001 From: Rodolfo Giometti Date: Wed, 13 Nov 2013 18:20:54 +0100 Subject: ARM: at91: add support for Cosino board series by HCE Engineering This patch adds the Cosino at91sam9g35 based CPU module and the Cosino Mega 2560 extension board. Web site: http://www.cosino.it Signed-off-by: Rodolfo Giometti [plagnioj@jcrosoft.com: added "at91-" to files, pinctrl fixed, removed unneeded stuff] Acked-by: Jean-Christophe PLAGNIOL-VILLARD [nicolas.ferre@atmel.com: adapted to newer kernel, modified commit message] Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/at91-cosino.dtsi | 122 +++++++++++++++++++++++++++++ arch/arm/boot/dts/at91-cosino_mega2560.dts | 84 ++++++++++++++++++++ 3 files changed, 207 insertions(+) create mode 100644 arch/arm/boot/dts/at91-cosino.dtsi create mode 100644 arch/arm/boot/dts/at91-cosino_mega2560.dts (limited to 'arch') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index d57c1a6..772a30e 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -30,6 +30,7 @@ dtb-$(CONFIG_ARCH_AT91) += pm9g45.dtb dtb-$(CONFIG_ARCH_AT91) += at91sam9n12ek.dtb # sam9x5 dtb-$(CONFIG_ARCH_AT91) += at91-ariag25.dtb +dtb-$(CONFIG_ARCH_AT91) += at91-cosino_mega2560.dtb dtb-$(CONFIG_ARCH_AT91) += at91sam9g15ek.dtb dtb-$(CONFIG_ARCH_AT91) += at91sam9g25ek.dtb dtb-$(CONFIG_ARCH_AT91) += at91sam9g35ek.dtb diff --git a/arch/arm/boot/dts/at91-cosino.dtsi b/arch/arm/boot/dts/at91-cosino.dtsi new file mode 100644 index 0000000..2093c4d --- /dev/null +++ b/arch/arm/boot/dts/at91-cosino.dtsi @@ -0,0 +1,122 @@ +/* + * at91-cosino.dtsi - Device Tree file for Cosino core module + * + * Copyright (C) 2013 - Rodolfo Giometti + * HCE Engineering + * + * Derived from at91sam9x5ek.dtsi by: + * Copyright (C) 2012 Atmel, + * 2012 Nicolas Ferre + * + * Licensed under GPLv2 or later. + */ + +#include "at91sam9g35.dtsi" + +/ { + model = "HCE Cosino core module"; + compatible = "hce,cosino", "atmel,at91sam9x5", "atmel,at91sam9"; + + chosen { + bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootfstype=ext3 rootwait"; + }; + + memory { + reg = <0x20000000 0x8000000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + main_clock: clock@0 { + compatible = "atmel,osc", "fixed-clock"; + clock-frequency = <12000000>; + }; + }; + + ahb { + apb { + mmc0: mmc@f0008000 { + pinctrl-0 = < + &pinctrl_board_mmc0 + &pinctrl_mmc0_slot0_clk_cmd_dat0 + &pinctrl_mmc0_slot0_dat1_3>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>; + }; + }; + + dbgu: serial@fffff200 { + status = "okay"; + }; + + usart0: serial@f801c000 { + status = "okay"; + }; + + i2c0: i2c@f8010000 { + status = "okay"; + }; + + adc0: adc@f804c000 { + atmel,adc-clock-rate = <1000000>; + atmel,adc-ts-wires = <4>; + atmel,adc-ts-pressure-threshold = <10000>; + status = "okay"; + }; + + pinctrl@fffff400 { + mmc0 { + pinctrl_board_mmc0: mmc0-board { + atmel,pins = + ; /* PD15 gpio CD pin pull up and deglitch */ + }; + }; + }; + + watchdog@fffffe40 { + status = "okay"; + }; + }; + + nand0: nand@40000000 { + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + atmel,has-pmecc; /* Enable PMECC */ + atmel,pmecc-cap = <4>; + atmel,pmecc-sector-size = <512>; + nand-on-flash-bbt; + status = "okay"; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + uboot@40000 { + label = "u-boot"; + reg = <0x40000 0x80000>; + }; + + ubootenv@c0000 { + label = "U-Boot Env"; + reg = <0xc0000 0x140000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x0f800000>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/at91-cosino_mega2560.dts b/arch/arm/boot/dts/at91-cosino_mega2560.dts new file mode 100644 index 0000000..f9415dd --- /dev/null +++ b/arch/arm/boot/dts/at91-cosino_mega2560.dts @@ -0,0 +1,84 @@ +/* + * at91-cosino_mega2560.dts - Device Tree file for Cosino board with + * Mega 2560 extension + * + * Copyright (C) 2013 - Rodolfo Giometti + * HCE Engineering + * + * Derived from at91sam9g35ek.dts by: + * Copyright (C) 2012 Atmel, + * 2012 Nicolas Ferre + * + * Licensed under GPLv2 or later. + */ + +/dts-v1/; +#include "at91-cosino.dtsi" + +/ { + model = "HCE Cosino Mega 2560"; + compatible = "hce,cosino_mega2560", "atmel,at91sam9x5", "atmel,at91sam9"; + + ahb { + apb { + macb0: ethernet@f802c000 { + phy-mode = "rmii"; + status = "okay"; + }; + + adc0: adc@f804c000 { + atmel,adc-clock-rate = <1000000>; + atmel,adc-ts-wires = <4>; + atmel,adc-ts-pressure-threshold = <10000>; + status = "okay"; + }; + + + tsadcc: tsadcc@f804c000 { + status = "okay"; + }; + + rtc@fffffeb0 { + status = "okay"; + }; + + usart1: serial@f8020000 { + status = "okay"; + }; + + usart2: serial@f8024000 { + status = "okay"; + }; + + usb2: gadget@f803c000 { + atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + mmc1: mmc@f000c000 { + pinctrl-0 = < + &pinctrl_mmc1_slot0_clk_cmd_dat0 + &pinctrl_mmc1_slot0_dat1_3>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + non-removable; + }; + }; + }; + + usb0: ohci@00600000 { + status = "okay"; + num-ports = <3>; + atmel,vbus-gpio = <0 /* &pioD 18 GPIO_ACTIVE_LOW */ + &pioD 19 GPIO_ACTIVE_LOW + &pioD 20 GPIO_ACTIVE_LOW + >; + }; + + usb1: ehci@00700000 { + status = "okay"; + }; + }; +}; -- cgit v1.1 From c1463f68bf2b2a723d715898f89fd654865ab000 Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Mon, 2 Dec 2013 16:29:48 +0800 Subject: ARM: at91: sama5d3: enable qt1070 as a wakeup source Enable qt1070 keyboard as a wakeup source on sama5d3xek board. Signed-off-by: Bo Shen Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/sama5d3xdm.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sama5d3xdm.dtsi b/arch/arm/boot/dts/sama5d3xdm.dtsi index 1c296d6..f9bdde5 100644 --- a/arch/arm/boot/dts/sama5d3xdm.dtsi +++ b/arch/arm/boot/dts/sama5d3xdm.dtsi @@ -18,6 +18,7 @@ interrupts = <31 0x0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_qt1070_irq>; + wakeup-source; }; }; -- cgit v1.1 From 0645b93f6c223b594c0dca348e2ae0a23bccf6e3 Mon Sep 17 00:00:00 2001 From: Ludovic Desroches Date: Fri, 22 Nov 2013 14:49:52 +0100 Subject: ARM: at91: at91sam9g45: set default mmc pinctrl-names pinctrl-names property was missing from mmc nodes. Cc: #3.11+ Signed-off-by: Ludovic Desroches Acked-by: Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/at91sam9g45.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index c2021d1..4e20b44 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -654,6 +654,7 @@ compatible = "atmel,hsmci"; reg = <0xfff80000 0x600>; interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-names = "default"; dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>; dma-names = "rxtx"; #address-cells = <1>; @@ -665,6 +666,7 @@ compatible = "atmel,hsmci"; reg = <0xfffd0000 0x600>; interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-names = "default"; dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>; dma-names = "rxtx"; #address-cells = <1>; -- cgit v1.1 From cd127e1d99c9453d3a877a6f109b58615ac491ab Mon Sep 17 00:00:00 2001 From: Ludovic Desroches Date: Fri, 22 Nov 2013 14:49:53 +0100 Subject: ARM: at91: at91sam9g45: add i2c pinctrl Signed-off-by: Ludovic Desroches Acked-by: Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/at91sam9g45.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index 4e20b44..d7af9ec 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -143,6 +143,22 @@ }; }; + i2c0 { + pinctrl_i2c0: i2c0-0 { + atmel,pins = + ; /* PA20 periph A TWD0 */ + }; + }; + + i2c1 { + pinctrl_i2c1: i2c1-0 { + atmel,pins = + ; /* PB10 periph A TWD1 */ + }; + }; + usart0 { pinctrl_usart0: usart0-0 { atmel,pins = @@ -578,6 +594,8 @@ compatible = "atmel,at91sam9g10-i2c"; reg = <0xfff84000 0x100>; interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -587,6 +605,8 @@ compatible = "atmel,at91sam9g10-i2c"; reg = <0xfff88000 0x100>; interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; -- cgit v1.1 From 2f8e45820406416be5dd6d76248bd2e53835595e Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Fri, 27 Sep 2013 08:48:15 +0200 Subject: ARM: at91: Animeo IP: fix mtd partition table Update to production one. Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/animeo_ip.dts | 31 ++++++++----------------------- 1 file changed, 8 insertions(+), 23 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/animeo_ip.dts b/arch/arm/boot/dts/animeo_ip.dts index 3a1de9e..3c4f6d9 100644 --- a/arch/arm/boot/dts/animeo_ip.dts +++ b/arch/arm/boot/dts/animeo_ip.dts @@ -90,34 +90,19 @@ nand-on-flash-bbt; status = "okay"; - at91bootstrap@0 { - label = "at91bootstrap"; - reg = <0x0 0x8000>; - }; - - barebox@8000 { + barebox@0 { label = "barebox"; - reg = <0x8000 0x40000>; - }; - - bareboxenv@48000 { - label = "bareboxenv"; - reg = <0x48000 0x8000>; - }; - - user_block@0x50000 { - label = "user_block"; - reg = <0x50000 0xb0000>; + reg = <0x0 0x58000>; }; - kernel@100000 { - label = "kernel"; - reg = <0x100000 0x1b0000>; + u_boot_env@58000 { + label = "u_boot_env"; + reg = <0x58000 0x8000>; }; - root@2b0000 { - label = "root"; - reg = <0x2b0000 0x1D50000>; + ubi@60000 { + label = "ubi"; + reg = <0x60000 0x1FA0000>; }; }; -- cgit v1.1 From 557844ecc03e9c32416734553da0e623079ef503 Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Mon, 2 Dec 2013 17:18:48 +0100 Subject: ARM: at91: add i2c2 pinctrl speficifation to sama5d3 DT Signed-off-by: Nicolas Ferre Acked-by: Boris BREZILLON --- arch/arm/boot/dts/sama5d3.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 951fa2c..070c5c3 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -304,6 +304,8 @@ dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>, <&dma1 2 AT91_DMA_CFG_PER_ID(12)>; dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; #address-cells = <1>; #size-cells = <0>; clocks = <&twi2_clk>; @@ -494,6 +496,14 @@ }; }; + i2c2 { + pinctrl_i2c2: i2c2-0 { + atmel,pins = + ; /* TWCK2 pin, conflicts with LCDDAT19, ISI_D3 */ + }; + }; + isi { pinctrl_isi: isi-0 { atmel,pins = -- cgit v1.1 From ac0585cad0d4b702495071f8aba6103dac24ed6c Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Mon, 2 Dec 2013 17:10:04 +0100 Subject: ARM: at91: add uart aliases to sama5d3 dtsi Signed-off-by: Nicolas Ferre Acked-by Boris BREZILLON --- arch/arm/boot/dts/sama5d3_uart.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sama5d3_uart.dtsi b/arch/arm/boot/dts/sama5d3_uart.dtsi index 49d4d76..a9fa75e 100644 --- a/arch/arm/boot/dts/sama5d3_uart.dtsi +++ b/arch/arm/boot/dts/sama5d3_uart.dtsi @@ -12,6 +12,11 @@ #include / { + aliases { + serial5 = &uart0; + serial6 = &uart1; + }; + ahb { apb { pinctrl@fffff200 { -- cgit v1.1 From c8b3cc56b753f0f50cc635726d5e0ecd82625485 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Fri, 15 Nov 2013 15:49:56 +0100 Subject: ARM: at91: dt: at91rm9200ek: add emac and nor flash support Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD [nicolas.ferre@atmel.com: remove one macb node too many] Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/at91rm9200ek.dts | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/at91rm9200ek.dts b/arch/arm/boot/dts/at91rm9200ek.dts index e40b6a5..31f5c32 100644 --- a/arch/arm/boot/dts/at91rm9200ek.dts +++ b/arch/arm/boot/dts/at91rm9200ek.dts @@ -75,6 +75,35 @@ num-ports = <2>; status = "okay"; }; + + nor_flash@10000000 { + compatible = "cfi-flash"; + reg = <0x10000000 0x800000>; + linux,mtd-name = "physmap-flash.0"; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + + barebox@0 { + label = "barebox"; + reg = <0x00000 0x40000>; + }; + + bareboxenv@40000 { + label = "bareboxenv"; + reg = <0x40000 0x10000>; + }; + + kernel@50000 { + label = "kernel"; + reg = <0x50000 0x300000>; + }; + + root@350000 { + label = "root"; + reg = <0x350000 0x4B0000>; + }; + }; }; leds { -- cgit v1.1 From ca594844e4a53f778811c06feef60bdf36bc5fec Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Mon, 9 Dec 2013 14:42:50 +0100 Subject: ARM: at91/at91rm9200ek.dts: rearrange nodes in address ascending order Signed-off-by: Nicolas Ferre Acked-by: Boris BREZILLON --- arch/arm/boot/dts/at91rm9200ek.dts | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/at91rm9200ek.dts b/arch/arm/boot/dts/at91rm9200ek.dts index 31f5c32..df6b0aa 100644 --- a/arch/arm/boot/dts/at91rm9200ek.dts +++ b/arch/arm/boot/dts/at91rm9200ek.dts @@ -29,18 +29,9 @@ ahb { apb { - dbgu: serial@fffff200 { - status = "okay"; - }; - - usart1: serial@fffc4000 { - pinctrl-0 = - <&pinctrl_uart1 - &pinctrl_uart1_rts - &pinctrl_uart1_cts - &pinctrl_uart1_dtr_dsr - &pinctrl_uart1_dcd - &pinctrl_uart1_ri>; + usb1: gadget@fffb0000 { + atmel,vbus-gpio = <&pioD 4 GPIO_ACTIVE_HIGH>; + atmel,pullup-gpio = <&pioD 5 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -54,9 +45,14 @@ }; }; - usb1: gadget@fffb0000 { - atmel,vbus-gpio = <&pioD 4 GPIO_ACTIVE_HIGH>; - atmel,pullup-gpio = <&pioD 5 GPIO_ACTIVE_HIGH>; + usart1: serial@fffc4000 { + pinctrl-0 = + <&pinctrl_uart1 + &pinctrl_uart1_rts + &pinctrl_uart1_cts + &pinctrl_uart1_dtr_dsr + &pinctrl_uart1_dcd + &pinctrl_uart1_ri>; status = "okay"; }; @@ -69,6 +65,10 @@ reg = <0>; }; }; + + dbgu: serial@fffff200 { + status = "okay"; + }; }; usb0: ohci@00300000 { -- cgit v1.1 From 3acb51b9215bd99da403ecf8200f8425176b1926 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 3 Oct 2013 23:44:15 -0700 Subject: ARM: shmobile: r8a7778: add I2C support on DTSI Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7778.dtsi | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index a6308a3..7a2c433 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -116,4 +116,44 @@ compatible = "renesas,pfc-r8a7778"; reg = <0xfffc000 0x118>; }; + + i2c0: i2c@ffc70000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7778"; + reg = <0xffc70000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 67 0x4>; + status = "disabled"; + }; + + i2c1: i2c@ffc71000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7778"; + reg = <0xffc71000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 78 0x4>; + status = "disabled"; + }; + + i2c2: i2c@ffc72000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7778"; + reg = <0xffc72000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 76 0x4>; + status = "disabled"; + }; + + i2c3: i2c@ffc73000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7778"; + reg = <0xffc73000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 77 0x4>; + status = "disabled"; + }; }; -- cgit v1.1 From 6363070ef7744ad8b6af2ef37afc913c41e82547 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 3 Oct 2013 23:44:44 -0700 Subject: ARM: shmobile: r8a7779: tidyup I2C driver name on DTSI 10e8d4f6dddb0f9dc408c2f2bde8399b243a42ca (ARM: mach-shmobile: r8a7779: Minimal setup using DT) added I2C driver, but it was SH-Mobile I2C. R-Car H1 needs R-Car I2C driver. Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7779.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index 19faeac..da61d27 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -153,7 +153,7 @@ i2c0: i2c@ffc70000 { #address-cells = <1>; #size-cells = <0>; - compatible = "renesas,rmobile-iic"; + compatible = "renesas,i2c-r8a7779"; reg = <0xffc70000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 79 0x4>; @@ -163,7 +163,7 @@ i2c1: i2c@ffc71000 { #address-cells = <1>; #size-cells = <0>; - compatible = "renesas,rmobile-iic"; + compatible = "renesas,i2c-r8a7779"; reg = <0xffc71000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 82 0x4>; @@ -173,7 +173,7 @@ i2c2: i2c@ffc72000 { #address-cells = <1>; #size-cells = <0>; - compatible = "renesas,rmobile-iic"; + compatible = "renesas,i2c-r8a7779"; reg = <0xffc72000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 80 0x4>; @@ -183,7 +183,7 @@ i2c3: i2c@ffc73000 { #address-cells = <1>; #size-cells = <0>; - compatible = "renesas,rmobile-iic"; + compatible = "renesas,i2c-r8a7779"; reg = <0xffc73000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 81 0x4>; -- cgit v1.1 From 4a46beadec749d690acecc92811259cd7e85c6c4 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Sun, 6 Oct 2013 21:26:40 -0700 Subject: ARM: shmobile: lager: add default PFC settings on DTS SCIF0/SCIF1 PFC setting is needed as default Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790-lager-reference.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7790-lager-reference.dts b/arch/arm/boot/dts/r8a7790-lager-reference.dts index c462ef1..0a3f0c6 100644 --- a/arch/arm/boot/dts/r8a7790-lager-reference.dts +++ b/arch/arm/boot/dts/r8a7790-lager-reference.dts @@ -43,3 +43,18 @@ }; }; }; + +&pfc { + pinctrl-0 = <&scif0_pins &scif1_pins>; + pinctrl-names = "default"; + + scif0_pins: scif0 { + renesas,groups = "scif0_data"; + renesas,function = "scif0"; + }; + + scif1_pins: scif1 { + renesas,groups = "scif1_data"; + renesas,function = "scif1"; + }; +}; -- cgit v1.1 From 02b4a748c7ef37c2852478e67251a86e36d87152 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Sun, 6 Oct 2013 21:26:58 -0700 Subject: ARM: shmobile: lager: add MMCIF support on DTS Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790-lager-reference.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7790-lager-reference.dts b/arch/arm/boot/dts/r8a7790-lager-reference.dts index 0a3f0c6..75730f5 100644 --- a/arch/arm/boot/dts/r8a7790-lager-reference.dts +++ b/arch/arm/boot/dts/r8a7790-lager-reference.dts @@ -42,6 +42,15 @@ gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; }; }; + + fixedregulator3v3: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; }; &pfc { @@ -57,4 +66,19 @@ renesas,groups = "scif1_data"; renesas,function = "scif1"; }; + + mmc1_pins: mmc1 { + renesas,groups = "mmc1_data8", "mmc1_ctrl"; + renesas,function = "mmc1"; + }; +}; + +&mmcif1 { + pinctrl-0 = <&mmc1_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&fixedregulator3v3>; + bus-width = <8>; + non-removable; + status = "okay"; }; -- cgit v1.1 From 55146927a7d504dc9bef65cad9435ce04329d854 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 8 Oct 2013 12:39:01 +0900 Subject: ARM: shmobile: r8a7791 PFC device tree node Add a DT node for the r8a7791 PFC device. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index fea5cfe..765d989 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -71,4 +71,10 @@ <0 16 4>, <0 17 4>; }; + + pfc: pfc@e6060000 { + compatible = "renesas,pfc-r8a7791"; + reg = <0 0xe6060000 0 0x250>; + #gpio-range-cells = <3>; + }; }; -- cgit v1.1 From ab87e3fc0b3532f8ff1cb08b9f3680bc98be7728 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 8 Oct 2013 12:39:30 +0900 Subject: ARM: shmobile: r8a7791 GPIO device tree node Add GPIO controllers to the r8a7791 DTSI file. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 96 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 96 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 765d989..344f1f7 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -46,6 +46,102 @@ interrupts = <1 9 0xf04>; }; + gpio0: gpio@ffc40000 { + compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; + reg = <0 0xffc40000 0 0x50>; + interrupt-parent = <&gic>; + interrupts = <0 4 0x4>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 32>; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio1: gpio@ffc41000 { + compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; + reg = <0 0xffc41000 0 0x50>; + interrupt-parent = <&gic>; + interrupts = <0 5 0x4>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 32>; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio2: gpio@ffc42000 { + compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; + reg = <0 0xffc42000 0 0x50>; + interrupt-parent = <&gic>; + interrupts = <0 6 0x4>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 32>; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio3: gpio@ffc43000 { + compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; + reg = <0 0xffc43000 0 0x50>; + interrupt-parent = <&gic>; + interrupts = <0 7 0x4>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 32>; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio4: gpio@ffc44000 { + compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; + reg = <0 0xffc44000 0 0x50>; + interrupt-parent = <&gic>; + interrupts = <0 8 0x4>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 32>; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio5: gpio@ffc45000 { + compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; + reg = <0 0xffc45000 0 0x50>; + interrupt-parent = <&gic>; + interrupts = <0 9 0x4>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 32>; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio6: gpio@ffc45400 { + compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; + reg = <0 0xffc45400 0 0x50>; + interrupt-parent = <&gic>; + interrupts = <0 10 0x4>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 32>; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio7: gpio@ffc45800 { + compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; + reg = <0 0xffc45800 0 0x50>; + interrupt-parent = <&gic>; + interrupts = <0 11 0x4>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 224 26>; + #interrupt-cells = <2>; + interrupt-controller; + }; + timer { compatible = "arm,armv7-timer"; interrupts = <1 13 0xf08>, -- cgit v1.1 From 1919a0a4b4a7e505fdeb99e9df449c9d90b0da0c Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 8 Oct 2013 15:30:09 +0900 Subject: ARM: shmobile: r8a7791 Koelsch DT reference DTS bits Add DTS for the DT reference version of the Koelsch board support. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/r8a7791-koelsch-reference.dts | 32 +++++++++++++++++++++++++ 2 files changed, 33 insertions(+) create mode 100644 arch/arm/boot/dts/r8a7791-koelsch-reference.dts (limited to 'arch') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 5839077..909d910 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -225,6 +225,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += emev2-kzm9d.dtb \ r8a7779-marzen.dtb \ r8a7779-marzen-reference.dtb \ r8a7791-koelsch.dtb \ + r8a7791-koelsch-reference.dtb \ r8a7790-lager.dtb \ r8a7790-lager-reference.dtb \ sh73a0-kzm9g.dtb \ diff --git a/arch/arm/boot/dts/r8a7791-koelsch-reference.dts b/arch/arm/boot/dts/r8a7791-koelsch-reference.dts new file mode 100644 index 0000000..b8a374a --- /dev/null +++ b/arch/arm/boot/dts/r8a7791-koelsch-reference.dts @@ -0,0 +1,32 @@ +/* + * Device Tree Source for the Koelsch board + * + * Copyright (C) 2013 Renesas Electronics Corporation + * Copyright (C) 2013 Renesas Solutions Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +/include/ "r8a7791.dtsi" + +/ { + model = "Koelsch"; + compatible = "renesas,koelsch-reference", "renesas,r8a7791"; + + chosen { + bootargs = "console=ttySC6,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x80000000>; + }; + + lbsc { + #address-cells = <1>; + #size-cells = <1>; + }; +}; -- cgit v1.1 From 80d01feec9f20e30ab7a998a120bce697bb7d935 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 3 Oct 2013 19:35:41 +0200 Subject: ARM: shmobile: r8a7778: Fix pin control device address in DT The PFC device is erroneously declared at address 0xfffc000 instead of 0xfffc0000. Fix it. Signed-off-by: Laurent Pinchart Tested-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7778.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index 7a2c433..a582211 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -114,7 +114,7 @@ pfc: pfc@fffc0000 { compatible = "renesas,pfc-r8a7778"; - reg = <0xfffc000 0x118>; + reg = <0xfffc0000 0x118>; }; i2c0: i2c@ffc70000 { -- cgit v1.1 From 8ed1f8a5e1fdd76b0d2b04871a33a2f90e5f8343 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 3 Oct 2013 18:31:16 -0700 Subject: ARM: shmobile: bockw: add default PFC settings on DTS SCIF0 PFC setting is needed as default Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7778-bockw-reference.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7778-bockw-reference.dts b/arch/arm/boot/dts/r8a7778-bockw-reference.dts index 969e386..3c1d1f0 100644 --- a/arch/arm/boot/dts/r8a7778-bockw-reference.dts +++ b/arch/arm/boot/dts/r8a7778-bockw-reference.dts @@ -55,3 +55,13 @@ &irqpin { status = "okay"; }; + +&pfc { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + + scif0_pins: scif0 { + renesas,groups = "scif0_data_a", "scif0_ctrl"; + renesas,function = "scif0"; + }; +}; -- cgit v1.1 From dbece02b3460dcc8f43b8c1827b9eb363c2ced36 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 3 Oct 2013 18:32:01 -0700 Subject: ARM: shmobile: bockw: remove manual PFC settings on reference Current Bock-W reference is calling PFC initializer manually, but now, it can use DTS PFC. Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/board-bockw-reference.c | 12 ------------ 1 file changed, 12 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/board-bockw-reference.c b/arch/arm/mach-shmobile/board-bockw-reference.c index ae88fda..972f951 100644 --- a/arch/arm/mach-shmobile/board-bockw-reference.c +++ b/arch/arm/mach-shmobile/board-bockw-reference.c @@ -28,14 +28,6 @@ * see board-bock.c for checking detail of dip-switch */ -static const struct pinctrl_map bockw_pinctrl_map[] = { - /* SCIF0 */ - PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778", - "scif0_data_a", "scif0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778", - "scif0_ctrl", "scif0"), -}; - #define FPGA 0x18200000 #define IRQ0MR 0x30 #define COMCTLR 0x101c @@ -45,10 +37,6 @@ static void __init bockw_init(void) r8a7778_clock_init(); r8a7778_init_irq_extpin_dt(1); - - pinctrl_register_mappings(bockw_pinctrl_map, - ARRAY_SIZE(bockw_pinctrl_map)); - r8a7778_pinmux_init(); r8a7778_add_dt_devices(); fpga = ioremap_nocache(FPGA, SZ_1M); -- cgit v1.1 From f7b901757918a99a52ef3ff281401ee1118fa7f6 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 3 Oct 2013 18:32:22 -0700 Subject: ARM: shmobile: r8a7778: add MMCIF support on DTSI Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7778.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index a582211..0ff38e6 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -156,4 +156,12 @@ interrupts = <0 77 0x4>; status = "disabled"; }; + + mmcif: mmcif@ffe4e000 { + compatible = "renesas,sh-mmcif"; + reg = <0xffe4e000 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 61 4>; + status = "disabled"; + }; }; -- cgit v1.1 From 14cdd83a6df84849c369b201ce248e0213d735e0 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 3 Oct 2013 18:32:34 -0700 Subject: ARM: shmobile: bockw: add MMCIF support on DTS Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7778-bockw-reference.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7778-bockw-reference.dts b/arch/arm/boot/dts/r8a7778-bockw-reference.dts index 3c1d1f0..c6b834f 100644 --- a/arch/arm/boot/dts/r8a7778-bockw-reference.dts +++ b/arch/arm/boot/dts/r8a7778-bockw-reference.dts @@ -50,6 +50,21 @@ vddvario-supply = <&fixedregulator3v3>; vdd33a-supply = <&fixedregulator3v3>; }; + + mmc_pins: mmc { + renesas,groups = "mmc_data8", "mmc_ctrl"; + renesas,function = "mmc"; + }; +}; + +&mmcif { + pinctrl-0 = <&mmc_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&fixedregulator3v3>; + bus-width = <8>; + broken-cd; + status = "okay"; }; &irqpin { -- cgit v1.1 From 9ebe54baf8a166384201b4a78c649106047ebc75 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 10 Oct 2013 23:34:33 -0700 Subject: ARM: shmobile: bockw: fixup MMC pin conflict on DTS Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7778-bockw-reference.dts | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7778-bockw-reference.dts b/arch/arm/boot/dts/r8a7778-bockw-reference.dts index c6b834f..4d997f8 100644 --- a/arch/arm/boot/dts/r8a7778-bockw-reference.dts +++ b/arch/arm/boot/dts/r8a7778-bockw-reference.dts @@ -51,10 +51,6 @@ vdd33a-supply = <&fixedregulator3v3>; }; - mmc_pins: mmc { - renesas,groups = "mmc_data8", "mmc_ctrl"; - renesas,function = "mmc"; - }; }; &mmcif { @@ -79,4 +75,9 @@ renesas,groups = "scif0_data_a", "scif0_ctrl"; renesas,function = "scif0"; }; + + mmc_pins: mmc { + renesas,groups = "mmc_data8", "mmc_ctrl"; + renesas,function = "mmc"; + }; }; -- cgit v1.1 From 04cbd88902dd16a8f20db808ab444035be2557ac Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 10 Oct 2013 23:35:46 -0700 Subject: ARM: shmobile: r8a7778: add SDHI support on DTSI Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7778.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index 0ff38e6..873eeb9 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -164,4 +164,34 @@ interrupts = <0 61 4>; status = "disabled"; }; + + sdhi0: sdhi@ffe4c000 { + compatible = "renesas,sdhi-r8a7778"; + reg = <0xffe4c000 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 87 4>; + cap-sd-highspeed; + cap-sdio-irq; + status = "disabled"; + }; + + sdhi1: sdhi@ffe4d000 { + compatible = "renesas,sdhi-r8a7778"; + reg = <0xffe4d000 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 88 4>; + cap-sd-highspeed; + cap-sdio-irq; + status = "disabled"; + }; + + sdhi2: sdhi@ffe4f000 { + compatible = "renesas,sdhi-r8a7778"; + reg = <0xffe4f000 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 86 4>; + cap-sd-highspeed; + cap-sdio-irq; + status = "disabled"; + }; }; -- cgit v1.1 From 9d0395a5e1de5a1ea14298774006f3f285040848 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 10 Oct 2013 23:36:01 -0700 Subject: ARM: shmobile: bockw: add SDHI support on DTS Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7778-bockw-reference.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7778-bockw-reference.dts b/arch/arm/boot/dts/r8a7778-bockw-reference.dts index 4d997f8..8b8208e 100644 --- a/arch/arm/boot/dts/r8a7778-bockw-reference.dts +++ b/arch/arm/boot/dts/r8a7778-bockw-reference.dts @@ -80,4 +80,19 @@ renesas,groups = "mmc_data8", "mmc_ctrl"; renesas,function = "mmc"; }; + + sdhi0_pins: sdhi0 { + renesas,groups = "sdhi0_data4", "sdhi0_ctrl", + "sdhi0_cd", "sdhi0_wp"; + renesas,function = "sdhi0"; + }; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&fixedregulator3v3>; + bus-width = <4>; + status = "okay"; }; -- cgit v1.1 From c4866e70a92d8d5fd8ea7ad2c64ddf0efa7a0700 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 10 Oct 2013 23:36:22 -0700 Subject: ARM: shmobile: r8a7779: add SDHI support on DTSI Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7779.dtsi | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index da61d27..be737ef 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -206,4 +206,44 @@ interrupt-parent = <&gic>; interrupts = <0 100 0x4>; }; + + sdhi0: sdhi@ffe4c000 { + compatible = "renesas,sdhi-r8a7779"; + reg = <0xffe4c000 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 104 4>; + cap-sd-highspeed; + cap-sdio-irq; + status = "disabled"; + }; + + sdhi1: sdhi@ffe4d000 { + compatible = "renesas,sdhi-r8a7779"; + reg = <0xffe4d000 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 105 4>; + cap-sd-highspeed; + cap-sdio-irq; + status = "disabled"; + }; + + sdhi2: sdhi@ffe4e000 { + compatible = "renesas,sdhi-r8a7779"; + reg = <0xffe4e000 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 107 4>; + cap-sd-highspeed; + cap-sdio-irq; + status = "disabled"; + }; + + sdhi3: sdhi@ffe4f000 { + compatible = "renesas,sdhi-r8a7779"; + reg = <0xffe4f000 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 106 4>; + cap-sd-highspeed; + cap-sdio-irq; + status = "disabled"; + }; }; -- cgit v1.1 From 00bf591c3faae65eb00cc8b1ce7ede08b4ccc067 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 10 Oct 2013 23:36:44 -0700 Subject: ARM: shmobile: marzen: add SDHI support on DTS Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7779-marzen-reference.dts | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7779-marzen-reference.dts b/arch/arm/boot/dts/r8a7779-marzen-reference.dts index ab4110a..f7578d5 100644 --- a/arch/arm/boot/dts/r8a7779-marzen-reference.dts +++ b/arch/arm/boot/dts/r8a7779-marzen-reference.dts @@ -68,7 +68,7 @@ }; &pfc { - pinctrl-0 = <&scif2_pins &scif4_pins &sdhi0_pins>; + pinctrl-0 = <&scif2_pins &scif4_pins>; pinctrl-names = "default"; lan0_pins: lan0 { @@ -98,3 +98,12 @@ renesas,function = "sdhi0"; }; }; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&fixedregulator3v3>; + bus-width = <4>; + status = "okay"; +}; -- cgit v1.1 From 7d907894bfe3848a033aa19a2dbb12105300b8e5 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 21 Oct 2013 19:35:08 -0700 Subject: ARM: shmobile: r8a7740: tidyup DT node naming According to ePAPR spec, this patch tidies up DT node name and related clock. This patch also adds missing SDHI2 entry Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7740.dtsi | 18 +++++++++++++++--- arch/arm/mach-shmobile/clock-r8a7740.c | 8 ++++---- 2 files changed, 19 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index ae1e230..4cc945a 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -162,7 +162,7 @@ #pwm-cells = <3>; }; - mmcif0: mmcif@e6bd0000 { + mmcif0: mmc@e6bd0000 { compatible = "renesas,sh-mmcif"; reg = <0xe6bd0000 0x100>; interrupt-parent = <&gic>; @@ -171,7 +171,7 @@ status = "disabled"; }; - sdhi0: sdhi@e6850000 { + sdhi0: sd@e6850000 { compatible = "renesas,sdhi-r8a7740"; reg = <0xe6850000 0x100>; interrupt-parent = <&gic>; @@ -183,7 +183,7 @@ status = "disabled"; }; - sdhi1: sdhi@e6860000 { + sdhi1: sd@e6860000 { compatible = "renesas,sdhi-r8a7740"; reg = <0xe6860000 0x100>; interrupt-parent = <&gic>; @@ -194,4 +194,16 @@ cap-sdio-irq; status = "disabled"; }; + + sdhi2: sd@e6870000 { + compatible = "renesas,sdhi-r8a7740"; + reg = <0xe6870000 0x100>; + interrupt-parent = <&gic>; + interrupts = <0 125 4 + 0 126 4 + 0 127 4>; + cap-sd-highspeed; + cap-sdio-irq; + status = "disabled"; + }; }; diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c index e9a3c64..dd989f9 100644 --- a/arch/arm/mach-shmobile/clock-r8a7740.c +++ b/arch/arm/mach-shmobile/clock-r8a7740.c @@ -590,18 +590,18 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("e6c20000.i2c", &mstp_clks[MSTP323]), CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP320]), CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), - CLKDEV_DEV_ID("e6850000.sdhi", &mstp_clks[MSTP314]), + CLKDEV_DEV_ID("e6850000.sd", &mstp_clks[MSTP314]), CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), - CLKDEV_DEV_ID("e6860000.sdhi", &mstp_clks[MSTP313]), + CLKDEV_DEV_ID("e6860000.sd", &mstp_clks[MSTP313]), CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP312]), - CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), + CLKDEV_DEV_ID("e6bd0000.mmc", &mstp_clks[MSTP312]), CLKDEV_DEV_ID("r8a7740-gether", &mstp_clks[MSTP309]), CLKDEV_DEV_ID("e9a00000.sh-eth", &mstp_clks[MSTP309]), CLKDEV_DEV_ID("renesas-tpu-pwm", &mstp_clks[MSTP304]), CLKDEV_DEV_ID("e6600000.pwm", &mstp_clks[MSTP304]), CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]), - CLKDEV_DEV_ID("e6870000.sdhi", &mstp_clks[MSTP415]), + CLKDEV_DEV_ID("e6870000.sd", &mstp_clks[MSTP415]), /* ICK */ CLKDEV_ICK_ID("host", "renesas_usbhs", &mstp_clks[MSTP416]), -- cgit v1.1 From 43304a5f51066a7ef851732c35b4582a8d6a5bc0 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 21 Oct 2013 19:35:31 -0700 Subject: ARM: shmobile: r8a73a4: tidyup DT node naming According to ePAPR spec, this patch tidies up DT node name and related clock. Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a73a4.dtsi | 10 +++++----- arch/arm/mach-shmobile/clock-r8a73a4.c | 10 +++++----- 2 files changed, 10 insertions(+), 10 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index 287e047..e079c99 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -219,7 +219,7 @@ status = "disabled"; }; - mmcif0: mmcif@ee200000 { + mmcif0: mmc@ee200000 { compatible = "renesas,sh-mmcif"; reg = <0 0xee200000 0 0x80>; interrupt-parent = <&gic>; @@ -228,7 +228,7 @@ status = "disabled"; }; - mmcif1: mmcif@ee220000 { + mmcif1: mmc@ee220000 { compatible = "renesas,sh-mmcif"; reg = <0 0xee220000 0 0x80>; interrupt-parent = <&gic>; @@ -244,7 +244,7 @@ #gpio-cells = <2>; }; - sdhi0: sdhi@ee100000 { + sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a73a4"; reg = <0 0xee100000 0 0x100>; interrupt-parent = <&gic>; @@ -253,7 +253,7 @@ status = "disabled"; }; - sdhi1: sdhi@ee120000 { + sdhi1: sd@ee120000 { compatible = "renesas,sdhi-r8a73a4"; reg = <0 0xee120000 0 0x100>; interrupt-parent = <&gic>; @@ -262,7 +262,7 @@ status = "disabled"; }; - sdhi2: sdhi@ee140000 { + sdhi2: sd@ee140000 { compatible = "renesas,sdhi-r8a73a4"; reg = <0 0xee140000 0 0x100>; interrupt-parent = <&gic>; diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c index 571409b..7348d58 100644 --- a/arch/arm/mach-shmobile/clock-r8a73a4.c +++ b/arch/arm/mach-shmobile/clock-r8a73a4.c @@ -584,15 +584,15 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]), CLKDEV_DEV_ID("e6520000.i2c", &mstp_clks[MSTP300]), CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]), - CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]), + CLKDEV_DEV_ID("ee220000.mmc", &mstp_clks[MSTP305]), CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]), - CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP312]), + CLKDEV_DEV_ID("ee140000.sd", &mstp_clks[MSTP312]), CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), - CLKDEV_DEV_ID("ee120000.sdhi", &mstp_clks[MSTP313]), + CLKDEV_DEV_ID("ee120000.sd", &mstp_clks[MSTP313]), CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), - CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]), + CLKDEV_DEV_ID("ee100000.sd", &mstp_clks[MSTP314]), CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]), - CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]), + CLKDEV_DEV_ID("ee200000.mmc", &mstp_clks[MSTP315]), CLKDEV_DEV_ID("e6550000.i2c", &mstp_clks[MSTP316]), CLKDEV_DEV_ID("e6560000.i2c", &mstp_clks[MSTP317]), CLKDEV_DEV_ID("e6500000.i2c", &mstp_clks[MSTP318]), -- cgit v1.1 From 14e1d9147d96e0e6cc7f14eb339a7754404b4b73 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 21 Oct 2013 19:35:42 -0700 Subject: ARM: shmobile: r8a7778: tidyup DT node naming According to ePAPR spec, this patch tidies up DT node name and related clock. Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7778.dtsi | 8 ++++---- arch/arm/mach-shmobile/clock-r8a7778.c | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index 873eeb9..ca88b3b 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -157,7 +157,7 @@ status = "disabled"; }; - mmcif: mmcif@ffe4e000 { + mmcif: mmc@ffe4e000 { compatible = "renesas,sh-mmcif"; reg = <0xffe4e000 0x100>; interrupt-parent = <&gic>; @@ -165,7 +165,7 @@ status = "disabled"; }; - sdhi0: sdhi@ffe4c000 { + sdhi0: sd@ffe4c000 { compatible = "renesas,sdhi-r8a7778"; reg = <0xffe4c000 0x100>; interrupt-parent = <&gic>; @@ -175,7 +175,7 @@ status = "disabled"; }; - sdhi1: sdhi@ffe4d000 { + sdhi1: sd@ffe4d000 { compatible = "renesas,sdhi-r8a7778"; reg = <0xffe4d000 0x100>; interrupt-parent = <&gic>; @@ -185,7 +185,7 @@ status = "disabled"; }; - sdhi2: sdhi@ffe4f000 { + sdhi2: sd@ffe4f000 { compatible = "renesas,sdhi-r8a7778"; reg = <0xffe4f000 0x100>; interrupt-parent = <&gic>; diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c index 5406434..4b601bf 100644 --- a/arch/arm/mach-shmobile/clock-r8a7778.c +++ b/arch/arm/mach-shmobile/clock-r8a7778.c @@ -173,13 +173,13 @@ static struct clk_lookup lookups[] = { /* MSTP32 clocks */ CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP331]), /* MMC */ - CLKDEV_DEV_ID("ffe4e000.mmcif", &mstp_clks[MSTP331]), /* MMC */ + CLKDEV_DEV_ID("ffe4e000.mmc", &mstp_clks[MSTP331]), /* MMC */ CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */ - CLKDEV_DEV_ID("ffe4c000.sdhi", &mstp_clks[MSTP323]), /* SDHI0 */ + CLKDEV_DEV_ID("ffe4c000.sd", &mstp_clks[MSTP323]), /* SDHI0 */ CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */ - CLKDEV_DEV_ID("ffe4d000.sdhi", &mstp_clks[MSTP322]), /* SDHI1 */ + CLKDEV_DEV_ID("ffe4d000.sd", &mstp_clks[MSTP322]), /* SDHI1 */ CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */ - CLKDEV_DEV_ID("ffe4f000.sdhi", &mstp_clks[MSTP321]), /* SDHI2 */ + CLKDEV_DEV_ID("ffe4f000.sd", &mstp_clks[MSTP321]), /* SDHI2 */ CLKDEV_DEV_ID("r8a777x-ether", &mstp_clks[MSTP114]), /* Ether */ CLKDEV_DEV_ID("r8a7778-vin.0", &mstp_clks[MSTP110]), /* VIN0 */ CLKDEV_DEV_ID("r8a7778-vin.1", &mstp_clks[MSTP109]), /* VIN1 */ -- cgit v1.1 From 2624705ceb7b139cffdb409682d3e1bc480abec7 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 21 Oct 2013 19:36:02 -0700 Subject: ARM: shmobile: r8a7779: tidyup DT node naming According to ePAPR spec, this patch tidies up DT node name and related clock. Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7779.dtsi | 8 ++++---- arch/arm/mach-shmobile/clock-r8a7779.c | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index be737ef..05fd41c 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -207,7 +207,7 @@ interrupts = <0 100 0x4>; }; - sdhi0: sdhi@ffe4c000 { + sdhi0: sd@ffe4c000 { compatible = "renesas,sdhi-r8a7779"; reg = <0xffe4c000 0x100>; interrupt-parent = <&gic>; @@ -217,7 +217,7 @@ status = "disabled"; }; - sdhi1: sdhi@ffe4d000 { + sdhi1: sd@ffe4d000 { compatible = "renesas,sdhi-r8a7779"; reg = <0xffe4d000 0x100>; interrupt-parent = <&gic>; @@ -227,7 +227,7 @@ status = "disabled"; }; - sdhi2: sdhi@ffe4e000 { + sdhi2: sd@ffe4e000 { compatible = "renesas,sdhi-r8a7779"; reg = <0xffe4e000 0x100>; interrupt-parent = <&gic>; @@ -237,7 +237,7 @@ status = "disabled"; }; - sdhi3: sdhi@ffe4f000 { + sdhi3: sd@ffe4f000 { compatible = "renesas,sdhi-r8a7779"; reg = <0xffe4f000 0x100>; interrupt-parent = <&gic>; diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c index b545c8d..f1fb89b 100644 --- a/arch/arm/mach-shmobile/clock-r8a7779.c +++ b/arch/arm/mach-shmobile/clock-r8a7779.c @@ -204,13 +204,13 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */ CLKDEV_DEV_ID("fffc6000.spi", &mstp_clks[MSTP007]), /* HSPI2 */ CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */ - CLKDEV_DEV_ID("ffe4c000.sdhi", &mstp_clks[MSTP323]), /* SDHI0 */ + CLKDEV_DEV_ID("ffe4c000.sd", &mstp_clks[MSTP323]), /* SDHI0 */ CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */ - CLKDEV_DEV_ID("ffe4d000.sdhi", &mstp_clks[MSTP322]), /* SDHI1 */ + CLKDEV_DEV_ID("ffe4d000.sd", &mstp_clks[MSTP322]), /* SDHI1 */ CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */ - CLKDEV_DEV_ID("ffe4e000.sdhi", &mstp_clks[MSTP321]), /* SDHI2 */ + CLKDEV_DEV_ID("ffe4e000.sd", &mstp_clks[MSTP321]), /* SDHI2 */ CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */ - CLKDEV_DEV_ID("ffe4f000.sdhi", &mstp_clks[MSTP320]), /* SDHI3 */ + CLKDEV_DEV_ID("ffe4f000.sd", &mstp_clks[MSTP320]), /* SDHI3 */ CLKDEV_DEV_ID("rcar-du-r8a7779", &mstp_clks[MSTP103]), /* DU */ }; -- cgit v1.1 From b718aa448378a83c698f92073a4aa24df0d9444b Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 21 Oct 2013 19:36:13 -0700 Subject: ARM: shmobile: r8a7790: tidyup DT node naming According to ePAPR spec, this patch tidies up DT node name and related clock. Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 10 +++++----- arch/arm/mach-shmobile/clock-r8a7790.c | 12 ++++++------ 2 files changed, 11 insertions(+), 11 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index ee845fa..5ae7db6 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -225,7 +225,7 @@ status = "disabled"; }; - mmcif1: mmcif@ee220000 { + mmcif1: mmc@ee220000 { compatible = "renesas,sh-mmcif"; reg = <0 0xee220000 0 0x80>; interrupt-parent = <&gic>; @@ -239,7 +239,7 @@ reg = <0 0xe6060000 0 0x250>; }; - sdhi0: sdhi@ee100000 { + sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a7790"; reg = <0 0xee100000 0 0x100>; interrupt-parent = <&gic>; @@ -248,7 +248,7 @@ status = "disabled"; }; - sdhi1: sdhi@ee120000 { + sdhi1: sd@ee120000 { compatible = "renesas,sdhi-r8a7790"; reg = <0 0xee120000 0 0x100>; interrupt-parent = <&gic>; @@ -257,7 +257,7 @@ status = "disabled"; }; - sdhi2: sdhi@ee140000 { + sdhi2: sd@ee140000 { compatible = "renesas,sdhi-r8a7790"; reg = <0 0xee140000 0 0x100>; interrupt-parent = <&gic>; @@ -266,7 +266,7 @@ status = "disabled"; }; - sdhi3: sdhi@ee160000 { + sdhi3: sd@ee160000 { compatible = "renesas,sdhi-r8a7790"; reg = <0 0xee160000 0 0x100>; interrupt-parent = <&gic>; diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c index 36c8917..092975a 100644 --- a/arch/arm/mach-shmobile/clock-r8a7790.c +++ b/arch/arm/mach-shmobile/clock-r8a7790.c @@ -298,17 +298,17 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]), CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]), CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]), - CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]), + CLKDEV_DEV_ID("ee200000.mmc", &mstp_clks[MSTP315]), CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]), - CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]), + CLKDEV_DEV_ID("ee100000.sd", &mstp_clks[MSTP314]), CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), - CLKDEV_DEV_ID("ee120000.sdhi", &mstp_clks[MSTP313]), + CLKDEV_DEV_ID("ee120000.sd", &mstp_clks[MSTP313]), CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), - CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP312]), + CLKDEV_DEV_ID("ee140000.sd", &mstp_clks[MSTP312]), CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]), - CLKDEV_DEV_ID("ee160000.sdhi", &mstp_clks[MSTP311]), + CLKDEV_DEV_ID("ee160000.sd", &mstp_clks[MSTP311]), CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP311]), - CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]), + CLKDEV_DEV_ID("ee220000.mmc", &mstp_clks[MSTP305]), CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]), CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]), CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]), -- cgit v1.1 From 33f6be3bf6b79c2b9b7c8cd1387e8e7d4b839d9e Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 21 Oct 2013 19:36:22 -0700 Subject: ARM: shmobile: sh73a0: tidyup DT node naming According to ePAPR spec, this patch tidies up DT node name and related clock. Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/sh73a0.dtsi | 8 ++++---- arch/arm/mach-shmobile/clock-sh73a0.c | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index fcf2688..78f7201a 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -190,7 +190,7 @@ status = "disabled"; }; - mmcif: mmcif@e6bd0000 { + mmcif: mmc@e6bd0000 { compatible = "renesas,sh-mmcif"; reg = <0xe6bd0000 0x100>; interrupt-parent = <&gic>; @@ -200,7 +200,7 @@ status = "disabled"; }; - sdhi0: sdhi@ee100000 { + sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a7740"; reg = <0xee100000 0x100>; interrupt-parent = <&gic>; @@ -212,7 +212,7 @@ }; /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */ - sdhi1: sdhi@ee120000 { + sdhi1: sd@ee120000 { compatible = "renesas,sdhi-r8a7740"; reg = <0xee120000 0x100>; interrupt-parent = <&gic>; @@ -223,7 +223,7 @@ status = "disabled"; }; - sdhi2: sdhi@ee140000 { + sdhi2: sd@ee140000 { compatible = "renesas,sdhi-r8a7740"; reg = <0xee140000 0x100>; interrupt-parent = <&gic>; diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c index c92c023..96cc7da 100644 --- a/arch/arm/mach-shmobile/clock-sh73a0.c +++ b/arch/arm/mach-shmobile/clock-sh73a0.c @@ -663,13 +663,13 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("e6822000.i2c", &mstp_clks[MSTP323]), /* I2C1 */ CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP322]), /* USB */ CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */ - CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]), /* SDHI0 */ + CLKDEV_DEV_ID("ee100000.sd", &mstp_clks[MSTP314]), /* SDHI0 */ CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */ - CLKDEV_DEV_ID("ee120000.sdhi", &mstp_clks[MSTP313]), /* SDHI1 */ + CLKDEV_DEV_ID("ee120000.sd", &mstp_clks[MSTP313]), /* SDHI1 */ CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */ - CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), /* MMCIF0 */ + CLKDEV_DEV_ID("e6bd0000.mmc", &mstp_clks[MSTP312]), /* MMCIF0 */ CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]), /* SDHI2 */ - CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP311]), /* SDHI2 */ + CLKDEV_DEV_ID("ee140000.sd", &mstp_clks[MSTP311]), /* SDHI2 */ CLKDEV_DEV_ID("renesas-tpu-pwm.0", &mstp_clks[MSTP304]), /* TPU0 */ CLKDEV_DEV_ID("renesas-tpu-pwm.1", &mstp_clks[MSTP303]), /* TPU1 */ CLKDEV_DEV_ID("renesas-tpu-pwm.2", &mstp_clks[MSTP302]), /* TPU2 */ -- cgit v1.1 From e63763b9b55a6833047199bd587e061520302ffc Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 21 Oct 2013 19:37:14 -0700 Subject: ARM: shmobile: armadillo: tidyup DT node naming According to ePAPR spec, this patch tidies up DT node name. This patch removed un-used "touchscreen" label Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts index 1c56c5e..6a54219 100644 --- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts @@ -90,7 +90,7 @@ &i2c0 { status = "okay"; - touchscreen: st1232@55 { + touchscreen@55 { compatible = "sitronix,st1232"; reg = <0x55>; interrupt-parent = <&irqpin1>; @@ -105,12 +105,12 @@ pinctrl-0 = <&scifa1_pins>; pinctrl-names = "default"; - scifa1_pins: scifa1 { + scifa1_pins: serial1 { renesas,groups = "scifa1_data"; renesas,function = "scifa1"; }; - st1232_pins: st1232 { + st1232_pins: touchscreen { renesas,groups = "intc_irq10"; renesas,function = "intc"; }; @@ -125,7 +125,7 @@ renesas,function = "mmc0"; }; - sdhi0_pins: sdhi0 { + sdhi0_pins: sd0 { renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_wp"; renesas,function = "sdhi0"; }; -- cgit v1.1 From eeafbdf3253f23cbd30ee5f876ee9bb696a3c207 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 21 Oct 2013 19:37:26 -0700 Subject: ARM: shmobile: ape6evm: tidyup DT node naming According to ePAPR spec, this patch tidies up DT node name. Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts index 9443e93..25dbc1c 100644 --- a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts +++ b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts @@ -88,22 +88,22 @@ pinctrl-0 = <&scifa0_pins>; pinctrl-names = "default"; - scifa0_pins: scifa0 { + scifa0_pins: serial0 { renesas,groups = "scifa0_data"; renesas,function = "scifa0"; }; - mmc0_pins: mmcif { + mmc0_pins: mmc { renesas,groups = "mmc0_data8", "mmc0_ctrl"; renesas,function = "mmc0"; }; - sdhi0_pins: sdhi0 { + sdhi0_pins: sd0 { renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd"; renesas,function = "sdhi0"; }; - sdhi1_pins: sdhi1 { + sdhi1_pins: sd1 { renesas,groups = "sdhi1_data4", "sdhi1_ctrl"; renesas,function = "sdhi1"; }; -- cgit v1.1 From 26adf1a79e847ac147c1cc9f2c033ff5e4a73e22 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 21 Oct 2013 19:37:39 -0700 Subject: ARM: shmobile: kzm9g: tidyup DT node naming According to ePAPR spec, this patch tidies up DT node name. Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/sh73a0-kzm9g-reference.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts index 8ee06dd..df75aea 100644 --- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts +++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts @@ -205,7 +205,7 @@ renesas,function = "i2c3"; }; - mmcif_pins: mmcif { + mmcif_pins: mmc { mux { renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0"; renesas,function = "mmc0"; @@ -217,17 +217,17 @@ }; }; - scifa4_pins: scifa4 { + scifa4_pins: serial4 { renesas,groups = "scifa4_data", "scifa4_ctrl"; renesas,function = "scifa4"; }; - sdhi0_pins: sdhi0 { + sdhi0_pins: sd0 { renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", "sdhi0_wp"; renesas,function = "sdhi0"; }; - sdhi2_pins: sdhi2 { + sdhi2_pins: sd2 { renesas,groups = "sdhi2_data4", "sdhi2_ctrl"; renesas,function = "sdhi2"; }; -- cgit v1.1 From fb9c1ce47c2d5844ad2bf8dc8c06affa057e69c5 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 21 Oct 2013 19:37:48 -0700 Subject: ARM: shmobile: bockw: tidyup DT node naming According to ePAPR spec, this patch tidies up DT node name. Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7778-bockw-reference.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7778-bockw-reference.dts b/arch/arm/boot/dts/r8a7778-bockw-reference.dts index 8b8208e..9c8bd37 100644 --- a/arch/arm/boot/dts/r8a7778-bockw-reference.dts +++ b/arch/arm/boot/dts/r8a7778-bockw-reference.dts @@ -71,7 +71,7 @@ pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; - scif0_pins: scif0 { + scif0_pins: serial0 { renesas,groups = "scif0_data_a", "scif0_ctrl"; renesas,function = "scif0"; }; @@ -81,7 +81,7 @@ renesas,function = "mmc"; }; - sdhi0_pins: sdhi0 { + sdhi0_pins: sd0 { renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", "sdhi0_wp"; renesas,function = "sdhi0"; -- cgit v1.1 From 6220c5197eb0820d9fd75595efa73c56a2162689 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 21 Oct 2013 19:38:04 -0700 Subject: ARM: shmobile: marzen: tidyup DT node naming According to ePAPR spec, this patch tidies up DT node name. Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7779-marzen-reference.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7779-marzen-reference.dts b/arch/arm/boot/dts/r8a7779-marzen-reference.dts index f7578d5..ce3fe9e 100644 --- a/arch/arm/boot/dts/r8a7779-marzen-reference.dts +++ b/arch/arm/boot/dts/r8a7779-marzen-reference.dts @@ -82,17 +82,17 @@ }; }; - scif2_pins: scif2 { + scif2_pins: serial2 { renesas,groups = "scif2_data_c"; renesas,function = "scif2"; }; - scif4_pins: scif4 { + scif4_pins: serial4 { renesas,groups = "scif4_data"; renesas,function = "scif4"; }; - sdhi0_pins: sdhi0 { + sdhi0_pins: sd0 { renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", "sdhi0_wp"; renesas,function = "sdhi0"; -- cgit v1.1 From f56d51fcafcb222b7cf8cdd17eedb516f3197639 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 21 Oct 2013 19:38:16 -0700 Subject: ARM: shmobile: lager: tidyup DT node naming According to ePAPR spec, this patch tidies up DT node name. Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790-lager-reference.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7790-lager-reference.dts b/arch/arm/boot/dts/r8a7790-lager-reference.dts index 75730f5..ec82674 100644 --- a/arch/arm/boot/dts/r8a7790-lager-reference.dts +++ b/arch/arm/boot/dts/r8a7790-lager-reference.dts @@ -57,12 +57,12 @@ pinctrl-0 = <&scif0_pins &scif1_pins>; pinctrl-names = "default"; - scif0_pins: scif0 { + scif0_pins: serial0 { renesas,groups = "scif0_data"; renesas,function = "scif0"; }; - scif1_pins: scif1 { + scif1_pins: serial1 { renesas,groups = "scif1_data"; renesas,function = "scif1"; }; -- cgit v1.1 From fdf6fd2205181485ffc0fc622be7ed93dfbce361 Mon Sep 17 00:00:00 2001 From: Takashi Yoshii Date: Tue, 8 Oct 2013 14:33:07 +0900 Subject: ARM: shmobile: emev2: Add clock tree description in DT Add minimum clock tree description to .dts file. This provides same set of clocks as current sh-clkfwk version .c code does. Signed-off-by: Takashi Yoshii Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/emev2.dtsi | 84 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi index 9063a443..df1d4cd 100644 --- a/arch/arm/boot/dts/emev2.dtsi +++ b/arch/arm/boot/dts/emev2.dtsi @@ -52,34 +52,118 @@ <0 121 4>; }; + smu@e0110000 { + compatible = "renesas,emev2-smu"; + reg = <0xe0110000 0x10000>; + #address-cells = <2>; + #size-cells = <0>; + + c32ki: c32ki { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + pll3_fo: pll3_fo { + compatible = "fixed-factor-clock"; + clocks = <&c32ki>; + clock-div = <1>; + clock-mult = <7000>; + #clock-cells = <0>; + }; + usia_u0_sclkdiv: usia_u0_sclkdiv { + compatible = "renesas,emev2-smu-clkdiv"; + reg = <0x610 0>; + clocks = <&pll3_fo>; + #clock-cells = <0>; + }; + usib_u1_sclkdiv: usib_u1_sclkdiv { + compatible = "renesas,emev2-smu-clkdiv"; + reg = <0x65c 0>; + clocks = <&pll3_fo>; + #clock-cells = <0>; + }; + usib_u2_sclkdiv: usib_u2_sclkdiv { + compatible = "renesas,emev2-smu-clkdiv"; + reg = <0x65c 16>; + clocks = <&pll3_fo>; + #clock-cells = <0>; + }; + usib_u3_sclkdiv: usib_u3_sclkdiv { + compatible = "renesas,emev2-smu-clkdiv"; + reg = <0x660 0>; + clocks = <&pll3_fo>; + #clock-cells = <0>; + }; + usia_u0_sclk: usia_u0_sclk { + compatible = "renesas,emev2-smu-gclk"; + reg = <0x4a0 1>; + clocks = <&usia_u0_sclkdiv>; + #clock-cells = <0>; + }; + usib_u1_sclk: usib_u1_sclk { + compatible = "renesas,emev2-smu-gclk"; + reg = <0x4b8 1>; + clocks = <&usib_u1_sclkdiv>; + #clock-cells = <0>; + }; + usib_u2_sclk: usib_u2_sclk { + compatible = "renesas,emev2-smu-gclk"; + reg = <0x4bc 1>; + clocks = <&usib_u2_sclkdiv>; + #clock-cells = <0>; + }; + usib_u3_sclk: usib_u3_sclk { + compatible = "renesas,emev2-smu-gclk"; + reg = <0x4c0 1>; + clocks = <&usib_u3_sclkdiv>; + #clock-cells = <0>; + }; + sti_sclk: sti_sclk { + compatible = "renesas,emev2-smu-gclk"; + reg = <0x528 1>; + clocks = <&c32ki>; + #clock-cells = <0>; + }; + }; + sti@e0180000 { compatible = "renesas,em-sti"; reg = <0xe0180000 0x54>; interrupts = <0 125 0>; + clocks = <&sti_sclk>; + clock-names = "sclk"; }; uart@e1020000 { compatible = "renesas,em-uart"; reg = <0xe1020000 0x38>; interrupts = <0 8 0>; + clocks = <&usia_u0_sclk>; + clock-names = "sclk"; }; uart@e1030000 { compatible = "renesas,em-uart"; reg = <0xe1030000 0x38>; interrupts = <0 9 0>; + clocks = <&usib_u1_sclk>; + clock-names = "sclk"; }; uart@e1040000 { compatible = "renesas,em-uart"; reg = <0xe1040000 0x38>; interrupts = <0 10 0>; + clocks = <&usib_u2_sclk>; + clock-names = "sclk"; }; uart@e1050000 { compatible = "renesas,em-uart"; reg = <0xe1050000 0x38>; interrupts = <0 11 0>; + clocks = <&usib_u3_sclk>; + clock-names = "sclk"; }; gpio0: gpio@e0050000 { -- cgit v1.1 From ae4273ec7b25c8b9c895a4aae31f2fced980b7bf Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 3 Oct 2013 23:44:15 -0700 Subject: ARM: shmobile: r8a7778: add I2C support on DTSI Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7778.dtsi | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index ca88b3b..698809f 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -194,4 +194,44 @@ cap-sdio-irq; status = "disabled"; }; + + i2c0: i2c@ffc70000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7778"; + reg = <0xffc70000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 67 0x4>; + status = "disabled"; + }; + + i2c1: i2c@ffc71000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7778"; + reg = <0xffc71000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 78 0x4>; + status = "disabled"; + }; + + i2c2: i2c@ffc72000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7778"; + reg = <0xffc72000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 76 0x4>; + status = "disabled"; + }; + + i2c3: i2c@ffc73000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7778"; + reg = <0xffc73000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 77 0x4>; + status = "disabled"; + }; }; -- cgit v1.1 From a50da08569b2d9804575c0cf9d0b67db049afa81 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 31 Oct 2013 18:22:21 -0700 Subject: ARM: shmobile: r8a7778: add HSPI suppport on DTSI Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7778.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index 698809f..819b194 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -25,6 +25,12 @@ }; }; + aliases { + spi0 = &hspi0; + spi1 = &hspi1; + spi2 = &hspi2; + }; + gic: interrupt-controller@fe438000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; @@ -234,4 +240,28 @@ interrupts = <0 77 0x4>; status = "disabled"; }; + + hspi0: spi@fffc7000 { + compatible = "renesas,hspi"; + reg = <0xfffc7000 0x18>; + interrupt-controller = <&gic>; + interrupts = <0 63 4>; + status = "disabled"; + }; + + hspi1: spi@fffc8000 { + compatible = "renesas,hspi"; + reg = <0xfffc8000 0x18>; + interrupt-controller = <&gic>; + interrupts = <0 84 4>; + status = "disabled"; + }; + + hspi2: spi@fffc6000 { + compatible = "renesas,hspi"; + reg = <0xfffc6000 0x18>; + interrupt-controller = <&gic>; + interrupts = <0 85 4>; + status = "disabled"; + }; }; -- cgit v1.1 From 8c6639665d9771d2e84fe6e0915d46a6fbb8594e Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 31 Oct 2013 18:22:53 -0700 Subject: ARM: shmobile: bockw: enable HSPI0 on DTS Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7778-bockw-reference.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7778-bockw-reference.dts b/arch/arm/boot/dts/r8a7778-bockw-reference.dts index 9c8bd37..f488c48 100644 --- a/arch/arm/boot/dts/r8a7778-bockw-reference.dts +++ b/arch/arm/boot/dts/r8a7778-bockw-reference.dts @@ -86,6 +86,11 @@ "sdhi0_cd", "sdhi0_wp"; renesas,function = "sdhi0"; }; + + hspi0_pins: hspi0 { + renesas,groups = "hspi0_a"; + renesas,function = "hspi0"; + }; }; &sdhi0 { @@ -96,3 +101,9 @@ bus-width = <4>; status = "okay"; }; + +&hspi0 { + pinctrl-0 = <&hspi0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; -- cgit v1.1 From 31c46cbf5b8bab87e89028977521c84f2d871040 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sat, 9 Nov 2013 13:23:53 +0100 Subject: ARM: shmobile: Use #include in device tree sources In order to allow usage of the preprocessor in the SoC device tree sources, switch from /include/ to #include. Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r7s72100-genmai.dts | 2 +- arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts | 2 +- arch/arm/boot/dts/r8a73a4-ape6evm.dts | 2 +- arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts | 2 +- arch/arm/boot/dts/r8a7740-armadillo800eva.dts | 2 +- arch/arm/boot/dts/r8a7778-bockw-reference.dts | 2 +- arch/arm/boot/dts/r8a7778-bockw.dts | 2 +- arch/arm/boot/dts/r8a7779-marzen-reference.dts | 2 +- arch/arm/boot/dts/r8a7779-marzen.dts | 2 +- arch/arm/boot/dts/r8a7790-lager-reference.dts | 2 +- arch/arm/boot/dts/r8a7790-lager.dts | 2 +- arch/arm/boot/dts/r8a7791-koelsch-reference.dts | 2 +- arch/arm/boot/dts/r8a7791-koelsch.dts | 2 +- arch/arm/boot/dts/sh7372-mackerel.dts | 2 +- arch/arm/boot/dts/sh73a0-kzm9g-reference.dts | 2 +- arch/arm/boot/dts/sh73a0-kzm9g.dts | 2 +- 16 files changed, 16 insertions(+), 16 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts index 1fb20f2..b1deaf7 100644 --- a/arch/arm/boot/dts/r7s72100-genmai.dts +++ b/arch/arm/boot/dts/r7s72100-genmai.dts @@ -9,7 +9,7 @@ */ /dts-v1/; -/include/ "r7s72100.dtsi" +#include "r7s72100.dtsi" / { model = "Genmai"; diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts index 25dbc1c..338f0cb 100644 --- a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts +++ b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts @@ -9,7 +9,7 @@ */ /dts-v1/; -/include/ "r8a73a4.dtsi" +#include "r8a73a4.dtsi" #include / { diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts index 91436b5..7db8d79 100644 --- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts +++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts @@ -9,7 +9,7 @@ */ /dts-v1/; -/include/ "r8a73a4.dtsi" +#include "r8a73a4.dtsi" / { model = "APE6EVM"; diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts index 6a54219..c7c5bcb 100644 --- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts @@ -9,7 +9,7 @@ */ /dts-v1/; -/include/ "r8a7740.dtsi" +#include "r8a7740.dtsi" #include #include diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts index 426cd9c..a06a11e 100644 --- a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts @@ -9,7 +9,7 @@ */ /dts-v1/; -/include/ "r8a7740.dtsi" +#include "r8a7740.dtsi" / { model = "armadillo 800 eva"; diff --git a/arch/arm/boot/dts/r8a7778-bockw-reference.dts b/arch/arm/boot/dts/r8a7778-bockw-reference.dts index f488c48..be9b753 100644 --- a/arch/arm/boot/dts/r8a7778-bockw-reference.dts +++ b/arch/arm/boot/dts/r8a7778-bockw-reference.dts @@ -15,7 +15,7 @@ */ /dts-v1/; -/include/ "r8a7778.dtsi" +#include "r8a7778.dtsi" / { model = "bockw"; diff --git a/arch/arm/boot/dts/r8a7778-bockw.dts b/arch/arm/boot/dts/r8a7778-bockw.dts index 12bbebc..46a884d 100644 --- a/arch/arm/boot/dts/r8a7778-bockw.dts +++ b/arch/arm/boot/dts/r8a7778-bockw.dts @@ -15,7 +15,7 @@ */ /dts-v1/; -/include/ "r8a7778.dtsi" +#include "r8a7778.dtsi" / { model = "bockw"; diff --git a/arch/arm/boot/dts/r8a7779-marzen-reference.dts b/arch/arm/boot/dts/r8a7779-marzen-reference.dts index ce3fe9e..08b9ee37 100644 --- a/arch/arm/boot/dts/r8a7779-marzen-reference.dts +++ b/arch/arm/boot/dts/r8a7779-marzen-reference.dts @@ -10,7 +10,7 @@ */ /dts-v1/; -/include/ "r8a7779.dtsi" +#include "r8a7779.dtsi" #include / { diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts index f3f7f79..a7af2c2 100644 --- a/arch/arm/boot/dts/r8a7779-marzen.dts +++ b/arch/arm/boot/dts/r8a7779-marzen.dts @@ -10,7 +10,7 @@ */ /dts-v1/; -/include/ "r8a7779.dtsi" +#include "r8a7779.dtsi" / { model = "marzen"; diff --git a/arch/arm/boot/dts/r8a7790-lager-reference.dts b/arch/arm/boot/dts/r8a7790-lager-reference.dts index ec82674..cce7dbf 100644 --- a/arch/arm/boot/dts/r8a7790-lager-reference.dts +++ b/arch/arm/boot/dts/r8a7790-lager-reference.dts @@ -9,7 +9,7 @@ */ /dts-v1/; -/include/ "r8a7790.dtsi" +#include "r8a7790.dtsi" #include / { diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 203bd08..8799dfb 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -9,7 +9,7 @@ */ /dts-v1/; -/include/ "r8a7790.dtsi" +#include "r8a7790.dtsi" / { model = "Lager"; diff --git a/arch/arm/boot/dts/r8a7791-koelsch-reference.dts b/arch/arm/boot/dts/r8a7791-koelsch-reference.dts index b8a374a..1a0f082 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch-reference.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch-reference.dts @@ -10,7 +10,7 @@ */ /dts-v1/; -/include/ "r8a7791.dtsi" +#include "r8a7791.dtsi" / { model = "Koelsch"; diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index 1ce5250..c4e8b3a 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -10,7 +10,7 @@ */ /dts-v1/; -/include/ "r8a7791.dtsi" +#include "r8a7791.dtsi" / { model = "Koelsch"; diff --git a/arch/arm/boot/dts/sh7372-mackerel.dts b/arch/arm/boot/dts/sh7372-mackerel.dts index 8acf51e..a759a27 100644 --- a/arch/arm/boot/dts/sh7372-mackerel.dts +++ b/arch/arm/boot/dts/sh7372-mackerel.dts @@ -9,7 +9,7 @@ */ /dts-v1/; -/include/ "sh7372.dtsi" +#include "sh7372.dtsi" / { model = "Mackerel (AP4 EVM 2nd)"; diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts index df75aea..d5a6d74 100644 --- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts +++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts @@ -12,7 +12,7 @@ */ /dts-v1/; -/include/ "sh73a0.dtsi" +#include "sh73a0.dtsi" #include / { diff --git a/arch/arm/boot/dts/sh73a0-kzm9g.dts b/arch/arm/boot/dts/sh73a0-kzm9g.dts index 0f1ca77..27c5f42 100644 --- a/arch/arm/boot/dts/sh73a0-kzm9g.dts +++ b/arch/arm/boot/dts/sh73a0-kzm9g.dts @@ -9,7 +9,7 @@ */ /dts-v1/; -/include/ "sh73a0.dtsi" +#include "sh73a0.dtsi" / { model = "KZM-A9-GT"; -- cgit v1.1 From 5f75e73c376c247a2c7bbe6f3fa3901b2d8f1a9c Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 19 Nov 2013 03:18:25 +0100 Subject: ARM: shmobile: Use interrupt macros in SoC DT files Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a73a4.dtsi | 108 ++++++++++++++++++++++++---------- arch/arm/boot/dts/r8a7740.dtsi | 106 +++++++++++++++++----------------- arch/arm/boot/dts/r8a7778.dtsi | 44 +++++++------- arch/arm/boot/dts/r8a7779.dtsi | 42 +++++++------- arch/arm/boot/dts/r8a7790.dtsi | 50 +++++++++------- arch/arm/boot/dts/r8a7791.dtsi | 49 ++++++++-------- arch/arm/boot/dts/sh73a0.dtsi | 128 +++++++++++++++++++++-------------------- 7 files changed, 295 insertions(+), 232 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index e079c99..b4a6c3b 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -9,6 +9,9 @@ * kind, whether express or implied. */ +#include +#include + / { compatible = "renesas,r8a73a4"; interrupt-parent = <&gic>; @@ -36,15 +39,15 @@ <0 0xf1002000 0 0x1000>, <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; - interrupts = <1 9 0xf04>; + interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; timer { compatible = "arm,armv7-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; + interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; irqc0: interrupt-controller@e61c0000 { @@ -53,14 +56,38 @@ interrupt-controller; reg = <0 0xe61c0000 0 0x200>; interrupt-parent = <&gic>; - interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>, - <0 4 4>, <0 5 4>, <0 6 4>, <0 7 4>, - <0 8 4>, <0 9 4>, <0 10 4>, <0 11 4>, - <0 12 4>, <0 13 4>, <0 14 4>, <0 15 4>, - <0 16 4>, <0 17 4>, <0 18 4>, <0 19 4>, - <0 20 4>, <0 21 4>, <0 22 4>, <0 23 4>, - <0 24 4>, <0 25 4>, <0 26 4>, <0 27 4>, - <0 28 4>, <0 29 4>, <0 30 4>, <0 31 4>; + interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, + <0 1 IRQ_TYPE_LEVEL_HIGH>, + <0 2 IRQ_TYPE_LEVEL_HIGH>, + <0 3 IRQ_TYPE_LEVEL_HIGH>, + <0 4 IRQ_TYPE_LEVEL_HIGH>, + <0 5 IRQ_TYPE_LEVEL_HIGH>, + <0 6 IRQ_TYPE_LEVEL_HIGH>, + <0 7 IRQ_TYPE_LEVEL_HIGH>, + <0 8 IRQ_TYPE_LEVEL_HIGH>, + <0 9 IRQ_TYPE_LEVEL_HIGH>, + <0 10 IRQ_TYPE_LEVEL_HIGH>, + <0 11 IRQ_TYPE_LEVEL_HIGH>, + <0 12 IRQ_TYPE_LEVEL_HIGH>, + <0 13 IRQ_TYPE_LEVEL_HIGH>, + <0 14 IRQ_TYPE_LEVEL_HIGH>, + <0 15 IRQ_TYPE_LEVEL_HIGH>, + <0 16 IRQ_TYPE_LEVEL_HIGH>, + <0 17 IRQ_TYPE_LEVEL_HIGH>, + <0 18 IRQ_TYPE_LEVEL_HIGH>, + <0 19 IRQ_TYPE_LEVEL_HIGH>, + <0 20 IRQ_TYPE_LEVEL_HIGH>, + <0 21 IRQ_TYPE_LEVEL_HIGH>, + <0 22 IRQ_TYPE_LEVEL_HIGH>, + <0 23 IRQ_TYPE_LEVEL_HIGH>, + <0 24 IRQ_TYPE_LEVEL_HIGH>, + <0 25 IRQ_TYPE_LEVEL_HIGH>, + <0 26 IRQ_TYPE_LEVEL_HIGH>, + <0 27 IRQ_TYPE_LEVEL_HIGH>, + <0 28 IRQ_TYPE_LEVEL_HIGH>, + <0 29 IRQ_TYPE_LEVEL_HIGH>, + <0 30 IRQ_TYPE_LEVEL_HIGH>, + <0 31 IRQ_TYPE_LEVEL_HIGH>; }; irqc1: interrupt-controller@e61c0200 { @@ -69,13 +96,32 @@ interrupt-controller; reg = <0 0xe61c0200 0 0x200>; interrupt-parent = <&gic>; - interrupts = <0 32 4>, <0 33 4>, <0 34 4>, <0 35 4>, - <0 36 4>, <0 37 4>, <0 38 4>, <0 39 4>, - <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>, - <0 44 4>, <0 45 4>, <0 46 4>, <0 47 4>, - <0 48 4>, <0 49 4>, <0 50 4>, <0 51 4>, - <0 52 4>, <0 53 4>, <0 54 4>, <0 55 4>, - <0 56 4>, <0 57 4>; + interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>, + <0 33 IRQ_TYPE_LEVEL_HIGH>, + <0 34 IRQ_TYPE_LEVEL_HIGH>, + <0 35 IRQ_TYPE_LEVEL_HIGH>, + <0 36 IRQ_TYPE_LEVEL_HIGH>, + <0 37 IRQ_TYPE_LEVEL_HIGH>, + <0 38 IRQ_TYPE_LEVEL_HIGH>, + <0 39 IRQ_TYPE_LEVEL_HIGH>, + <0 40 IRQ_TYPE_LEVEL_HIGH>, + <0 41 IRQ_TYPE_LEVEL_HIGH>, + <0 42 IRQ_TYPE_LEVEL_HIGH>, + <0 43 IRQ_TYPE_LEVEL_HIGH>, + <0 44 IRQ_TYPE_LEVEL_HIGH>, + <0 45 IRQ_TYPE_LEVEL_HIGH>, + <0 46 IRQ_TYPE_LEVEL_HIGH>, + <0 47 IRQ_TYPE_LEVEL_HIGH>, + <0 48 IRQ_TYPE_LEVEL_HIGH>, + <0 49 IRQ_TYPE_LEVEL_HIGH>, + <0 50 IRQ_TYPE_LEVEL_HIGH>, + <0 51 IRQ_TYPE_LEVEL_HIGH>, + <0 52 IRQ_TYPE_LEVEL_HIGH>, + <0 53 IRQ_TYPE_LEVEL_HIGH>, + <0 54 IRQ_TYPE_LEVEL_HIGH>, + <0 55 IRQ_TYPE_LEVEL_HIGH>, + <0 56 IRQ_TYPE_LEVEL_HIGH>, + <0 57 IRQ_TYPE_LEVEL_HIGH>; }; dmac: dma-multiplexer@0 { @@ -126,7 +172,7 @@ reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>, <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>; interrupt-parent = <&gic>; - interrupts = <0 69 4>; + interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; }; i2c0: i2c@e6500000 { @@ -175,7 +221,7 @@ compatible = "renesas,rmobile-iic"; reg = <0 0xe6540000 0 0x428>; interrupt-parent = <&gic>; - interrupts = <0 178 0x4>; + interrupts = <0 178 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -185,7 +231,7 @@ compatible = "renesas,rmobile-iic"; reg = <0 0xe60b0000 0 0x428>; interrupt-parent = <&gic>; - interrupts = <0 179 0x4>; + interrupts = <0 179 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -195,7 +241,7 @@ compatible = "renesas,rmobile-iic"; reg = <0 0xe6550000 0 0x428>; interrupt-parent = <&gic>; - interrupts = <0 184 0x4>; + interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -205,7 +251,7 @@ compatible = "renesas,rmobile-iic"; reg = <0 0xe6560000 0 0x428>; interrupt-parent = <&gic>; - interrupts = <0 185 0x4>; + interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -215,7 +261,7 @@ compatible = "renesas,rmobile-iic"; reg = <0 0xe6570000 0 0x428>; interrupt-parent = <&gic>; - interrupts = <0 173 0x4>; + interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -223,7 +269,7 @@ compatible = "renesas,sh-mmcif"; reg = <0 0xee200000 0 0x80>; interrupt-parent = <&gic>; - interrupts = <0 169 0x4>; + interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <4>; status = "disabled"; }; @@ -232,7 +278,7 @@ compatible = "renesas,sh-mmcif"; reg = <0 0xee220000 0 0x80>; interrupt-parent = <&gic>; - interrupts = <0 170 0x4>; + interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <4>; status = "disabled"; }; @@ -248,7 +294,7 @@ compatible = "renesas,sdhi-r8a73a4"; reg = <0 0xee100000 0 0x100>; interrupt-parent = <&gic>; - interrupts = <0 165 4>; + interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; cap-sd-highspeed; status = "disabled"; }; @@ -257,7 +303,7 @@ compatible = "renesas,sdhi-r8a73a4"; reg = <0 0xee120000 0 0x100>; interrupt-parent = <&gic>; - interrupts = <0 166 4>; + interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>; cap-sd-highspeed; status = "disabled"; }; @@ -266,7 +312,7 @@ compatible = "renesas,sdhi-r8a73a4"; reg = <0 0xee140000 0 0x100>; interrupt-parent = <&gic>; - interrupts = <0 167 4>; + interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; cap-sd-highspeed; status = "disabled"; }; diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index 4cc945a..b1c2ed9 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -10,6 +10,8 @@ /include/ "skeleton.dtsi" +#include + / { compatible = "renesas,r8a7740"; @@ -34,7 +36,7 @@ pmu { compatible = "arm,cortex-a9-pmu"; - interrupts = <0 83 4>; + interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; }; /* irqpin0: IRQ0 - IRQ7 */ @@ -48,14 +50,14 @@ <0xe6900040 1>, <0xe6900060 1>; interrupt-parent = <&gic>; - interrupts = <0 149 0x4 - 0 149 0x4 - 0 149 0x4 - 0 149 0x4 - 0 149 0x4 - 0 149 0x4 - 0 149 0x4 - 0 149 0x4>; + interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH>; }; /* irqpin1: IRQ8 - IRQ15 */ @@ -69,14 +71,14 @@ <0xe6900044 1>, <0xe6900064 1>; interrupt-parent = <&gic>; - interrupts = <0 149 0x4 - 0 149 0x4 - 0 149 0x4 - 0 149 0x4 - 0 149 0x4 - 0 149 0x4 - 0 149 0x4 - 0 149 0x4>; + interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH>; }; /* irqpin2: IRQ16 - IRQ23 */ @@ -90,14 +92,14 @@ <0xe6900048 1>, <0xe6900068 1>; interrupt-parent = <&gic>; - interrupts = <0 149 0x4 - 0 149 0x4 - 0 149 0x4 - 0 149 0x4 - 0 149 0x4 - 0 149 0x4 - 0 149 0x4 - 0 149 0x4>; + interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH>; }; /* irqpin3: IRQ24 - IRQ31 */ @@ -111,14 +113,14 @@ <0xe690004c 1>, <0xe690006c 1>; interrupt-parent = <&gic>; - interrupts = <0 149 0x4 - 0 149 0x4 - 0 149 0x4 - 0 149 0x4 - 0 149 0x4 - 0 149 0x4 - 0 149 0x4 - 0 149 0x4>; + interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH + 0 149 IRQ_TYPE_LEVEL_HIGH>; }; i2c0: i2c@fff20000 { @@ -127,10 +129,10 @@ compatible = "renesas,rmobile-iic"; reg = <0xfff20000 0x425>; interrupt-parent = <&gic>; - interrupts = <0 201 0x4 - 0 202 0x4 - 0 203 0x4 - 0 204 0x4>; + interrupts = <0 201 IRQ_TYPE_LEVEL_HIGH + 0 202 IRQ_TYPE_LEVEL_HIGH + 0 203 IRQ_TYPE_LEVEL_HIGH + 0 204 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -140,10 +142,10 @@ compatible = "renesas,rmobile-iic"; reg = <0xe6c20000 0x425>; interrupt-parent = <&gic>; - interrupts = <0 70 0x4 - 0 71 0x4 - 0 72 0x4 - 0 73 0x4>; + interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH + 0 71 IRQ_TYPE_LEVEL_HIGH + 0 72 IRQ_TYPE_LEVEL_HIGH + 0 73 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -166,8 +168,8 @@ compatible = "renesas,sh-mmcif"; reg = <0xe6bd0000 0x100>; interrupt-parent = <&gic>; - interrupts = <0 56 4 - 0 57 4>; + interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH + 0 57 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -175,9 +177,9 @@ compatible = "renesas,sdhi-r8a7740"; reg = <0xe6850000 0x100>; interrupt-parent = <&gic>; - interrupts = <0 117 4 - 0 118 4 - 0 119 4>; + interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH + 0 118 IRQ_TYPE_LEVEL_HIGH + 0 119 IRQ_TYPE_LEVEL_HIGH>; cap-sd-highspeed; cap-sdio-irq; status = "disabled"; @@ -187,9 +189,9 @@ compatible = "renesas,sdhi-r8a7740"; reg = <0xe6860000 0x100>; interrupt-parent = <&gic>; - interrupts = <0 121 4 - 0 122 4 - 0 123 4>; + interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH + 0 122 IRQ_TYPE_LEVEL_HIGH + 0 123 IRQ_TYPE_LEVEL_HIGH>; cap-sd-highspeed; cap-sdio-irq; status = "disabled"; @@ -199,9 +201,9 @@ compatible = "renesas,sdhi-r8a7740"; reg = <0xe6870000 0x100>; interrupt-parent = <&gic>; - interrupts = <0 125 4 - 0 126 4 - 0 127 4>; + interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH + 0 126 IRQ_TYPE_LEVEL_HIGH + 0 127 IRQ_TYPE_LEVEL_HIGH>; cap-sd-highspeed; cap-sdio-irq; status = "disabled"; diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index 819b194..3314e0a 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -16,6 +16,8 @@ /include/ "skeleton.dtsi" +#include + / { compatible = "renesas,r8a7778"; @@ -51,10 +53,10 @@ <0xfe780044 4>, <0xfe780064 4>; interrupt-parent = <&gic>; - interrupts = <0 27 0x4 - 0 28 0x4 - 0 29 0x4 - 0 30 0x4>; + interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH + 0 28 IRQ_TYPE_LEVEL_HIGH + 0 29 IRQ_TYPE_LEVEL_HIGH + 0 30 IRQ_TYPE_LEVEL_HIGH>; sense-bitfield-width = <2>; }; @@ -62,7 +64,7 @@ compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; reg = <0xffc40000 0x2c>; interrupt-parent = <&gic>; - interrupts = <0 103 0x4>; + interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 0 32>; @@ -74,7 +76,7 @@ compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; reg = <0xffc41000 0x2c>; interrupt-parent = <&gic>; - interrupts = <0 103 0x4>; + interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 32 32>; @@ -86,7 +88,7 @@ compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; reg = <0xffc42000 0x2c>; interrupt-parent = <&gic>; - interrupts = <0 103 0x4>; + interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 64 32>; @@ -98,7 +100,7 @@ compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; reg = <0xffc43000 0x2c>; interrupt-parent = <&gic>; - interrupts = <0 103 0x4>; + interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 96 32>; @@ -110,7 +112,7 @@ compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; reg = <0xffc44000 0x2c>; interrupt-parent = <&gic>; - interrupts = <0 103 0x4>; + interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 128 27>; @@ -129,7 +131,7 @@ compatible = "renesas,i2c-r8a7778"; reg = <0xffc70000 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 67 0x4>; + interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -139,7 +141,7 @@ compatible = "renesas,i2c-r8a7778"; reg = <0xffc71000 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 78 0x4>; + interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -149,7 +151,7 @@ compatible = "renesas,i2c-r8a7778"; reg = <0xffc72000 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 76 0x4>; + interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -159,7 +161,7 @@ compatible = "renesas,i2c-r8a7778"; reg = <0xffc73000 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 77 0x4>; + interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -167,7 +169,7 @@ compatible = "renesas,sh-mmcif"; reg = <0xffe4e000 0x100>; interrupt-parent = <&gic>; - interrupts = <0 61 4>; + interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -175,7 +177,7 @@ compatible = "renesas,sdhi-r8a7778"; reg = <0xffe4c000 0x100>; interrupt-parent = <&gic>; - interrupts = <0 87 4>; + interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>; cap-sd-highspeed; cap-sdio-irq; status = "disabled"; @@ -185,7 +187,7 @@ compatible = "renesas,sdhi-r8a7778"; reg = <0xffe4d000 0x100>; interrupt-parent = <&gic>; - interrupts = <0 88 4>; + interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>; cap-sd-highspeed; cap-sdio-irq; status = "disabled"; @@ -195,7 +197,7 @@ compatible = "renesas,sdhi-r8a7778"; reg = <0xffe4f000 0x100>; interrupt-parent = <&gic>; - interrupts = <0 86 4>; + interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; cap-sd-highspeed; cap-sdio-irq; status = "disabled"; @@ -207,7 +209,7 @@ compatible = "renesas,i2c-r8a7778"; reg = <0xffc70000 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 67 0x4>; + interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -217,7 +219,7 @@ compatible = "renesas,i2c-r8a7778"; reg = <0xffc71000 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 78 0x4>; + interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -227,7 +229,7 @@ compatible = "renesas,i2c-r8a7778"; reg = <0xffc72000 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 76 0x4>; + interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -237,7 +239,7 @@ compatible = "renesas,i2c-r8a7778"; reg = <0xffc73000 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 77 0x4>; + interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index 05fd41c..b2b418a 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -11,6 +11,8 @@ /include/ "skeleton.dtsi" +#include + / { compatible = "renesas,r8a7779"; @@ -52,7 +54,7 @@ compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; reg = <0xffc40000 0x2c>; interrupt-parent = <&gic>; - interrupts = <0 141 0x4>; + interrupts = <0 141 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 0 32>; @@ -64,7 +66,7 @@ compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; reg = <0xffc41000 0x2c>; interrupt-parent = <&gic>; - interrupts = <0 142 0x4>; + interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 32 32>; @@ -76,7 +78,7 @@ compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; reg = <0xffc42000 0x2c>; interrupt-parent = <&gic>; - interrupts = <0 143 0x4>; + interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 64 32>; @@ -88,7 +90,7 @@ compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; reg = <0xffc43000 0x2c>; interrupt-parent = <&gic>; - interrupts = <0 144 0x4>; + interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 96 32>; @@ -100,7 +102,7 @@ compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; reg = <0xffc44000 0x2c>; interrupt-parent = <&gic>; - interrupts = <0 145 0x4>; + interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 128 32>; @@ -112,7 +114,7 @@ compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; reg = <0xffc45000 0x2c>; interrupt-parent = <&gic>; - interrupts = <0 146 0x4>; + interrupts = <0 146 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 160 32>; @@ -124,7 +126,7 @@ compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; reg = <0xffc46000 0x2c>; interrupt-parent = <&gic>; - interrupts = <0 147 0x4>; + interrupts = <0 147 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 192 9>; @@ -143,10 +145,10 @@ <0xfe780044 4>, <0xfe780064 4>; interrupt-parent = <&gic>; - interrupts = <0 27 0x4 - 0 28 0x4 - 0 29 0x4 - 0 30 0x4>; + interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH + 0 28 IRQ_TYPE_LEVEL_HIGH + 0 29 IRQ_TYPE_LEVEL_HIGH + 0 30 IRQ_TYPE_LEVEL_HIGH>; sense-bitfield-width = <2>; }; @@ -156,7 +158,7 @@ compatible = "renesas,i2c-r8a7779"; reg = <0xffc70000 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 79 0x4>; + interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -166,7 +168,7 @@ compatible = "renesas,i2c-r8a7779"; reg = <0xffc71000 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 82 0x4>; + interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -176,7 +178,7 @@ compatible = "renesas,i2c-r8a7779"; reg = <0xffc72000 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 80 0x4>; + interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -186,7 +188,7 @@ compatible = "renesas,i2c-r8a7779"; reg = <0xffc73000 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 81 0x4>; + interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -204,14 +206,14 @@ compatible = "renesas,rcar-sata"; reg = <0xfc600000 0x2000>; interrupt-parent = <&gic>; - interrupts = <0 100 0x4>; + interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; }; sdhi0: sd@ffe4c000 { compatible = "renesas,sdhi-r8a7779"; reg = <0xffe4c000 0x100>; interrupt-parent = <&gic>; - interrupts = <0 104 4>; + interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>; cap-sd-highspeed; cap-sdio-irq; status = "disabled"; @@ -221,7 +223,7 @@ compatible = "renesas,sdhi-r8a7779"; reg = <0xffe4d000 0x100>; interrupt-parent = <&gic>; - interrupts = <0 105 4>; + interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; cap-sd-highspeed; cap-sdio-irq; status = "disabled"; @@ -231,7 +233,7 @@ compatible = "renesas,sdhi-r8a7779"; reg = <0xffe4e000 0x100>; interrupt-parent = <&gic>; - interrupts = <0 107 4>; + interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; cap-sd-highspeed; cap-sdio-irq; status = "disabled"; @@ -241,7 +243,7 @@ compatible = "renesas,sdhi-r8a7779"; reg = <0xffe4f000 0x100>; interrupt-parent = <&gic>; - interrupts = <0 106 4>; + interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; cap-sd-highspeed; cap-sdio-irq; status = "disabled"; diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 5ae7db6..3800952 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -8,6 +8,9 @@ * kind, whether express or implied. */ +#include +#include + / { compatible = "renesas,r8a7790"; interrupt-parent = <&gic>; @@ -84,14 +87,14 @@ <0 0xf1002000 0 0x1000>, <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; - interrupts = <1 9 0xf04>; + interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; gpio0: gpio@ffc40000 { compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; reg = <0 0xffc40000 0 0x2c>; interrupt-parent = <&gic>; - interrupts = <0 4 0x4>; + interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 0 32>; @@ -103,7 +106,7 @@ compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; reg = <0 0xffc41000 0 0x2c>; interrupt-parent = <&gic>; - interrupts = <0 5 0x4>; + interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 32 32>; @@ -115,7 +118,7 @@ compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; reg = <0 0xffc42000 0 0x2c>; interrupt-parent = <&gic>; - interrupts = <0 6 0x4>; + interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 64 32>; @@ -127,7 +130,7 @@ compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; reg = <0 0xffc43000 0 0x2c>; interrupt-parent = <&gic>; - interrupts = <0 7 0x4>; + interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 96 32>; @@ -139,7 +142,7 @@ compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; reg = <0 0xffc44000 0 0x2c>; interrupt-parent = <&gic>; - interrupts = <0 8 0x4>; + interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 128 32>; @@ -151,7 +154,7 @@ compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; reg = <0 0xffc45000 0 0x2c>; interrupt-parent = <&gic>; - interrupts = <0 9 0x4>; + interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 160 32>; @@ -161,10 +164,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; + interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; irqc0: interrupt-controller@e61c0000 { @@ -173,7 +176,10 @@ interrupt-controller; reg = <0 0xe61c0000 0 0x200>; interrupt-parent = <&gic>; - interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>; + interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, + <0 1 IRQ_TYPE_LEVEL_HIGH>, + <0 2 IRQ_TYPE_LEVEL_HIGH>, + <0 3 IRQ_TYPE_LEVEL_HIGH>; }; i2c0: i2c@e6508000 { @@ -182,7 +188,7 @@ compatible = "renesas,i2c-r8a7790"; reg = <0 0xe6508000 0 0x40>; interrupt-parent = <&gic>; - interrupts = <0 287 0x4>; + interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -192,7 +198,7 @@ compatible = "renesas,i2c-r8a7790"; reg = <0 0xe6518000 0 0x40>; interrupt-parent = <&gic>; - interrupts = <0 288 0x4>; + interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -202,7 +208,7 @@ compatible = "renesas,i2c-r8a7790"; reg = <0 0xe6530000 0 0x40>; interrupt-parent = <&gic>; - interrupts = <0 286 0x4>; + interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -212,7 +218,7 @@ compatible = "renesas,i2c-r8a7790"; reg = <0 0xe6540000 0 0x40>; interrupt-parent = <&gic>; - interrupts = <0 290 0x4>; + interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -220,7 +226,7 @@ compatible = "renesas,sh-mmcif"; reg = <0 0xee200000 0 0x80>; interrupt-parent = <&gic>; - interrupts = <0 169 0x4>; + interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <4>; status = "disabled"; }; @@ -229,7 +235,7 @@ compatible = "renesas,sh-mmcif"; reg = <0 0xee220000 0 0x80>; interrupt-parent = <&gic>; - interrupts = <0 170 0x4>; + interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <4>; status = "disabled"; }; @@ -243,7 +249,7 @@ compatible = "renesas,sdhi-r8a7790"; reg = <0 0xee100000 0 0x100>; interrupt-parent = <&gic>; - interrupts = <0 165 4>; + interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; cap-sd-highspeed; status = "disabled"; }; @@ -252,7 +258,7 @@ compatible = "renesas,sdhi-r8a7790"; reg = <0 0xee120000 0 0x100>; interrupt-parent = <&gic>; - interrupts = <0 166 4>; + interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>; cap-sd-highspeed; status = "disabled"; }; @@ -261,7 +267,7 @@ compatible = "renesas,sdhi-r8a7790"; reg = <0 0xee140000 0 0x100>; interrupt-parent = <&gic>; - interrupts = <0 167 4>; + interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; cap-sd-highspeed; status = "disabled"; }; @@ -270,7 +276,7 @@ compatible = "renesas,sdhi-r8a7790"; reg = <0 0xee160000 0 0x100>; interrupt-parent = <&gic>; - interrupts = <0 168 4>; + interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; cap-sd-highspeed; status = "disabled"; }; diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 344f1f7..86d5d3a 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -9,6 +9,9 @@ * kind, whether express or implied. */ +#include +#include + / { compatible = "renesas,r8a7791"; interrupt-parent = <&gic>; @@ -43,14 +46,14 @@ <0 0xf1002000 0 0x1000>, <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; - interrupts = <1 9 0xf04>; + interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; gpio0: gpio@ffc40000 { compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; reg = <0 0xffc40000 0 0x50>; interrupt-parent = <&gic>; - interrupts = <0 4 0x4>; + interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 0 32>; @@ -62,7 +65,7 @@ compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; reg = <0 0xffc41000 0 0x50>; interrupt-parent = <&gic>; - interrupts = <0 5 0x4>; + interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 32 32>; @@ -74,7 +77,7 @@ compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; reg = <0 0xffc42000 0 0x50>; interrupt-parent = <&gic>; - interrupts = <0 6 0x4>; + interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 64 32>; @@ -86,7 +89,7 @@ compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; reg = <0 0xffc43000 0 0x50>; interrupt-parent = <&gic>; - interrupts = <0 7 0x4>; + interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 96 32>; @@ -98,7 +101,7 @@ compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; reg = <0 0xffc44000 0 0x50>; interrupt-parent = <&gic>; - interrupts = <0 8 0x4>; + interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 128 32>; @@ -110,7 +113,7 @@ compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; reg = <0 0xffc45000 0 0x50>; interrupt-parent = <&gic>; - interrupts = <0 9 0x4>; + interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 160 32>; @@ -122,7 +125,7 @@ compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; reg = <0 0xffc45400 0 0x50>; interrupt-parent = <&gic>; - interrupts = <0 10 0x4>; + interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 192 32>; @@ -134,7 +137,7 @@ compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; reg = <0 0xffc45800 0 0x50>; interrupt-parent = <&gic>; - interrupts = <0 11 0x4>; + interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 224 26>; @@ -144,10 +147,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; + interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; irqc0: interrupt-controller@e61c0000 { @@ -156,16 +159,16 @@ interrupt-controller; reg = <0 0xe61c0000 0 0x200>; interrupt-parent = <&gic>; - interrupts = <0 0 4>, - <0 1 4>, - <0 2 4>, - <0 3 4>, - <0 12 4>, - <0 13 4>, - <0 14 4>, - <0 15 4>, - <0 16 4>, - <0 17 4>; + interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, + <0 1 IRQ_TYPE_LEVEL_HIGH>, + <0 2 IRQ_TYPE_LEVEL_HIGH>, + <0 3 IRQ_TYPE_LEVEL_HIGH>, + <0 12 IRQ_TYPE_LEVEL_HIGH>, + <0 13 IRQ_TYPE_LEVEL_HIGH>, + <0 14 IRQ_TYPE_LEVEL_HIGH>, + <0 15 IRQ_TYPE_LEVEL_HIGH>, + <0 16 IRQ_TYPE_LEVEL_HIGH>, + <0 17 IRQ_TYPE_LEVEL_HIGH>; }; pfc: pfc@e6060000 { diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index 78f7201a..aef8a61 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -10,6 +10,8 @@ /include/ "skeleton.dtsi" +#include + / { compatible = "renesas,sh73a0"; @@ -40,8 +42,8 @@ pmu { compatible = "arm,cortex-a9-pmu"; - interrupts = <0 55 4>, - <0 56 4>; + interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>, + <0 56 IRQ_TYPE_LEVEL_HIGH>; }; irqpin0: irqpin@e6900000 { @@ -54,14 +56,14 @@ <0xe6900040 1>, <0xe6900060 1>; interrupt-parent = <&gic>; - interrupts = <0 1 0x4 - 0 2 0x4 - 0 3 0x4 - 0 4 0x4 - 0 5 0x4 - 0 6 0x4 - 0 7 0x4 - 0 8 0x4>; + interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH + 0 2 IRQ_TYPE_LEVEL_HIGH + 0 3 IRQ_TYPE_LEVEL_HIGH + 0 4 IRQ_TYPE_LEVEL_HIGH + 0 5 IRQ_TYPE_LEVEL_HIGH + 0 6 IRQ_TYPE_LEVEL_HIGH + 0 7 IRQ_TYPE_LEVEL_HIGH + 0 8 IRQ_TYPE_LEVEL_HIGH>; }; irqpin1: irqpin@e6900004 { @@ -74,14 +76,14 @@ <0xe6900044 1>, <0xe6900064 1>; interrupt-parent = <&gic>; - interrupts = <0 9 0x4 - 0 10 0x4 - 0 11 0x4 - 0 12 0x4 - 0 13 0x4 - 0 14 0x4 - 0 15 0x4 - 0 16 0x4>; + interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH + 0 10 IRQ_TYPE_LEVEL_HIGH + 0 11 IRQ_TYPE_LEVEL_HIGH + 0 12 IRQ_TYPE_LEVEL_HIGH + 0 13 IRQ_TYPE_LEVEL_HIGH + 0 14 IRQ_TYPE_LEVEL_HIGH + 0 15 IRQ_TYPE_LEVEL_HIGH + 0 16 IRQ_TYPE_LEVEL_HIGH>; control-parent; }; @@ -95,14 +97,14 @@ <0xe6900048 1>, <0xe6900068 1>; interrupt-parent = <&gic>; - interrupts = <0 17 0x4 - 0 18 0x4 - 0 19 0x4 - 0 20 0x4 - 0 21 0x4 - 0 22 0x4 - 0 23 0x4 - 0 24 0x4>; + interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH + 0 18 IRQ_TYPE_LEVEL_HIGH + 0 19 IRQ_TYPE_LEVEL_HIGH + 0 20 IRQ_TYPE_LEVEL_HIGH + 0 21 IRQ_TYPE_LEVEL_HIGH + 0 22 IRQ_TYPE_LEVEL_HIGH + 0 23 IRQ_TYPE_LEVEL_HIGH + 0 24 IRQ_TYPE_LEVEL_HIGH>; }; irqpin3: irqpin@e690000c { @@ -115,14 +117,14 @@ <0xe690004c 1>, <0xe690006c 1>; interrupt-parent = <&gic>; - interrupts = <0 25 0x4 - 0 26 0x4 - 0 27 0x4 - 0 28 0x4 - 0 29 0x4 - 0 30 0x4 - 0 31 0x4 - 0 32 0x4>; + interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH + 0 26 IRQ_TYPE_LEVEL_HIGH + 0 27 IRQ_TYPE_LEVEL_HIGH + 0 28 IRQ_TYPE_LEVEL_HIGH + 0 29 IRQ_TYPE_LEVEL_HIGH + 0 30 IRQ_TYPE_LEVEL_HIGH + 0 31 IRQ_TYPE_LEVEL_HIGH + 0 32 IRQ_TYPE_LEVEL_HIGH>; }; i2c0: i2c@e6820000 { @@ -131,10 +133,10 @@ compatible = "renesas,rmobile-iic"; reg = <0xe6820000 0x425>; interrupt-parent = <&gic>; - interrupts = <0 167 0x4 - 0 168 0x4 - 0 169 0x4 - 0 170 0x4>; + interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH + 0 168 IRQ_TYPE_LEVEL_HIGH + 0 169 IRQ_TYPE_LEVEL_HIGH + 0 170 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -144,10 +146,10 @@ compatible = "renesas,rmobile-iic"; reg = <0xe6822000 0x425>; interrupt-parent = <&gic>; - interrupts = <0 51 0x4 - 0 52 0x4 - 0 53 0x4 - 0 54 0x4>; + interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH + 0 52 IRQ_TYPE_LEVEL_HIGH + 0 53 IRQ_TYPE_LEVEL_HIGH + 0 54 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -157,10 +159,10 @@ compatible = "renesas,rmobile-iic"; reg = <0xe6824000 0x425>; interrupt-parent = <&gic>; - interrupts = <0 171 0x4 - 0 172 0x4 - 0 173 0x4 - 0 174 0x4>; + interrupts = <0 171 IRQ_TYPE_LEVEL_HIGH + 0 172 IRQ_TYPE_LEVEL_HIGH + 0 173 IRQ_TYPE_LEVEL_HIGH + 0 174 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -170,10 +172,10 @@ compatible = "renesas,rmobile-iic"; reg = <0xe6826000 0x425>; interrupt-parent = <&gic>; - interrupts = <0 183 0x4 - 0 184 0x4 - 0 185 0x4 - 0 186 0x4>; + interrupts = <0 183 IRQ_TYPE_LEVEL_HIGH + 0 184 IRQ_TYPE_LEVEL_HIGH + 0 185 IRQ_TYPE_LEVEL_HIGH + 0 186 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -183,10 +185,10 @@ compatible = "renesas,rmobile-iic"; reg = <0xe6828000 0x425>; interrupt-parent = <&gic>; - interrupts = <0 187 0x4 - 0 188 0x4 - 0 189 0x4 - 0 190 0x4>; + interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH + 0 188 IRQ_TYPE_LEVEL_HIGH + 0 189 IRQ_TYPE_LEVEL_HIGH + 0 190 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -194,8 +196,8 @@ compatible = "renesas,sh-mmcif"; reg = <0xe6bd0000 0x100>; interrupt-parent = <&gic>; - interrupts = <0 140 0x4 - 0 141 0x4>; + interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH + 0 141 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <4>; status = "disabled"; }; @@ -204,9 +206,9 @@ compatible = "renesas,sdhi-r8a7740"; reg = <0xee100000 0x100>; interrupt-parent = <&gic>; - interrupts = <0 83 4 - 0 84 4 - 0 85 4>; + interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH + 0 84 IRQ_TYPE_LEVEL_HIGH + 0 85 IRQ_TYPE_LEVEL_HIGH>; cap-sd-highspeed; status = "disabled"; }; @@ -216,8 +218,8 @@ compatible = "renesas,sdhi-r8a7740"; reg = <0xee120000 0x100>; interrupt-parent = <&gic>; - interrupts = <0 88 4 - 0 89 4>; + interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH + 0 89 IRQ_TYPE_LEVEL_HIGH>; toshiba,mmc-wrprotect-disable; cap-sd-highspeed; status = "disabled"; @@ -227,8 +229,8 @@ compatible = "renesas,sdhi-r8a7740"; reg = <0xee140000 0x100>; interrupt-parent = <&gic>; - interrupts = <0 104 4 - 0 105 4>; + interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH + 0 105 IRQ_TYPE_LEVEL_HIGH>; toshiba,mmc-wrprotect-disable; cap-sd-highspeed; status = "disabled"; -- cgit v1.1 From 77e2d7e27e9842a1141a624bfbb53ebce1c9e3e1 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sat, 9 Nov 2013 13:23:55 +0100 Subject: ARM: shmobile: Use interrupt macros in board DT files Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a73a4-ape6evm.dts | 3 ++- arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts | 3 ++- arch/arm/boot/dts/r8a7778-bockw-reference.dts | 3 ++- arch/arm/boot/dts/r8a7779-marzen-reference.dts | 3 ++- arch/arm/boot/dts/sh73a0-kzm9g-reference.dts | 3 ++- 5 files changed, 10 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts index 7db8d79..e84d1a7 100644 --- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts +++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts @@ -10,6 +10,7 @@ /dts-v1/; #include "r8a73a4.dtsi" +#include / { model = "APE6EVM"; @@ -40,7 +41,7 @@ compatible = "smsc,lan9118", "smsc,lan9115"; reg = <0x08000000 0x1000>; interrupt-parent = <&irqc1>; - interrupts = <8 0x4>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; phy-mode = "mii"; reg-io-width = <4>; smsc,irq-active-high; diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts index c7c5bcb..aef425f 100644 --- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts @@ -11,6 +11,7 @@ /dts-v1/; #include "r8a7740.dtsi" #include +#include #include / { @@ -94,7 +95,7 @@ compatible = "sitronix,st1232"; reg = <0x55>; interrupt-parent = <&irqpin1>; - interrupts = <2 0>; /* IRQ10: hwirq 2 on irqpin1 */ + interrupts = <2 IRQ_TYPE_NONE>; /* IRQ10: hwirq 2 on irqpin1 */ pinctrl-0 = <&st1232_pins>; pinctrl-names = "default"; gpios = <&pfc 166 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/r8a7778-bockw-reference.dts b/arch/arm/boot/dts/r8a7778-bockw-reference.dts index be9b753..2000cf8 100644 --- a/arch/arm/boot/dts/r8a7778-bockw-reference.dts +++ b/arch/arm/boot/dts/r8a7778-bockw-reference.dts @@ -16,6 +16,7 @@ /dts-v1/; #include "r8a7778.dtsi" +#include / { model = "bockw"; @@ -45,7 +46,7 @@ phy-mode = "mii"; interrupt-parent = <&irqpin>; - interrupts = <0 0>; /* IRQ0: hwirq 0 on irqpin */ + interrupts = <0 IRQ_TYPE_NONE>; /* IRQ0: hwirq 0 on irqpin */ reg-io-width = <4>; vddvario-supply = <&fixedregulator3v3>; vdd33a-supply = <&fixedregulator3v3>; diff --git a/arch/arm/boot/dts/r8a7779-marzen-reference.dts b/arch/arm/boot/dts/r8a7779-marzen-reference.dts index 08b9ee37..0f5c614 100644 --- a/arch/arm/boot/dts/r8a7779-marzen-reference.dts +++ b/arch/arm/boot/dts/r8a7779-marzen-reference.dts @@ -12,6 +12,7 @@ /dts-v1/; #include "r8a7779.dtsi" #include +#include / { model = "marzen"; @@ -43,7 +44,7 @@ phy-mode = "mii"; interrupt-parent = <&irqpin0>; - interrupts = <1 0>; /* IRQ1: hwirq 1 on irqpin0 */ + interrupts = <1 IRQ_TYPE_NONE>; /* IRQ1: hwirq 1 on irqpin0 */ reg-io-width = <4>; vddvario-supply = <&fixedregulator3v3>; vdd33a-supply = <&fixedregulator3v3>; diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts index d5a6d74..605f6c6 100644 --- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts +++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts @@ -14,6 +14,7 @@ /dts-v1/; #include "sh73a0.dtsi" #include +#include / { model = "KZM-A9-GT"; @@ -82,7 +83,7 @@ reg = <0x10000000 0x100>; phy-mode = "mii"; interrupt-parent = <&irqpin0>; - interrupts = <3 0>; /* active low */ + interrupts = <3 IRQ_TYPE_NONE>; /* active low */ reg-io-width = <4>; smsc,irq-push-pull; smsc,save-mac-address; -- cgit v1.1 From e60038eda492460c46833f4a54bebd256018a912 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sat, 9 Nov 2013 13:23:56 +0100 Subject: ARM: shmobile: marzen-reference: Use falling edge IRQ for LAN9221 The device is configured to generate an active-low interrupt signal that is automatically deasserted without requiring any action from the host. Use falling edge trigger as that is the configuration currently used on the board. Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7779-marzen-reference.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7779-marzen-reference.dts b/arch/arm/boot/dts/r8a7779-marzen-reference.dts index 0f5c614..13fa8be 100644 --- a/arch/arm/boot/dts/r8a7779-marzen-reference.dts +++ b/arch/arm/boot/dts/r8a7779-marzen-reference.dts @@ -44,7 +44,7 @@ phy-mode = "mii"; interrupt-parent = <&irqpin0>; - interrupts = <1 IRQ_TYPE_NONE>; /* IRQ1: hwirq 1 on irqpin0 */ + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; reg-io-width = <4>; vddvario-supply = <&fixedregulator3v3>; vdd33a-supply = <&fixedregulator3v3>; -- cgit v1.1 From 08281424f1ca5680e4a17656f3d9b978103779eb Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sat, 9 Nov 2013 13:23:57 +0100 Subject: ARM: shmobile: bockw-reference: Use falling edge IRQ for LAN9221 The device is configured to generate an active-low interrupt signal that is automatically deasserted without requiring any action from the host. Configure the IRQ to trigger on falling edge. Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7778-bockw-reference.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7778-bockw-reference.dts b/arch/arm/boot/dts/r8a7778-bockw-reference.dts index 2000cf8..bb62c7a 100644 --- a/arch/arm/boot/dts/r8a7778-bockw-reference.dts +++ b/arch/arm/boot/dts/r8a7778-bockw-reference.dts @@ -46,7 +46,7 @@ phy-mode = "mii"; interrupt-parent = <&irqpin>; - interrupts = <0 IRQ_TYPE_NONE>; /* IRQ0: hwirq 0 on irqpin */ + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; reg-io-width = <4>; vddvario-supply = <&fixedregulator3v3>; vdd33a-supply = <&fixedregulator3v3>; -- cgit v1.1 From 72e14c051a920d9c30d6cab2aecd1699a070aebe Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sat, 9 Nov 2013 13:23:58 +0100 Subject: ARM: shmobile: kzm9g-reference: Use falling edge IRQ for LAN9221 The device is configured to generate an active-low interrupt signal that is automatically deasserted without requiring any action from the host. Configure the IRQ to trigger on falling edge. Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/sh73a0-kzm9g-reference.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts index 605f6c6..12fdfaa 100644 --- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts +++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts @@ -83,7 +83,7 @@ reg = <0x10000000 0x100>; phy-mode = "mii"; interrupt-parent = <&irqpin0>; - interrupts = <3 IRQ_TYPE_NONE>; /* active low */ + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; reg-io-width = <4>; smsc,irq-push-pull; smsc,save-mac-address; -- cgit v1.1 From 72e7db878b8469261d01a3dfcece8ab99ffc9cb6 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Tue, 19 Nov 2013 19:17:41 -0800 Subject: ARM: shmobile: marzen: remove SDHI0 WP pin setting from DTS WP pin is not implemented on Marzen Acked-by: Laurent Pinchart Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7779-marzen-reference.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7779-marzen-reference.dts b/arch/arm/boot/dts/r8a7779-marzen-reference.dts index 13fa8be..918085c 100644 --- a/arch/arm/boot/dts/r8a7779-marzen-reference.dts +++ b/arch/arm/boot/dts/r8a7779-marzen-reference.dts @@ -94,8 +94,7 @@ }; sdhi0_pins: sd0 { - renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", - "sdhi0_wp"; + renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd"; renesas,function = "sdhi0"; }; }; -- cgit v1.1 From 9e5a68d2b9aba2c65112986ece1334bf72711117 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Tue, 19 Nov 2013 19:17:55 -0800 Subject: ARM: shmobile: marzen: remove SDHI0 WP pin setting WP pin is not implemented on Marzen Acked-by: Laurent Pinchart Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/board-marzen.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c index da1352f..7e0395e1 100644 --- a/arch/arm/mach-shmobile/board-marzen.c +++ b/arch/arm/mach-shmobile/board-marzen.c @@ -326,8 +326,6 @@ static const struct pinctrl_map marzen_pinctrl_map[] = { "sdhi0_ctrl", "sdhi0"), PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779", "sdhi0_cd", "sdhi0"), - PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779", - "sdhi0_wp", "sdhi0"), /* SMSC */ PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779", "intc_irq1_b", "intc"), -- cgit v1.1 From e8a8b8a3cd6e09209a9c253a22673836ef794f58 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Tue, 19 Nov 2013 19:18:09 -0800 Subject: ARM: shmobile: sh73a0: fixup sdhi compatible name sh73a0 != r8a7740 Acked-by: Laurent Pinchart Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/sh73a0.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index aef8a61..29d2ee6 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -203,7 +203,7 @@ }; sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a7740"; + compatible = "renesas,sdhi-sh73a0"; reg = <0xee100000 0x100>; interrupt-parent = <&gic>; interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH @@ -215,7 +215,7 @@ /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */ sdhi1: sd@ee120000 { - compatible = "renesas,sdhi-r8a7740"; + compatible = "renesas,sdhi-sh73a0"; reg = <0xee120000 0x100>; interrupt-parent = <&gic>; interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH @@ -226,7 +226,7 @@ }; sdhi2: sd@ee140000 { - compatible = "renesas,sdhi-r8a7740"; + compatible = "renesas,sdhi-sh73a0"; reg = <0xee140000 0x100>; interrupt-parent = <&gic>; interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH -- cgit v1.1 From 26041b06107fbf4618422618630f154f8d1a7d64 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 20 Nov 2013 13:18:05 +0900 Subject: ARM: shmobile: Use r8a7791 suffix for IRQC compat string Add "renesas,irqc-r8a7791" to the compatible string for IRQC in case of r8a7791. This makes the IRQC follow the same style as the other devices and also makes it more future proof. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 86d5d3a..d85254c 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -154,7 +154,7 @@ }; irqc0: interrupt-controller@e61c0000 { - compatible = "renesas,irqc"; + compatible = "renesas,irqc-r8a7791", "renesas,irqc"; #interrupt-cells = <2>; interrupt-controller; reg = <0 0xe61c0000 0 0x200>; -- cgit v1.1 From b91a89cf8d9880d1d82c7f9f4c1a448bb680dc2c Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 20 Nov 2013 16:36:59 +0900 Subject: ARM: shmobile: Configure r8a7791 PFC on Koelsch via DTS Configure the "D" set of data signals for SCIF0 and SCIF1 on the Koelsch board to setup pinctrl serial console bits. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791-koelsch-reference.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7791-koelsch-reference.dts b/arch/arm/boot/dts/r8a7791-koelsch-reference.dts index 1a0f082..8e7e917 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch-reference.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch-reference.dts @@ -30,3 +30,18 @@ #size-cells = <1>; }; }; + +&pfc { + pinctrl-0 = <&scif0_pins &scif1_pins>; + pinctrl-names = "default"; + + scif0_pins: serial0 { + renesas,groups = "scif0_data_d"; + renesas,function = "scif0"; + }; + + scif1_pins: serial1 { + renesas,groups = "scif1_data_d"; + renesas,function = "scif1"; + }; +}; -- cgit v1.1 From 03e2f56b8f68594ccae4b219a2693c938a04c51e Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 20 Nov 2013 16:59:30 +0900 Subject: ARM: shmobile: Add r8a7790 thermal device node to DTS Hook up the r8a7790 thermal sensor to the DTS. Signed-off-by: Magnus Damm Acked-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 3800952..f844b63 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -162,6 +162,13 @@ interrupt-controller; }; + thermal@e61f0000 { + compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal"; + reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; + interrupt-parent = <&gic>; + interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; + }; + timer { compatible = "arm,armv7-timer"; interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, -- cgit v1.1 From d103f4d3152b187b22fd6010370fe1d16419a334 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 20 Nov 2013 16:59:48 +0900 Subject: ARM: shmobile: Add r8a7791 thermal device node to DTS Hook up the r8a7791 thermal sensor to the DTS. Signed-off-by: Magnus Damm Acked-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index d85254c..e36b3652 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -145,6 +145,13 @@ interrupt-controller; }; + thermal@e61f0000 { + compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal"; + reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; + interrupt-parent = <&gic>; + interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; + }; + timer { compatible = "arm,armv7-timer"; interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, -- cgit v1.1 From 063e85607ddf26e5ede36b7454eddc8e87544540 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 20 Nov 2013 09:05:53 +0900 Subject: ARM: shmobile: Use r8a7790 suffix for MMCIF compat string Add "renesas,mmcif-r8a7790" to the compatible string for MMCIF in case of r8a7790. This makes the MMCIF follow the same style as the other devices and also makes it more future proof. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index f844b63..fb9225f 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -230,7 +230,7 @@ }; mmcif0: mmcif@ee200000 { - compatible = "renesas,sh-mmcif"; + compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; reg = <0 0xee200000 0 0x80>; interrupt-parent = <&gic>; interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; @@ -239,7 +239,7 @@ }; mmcif1: mmc@ee220000 { - compatible = "renesas,sh-mmcif"; + compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; reg = <0 0xee220000 0 0x80>; interrupt-parent = <&gic>; interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>; -- cgit v1.1 From 220fc352163de3b93e13d5a2e27d9eefd47bae84 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 20 Nov 2013 09:07:40 +0900 Subject: ARM: shmobile: Use r8a7790 suffix for IRQC compat string Add "renesas,irqc-r8a7790" to the compatible string for IRQC in case of r8a7790. This makes the IRQC follow the same style as the other devices and also makes it more future proof. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index fb9225f..0e4d5b5 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -178,7 +178,7 @@ }; irqc0: interrupt-controller@e61c0000 { - compatible = "renesas,irqc"; + compatible = "renesas,irqc-r8a7790", "renesas,irqc"; #interrupt-cells = <2>; interrupt-controller; reg = <0 0xe61c0000 0 0x200>; -- cgit v1.1 From b69e4435e34df68d54e204b37d6bb256606fef5d Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 19 Nov 2013 13:59:49 +0100 Subject: ARM: shmobile: armadillo-reference: Use low level IRQ for ST1231 The device is configured to generate an active-low interrupt signal that needs to be acknowledged by the host. Configure the IRQ to trigger on low level. Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts index aef425f..7b80f19 100644 --- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts @@ -95,7 +95,7 @@ compatible = "sitronix,st1232"; reg = <0x55>; interrupt-parent = <&irqpin1>; - interrupts = <2 IRQ_TYPE_NONE>; /* IRQ10: hwirq 2 on irqpin1 */ + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; pinctrl-0 = <&st1232_pins>; pinctrl-names = "default"; gpios = <&pfc 166 GPIO_ACTIVE_LOW>; -- cgit v1.1 From cef20af093fc018009ed7f7fde38f9fb8b445e6b Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Thu, 14 Nov 2013 08:03:45 +0900 Subject: ARM: shmobile: Enable DSW2 with gpio-keys on KZM9D Use the gpio-keys driver to support the 4 pins on the dip switch DSW2 which is mounted on the KZM9D board. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/emev2-kzm9d.dts | 39 ++++++++++++++++++++++++++++++++++++++- arch/arm/boot/dts/emev2.dtsi | 2 +- 2 files changed, 39 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts index 861aa7d..baaa66c 100644 --- a/arch/arm/boot/dts/emev2-kzm9d.dts +++ b/arch/arm/boot/dts/emev2-kzm9d.dts @@ -9,7 +9,9 @@ */ /dts-v1/; -/include/ "emev2.dtsi" +#include "emev2.dtsi" +#include +#include / { model = "EMEV2 KZM9D Board"; @@ -54,4 +56,39 @@ vddvario-supply = <®_1p8v>; vdd33a-supply = <®_3p3v>; }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + button@1 { + debounce_interval = <50>; + wakeup = <1>; + label = "DSW2-1"; + linux,code = ; + gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + }; + button@2 { + debounce_interval = <50>; + wakeup = <1>; + label = "DSW2-2"; + linux,code = ; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; + }; + button@3 { + debounce_interval = <50>; + wakeup = <1>; + label = "DSW2-3"; + linux,code = ; + gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; + }; + button@4 { + debounce_interval = <50>; + wakeup = <1>; + label = "DSW2-4"; + linux,code = ; + gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; + }; + }; }; diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi index df1d4cd..256c2f8 100644 --- a/arch/arm/boot/dts/emev2.dtsi +++ b/arch/arm/boot/dts/emev2.dtsi @@ -8,7 +8,7 @@ * kind, whether express or implied. */ -/include/ "skeleton.dtsi" +#include "skeleton.dtsi" / { compatible = "renesas,emev2"; -- cgit v1.1 From 614a198d45e523f6066f1c22b9c10e4067f2c44a Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Thu, 21 Nov 2013 09:44:04 +0900 Subject: ARM: shmobile: Koelsch DT reference GPIO LED support Add led6, led7 and led8 to the Koelsch DT reference board support. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791-koelsch-reference.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7791-koelsch-reference.dts b/arch/arm/boot/dts/r8a7791-koelsch-reference.dts index 8e7e917..1919273 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch-reference.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch-reference.dts @@ -11,6 +11,7 @@ /dts-v1/; #include "r8a7791.dtsi" +#include / { model = "Koelsch"; @@ -29,6 +30,19 @@ #address-cells = <1>; #size-cells = <1>; }; + + leds { + compatible = "gpio-leds"; + led6 { + gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; + }; + led7 { + gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; + }; + led8 { + gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; + }; + }; }; &pfc { -- cgit v1.1 From a40d9ad3dd8dbb5d44843156157d83c4172e11f9 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 26 Nov 2013 02:21:18 +0100 Subject: ARM: shmobile: kzm9g-reference: Add PCF8575 GPIO extender to DT Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/sh73a0-kzm9g-reference.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts index 12fdfaa..d58877d 100644 --- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts +++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts @@ -186,6 +186,17 @@ pinctrl-0 = <&i2c3_pins>; pinctrl-names = "default"; status = "okay"; + + pcf8575: gpio@20 { + compatible = "nxp,pcf8575"; + reg = <0x20>; + interrupt-parent = <&irqpin2>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; &mmcif { -- cgit v1.1 From 5ec5f73463611514fe46b2167e471b17626007f9 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 26 Nov 2013 02:21:19 +0100 Subject: ARM: shmobile: kzm9g-reference: Add GPIO keys to DT Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/sh73a0-kzm9g-reference.dts | 46 ++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts index d58877d..5bb593d 100644 --- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts +++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts @@ -106,6 +106,52 @@ gpios = <&pfc 23 GPIO_ACTIVE_LOW>; }; }; + + gpio-keys { + compatible = "gpio-keys"; + + back-key { + gpios = <&pcf8575 8 GPIO_ACTIVE_LOW>; + linux,code = <158>; + label = "SW3"; + }; + + right-key { + gpios = <&pcf8575 9 GPIO_ACTIVE_LOW>; + linux,code = <106>; + label = "SW2-R"; + }; + + left-key { + gpios = <&pcf8575 10 GPIO_ACTIVE_LOW>; + linux,code = <105>; + label = "SW2-L"; + }; + + enter-key { + gpios = <&pcf8575 11 GPIO_ACTIVE_LOW>; + linux,code = <28>; + label = "SW2-P"; + }; + + up-key { + gpios = <&pcf8575 12 GPIO_ACTIVE_LOW>; + linux,code = <103>; + label = "SW2-U"; + }; + + down-key { + gpios = <&pcf8575 13 GPIO_ACTIVE_LOW>; + linux,code = <108>; + label = "SW2-D"; + }; + + home-key { + gpios = <&pcf8575 14 GPIO_ACTIVE_LOW>; + linux,code = <102>; + label = "SW1"; + }; + }; }; &i2c0 { -- cgit v1.1 From 9701f442139bd21c4db5b6354611b3d793431a95 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Thu, 31 Oct 2013 12:18:41 +0900 Subject: ARM: shmobile: Include all 2 GiB of memory on APE6EVM DT Ref Add 1GiB of DRAM at 0x2_0000_0000 to support the full 2GiB of APE6EVM system memory also in case of DT reference. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts index 338f0cb..70b1fff 100644 --- a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts +++ b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts @@ -25,6 +25,11 @@ reg = <0 0x40000000 0 0x40000000>; }; + memory@200000000 { + device_type = "memory"; + reg = <2 0x00000000 0 0x40000000>; + }; + vcc_mmc0: regulator@0 { compatible = "regulator-fixed"; regulator-name = "MMC0 Vcc"; -- cgit v1.1 From 8353f09f579631d095292bd838114833dbe1298f Mon Sep 17 00:00:00 2001 From: Takashi Yoshii Date: Thu, 31 Oct 2013 12:15:49 +0900 Subject: ARM: shmobile: Include all 2 GiB of memory on APE6EVM Add 1GiB of DRAM at 0x2_0000_0000 to support the full 2GiB of APE6EVM system memory. Signed-off-by: Takashi Yoshii Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a73a4-ape6evm.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts index e84d1a7..ce085fa 100644 --- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts +++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts @@ -25,6 +25,11 @@ reg = <0 0x40000000 0 0x40000000>; }; + memory@200000000 { + device_type = "memory"; + reg = <2 0x00000000 0 0x40000000>; + }; + ape6evm_fixed_3v3: fixedregulator@0 { compatible = "regulator-fixed"; regulator-name = "3V3"; -- cgit v1.1 From 62bc32a2573c421926a292e13b71ad9cc3ebf6e4 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Thu, 31 Oct 2013 12:21:41 +0900 Subject: ARM: shmobile: Include all 4 GiB of memory on Lager Add 2GiB of DRAM at 0x1_8000_0000 to support the full 4GiB of Lager system memory. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790-lager.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 8799dfb..10e6a08 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -24,6 +24,11 @@ reg = <0 0x40000000 0 0x80000000>; }; + memory@180000000 { + device_type = "memory"; + reg = <1 0x80000000 0 0x80000000>; + }; + lbsc { #address-cells = <1>; #size-cells = <1>; -- cgit v1.1 From fb8d2ee32e899e53de76b66da5cc3c7149d4fc04 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Thu, 31 Oct 2013 12:24:36 +0900 Subject: ARM: shmobile: Include all 4 GiB of memory on Lager DT Ref Add 2GiB of DRAM at 0x1_8000_0000 to support the full 4GiB of Lager system memory in case of DT Reference. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790-lager-reference.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7790-lager-reference.dts b/arch/arm/boot/dts/r8a7790-lager-reference.dts index cce7dbf..dfedc0e 100644 --- a/arch/arm/boot/dts/r8a7790-lager-reference.dts +++ b/arch/arm/boot/dts/r8a7790-lager-reference.dts @@ -25,6 +25,11 @@ reg = <0 0x40000000 0 0x80000000>; }; + memory@180000000 { + device_type = "memory"; + reg = <1 0x80000000 0 0x80000000>; + }; + lbsc { #address-cells = <1>; #size-cells = <1>; -- cgit v1.1 From 89fbba1210a171f134b72c4d3ccf376265c6ff3f Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Thu, 21 Nov 2013 14:22:00 +0900 Subject: ARM: shmobile: Fix r8a7791 GPIO resources in DTS The r8a7791 GPIO resources are currently incorrect. Fix that by making them match the English r8a7791 v0.31 data sheet. Tested with GPIO LED using Koelsch DT reference. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index e36b3652..a349aff 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -49,9 +49,9 @@ interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; - gpio0: gpio@ffc40000 { + gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; - reg = <0 0xffc40000 0 0x50>; + reg = <0 0xe6050000 0 0x50>; interrupt-parent = <&gic>; interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -61,9 +61,9 @@ interrupt-controller; }; - gpio1: gpio@ffc41000 { + gpio1: gpio@e6051000 { compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; - reg = <0 0xffc41000 0 0x50>; + reg = <0 0xe6051000 0 0x50>; interrupt-parent = <&gic>; interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -73,9 +73,9 @@ interrupt-controller; }; - gpio2: gpio@ffc42000 { + gpio2: gpio@e6052000 { compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; - reg = <0 0xffc42000 0 0x50>; + reg = <0 0xe6052000 0 0x50>; interrupt-parent = <&gic>; interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -85,9 +85,9 @@ interrupt-controller; }; - gpio3: gpio@ffc43000 { + gpio3: gpio@e6053000 { compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; - reg = <0 0xffc43000 0 0x50>; + reg = <0 0xe6053000 0 0x50>; interrupt-parent = <&gic>; interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -97,9 +97,9 @@ interrupt-controller; }; - gpio4: gpio@ffc44000 { + gpio4: gpio@e6054000 { compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; - reg = <0 0xffc44000 0 0x50>; + reg = <0 0xe6054000 0 0x50>; interrupt-parent = <&gic>; interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -109,9 +109,9 @@ interrupt-controller; }; - gpio5: gpio@ffc45000 { + gpio5: gpio@e6055000 { compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; - reg = <0 0xffc45000 0 0x50>; + reg = <0 0xe6055000 0 0x50>; interrupt-parent = <&gic>; interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -121,9 +121,9 @@ interrupt-controller; }; - gpio6: gpio@ffc45400 { + gpio6: gpio@e6055400 { compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; - reg = <0 0xffc45400 0 0x50>; + reg = <0 0xe6055400 0 0x50>; interrupt-parent = <&gic>; interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; @@ -133,9 +133,9 @@ interrupt-controller; }; - gpio7: gpio@ffc45800 { + gpio7: gpio@e6055800 { compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; - reg = <0 0xffc45800 0 0x50>; + reg = <0 0xe6055800 0 0x50>; interrupt-parent = <&gic>; interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; -- cgit v1.1 From d6dd1313f74e2035e77c36686e7348a1bcd1c102 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 28 Nov 2013 17:22:13 +0100 Subject: ARM: shmobile: Use interrupt macros in r8a73a4 and r8a7778 DT files Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a73a4.dtsi | 50 +++++++++++++++++++++--------------------- arch/arm/boot/dts/r8a7778.dtsi | 6 ++--- 2 files changed, 28 insertions(+), 28 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index b4a6c3b..6b7ce89 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -137,27 +137,27 @@ compatible = "renesas,shdma-r8a73a4"; reg = <0 0xe6700020 0 0x89e0>; interrupt-parent = <&gic>; - interrupts = <0 220 4 - 0 200 4 - 0 201 4 - 0 202 4 - 0 203 4 - 0 204 4 - 0 205 4 - 0 206 4 - 0 207 4 - 0 208 4 - 0 209 4 - 0 210 4 - 0 211 4 - 0 212 4 - 0 213 4 - 0 214 4 - 0 215 4 - 0 216 4 - 0 217 4 - 0 218 4 - 0 219 4>; + interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH + 0 200 IRQ_TYPE_LEVEL_HIGH + 0 201 IRQ_TYPE_LEVEL_HIGH + 0 202 IRQ_TYPE_LEVEL_HIGH + 0 203 IRQ_TYPE_LEVEL_HIGH + 0 204 IRQ_TYPE_LEVEL_HIGH + 0 205 IRQ_TYPE_LEVEL_HIGH + 0 206 IRQ_TYPE_LEVEL_HIGH + 0 207 IRQ_TYPE_LEVEL_HIGH + 0 208 IRQ_TYPE_LEVEL_HIGH + 0 209 IRQ_TYPE_LEVEL_HIGH + 0 210 IRQ_TYPE_LEVEL_HIGH + 0 211 IRQ_TYPE_LEVEL_HIGH + 0 212 IRQ_TYPE_LEVEL_HIGH + 0 213 IRQ_TYPE_LEVEL_HIGH + 0 214 IRQ_TYPE_LEVEL_HIGH + 0 215 IRQ_TYPE_LEVEL_HIGH + 0 216 IRQ_TYPE_LEVEL_HIGH + 0 217 IRQ_TYPE_LEVEL_HIGH + 0 218 IRQ_TYPE_LEVEL_HIGH + 0 219 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "error", "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7", @@ -181,7 +181,7 @@ compatible = "renesas,rmobile-iic"; reg = <0 0xe6500000 0 0x428>; interrupt-parent = <&gic>; - interrupts = <0 174 0x4>; + interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -191,7 +191,7 @@ compatible = "renesas,rmobile-iic"; reg = <0 0xe6510000 0 0x428>; interrupt-parent = <&gic>; - interrupts = <0 175 0x4>; + interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -201,7 +201,7 @@ compatible = "renesas,rmobile-iic"; reg = <0 0xe6520000 0 0x428>; interrupt-parent = <&gic>; - interrupts = <0 176 0x4>; + interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -211,7 +211,7 @@ compatible = "renesas,rmobile-iic"; reg = <0 0xe6530000 0 0x428>; interrupt-parent = <&gic>; - interrupts = <0 177 0x4>; + interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index 3314e0a..b530df6 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -247,7 +247,7 @@ compatible = "renesas,hspi"; reg = <0xfffc7000 0x18>; interrupt-controller = <&gic>; - interrupts = <0 63 4>; + interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -255,7 +255,7 @@ compatible = "renesas,hspi"; reg = <0xfffc8000 0x18>; interrupt-controller = <&gic>; - interrupts = <0 84 4>; + interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -263,7 +263,7 @@ compatible = "renesas,hspi"; reg = <0xfffc6000 0x18>; interrupt-controller = <&gic>; - interrupts = <0 85 4>; + interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; }; -- cgit v1.1 From 3dc76086fa0a8def96f331785cceb6e84e3c34de Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 28 Nov 2013 17:37:50 +0100 Subject: ARM: shmobile: emev2: Use interrupt macros in DT files Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/emev2-kzm9d.dts | 3 ++- arch/arm/boot/dts/emev2.dtsi | 30 ++++++++++++++++++------------ 2 files changed, 20 insertions(+), 13 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts index baaa66c..50ccd15 100644 --- a/arch/arm/boot/dts/emev2-kzm9d.dts +++ b/arch/arm/boot/dts/emev2-kzm9d.dts @@ -12,6 +12,7 @@ #include "emev2.dtsi" #include #include +#include / { model = "EMEV2 KZM9D Board"; @@ -49,7 +50,7 @@ reg = <0x20000000 0x10000>; phy-mode = "mii"; interrupt-parent = <&gpio0>; - interrupts = <1 1>; /* active high */ + interrupts = <1 IRQ_TYPE_EDGE_RISING>; reg-io-width = <4>; smsc,irq-active-high; smsc,irq-push-pull; diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi index 256c2f8..8467e4c 100644 --- a/arch/arm/boot/dts/emev2.dtsi +++ b/arch/arm/boot/dts/emev2.dtsi @@ -9,6 +9,7 @@ */ #include "skeleton.dtsi" +#include / { compatible = "renesas,emev2"; @@ -48,8 +49,8 @@ pmu { compatible = "arm,cortex-a9-pmu"; - interrupts = <0 120 4>, - <0 121 4>; + interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>, + <0 121 IRQ_TYPE_LEVEL_HIGH>; }; smu@e0110000 { @@ -129,7 +130,7 @@ sti@e0180000 { compatible = "renesas,em-sti"; reg = <0xe0180000 0x54>; - interrupts = <0 125 0>; + interrupts = <0 125 IRQ_TYPE_NONE>; clocks = <&sti_sclk>; clock-names = "sclk"; }; @@ -137,7 +138,7 @@ uart@e1020000 { compatible = "renesas,em-uart"; reg = <0xe1020000 0x38>; - interrupts = <0 8 0>; + interrupts = <0 8 IRQ_TYPE_NONE>; clocks = <&usia_u0_sclk>; clock-names = "sclk"; }; @@ -145,7 +146,7 @@ uart@e1030000 { compatible = "renesas,em-uart"; reg = <0xe1030000 0x38>; - interrupts = <0 9 0>; + interrupts = <0 9 IRQ_TYPE_NONE>; clocks = <&usib_u1_sclk>; clock-names = "sclk"; }; @@ -153,7 +154,7 @@ uart@e1040000 { compatible = "renesas,em-uart"; reg = <0xe1040000 0x38>; - interrupts = <0 10 0>; + interrupts = <0 10 IRQ_TYPE_NONE>; clocks = <&usib_u2_sclk>; clock-names = "sclk"; }; @@ -161,7 +162,7 @@ uart@e1050000 { compatible = "renesas,em-uart"; reg = <0xe1050000 0x38>; - interrupts = <0 11 0>; + interrupts = <0 11 IRQ_TYPE_NONE>; clocks = <&usib_u3_sclk>; clock-names = "sclk"; }; @@ -169,7 +170,8 @@ gpio0: gpio@e0050000 { compatible = "renesas,em-gio"; reg = <0xe0050000 0x2c>, <0xe0050040 0x20>; - interrupts = <0 67 0>, <0 68 0>; + interrupts = <0 67 IRQ_TYPE_NONE>, + <0 68 IRQ_TYPE_NONE>; gpio-controller; #gpio-cells = <2>; ngpios = <32>; @@ -179,7 +181,8 @@ gpio1: gpio@e0050080 { compatible = "renesas,em-gio"; reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>; - interrupts = <0 69 0>, <0 70 0>; + interrupts = <0 69 IRQ_TYPE_NONE>, + <0 70 IRQ_TYPE_NONE>; gpio-controller; #gpio-cells = <2>; ngpios = <32>; @@ -189,7 +192,8 @@ gpio2: gpio@e0050100 { compatible = "renesas,em-gio"; reg = <0xe0050100 0x2c>, <0xe0050140 0x20>; - interrupts = <0 71 0>, <0 72 0>; + interrupts = <0 71 IRQ_TYPE_NONE>, + <0 72 IRQ_TYPE_NONE>; gpio-controller; #gpio-cells = <2>; ngpios = <32>; @@ -199,7 +203,8 @@ gpio3: gpio@e0050180 { compatible = "renesas,em-gio"; reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>; - interrupts = <0 73 0>, <0 74 0>; + interrupts = <0 73 IRQ_TYPE_NONE>, + <0 74 IRQ_TYPE_NONE>; gpio-controller; #gpio-cells = <2>; ngpios = <32>; @@ -209,7 +214,8 @@ gpio4: gpio@e0050200 { compatible = "renesas,em-gio"; reg = <0xe0050200 0x2c>, <0xe0050240 0x20>; - interrupts = <0 75 0>, <0 76 0>; + interrupts = <0 75 IRQ_TYPE_NONE>, + <0 76 IRQ_TYPE_NONE>; gpio-controller; #gpio-cells = <2>; ngpios = <31>; -- cgit v1.1 From e05ab0bb14723d419b43341d413e4418000f58f9 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 28 Nov 2013 17:37:51 +0100 Subject: ARM: shmobile: emev2: Setup internal peripheral interrupts as level high Interrupts generated by SoC internal devices are currently marked as IRQ_TYPE_NONE. As they're level-triggered and active-high, mark them as such. Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/emev2.dtsi | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi index 8467e4c..e37985f 100644 --- a/arch/arm/boot/dts/emev2.dtsi +++ b/arch/arm/boot/dts/emev2.dtsi @@ -130,7 +130,7 @@ sti@e0180000 { compatible = "renesas,em-sti"; reg = <0xe0180000 0x54>; - interrupts = <0 125 IRQ_TYPE_NONE>; + interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; clocks = <&sti_sclk>; clock-names = "sclk"; }; @@ -138,7 +138,7 @@ uart@e1020000 { compatible = "renesas,em-uart"; reg = <0xe1020000 0x38>; - interrupts = <0 8 IRQ_TYPE_NONE>; + interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; clocks = <&usia_u0_sclk>; clock-names = "sclk"; }; @@ -146,7 +146,7 @@ uart@e1030000 { compatible = "renesas,em-uart"; reg = <0xe1030000 0x38>; - interrupts = <0 9 IRQ_TYPE_NONE>; + interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; clocks = <&usib_u1_sclk>; clock-names = "sclk"; }; @@ -154,7 +154,7 @@ uart@e1040000 { compatible = "renesas,em-uart"; reg = <0xe1040000 0x38>; - interrupts = <0 10 IRQ_TYPE_NONE>; + interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; clocks = <&usib_u2_sclk>; clock-names = "sclk"; }; @@ -162,7 +162,7 @@ uart@e1050000 { compatible = "renesas,em-uart"; reg = <0xe1050000 0x38>; - interrupts = <0 11 IRQ_TYPE_NONE>; + interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; clocks = <&usib_u3_sclk>; clock-names = "sclk"; }; @@ -170,8 +170,8 @@ gpio0: gpio@e0050000 { compatible = "renesas,em-gio"; reg = <0xe0050000 0x2c>, <0xe0050040 0x20>; - interrupts = <0 67 IRQ_TYPE_NONE>, - <0 68 IRQ_TYPE_NONE>; + interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>, + <0 68 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; ngpios = <32>; @@ -181,8 +181,8 @@ gpio1: gpio@e0050080 { compatible = "renesas,em-gio"; reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>; - interrupts = <0 69 IRQ_TYPE_NONE>, - <0 70 IRQ_TYPE_NONE>; + interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>, + <0 70 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; ngpios = <32>; @@ -192,8 +192,8 @@ gpio2: gpio@e0050100 { compatible = "renesas,em-gio"; reg = <0xe0050100 0x2c>, <0xe0050140 0x20>; - interrupts = <0 71 IRQ_TYPE_NONE>, - <0 72 IRQ_TYPE_NONE>; + interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>, + <0 72 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; ngpios = <32>; @@ -203,8 +203,8 @@ gpio3: gpio@e0050180 { compatible = "renesas,em-gio"; reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>; - interrupts = <0 73 IRQ_TYPE_NONE>, - <0 74 IRQ_TYPE_NONE>; + interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>, + <0 74 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; ngpios = <32>; @@ -214,8 +214,8 @@ gpio4: gpio@e0050200 { compatible = "renesas,em-gio"; reg = <0xe0050200 0x2c>, <0xe0050240 0x20>; - interrupts = <0 75 IRQ_TYPE_NONE>, - <0 76 IRQ_TYPE_NONE>; + interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>, + <0 76 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; ngpios = <31>; -- cgit v1.1 From efcd869b7c5ef0cff5887842afe2c184e509807a Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Tue, 3 Dec 2013 17:28:41 -0800 Subject: ARM: shmobile: r8a7740: add FSI support via DTSI Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7740.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index b1c2ed9..52255bf 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -208,4 +208,13 @@ cap-sdio-irq; status = "disabled"; }; + + sh_fsi2: sound@fe1f0000 { + #sound-dai-cells = <1>; + compatible = "renesas,sh_fsi2"; + reg = <0xfe1f0000 0x400>; + interrupt-parent = <&gic>; + interrupts = <0 9 0x4>; + status = "disabled"; + }; }; -- cgit v1.1 From 6a3549d464bf8dc05ab87eab0f3ed2da0dbc5379 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Tue, 3 Dec 2013 17:28:59 -0800 Subject: ARM: shmobile: armadillo: add FSI support for DTS This patch support FSI-WM8978 with simple audio card Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- .../boot/dts/r8a7740-armadillo800eva-reference.dts | 37 ++++++++++++++++++++++ 1 file changed, 37 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts index 7b80f19..6d6fd3d 100644 --- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts @@ -87,6 +87,24 @@ pinctrl-0 = <&backlight_pins>; pinctrl-names = "default"; }; + + sound { + compatible = "simple-audio-card"; + + simple-audio-card,format = "i2s"; + + simple-audio-card,cpu { + sound-dai = <&sh_fsi2 0>; + bitclock-inversion; + }; + + simple-audio-card,codec { + sound-dai = <&wm8978>; + bitclock-master; + frame-master; + system-clock-frequency = <12288000>; + }; + }; }; &i2c0 { @@ -100,6 +118,12 @@ pinctrl-names = "default"; gpios = <&pfc 166 GPIO_ACTIVE_LOW>; }; + + wm8978: wm8978@1a { + #sound-dai-cells = <0>; + compatible = "wlf,wm8978"; + reg = <0x1a>; + }; }; &pfc { @@ -130,6 +154,12 @@ renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_wp"; renesas,function = "sdhi0"; }; + + fsia_pins: sounda { + renesas,groups = "fsia_sclk_in", "fsia_mclk_out", + "fsia_data_in_1", "fsia_data_out_0"; + renesas,function = "fsia"; + }; }; &tpu { @@ -156,3 +186,10 @@ cd-gpios = <&pfc 167 GPIO_ACTIVE_LOW>; status = "okay"; }; + +&sh_fsi2 { + pinctrl-0 = <&fsia_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; -- cgit v1.1 From 8bb44445b08d1068a0ca5f72159d8e373f810155 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Thu, 28 Nov 2013 08:14:57 +0900 Subject: ARM: shmobile: Use sh73a0 suffix for INTC compat string Add "renesas,intc-irqpin-sh73a0" to the compatible string for the IRQ pins in case of sh73a0 INTC. This makes the INTC irqpin follow the same style as the other devices and also makes it more future proof. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/sh73a0.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index 29d2ee6..241c8cd 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -47,7 +47,7 @@ }; irqpin0: irqpin@e6900000 { - compatible = "renesas,intc-irqpin"; + compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; #interrupt-cells = <2>; interrupt-controller; reg = <0xe6900000 4>, @@ -67,7 +67,7 @@ }; irqpin1: irqpin@e6900004 { - compatible = "renesas,intc-irqpin"; + compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; #interrupt-cells = <2>; interrupt-controller; reg = <0xe6900004 4>, @@ -88,7 +88,7 @@ }; irqpin2: irqpin@e6900008 { - compatible = "renesas,intc-irqpin"; + compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; #interrupt-cells = <2>; interrupt-controller; reg = <0xe6900008 4>, @@ -108,7 +108,7 @@ }; irqpin3: irqpin@e690000c { - compatible = "renesas,intc-irqpin"; + compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; #interrupt-cells = <2>; interrupt-controller; reg = <0xe690000c 4>, -- cgit v1.1 From 96327999805dfb5b6e91e6969311d9a77a0160cd Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Thu, 28 Nov 2013 08:15:04 +0900 Subject: ARM: shmobile: Use r8a7740 suffix for INTC compat string Add "renesas,intc-irqpin-r8a7740" to the compatible string for the IRQ pins in case of r8a7740 INTC. This makes the INTC irqpin follow the same style as the other devices and also makes it more future proof. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7740.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index 52255bf..2782f64 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -41,7 +41,7 @@ /* irqpin0: IRQ0 - IRQ7 */ irqpin0: irqpin@e6900000 { - compatible = "renesas,intc-irqpin"; + compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; #interrupt-cells = <2>; interrupt-controller; reg = <0xe6900000 4>, @@ -62,7 +62,7 @@ /* irqpin1: IRQ8 - IRQ15 */ irqpin1: irqpin@e6900004 { - compatible = "renesas,intc-irqpin"; + compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; #interrupt-cells = <2>; interrupt-controller; reg = <0xe6900004 4>, @@ -83,7 +83,7 @@ /* irqpin2: IRQ16 - IRQ23 */ irqpin2: irqpin@e6900008 { - compatible = "renesas,intc-irqpin"; + compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; #interrupt-cells = <2>; interrupt-controller; reg = <0xe6900008 4>, @@ -104,7 +104,7 @@ /* irqpin3: IRQ24 - IRQ31 */ irqpin3: irqpin@e690000c { - compatible = "renesas,intc-irqpin"; + compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; #interrupt-cells = <2>; interrupt-controller; reg = <0xe690000c 4>, -- cgit v1.1 From d79af224b7a7d4d24c1170960eefb48ccb328eff Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Thu, 28 Nov 2013 08:15:11 +0900 Subject: ARM: shmobile: Use r8a7778 suffix for INTC compat string Add "renesas,intc-irqpin-r8a7778" to the compatible string for the IRQ pins in case of r8a7778 INTC. This makes the INTC irqpin follow the same style as the other devices and also makes it more future proof. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7778.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index b530df6..ddb3bd7 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -43,7 +43,7 @@ /* irqpin: IRQ0 - IRQ3 */ irqpin: irqpin@fe78001c { - compatible = "renesas,intc-irqpin"; + compatible = "renesas,intc-irqpin-r8a7778", "renesas,intc-irqpin"; #interrupt-cells = <2>; interrupt-controller; status = "disabled"; /* default off */ -- cgit v1.1 From 11ef0340a8cdf9db9a5c49298f361258d090fefb Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Thu, 28 Nov 2013 08:15:18 +0900 Subject: ARM: shmobile: Use r8a7779 suffix for INTC compat string Add "renesas,intc-irqpin-r8a7779" to the compatible string for the IRQ pins in case of r8a7779 INTC. This makes the INTC irqpin follow the same style as the other devices and also makes it more future proof. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7779.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index b2b418a..8284715 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -135,7 +135,7 @@ }; irqpin0: irqpin@fe780010 { - compatible = "renesas,intc-irqpin"; + compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin"; #interrupt-cells = <2>; status = "disabled"; interrupt-controller; -- cgit v1.1 From 3c3f6ad350bbeccaba5ab54a267900dcc76b9dd2 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Tue, 26 Nov 2013 16:47:11 +0900 Subject: ARM: shmobile: r8a7779: add HSPI support to DTSI Based on work for the r8a7778 SoC by Kuninori Morimoto. Cc: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7779.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index 8284715..d0561d4 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -42,6 +42,12 @@ }; }; + aliases { + spi0 = &hspi0; + spi1 = &hspi1; + spi2 = &hspi2; + }; + gic: interrupt-controller@f0001000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; @@ -248,4 +254,28 @@ cap-sdio-irq; status = "disabled"; }; + + hspi0: spi@fffc7000 { + compatible = "renesas,hspi"; + reg = <0xfffc7000 0x18>; + interrupt-controller = <&gic>; + interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + hspi1: spi@fffc8000 { + compatible = "renesas,hspi"; + reg = <0xfffc8000 0x18>; + interrupt-controller = <&gic>; + interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + hspi2: spi@fffc6000 { + compatible = "renesas,hspi"; + reg = <0xfffc6000 0x18>; + interrupt-controller = <&gic>; + interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; }; -- cgit v1.1 From 1fd219561a4afc51b5f257692f3581546434db5b Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Tue, 26 Nov 2013 16:47:12 +0900 Subject: ARM: shmobile: marzen: enable HSPI0 in DTS Based on work for the bockw board by Kuninori Morimoto. Cc: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7779-marzen-reference.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7779-marzen-reference.dts b/arch/arm/boot/dts/r8a7779-marzen-reference.dts index 918085c..76f5eef 100644 --- a/arch/arm/boot/dts/r8a7779-marzen-reference.dts +++ b/arch/arm/boot/dts/r8a7779-marzen-reference.dts @@ -97,6 +97,11 @@ renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd"; renesas,function = "sdhi0"; }; + + hspi0_pins: hspi0 { + renesas,groups = "hspi0"; + renesas,function = "hspi0"; + }; }; &sdhi0 { @@ -107,3 +112,9 @@ bus-width = <4>; status = "okay"; }; + +&hspi0 { + pinctrl-0 = <&hspi0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; -- cgit v1.1 From b32313c614268ee1fac37d63eceb33413b2d84c0 Mon Sep 17 00:00:00 2001 From: Josh Wu Date: Wed, 6 Nov 2013 18:01:12 +0800 Subject: ARM: at91: sama5d3/dt: add sama5d36ek dts files Add .dts and .dtsi file to support sama5d36ek board. Also update the the comments for sama5d36 in sama5d3.dtsi. Signed-off-by: Josh Wu Acked-by: Boris BREZILLON Signed-off-by: Nicolas Ferre Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/Makefile | 2 ++ arch/arm/boot/dts/sama5d3.dtsi | 2 +- arch/arm/boot/dts/sama5d36.dtsi | 20 +++++++++++++++ arch/arm/boot/dts/sama5d36ek.dts | 53 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 76 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/sama5d36.dtsi create mode 100644 arch/arm/boot/dts/sama5d36ek.dts (limited to 'arch') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index adcc606..7154de6 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -40,6 +40,8 @@ dtb-$(CONFIG_ARCH_AT91) += sama5d31ek.dtb dtb-$(CONFIG_ARCH_AT91) += sama5d33ek.dtb dtb-$(CONFIG_ARCH_AT91) += sama5d34ek.dtb dtb-$(CONFIG_ARCH_AT91) += sama5d35ek.dtb +dtb-$(CONFIG_ARCH_AT91) += sama5d36ek.dtb + dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm11351-brt.dtb \ diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index de9fece..0b0aade 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -1,6 +1,6 @@ /* * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC - * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35 SoC + * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36 SoC * * Copyright (C) 2013 Atmel, * 2013 Ludovic Desroches diff --git a/arch/arm/boot/dts/sama5d36.dtsi b/arch/arm/boot/dts/sama5d36.dtsi new file mode 100644 index 0000000..6c31c26 --- /dev/null +++ b/arch/arm/boot/dts/sama5d36.dtsi @@ -0,0 +1,20 @@ +/* + * sama5d36.dtsi - Device Tree Include file for SAMA5D36 SoC + * + * Copyright (C) 2013 Atmel, + * 2013 Josh Wu + * + * Licensed under GPLv2 or later. + */ +#include "sama5d3.dtsi" +#include "sama5d3_can.dtsi" +#include "sama5d3_emac.dtsi" +#include "sama5d3_gmac.dtsi" +#include "sama5d3_lcd.dtsi" +#include "sama5d3_mci2.dtsi" +#include "sama5d3_tcb1.dtsi" +#include "sama5d3_uart.dtsi" + +/ { + compatible = "atmel,samad36", "atmel,sama5d3", "atmel,sama5"; +}; diff --git a/arch/arm/boot/dts/sama5d36ek.dts b/arch/arm/boot/dts/sama5d36ek.dts new file mode 100644 index 0000000..59576c6 --- /dev/null +++ b/arch/arm/boot/dts/sama5d36ek.dts @@ -0,0 +1,53 @@ +/* + * sama5d36ek.dts - Device Tree file for SAMA5D36-EK board + * + * Copyright (C) 2013 Atmel, + * 2013 Josh Wu + * + * Licensed under GPLv2 or later. + */ +/dts-v1/; +#include "sama5d36.dtsi" +#include "sama5d3xmb.dtsi" +#include "sama5d3xdm.dtsi" + +/ { + model = "Atmel SAMA5D36-EK"; + compatible = "atmel,sama5d36ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d36", "atmel,sama5d3", "atmel,sama5"; + + ahb { + apb { + spi0: spi@f0004000 { + status = "okay"; + }; + + ssc0: ssc@f0008000 { + status = "okay"; + }; + + can0: can@f000c000 { + status = "okay"; + }; + + i2c0: i2c@f0014000 { + status = "okay"; + }; + + i2c1: i2c@f0018000 { + status = "okay"; + }; + + macb0: ethernet@f0028000 { + status = "okay"; + }; + + macb1: ethernet@f802c000 { + status = "okay"; + }; + }; + }; + + sound { + status = "okay"; + }; +}; -- cgit v1.1 From e7b4a8dfc82fb07d7db48d6e84e36451a7c73c5c Mon Sep 17 00:00:00 2001 From: Mike Dunn Date: Sat, 21 Sep 2013 12:19:34 -0700 Subject: ARM: pxa: add PWM nodes to pxa27x.dtsi This patch adds PWM nodes for each of the four channels present on the pxa270. Signed-off-by: Mike Dunn Signed-off-by: Haojian Zhuang Signed-off-by: Olof Johansson --- arch/arm/boot/dts/pxa27x.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/pxa27x.dtsi b/arch/arm/boot/dts/pxa27x.dtsi index d7c5d72..a705469 100644 --- a/arch/arm/boot/dts/pxa27x.dtsi +++ b/arch/arm/boot/dts/pxa27x.dtsi @@ -10,5 +10,29 @@ marvell,intc-priority; marvell,intc-nr-irqs = <34>; }; + + pwm0: pwm@40b00000 { + compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; + reg = <0x40b00000 0x10>; + #pwm-cells = <1>; + }; + + pwm1: pwm@40b00010 { + compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; + reg = <0x40b00010 0x10>; + #pwm-cells = <1>; + }; + + pwm2: pwm@40c00000 { + compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; + reg = <0x40c00000 0x10>; + #pwm-cells = <1>; + }; + + pwm3: pwm@40c00010 { + compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; + reg = <0x40c00010 0x10>; + #pwm-cells = <1>; + }; }; }; -- cgit v1.1 From 982264c3e0bf52e81a2c2b908a81ab0e9b422f32 Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Wed, 11 Dec 2013 09:29:49 -0800 Subject: ARM: zynq: add gem support The zynq includes a Cadence GEM IP core. This is compatible with the macb driver. Add it to the zynq-7000 DT. Signed-off-by: Steffen Trumtrar Cc: Michal Simek Cc: Josh Cartwright [soren: rebased to current Linus tree, added zc706 + zed support, moved phy-mode property to board level dtses] Signed-off-by: Soren Brinkmann Signed-off-by: Michal Simek --- arch/arm/boot/dts/zynq-7000.dtsi | 18 ++++++++++++++++++ arch/arm/boot/dts/zynq-zc702.dts | 5 +++++ arch/arm/boot/dts/zynq-zc706.dts | 5 +++++ arch/arm/boot/dts/zynq-zed.dts | 5 +++++ 4 files changed, 33 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index e7f73b2..aebc48d 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -65,6 +65,24 @@ interrupts = <0 50 4>; }; + gem0: ethernet@e000b000 { + compatible = "cdns,gem"; + reg = <0xe000b000 0x4000>; + status = "disabled"; + interrupts = <0 22 4>; + clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; + clock-names = "pclk", "hclk", "tx_clk"; + }; + + gem1: ethernet@e000c000 { + compatible = "cdns,gem"; + reg = <0xe000c000 0x4000>; + status = "disabled"; + interrupts = <0 45 4>; + clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; + clock-names = "pclk", "hclk", "tx_clk"; + }; + slcr: slcr@f8000000 { compatible = "xlnx,zynq-slcr"; reg = <0xF8000000 0x1000>; diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts index 21aea99..34d680a 100644 --- a/arch/arm/boot/dts/zynq-zc702.dts +++ b/arch/arm/boot/dts/zynq-zc702.dts @@ -29,6 +29,11 @@ }; +&gem0 { + status = "okay"; + phy-mode = "rgmii"; +}; + &uart1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/zynq-zc706.dts b/arch/arm/boot/dts/zynq-zc706.dts index 79009e0..b2835d5 100644 --- a/arch/arm/boot/dts/zynq-zc706.dts +++ b/arch/arm/boot/dts/zynq-zc706.dts @@ -30,6 +30,11 @@ }; +&gem0 { + status = "okay"; + phy-mode = "rgmii"; +}; + &uart1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/zynq-zed.dts b/arch/arm/boot/dts/zynq-zed.dts index d6acf2b..2eda068 100644 --- a/arch/arm/boot/dts/zynq-zed.dts +++ b/arch/arm/boot/dts/zynq-zed.dts @@ -30,6 +30,11 @@ }; +&gem0 { + status = "okay"; + phy-mode = "rgmii"; +}; + &uart1 { status = "okay"; }; -- cgit v1.1 From 204accaf18d84dd9dc4a98f37c82053f79b9b931 Mon Sep 17 00:00:00 2001 From: Soren Brinkmann Date: Tue, 26 Nov 2013 17:04:48 -0800 Subject: arm: dt: zynq: Remove 'clock-ranges' from TTC nodes The bindings for the TTC changed in commit 'arm: zynq: Use standard timer binding' (e932900a3279b5dbb6d8f43c7b369003620e137c). That change removed possible subnodes from this driver rendering the 'clock-ranges' property invalid for this node. Signed-off-by: Soren Brinkmann Acked-by: Peter Crosthwaite Acked-by: Daniel Lezcano Signed-off-by: Michal Simek --- arch/arm/boot/dts/zynq-7000.dtsi | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index aebc48d..3ea27e4 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -124,7 +124,6 @@ compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8001000 0x1000>; - clock-ranges; }; ttc1: ttc1@f8002000 { @@ -133,7 +132,6 @@ compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8002000 0x1000>; - clock-ranges; }; scutimer: scutimer@f8f00600 { interrupt-parent = <&intc>; -- cgit v1.1 From 41e4cdb95efa7e8fc88c65cb3c7221e89b9efb49 Mon Sep 17 00:00:00 2001 From: Soren Brinkmann Date: Tue, 26 Nov 2013 17:04:49 -0800 Subject: arm: dt: zynq: Add 'cpus' node Add a 'cpus' node to describe the CPU cores of Zynq. Signed-off-by: Soren Brinkmann Acked-by: Peter Crosthwaite Signed-off-by: Michal Simek --- arch/arm/boot/dts/zynq-7000.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index 3ea27e4..5d7681b 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -15,6 +15,25 @@ / { compatible = "xlnx,zynq-7000"; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0>; + clocks = <&clkc 3>; + }; + + cpu@1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <1>; + clocks = <&clkc 3>; + }; + }; + pmu { compatible = "arm,cortex-a9-pmu"; interrupts = <0 5 4>, <0 6 4>; -- cgit v1.1 From 63b1303d1922f7660bd9e90da56dfbf93134c5aa Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 4 Dec 2013 17:32:54 -0800 Subject: ARM: shmobile: sh73a0: add FSI support via DTSI Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/sh73a0.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index 241c8cd..c460dd2 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -243,4 +243,13 @@ gpio-controller; #gpio-cells = <2>; }; + + sh_fsi2: sound@ec230000 { + #sound-dai-cells = <1>; + compatible = "renesas,sh_fsi2"; + reg = <0xec230000 0x400>; + interrupt-parent = <&gic>; + interrupts = <0 146 0x4>; + status = "disabled"; + }; }; -- cgit v1.1 From 3c2a87c85391272b098827e432813c9437e93992 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 4 Dec 2013 17:33:10 -0800 Subject: ARM: shmobile: kzm9g: add FSI support for DTS This patch support FSI-AK4648 with simple audio card Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/sh73a0-kzm9g-reference.dts | 33 ++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts index 5bb593d..eb8886b 100644 --- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts +++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts @@ -152,6 +152,20 @@ label = "SW1"; }; }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "left_j"; + simple-audio-card,cpu { + sound-dai = <&sh_fsi2 0>; + }; + simple-audio-card,codec { + sound-dai = <&ak4648>; + bitclock-master; + frame-master; + system-clock-frequency = <11289600>; + }; + }; }; &i2c0 { @@ -226,6 +240,12 @@ }; }; }; + + ak4648: ak4648@0x12 { + #sound-dai-cells = <0>; + compatible = "asahi-kasei,ak4648"; + reg = <0x12>; + }; }; &i2c3 { @@ -289,6 +309,12 @@ renesas,groups = "sdhi2_data4", "sdhi2_ctrl"; renesas,function = "sdhi2"; }; + + fsia_pins: sounda { + renesas,groups = "fsia_mclk_in", "fsia_sclk_in", + "fsia_data_in", "fsia_data_out"; + renesas,function = "fsia"; + }; }; &sdhi0 { @@ -309,3 +335,10 @@ broken-cd; status = "okay"; }; + +&sh_fsi2 { + pinctrl-0 = <&fsia_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; -- cgit v1.1 From bd0609896eabe2e64b75d7955ae5ecec528cf860 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 11 Dec 2013 16:42:51 +0100 Subject: ARM: shmobile: koelsch: dts: Add gpio-keys device The board has 7 buttons connected to GPIOs, add a corresponding gpio-keys device. Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791-koelsch-reference.dts | 54 +++++++++++++++++++++++++ 1 file changed, 54 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7791-koelsch-reference.dts b/arch/arm/boot/dts/r8a7791-koelsch-reference.dts index 1919273..588ca17 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch-reference.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch-reference.dts @@ -31,6 +31,60 @@ #size-cells = <1>; }; + gpio-keys { + compatible = "gpio-keys"; + + key-a { + gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; + linux,code = <30>; + label = "SW30"; + gpio-key,wakeup; + debounce-interval = <20>; + }; + key-b { + gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; + linux,code = <48>; + label = "SW31"; + gpio-key,wakeup; + debounce-interval = <20>; + }; + key-c { + gpios = <&gpio7 2 GPIO_ACTIVE_LOW>; + linux,code = <46>; + label = "SW32"; + gpio-key,wakeup; + debounce-interval = <20>; + }; + key-d { + gpios = <&gpio7 3 GPIO_ACTIVE_LOW>; + linux,code = <32>; + label = "SW33"; + gpio-key,wakeup; + debounce-interval = <20>; + }; + key-e { + gpios = <&gpio7 4 GPIO_ACTIVE_LOW>; + linux,code = <18>; + label = "SW34"; + gpio-key,wakeup; + debounce-interval = <20>; + }; + key-f { + gpios = <&gpio7 5 GPIO_ACTIVE_LOW>; + linux,code = <33>; + label = "SW35"; + gpio-key,wakeup; + debounce-interval = <20>; + }; + key-g { + gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; + linux,code = <34>; + label = "SW36"; + gpio-key,wakeup; + debounce-interval = <20>; + }; + }; + leds { compatible = "gpio-leds"; led6 { -- cgit v1.1 From 69e18e26b5773092276a9702244784faf9b6c65f Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Wed, 11 Dec 2013 19:28:39 -0300 Subject: ARM: mvebu: Enable NAND controller in A370 Reference Design board Marvell's Armada 370 Reference Design has a NAND flash, so enable it in the devicetree and add the partitions as prepared in the factory images. In order to skip the driver's custom device detection and use only ONFI detection, the "marvell,keep-config" parameter is used. This is needed because we have no support for setting the timings parameters yet. Signed-off-by: Ezequiel Garcia Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-370-rd.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts index f81810a..abbb807 100644 --- a/arch/arm/boot/dts/armada-370-rd.dts +++ b/arch/arm/boot/dts/armada-370-rd.dts @@ -104,6 +104,27 @@ gpios = <&gpio0 6 1>; }; }; + + nand@d0000 { + status = "okay"; + num-cs = <1>; + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + + partition@0 { + label = "U-Boot"; + reg = <0 0x800000>; + }; + partition@800000 { + label = "Linux"; + reg = <0x800000 0x800000>; + }; + partition@1000000 { + label = "Filesystem"; + reg = <0x1000000 0x3f000000>; + }; + }; }; }; }; -- cgit v1.1 From 20bba5883acf79460dff047cf45b6fb8089168b2 Mon Sep 17 00:00:00 2001 From: Jason Cooper Date: Wed, 11 Dec 2013 20:19:58 +0000 Subject: ARM: kirkwood: sort dt nodes by address This has caused merge conflicts in the past. Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood.dtsi | 140 ++++++++++++++++++++-------------------- 1 file changed, 70 insertions(+), 70 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index dd58a25..1da94c1 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -70,39 +70,21 @@ #address-cells = <1>; #size-cells = <1>; - mbusc: mbus-controller@20000 { - compatible = "marvell,mbus-controller"; - reg = <0x20000 0x80>, <0x1500 0x20>; - }; - - timer: timer@20300 { - compatible = "marvell,orion-timer"; - reg = <0x20300 0x20>; - interrupt-parent = <&bridge_intc>; - interrupts = <1>, <2>; - clocks = <&core_clk 0>; - }; - - intc: main-interrupt-ctrl@20200 { - compatible = "marvell,orion-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x20200 0x10>, <0x20210 0x10>; - }; - - bridge_intc: bridge-interrupt-ctrl@20110 { - compatible = "marvell,orion-bridge-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x20110 0x8>; - interrupts = <1>; - marvell,#interrupts = <6>; - }; - core_clk: core-clocks@10030 { compatible = "marvell,kirkwood-core-clock"; reg = <0x10030 0x4>; - #clock-cells = <1>; + #clock-cells = <1>; + }; + + spi@10600 { + compatible = "marvell,orion-spi"; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + interrupts = <23>; + reg = <0x10600 0x28>; + clocks = <&gate_clk 7>; + status = "disabled"; }; gpio0: gpio@10100 { @@ -129,6 +111,17 @@ clocks = <&gate_clk 7>; }; + i2c@11000 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <29>; + clock-frequency = <100000>; + clocks = <&gate_clk 7>; + status = "disabled"; + }; + serial@12000 { compatible = "ns16550a"; reg = <0x12000 0x100>; @@ -147,15 +140,18 @@ status = "disabled"; }; - spi@10600 { - compatible = "marvell,orion-spi"; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - interrupts = <23>; - reg = <0x10600 0x28>; - clocks = <&gate_clk 7>; - status = "disabled"; + mbusc: mbus-controller@20000 { + compatible = "marvell,mbus-controller"; + reg = <0x20000 0x80>, <0x1500 0x20>; + }; + + bridge_intc: bridge-interrupt-ctrl@20110 { + compatible = "marvell,orion-bridge-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x20110 0x8>; + interrupts = <1>; + marvell,#interrupts = <6>; }; gate_clk: clock-gating-control@2011c { @@ -165,6 +161,21 @@ #clock-cells = <1>; }; + intc: main-interrupt-ctrl@20200 { + compatible = "marvell,orion-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x20200 0x10>, <0x20210 0x10>; + }; + + timer: timer@20300 { + compatible = "marvell,orion-timer"; + reg = <0x20300 0x20>; + interrupt-parent = <&bridge_intc>; + interrupts = <1>, <2>; + clocks = <&core_clk 0>; + }; + wdt: watchdog-timer@20300 { compatible = "marvell,orion-wdt"; reg = <0x20300 0x28>; @@ -174,6 +185,14 @@ status = "okay"; }; + ehci@50000 { + compatible = "marvell,orion-ehci"; + reg = <0x50000 0x1000>; + interrupts = <19>; + clocks = <&gate_clk 3>; + status = "okay"; + }; + xor@60800 { compatible = "marvell,orion-xor"; reg = <0x60800 0x100 @@ -214,37 +233,6 @@ }; }; - ehci@50000 { - compatible = "marvell,orion-ehci"; - reg = <0x50000 0x1000>; - interrupts = <19>; - clocks = <&gate_clk 3>; - status = "okay"; - }; - - i2c@11000 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11000 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <29>; - clock-frequency = <100000>; - clocks = <&gate_clk 7>; - status = "disabled"; - }; - - mdio: mdio-bus@72004 { - compatible = "marvell,orion-mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72004 0x84>; - interrupts = <46>; - clocks = <&gate_clk 0>; - status = "disabled"; - - /* add phy nodes in board file */ - }; - eth0: ethernet-controller@72000 { compatible = "marvell,kirkwood-eth"; #address-cells = <1>; @@ -265,6 +253,18 @@ }; }; + mdio: mdio-bus@72004 { + compatible = "marvell,orion-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x72004 0x84>; + interrupts = <46>; + clocks = <&gate_clk 0>; + status = "disabled"; + + /* add phy nodes in board file */ + }; + eth1: ethernet-controller@76000 { compatible = "marvell,kirkwood-eth"; #address-cells = <1>; -- cgit v1.1 From b31b32119abefd540c71beb93ebb059577748c85 Mon Sep 17 00:00:00 2001 From: Jason Cooper Date: Wed, 11 Dec 2013 20:29:13 +0000 Subject: ARM: dove: sort DT nodes by address Prevent future (unnecessary) merge conflicts Signed-off-by: Jason Cooper --- arch/arm/boot/dts/dove.dtsi | 496 ++++++++++++++++++++++---------------------- 1 file changed, 248 insertions(+), 248 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index db24b41..852db28 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -107,60 +107,29 @@ 0xffffe000 MBUS_ID(0x03, 0x01) 0 0x0000800 /* CESA SRAM 2k */ 0xfffff000 MBUS_ID(0x0d, 0x00) 0 0x0000800>; /* PMU SRAM 2k */ - mbusc: mbus-ctrl@20000 { - compatible = "marvell,mbus-controller"; - reg = <0x20000 0x80>, <0x800100 0x8>; - }; - - timer: timer@20300 { - compatible = "marvell,orion-timer"; - reg = <0x20300 0x20>; - interrupt-parent = <&bridge_intc>; - interrupts = <1>, <2>; + spi0: spi-ctrl@10600 { + compatible = "marvell,orion-spi"; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + interrupts = <6>; + reg = <0x10600 0x28>; clocks = <&core_clk 0>; + pinctrl-0 = <&pmx_spi0>; + pinctrl-names = "default"; + status = "disabled"; }; - intc: main-interrupt-ctrl@20200 { - compatible = "marvell,orion-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x20200 0x10>, <0x20210 0x10>; - }; - - bridge_intc: bridge-interrupt-ctrl@20110 { - compatible = "marvell,orion-bridge-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x20110 0x8>; - interrupts = <0>; - marvell,#interrupts = <5>; - }; - - pmu_intc: pmu-interrupt-ctrl@d0050 { - compatible = "marvell,dove-pmu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xd0050 0x8>; - interrupts = <33>; - marvell,#interrupts = <7>; - }; - - core_clk: core-clocks@d0214 { - compatible = "marvell,dove-core-clock"; - reg = <0xd0214 0x4>; - #clock-cells = <1>; - }; - - gate_clk: clock-gating-ctrl@d0038 { - compatible = "marvell,dove-gating-clock"; - reg = <0xd0038 0x4>; + i2c0: i2c-ctrl@11000 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <11>; + clock-frequency = <400000>; + timeout-ms = <1000>; clocks = <&core_clk 0>; - #clock-cells = <1>; - }; - - thermal: thermal-diode@d001c { - compatible = "marvell,dove-thermal"; - reg = <0xd001c 0x0c>, <0xd005c 0x08>; + status = "disabled"; }; uart0: serial@12000 { @@ -201,34 +170,213 @@ status = "disabled"; }; - gpio0: gpio-ctrl@d0400 { - compatible = "marvell,orion-gpio"; - #gpio-cells = <2>; - gpio-controller; - reg = <0xd0400 0x20>; - ngpios = <32>; + spi1: spi-ctrl@14600 { + compatible = "marvell,orion-spi"; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + interrupts = <5>; + reg = <0x14600 0x28>; + clocks = <&core_clk 0>; + status = "disabled"; + }; + + mbusc: mbus-ctrl@20000 { + compatible = "marvell,mbus-controller"; + reg = <0x20000 0x80>, <0x800100 0x8>; + }; + + bridge_intc: bridge-interrupt-ctrl@20110 { + compatible = "marvell,orion-bridge-intc"; interrupt-controller; - #interrupt-cells = <2>; - interrupts = <12>, <13>, <14>, <60>; + #interrupt-cells = <1>; + reg = <0x20110 0x8>; + interrupts = <0>; + marvell,#interrupts = <5>; }; - gpio1: gpio-ctrl@d0420 { - compatible = "marvell,orion-gpio"; - #gpio-cells = <2>; - gpio-controller; - reg = <0xd0420 0x20>; - ngpios = <32>; + intc: main-interrupt-ctrl@20200 { + compatible = "marvell,orion-intc"; interrupt-controller; - #interrupt-cells = <2>; - interrupts = <61>; + #interrupt-cells = <1>; + reg = <0x20200 0x10>, <0x20210 0x10>; }; - gpio2: gpio-ctrl@e8400 { - compatible = "marvell,orion-gpio"; - #gpio-cells = <2>; - gpio-controller; - reg = <0xe8400 0x0c>; - ngpios = <8>; + timer: timer@20300 { + compatible = "marvell,orion-timer"; + reg = <0x20300 0x20>; + interrupt-parent = <&bridge_intc>; + interrupts = <1>, <2>; + clocks = <&core_clk 0>; + }; + + crypto: crypto-engine@30000 { + compatible = "marvell,orion-crypto"; + reg = <0x30000 0x10000>, + <0xffffe000 0x800>; + reg-names = "regs", "sram"; + interrupts = <31>; + clocks = <&gate_clk 15>; + status = "okay"; + }; + + ehci0: usb-host@50000 { + compatible = "marvell,orion-ehci"; + reg = <0x50000 0x1000>; + interrupts = <24>; + clocks = <&gate_clk 0>; + status = "okay"; + }; + + ehci1: usb-host@51000 { + compatible = "marvell,orion-ehci"; + reg = <0x51000 0x1000>; + interrupts = <25>; + clocks = <&gate_clk 1>; + status = "okay"; + }; + + xor0: dma-engine@60800 { + compatible = "marvell,orion-xor"; + reg = <0x60800 0x100 + 0x60a00 0x100>; + clocks = <&gate_clk 23>; + status = "okay"; + + channel0 { + interrupts = <39>; + dmacap,memcpy; + dmacap,xor; + }; + + channel1 { + interrupts = <40>; + dmacap,memcpy; + dmacap,xor; + }; + }; + + xor1: dma-engine@60900 { + compatible = "marvell,orion-xor"; + reg = <0x60900 0x100 + 0x60b00 0x100>; + clocks = <&gate_clk 24>; + status = "okay"; + + channel0 { + interrupts = <42>; + dmacap,memcpy; + dmacap,xor; + }; + + channel1 { + interrupts = <43>; + dmacap,memcpy; + dmacap,xor; + }; + }; + + sdio1: sdio-host@90000 { + compatible = "marvell,dove-sdhci"; + reg = <0x90000 0x100>; + interrupts = <36>, <38>; + clocks = <&gate_clk 9>; + pinctrl-0 = <&pmx_sdio1>; + pinctrl-names = "default"; + status = "disabled"; + }; + + eth: ethernet-ctrl@72000 { + compatible = "marvell,orion-eth"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x72000 0x4000>; + clocks = <&gate_clk 2>; + marvell,tx-checksum-limit = <1600>; + status = "disabled"; + + ethernet-port@0 { + device_type = "network"; + compatible = "marvell,orion-eth-port"; + reg = <0>; + interrupts = <29>; + /* overwrite MAC address in bootloader */ + local-mac-address = [00 00 00 00 00 00]; + phy-handle = <ðphy>; + }; + }; + + mdio: mdio-bus@72004 { + compatible = "marvell,orion-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x72004 0x84>; + interrupts = <30>; + clocks = <&gate_clk 2>; + status = "disabled"; + + ethphy: ethernet-phy { + device_type = "ethernet-phy"; + /* set phy address in board file */ + }; + }; + + sdio0: sdio-host@92000 { + compatible = "marvell,dove-sdhci"; + reg = <0x92000 0x100>; + interrupts = <35>, <37>; + clocks = <&gate_clk 8>; + pinctrl-0 = <&pmx_sdio0>; + pinctrl-names = "default"; + status = "disabled"; + }; + + sata0: sata-host@a0000 { + compatible = "marvell,orion-sata"; + reg = <0xa0000 0x2400>; + interrupts = <62>; + clocks = <&gate_clk 3>; + nr-ports = <1>; + status = "disabled"; + }; + + audio0: audio-controller@b0000 { + compatible = "marvell,dove-audio"; + reg = <0xb0000 0x2210>; + interrupts = <19>, <20>; + clocks = <&gate_clk 12>; + clock-names = "internal"; + status = "disabled"; + }; + + audio1: audio-controller@b4000 { + compatible = "marvell,dove-audio"; + reg = <0xb4000 0x2210>; + interrupts = <21>, <22>; + clocks = <&gate_clk 13>; + clock-names = "internal"; + status = "disabled"; + }; + + thermal: thermal-diode@d001c { + compatible = "marvell,dove-thermal"; + reg = <0xd001c 0x0c>, <0xd005c 0x08>; + }; + + gate_clk: clock-gating-ctrl@d0038 { + compatible = "marvell,dove-gating-clock"; + reg = <0xd0038 0x4>; + clocks = <&core_clk 0>; + #clock-cells = <1>; + }; + + pmu_intc: pmu-interrupt-ctrl@d0050 { + compatible = "marvell,dove-pmu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xd0050 0x8>; + interrupts = <33>; + marvell,#interrupts = <7>; }; pinctrl: pin-ctrl@d0200 { @@ -422,85 +570,32 @@ }; }; - spi0: spi-ctrl@10600 { - compatible = "marvell,orion-spi"; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - interrupts = <6>; - reg = <0x10600 0x28>; - clocks = <&core_clk 0>; - pinctrl-0 = <&pmx_spi0>; - pinctrl-names = "default"; - status = "disabled"; - }; - - spi1: spi-ctrl@14600 { - compatible = "marvell,orion-spi"; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <1>; - interrupts = <5>; - reg = <0x14600 0x28>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - i2c0: i2c-ctrl@11000 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11000 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <11>; - clock-frequency = <400000>; - timeout-ms = <1000>; - clocks = <&core_clk 0>; - status = "disabled"; - }; - - ehci0: usb-host@50000 { - compatible = "marvell,orion-ehci"; - reg = <0x50000 0x1000>; - interrupts = <24>; - clocks = <&gate_clk 0>; - status = "okay"; - }; - - ehci1: usb-host@51000 { - compatible = "marvell,orion-ehci"; - reg = <0x51000 0x1000>; - interrupts = <25>; - clocks = <&gate_clk 1>; - status = "okay"; - }; - - sdio0: sdio-host@92000 { - compatible = "marvell,dove-sdhci"; - reg = <0x92000 0x100>; - interrupts = <35>, <37>; - clocks = <&gate_clk 8>; - pinctrl-0 = <&pmx_sdio0>; - pinctrl-names = "default"; - status = "disabled"; + core_clk: core-clocks@d0214 { + compatible = "marvell,dove-core-clock"; + reg = <0xd0214 0x4>; + #clock-cells = <1>; }; - sdio1: sdio-host@90000 { - compatible = "marvell,dove-sdhci"; - reg = <0x90000 0x100>; - interrupts = <36>, <38>; - clocks = <&gate_clk 9>; - pinctrl-0 = <&pmx_sdio1>; - pinctrl-names = "default"; - status = "disabled"; + gpio0: gpio-ctrl@d0400 { + compatible = "marvell,orion-gpio"; + #gpio-cells = <2>; + gpio-controller; + reg = <0xd0400 0x20>; + ngpios = <32>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <12>, <13>, <14>, <60>; }; - sata0: sata-host@a0000 { - compatible = "marvell,orion-sata"; - reg = <0xa0000 0x2400>; - interrupts = <62>; - clocks = <&gate_clk 3>; - nr-ports = <1>; - status = "disabled"; + gpio1: gpio-ctrl@d0420 { + compatible = "marvell,orion-gpio"; + #gpio-cells = <2>; + gpio-controller; + reg = <0xd0420 0x20>; + ngpios = <32>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <61>; }; rtc: real-time-clock@d8500 { @@ -510,107 +605,12 @@ interrupts = <5>; }; - crypto: crypto-engine@30000 { - compatible = "marvell,orion-crypto"; - reg = <0x30000 0x10000>, - <0xffffe000 0x800>; - reg-names = "regs", "sram"; - interrupts = <31>; - clocks = <&gate_clk 15>; - status = "okay"; - }; - - xor0: dma-engine@60800 { - compatible = "marvell,orion-xor"; - reg = <0x60800 0x100 - 0x60a00 0x100>; - clocks = <&gate_clk 23>; - status = "okay"; - - channel0 { - interrupts = <39>; - dmacap,memcpy; - dmacap,xor; - }; - - channel1 { - interrupts = <40>; - dmacap,memcpy; - dmacap,xor; - }; - }; - - xor1: dma-engine@60900 { - compatible = "marvell,orion-xor"; - reg = <0x60900 0x100 - 0x60b00 0x100>; - clocks = <&gate_clk 24>; - status = "okay"; - - channel0 { - interrupts = <42>; - dmacap,memcpy; - dmacap,xor; - }; - - channel1 { - interrupts = <43>; - dmacap,memcpy; - dmacap,xor; - }; - }; - - mdio: mdio-bus@72004 { - compatible = "marvell,orion-mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72004 0x84>; - interrupts = <30>; - clocks = <&gate_clk 2>; - status = "disabled"; - - ethphy: ethernet-phy { - device_type = "ethernet-phy"; - /* set phy address in board file */ - }; - }; - - eth: ethernet-ctrl@72000 { - compatible = "marvell,orion-eth"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72000 0x4000>; - clocks = <&gate_clk 2>; - marvell,tx-checksum-limit = <1600>; - status = "disabled"; - - ethernet-port@0 { - device_type = "network"; - compatible = "marvell,orion-eth-port"; - reg = <0>; - interrupts = <29>; - /* overwrite MAC address in bootloader */ - local-mac-address = [00 00 00 00 00 00]; - phy-handle = <ðphy>; - }; - }; - - audio0: audio-controller@b0000 { - compatible = "marvell,dove-audio"; - reg = <0xb0000 0x2210>; - interrupts = <19>, <20>; - clocks = <&gate_clk 12>; - clock-names = "internal"; - status = "disabled"; - }; - - audio1: audio-controller@b4000 { - compatible = "marvell,dove-audio"; - reg = <0xb4000 0x2210>; - interrupts = <21>, <22>; - clocks = <&gate_clk 13>; - clock-names = "internal"; - status = "disabled"; + gpio2: gpio-ctrl@e8400 { + compatible = "marvell,orion-gpio"; + #gpio-cells = <2>; + gpio-controller; + reg = <0xe8400 0x0c>; + ngpios = <8>; }; }; }; -- cgit v1.1 From 6226cf186cd1d8dfd3495d9084b7ca543bb2ea1a Mon Sep 17 00:00:00 2001 From: Jason Cooper Date: Wed, 11 Dec 2013 20:32:50 +0000 Subject: ARM: orion5x: sort DT nodes by address Prevent future unnecessary merge conflicts Signed-off-by: Jason Cooper --- arch/arm/boot/dts/orion5x.dtsi | 106 ++++++++++++++++++++--------------------- 1 file changed, 53 insertions(+), 53 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi index e06c37e..9f51538 100644 --- a/arch/arm/boot/dts/orion5x.dtsi +++ b/arch/arm/boot/dts/orion5x.dtsi @@ -42,6 +42,25 @@ interrupts = <6>, <7>, <8>, <9>; }; + spi@10600 { + compatible = "marvell,orion-spi"; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + reg = <0x10600 0x28>; + status = "disabled"; + }; + + i2c@11000 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <5>; + clock-frequency = <100000>; + status = "disabled"; + }; + serial@12000 { compatible = "ns16550a"; reg = <0x12000 0x100>; @@ -60,15 +79,6 @@ status = "disabled"; }; - spi@10600 { - compatible = "marvell,orion-spi"; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - reg = <0x10600 0x28>; - status = "disabled"; - }; - wdt@20300 { compatible = "marvell,orion-wdt"; reg = <0x20300 0x28>; @@ -82,30 +92,6 @@ status = "disabled"; }; - ehci@a0000 { - compatible = "marvell,orion-ehci"; - reg = <0xa0000 0x1000>; - interrupts = <12>; - status = "disabled"; - }; - - sata@80000 { - compatible = "marvell,orion-sata"; - reg = <0x80000 0x5000>; - interrupts = <29>; - status = "disabled"; - }; - - i2c@11000 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11000 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <5>; - clock-frequency = <100000>; - status = "disabled"; - }; - xor@60900 { compatible = "marvell,orion-xor"; reg = <0x60900 0x100 @@ -125,26 +111,6 @@ }; }; - crypto@90000 { - compatible = "marvell,orion-crypto"; - reg = <0x90000 0x10000>, - <0xf2200000 0x800>; - reg-names = "regs", "sram"; - interrupts = <28>; - status = "okay"; - }; - - mdio: mdio-bus@72004 { - compatible = "marvell,orion-mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72004 0x84>; - interrupts = <22>; - status = "disabled"; - - /* add phy nodes in board file */ - }; - eth: ethernet-controller@72000 { compatible = "marvell,orion-eth"; #address-cells = <1>; @@ -162,5 +128,39 @@ /* set phy-handle property in board file */ }; }; + + mdio: mdio-bus@72004 { + compatible = "marvell,orion-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x72004 0x84>; + interrupts = <22>; + status = "disabled"; + + /* add phy nodes in board file */ + }; + + sata@80000 { + compatible = "marvell,orion-sata"; + reg = <0x80000 0x5000>; + interrupts = <29>; + status = "disabled"; + }; + + crypto@90000 { + compatible = "marvell,orion-crypto"; + reg = <0x90000 0x10000>, + <0xf2200000 0x800>; + reg-names = "regs", "sram"; + interrupts = <28>; + status = "okay"; + }; + + ehci@a0000 { + compatible = "marvell,orion-ehci"; + reg = <0xa0000 0x1000>; + interrupts = <12>; + status = "disabled"; + }; }; }; -- cgit v1.1 From a095b1c78a35f05755ca2f0e106d84792974aef5 Mon Sep 17 00:00:00 2001 From: Jason Cooper Date: Thu, 12 Dec 2013 13:59:17 +0000 Subject: ARM: mvebu: sort DT nodes by address Prevent future unnecessary merge conflicts Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-370-xp.dtsi | 176 +++++++++++++++++------------------ arch/arm/boot/dts/armada-370.dtsi | 74 +++++++-------- arch/arm/boot/dts/armada-xp.dtsi | 100 ++++++++++---------- 3 files changed, 175 insertions(+), 175 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index f2b6ae4..46a541e 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -103,22 +103,52 @@ #size-cells = <1>; ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; - mbusc: mbus-controller@20000 { - compatible = "marvell,mbus-controller"; - reg = <0x20000 0x100>, <0x20180 0x20>; + rtc@10300 { + compatible = "marvell,orion-rtc"; + reg = <0x10300 0x20>; + interrupts = <50>; }; - mpic: interrupt-controller@20000 { - compatible = "marvell,mpic"; - #interrupt-cells = <1>; - #size-cells = <1>; - interrupt-controller; - msi-controller; + spi0: spi@10600 { + compatible = "marvell,orion-spi"; + reg = <0x10600 0x28>; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + interrupts = <30>; + clocks = <&coreclk 0>; + status = "disabled"; }; - coherency-fabric@20200 { - compatible = "marvell,coherency-fabric"; - reg = <0x20200 0xb0>, <0x21810 0x1c>; + spi1: spi@10680 { + compatible = "marvell,orion-spi"; + reg = <0x10680 0x28>; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + interrupts = <92>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + i2c0: i2c@11000 { + compatible = "marvell,mv64xxx-i2c"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <31>; + timeout-ms = <1000>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + i2c1: i2c@11100 { + compatible = "marvell,mv64xxx-i2c"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <32>; + timeout-ms = <1000>; + clocks = <&coreclk 0>; + status = "disabled"; }; serial@12000 { @@ -146,25 +176,41 @@ clock-output-names = "nand"; }; + mbusc: mbus-controller@20000 { + compatible = "marvell,mbus-controller"; + reg = <0x20000 0x100>, <0x20180 0x20>; + }; + + mpic: interrupt-controller@20000 { + compatible = "marvell,mpic"; + #interrupt-cells = <1>; + #size-cells = <1>; + interrupt-controller; + msi-controller; + }; + + coherency-fabric@20200 { + compatible = "marvell,coherency-fabric"; + reg = <0x20200 0xb0>, <0x21810 0x1c>; + }; + timer@20300 { reg = <0x20300 0x30>, <0x21040 0x30>; interrupts = <37>, <38>, <39>, <40>, <5>, <6>; }; - sata@a0000 { - compatible = "marvell,orion-sata"; - reg = <0xa0000 0x5000>; - interrupts = <55>; - clocks = <&gateclk 15>, <&gateclk 30>; - clock-names = "0", "1"; + usb@50000 { + compatible = "marvell,orion-ehci"; + reg = <0x50000 0x500>; + interrupts = <45>; status = "disabled"; }; - mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "marvell,orion-mdio"; - reg = <0x72004 0x4>; + usb@51000 { + compatible = "marvell,orion-ehci"; + reg = <0x51000 0x500>; + interrupts = <46>; + status = "disabled"; }; eth0: ethernet@70000 { @@ -175,6 +221,13 @@ status = "disabled"; }; + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "marvell,orion-mdio"; + reg = <0x72004 0x4>; + }; + eth1: ethernet@74000 { compatible = "marvell,armada-370-neta"; reg = <0x74000 0x4000>; @@ -183,32 +236,25 @@ status = "disabled"; }; - i2c0: i2c@11000 { - compatible = "marvell,mv64xxx-i2c"; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <31>; - timeout-ms = <1000>; - clocks = <&coreclk 0>; + sata@a0000 { + compatible = "marvell,orion-sata"; + reg = <0xa0000 0x5000>; + interrupts = <55>; + clocks = <&gateclk 15>, <&gateclk 30>; + clock-names = "0", "1"; status = "disabled"; }; - i2c1: i2c@11100 { - compatible = "marvell,mv64xxx-i2c"; + nand@d0000 { + compatible = "marvell,armada370-nand"; + reg = <0xd0000 0x54>; #address-cells = <1>; - #size-cells = <0>; - interrupts = <32>; - timeout-ms = <1000>; - clocks = <&coreclk 0>; + #size-cells = <1>; + interrupts = <113>; + clocks = <&coredivclk 0>; status = "disabled"; }; - rtc@10300 { - compatible = "marvell,orion-rtc"; - reg = <0x10300 0x20>; - interrupts = <50>; - }; - mvsdio@d4000 { compatible = "marvell,orion-sdio"; reg = <0xd4000 0x200>; @@ -220,52 +266,6 @@ cap-mmc-highspeed; status = "disabled"; }; - - usb@50000 { - compatible = "marvell,orion-ehci"; - reg = <0x50000 0x500>; - interrupts = <45>; - status = "disabled"; - }; - - usb@51000 { - compatible = "marvell,orion-ehci"; - reg = <0x51000 0x500>; - interrupts = <46>; - status = "disabled"; - }; - - spi0: spi@10600 { - compatible = "marvell,orion-spi"; - reg = <0x10600 0x28>; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - interrupts = <30>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - spi1: spi@10680 { - compatible = "marvell,orion-spi"; - reg = <0x10680 0x28>; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <1>; - interrupts = <92>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - nand@d0000 { - compatible = "marvell,armada370-nand"; - reg = <0xd0000 0x54>; - #address-cells = <1>; - #size-cells = <1>; - interrupts = <113>; - clocks = <&coredivclk 0>; - status = "disabled"; - }; }; }; diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index 7a4b82e..0d8530c 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi @@ -91,11 +91,6 @@ }; internal-regs { - system-controller@18200 { - compatible = "marvell,armada-370-xp-system-controller"; - reg = <0x18200 0x100>; - }; - L2: l2-cache { compatible = "marvell,aurora-outer-cache"; reg = <0x08000 0x1000>; @@ -103,8 +98,17 @@ wt-override; }; - interrupt-controller@20000 { - reg = <0x20a00 0x1d0>, <0x21870 0x58>; + i2c0: i2c@11000 { + reg = <0x11000 0x20>; + }; + + i2c1: i2c@11100 { + reg = <0x11100 0x20>; + }; + + system-controller@18200 { + compatible = "marvell,armada-370-xp-system-controller"; + reg = <0x18200 0x100>; }; pinctrl { @@ -163,9 +167,11 @@ interrupts = <91>; }; - timer@20300 { - compatible = "marvell,armada-370-timer"; - clocks = <&coreclk 2>; + gateclk: clock-gating-control@18220 { + compatible = "marvell,armada-370-gating-clock"; + reg = <0x18220 0x4>; + clocks = <&coreclk 0>; + #clock-cells = <1>; }; coreclk: mvebu-sar@18230 { @@ -174,11 +180,28 @@ #clock-cells = <1>; }; - gateclk: clock-gating-control@18220 { - compatible = "marvell,armada-370-gating-clock"; - reg = <0x18220 0x4>; + thermal@18300 { + compatible = "marvell,armada370-thermal"; + reg = <0x18300 0x4 + 0x18304 0x4>; + status = "okay"; + }; + + interrupt-controller@20000 { + reg = <0x20a00 0x1d0>, <0x21870 0x58>; + }; + + timer@20300 { + compatible = "marvell,armada-370-timer"; + clocks = <&coreclk 2>; + }; + + usb@50000 { + clocks = <&coreclk 0>; + }; + + usb@51000 { clocks = <&coreclk 0>; - #clock-cells = <1>; }; xor@60800 { @@ -218,29 +241,6 @@ dmacap,memset; }; }; - - i2c0: i2c@11000 { - reg = <0x11000 0x20>; - }; - - i2c1: i2c@11100 { - reg = <0x11100 0x20>; - }; - - usb@50000 { - clocks = <&coreclk 0>; - }; - - usb@51000 { - clocks = <&coreclk 0>; - }; - - thermal@18300 { - compatible = "marvell,armada370-thermal"; - reg = <0x18300 0x4 - 0x18304 0x4>; - status = "okay"; - }; }; }; }; diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index 281c644..4919fb8 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi @@ -42,13 +42,14 @@ wt-override; }; - interrupt-controller@20000 { - reg = <0x20a00 0x2d0>, <0x21070 0x58>; + i2c0: i2c@11000 { + compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; + reg = <0x11000 0x100>; }; - armada-370-xp-pmsu@22000 { - compatible = "marvell,armada-370-xp-pmsu"; - reg = <0x22100 0x430>, <0x20800 0x20>; + i2c1: i2c@11100 { + compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; + reg = <0x11100 0x100>; }; serial@12200 { @@ -68,10 +69,16 @@ status = "disabled"; }; - timer@20300 { - compatible = "marvell,armada-xp-timer"; - clocks = <&coreclk 2>, <&refclk>; - clock-names = "nbclk", "fixed"; + system-controller@18200 { + compatible = "marvell,armada-370-xp-system-controller"; + reg = <0x18200 0x500>; + }; + + gateclk: clock-gating-control@18220 { + compatible = "marvell,armada-xp-gating-clock"; + reg = <0x18220 0x4>; + clocks = <&coreclk 0>; + #clock-cells = <1>; }; coreclk: mvebu-sar@18230 { @@ -80,6 +87,13 @@ #clock-cells = <1>; }; + thermal@182b0 { + compatible = "marvell,armadaxp-thermal"; + reg = <0x182b0 0x4 + 0x184d0 0x4>; + status = "okay"; + }; + cpuclk: clock-complex@18700 { #clock-cells = <1>; compatible = "marvell,armada-xp-cpu-clock"; @@ -87,16 +101,19 @@ clocks = <&coreclk 1>; }; - gateclk: clock-gating-control@18220 { - compatible = "marvell,armada-xp-gating-clock"; - reg = <0x18220 0x4>; - clocks = <&coreclk 0>; - #clock-cells = <1>; + interrupt-controller@20000 { + reg = <0x20a00 0x2d0>, <0x21070 0x58>; }; - system-controller@18200 { - compatible = "marvell,armada-370-xp-system-controller"; - reg = <0x18200 0x500>; + timer@20300 { + compatible = "marvell,armada-xp-timer"; + clocks = <&coreclk 2>, <&refclk>; + clock-names = "nbclk", "fixed"; + }; + + armada-370-xp-pmsu@22000 { + compatible = "marvell,armada-370-xp-pmsu"; + reg = <0x22100 0x430>, <0x20800 0x20>; }; eth2: ethernet@30000 { @@ -107,6 +124,22 @@ status = "disabled"; }; + usb@50000 { + clocks = <&gateclk 18>; + }; + + usb@51000 { + clocks = <&gateclk 19>; + }; + + usb@52000 { + compatible = "marvell,orion-ehci"; + reg = <0x52000 0x500>; + interrupts = <47>; + clocks = <&gateclk 20>; + status = "disabled"; + }; + xor@60900 { compatible = "marvell,orion-xor"; reg = <0x60900 0x100 @@ -146,39 +179,6 @@ dmacap,memset; }; }; - - i2c0: i2c@11000 { - compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; - reg = <0x11000 0x100>; - }; - - i2c1: i2c@11100 { - compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; - reg = <0x11100 0x100>; - }; - - usb@50000 { - clocks = <&gateclk 18>; - }; - - usb@51000 { - clocks = <&gateclk 19>; - }; - - usb@52000 { - compatible = "marvell,orion-ehci"; - reg = <0x52000 0x500>; - interrupts = <47>; - clocks = <&gateclk 20>; - status = "disabled"; - }; - - thermal@182b0 { - compatible = "marvell,armadaxp-thermal"; - reg = <0x182b0 0x4 - 0x184d0 0x4>; - status = "okay"; - }; }; }; -- cgit v1.1 From b8273f2eb5d266755a2ae2db39b2cc16f29b0941 Mon Sep 17 00:00:00 2001 From: Murali Karicheri Date: Sat, 23 Nov 2013 16:26:06 -0500 Subject: ARM: keystone: dts: add a k2hk-evm specific dts file This patch adds K2 Kepler/Hawking evm (k2hk-evm) specific dts file. To enable re-use of bindings across multiple evms of this family, rename current keystone.dts to keystone.dtsi and include it in the evm specific dts file. K2 SoC has separate ref clock inputs for various clocks. So add separate ref clock nodes for ARM, DDR3A, DDR3B and PA PLL input clocks in k2hk-evm.dts. While at it, rename refclkmain to refclksys based on device User Guide naming convention Signed-off-by: Murali Karicheri Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/k2hk-evm.dts | 55 ++++++++++ arch/arm/boot/dts/keystone-clocks.dtsi | 23 ++--- arch/arm/boot/dts/keystone.dts | 183 --------------------------------- arch/arm/boot/dts/keystone.dtsi | 181 ++++++++++++++++++++++++++++++++ 4 files changed, 242 insertions(+), 200 deletions(-) create mode 100644 arch/arm/boot/dts/k2hk-evm.dts delete mode 100644 arch/arm/boot/dts/keystone.dts create mode 100644 arch/arm/boot/dts/keystone.dtsi (limited to 'arch') diff --git a/arch/arm/boot/dts/k2hk-evm.dts b/arch/arm/boot/dts/k2hk-evm.dts new file mode 100644 index 0000000..15b3a95 --- /dev/null +++ b/arch/arm/boot/dts/k2hk-evm.dts @@ -0,0 +1,55 @@ +/* + * Copyright 2013 Texas Instruments, Inc. + * + * Keystone 2 Kepler/Hawking EVM device tree + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "keystone.dtsi" + +/ { + compatible = "ti,keystone-evm"; + + soc { + clock { + refclksys: refclksys { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <122880000>; + clock-output-names = "refclk-sys"; + }; + + refclkpass: refclkpass { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <122880000>; + clock-output-names = "refclk-pass"; + }; + + refclkarm: refclkarm { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "refclk-arm"; + }; + + refclkddr3a: refclkddr3a { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + clock-output-names = "refclk-ddr3a"; + }; + + refclkddr3b: refclkddr3b { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + clock-output-names = "refclk-ddr3b"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/keystone-clocks.dtsi b/arch/arm/boot/dts/keystone-clocks.dtsi index d6713b1..67e70ec 100644 --- a/arch/arm/boot/dts/keystone-clocks.dtsi +++ b/arch/arm/boot/dts/keystone-clocks.dtsi @@ -13,17 +13,10 @@ clocks { #size-cells = <1>; ranges; - refclkmain: refclkmain { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <122880000>; - clock-output-names = "refclk-main"; - }; - mainpllclk: mainpllclk@2310110 { #clock-cells = <0>; compatible = "ti,keystone,main-pll-clock"; - clocks = <&refclkmain>; + clocks = <&refclksys>; reg = <0x02620350 4>, <0x02310110 4>; reg-names = "control", "multiplier"; fixed-postdiv = <2>; @@ -32,47 +25,43 @@ clocks { papllclk: papllclk@2620358 { #clock-cells = <0>; compatible = "ti,keystone,pll-clock"; - clocks = <&refclkmain>; + clocks = <&refclkpass>; clock-output-names = "pa-pll-clk"; reg = <0x02620358 4>; reg-names = "control"; - fixed-postdiv = <6>; }; ddr3allclk: ddr3apllclk@2620360 { #clock-cells = <0>; compatible = "ti,keystone,pll-clock"; - clocks = <&refclkmain>; + clocks = <&refclkddr3a>; clock-output-names = "ddr-3a-pll-clk"; reg = <0x02620360 4>; reg-names = "control"; - fixed-postdiv = <6>; }; ddr3bllclk: ddr3bpllclk@2620368 { #clock-cells = <0>; compatible = "ti,keystone,pll-clock"; - clocks = <&refclkmain>; + clocks = <&refclkddr3b>; clock-output-names = "ddr-3b-pll-clk"; reg = <0x02620368 4>; reg-names = "control"; - fixed-postdiv = <6>; }; armpllclk: armpllclk@2620370 { #clock-cells = <0>; compatible = "ti,keystone,pll-clock"; - clocks = <&refclkmain>; + clocks = <&refclkarm>; clock-output-names = "arm-pll-clk"; reg = <0x02620370 4>; reg-names = "control"; - fixed-postdiv = <6>; }; mainmuxclk: mainmuxclk@2310108 { #clock-cells = <0>; compatible = "ti,keystone,pll-mux-clock"; - clocks = <&mainpllclk>, <&refclkmain>; + clocks = <&mainpllclk>, <&refclksys>; reg = <0x02310108 4>; bit-shift = <23>; bit-mask = <1>; diff --git a/arch/arm/boot/dts/keystone.dts b/arch/arm/boot/dts/keystone.dts deleted file mode 100644 index 100bdf5..0000000 --- a/arch/arm/boot/dts/keystone.dts +++ /dev/null @@ -1,183 +0,0 @@ -/* - * Copyright 2013 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; -#include - -#include "skeleton.dtsi" - -/ { - model = "Texas Instruments Keystone 2 SoC"; - compatible = "ti,keystone-evm"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&gic>; - - aliases { - serial0 = &uart0; - }; - - memory { - reg = <0x00000000 0x80000000 0x00000000 0x40000000>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - interrupt-parent = <&gic>; - - cpu@0 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <0>; - }; - - cpu@1 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <1>; - }; - - cpu@2 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <2>; - }; - - cpu@3 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <3>; - }; - }; - - gic: interrupt-controller { - compatible = "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - #size-cells = <0>; - #address-cells = <1>; - interrupt-controller; - reg = <0x0 0x02561000 0x0 0x1000>, - <0x0 0x02562000 0x0 0x2000>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = - , - , - , - ; - }; - - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupts = , - , - , - ; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "ti,keystone","simple-bus"; - interrupt-parent = <&gic>; - ranges = <0x0 0x0 0x0 0xc0000000>; - - rstctrl: reset-controller { - compatible = "ti,keystone-reset"; - reg = <0x023100e8 4>; /* pll reset control reg */ - }; - - /include/ "keystone-clocks.dtsi" - - uart0: serial@02530c00 { - compatible = "ns16550a"; - current-speed = <115200>; - reg-shift = <2>; - reg-io-width = <4>; - reg = <0x02530c00 0x100>; - clocks = <&clkuart0>; - interrupts = ; - }; - - uart1: serial@02531000 { - compatible = "ns16550a"; - current-speed = <115200>; - reg-shift = <2>; - reg-io-width = <4>; - reg = <0x02531000 0x100>; - clocks = <&clkuart1>; - interrupts = ; - }; - - i2c0: i2c@2530000 { - compatible = "ti,davinci-i2c"; - reg = <0x02530000 0x400>; - clock-frequency = <100000>; - clocks = <&clki2c>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - - dtt@50 { - compatible = "at,24c1024"; - reg = <0x50>; - }; - }; - - i2c1: i2c@2530400 { - compatible = "ti,davinci-i2c"; - reg = <0x02530400 0x400>; - clock-frequency = <100000>; - clocks = <&clki2c>; - interrupts = ; - }; - - i2c2: i2c@2530800 { - compatible = "ti,davinci-i2c"; - reg = <0x02530800 0x400>; - clock-frequency = <100000>; - clocks = <&clki2c>; - interrupts = ; - }; - - spi0: spi@21000400 { - compatible = "ti,dm6441-spi"; - reg = <0x21000400 0x200>; - num-cs = <4>; - ti,davinci-spi-intr-line = <0>; - interrupts = ; - clocks = <&clkspi>; - }; - - spi1: spi@21000600 { - compatible = "ti,dm6441-spi"; - reg = <0x21000600 0x200>; - num-cs = <4>; - ti,davinci-spi-intr-line = <0>; - interrupts = ; - clocks = <&clkspi>; - }; - - spi2: spi@21000800 { - compatible = "ti,dm6441-spi"; - reg = <0x21000800 0x200>; - num-cs = <4>; - ti,davinci-spi-intr-line = <0>; - interrupts = ; - clocks = <&clkspi>; - }; - }; -}; diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi new file mode 100644 index 0000000..c01c6fb --- /dev/null +++ b/arch/arm/boot/dts/keystone.dtsi @@ -0,0 +1,181 @@ +/* + * Copyright 2013 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include + +#include "skeleton.dtsi" + +/ { + model = "Texas Instruments Keystone 2 SoC"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + + aliases { + serial0 = &uart0; + }; + + memory { + reg = <0x00000000 0x80000000 0x00000000 0x40000000>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&gic>; + + cpu@0 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <1>; + }; + + cpu@2 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <2>; + }; + + cpu@3 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <3>; + }; + }; + + gic: interrupt-controller { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + #size-cells = <0>; + #address-cells = <1>; + interrupt-controller; + reg = <0x0 0x02561000 0x0 0x1000>, + <0x0 0x02562000 0x0 0x2000>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = + , + , + , + ; + }; + + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts = , + , + , + ; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ti,keystone","simple-bus"; + interrupt-parent = <&gic>; + ranges = <0x0 0x0 0x0 0xc0000000>; + + rstctrl: reset-controller { + compatible = "ti,keystone-reset"; + reg = <0x023100e8 4>; /* pll reset control reg */ + }; + + /include/ "keystone-clocks.dtsi" + + uart0: serial@02530c00 { + compatible = "ns16550a"; + current-speed = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + reg = <0x02530c00 0x100>; + clocks = <&clkuart0>; + interrupts = ; + }; + + uart1: serial@02531000 { + compatible = "ns16550a"; + current-speed = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + reg = <0x02531000 0x100>; + clocks = <&clkuart1>; + interrupts = ; + }; + + i2c0: i2c@2530000 { + compatible = "ti,davinci-i2c"; + reg = <0x02530000 0x400>; + clock-frequency = <100000>; + clocks = <&clki2c>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + + dtt@50 { + compatible = "at,24c1024"; + reg = <0x50>; + }; + }; + + i2c1: i2c@2530400 { + compatible = "ti,davinci-i2c"; + reg = <0x02530400 0x400>; + clock-frequency = <100000>; + clocks = <&clki2c>; + interrupts = ; + }; + + i2c2: i2c@2530800 { + compatible = "ti,davinci-i2c"; + reg = <0x02530800 0x400>; + clock-frequency = <100000>; + clocks = <&clki2c>; + interrupts = ; + }; + + spi0: spi@21000400 { + compatible = "ti,dm6441-spi"; + reg = <0x21000400 0x200>; + num-cs = <4>; + ti,davinci-spi-intr-line = <0>; + interrupts = ; + clocks = <&clkspi>; + }; + + spi1: spi@21000600 { + compatible = "ti,dm6441-spi"; + reg = <0x21000600 0x200>; + num-cs = <4>; + ti,davinci-spi-intr-line = <0>; + interrupts = ; + clocks = <&clkspi>; + }; + + spi2: spi@21000800 { + compatible = "ti,dm6441-spi"; + reg = <0x21000800 0x200>; + num-cs = <4>; + ti,davinci-spi-intr-line = <0>; + interrupts = ; + clocks = <&clkspi>; + }; + }; +}; -- cgit v1.1 From afdd8b61115801c2fdb2b407eb879fd995ec8af4 Mon Sep 17 00:00:00 2001 From: Murali Karicheri Date: Sat, 23 Nov 2013 16:26:11 -0500 Subject: ARM: keystone: dts: fix typo in the ddr3 pllclk node name Fix following typo ddr3allclk -> ddr3apllclk ddr3bllclk -> ddr3bpllclk Signed-off-by: Murali Karicheri Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/keystone-clocks.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/keystone-clocks.dtsi b/arch/arm/boot/dts/keystone-clocks.dtsi index 67e70ec..2a2f247 100644 --- a/arch/arm/boot/dts/keystone-clocks.dtsi +++ b/arch/arm/boot/dts/keystone-clocks.dtsi @@ -31,7 +31,7 @@ clocks { reg-names = "control"; }; - ddr3allclk: ddr3apllclk@2620360 { + ddr3apllclk: ddr3apllclk@2620360 { #clock-cells = <0>; compatible = "ti,keystone,pll-clock"; clocks = <&refclkddr3a>; @@ -40,7 +40,7 @@ clocks { reg-names = "control"; }; - ddr3bllclk: ddr3bpllclk@2620368 { + ddr3bpllclk: ddr3bpllclk@2620368 { #clock-cells = <0>; compatible = "ti,keystone,pll-clock"; clocks = <&refclkddr3b>; -- cgit v1.1 From 1f2181a95d2a4bf8bd90406c1041a68679dffe49 Mon Sep 17 00:00:00 2001 From: Murali Karicheri Date: Sat, 23 Nov 2013 16:26:16 -0500 Subject: ARM: keystone: dts: add paclk divider clock node PA subsystem has a fixed factor clock at the input which is input clock divided by 3. This patch adds this clock node to dts Signed-off-by: Murali Karicheri Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/keystone-clocks.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/keystone-clocks.dtsi b/arch/arm/boot/dts/keystone-clocks.dtsi index 2a2f247..2363593 100644 --- a/arch/arm/boot/dts/keystone-clocks.dtsi +++ b/arch/arm/boot/dts/keystone-clocks.dtsi @@ -124,6 +124,15 @@ clocks { clock-output-names = "chipclk13"; }; + paclk13: paclk13 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&papllclk>; + clock-div = <3>; + clock-mult = <1>; + clock-output-names = "paclk13"; + }; + chipclk14: chipclk14 { #clock-cells = <0>; compatible = "fixed-factor-clock"; -- cgit v1.1 From a18b4aa2a061b146c018f9ebd3e0a8bb35445e57 Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Sat, 9 Nov 2013 14:33:13 -0500 Subject: ARM: dts: keystone: Add the GICV and GICH address space Update the Keystone gic node to add the GICV and GIGH address space needed by the KVM. Cc: Marc Zyngier Cc: Christoffer Dall Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/keystone.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi index c01c6fb..00ce8f3 100644 --- a/arch/arm/boot/dts/keystone.dtsi +++ b/arch/arm/boot/dts/keystone.dtsi @@ -62,7 +62,9 @@ #address-cells = <1>; interrupt-controller; reg = <0x0 0x02561000 0x0 0x1000>, - <0x0 0x02562000 0x0 0x2000>; + <0x0 0x02562000 0x0 0x2000>, + <0x0 0x02564000 0x0 0x1000>, + <0x0 0x02566000 0x0 0x2000>; }; timer { -- cgit v1.1 From 0ee154443b9906a792b0b32a5b897947bb90c827 Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Sat, 9 Nov 2013 14:36:00 -0500 Subject: ARM: dts: keystone: Add guestos maintenance interrupt Update the Keystone gic device tree entry to add the maintenance interrupt information. Cc: Marc Zyngier Cc: Christoffer Dall Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/keystone.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi index 00ce8f3..f6d6d9e 100644 --- a/arch/arm/boot/dts/keystone.dtsi +++ b/arch/arm/boot/dts/keystone.dtsi @@ -65,6 +65,8 @@ <0x0 0x02562000 0x0 0x2000>, <0x0 0x02564000 0x0 0x1000>, <0x0 0x02566000 0x0 0x2000>; + interrupts = ; }; timer { -- cgit v1.1 From 08c36762db9a0223a5477441bd93650b474aa9c8 Mon Sep 17 00:00:00 2001 From: WingMan Kwok Date: Mon, 9 Dec 2013 14:43:23 -0500 Subject: ARM: dts: keystone: Add usb phy devicetree bindings Added device tree support for TI's Keystone USB PHY driver and updated the Documentation with device tree binding information. Signed-off-by: WingMan Kwok Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/keystone.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi index f6d6d9e..276bea9 100644 --- a/arch/arm/boot/dts/keystone.dtsi +++ b/arch/arm/boot/dts/keystone.dtsi @@ -181,5 +181,13 @@ interrupts = ; clocks = <&clkspi>; }; + + usb_phy: usb_phy@2620738 { + compatible = "ti,keystone-usbphy"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2620738 32>; + status = "disabled"; + }; }; }; -- cgit v1.1 From 732079567da4942b7b4929deff8f236926d0b3eb Mon Sep 17 00:00:00 2001 From: WingMan Kwok Date: Mon, 9 Dec 2013 17:25:12 -0500 Subject: ARM: dts: keystone: Add usb devicetree bindings Added device tree support for TI's Keystone USB driver and updated the Documentation with device tree binding information. Signed-off-by: WingMan Kwok Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/k2hk-evm.dts | 8 ++++++++ arch/arm/boot/dts/keystone.dtsi | 19 +++++++++++++++++++ 2 files changed, 27 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/k2hk-evm.dts b/arch/arm/boot/dts/k2hk-evm.dts index 15b3a95..eaefdfe 100644 --- a/arch/arm/boot/dts/k2hk-evm.dts +++ b/arch/arm/boot/dts/k2hk-evm.dts @@ -53,3 +53,11 @@ }; }; }; + +&usb_phy { + status = "okay"; +}; + +&usb { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi index 276bea9..b420290 100644 --- a/arch/arm/boot/dts/keystone.dtsi +++ b/arch/arm/boot/dts/keystone.dtsi @@ -189,5 +189,24 @@ reg = <0x2620738 32>; status = "disabled"; }; + + usb: usb@2680000 { + compatible = "ti,keystone-dwc3"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2680000 0x10000>; + clocks = <&clkusb>; + clock-names = "usb"; + interrupts = ; + ranges; + status = "disabled"; + + dwc3@2690000 { + compatible = "synopsys,dwc3"; + reg = <0x2690000 0x70000>; + interrupts = ; + usb-phy = <&usb_phy>, <&usb_phy>; + }; + }; }; }; -- cgit v1.1 From c06551eedeea305be57cfa756cff03c2d4337179 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 3 Dec 2013 14:28:04 +0100 Subject: ARM: ux500: delete U8540 UART auxdata The other Ux500's does not need this anymore, and the U8540 certainly is no different. Cc: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/mach-ux500/cpu-db8500.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index 840452b..75ce3b1 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c @@ -170,10 +170,6 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = { }; static struct of_dev_auxdata u8540_auxdata_lookup[] __initdata = { - /* Requires DMA bindings. */ - OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", NULL), - OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", NULL), - OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", NULL), OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu", &db8500_prcmu_pdata), {}, -- cgit v1.1 From a987a3accc06b290f49f731260474dfdbf2b6af6 Mon Sep 17 00:00:00 2001 From: Ulf Hansson Date: Thu, 12 Dec 2013 14:31:36 +0100 Subject: ARM: ux500: Refactor common DT configs for sdi[n] devices Remove duplicated configurations and move specific details into each corresponding dtsi file for the href versions. Cc: Lee Jones Cc: devicetree@vger.kernel.org Signed-off-by: Ulf Hansson Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-href.dtsi | 2 -- arch/arm/boot/dts/ste-hrefprev60.dtsi | 5 +++++ arch/arm/boot/dts/ste-hrefv60plus.dtsi | 39 ---------------------------------- 3 files changed, 5 insertions(+), 41 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi index e282421..0c1e8d8 100644 --- a/arch/arm/boot/dts/ste-href.dtsi +++ b/arch/arm/boot/dts/ste-href.dtsi @@ -124,8 +124,6 @@ pinctrl-0 = <&sdi0_default_mode>; pinctrl-1 = <&sdi0_sleep_mode>; - cd-gpios = <&tc3589x_gpio 3 0x4>; - status = "okay"; }; diff --git a/arch/arm/boot/dts/ste-hrefprev60.dtsi b/arch/arm/boot/dts/ste-hrefprev60.dtsi index b0f5def..af9914e 100644 --- a/arch/arm/boot/dts/ste-hrefprev60.dtsi +++ b/arch/arm/boot/dts/ste-hrefprev60.dtsi @@ -60,6 +60,11 @@ pinctrl-0 = <&ssp0_hrefprev60_mode>; }; + // External Micro SD slot + sdi0_per1@80126000 { + cd-gpios = <&tc3589x_gpio 3 0x4>; + }; + vmmci: regulator-gpio { gpios = <&tc3589x_gpio 18 0x4>; enable-gpio = <&tc3589x_gpio 17 0x4>; diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dtsi b/arch/arm/boot/dts/ste-hrefv60plus.dtsi index 941bf9a..1f7b46b 100644 --- a/arch/arm/boot/dts/ste-hrefv60plus.dtsi +++ b/arch/arm/boot/dts/ste-hrefv60plus.dtsi @@ -19,46 +19,7 @@ soc { // External Micro SD slot sdi0_per1@80126000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <4>; - mmc-cap-sd-highspeed; - mmc-cap-mmc-highspeed; - vmmc-supply = <&ab8500_ldo_aux3_reg>; - cd-gpios = <&gpio2 31 0x4>; // 95 - - status = "okay"; - }; - - // WLAN SDIO channel - sdi1_per2@80118000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <4>; - - status = "okay"; - }; - - // PoP:ed eMMC - sdi2_per3@80005000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <8>; - mmc-cap-mmc-highspeed; - - status = "okay"; - }; - - // On-board eMMC - sdi4_per2@80114000 { - arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; - bus-width = <8>; - mmc-cap-mmc-highspeed; - vmmc-supply = <&ab8500_ldo_aux2_reg>; - - status = "okay"; }; pinctrl { -- cgit v1.1 From a1ab5e4c8073ed5ba76bc08de4bb976a1171a37f Mon Sep 17 00:00:00 2001 From: Ulf Hansson Date: Thu, 12 Dec 2013 14:31:37 +0100 Subject: ARM: ux500: Configure regulator for I/O voltage for SD-card slot To be able to enable SDR12|25 for SD-cards, we needed to fixup the configuration in DT of the gpio regulator, which handles the signal voltage level. Some configuration were missing and some were wrong. Cc: Lee Jones Cc: devicetree@vger.kernel.org Signed-off-by: Ulf Hansson Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-hrefprev60.dtsi | 2 -- arch/arm/boot/dts/ste-hrefv60plus.dtsi | 5 +++++ arch/arm/boot/dts/ste-snowball.dts | 6 ++---- 3 files changed, 7 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/ste-hrefprev60.dtsi b/arch/arm/boot/dts/ste-hrefprev60.dtsi index af9914e..40f0ecd 100644 --- a/arch/arm/boot/dts/ste-hrefprev60.dtsi +++ b/arch/arm/boot/dts/ste-hrefprev60.dtsi @@ -68,8 +68,6 @@ vmmci: regulator-gpio { gpios = <&tc3589x_gpio 18 0x4>; enable-gpio = <&tc3589x_gpio 17 0x4>; - - status = "okay"; }; pinctrl { diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dtsi b/arch/arm/boot/dts/ste-hrefv60plus.dtsi index 1f7b46b..3b6d118 100644 --- a/arch/arm/boot/dts/ste-hrefv60plus.dtsi +++ b/arch/arm/boot/dts/ste-hrefv60plus.dtsi @@ -22,6 +22,11 @@ cd-gpios = <&gpio2 31 0x4>; // 95 }; + vmmci: regulator-gpio { + gpios = <&gpio0 5 0x4>; + enable-gpio = <&gpio5 9 0x4>; + }; + pinctrl { /* * Set this up using hogs, as time goes by and as seems fit, these diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts index 9070c37..97d5d21 100644 --- a/arch/arm/boot/dts/ste-snowball.dts +++ b/arch/arm/boot/dts/ste-snowball.dts @@ -146,10 +146,8 @@ }; vmmci: regulator-gpio { - gpios = <&gpio6 25 0x4>; - enable-gpio = <&gpio7 4 0x4>; - - status = "okay"; + gpios = <&gpio7 4 0x4>; + enable-gpio = <&gpio6 25 0x4>; }; // External Micro SD slot -- cgit v1.1 From 0e7a268a9e2d85d36f146f9dcf1f54488111f3d8 Mon Sep 17 00:00:00 2001 From: Ulf Hansson Date: Fri, 13 Dec 2013 09:31:33 +0100 Subject: ARM: ux500: regulators: Remove dead code for SD-card regulator The signal-voltage regulator is handled through a gpio regulator configured in DT. Remove the old dead code. Cc: Lee Jones Signed-off-by: Ulf Hansson Signed-off-by: Linus Walleij --- arch/arm/mach-ux500/board-mop500-regulators.c | 14 -------------- arch/arm/mach-ux500/board-mop500-regulators.h | 1 - 2 files changed, 15 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c index 0dc44c6..a4e139a 100644 --- a/arch/arm/mach-ux500/board-mop500-regulators.c +++ b/arch/arm/mach-ux500/board-mop500-regulators.c @@ -30,20 +30,6 @@ struct regulator_init_data gpio_en_3v3_regulator = { .consumer_supplies = gpio_en_3v3_consumers, }; -static struct regulator_consumer_supply sdi0_reg_consumers[] = { - REGULATOR_SUPPLY("vqmmc", "sdi0"), -}; - -struct regulator_init_data sdi0_reg_init_data = { - .constraints = { - .min_uV = 1800000, - .max_uV = 2900000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE|REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(sdi0_reg_consumers), - .consumer_supplies = sdi0_reg_consumers, -}; - /* * TPS61052 regulator */ diff --git a/arch/arm/mach-ux500/board-mop500-regulators.h b/arch/arm/mach-ux500/board-mop500-regulators.h index 039f513..9bece38 100644 --- a/arch/arm/mach-ux500/board-mop500-regulators.h +++ b/arch/arm/mach-ux500/board-mop500-regulators.h @@ -18,7 +18,6 @@ extern struct ab8500_regulator_platform_data ab8500_regulator_plat_data; extern struct ab8500_regulator_platform_data ab8505_regulator_plat_data; extern struct regulator_init_data tps61052_regulator; extern struct regulator_init_data gpio_en_3v3_regulator; -extern struct regulator_init_data sdi0_reg_init_data; void mop500_regulator_init(void); -- cgit v1.1 From 2e38b946dc54a46eaa1ab8ee1ab994a87430af9a Mon Sep 17 00:00:00 2001 From: KV Sujith Date: Thu, 21 Nov 2013 23:45:30 +0530 Subject: ARM: davinci: da850: add GPIO DT node Add DT node for Davinci GPIO driver. Signed-off-by: KV Sujith Signed-off-by: Philip Avinash Signed-off-by: Lad, Prabhakar Signed-off-by: Sekhar Nori --- arch/arm/boot/dts/da850.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi index 8d17346..b695548 100644 --- a/arch/arm/boot/dts/da850.dtsi +++ b/arch/arm/boot/dts/da850.dtsi @@ -8,6 +8,7 @@ * option) any later version. */ #include "skeleton.dtsi" +#include / { arm { @@ -256,6 +257,19 @@ 36 >; }; + gpio: gpio@1e26000 { + compatible = "ti,dm6441-gpio"; + gpio-controller; + reg = <0x226000 0x1000>; + interrupts = <42 IRQ_TYPE_EDGE_BOTH + 43 IRQ_TYPE_EDGE_BOTH 44 IRQ_TYPE_EDGE_BOTH + 45 IRQ_TYPE_EDGE_BOTH 46 IRQ_TYPE_EDGE_BOTH + 47 IRQ_TYPE_EDGE_BOTH 48 IRQ_TYPE_EDGE_BOTH + 49 IRQ_TYPE_EDGE_BOTH 50 IRQ_TYPE_EDGE_BOTH>; + ti,ngpio = <144>; + ti,davinci-gpio-unbanked = <0>; + status = "disabled"; + }; }; nand_cs3@62000000 { compatible = "ti,davinci-nand"; -- cgit v1.1 From 3a9574f2aa4ffd9b867321a1f298893410bd3718 Mon Sep 17 00:00:00 2001 From: KV Sujith Date: Thu, 21 Nov 2013 23:45:31 +0530 Subject: ARM: davinci: da850 evm: add GPIO pinumux entries DT node Add GPIO DT node and pinmux entries for DA850 EVM. GPIO is configurable differently on different boards. So add GPIO pinmuxing in dts file. Signed-off-by: KV Sujith Signed-off-by: Philip Avinash Signed-off-by: Lad, Prabhakar Signed-off-by: Sekhar Nori --- arch/arm/boot/dts/da850-evm.dts | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts index 588ce58..1e11e5a 100644 --- a/arch/arm/boot/dts/da850-evm.dts +++ b/arch/arm/boot/dts/da850-evm.dts @@ -101,6 +101,9 @@ pinctrl-names = "default"; pinctrl-0 = <&mii_pins>; }; + gpio: gpio@1e26000 { + status = "okay"; + }; }; nand_cs3@62000000 { status = "okay"; -- cgit v1.1 From e908d5c5dc3b9258449b3c4d926e347c4247ce09 Mon Sep 17 00:00:00 2001 From: Yuvaraj Kumar C D Date: Mon, 21 Oct 2013 05:48:06 +0900 Subject: ARM: dts: change status property of dwmmc nodes for exynos5250 According to ePAPR, chapter 2.3.4, the status property has defined that it should be set to "disabled" when "the device is not presently operational, but it might become operational in the future". So this patch disable dwmmc node by "status = disabled" in SOC dts file and enable dwmmc node by "status = okay" in board specific dts file. Signed-off-by: Yuvaraj Kumar C D Reviewed-by: Tomasz Figa Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5250-arndale.dts | 10 ++-------- arch/arm/boot/dts/exynos5250-smdk5250.dts | 10 ++-------- arch/arm/boot/dts/exynos5250.dtsi | 4 ++++ 3 files changed, 8 insertions(+), 16 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index 6845270..18e3e93 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -385,6 +385,7 @@ }; dwmmc_0: dwmmc0@12200000 { + status = "okay"; num-slots = <1>; supports-highspeed; broken-cd; @@ -403,11 +404,8 @@ }; }; - dwmmc_1: dwmmc1@12210000 { - status = "disabled"; - }; - dwmmc_2: dwmmc2@12220000 { + status = "okay"; num-slots = <1>; supports-highspeed; fifo-depth = <0x80>; @@ -426,10 +424,6 @@ }; }; - dwmmc_3: dwmmc3@12230000 { - status = "disabled"; - }; - i2s0: i2s@03830000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index f86d567..78ecc75 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -141,6 +141,7 @@ }; dwmmc0@12200000 { + status = "okay"; num-slots = <1>; supports-highspeed; broken-cd; @@ -158,11 +159,8 @@ }; }; - dwmmc1@12210000 { - status = "disabled"; - }; - dwmmc2@12220000 { + status = "okay"; num-slots = <1>; supports-highspeed; fifo-depth = <0x80>; @@ -180,10 +178,6 @@ }; }; - dwmmc3@12230000 { - status = "disabled"; - }; - spi_0: spi@12d20000 { status = "disabled"; }; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index e613da1..2507281 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -400,6 +400,7 @@ reg = <0x12200000 0x1000>; clocks = <&clock 280>, <&clock 139>; clock-names = "biu", "ciu"; + status = "disabled"; }; dwmmc_1: dwmmc1@12210000 { @@ -410,6 +411,7 @@ reg = <0x12210000 0x1000>; clocks = <&clock 281>, <&clock 140>; clock-names = "biu", "ciu"; + status = "disabled"; }; dwmmc_2: dwmmc2@12220000 { @@ -420,6 +422,7 @@ reg = <0x12220000 0x1000>; clocks = <&clock 282>, <&clock 141>; clock-names = "biu", "ciu"; + status = "disabled"; }; dwmmc_3: dwmmc3@12230000 { @@ -430,6 +433,7 @@ #size-cells = <0>; clocks = <&clock 283>, <&clock 142>; clock-names = "biu", "ciu"; + status = "disabled"; }; i2s0: i2s@03830000 { -- cgit v1.1 From 46285a90f21541539164e06963c3069a91c9963f Mon Sep 17 00:00:00 2001 From: Yuvaraj Kumar C D Date: Mon, 21 Oct 2013 05:48:11 +0900 Subject: ARM: dts: Move fifo-depth property from exynos5250 board dts As fifo-depth property in dw_mmc device tree node is SOC specific, move this property to exynos5250 SOC specific file. Signed-off-by: Yuvaraj Kumar C D Reviewed-by: Tomasz Figa [kgene.kim@samsung.com: squashed fifo-depth patch for cros5250-common] Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/cros5250-common.dtsi | 3 --- arch/arm/boot/dts/exynos5250-arndale.dts | 2 -- arch/arm/boot/dts/exynos5250-smdk5250.dts | 2 -- arch/arm/boot/dts/exynos5250.dtsi | 4 ++++ 4 files changed, 4 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/cros5250-common.dtsi b/arch/arm/boot/dts/cros5250-common.dtsi index dc259e8b..a18833d 100644 --- a/arch/arm/boot/dts/cros5250-common.dtsi +++ b/arch/arm/boot/dts/cros5250-common.dtsi @@ -233,7 +233,6 @@ num-slots = <1>; supports-highspeed; broken-cd; - fifo-depth = <0x80>; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; @@ -254,7 +253,6 @@ dwmmc2@12220000 { num-slots = <1>; supports-highspeed; - fifo-depth = <0x80>; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; @@ -273,7 +271,6 @@ num-slots = <1>; supports-highspeed; broken-cd; - fifo-depth = <0x80>; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index 18e3e93..169a13a 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -389,7 +389,6 @@ num-slots = <1>; supports-highspeed; broken-cd; - fifo-depth = <0x80>; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; @@ -408,7 +407,6 @@ status = "okay"; num-slots = <1>; supports-highspeed; - fifo-depth = <0x80>; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 78ecc75..ae1562f 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -145,7 +145,6 @@ num-slots = <1>; supports-highspeed; broken-cd; - fifo-depth = <0x80>; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; @@ -163,7 +162,6 @@ status = "okay"; num-slots = <1>; supports-highspeed; - fifo-depth = <0x80>; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 2507281..0f8c0bd 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -400,6 +400,7 @@ reg = <0x12200000 0x1000>; clocks = <&clock 280>, <&clock 139>; clock-names = "biu", "ciu"; + fifo-depth = <0x80>; status = "disabled"; }; @@ -411,6 +412,7 @@ reg = <0x12210000 0x1000>; clocks = <&clock 281>, <&clock 140>; clock-names = "biu", "ciu"; + fifo-depth = <0x80>; status = "disabled"; }; @@ -422,6 +424,7 @@ reg = <0x12220000 0x1000>; clocks = <&clock 282>, <&clock 141>; clock-names = "biu", "ciu"; + fifo-depth = <0x80>; status = "disabled"; }; @@ -433,6 +436,7 @@ #size-cells = <0>; clocks = <&clock 283>, <&clock 142>; clock-names = "biu", "ciu"; + fifo-depth = <0x80>; status = "disabled"; }; -- cgit v1.1 From c8149df0f3bad21c27fb6289e5408e8c7ff9c817 Mon Sep 17 00:00:00 2001 From: Yuvaraj Kumar C D Date: Mon, 21 Oct 2013 05:48:16 +0900 Subject: ARM: dts: rename mmc dts node for exynos5 series This patch rename's the device tree mmc node's from "dwmmc" to "mmc". According to ePAPR chapter 2.2.2 generic node name recommendation, it has been opted change from dwmmc to mmc.Also this patch remove the instance index from the node name. Signed-off-by: Yuvaraj Kumar C D Reviewed-by: Tomasz Figa Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/cros5250-common.dtsi | 8 ++++---- arch/arm/boot/dts/exynos5250-arndale.dts | 4 ++-- arch/arm/boot/dts/exynos5250-smdk5250.dts | 4 ++-- arch/arm/boot/dts/exynos5250-snow.dts | 2 +- arch/arm/boot/dts/exynos5250.dtsi | 16 ++++++++-------- 5 files changed, 17 insertions(+), 17 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/cros5250-common.dtsi b/arch/arm/boot/dts/cros5250-common.dtsi index a18833d..03cb897 100644 --- a/arch/arm/boot/dts/cros5250-common.dtsi +++ b/arch/arm/boot/dts/cros5250-common.dtsi @@ -229,7 +229,7 @@ }; }; - dwmmc0@12200000 { + mmc@12200000 { num-slots = <1>; supports-highspeed; broken-cd; @@ -246,11 +246,11 @@ }; }; - dwmmc1@12210000 { + mmc@12210000 { status = "disabled"; }; - dwmmc2@12220000 { + mmc@12220000 { num-slots = <1>; supports-highspeed; card-detect-delay = <200>; @@ -267,7 +267,7 @@ }; }; - dwmmc3@12230000 { + mmc@12230000 { num-slots = <1>; supports-highspeed; broken-cd; diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index 169a13a..b77a37e 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -384,7 +384,7 @@ status = "disabled"; }; - dwmmc_0: dwmmc0@12200000 { + mmc_0: mmc@12200000 { status = "okay"; num-slots = <1>; supports-highspeed; @@ -403,7 +403,7 @@ }; }; - dwmmc_2: dwmmc2@12220000 { + mmc_2: mmc@12220000 { status = "okay"; num-slots = <1>; supports-highspeed; diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index ae1562f..13746df 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -140,7 +140,7 @@ }; }; - dwmmc0@12200000 { + mmc@12200000 { status = "okay"; num-slots = <1>; supports-highspeed; @@ -158,7 +158,7 @@ }; }; - dwmmc2@12220000 { + mmc@12220000 { status = "okay"; num-slots = <1>; supports-highspeed; diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts index fd711e2..a9395c4 100644 --- a/arch/arm/boot/dts/exynos5250-snow.dts +++ b/arch/arm/boot/dts/exynos5250-snow.dts @@ -175,7 +175,7 @@ * On Snow we've got SIP WiFi and so can keep drive strengths low to * reduce EMI. */ - dwmmc3@12230000 { + mmc@12230000 { slot@0 { pinctrl-names = "default"; pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 0f8c0bd..b98ffc3 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -33,10 +33,10 @@ gsc1 = &gsc_1; gsc2 = &gsc_2; gsc3 = &gsc_3; - mshc0 = &dwmmc_0; - mshc1 = &dwmmc_1; - mshc2 = &dwmmc_2; - mshc3 = &dwmmc_3; + mshc0 = &mmc_0; + mshc1 = &mmc_1; + mshc2 = &mmc_2; + mshc3 = &mmc_3; i2c0 = &i2c_0; i2c1 = &i2c_1; i2c2 = &i2c_2; @@ -392,7 +392,7 @@ pinctrl-0 = <&spi2_bus>; }; - dwmmc_0: dwmmc0@12200000 { + mmc_0: mmc@12200000 { compatible = "samsung,exynos5250-dw-mshc"; interrupts = <0 75 0>; #address-cells = <1>; @@ -404,7 +404,7 @@ status = "disabled"; }; - dwmmc_1: dwmmc1@12210000 { + mmc_1: mmc@12210000 { compatible = "samsung,exynos5250-dw-mshc"; interrupts = <0 76 0>; #address-cells = <1>; @@ -416,7 +416,7 @@ status = "disabled"; }; - dwmmc_2: dwmmc2@12220000 { + mmc_2: mmc@12220000 { compatible = "samsung,exynos5250-dw-mshc"; interrupts = <0 77 0>; #address-cells = <1>; @@ -428,7 +428,7 @@ status = "disabled"; }; - dwmmc_3: dwmmc3@12230000 { + mmc_3: mmc@12230000 { compatible = "samsung,exynos5250-dw-mshc"; reg = <0x12230000 0x1000>; interrupts = <0 78 0>; -- cgit v1.1 From 0e2c5915911253bf92eca5a228da4535934b6c58 Mon Sep 17 00:00:00 2001 From: Yuvaraj Kumar C D Date: Mon, 21 Oct 2013 05:57:00 +0900 Subject: ARM: dts: Add dwmmc DT nodes for exynos5420 SOC This patch adds the mmc device tree node entries for exynos5420 SOC. Exynos5420 has a different version of DWMMC controller,so a new compatible string is used to distinguish it from the prior SOC's. Signed-off-by: Yuvaraj Kumar C D Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5420-smdk5420.dts | 33 ++++++++++++++++++++++++++ arch/arm/boot/dts/exynos5420.dtsi | 39 +++++++++++++++++++++++++++++++ 2 files changed, 72 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts index 79524c7..fb5a1e2 100644 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts @@ -31,6 +31,39 @@ }; }; + mmc@12200000 { + status = "okay"; + broken-cd; + supports-highspeed; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <0 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; + + slot@0 { + reg = <0>; + bus-width = <8>; + }; + }; + + mmc@12220000 { + status = "okay"; + supports-highspeed; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; + + slot@0 { + reg = <0>; + bus-width = <4>; + }; + }; + dp-controller@145B0000 { pinctrl-names = "default"; pinctrl-0 = <&dp_hpd>; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 09aa06c..3ac3afe 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -22,6 +22,9 @@ compatible = "samsung,exynos5420"; aliases { + mshc0 = &mmc_0; + mshc1 = &mmc_1; + mshc2 = &mmc_2; pinctrl0 = &pinctrl_0; pinctrl1 = &pinctrl_1; pinctrl2 = &pinctrl_2; @@ -88,6 +91,42 @@ clock-names = "mfc"; }; + mmc_0: mmc@12200000 { + compatible = "samsung,exynos5420-dw-mshc-smu"; + interrupts = <0 75 0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x12200000 0x2000>; + clocks = <&clock 351>, <&clock 132>; + clock-names = "biu", "ciu"; + fifo-depth = <0x40>; + status = "disabled"; + }; + + mmc_1: mmc@12210000 { + compatible = "samsung,exynos5420-dw-mshc-smu"; + interrupts = <0 76 0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x12210000 0x2000>; + clocks = <&clock 352>, <&clock 133>; + clock-names = "biu", "ciu"; + fifo-depth = <0x40>; + status = "disabled"; + }; + + mmc_2: mmc@12220000 { + compatible = "samsung,exynos5420-dw-mshc"; + interrupts = <0 77 0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x12220000 0x1000>; + clocks = <&clock 353>, <&clock 134>; + clock-names = "biu", "ciu"; + fifo-depth = <0x40>; + status = "disabled"; + }; + mct@101C0000 { compatible = "samsung,exynos4210-mct"; reg = <0x101C0000 0x800>; -- cgit v1.1 From 01eb46364104925e6f3e66e05203882a519f2c79 Mon Sep 17 00:00:00 2001 From: Leela Krishna Amudala Date: Mon, 21 Oct 2013 05:59:06 +0900 Subject: ARM: dts: Add device nodes for GScaler blocks for exynos5420 Adds G-Scaler device nodes to the DT device list Signed-off-by: Leela Krishna Amudala Reviewed-by: Tomasz Figa Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5420.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 3ac3afe..6ffefd1 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -34,6 +34,8 @@ i2c1 = &i2c_1; i2c2 = &i2c_2; i2c3 = &i2c_3; + gsc0 = &gsc_0; + gsc1 = &gsc_1; }; cpus { @@ -349,4 +351,22 @@ clocks = <&clock 431>, <&clock 143>; clock-names = "mixer", "sclk_hdmi"; }; + + gsc_0: video-scaler@13e00000 { + compatible = "samsung,exynos5-gsc"; + reg = <0x13e00000 0x1000>; + interrupts = <0 85 0>; + clocks = <&clock 465>; + clock-names = "gscl"; + samsung,power-domain = <&gsc_pd>; + }; + + gsc_1: video-scaler@13e10000 { + compatible = "samsung,exynos5-gsc"; + reg = <0x13e10000 0x1000>; + interrupts = <0 86 0>; + clocks = <&clock 466>; + clock-names = "gscl"; + samsung,power-domain = <&gsc_pd>; + }; }; -- cgit v1.1 From 6c16dedfd4c49c6a7f410f171c6da3116834a23d Mon Sep 17 00:00:00 2001 From: Chander Kashyap Date: Mon, 2 Dec 2013 07:48:23 +0900 Subject: clocksource: mct: extend mct to support 8 local interrupts for Exynos5420 Exynos5420 is octa-core SoC from Samsung. Hence extend exynos-mct clocksource driver to support 8 local interrupts. Also extend dts entries for 8 interrupts. Signed-off-by: Chander Kashyap Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5420.dtsi | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 6ffefd1..f909d82 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -135,7 +135,8 @@ interrupt-controller; #interrups-cells = <1>; interrupt-parent = <&mct_map>; - interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>; + interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, + <8>, <9>, <10>, <11>; clocks = <&clock 1>, <&clock 315>; clock-names = "fin_pll", "mct"; @@ -150,7 +151,11 @@ <4 &gic 0 120 0>, <5 &gic 0 121 0>, <6 &gic 0 122 0>, - <7 &gic 0 123 0>; + <7 &gic 0 123 0>, + <8 &gic 0 128 0>, + <9 &gic 0 129 0>, + <10 &gic 0 130 0>, + <11 &gic 0 131 0>; }; }; -- cgit v1.1 From 1c0e085444dd8adfd93945f693f11fa43b215603 Mon Sep 17 00:00:00 2001 From: Chander Kashyap Date: Mon, 2 Dec 2013 07:49:59 +0900 Subject: ARM: dts: populate cpu node entries to 8 cpus for exynos5420 Exynos5420 is octa-core SoC from Samsung. Hence populate all the CPU node entries. Signed-off-by: Chander Kashyap Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5420.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index f909d82..b1fa334 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -69,6 +69,34 @@ reg = <0x3>; clock-frequency = <1800000000>; }; + + cpu4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x100>; + clock-frequency = <1000000000>; + }; + + cpu5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x101>; + clock-frequency = <1000000000>; + }; + + cpu6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x102>; + clock-frequency = <1000000000>; + }; + + cpu7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x103>; + clock-frequency = <1000000000>; + }; }; clock: clock-controller@10010000 { -- cgit v1.1 From bb28205adeb835f6cd0cdd78d0d03083bdd97c02 Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Thu, 12 Dec 2013 06:51:39 +0900 Subject: ARM: dts: Update min voltage for vdd_arm on Arndale The minimum recommended ARM voltage for Exynos5250 at 200MHz on Arndale board is 0.9125V. Update accordingly. Signed-off-by: Sachin Kamat Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5250-arndale.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index b77a37e..9322652 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -266,7 +266,7 @@ buck2_reg: BUCK2 { regulator-name = "vdd_arm"; - regulator-min-microvolt = <925000>; + regulator-min-microvolt = <912500>; regulator-max-microvolt = <1300000>; regulator-always-on; regulator-boot-on; -- cgit v1.1 From 1a9110d6ddaa4e4533b71ed178b1e1e8b894ab91 Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Thu, 12 Dec 2013 07:01:11 +0900 Subject: ARM: dts: Add hs-i2c nodes to exynos5420 Added high speed I2C nodes to Exynos5420 DT file. Signed-off-by: Sachin Kamat Reviewed-by: Tomasz Figa Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5420.dtsi | 98 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 98 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index b1fa334..76f4e0b 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -34,6 +34,13 @@ i2c1 = &i2c_1; i2c2 = &i2c_2; i2c3 = &i2c_3; + i2c4 = &hsi2c_4; + i2c5 = &hsi2c_5; + i2c6 = &hsi2c_6; + i2c7 = &hsi2c_7; + i2c8 = &hsi2c_8; + i2c9 = &hsi2c_9; + i2c10 = &hsi2c_10; gsc0 = &gsc_0; gsc1 = &gsc_1; }; @@ -366,6 +373,97 @@ status = "disabled"; }; + hsi2c_4: i2c@12CA0000 { + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12CA0000 0x1000>; + interrupts = <0 60 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_hs_bus>; + clocks = <&clock 265>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_5: i2c@12CB0000 { + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12CB0000 0x1000>; + interrupts = <0 61 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_hs_bus>; + clocks = <&clock 266>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_6: i2c@12CC0000 { + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12CC0000 0x1000>; + interrupts = <0 62 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_hs_bus>; + clocks = <&clock 267>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_7: i2c@12CD0000 { + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12CD0000 0x1000>; + interrupts = <0 63 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_hs_bus>; + clocks = <&clock 268>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_8: i2c@12E00000 { + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12E00000 0x1000>; + interrupts = <0 87 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_hs_bus>; + clocks = <&clock 281>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_9: i2c@12E10000 { + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12E10000 0x1000>; + interrupts = <0 88 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c9_hs_bus>; + clocks = <&clock 282>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_10: i2c@12E20000 { + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12E20000 0x1000>; + interrupts = <0 203 0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c10_hs_bus>; + clocks = <&clock 283>; + clock-names = "hsi2c"; + status = "disabled"; + }; + hdmi@14530000 { compatible = "samsung,exynos4212-hdmi"; reg = <0x14530000 0x70000>; -- cgit v1.1 From 9f052d0c5fcabbe4ece6cf166502127d2a0b8c5c Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Thu, 12 Dec 2013 07:39:18 +0900 Subject: ARM: dts: Fix sysreg node name in exynos4.dtsi Fix the name as per DT node naming convention. - rename the node to syscon which is a more generic name. - append the register value to the node name. Signed-off-by: Sachin Kamat Reviewed-by: Tomasz Figa Reviewed-by: Sylwester Nawrocki Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos4.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index a73eeb5..c2a9964 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -99,7 +99,7 @@ reg = <0x10440000 0x1000>; }; - sys_reg: sysreg { + sys_reg: syscon@10010000 { compatible = "samsung,exynos4-sysreg", "syscon"; reg = <0x10010000 0x400>; }; -- cgit v1.1 From 52e86b37b1d3f7c02938def3a036e0bb0f723964 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sun, 15 Dec 2013 20:23:36 +0100 Subject: ARM: dts: sun5i: Add new sun5i-a13-olinuxino-micro board The A13-OLinuXino-MICRO is a small dev-board with the Allwinner A13 SoC: https://www.olimex.com/Products/OLinuXino/A13/A13-OLinuXino-MICRO/ Features: A13 Cortex A8 processor at 1GHz, 3D Mali400 GPU 256 MB RAM (128Mbit x 16) 5VDC input power supply with own ICs, noise immune design 1 USB host 1 USB OTG which can power the board SD-card connector for booting the Linux image VGA video output LCD signals available on connector so you still can use LCD if you disable VGA/HDMI Audio output Microphone input pads (no connector) Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts | 68 +++++++++++++++++++++++++ 2 files changed, 69 insertions(+) create mode 100644 arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts (limited to 'arch') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index d57c1a6..b663ed7 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -255,6 +255,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += \ sun4i-a10-hackberry.dtb \ sun5i-a10s-olinuxino-micro.dtb \ sun5i-a13-olinuxino.dtb \ + sun5i-a13-olinuxino-micro.dtb \ sun6i-a31-colombus.dtb \ sun7i-a20-cubieboard2.dtb \ sun7i-a20-cubietruck.dtb \ diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts new file mode 100644 index 0000000..fe2ce0a --- /dev/null +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts @@ -0,0 +1,68 @@ +/* + * Copyright 2012 Maxime Ripard + * Copyright 2013 Hans de Goede + * + * Maxime Ripard + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "sun5i-a13.dtsi" + +/ { + model = "Olimex A13-Olinuxino Micro"; + compatible = "olimex,a13-olinuxino-micro", "allwinner,sun5i-a13"; + + soc@01c00000 { + pinctrl@01c20800 { + led_pins_olinuxinom: led_pins@0 { + allwinner,pins = "PG9"; + allwinner,function = "gpio_out"; + allwinner,drive = <1>; + allwinner,pull = <0>; + }; + }; + + uart1: serial@01c28400 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins_b>; + status = "okay"; + }; + + i2c0: i2c@01c2ac00 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + }; + + i2c1: i2c@01c2b000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; + }; + + i2c2: i2c@01c2b400 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_olinuxinom>; + + power { + label = "a13-olinuxino-micro:green:power"; + gpios = <&pio 6 9 0>; + default-state = "on"; + }; + }; +}; -- cgit v1.1 From 81ee429ffdd021626bf191bb8a3ae886dd94adcc Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Sun, 3 Nov 2013 10:30:12 +0100 Subject: ARM: sun6i: dt: Add IP needed to bring up the additional cores Add the PRCM and CPU configuration units needed for SMP in the A31 DTSI. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 7e8d630..6dd9393 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -319,5 +319,15 @@ #interrupt-cells = <3>; interrupts = <1 9 0xf04>; }; + + cpucfg@01f01c00 { + compatible = "allwinner,sun6i-a31-cpuconfig"; + reg = <0x01f01c00 0x300>; + }; + + prcm@01f01c00 { + compatible = "allwinner,sun6i-a31-prcm"; + reg = <0x01f01400 0x200>; + }; }; }; -- cgit v1.1 From 58ecb23f64ee3a2ef66bb55b2e1e841385b6d08b Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 25 Nov 2013 17:53:16 -0700 Subject: ARM: tegra: add missing unit addresses to DT DT node names should include a unit address iff the node has a reg property. For Tegra DTs at least, we were previously applying a different rule, namely that node names only needed to include a unit address if it was required to make the node name unique. Consequently, many unit addresses are missing. Add them. Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra114-dalmore.dts | 18 +++++----- arch/arm/boot/dts/tegra114.dtsi | 24 ++++++------- arch/arm/boot/dts/tegra20-colibri-512.dtsi | 12 +++---- arch/arm/boot/dts/tegra20-harmony.dts | 14 ++++---- arch/arm/boot/dts/tegra20-iris-512.dts | 6 ++-- arch/arm/boot/dts/tegra20-medcom-wide.dts | 2 +- arch/arm/boot/dts/tegra20-paz00.dts | 12 +++---- arch/arm/boot/dts/tegra20-plutux.dts | 4 +-- arch/arm/boot/dts/tegra20-seaboard.dts | 12 +++---- arch/arm/boot/dts/tegra20-tamonten.dtsi | 12 +++---- arch/arm/boot/dts/tegra20-tec.dts | 6 ++-- arch/arm/boot/dts/tegra20-trimslice.dts | 12 +++---- arch/arm/boot/dts/tegra20-ventana.dts | 10 +++--- arch/arm/boot/dts/tegra20-whistler.dts | 14 ++++---- arch/arm/boot/dts/tegra20.dtsi | 54 +++++++++++++++--------------- arch/arm/boot/dts/tegra30-beaver.dts | 18 +++++----- arch/arm/boot/dts/tegra30-cardhu.dtsi | 12 +++---- arch/arm/boot/dts/tegra30.dtsi | 50 +++++++++++++-------------- 18 files changed, 146 insertions(+), 146 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index cb5ec23..5d2d6f6 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -11,7 +11,7 @@ reg = <0x80000000 0x40000000>; }; - pinmux { + pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -722,7 +722,7 @@ status = "okay"; clock-frequency = <100000>; - battery: smart-battery { + battery: smart-battery@b { compatible = "ti,bq20z45", "sbs,sbs-battery"; reg = <0xb>; battery-name = "battery"; @@ -731,7 +731,7 @@ power-supplies = <&charger>; }; - rt5640: rt5640 { + rt5640: rt5640@1c { compatible = "realtek,rt5640"; reg = <0x1c>; interrupt-parent = <&gpio>; @@ -753,7 +753,7 @@ status = "okay"; clock-frequency = <400000>; - tps51632 { + tps51632@43 { compatible = "ti,tps51632"; reg = <0x43>; regulator-name = "vdd-cpu"; @@ -763,7 +763,7 @@ regulator-always-on; }; - tps65090 { + tps65090@48 { compatible = "ti,tps65090"; reg = <0x48>; interrupt-parent = <&gpio>; @@ -846,7 +846,7 @@ }; }; - palmas: tps65913 { + palmas: tps65913@58 { compatible = "ti,palmas"; reg = <0x58>; interrupts = <0 86 IRQ_TYPE_LEVEL_LOW>; @@ -1046,7 +1046,7 @@ }; }; - pmc { + pmc@7000e400 { nvidia,invert-interrupt; nvidia,suspend-mode = <1>; nvidia,cpu-pwr-good-time = <500>; @@ -1057,7 +1057,7 @@ nvidia,sys-clock-req-active-high; }; - ahub { + ahub@70080000 { i2s@70080400 { status = "okay"; }; @@ -1089,7 +1089,7 @@ #address-cells = <1>; #size-cells = <0>; - clk32k_in: clock { + clk32k_in: clock@0 { compatible = "fixed-clock"; reg=<0>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 731249f..8fdf8d5 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -15,7 +15,7 @@ serial3 = &uartd; }; - gic: interrupt-controller { + gic: interrupt-controller@50041000 { compatible = "arm,cortex-a15-gic"; #interrupt-cells = <3>; interrupt-controller; @@ -39,14 +39,14 @@ clocks = <&tegra_car TEGRA114_CLK_TIMER>; }; - tegra_car: clock { + tegra_car: clock@60006000 { compatible = "nvidia,tegra114-car"; reg = <0x60006000 0x1000>; #clock-cells = <1>; #reset-cells = <1>; }; - apbdma: dma { + apbdma: dma@6000a000 { compatible = "nvidia,tegra114-apbdma"; reg = <0x6000a000 0x1400>; interrupts = , @@ -87,12 +87,12 @@ #dma-cells = <1>; }; - ahb: ahb { + ahb: ahb@6000c004 { compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb"; reg = <0x6000c004 0x14c>; }; - gpio: gpio { + gpio: gpio@6000d000 { compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio"; reg = <0x6000d000 0x1000>; interrupts = , @@ -109,7 +109,7 @@ interrupt-controller; }; - pinmux: pinmux { + pinmux: pinmux@70000868 { compatible = "nvidia,tegra114-pinmux"; reg = <0x70000868 0x148 /* Pad control registers */ 0x70003000 0x40c>; /* Mux registers */ @@ -175,7 +175,7 @@ status = "disabled"; }; - pwm: pwm { + pwm: pwm@7000a000 { compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm"; reg = <0x7000a000 0x100>; #pwm-cells = <2>; @@ -350,14 +350,14 @@ status = "disabled"; }; - rtc { + rtc@7000e000 { compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; reg = <0x7000e000 0x100>; interrupts = ; clocks = <&tegra_car TEGRA114_CLK_RTC>; }; - kbc { + kbc@7000e200 { compatible = "nvidia,tegra114-kbc"; reg = <0x7000e200 0x100>; interrupts = ; @@ -367,14 +367,14 @@ status = "disabled"; }; - pmc { + pmc@7000e400 { compatible = "nvidia,tegra114-pmc"; reg = <0x7000e400 0x400>; clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; }; - iommu { + iommu@70019010 { compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu"; reg = <0x70019010 0x02c 0x700191f0 0x010 @@ -385,7 +385,7 @@ nvidia,ahb = <&ahb>; }; - ahub { + ahub@70080000 { compatible = "nvidia,tegra114-ahub"; reg = <0x70080000 0x200>, <0x70080200 0x100>, diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi index d5c9bca..f20fc97 100644 --- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi @@ -8,8 +8,8 @@ reg = <0x00000000 0x20000000>; }; - host1x { - hdmi { + host1x@50000000 { + hdmi@54280000 { vdd-supply = <&hdmi_vdd_reg>; pll-supply = <&hdmi_pll_reg>; @@ -19,7 +19,7 @@ }; }; - pinmux { + pinmux@70000014 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -362,7 +362,7 @@ }; }; - pmc { + pmc@7000e400 { nvidia,suspend-mode = <1>; nvidia,cpu-pwr-good-time = <5000>; nvidia,cpu-pwr-off-time = <5000>; @@ -442,7 +442,7 @@ }; }; - ac97: ac97 { + ac97: ac97@70002000 { status = "okay"; nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_HIGH>; @@ -471,7 +471,7 @@ #address-cells = <1>; #size-cells = <0>; - clk32k_in: clock { + clk32k_in: clock@0 { compatible = "fixed-clock"; reg=<0>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index e156ab3..b9c6f67 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -10,8 +10,8 @@ reg = <0x00000000 0x40000000>; }; - host1x { - hdmi { + host1x@50000000 { + hdmi@54280000 { status = "okay"; vdd-supply = <&hdmi_vdd_reg>; @@ -23,7 +23,7 @@ }; }; - pinmux { + pinmux@70000014 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -415,7 +415,7 @@ }; }; - pmc { + pmc@7000e400 { nvidia,invert-interrupt; nvidia,suspend-mode = <1>; nvidia,cpu-pwr-good-time = <5000>; @@ -425,7 +425,7 @@ nvidia,sys-clock-req-active-high; }; - pcie-controller { + pcie-controller@80003000 { pex-clk-supply = <&pci_clk_reg>; vdd-supply = <&pci_vdd_reg>; status = "okay"; @@ -488,7 +488,7 @@ #address-cells = <1>; #size-cells = <0>; - clk32k_in: clock { + clk32k_in: clock@0 { compatible = "fixed-clock"; reg=<0>; #clock-cells = <0>; @@ -507,7 +507,7 @@ }; }; - kbc { + kbc@7000e200 { status = "okay"; nvidia,debounce-delay-ms = <2>; nvidia,repeat-delay-ms = <160>; diff --git a/arch/arm/boot/dts/tegra20-iris-512.dts b/arch/arm/boot/dts/tegra20-iris-512.dts index f2222bd..770fc66 100644 --- a/arch/arm/boot/dts/tegra20-iris-512.dts +++ b/arch/arm/boot/dts/tegra20-iris-512.dts @@ -6,13 +6,13 @@ model = "Toradex Colibri T20 512MB on Iris"; compatible = "toradex,iris", "toradex,colibri_t20-512", "nvidia,tegra20"; - host1x { - hdmi { + host1x@50000000 { + hdmi@54280000 { status = "okay"; }; }; - pinmux { + pinmux@70000014 { state_default: pinmux { hdint { nvidia,tristate = <0>; diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts index 7580578..6d3a4cb 100644 --- a/arch/arm/boot/dts/tegra20-medcom-wide.dts +++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts @@ -6,7 +6,7 @@ model = "Avionic Design Medcom-Wide board"; compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20"; - pwm { + pwm@7000a000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index e57fb3ae..4b961b1 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -10,8 +10,8 @@ reg = <0x00000000 0x20000000>; }; - host1x { - hdmi { + host1x@50000000 { + hdmi@54280000 { status = "okay"; vdd-supply = <&hdmi_vdd_reg>; @@ -23,7 +23,7 @@ }; }; - pinmux { + pinmux@70000014 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -268,7 +268,7 @@ clock-frequency = <100000>; }; - nvec { + nvec@7000c500 { compatible = "nvidia,nvec"; reg = <0x7000c500 0x100>; interrupts = ; @@ -417,7 +417,7 @@ }; }; - pmc { + pmc@7000e400 { nvidia,invert-interrupt; nvidia,suspend-mode = <1>; nvidia,cpu-pwr-good-time = <2000>; @@ -474,7 +474,7 @@ #address-cells = <1>; #size-cells = <0>; - clk32k_in: clock { + clk32k_in: clock@0 { compatible = "fixed-clock"; reg=<0>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts index d7a358a..29051a2 100644 --- a/arch/arm/boot/dts/tegra20-plutux.dts +++ b/arch/arm/boot/dts/tegra20-plutux.dts @@ -6,8 +6,8 @@ model = "Avionic Design Plutux board"; compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20"; - host1x { - hdmi { + host1x@50000000 { + hdmi@54280000 { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index 315aae2..01442fc 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -10,8 +10,8 @@ reg = <0x00000000 0x40000000>; }; - host1x { - hdmi { + host1x@50000000 { + hdmi@54280000 { status = "okay"; vdd-supply = <&hdmi_vdd_reg>; @@ -23,7 +23,7 @@ }; }; - pinmux { + pinmux@70000014 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -516,7 +516,7 @@ }; }; - pmc { + pmc@7000e400 { nvidia,invert-interrupt; nvidia,suspend-mode = <1>; nvidia,cpu-pwr-good-time = <5000>; @@ -621,7 +621,7 @@ #address-cells = <1>; #size-cells = <0>; - clk32k_in: clock { + clk32k_in: clock@0 { compatible = "fixed-clock"; reg=<0>; #clock-cells = <0>; @@ -649,7 +649,7 @@ }; }; - kbc { + kbc@7000e200 { status = "okay"; nvidia,debounce-delay-ms = <32>; nvidia,repeat-delay-ms = <160>; diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi index 7726dab..02dbc69 100644 --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -8,8 +8,8 @@ reg = <0x00000000 0x20000000>; }; - host1x { - hdmi { + host1x@50000000 { + hdmi@54280000 { vdd-supply = <&hdmi_vdd_reg>; pll-supply = <&hdmi_pll_reg>; @@ -19,7 +19,7 @@ }; }; - pinmux { + pinmux@70000014 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -457,7 +457,7 @@ }; }; - pmc { + pmc@7000e400 { nvidia,invert-interrupt; nvidia,suspend-mode = <1>; nvidia,cpu-pwr-good-time = <5000>; @@ -467,7 +467,7 @@ nvidia,sys-clock-req-active-high; }; - pcie-controller { + pcie-controller@80003000 { pex-clk-supply = <&pci_clk_reg>; vdd-supply = <&pci_vdd_reg>; }; @@ -492,7 +492,7 @@ #address-cells = <1>; #size-cells = <0>; - clk32k_in: clock { + clk32k_in: clock@0 { compatible = "fixed-clock"; reg=<0>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts index 3ada3cb..890562c 100644 --- a/arch/arm/boot/dts/tegra20-tec.dts +++ b/arch/arm/boot/dts/tegra20-tec.dts @@ -6,8 +6,8 @@ model = "Avionic Design Tamonten Evaluation Carrier"; compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20"; - host1x { - hdmi { + host1x@50000000 { + hdmi@54280000 { status = "okay"; }; }; @@ -32,7 +32,7 @@ }; }; - pcie-controller { + pcie-controller@80003000 { status = "okay"; pci@1,0 { diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index 78deea5..eab7cd2 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -10,8 +10,8 @@ reg = <0x00000000 0x40000000>; }; - host1x { - hdmi { + host1x@50000000 { + hdmi@54280000 { status = "okay"; vdd-supply = <&hdmi_vdd_reg>; @@ -23,7 +23,7 @@ }; }; - pinmux { + pinmux@70000014 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -301,7 +301,7 @@ }; }; - pmc { + pmc@7000e400 { nvidia,suspend-mode = <1>; nvidia,cpu-pwr-good-time = <5000>; nvidia,cpu-pwr-off-time = <5000>; @@ -310,7 +310,7 @@ nvidia,sys-clock-req-active-high; }; - pcie-controller { + pcie-controller@80003000 { status = "okay"; pex-clk-supply = <&pci_clk_reg>; vdd-supply = <&pci_vdd_reg>; @@ -366,7 +366,7 @@ #address-cells = <1>; #size-cells = <0>; - clk32k_in: clock { + clk32k_in: clock@0 { compatible = "fixed-clock"; reg=<0>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index aab872c..bce7640 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -10,8 +10,8 @@ reg = <0x00000000 0x40000000>; }; - host1x { - hdmi { + host1x@50000000 { + hdmi@54280000 { status = "okay"; vdd-supply = <&hdmi_vdd_reg>; @@ -23,7 +23,7 @@ }; }; - pinmux { + pinmux@70000014 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -492,7 +492,7 @@ }; }; - pmc { + pmc@7000e400 { nvidia,invert-interrupt; nvidia,suspend-mode = <1>; nvidia,cpu-pwr-good-time = <2000>; @@ -556,7 +556,7 @@ #address-cells = <1>; #size-cells = <0>; - clk32k_in: clock { + clk32k_in: clock@0 { compatible = "fixed-clock"; reg=<0>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts index d33a73cf..b047621 100644 --- a/arch/arm/boot/dts/tegra20-whistler.dts +++ b/arch/arm/boot/dts/tegra20-whistler.dts @@ -10,8 +10,8 @@ reg = <0x00000000 0x20000000>; }; - host1x { - hdmi { + host1x@50000000 { + hdmi@54280000 { status = "okay"; vdd-supply = <&hdmi_vdd_reg>; @@ -23,7 +23,7 @@ }; }; - pinmux { + pinmux@70000014 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -495,7 +495,7 @@ }; }; - pmc { + pmc@7000e400 { nvidia,invert-interrupt; nvidia,suspend-mode = <1>; nvidia,cpu-pwr-good-time = <2000>; @@ -543,7 +543,7 @@ #address-cells = <1>; #size-cells = <0>; - clk32k_in: clock { + clk32k_in: clock@0 { compatible = "fixed-clock"; reg=<0>; #clock-cells = <0>; @@ -551,7 +551,7 @@ }; }; - kbc { + kbc@7000e200 { status = "okay"; nvidia,debounce-delay-ms = <20>; nvidia,repeat-delay-ms = <160>; @@ -569,7 +569,7 @@ #address-cells = <1>; #size-cells = <0>; - usb0_vbus_reg: regulator { + usb0_vbus_reg: regulator@0 { compatible = "regulator-fixed"; reg = <0>; regulator-name = "usb0_vbus"; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index c90d0aa..648c494 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -16,7 +16,7 @@ serial4 = &uarte; }; - host1x { + host1x@50000000 { compatible = "nvidia,tegra20-host1x", "simple-bus"; reg = <0x50000000 0x00024000>; interrupts = , /* syncpt */ @@ -30,7 +30,7 @@ ranges = <0x54000000 0x54000000 0x04000000>; - mpe { + mpe@54040000 { compatible = "nvidia,tegra20-mpe"; reg = <0x54040000 0x00040000>; interrupts = ; @@ -39,7 +39,7 @@ reset-names = "mpe"; }; - vi { + vi@54080000 { compatible = "nvidia,tegra20-vi"; reg = <0x54080000 0x00040000>; interrupts = ; @@ -48,7 +48,7 @@ reset-names = "vi"; }; - epp { + epp@540c0000 { compatible = "nvidia,tegra20-epp"; reg = <0x540c0000 0x00040000>; interrupts = ; @@ -57,7 +57,7 @@ reset-names = "epp"; }; - isp { + isp@54100000 { compatible = "nvidia,tegra20-isp"; reg = <0x54100000 0x00040000>; interrupts = ; @@ -66,7 +66,7 @@ reset-names = "isp"; }; - gr2d { + gr2d@54140000 { compatible = "nvidia,tegra20-gr2d"; reg = <0x54140000 0x00040000>; interrupts = ; @@ -75,9 +75,9 @@ reset-names = "2d"; }; - gr3d { + gr3d@54140000 { compatible = "nvidia,tegra20-gr3d"; - reg = <0x54180000 0x00040000>; + reg = <0x54140000 0x00040000>; clocks = <&tegra_car TEGRA20_CLK_GR3D>; resets = <&tegra_car 24>; reset-names = "3d"; @@ -113,7 +113,7 @@ }; }; - hdmi { + hdmi@54280000 { compatible = "nvidia,tegra20-hdmi"; reg = <0x54280000 0x00040000>; interrupts = ; @@ -125,7 +125,7 @@ status = "disabled"; }; - tvo { + tvo@542c0000 { compatible = "nvidia,tegra20-tvo"; reg = <0x542c0000 0x00040000>; interrupts = ; @@ -133,9 +133,9 @@ status = "disabled"; }; - dsi { + dsi@542c0000 { compatible = "nvidia,tegra20-dsi"; - reg = <0x54300000 0x00040000>; + reg = <0x542c0000 0x00040000>; clocks = <&tegra_car TEGRA20_CLK_DSI>; resets = <&tegra_car 48>; reset-names = "dsi"; @@ -151,7 +151,7 @@ clocks = <&tegra_car TEGRA20_CLK_TWD>; }; - intc: interrupt-controller { + intc: interrupt-controller@50041000 { compatible = "arm,cortex-a9-gic"; reg = <0x50041000 0x1000 0x50040100 0x0100>; @@ -159,7 +159,7 @@ #interrupt-cells = <3>; }; - cache-controller { + cache-controller@50043000 { compatible = "arm,pl310-cache"; reg = <0x50043000 0x1000>; arm,data-latency = <5 5 2>; @@ -178,14 +178,14 @@ clocks = <&tegra_car TEGRA20_CLK_TIMER>; }; - tegra_car: clock { + tegra_car: clock@60006000 { compatible = "nvidia,tegra20-car"; reg = <0x60006000 0x1000>; #clock-cells = <1>; #reset-cells = <1>; }; - apbdma: dma { + apbdma: dma@6000a000 { compatible = "nvidia,tegra20-apbdma"; reg = <0x6000a000 0x1200>; interrupts = , @@ -210,12 +210,12 @@ #dma-cells = <1>; }; - ahb { + ahb@6000c004 { compatible = "nvidia,tegra20-ahb"; reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */ }; - gpio: gpio { + gpio: gpio@6000d000 { compatible = "nvidia,tegra20-gpio"; reg = <0x6000d000 0x1000>; interrupts = , @@ -231,7 +231,7 @@ interrupt-controller; }; - pinmux: pinmux { + pinmux: pinmux@70000014 { compatible = "nvidia,tegra20-pinmux"; reg = <0x70000014 0x10 /* Tri-state registers */ 0x70000080 0x20 /* Mux registers */ @@ -239,12 +239,12 @@ 0x70000868 0xa8>; /* Pad control registers */ }; - das { + das@70000c00 { compatible = "nvidia,tegra20-das"; reg = <0x70000c00 0x80>; }; - tegra_ac97: ac97 { + tegra_ac97: ac97@70002000 { compatible = "nvidia,tegra20-ac97"; reg = <0x70002000 0x200>; interrupts = ; @@ -352,7 +352,7 @@ status = "disabled"; }; - pwm: pwm { + pwm: pwm@7000a000 { compatible = "nvidia,tegra20-pwm"; reg = <0x7000a000 0x100>; #pwm-cells = <2>; @@ -362,7 +362,7 @@ status = "disabled"; }; - rtc { + rtc@7000e000 { compatible = "nvidia,tegra20-rtc"; reg = <0x7000e000 0x100>; interrupts = ; @@ -503,7 +503,7 @@ status = "disabled"; }; - kbc { + kbc@7000e200 { compatible = "nvidia,tegra20-kbc"; reg = <0x7000e200 0x100>; interrupts = ; @@ -513,7 +513,7 @@ status = "disabled"; }; - pmc { + pmc@7000e400 { compatible = "nvidia,tegra20-pmc"; reg = <0x7000e400 0x400>; clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>; @@ -527,7 +527,7 @@ interrupts = ; }; - iommu { + iommu@7000f024 { compatible = "nvidia,tegra20-gart"; reg = <0x7000f024 0x00000018 /* controller registers */ 0x58000000 0x02000000>; /* GART aperture */ @@ -540,7 +540,7 @@ #size-cells = <0>; }; - pcie-controller { + pcie-controller@80003000 { compatible = "nvidia,tegra20-pcie"; device_type = "pci"; reg = <0x80003000 0x00000800 /* PADS registers */ diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index 08cad69..bc28e27 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -10,7 +10,7 @@ reg = <0x80000000 0x7ff00000>; }; - pcie-controller { + pcie-controller@00003000 { status = "okay"; pex-clk-supply = <&sys_3v3_pexs_reg>; vdd-supply = <&ldo1_reg>; @@ -31,8 +31,8 @@ }; }; - host1x { - hdmi { + host1x@50000000 { + hdmi@54280000 { status = "okay"; vdd-supply = <&sys_3v3_reg>; @@ -44,7 +44,7 @@ }; }; - pinmux { + pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -159,7 +159,7 @@ status = "okay"; clock-frequency = <100000>; - rt5640: rt5640 { + rt5640: rt5640@1c { compatible = "realtek,rt5640"; reg = <0x1c>; interrupt-parent = <&gpio>; @@ -168,7 +168,7 @@ <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_HIGH>; }; - tps62361 { + tps62361@60 { compatible = "ti,tps62361"; reg = <0x60>; @@ -296,13 +296,13 @@ }; }; - ahub { + ahub@70080000 { i2s@70080400 { status = "okay"; }; }; - pmc { + pmc@7000e400 { status = "okay"; nvidia,invert-interrupt; nvidia,suspend-mode = <1>; @@ -342,7 +342,7 @@ #address-cells = <1>; #size-cells = <0>; - clk32k_in: clock { + clk32k_in: clock@0 { compatible = "fixed-clock"; reg=<0>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index 5ea7dfa..b159a41 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -31,7 +31,7 @@ reg = <0x80000000 0x40000000>; }; - pcie-controller { + pcie-controller@00003000 { status = "okay"; pex-clk-supply = <&pex_hvdd_3v3_reg>; vdd-supply = <&ldo1_reg>; @@ -51,7 +51,7 @@ }; }; - pinmux { + pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -302,7 +302,7 @@ interrupts = ; }; - tps62361 { + tps62361@60 { compatible = "ti,tps62361"; reg = <0x60>; @@ -326,13 +326,13 @@ }; }; - ahub { + ahub@70080000 { i2s@70080400 { status = "okay"; }; }; - pmc { + pmc@7000e400 { status = "okay"; nvidia,invert-interrupt; nvidia,suspend-mode = <1>; @@ -372,7 +372,7 @@ #address-cells = <1>; #size-cells = <0>; - clk32k_in: clock { + clk32k_in: clock@0 { compatible = "fixed-clock"; reg=<0>; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 31259b0..829eb4b 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -16,7 +16,7 @@ serial4 = &uarte; }; - pcie-controller { + pcie-controller@00003000 { compatible = "nvidia,tegra30-pcie"; device_type = "pci"; reg = <0x00003000 0x00000800 /* PADS registers */ @@ -89,7 +89,7 @@ }; }; - host1x { + host1x@50000000 { compatible = "nvidia,tegra30-host1x", "simple-bus"; reg = <0x50000000 0x00024000>; interrupts = , /* syncpt */ @@ -103,7 +103,7 @@ ranges = <0x54000000 0x54000000 0x04000000>; - mpe { + mpe@54040000 { compatible = "nvidia,tegra30-mpe"; reg = <0x54040000 0x00040000>; interrupts = ; @@ -112,7 +112,7 @@ reset-names = "mpe"; }; - vi { + vi@54080000 { compatible = "nvidia,tegra30-vi"; reg = <0x54080000 0x00040000>; interrupts = ; @@ -121,7 +121,7 @@ reset-names = "vi"; }; - epp { + epp@540c0000 { compatible = "nvidia,tegra30-epp"; reg = <0x540c0000 0x00040000>; interrupts = ; @@ -130,7 +130,7 @@ reset-names = "epp"; }; - isp { + isp@54100000 { compatible = "nvidia,tegra30-isp"; reg = <0x54100000 0x00040000>; interrupts = ; @@ -139,7 +139,7 @@ reset-names = "isp"; }; - gr2d { + gr2d@54140000 { compatible = "nvidia,tegra30-gr2d"; reg = <0x54140000 0x00040000>; interrupts = ; @@ -148,7 +148,7 @@ clocks = <&tegra_car TEGRA30_CLK_GR2D>; }; - gr3d { + gr3d@54180000 { compatible = "nvidia,tegra30-gr3d"; reg = <0x54180000 0x00040000>; clocks = <&tegra_car TEGRA30_CLK_GR3D @@ -189,7 +189,7 @@ }; }; - hdmi { + hdmi@54280000 { compatible = "nvidia,tegra30-hdmi"; reg = <0x54280000 0x00040000>; interrupts = ; @@ -201,7 +201,7 @@ status = "disabled"; }; - tvo { + tvo@542c0000 { compatible = "nvidia,tegra30-tvo"; reg = <0x542c0000 0x00040000>; interrupts = ; @@ -209,7 +209,7 @@ status = "disabled"; }; - dsi { + dsi@54300000 { compatible = "nvidia,tegra30-dsi"; reg = <0x54300000 0x00040000>; clocks = <&tegra_car TEGRA30_CLK_DSIA>; @@ -227,7 +227,7 @@ clocks = <&tegra_car TEGRA30_CLK_TWD>; }; - intc: interrupt-controller { + intc: interrupt-controller@50041000 { compatible = "arm,cortex-a9-gic"; reg = <0x50041000 0x1000 0x50040100 0x0100>; @@ -235,7 +235,7 @@ #interrupt-cells = <3>; }; - cache-controller { + cache-controller@50043000 { compatible = "arm,pl310-cache"; reg = <0x50043000 0x1000>; arm,data-latency = <6 6 2>; @@ -256,14 +256,14 @@ clocks = <&tegra_car TEGRA30_CLK_TIMER>; }; - tegra_car: clock { + tegra_car: clock@60006000 { compatible = "nvidia,tegra30-car"; reg = <0x60006000 0x1000>; #clock-cells = <1>; #reset-cells = <1>; }; - apbdma: dma { + apbdma: dma@6000a000 { compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; reg = <0x6000a000 0x1400>; interrupts = , @@ -304,12 +304,12 @@ #dma-cells = <1>; }; - ahb: ahb { + ahb: ahb@6000c004 { compatible = "nvidia,tegra30-ahb"; reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */ }; - gpio: gpio { + gpio: gpio@6000d000 { compatible = "nvidia,tegra30-gpio"; reg = <0x6000d000 0x1000>; interrupts = , @@ -326,7 +326,7 @@ interrupt-controller; }; - pinmux: pinmux { + pinmux: pinmux@70000868 { compatible = "nvidia,tegra30-pinmux"; reg = <0x70000868 0xd4 /* Pad control registers */ 0x70003000 0x3e4>; /* Mux registers */ @@ -405,7 +405,7 @@ status = "disabled"; }; - pwm: pwm { + pwm: pwm@7000a000 { compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; reg = <0x7000a000 0x100>; #pwm-cells = <2>; @@ -415,7 +415,7 @@ status = "disabled"; }; - rtc { + rtc@7000e000 { compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; reg = <0x7000e000 0x100>; interrupts = ; @@ -586,7 +586,7 @@ status = "disabled"; }; - kbc { + kbc@7000e200 { compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc"; reg = <0x7000e200 0x100>; interrupts = ; @@ -596,14 +596,14 @@ status = "disabled"; }; - pmc { + pmc@7000e400 { compatible = "nvidia,tegra30-pmc"; reg = <0x7000e400 0x400>; clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; }; - memory-controller { + memory-controller@7000f000 { compatible = "nvidia,tegra30-mc"; reg = <0x7000f000 0x010 0x7000f03c 0x1b4 @@ -612,7 +612,7 @@ interrupts = ; }; - iommu { + iommu@7000f010 { compatible = "nvidia,tegra30-smmu"; reg = <0x7000f010 0x02c 0x7000f1f0 0x010 @@ -622,7 +622,7 @@ nvidia,ahb = <&ahb>; }; - ahub { + ahub@70080000 { compatible = "nvidia,tegra30-ahub"; reg = <0x70080000 0x200 0x70080200 0x100>; -- cgit v1.1 From 578990537aa553a3194420e63d467fcb12d42ba4 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 26 Nov 2013 14:43:45 -0700 Subject: ARM: tegra: fix node sort order For Tegra DT files, I've been attempting to keep the nodes sorted in the order: 1) Nodes with reg, in order of reg. 2) Nodes without reg, alphabetically. This patch fixes a few escapees that I missed:-( The diffs look larger than they really are, because sometimes when one node was moved up or down, diff chose to represent this as many other nodes being moved the other way! Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra20-colibri-512.dtsi | 56 +++--- arch/arm/boot/dts/tegra20-harmony.dts | 184 +++++++++---------- arch/arm/boot/dts/tegra20-iris-512.dts | 14 +- arch/arm/boot/dts/tegra20-seaboard.dts | 281 +++++++++++++++-------------- arch/arm/boot/dts/tegra20-whistler.dts | 26 +-- arch/arm/boot/dts/tegra30-beaver.dts | 64 +++---- arch/arm/boot/dts/tegra30-cardhu-a02.dts | 14 +- arch/arm/boot/dts/tegra30-cardhu-a04.dts | 14 +- arch/arm/boot/dts/tegra30-cardhu.dtsi | 12 +- 9 files changed, 333 insertions(+), 332 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi index f20fc97..78f7e91 100644 --- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi @@ -199,6 +199,14 @@ }; }; + ac97: ac97@70002000 { + status = "okay"; + nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0) + GPIO_ACTIVE_HIGH>; + nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0) + GPIO_ACTIVE_HIGH>; + }; + i2c@7000c000 { clock-frequency = <400000>; }; @@ -442,14 +450,6 @@ }; }; - ac97: ac97@70002000 { - status = "okay"; - nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0) - GPIO_ACTIVE_HIGH>; - nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0) - GPIO_ACTIVE_HIGH>; - }; - usb@c5004000 { status = "okay"; nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) @@ -479,26 +479,6 @@ }; }; - sound { - compatible = "nvidia,tegra-audio-wm9712-colibri_t20", - "nvidia,tegra-audio-wm9712"; - nvidia,model = "Colibri T20 AC97 Audio"; - - nvidia,audio-routing = - "Headphone", "HPOUTL", - "Headphone", "HPOUTR", - "LineIn", "LINEINL", - "LineIn", "LINEINR", - "Mic", "MIC1"; - - nvidia,ac97-controller = <&ac97>; - - clocks = <&tegra_car TEGRA20_CLK_PLL_A>, - <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA20_CLK_CDEV1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; - regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -525,4 +505,24 @@ gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>; }; }; + + sound { + compatible = "nvidia,tegra-audio-wm9712-colibri_t20", + "nvidia,tegra-audio-wm9712"; + nvidia,model = "Colibri T20 AC97 Audio"; + + nvidia,audio-routing = + "Headphone", "HPOUTL", + "Headphone", "HPOUTR", + "LineIn", "LINEINL", + "LineIn", "LINEINR", + "Mic", "MIC1"; + + nvidia,ac97-controller = <&ac97>; + + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA20_CLK_CDEV1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + }; }; diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index b9c6f67..94d2189 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -415,98 +415,6 @@ }; }; - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <5000>; - nvidia,cpu-pwr-off-time = <5000>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <3875>; - nvidia,sys-clock-req-active-high; - }; - - pcie-controller@80003000 { - pex-clk-supply = <&pci_clk_reg>; - vdd-supply = <&pci_vdd_reg>; - status = "okay"; - - pci@1,0 { - status = "okay"; - }; - - pci@2,0 { - status = "okay"; - }; - }; - - usb@c5000000 { - status = "okay"; - }; - - usb-phy@c5000000 { - status = "okay"; - }; - - usb@c5004000 { - status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) - GPIO_ACTIVE_LOW>; - }; - - usb-phy@c5004000 { - status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) - GPIO_ACTIVE_LOW>; - }; - - usb@c5008000 { - status = "okay"; - }; - - usb-phy@c5008000 { - status = "okay"; - }; - - sdhci@c8000200 { - status = "okay"; - cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; - power-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - }; - - sdhci@c8000600 { - status = "okay"; - cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; - power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; - bus-width = <8>; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg=<0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - linux,code = <116>; /* KEY_POWER */ - gpio-key,wakeup; - }; - }; - kbc@7000e200 { status = "okay"; nvidia,debounce-delay-ms = <2>; @@ -624,6 +532,98 @@ 0x1F0400D6>; /* KEY_QUESTION */ }; + pmc@7000e400 { + nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <5000>; + nvidia,cpu-pwr-off-time = <5000>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <3875>; + nvidia,sys-clock-req-active-high; + }; + + pcie-controller@80003000 { + pex-clk-supply = <&pci_clk_reg>; + vdd-supply = <&pci_vdd_reg>; + status = "okay"; + + pci@1,0 { + status = "okay"; + }; + + pci@2,0 { + status = "okay"; + }; + }; + + usb@c5000000 { + status = "okay"; + }; + + usb-phy@c5000000 { + status = "okay"; + }; + + usb@c5004000 { + status = "okay"; + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) + GPIO_ACTIVE_LOW>; + }; + + usb-phy@c5004000 { + status = "okay"; + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) + GPIO_ACTIVE_LOW>; + }; + + usb@c5008000 { + status = "okay"; + }; + + usb-phy@c5008000 { + status = "okay"; + }; + + sdhci@c8000200 { + status = "okay"; + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + }; + + sdhci@c8000600 { + status = "okay"; + cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; + bus-width = <8>; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock@0 { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + linux,code = <116>; /* KEY_POWER */ + gpio-key,wakeup; + }; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/tegra20-iris-512.dts b/arch/arm/boot/dts/tegra20-iris-512.dts index 770fc66..274d252 100644 --- a/arch/arm/boot/dts/tegra20-iris-512.dts +++ b/arch/arm/boot/dts/tegra20-iris-512.dts @@ -36,31 +36,31 @@ }; }; - usb@c5000000 { + serial@70006000 { status = "okay"; }; - usb-phy@c5000000 { + serial@70006300 { status = "okay"; }; - usb@c5008000 { + i2c_ddc: i2c@7000c400 { status = "okay"; }; - usb-phy@c5008000 { + usb@c5000000 { status = "okay"; }; - serial@70006000 { + usb-phy@c5000000 { status = "okay"; }; - serial@70006300 { + usb@c5008000 { status = "okay"; }; - i2c_ddc: i2c@7000c400 { + usb-phy@c5008000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index 01442fc..07ff55a 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -386,6 +386,13 @@ status = "okay"; clock-frequency = <400000>; + magnetometer@c { + compatible = "ak,ak8975"; + reg = <0xc>; + interrupt-parent = <&gpio>; + interrupts = ; + }; + pmic: tps6586x@34 { compatible = "ti,tps6586x"; reg = <0x34>; @@ -507,146 +514,6 @@ compatible = "onnn,nct1008"; reg = <0x4c>; }; - - magnetometer@c { - compatible = "ak,ak8975"; - reg = <0xc>; - interrupt-parent = <&gpio>; - interrupts = ; - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <5000>; - nvidia,cpu-pwr-off-time = <5000>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <3875>; - nvidia,sys-clock-req-active-high; - }; - - memory-controller@7000f400 { - emc-table@190000 { - reg = <190000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <190000>; - nvidia,emc-registers = <0x0000000c 0x00000026 - 0x00000009 0x00000003 0x00000004 0x00000004 - 0x00000002 0x0000000c 0x00000003 0x00000003 - 0x00000002 0x00000001 0x00000004 0x00000005 - 0x00000004 0x00000009 0x0000000d 0x0000059f - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000003 0x00000001 0x0000000b 0x000000c8 - 0x00000003 0x00000007 0x00000004 0x0000000f - 0x00000002 0x00000000 0x00000000 0x00000002 - 0x00000000 0x00000000 0x00000083 0xa06204ae - 0x007dc010 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - - emc-table@380000 { - reg = <380000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <380000>; - nvidia,emc-registers = <0x00000017 0x0000004b - 0x00000012 0x00000006 0x00000004 0x00000005 - 0x00000003 0x0000000c 0x00000006 0x00000006 - 0x00000003 0x00000001 0x00000004 0x00000005 - 0x00000004 0x00000009 0x0000000d 0x00000b5f - 0x00000000 0x00000003 0x00000003 0x00000006 - 0x00000006 0x00000001 0x00000011 0x000000c8 - 0x00000003 0x0000000e 0x00000007 0x0000000f - 0x00000002 0x00000000 0x00000000 0x00000002 - 0x00000000 0x00000000 0x00000083 0xe044048b - 0x007d8010 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - }; - - usb@c5000000 { - status = "okay"; - dr_mode = "otg"; - }; - - usb-phy@c5000000 { - status = "okay"; - vbus-supply = <&vbus_reg>; - dr_mode = "otg"; - }; - - usb@c5004000 { - status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) - GPIO_ACTIVE_LOW>; - }; - - usb-phy@c5004000 { - status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) - GPIO_ACTIVE_LOW>; - }; - - usb@c5008000 { - status = "okay"; - }; - - usb-phy@c5008000 { - status = "okay"; - }; - - sdhci@c8000000 { - status = "okay"; - power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - keep-power-in-suspend; - }; - - sdhci@c8000400 { - status = "okay"; - cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; - power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - }; - - sdhci@c8000600 { - status = "okay"; - bus-width = <8>; - non-removable; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg=<0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - linux,code = <116>; /* KEY_POWER */ - gpio-key,wakeup; - }; - - lid { - label = "Lid"; - gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>; - linux,input-type = <5>; /* EV_SW */ - linux,code = <0>; /* SW_LID */ - debounce-interval = <1>; - gpio-key,wakeup; - }; }; kbc@7000e200 { @@ -788,6 +655,140 @@ 0x1F04008A>; /* KEY_HELP */ }; + + pmc@7000e400 { + nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <5000>; + nvidia,cpu-pwr-off-time = <5000>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <3875>; + nvidia,sys-clock-req-active-high; + }; + + memory-controller@7000f400 { + emc-table@190000 { + reg = <190000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <190000>; + nvidia,emc-registers = <0x0000000c 0x00000026 + 0x00000009 0x00000003 0x00000004 0x00000004 + 0x00000002 0x0000000c 0x00000003 0x00000003 + 0x00000002 0x00000001 0x00000004 0x00000005 + 0x00000004 0x00000009 0x0000000d 0x0000059f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000003 0x00000001 0x0000000b 0x000000c8 + 0x00000003 0x00000007 0x00000004 0x0000000f + 0x00000002 0x00000000 0x00000000 0x00000002 + 0x00000000 0x00000000 0x00000083 0xa06204ae + 0x007dc010 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@380000 { + reg = <380000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <380000>; + nvidia,emc-registers = <0x00000017 0x0000004b + 0x00000012 0x00000006 0x00000004 0x00000005 + 0x00000003 0x0000000c 0x00000006 0x00000006 + 0x00000003 0x00000001 0x00000004 0x00000005 + 0x00000004 0x00000009 0x0000000d 0x00000b5f + 0x00000000 0x00000003 0x00000003 0x00000006 + 0x00000006 0x00000001 0x00000011 0x000000c8 + 0x00000003 0x0000000e 0x00000007 0x0000000f + 0x00000002 0x00000000 0x00000000 0x00000002 + 0x00000000 0x00000000 0x00000083 0xe044048b + 0x007d8010 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + }; + + usb@c5000000 { + status = "okay"; + dr_mode = "otg"; + }; + + usb-phy@c5000000 { + status = "okay"; + vbus-supply = <&vbus_reg>; + dr_mode = "otg"; + }; + + usb@c5004000 { + status = "okay"; + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) + GPIO_ACTIVE_LOW>; + }; + + usb-phy@c5004000 { + status = "okay"; + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) + GPIO_ACTIVE_LOW>; + }; + + usb@c5008000 { + status = "okay"; + }; + + usb-phy@c5008000 { + status = "okay"; + }; + + sdhci@c8000000 { + status = "okay"; + power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + keep-power-in-suspend; + }; + + sdhci@c8000400 { + status = "okay"; + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + }; + + sdhci@c8000600 { + status = "okay"; + bus-width = <8>; + non-removable; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock@0 { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + linux,code = <116>; /* KEY_POWER */ + gpio-key,wakeup; + }; + + lid { + label = "Lid"; + gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>; + linux,input-type = <5>; /* EV_SW */ + linux,code = <0>; /* SW_LID */ + debounce-interval = <1>; + gpio-key,wakeup; + }; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts index b047621..82037fe 100644 --- a/arch/arm/boot/dts/tegra20-whistler.dts +++ b/arch/arm/boot/dts/tegra20-whistler.dts @@ -495,6 +495,19 @@ }; }; + kbc@7000e200 { + status = "okay"; + nvidia,debounce-delay-ms = <20>; + nvidia,repeat-delay-ms = <160>; + nvidia,kbc-row-pins = <0 1 2>; + nvidia,kbc-col-pins = <16 17>; + nvidia,wakeup-source; + linux,keymap = <0x00000074 /* KEY_POWER */ + 0x01000066 /* KEY_HOME */ + 0x0101009E /* KEY_BACK */ + 0x0201008B>; /* KEY_MENU */ + }; + pmc@7000e400 { nvidia,invert-interrupt; nvidia,suspend-mode = <1>; @@ -551,19 +564,6 @@ }; }; - kbc@7000e200 { - status = "okay"; - nvidia,debounce-delay-ms = <20>; - nvidia,repeat-delay-ms = <160>; - nvidia,kbc-row-pins = <0 1 2>; - nvidia,kbc-col-pins = <16 17>; - nvidia,wakeup-source; - linux,keymap = <0x00000074 /* KEY_POWER */ - 0x01000066 /* KEY_HOME */ - 0x0101009E /* KEY_BACK */ - 0x0201008B>; /* KEY_MENU */ - }; - regulators { compatible = "simple-bus"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index bc28e27..3ad193c 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -168,19 +168,6 @@ <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_HIGH>; }; - tps62361@60 { - compatible = "ti,tps62361"; - reg = <0x60>; - - regulator-name = "tps62361-vout"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - ti,vsel0-state-high; - ti,vsel1-state-high; - }; - pmic: tps65911@2d { compatible = "ti,tps65911"; reg = <0x2d>; @@ -284,6 +271,19 @@ }; }; }; + + tps62361@60 { + compatible = "ti,tps62361"; + reg = <0x60>; + + regulator-name = "tps62361-vout"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + ti,vsel0-state-high; + ti,vsel1-state-high; + }; }; spi@7000da00 { @@ -296,12 +296,6 @@ }; }; - ahub@70080000 { - i2s@70080400 { - status = "okay"; - }; - }; - pmc@7000e400 { status = "okay"; nvidia,invert-interrupt; @@ -314,6 +308,12 @@ nvidia,sys-clock-req-active-high; }; + ahub@70080000 { + i2s@70080400 { + status = "okay"; + }; + }; + sdhci@78000000 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; @@ -350,6 +350,19 @@ }; }; + gpio-leds { + compatible = "gpio-leds"; + + gpled1 { + label = "LED1"; /* CR5A1 (blue) */ + gpios = <&gpio TEGRA_GPIO(L, 1) GPIO_ACTIVE_HIGH>; + }; + gpled2 { + label = "LED2"; /* CR4A2 (green) */ + gpios = <&gpio TEGRA_GPIO(L, 0) GPIO_ACTIVE_HIGH>; + }; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -453,19 +466,6 @@ }; }; - gpio-leds { - compatible = "gpio-leds"; - - gpled1 { - label = "LED1"; /* CR5A1 (blue) */ - gpios = <&gpio TEGRA_GPIO(L, 1) GPIO_ACTIVE_HIGH>; - }; - gpled2 { - label = "LED2"; /* CR4A2 (green) */ - gpios = <&gpio TEGRA_GPIO(L, 0) GPIO_ACTIVE_HIGH>; - }; - }; - sound { compatible = "nvidia,tegra-audio-rt5640-beaver", "nvidia,tegra-audio-rt5640"; diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/tegra30-cardhu-a02.dts index 1082c5e..c9bfedc 100644 --- a/arch/arm/boot/dts/tegra30-cardhu-a02.dts +++ b/arch/arm/boot/dts/tegra30-cardhu-a02.dts @@ -8,6 +8,13 @@ model = "NVIDIA Tegra30 Cardhu A02 evaluation board"; compatible = "nvidia,cardhu-a02", "nvidia,cardhu", "nvidia,tegra30"; + sdhci@78000400 { + status = "okay"; + power-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + keep-power-in-suspend; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -83,12 +90,5 @@ gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_HIGH>; }; }; - - sdhci@78000400 { - status = "okay"; - power-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - keep-power-in-suspend; - }; }; diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts index bf012bdd..fadf55e 100644 --- a/arch/arm/boot/dts/tegra30-cardhu-a04.dts +++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dts @@ -8,6 +8,13 @@ model = "NVIDIA Tegra30 Cardhu A04 (A05, A06, A07) evaluation board"; compatible = "nvidia,cardhu-a04", "nvidia,cardhu", "nvidia,tegra30"; + sdhci@78000400 { + status = "okay"; + power-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + keep-power-in-suspend; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -95,11 +102,4 @@ gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>; }; }; - - sdhci@78000400 { - status = "okay"; - power-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>; - bus-width = <4>; - keep-power-in-suspend; - }; }; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index b159a41..748b4ba 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -326,12 +326,6 @@ }; }; - ahub@70080000 { - i2s@70080400 { - status = "okay"; - }; - }; - pmc@7000e400 { status = "okay"; nvidia,invert-interrupt; @@ -344,6 +338,12 @@ nvidia,sys-clock-req-active-high; }; + ahub@70080000 { + i2s@70080400 { + status = "okay"; + }; + }; + sdhci@78000000 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; -- cgit v1.1 From 3b86baf296eb2791eeeacd2ed07f7d2789784d24 Mon Sep 17 00:00:00 2001 From: Joseph Lo Date: Tue, 8 Oct 2013 15:47:40 +0800 Subject: ARM: tegra: add clock properties for devices of Tegra124 This patch adds clock properties for devices in the DT for basic support of Tegra124 SoC. Signed-off-by: Joseph Lo [swarren, added missing unit address to "clock" node] Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124-venice2.dts | 13 +++++++++++++ arch/arm/boot/dts/tegra124.dtsi | 16 ++++++++++++++++ 2 files changed, 29 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 431d67a..956b6e7 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -24,4 +24,17 @@ nvidia,core-power-req-active-high; nvidia,sys-clock-req-active-high; }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock@0 { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; }; diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index b741300..936579b 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -1,3 +1,4 @@ +#include #include #include @@ -28,6 +29,13 @@ , , ; + clocks = <&tegra_car TEGRA124_CLK_TIMER>; + }; + + tegra_car: clock@60006000 { + compatible = "nvidia,tegra124-car"; + reg = <0x60006000 0x1000>; + #clock-cells = <1>; }; gpio: gpio@6000d000 { @@ -60,6 +68,7 @@ reg = <0x70006000 0x40>; reg-shift = <2>; interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_UARTA>; status = "disabled"; }; @@ -68,6 +77,7 @@ reg = <0x70006040 0x40>; reg-shift = <2>; interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_UARTB>; status = "disabled"; }; @@ -76,6 +86,7 @@ reg = <0x70006200 0x40>; reg-shift = <2>; interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_UARTC>; status = "disabled"; }; @@ -84,6 +95,7 @@ reg = <0x70006300 0x40>; reg-shift = <2>; interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_UARTD>; status = "disabled"; }; @@ -92,6 +104,7 @@ reg = <0x70006400 0x40>; reg-shift = <2>; interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_UARTE>; status = "disabled"; }; @@ -99,11 +112,14 @@ compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; reg = <0x7000e000 0x100>; interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_RTC>; }; pmc@7000e400 { compatible = "nvidia,tegra124-pmc"; reg = <0x7000e400 0x400>; + clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; + clock-names = "pclk", "clk32k_in"; }; cpus { -- cgit v1.1 From f71e4f034a57b0203d91aa7c805a12c75f476dab Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 7 Nov 2013 12:20:57 -0700 Subject: ARM: tegra: add reset properties to Tegra124 DTs The DT bindings now require module resets to be specified. The earlier patches which added these nodes were originally written before that requirement. Signed-off-by: Stephen Warren Reviewed-by: Thierry Reding --- arch/arm/boot/dts/tegra124.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 936579b..4ed6a3a 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -36,6 +36,7 @@ compatible = "nvidia,tegra124-car"; reg = <0x60006000 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; }; gpio: gpio@6000d000 { @@ -69,6 +70,8 @@ reg-shift = <2>; interrupts = ; clocks = <&tegra_car TEGRA124_CLK_UARTA>; + resets = <&tegra_car 6>; + reset-names = "serial"; status = "disabled"; }; @@ -78,6 +81,8 @@ reg-shift = <2>; interrupts = ; clocks = <&tegra_car TEGRA124_CLK_UARTB>; + resets = <&tegra_car 7>; + reset-names = "serial"; status = "disabled"; }; @@ -87,6 +92,8 @@ reg-shift = <2>; interrupts = ; clocks = <&tegra_car TEGRA124_CLK_UARTC>; + resets = <&tegra_car 55>; + reset-names = "serial"; status = "disabled"; }; @@ -96,6 +103,8 @@ reg-shift = <2>; interrupts = ; clocks = <&tegra_car TEGRA124_CLK_UARTD>; + resets = <&tegra_car 65>; + reset-names = "serial"; status = "disabled"; }; @@ -105,6 +114,8 @@ reg-shift = <2>; interrupts = ; clocks = <&tegra_car TEGRA124_CLK_UARTE>; + resets = <&tegra_car 66>; + reset-names = "serial"; status = "disabled"; }; -- cgit v1.1 From 2f5a913eb59496e37c64449dfdcd66b0bef90630 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 15 Nov 2013 12:22:53 -0700 Subject: ARM: tegra: add APB DMA controller to Tegra124 DT Instantiate the APB DMA controller in the Tegra124 DT, and add all DMA-related properties to other DT nodes that rely on (reference) the DMA controller's node. Signed-off-by: Stephen Warren Reviewed-by: Thierry Reding --- arch/arm/boot/dts/tegra124.dtsi | 51 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 4ed6a3a..9a8b5b8 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -56,6 +56,47 @@ interrupt-controller; }; + apbdma: dma@60020000 { + compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; + reg = <0x60020000 0x1400>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&tegra_car TEGRA124_CLK_APBDMA>; + resets = <&tegra_car 34>; + reset-names = "dma"; + #dma-cells = <1>; + }; + /* * There are two serial driver i.e. 8250 based simple serial * driver and APB DMA based serial driver for higher baudrate @@ -72,6 +113,8 @@ clocks = <&tegra_car TEGRA124_CLK_UARTA>; resets = <&tegra_car 6>; reset-names = "serial"; + dmas = <&apbdma 8>, <&apbdma 8>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -83,6 +126,8 @@ clocks = <&tegra_car TEGRA124_CLK_UARTB>; resets = <&tegra_car 7>; reset-names = "serial"; + dmas = <&apbdma 9>, <&apbdma 9>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -94,6 +139,8 @@ clocks = <&tegra_car TEGRA124_CLK_UARTC>; resets = <&tegra_car 55>; reset-names = "serial"; + dmas = <&apbdma 10>, <&apbdma 10>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -105,6 +152,8 @@ clocks = <&tegra_car TEGRA124_CLK_UARTD>; resets = <&tegra_car 65>; reset-names = "serial"; + dmas = <&apbdma 19>, <&apbdma 19>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -116,6 +165,8 @@ clocks = <&tegra_car TEGRA124_CLK_UARTE>; resets = <&tegra_car 66>; reset-names = "serial"; + dmas = <&apbdma 20>, <&apbdma 20>; + dma-names = "rx", "tx"; status = "disabled"; }; -- cgit v1.1 From caefe637b494c437e86fa6c90bb4b17e01ea558e Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 1 Nov 2013 14:03:59 -0600 Subject: ARM: tegra: add Tegra124 pinmux node to DT Signed-off-by: Stephen Warren Reviewed-by: Thierry Reding Tested-by: Thierry Reding Acked by: Laxman Dewangan --- arch/arm/boot/dts/tegra124.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 9a8b5b8..fe070bc 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -97,6 +97,12 @@ #dma-cells = <1>; }; + pinmux: pinmux@70000868 { + compatible = "nvidia,tegra124-pinmux"; + reg = <0x70000868 0x164>, /* Pad control registers */ + <0x70003000 0x434>; /* Mux registers */ + }; + /* * There are two serial driver i.e. 8250 based simple serial * driver and APB DMA based serial driver for higher baudrate -- cgit v1.1 From 784c7444f052dda27db8d40ed35b57aefd2e04b8 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 31 Oct 2013 17:23:05 -0600 Subject: ARM: tegra: add MMC controllers to Tegra124 DT Tegra124 has 4 MMC controllers just like previous versions of the SoC. Note that there are some non-backwards-compatible HW differences, and hence a new DT compatible value must be used to describe the HW. Also enable the relevant controllers in the Venice2 board DT. power-gpios property suggested by Thierry Reding. Signed-off-by: Stephen Warren Reviewed-by: Thierry Reding Tested-by: Thierry Reding --- arch/arm/boot/dts/tegra124-venice2.dts | 12 ++++++++++ arch/arm/boot/dts/tegra124.dtsi | 40 ++++++++++++++++++++++++++++++++++ 2 files changed, 52 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 956b6e7..f765c82 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -25,6 +25,18 @@ nvidia,sys-clock-req-active-high; }; + sdhci@700b0400 { + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; + status = "okay"; + bus-width = <4>; + }; + + sdhci@700b0600 { + status = "okay"; + bus-width = <8>; + }; + clocks { compatible = "simple-bus"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index fe070bc..eb61456 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -190,6 +190,46 @@ clock-names = "pclk", "clk32k_in"; }; + sdhci@700b0000 { + compatible = "nvidia,tegra124-sdhci"; + reg = <0x700b0000 0x200>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; + resets = <&tegra_car 14>; + reset-names = "sdhci"; + status = "disable"; + }; + + sdhci@700b0200 { + compatible = "nvidia,tegra124-sdhci"; + reg = <0x700b0200 0x200>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; + resets = <&tegra_car 9>; + reset-names = "sdhci"; + status = "disable"; + }; + + sdhci@700b0400 { + compatible = "nvidia,tegra124-sdhci"; + reg = <0x700b0400 0x200>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; + resets = <&tegra_car 69>; + reset-names = "sdhci"; + status = "disable"; + }; + + sdhci@700b0600 { + compatible = "nvidia,tegra124-sdhci"; + reg = <0x700b0600 0x200>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; + resets = <&tegra_car 15>; + reset-names = "sdhci"; + status = "disable"; + }; + cpus { #address-cells = <1>; #size-cells = <0>; -- cgit v1.1 From 4f6074601a4dfaa628c4fa8f284f2841df41f0fe Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 3 Dec 2013 16:29:04 -0700 Subject: ARM: tegra: add I2C controllers to Tegra124 DT Tegra124 has 6 I2C controllers. The first 5 have identical configuration to Tegra114, but the sixth obviously has different interrupt/... IDs. Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124.dtsi | 90 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index eb61456..b940276 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -176,6 +176,96 @@ status = "disabled"; }; + i2c@7000c000 { + compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + reg = <0x7000c000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_I2C1>; + clock-names = "div-clk"; + resets = <&tegra_car 12>; + reset-names = "i2c"; + dmas = <&apbdma 21>, <&apbdma 21>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c@7000c400 { + compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + reg = <0x7000c400 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_I2C2>; + clock-names = "div-clk"; + resets = <&tegra_car 54>; + reset-names = "i2c"; + dmas = <&apbdma 22>, <&apbdma 22>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c@7000c500 { + compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + reg = <0x7000c500 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_I2C3>; + clock-names = "div-clk"; + resets = <&tegra_car 67>; + reset-names = "i2c"; + dmas = <&apbdma 23>, <&apbdma 23>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c@7000c700 { + compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + reg = <0x7000c700 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_I2C4>; + clock-names = "div-clk"; + resets = <&tegra_car 103>; + reset-names = "i2c"; + dmas = <&apbdma 26>, <&apbdma 26>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c@7000d000 { + compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + reg = <0x7000d000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_I2C5>; + clock-names = "div-clk"; + resets = <&tegra_car 47>; + reset-names = "i2c"; + dmas = <&apbdma 24>, <&apbdma 24>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c@7000d100 { + compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; + reg = <0x7000d100 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_I2C6>; + clock-names = "div-clk"; + resets = <&tegra_car 166>; + reset-names = "i2c"; + dmas = <&apbdma 30>, <&apbdma 30>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + rtc@7000e000 { compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; reg = <0x7000e000 0x100>; -- cgit v1.1 From 9d5b25050715ce052bc69ebafb840351bd255932 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 3 Dec 2013 16:44:35 -0700 Subject: ARM: tegra: enable I2C controllers on Venice2 Enable all the I2C controllers that are wired up on Venice2. I don't know the correct I2C bus clock rates, so set them all to a conservative 100KHz for now. Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124-venice2.dts | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index f765c82..3d6ba4b 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -14,6 +14,31 @@ status = "okay"; }; + i2c@7000c000 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c400 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c500 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c700 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <100000>; + }; + pmc@7000e400 { nvidia,invert-interrupt; nvidia,suspend-mode = <1>; -- cgit v1.1 From e66555788a314dec76e7735e0603549007625182 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 4 Dec 2013 15:05:51 -0700 Subject: ARM: tegra: add audio-related device to Tegra124 DT Tegra124 contains a similar set of audio devices to previous Tegra chips. Specifically, there is an AHUB device which contains DMA FIFOs and audio routing, and which hosts various audio-related components such as I2S controllers. Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124.dtsi | 103 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 103 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index b940276..a68aa33 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -320,6 +320,109 @@ status = "disable"; }; + ahub@70300000 { + compatible = "nvidia,tegra124-ahub"; + reg = <0x70300000 0x200>, + <0x70300800 0x800>, + <0x70300200 0x600>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>, + <&tegra_car TEGRA124_CLK_APBIF>; + clock-names = "d_audio", "apbif"; + resets = <&tegra_car 106>, /* d_audio */ + <&tegra_car 107>, /* apbif */ + <&tegra_car 30>, /* i2s0 */ + <&tegra_car 11>, /* i2s1 */ + <&tegra_car 18>, /* i2s2 */ + <&tegra_car 101>, /* i2s3 */ + <&tegra_car 102>, /* i2s4 */ + <&tegra_car 108>, /* dam0 */ + <&tegra_car 109>, /* dam1 */ + <&tegra_car 110>, /* dam2 */ + <&tegra_car 10>, /* spdif */ + <&tegra_car 153>, /* amx */ + <&tegra_car 185>, /* amx1 */ + <&tegra_car 154>, /* adx */ + <&tegra_car 180>, /* adx1 */ + <&tegra_car 186>, /* afc0 */ + <&tegra_car 187>, /* afc1 */ + <&tegra_car 188>, /* afc2 */ + <&tegra_car 189>, /* afc3 */ + <&tegra_car 190>, /* afc4 */ + <&tegra_car 191>; /* afc5 */ + reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", + "i2s3", "i2s4", "dam0", "dam1", "dam2", + "spdif", "amx", "amx1", "adx", "adx1", + "afc0", "afc1", "afc2", "afc3", "afc4", "afc5"; + dmas = <&apbdma 1>, <&apbdma 1>, + <&apbdma 2>, <&apbdma 2>, + <&apbdma 3>, <&apbdma 3>, + <&apbdma 4>, <&apbdma 4>, + <&apbdma 6>, <&apbdma 6>, + <&apbdma 7>, <&apbdma 7>, + <&apbdma 12>, <&apbdma 12>, + <&apbdma 13>, <&apbdma 13>, + <&apbdma 14>, <&apbdma 14>, + <&apbdma 29>, <&apbdma 29>; + dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", + "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", + "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", + "rx9", "tx9"; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + tegra_i2s0: i2s@70301000 { + compatible = "nvidia,tegra124-i2s"; + reg = <0x70301000 0x100>; + nvidia,ahub-cif-ids = <4 4>; + clocks = <&tegra_car TEGRA124_CLK_I2S0>; + resets = <&tegra_car 30>; + reset-names = "i2s"; + status = "disabled"; + }; + + tegra_i2s1: i2s@70301100 { + compatible = "nvidia,tegra124-i2s"; + reg = <0x70301100 0x100>; + nvidia,ahub-cif-ids = <5 5>; + clocks = <&tegra_car TEGRA124_CLK_I2S1>; + resets = <&tegra_car 11>; + reset-names = "i2s"; + status = "disabled"; + }; + + tegra_i2s2: i2s@70301200 { + compatible = "nvidia,tegra124-i2s"; + reg = <0x70301200 0x100>; + nvidia,ahub-cif-ids = <6 6>; + clocks = <&tegra_car TEGRA124_CLK_I2S2>; + resets = <&tegra_car 18>; + reset-names = "i2s"; + status = "disabled"; + }; + + tegra_i2s3: i2s@70301300 { + compatible = "nvidia,tegra124-i2s"; + reg = <0x70301300 0x100>; + nvidia,ahub-cif-ids = <7 7>; + clocks = <&tegra_car TEGRA124_CLK_I2S3>; + resets = <&tegra_car 101>; + reset-names = "i2s"; + status = "disabled"; + }; + + tegra_i2s4: i2s@70301400 { + compatible = "nvidia,tegra124-i2s"; + reg = <0x70301400 0x100>; + nvidia,ahub-cif-ids = <8 8>; + clocks = <&tegra_car TEGRA124_CLK_I2S4>; + resets = <&tegra_car 102>; + reset-names = "i2s"; + status = "disabled"; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; -- cgit v1.1 From b0e1caeeddea4fffb22a54b62e58d23e52ec6a62 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 3 Dec 2013 17:26:12 -0700 Subject: ARM: tegra: add sound card to Venice2 DT Venice2 uses the MAX98090 audio CODEC, and supports built-in speakers, and a combo headphones/microphone jack. Add a top-level sound card node to represent this. Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124-venice2.dts | 35 ++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 3d6ba4b..441b753 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -17,6 +17,13 @@ i2c@7000c000 { status = "okay"; clock-frequency = <100000>; + + acodec: audio-codec@10 { + compatible = "maxim,max98090"; + reg = <0x10>; + interrupt-parent = <&gpio>; + interrupts = ; + }; }; i2c@7000c400 { @@ -62,6 +69,12 @@ bus-width = <8>; }; + ahub@70300000 { + i2s@70301100 { + status = "okay"; + }; + }; + clocks { compatible = "simple-bus"; #address-cells = <1>; @@ -74,4 +87,26 @@ clock-frequency = <32768>; }; }; + + sound { + compatible = "nvidia,tegra-audio-max98090-venice2", + "nvidia,tegra-audio-max98090"; + nvidia,model = "NVIDIA Tegra Venice2"; + + nvidia,audio-routing = + "Headphones", "HPR", + "Headphones", "HPL", + "Speakers", "SPKR", + "Speakers", "SPKL", + "Mic Jack", "MICBIAS", + "IN34", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&acodec>; + + clocks = <&tegra_car TEGRA124_CLK_PLL_A>, + <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA124_CLK_EXTERN1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + }; }; -- cgit v1.1 From 111a1fc2a721187657e4fc49d4ab9039f6a662f4 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 18 Nov 2013 17:00:34 +0100 Subject: ARM: tegra: Add Tegra124 PWM support The PWM controller on Tegra124 is the same as the one on earlier SoC generations. Signed-off-by: Thierry Reding [swarren, added reset properties] Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index a68aa33..45d8f11 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -176,6 +176,16 @@ status = "disabled"; }; + pwm@7000a000 { + compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; + reg = <0x7000a000 0x100>; + #pwm-cells = <2>; + clocks = <&tegra_car TEGRA124_CLK_PWM>; + resets = <&tegra_car 17>; + reset-names = "pwm"; + status = "disabled"; + }; + i2c@7000c000 { compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; reg = <0x7000c000 0x100>; -- cgit v1.1 From e013485d12456e83838687cb779aebf366fd4fa1 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 18 Nov 2013 17:00:35 +0100 Subject: ARM: tegra: Enable PWM on Venice2 Subsequent patches will need to reference a PWM channel for backlight support, so enable the PWM device and assign a label to it. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124-venice2.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 441b753..7302e7d 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -14,6 +14,10 @@ status = "okay"; }; + pwm: pwm@7000a000 { + status = "okay"; + }; + i2c@7000c000 { status = "okay"; clock-frequency = <100000>; -- cgit v1.1 From 6bccbd5e18f65ca57b509ad25c9a8b0ad208627e Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Mon, 2 Dec 2013 18:39:57 +0530 Subject: ARM: tegra: convert device tree files to use key defines Use key code macros for all key code refernced for keys. For tegra20-seaboard.dts and tegra20-harmony.dts: The key comment for key (16th row and 1st column) is KEY_KPSLASH but code is 0x004e which is the key code for KEY_KPPLUS. As there other key exist with KY_KPPLUS, I am assuming key code is wrong and comment is fine. With this assumption, I am keeping the key code as KEY_KPSLASH. Signed-off-by: Laxman Dewangan Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra20-harmony.dts | 221 +++++++++++++-------------- arch/arm/boot/dts/tegra20-paz00.dts | 3 +- arch/arm/boot/dts/tegra20-seaboard.dts | 261 ++++++++++++++++---------------- arch/arm/boot/dts/tegra20-trimslice.dts | 3 +- arch/arm/boot/dts/tegra20-ventana.dts | 3 +- arch/arm/boot/dts/tegra20-whistler.dts | 9 +- 6 files changed, 253 insertions(+), 247 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index 94d2189..7e578f4 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -1,5 +1,6 @@ /dts-v1/; +#include #include "tegra20.dtsi" / { @@ -421,115 +422,115 @@ nvidia,repeat-delay-ms = <160>; nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>; - linux,keymap = <0x00020011 /* KEY_W */ - 0x0003001F /* KEY_S */ - 0x0004001E /* KEY_A */ - 0x0005002C /* KEY_Z */ - 0x000701D0 /* KEY_FN */ - 0x0107008B /* KEY_MENU */ - 0x02060038 /* KEY_LEFTALT */ - 0x02070064 /* KEY_RIGHTALT */ - 0x03000006 /* KEY_5 */ - 0x03010005 /* KEY_4 */ - 0x03020013 /* KEY_R */ - 0x03030012 /* KEY_E */ - 0x03040021 /* KEY_F */ - 0x03050020 /* KEY_D */ - 0x0306002D /* KEY_X */ - 0x04000008 /* KEY_7 */ - 0x04010007 /* KEY_6 */ - 0x04020014 /* KEY_T */ - 0x04030023 /* KEY_H */ - 0x04040022 /* KEY_G */ - 0x0405002F /* KEY_V */ - 0x0406002E /* KEY_C */ - 0x04070039 /* KEY_SPACE */ - 0x0500000A /* KEY_9 */ - 0x05010009 /* KEY_8 */ - 0x05020016 /* KEY_U */ - 0x05030015 /* KEY_Y */ - 0x05040024 /* KEY_J */ - 0x05050031 /* KEY_N */ - 0x05060030 /* KEY_B */ - 0x0507002B /* KEY_BACKSLASH */ - 0x0600000C /* KEY_MINUS */ - 0x0601000B /* KEY_0 */ - 0x06020018 /* KEY_O */ - 0x06030017 /* KEY_I */ - 0x06040026 /* KEY_L */ - 0x06050025 /* KEY_K */ - 0x06060033 /* KEY_COMMA */ - 0x06070032 /* KEY_M */ - 0x0701000D /* KEY_EQUAL */ - 0x0702001B /* KEY_RIGHTBRACE */ - 0x0703001C /* KEY_ENTER */ - 0x0707008B /* KEY_MENU */ - 0x0804002A /* KEY_LEFTSHIFT */ - 0x08050036 /* KEY_RIGHTSHIFT */ - 0x0905001D /* KEY_LEFTCTRL */ - 0x09070061 /* KEY_RIGHTCTRL */ - 0x0B00001A /* KEY_LEFTBRACE */ - 0x0B010019 /* KEY_P */ - 0x0B020028 /* KEY_APOSTROPHE */ - 0x0B030027 /* KEY_SEMICOLON */ - 0x0B040035 /* KEY_SLASH */ - 0x0B050034 /* KEY_DOT */ - 0x0C000044 /* KEY_F10 */ - 0x0C010043 /* KEY_F9 */ - 0x0C02000E /* KEY_BACKSPACE */ - 0x0C030004 /* KEY_3 */ - 0x0C040003 /* KEY_2 */ - 0x0C050067 /* KEY_UP */ - 0x0C0600D2 /* KEY_PRINT */ - 0x0C070077 /* KEY_PAUSE */ - 0x0D00006E /* KEY_INSERT */ - 0x0D01006F /* KEY_DELETE */ - 0x0D030068 /* KEY_PAGEUP */ - 0x0D04006D /* KEY_PAGEDOWN */ - 0x0D05006A /* KEY_RIGHT */ - 0x0D06006C /* KEY_DOWN */ - 0x0D070069 /* KEY_LEFT */ - 0x0E000057 /* KEY_F11 */ - 0x0E010058 /* KEY_F12 */ - 0x0E020042 /* KEY_F8 */ - 0x0E030010 /* KEY_Q */ - 0x0E04003E /* KEY_F4 */ - 0x0E05003D /* KEY_F3 */ - 0x0E060002 /* KEY_1 */ - 0x0E070041 /* KEY_F7 */ - 0x0F000001 /* KEY_ESC */ - 0x0F010029 /* KEY_GRAVE */ - 0x0F02003F /* KEY_F5 */ - 0x0F03000F /* KEY_TAB */ - 0x0F04003B /* KEY_F1 */ - 0x0F05003C /* KEY_F2 */ - 0x0F06003A /* KEY_CAPSLOCK */ - 0x0F070040 /* KEY_F6 */ - 0x14000047 /* KEY_KP7 */ - 0x15000049 /* KEY_KP9 */ - 0x15010048 /* KEY_KP8 */ - 0x1502004B /* KEY_KP4 */ - 0x1504004F /* KEY_KP1 */ - 0x1601004E /* KEY_KPSLASH */ - 0x1602004D /* KEY_KP6 */ - 0x1603004C /* KEY_KP5 */ - 0x16040051 /* KEY_KP3 */ - 0x16050050 /* KEY_KP2 */ - 0x16070052 /* KEY_KP0 */ - 0x1B010037 /* KEY_KPASTERISK */ - 0x1B03004A /* KEY_KPMINUS */ - 0x1B04004E /* KEY_KPPLUS */ - 0x1B050053 /* KEY_KPDOT */ - 0x1C050073 /* KEY_VOLUMEUP */ - 0x1D030066 /* KEY_HOME */ - 0x1D04006B /* KEY_END */ - 0x1D0500E1 /* KEY_BRIGHTNESSUP */ - 0x1D060072 /* KEY_VOLUMEDOWN */ - 0x1D0700E0 /* KEY_BRIGHTNESSDOWN */ - 0x1E000045 /* KEY_NUMLOCK */ - 0x1E010046 /* KEY_SCROLLLOCK */ - 0x1E020071 /* KEY_MUTE */ - 0x1F0400D6>; /* KEY_QUESTION */ + linux,keymap = ; }; pmc@7000e400 { @@ -619,7 +620,7 @@ power { label = "Power"; gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - linux,code = <116>; /* KEY_POWER */ + linux,code = ; gpio-key,wakeup; }; }; diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 4b961b1..31c14d0 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -1,5 +1,6 @@ /dts-v1/; +#include #include "tegra20.dtsi" / { @@ -488,7 +489,7 @@ power { label = "Power"; gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>; - linux,code = <116>; /* KEY_POWER */ + linux,code = ; gpio-key,wakeup; }; }; diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index 07ff55a..476e4e8 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -1,5 +1,6 @@ /dts-v1/; +#include #include "tegra20.dtsi" / { @@ -523,137 +524,137 @@ nvidia,ghost-filter; nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>; - linux,keymap = <0x00020011 /* KEY_W */ - 0x0003001F /* KEY_S */ - 0x0004001E /* KEY_A */ - 0x0005002C /* KEY_Z */ - 0x000701d0 /* KEY_FN */ - - 0x0107007D /* KEY_LEFTMETA */ - 0x02060064 /* KEY_RIGHTALT */ - 0x02070038 /* KEY_LEFTALT */ - - 0x03000006 /* KEY_5 */ - 0x03010005 /* KEY_4 */ - 0x03020013 /* KEY_R */ - 0x03030012 /* KEY_E */ - 0x03040021 /* KEY_F */ - 0x03050020 /* KEY_D */ - 0x0306002D /* KEY_X */ - - 0x04000008 /* KEY_7 */ - 0x04010007 /* KEY_6 */ - 0x04020014 /* KEY_T */ - 0x04030023 /* KEY_H */ - 0x04040022 /* KEY_G */ - 0x0405002F /* KEY_V */ - 0x0406002E /* KEY_C */ - 0x04070039 /* KEY_SPACE */ - - 0x0500000A /* KEY_9 */ - 0x05010009 /* KEY_8 */ - 0x05020016 /* KEY_U */ - 0x05030015 /* KEY_Y */ - 0x05040024 /* KEY_J */ - 0x05050031 /* KEY_N */ - 0x05060030 /* KEY_B */ - 0x0507002B /* KEY_BACKSLASH */ - - 0x0600000C /* KEY_MINUS */ - 0x0601000B /* KEY_0 */ - 0x06020018 /* KEY_O */ - 0x06030017 /* KEY_I */ - 0x06040026 /* KEY_L */ - 0x06050025 /* KEY_K */ - 0x06060033 /* KEY_COMMA */ - 0x06070032 /* KEY_M */ - - 0x0701000D /* KEY_EQUAL */ - 0x0702001B /* KEY_RIGHTBRACE */ - 0x0703001C /* KEY_ENTER */ - 0x0707008B /* KEY_MENU */ - - 0x08040036 /* KEY_RIGHTSHIFT */ - 0x0805002A /* KEY_LEFTSHIFT */ - - 0x09050061 /* KEY_RIGHTCTRL */ - 0x0907001D /* KEY_LEFTCTRL */ - - 0x0B00001A /* KEY_LEFTBRACE */ - 0x0B010019 /* KEY_P */ - 0x0B020028 /* KEY_APOSTROPHE */ - 0x0B030027 /* KEY_SEMICOLON */ - 0x0B040035 /* KEY_SLASH */ - 0x0B050034 /* KEY_DOT */ - - 0x0C000044 /* KEY_F10 */ - 0x0C010043 /* KEY_F9 */ - 0x0C02000E /* KEY_BACKSPACE */ - 0x0C030004 /* KEY_3 */ - 0x0C040003 /* KEY_2 */ - 0x0C050067 /* KEY_UP */ - 0x0C0600D2 /* KEY_PRINT */ - 0x0C070077 /* KEY_PAUSE */ - - 0x0D00006E /* KEY_INSERT */ - 0x0D01006F /* KEY_DELETE */ - 0x0D030068 /* KEY_PAGEUP */ - 0x0D04006D /* KEY_PAGEDOWN */ - 0x0D05006A /* KEY_RIGHT */ - 0x0D06006C /* KEY_DOWN */ - 0x0D070069 /* KEY_LEFT */ - - 0x0E000057 /* KEY_F11 */ - 0x0E010058 /* KEY_F12 */ - 0x0E020042 /* KEY_F8 */ - 0x0E030010 /* KEY_Q */ - 0x0E04003E /* KEY_F4 */ - 0x0E05003D /* KEY_F3 */ - 0x0E060002 /* KEY_1 */ - 0x0E070041 /* KEY_F7 */ - - 0x0F000001 /* KEY_ESC */ - 0x0F010029 /* KEY_GRAVE */ - 0x0F02003F /* KEY_F5 */ - 0x0F03000F /* KEY_TAB */ - 0x0F04003B /* KEY_F1 */ - 0x0F05003C /* KEY_F2 */ - 0x0F06003A /* KEY_CAPSLOCK */ - 0x0F070040 /* KEY_F6 */ + linux,keymap = ; /* KEY_HELP */ + MATRIX_KEY(0x14, 0x00, KEY_KP7) + + MATRIX_KEY(0x15, 0x00, KEY_KP9) + MATRIX_KEY(0x15, 0x01, KEY_KP8) + MATRIX_KEY(0x15, 0x02, KEY_KP4) + MATRIX_KEY(0x15, 0x04, KEY_KP1) + + MATRIX_KEY(0x16, 0x01, KEY_KPSLASH) + MATRIX_KEY(0x16, 0x02, KEY_KP6) + MATRIX_KEY(0x16, 0x03, KEY_KP5) + MATRIX_KEY(0x16, 0x04, KEY_KP3) + MATRIX_KEY(0x16, 0x05, KEY_KP2) + MATRIX_KEY(0x16, 0x07, KEY_KP0) + + MATRIX_KEY(0x1B, 0x01, KEY_KPASTERISK) + MATRIX_KEY(0x1B, 0x03, KEY_KPMINUS) + MATRIX_KEY(0x1B, 0x04, KEY_KPPLUS) + MATRIX_KEY(0x1B, 0x05, KEY_KPDOT) + + MATRIX_KEY(0x1C, 0x05, KEY_VOLUMEUP) + + MATRIX_KEY(0x1D, 0x03, KEY_HOME) + MATRIX_KEY(0x1D, 0x04, KEY_END) + MATRIX_KEY(0x1D, 0x05, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x1D, 0x06, KEY_VOLUMEDOWN) + MATRIX_KEY(0x1D, 0x07, KEY_BRIGHTNESSUP) + + MATRIX_KEY(0x1E, 0x00, KEY_NUMLOCK) + MATRIX_KEY(0x1E, 0x01, KEY_SCROLLLOCK) + MATRIX_KEY(0x1E, 0x02, KEY_MUTE) + + MATRIX_KEY(0x1F, 0x04, KEY_HELP)>; }; pmc@7000e400 { @@ -775,7 +776,7 @@ power { label = "Power"; gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - linux,code = <116>; /* KEY_POWER */ + linux,code = ; gpio-key,wakeup; }; diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index eab7cd2..babc8fb 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -1,5 +1,6 @@ /dts-v1/; +#include #include "tegra20.dtsi" / { @@ -380,7 +381,7 @@ power { label = "Power"; gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>; - linux,code = <116>; /* KEY_POWER */ + linux,code = ; gpio-key,wakeup; }; }; diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index bce7640..323ad64 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -1,5 +1,6 @@ /dts-v1/; +#include #include "tegra20.dtsi" / { @@ -570,7 +571,7 @@ power { label = "Power"; gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - linux,code = <116>; /* KEY_POWER */ + linux,code = ; gpio-key,wakeup; }; }; diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts index 82037fe..00ba97a 100644 --- a/arch/arm/boot/dts/tegra20-whistler.dts +++ b/arch/arm/boot/dts/tegra20-whistler.dts @@ -1,5 +1,6 @@ /dts-v1/; +#include #include "tegra20.dtsi" / { @@ -502,10 +503,10 @@ nvidia,kbc-row-pins = <0 1 2>; nvidia,kbc-col-pins = <16 17>; nvidia,wakeup-source; - linux,keymap = <0x00000074 /* KEY_POWER */ - 0x01000066 /* KEY_HOME */ - 0x0101009E /* KEY_BACK */ - 0x0201008B>; /* KEY_MENU */ + linux,keymap = ; }; pmc@7000e400 { -- cgit v1.1 From 5fc6b0dd319c5b726b4cad379bea6ddd3b4a380f Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Thu, 5 Dec 2013 16:14:07 +0530 Subject: ARM: tegra: convert dts files of Tegra114 platforms to use pinctrl defines Use Tegra pinconrol dt-binding macro to set the values of different pinmux properties of Tegra114 platforms. Signed-off-by: Laxman Dewangan Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra114-dalmore.dts | 548 ++++++++++++++++----------------- arch/arm/boot/dts/tegra114.dtsi | 1 + 2 files changed, 275 insertions(+), 274 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index 5d2d6f6..88be40c 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -19,41 +19,41 @@ clk1_out_pw4 { nvidia,pins = "clk1_out_pw4"; nvidia,function = "extperiph1"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; dap1_din_pn1 { nvidia,pins = "dap1_din_pn1"; nvidia,function = "i2s0"; - nvidia,pull = <0>; - nvidia,tristate = <1>; - nvidia,enable-input = <1>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; dap1_dout_pn2 { nvidia,pins = "dap1_dout_pn2", "dap1_fs_pn0", "dap1_sclk_pn3"; nvidia,function = "i2s0"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; dap2_din_pa4 { nvidia,pins = "dap2_din_pa4"; nvidia,function = "i2s1"; - nvidia,pull = <0>; - nvidia,tristate = <1>; - nvidia,enable-input = <1>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; dap2_dout_pa5 { nvidia,pins = "dap2_dout_pa5", "dap2_fs_pa2", "dap2_sclk_pa3"; nvidia,function = "i2s1"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; dap4_din_pp5 { nvidia,pins = "dap4_din_pp5", @@ -61,17 +61,17 @@ "dap4_fs_pp4", "dap4_sclk_pp7"; nvidia,function = "i2s3"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; dvfs_pwm_px0 { nvidia,pins = "dvfs_pwm_px0", "dvfs_clk_px2"; nvidia,function = "cldvfs"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; ulpi_clk_py0 { nvidia,pins = "ulpi_clk_py0", @@ -84,128 +84,128 @@ "ulpi_data6_po7", "ulpi_data7_po0"; nvidia,function = "ulpi"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; ulpi_dir_py1 { nvidia,pins = "ulpi_dir_py1", "ulpi_nxt_py2"; nvidia,function = "ulpi"; - nvidia,pull = <0>; - nvidia,tristate = <1>; - nvidia,enable-input = <1>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; ulpi_stp_py3 { nvidia,pins = "ulpi_stp_py3"; nvidia,function = "ulpi"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; cam_i2c_scl_pbb1 { nvidia,pins = "cam_i2c_scl_pbb1", "cam_i2c_sda_pbb2"; nvidia,function = "i2c3"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - nvidia,lock = <0>; - nvidia,open-drain = <0>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = ; + nvidia,open-drain = ; }; cam_mclk_pcc0 { nvidia,pins = "cam_mclk_pcc0", "pbb0"; nvidia,function = "vi_alt3"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; - nvidia,lock = <0>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = ; }; gen2_i2c_scl_pt5 { nvidia,pins = "gen2_i2c_scl_pt5", "gen2_i2c_sda_pt6"; nvidia,function = "i2c2"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - nvidia,lock = <0>; - nvidia,open-drain = <0>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = ; + nvidia,open-drain = ; }; gmi_a16_pj7 { nvidia,pins = "gmi_a16_pj7"; nvidia,function = "uartd"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; gmi_a17_pb0 { nvidia,pins = "gmi_a17_pb0", "gmi_a18_pb1"; nvidia,function = "uartd"; - nvidia,pull = <0>; - nvidia,tristate = <1>; - nvidia,enable-input = <1>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; gmi_a19_pk7 { nvidia,pins = "gmi_a19_pk7"; nvidia,function = "uartd"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; gmi_ad5_pg5 { nvidia,pins = "gmi_ad5_pg5", "gmi_cs6_n_pi3", "gmi_wr_n_pi0"; nvidia,function = "spi4"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; gmi_ad6_pg6 { nvidia,pins = "gmi_ad6_pg6", "gmi_ad7_pg7"; nvidia,function = "spi4"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; gmi_ad12_ph4 { nvidia,pins = "gmi_ad12_ph4"; nvidia,function = "rsvd4"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; gmi_ad9_ph1 { nvidia,pins = "gmi_ad9_ph1"; nvidia,function = "pwm1"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; gmi_cs1_n_pj2 { nvidia,pins = "gmi_cs1_n_pj2", "gmi_oe_n_pi1"; nvidia,function = "soc"; - nvidia,pull = <0>; - nvidia,tristate = <1>; - nvidia,enable-input = <1>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; clk2_out_pw5 { nvidia,pins = "clk2_out_pw5"; nvidia,function = "extperiph2"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; sdmmc1_clk_pz0 { nvidia,pins = "sdmmc1_clk_pz0"; nvidia,function = "sdmmc1"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; sdmmc1_cmd_pz1 { nvidia,pins = "sdmmc1_cmd_pz1", @@ -214,23 +214,23 @@ "sdmmc1_dat2_py5", "sdmmc1_dat3_py4"; nvidia,function = "sdmmc1"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; sdmmc1_wp_n_pv3 { nvidia,pins = "sdmmc1_wp_n_pv3"; nvidia,function = "spi4"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; sdmmc3_clk_pa6 { nvidia,pins = "sdmmc3_clk_pa6"; nvidia,function = "sdmmc3"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; sdmmc3_cmd_pa7 { nvidia,pins = "sdmmc3_cmd_pa7", @@ -242,16 +242,16 @@ "sdmmc3_clk_lb_out_pee4", "sdmmc3_clk_lb_in_pee5"; nvidia,function = "sdmmc3"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; sdmmc4_clk_pcc4 { nvidia,pins = "sdmmc4_clk_pcc4"; nvidia,function = "sdmmc4"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; sdmmc4_cmd_pt7 { nvidia,pins = "sdmmc4_cmd_pt7", @@ -264,16 +264,16 @@ "sdmmc4_dat6_paa6", "sdmmc4_dat7_paa7"; nvidia,function = "sdmmc4"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; clk_32k_out_pa0 { nvidia,pins = "clk_32k_out_pa0"; nvidia,function = "blink"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; kb_col0_pq0 { nvidia,pins = "kb_col0_pq0", @@ -283,265 +283,265 @@ "kb_row1_pr1", "kb_row2_pr2"; nvidia,function = "kbc"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; dap3_din_pp1 { nvidia,pins = "dap3_din_pp1", "dap3_sclk_pp3"; nvidia,function = "displayb"; - nvidia,pull = <0>; - nvidia,tristate = <1>; - nvidia,enable-input = <0>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; pv0 { nvidia,pins = "pv0"; nvidia,function = "rsvd4"; - nvidia,pull = <0>; - nvidia,tristate = <1>; - nvidia,enable-input = <0>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; kb_row7_pr7 { nvidia,pins = "kb_row7_pr7"; nvidia,function = "rsvd2"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; kb_row10_ps2 { nvidia,pins = "kb_row10_ps2"; nvidia,function = "uarta"; - nvidia,pull = <0>; - nvidia,tristate = <1>; - nvidia,enable-input = <1>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; kb_row9_ps1 { nvidia,pins = "kb_row9_ps1"; nvidia,function = "uarta"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; pwr_i2c_scl_pz6 { nvidia,pins = "pwr_i2c_scl_pz6", "pwr_i2c_sda_pz7"; nvidia,function = "i2cpwr"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - nvidia,lock = <0>; - nvidia,open-drain = <0>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = ; + nvidia,open-drain = ; }; sys_clk_req_pz5 { nvidia,pins = "sys_clk_req_pz5"; nvidia,function = "sysclk"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; core_pwr_req { nvidia,pins = "core_pwr_req"; nvidia,function = "pwron"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; cpu_pwr_req { nvidia,pins = "cpu_pwr_req"; nvidia,function = "cpu"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; pwr_int_n { nvidia,pins = "pwr_int_n"; nvidia,function = "pmi"; - nvidia,pull = <0>; - nvidia,tristate = <1>; - nvidia,enable-input = <1>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; reset_out_n { nvidia,pins = "reset_out_n"; nvidia,function = "reset_out_n"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; clk3_out_pee0 { nvidia,pins = "clk3_out_pee0"; nvidia,function = "extperiph3"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; gen1_i2c_scl_pc4 { nvidia,pins = "gen1_i2c_scl_pc4", "gen1_i2c_sda_pc5"; nvidia,function = "i2c1"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - nvidia,lock = <0>; - nvidia,open-drain = <0>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = ; + nvidia,open-drain = ; }; uart2_cts_n_pj5 { nvidia,pins = "uart2_cts_n_pj5"; nvidia,function = "uartb"; - nvidia,pull = <0>; - nvidia,tristate = <1>; - nvidia,enable-input = <1>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; uart2_rts_n_pj6 { nvidia,pins = "uart2_rts_n_pj6"; nvidia,function = "uartb"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; uart2_rxd_pc3 { nvidia,pins = "uart2_rxd_pc3"; nvidia,function = "irda"; - nvidia,pull = <0>; - nvidia,tristate = <1>; - nvidia,enable-input = <1>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; uart2_txd_pc2 { nvidia,pins = "uart2_txd_pc2"; nvidia,function = "irda"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; uart3_cts_n_pa1 { nvidia,pins = "uart3_cts_n_pa1", "uart3_rxd_pw7"; nvidia,function = "uartc"; - nvidia,pull = <0>; - nvidia,tristate = <1>; - nvidia,enable-input = <1>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; uart3_rts_n_pc0 { nvidia,pins = "uart3_rts_n_pc0", "uart3_txd_pw6"; nvidia,function = "uartc"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; owr { nvidia,pins = "owr"; nvidia,function = "owr"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; hdmi_cec_pee3 { nvidia,pins = "hdmi_cec_pee3"; nvidia,function = "cec"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - nvidia,lock = <0>; - nvidia,open-drain = <0>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = ; + nvidia,open-drain = ; }; ddc_scl_pv4 { nvidia,pins = "ddc_scl_pv4", "ddc_sda_pv5"; nvidia,function = "i2c4"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - nvidia,lock = <0>; - nvidia,rcv-sel = <1>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = ; + nvidia,rcv-sel = ; }; spdif_in_pk6 { nvidia,pins = "spdif_in_pk6"; nvidia,function = "usb"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - nvidia,lock = <0>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = ; }; usb_vbus_en0_pn4 { nvidia,pins = "usb_vbus_en0_pn4"; nvidia,function = "usb"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; - nvidia,lock = <0>; - nvidia,open-drain = <1>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = ; + nvidia,open-drain = ; }; gpio_x6_aud_px6 { nvidia,pins = "gpio_x6_aud_px6"; nvidia,function = "spi6"; - nvidia,pull = <2>; - nvidia,tristate = <1>; - nvidia,enable-input = <1>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; gpio_x4_aud_px4 { nvidia,pins = "gpio_x4_aud_px4", "gpio_x7_aud_px7"; nvidia,function = "rsvd1"; - nvidia,pull = <1>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; gpio_x5_aud_px5 { nvidia,pins = "gpio_x5_aud_px5"; nvidia,function = "rsvd1"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; gpio_w2_aud_pw2 { nvidia,pins = "gpio_w2_aud_pw2"; nvidia,function = "rsvd2"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; gpio_w3_aud_pw3 { nvidia,pins = "gpio_w3_aud_pw3"; nvidia,function = "spi6"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; gpio_x1_aud_px1 { nvidia,pins = "gpio_x1_aud_px1"; nvidia,function = "rsvd4"; - nvidia,pull = <1>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; gpio_x3_aud_px3 { nvidia,pins = "gpio_x3_aud_px3"; nvidia,function = "rsvd4"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; dap3_fs_pp0 { nvidia,pins = "dap3_fs_pp0"; nvidia,function = "i2s2"; - nvidia,pull = <1>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; dap3_dout_pp2 { nvidia,pins = "dap3_dout_pp2"; nvidia,function = "i2s2"; - nvidia,pull = <1>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; pv1 { nvidia,pins = "pv1"; nvidia,function = "rsvd1"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; pbb3 { nvidia,pins = "pbb3", @@ -549,25 +549,25 @@ "pbb6", "pbb7"; nvidia,function = "rsvd4"; - nvidia,pull = <1>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; pcc1 { nvidia,pins = "pcc1", "pcc2"; nvidia,function = "rsvd4"; - nvidia,pull = <1>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; gmi_ad0_pg0 { nvidia,pins = "gmi_ad0_pg0", "gmi_ad1_pg1"; nvidia,function = "gmi"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; gmi_ad10_ph2 { nvidia,pins = "gmi_ad10_ph2", @@ -576,17 +576,17 @@ "gmi_ad8_ph0", "gmi_clk_pk1"; nvidia,function = "gmi"; - nvidia,pull = <1>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; gmi_ad2_pg2 { nvidia,pins = "gmi_ad2_pg2", "gmi_ad3_pg3"; nvidia,function = "gmi"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; gmi_adv_n_pk0 { nvidia,pins = "gmi_adv_n_pk0", @@ -598,39 +598,39 @@ "gmi_iordy_pi5", "gmi_wp_n_pc7"; nvidia,function = "gmi"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; gmi_cs3_n_pk4 { nvidia,pins = "gmi_cs3_n_pk4"; nvidia,function = "gmi"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; clk2_req_pcc5 { nvidia,pins = "clk2_req_pcc5"; nvidia,function = "rsvd4"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; kb_col3_pq3 { nvidia,pins = "kb_col3_pq3", "kb_col6_pq6", "kb_col7_pq7"; nvidia,function = "kbc"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; kb_col5_pq5 { nvidia,pins = "kb_col5_pq5"; nvidia,function = "kbc"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; kb_row3_pr3 { nvidia,pins = "kb_row3_pr3", @@ -638,77 +638,77 @@ "kb_row6_pr6", "kb_row8_ps0"; nvidia,function = "kbc"; - nvidia,pull = <1>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; clk3_req_pee1 { nvidia,pins = "clk3_req_pee1"; nvidia,function = "rsvd4"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; pu4 { nvidia,pins = "pu4"; nvidia,function = "displayb"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <0>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; pu5 { nvidia,pins = "pu5", "pu6"; nvidia,function = "displayb"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; hdmi_int_pn7 { nvidia,pins = "hdmi_int_pn7"; nvidia,function = "rsvd1"; - nvidia,pull = <1>; - nvidia,tristate = <0>; - nvidia,enable-input = <1>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; clk1_req_pee2 { nvidia,pins = "clk1_req_pee2", "usb_vbus_en1_pn5"; nvidia,function = "rsvd4"; - nvidia,pull = <1>; - nvidia,tristate = <1>; - nvidia,enable-input = <0>; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; drive_sdio1 { nvidia,pins = "drive_sdio1"; - nvidia,high-speed-mode = <1>; - nvidia,schmitt = <0>; - nvidia,low-power-mode = <3>; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,low-power-mode = ; nvidia,pull-down-strength = <36>; nvidia,pull-up-strength = <20>; - nvidia,slew-rate-rising = <2>; - nvidia,slew-rate-falling = <2>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; }; drive_sdio3 { nvidia,pins = "drive_sdio3"; - nvidia,high-speed-mode = <1>; - nvidia,schmitt = <0>; - nvidia,low-power-mode = <3>; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,low-power-mode = ; nvidia,pull-down-strength = <22>; nvidia,pull-up-strength = <36>; - nvidia,slew-rate-rising = <0>; - nvidia,slew-rate-falling = <0>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; }; drive_gma { nvidia,pins = "drive_gma"; - nvidia,high-speed-mode = <1>; - nvidia,schmitt = <0>; - nvidia,low-power-mode = <3>; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,low-power-mode = ; nvidia,pull-down-strength = <2>; nvidia,pull-up-strength = <1>; - nvidia,slew-rate-rising = <0>; - nvidia,slew-rate-falling = <0>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; nvidia,drive-type = <1>; }; }; diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 8fdf8d5..ae855ec 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -1,5 +1,6 @@ #include #include +#include #include #include "skeleton.dtsi" -- cgit v1.1 From ba4104e79470ae848a9f38029fe1371790dc0df9 Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Thu, 5 Dec 2013 16:14:08 +0530 Subject: ARM: tegra: convert dts files of Tegra20 platforms to use pinctrl defines Use Tegra pinconrol dt-binding macro to set the values of different pinmux properties of Tegra20 platforms. Signed-off-by: Laxman Dewangan Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra20-colibri-512.dtsi | 104 ++++++++++++++--------------- arch/arm/boot/dts/tegra20-harmony.dts | 30 ++++----- arch/arm/boot/dts/tegra20-iris-512.dts | 10 +-- arch/arm/boot/dts/tegra20-paz00.dts | 30 ++++----- arch/arm/boot/dts/tegra20-seaboard.dts | 44 ++++++------ arch/arm/boot/dts/tegra20-tamonten.dtsi | 30 ++++----- arch/arm/boot/dts/tegra20-trimslice.dts | 34 +++++----- arch/arm/boot/dts/tegra20-ventana.dts | 44 ++++++------ arch/arm/boot/dts/tegra20-whistler.dts | 40 +++++------ arch/arm/boot/dts/tegra20.dtsi | 1 + 10 files changed, 184 insertions(+), 183 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi index 78f7e91..7792637 100644 --- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi @@ -27,20 +27,20 @@ audio_refclk { nvidia,pins = "cdev1"; nvidia,function = "plla_out"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = ; + nvidia,tristate = ; }; crt { nvidia,pins = "crtp"; nvidia,function = "crt"; - nvidia,pull = <0>; - nvidia,tristate = <1>; + nvidia,pull = ; + nvidia,tristate = ; }; dap3 { nvidia,pins = "dap3"; nvidia,function = "dap3"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = ; + nvidia,tristate = ; }; displaya { nvidia,pins = "ld0", "ld1", "ld2", "ld3", @@ -50,151 +50,151 @@ "lhs", "lpw0", "lpw2", "lsc0", "lsc1", "lsck", "lsda", "lspi", "lvs"; nvidia,function = "displaya"; - nvidia,tristate = <1>; + nvidia,tristate = ; }; gpio_dte { nvidia,pins = "dte"; nvidia,function = "rsvd1"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = ; + nvidia,tristate = ; }; gpio_gmi { nvidia,pins = "ata", "atc", "atd", "ate", "dap1", "dap2", "dap4", "gpu", "irrx", "irtx", "spia", "spib", "spic"; nvidia,function = "gmi"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = ; + nvidia,tristate = ; }; gpio_pta { nvidia,pins = "pta"; nvidia,function = "rsvd4"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = ; + nvidia,tristate = ; }; gpio_uac { nvidia,pins = "uac"; nvidia,function = "rsvd2"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = ; + nvidia,tristate = ; }; hdint { nvidia,pins = "hdint"; nvidia,function = "hdmi"; - nvidia,tristate = <1>; + nvidia,tristate = ; }; i2c1 { nvidia,pins = "rm"; nvidia,function = "i2c1"; - nvidia,pull = <0>; - nvidia,tristate = <1>; + nvidia,pull = ; + nvidia,tristate = ; }; i2c3 { nvidia,pins = "dtf"; nvidia,function = "i2c3"; - nvidia,pull = <0>; - nvidia,tristate = <1>; + nvidia,pull = ; + nvidia,tristate = ; }; i2cddc { nvidia,pins = "ddc"; nvidia,function = "i2c2"; - nvidia,pull = <2>; - nvidia,tristate = <1>; + nvidia,pull = ; + nvidia,tristate = ; }; i2cp { nvidia,pins = "i2cp"; nvidia,function = "i2cp"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = ; + nvidia,tristate = ; }; irda { nvidia,pins = "uad"; nvidia,function = "irda"; - nvidia,pull = <0>; - nvidia,tristate = <1>; + nvidia,pull = ; + nvidia,tristate = ; }; nand { nvidia,pins = "kbca", "kbcc", "kbcd", "kbce", "kbcf"; nvidia,function = "nand"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = ; + nvidia,tristate = ; }; owc { nvidia,pins = "owc"; nvidia,function = "owr"; - nvidia,pull = <0>; - nvidia,tristate = <1>; + nvidia,pull = ; + nvidia,tristate = ; }; pmc { nvidia,pins = "pmc"; nvidia,function = "pwr_on"; - nvidia,tristate = <0>; + nvidia,tristate = ; }; pwm { nvidia,pins = "sdb", "sdc", "sdd"; nvidia,function = "pwm"; - nvidia,tristate = <1>; + nvidia,tristate = ; }; sdio4 { nvidia,pins = "atb", "gma", "gme"; nvidia,function = "sdio4"; - nvidia,pull = <0>; - nvidia,tristate = <1>; + nvidia,pull = ; + nvidia,tristate = ; }; spi1 { nvidia,pins = "spid", "spie", "spif"; nvidia,function = "spi1"; - nvidia,pull = <0>; - nvidia,tristate = <1>; + nvidia,pull = ; + nvidia,tristate = ; }; spi4 { nvidia,pins = "slxa", "slxc", "slxd", "slxk"; nvidia,function = "spi4"; - nvidia,pull = <0>; - nvidia,tristate = <1>; + nvidia,pull = ; + nvidia,tristate = ; }; uarta { nvidia,pins = "sdio1"; nvidia,function = "uarta"; - nvidia,pull = <0>; - nvidia,tristate = <1>; + nvidia,pull = ; + nvidia,tristate = ; }; uartd { nvidia,pins = "gmc"; nvidia,function = "uartd"; - nvidia,pull = <0>; - nvidia,tristate = <1>; + nvidia,pull = ; + nvidia,tristate = ; }; ulpi { nvidia,pins = "uaa", "uab", "uda"; nvidia,function = "ulpi"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = ; + nvidia,tristate = ; }; ulpi_refclk { nvidia,pins = "cdev2"; nvidia,function = "pllp_out4"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = ; + nvidia,tristate = ; }; usb_gpio { nvidia,pins = "spig", "spih"; nvidia,function = "spi2_alt"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = ; + nvidia,tristate = ; }; vi { nvidia,pins = "dta", "dtb", "dtc", "dtd"; nvidia,function = "vi"; - nvidia,pull = <0>; - nvidia,tristate = <1>; + nvidia,pull = ; + nvidia,tristate = ; }; vi_sc { nvidia,pins = "csus"; nvidia,function = "vi_sensor_clk"; - nvidia,pull = <0>; - nvidia,tristate = <1>; + nvidia,pull = ; + nvidia,tristate = ; }; }; }; diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index 7e578f4..b02653d 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -185,50 +185,50 @@ "gmb", "gmc", "gmd", "gme", "gpu7", "gpv", "i2cp", "pta", "rm", "slxa", "slxk", "spia", "spib", "uac"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = ; + nvidia,tristate = ; }; conf_ck32 { nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; - nvidia,pull = <0>; + nvidia,pull = ; }; conf_csus { nvidia,pins = "csus", "spid", "spif"; - nvidia,pull = <1>; - nvidia,tristate = <1>; + nvidia,pull = ; + nvidia,tristate = ; }; conf_crtp { nvidia,pins = "crtp", "dap2", "dap3", "dap4", "dtc", "dte", "dtf", "gpu", "sdio1", "slxc", "slxd", "spdi", "spdo", "spig", "uda"; - nvidia,pull = <0>; - nvidia,tristate = <1>; + nvidia,pull = ; + nvidia,tristate = ; }; conf_ddc { nvidia,pins = "ddc", "dta", "dtd", "kbca", "kbcb", "kbcc", "kbcd", "kbce", "kbcf", "sdc"; - nvidia,pull = <2>; - nvidia,tristate = <0>; + nvidia,pull = ; + nvidia,tristate = ; }; conf_hdint { nvidia,pins = "hdint", "lcsn", "ldc", "lm1", "lpw1", "lsc1", "lsck", "lsda", "lsdi", "lvp0", "owc", "sdb"; - nvidia,tristate = <1>; + nvidia,tristate = ; }; conf_irrx { nvidia,pins = "irrx", "irtx", "sdd", "spic", "spie", "spih", "uaa", "uab", "uad", "uca", "ucb"; - nvidia,pull = <2>; - nvidia,tristate = <1>; + nvidia,pull = ; + nvidia,tristate = ; }; conf_lc { nvidia,pins = "lc", "ls"; - nvidia,pull = <2>; + nvidia,pull = ; }; conf_ld0 { nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", @@ -238,12 +238,12 @@ "lhp1", "lhp2", "lhs", "lm0", "lpp", "lpw0", "lpw2", "lsc0", "lspi", "lvp1", "lvs", "pmc"; - nvidia,tristate = <0>; + nvidia,tristate = ; }; conf_ld17_0 { nvidia,pins = "ld17_0", "ld19_18", "ld21_20", "ld23_22"; - nvidia,pull = <1>; + nvidia,pull = ; }; }; }; diff --git a/arch/arm/boot/dts/tegra20-iris-512.dts b/arch/arm/boot/dts/tegra20-iris-512.dts index 274d252..8cfb83f 100644 --- a/arch/arm/boot/dts/tegra20-iris-512.dts +++ b/arch/arm/boot/dts/tegra20-iris-512.dts @@ -15,23 +15,23 @@ pinmux@70000014 { state_default: pinmux { hdint { - nvidia,tristate = <0>; + nvidia,tristate = ; }; i2cddc { - nvidia,tristate = <0>; + nvidia,tristate = ; }; sdio4 { - nvidia,tristate = <0>; + nvidia,tristate = ; }; uarta { - nvidia,tristate = <0>; + nvidia,tristate = ; }; uartd { - nvidia,tristate = <0>; + nvidia,tristate = ; }; }; }; diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 31c14d0..02923fb 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -178,39 +178,39 @@ "gpu", "gpu7", "gpv", "i2cp", "pta", "rm", "sdio1", "slxk", "spdo", "uac", "uda"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = ; + nvidia,tristate = ; }; conf_ck32 { nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; - nvidia,pull = <0>; + nvidia,pull = ; }; conf_crtp { nvidia,pins = "crtp", "dap3", "dap4", "dtb", "dtc", "dte", "slxa", "slxc", "slxd", "spdi"; - nvidia,pull = <0>; - nvidia,tristate = <1>; + nvidia,pull = ; + nvidia,tristate = ; }; conf_csus { nvidia,pins = "csus", "spia", "spib", "spid", "spif"; - nvidia,pull = <1>; - nvidia,tristate = <1>; + nvidia,pull = ; + nvidia,tristate = ; }; conf_ddc { nvidia,pins = "ddc", "irrx", "irtx", "kbca", "kbcb", "kbcc", "kbcd", "kbce", "kbcf", "spic", "spig", "uaa", "uab"; - nvidia,pull = <2>; - nvidia,tristate = <0>; + nvidia,pull = ; + nvidia,tristate = ; }; conf_dta { nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd", "spie", "spih", "uad", "uca", "ucb"; - nvidia,pull = <2>; - nvidia,tristate = <1>; + nvidia,pull = ; + nvidia,tristate = ; }; conf_hdint { nvidia,pins = "hdint", "ld0", "ld1", "ld2", @@ -219,23 +219,23 @@ "ld13", "ld14", "ld15", "ld16", "ld17", "ldc", "ldi", "lhs", "lsc0", "lspi", "lvs", "pmc"; - nvidia,tristate = <0>; + nvidia,tristate = ; }; conf_lc { nvidia,pins = "lc", "ls"; - nvidia,pull = <2>; + nvidia,pull = ; }; conf_lcsn { nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2", "lm0", "lm1", "lpp", "lpw0", "lpw1", "lpw2", "lsc1", "lsck", "lsda", "lsdi", "lvp0", "lvp1", "sdb"; - nvidia,tristate = <1>; + nvidia,tristate = ; }; conf_ld17_0 { nvidia,pins = "ld17_0", "ld19_18", "ld21_20", "ld23_22"; - nvidia,pull = <1>; + nvidia,pull = ; }; }; }; diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index 476e4e8..1204738 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -190,53 +190,53 @@ "irtx", "pta", "rm", "sdc", "sdd", "slxd", "slxk", "spdi", "spdo", "uac", "uad", "uca", "ucb", "uda"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = ; + nvidia,tristate = ; }; conf_ate { nvidia,pins = "ate", "csus", "dap3", "gpv", "owc", "slxc", "spib", "spid", "spie"; - nvidia,pull = <0>; - nvidia,tristate = <1>; + nvidia,pull = ; + nvidia,tristate = ; }; conf_ck32 { nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; - nvidia,pull = <0>; + nvidia,pull = ; }; conf_crtp { nvidia,pins = "crtp", "gmb", "slxa", "spia", "spig", "spih"; - nvidia,pull = <2>; - nvidia,tristate = <1>; + nvidia,pull = ; + nvidia,tristate = ; }; conf_dta { nvidia,pins = "dta", "dtb", "dtc", "dtd"; - nvidia,pull = <1>; - nvidia,tristate = <0>; + nvidia,pull = ; + nvidia,tristate = ; }; conf_dte { nvidia,pins = "dte", "spif"; - nvidia,pull = <1>; - nvidia,tristate = <1>; + nvidia,pull = ; + nvidia,tristate = ; }; conf_hdint { nvidia,pins = "hdint", "lcsn", "ldc", "lm1", "lpw1", "lsc1", "lsck", "lsda", "lsdi", "lvp0"; - nvidia,tristate = <1>; + nvidia,tristate = ; }; conf_kbca { nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", "kbce", "kbcf", "sdio1", "spic", "uaa", "uab"; - nvidia,pull = <2>; - nvidia,tristate = <0>; + nvidia,pull = ; + nvidia,tristate = ; }; conf_lc { nvidia,pins = "lc", "ls"; - nvidia,pull = <2>; + nvidia,pull = ; }; conf_ld0 { nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", @@ -246,22 +246,22 @@ "lhp1", "lhp2", "lhs", "lm0", "lpp", "lpw0", "lpw2", "lsc0", "lspi", "lvp1", "lvs", "pmc", "sdb"; - nvidia,tristate = <0>; + nvidia,tristate = ; }; conf_ld17_0 { nvidia,pins = "ld17_0", "ld19_18", "ld21_20", "ld23_22"; - nvidia,pull = <1>; + nvidia,pull = ; }; drive_sdio1 { nvidia,pins = "drive_sdio1"; - nvidia,high-speed-mode = <0>; - nvidia,schmitt = <0>; - nvidia,low-power-mode = <3>; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,low-power-mode = ; nvidia,pull-down-strength = <31>; nvidia,pull-up-strength = <31>; - nvidia,slew-rate-rising = <3>; - nvidia,slew-rate-falling = <3>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; }; }; diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi index 02dbc69..eb2f9aa 100644 --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -176,50 +176,50 @@ "gmb", "gmc", "gmd", "gme", "gpu7", "gpv", "i2cp", "pta", "rm", "slxa", "slxk", "spia", "spib", "uac"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = ; + nvidia,tristate = ; }; conf_ck32 { nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; - nvidia,pull = <0>; + nvidia,pull = ; }; conf_csus { nvidia,pins = "csus", "spid", "spif"; - nvidia,pull = <1>; - nvidia,tristate = <1>; + nvidia,pull = ; + nvidia,tristate = ; }; conf_crtp { nvidia,pins = "crtp", "dap2", "dap3", "dap4", "dtc", "dte", "dtf", "gpu", "sdio1", "slxc", "slxd", "spdi", "spdo", "spig", "uda"; - nvidia,pull = <0>; - nvidia,tristate = <1>; + nvidia,pull = ; + nvidia,tristate = ; }; conf_ddc { nvidia,pins = "ddc", "dta", "dtd", "kbca", "kbcb", "kbcc", "kbcd", "kbce", "kbcf", "sdc"; - nvidia,pull = <2>; - nvidia,tristate = <0>; + nvidia,pull = ; + nvidia,tristate = ; }; conf_hdint { nvidia,pins = "hdint", "lcsn", "ldc", "lm1", "lpw1", "lsc1", "lsck", "lsda", "lsdi", "lvp0", "owc", "sdb"; - nvidia,tristate = <1>; + nvidia,tristate = ; }; conf_irrx { nvidia,pins = "irrx", "irtx", "sdd", "spic", "spie", "spih", "uaa", "uab", "uad", "uca", "ucb"; - nvidia,pull = <2>; - nvidia,tristate = <1>; + nvidia,pull = ; + nvidia,tristate = ; }; conf_lc { nvidia,pins = "lc", "ls"; - nvidia,pull = <2>; + nvidia,pull = ; }; conf_ld0 { nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", @@ -229,12 +229,12 @@ "lhp1", "lhp2", "lhs", "lm0", "lpp", "lpw0", "lpw2", "lsc0", "lspi", "lvp1", "lvs", "pmc"; - nvidia,tristate = <0>; + nvidia,tristate = ; }; conf_ld17_0 { nvidia,pins = "ld17_0", "ld19_18", "ld21_20", "ld23_22"; - nvidia,pull = <1>; + nvidia,pull = ; }; }; diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index babc8fb..ec36faf 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -192,49 +192,49 @@ "dtb", "dtc", "dtd", "dte", "gmb", "gme", "i2cp", "pta", "slxc", "slxd", "spdi", "spdo", "uda"; - nvidia,pull = <0>; - nvidia,tristate = <1>; + nvidia,pull = ; + nvidia,tristate = ; }; conf_atb { nvidia,pins = "atb", "cdev1", "cdev2", "dap1", "gma", "gmc", "gmd", "gpu", "gpu7", "gpv", "sdio1", "slxa", "slxk", "uac"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = ; + nvidia,tristate = ; }; conf_ck32 { nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; - nvidia,pull = <0>; + nvidia,pull = ; }; conf_csus { nvidia,pins = "csus", "spia", "spib", "spid", "spif"; - nvidia,pull = <1>; - nvidia,tristate = <1>; + nvidia,pull = ; + nvidia,tristate = ; }; conf_ddc { nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd"; - nvidia,pull = <2>; - nvidia,tristate = <0>; + nvidia,pull = ; + nvidia,tristate = ; }; conf_hdint { nvidia,pins = "hdint", "lcsn", "ldc", "lm1", "lpw1", "lsc1", "lsck", "lsda", "lsdi", "lvp0", "pmc"; - nvidia,tristate = <1>; + nvidia,tristate = ; }; conf_irrx { nvidia,pins = "irrx", "irtx", "kbca", "kbcb", "kbcc", "kbcd", "kbce", "kbcf", "owc", "spic", "spie", "spig", "spih", "uaa", "uab", "uad", "uca", "ucb"; - nvidia,pull = <2>; - nvidia,tristate = <1>; + nvidia,pull = ; + nvidia,tristate = ; }; conf_lc { nvidia,pins = "lc", "ls"; - nvidia,pull = <2>; + nvidia,pull = ; }; conf_ld0 { nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", @@ -244,17 +244,17 @@ "lhp1", "lhp2", "lhs", "lm0", "lpp", "lpw0", "lpw2", "lsc0", "lspi", "lvp1", "lvs", "sdb"; - nvidia,tristate = <0>; + nvidia,tristate = ; }; conf_ld17_0 { nvidia,pins = "ld17_0", "ld19_18", "ld21_20", "ld23_22"; - nvidia,pull = <1>; + nvidia,pull = ; }; conf_spif { nvidia,pins = "spif"; - nvidia,pull = <1>; - nvidia,tristate = <0>; + nvidia,pull = ; + nvidia,tristate = ; }; }; }; diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index 323ad64..0d83062 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -190,50 +190,50 @@ "irtx", "pta", "rm", "sdc", "sdd", "slxc", "slxd", "slxk", "spdi", "spdo", "uac", "uad", "uca", "ucb", "uda"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = ; + nvidia,tristate = ; }; conf_ate { nvidia,pins = "ate", "csus", "dap3", "gmd", "gpv", "owc", "spia", "spib", "spic", "spid", "spie", "spig"; - nvidia,pull = <0>; - nvidia,tristate = <1>; + nvidia,pull = ; + nvidia,tristate = ; }; conf_ck32 { nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; - nvidia,pull = <0>; + nvidia,pull = ; }; conf_crtp { nvidia,pins = "crtp", "gmb", "slxa", "spih"; - nvidia,pull = <2>; - nvidia,tristate = <1>; + nvidia,pull = ; + nvidia,tristate = ; }; conf_dta { nvidia,pins = "dta", "dtb", "dtc", "dtd"; - nvidia,pull = <1>; - nvidia,tristate = <0>; + nvidia,pull = ; + nvidia,tristate = ; }; conf_dte { nvidia,pins = "dte", "spif"; - nvidia,pull = <1>; - nvidia,tristate = <1>; + nvidia,pull = ; + nvidia,tristate = ; }; conf_hdint { nvidia,pins = "hdint", "lcsn", "ldc", "lm1", "lpw1", "lsck", "lsda", "lsdi", "lvp0"; - nvidia,tristate = <1>; + nvidia,tristate = ; }; conf_kbca { nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", "kbce", "kbcf", "sdio1", "uaa", "uab"; - nvidia,pull = <2>; - nvidia,tristate = <0>; + nvidia,pull = ; + nvidia,tristate = ; }; conf_lc { nvidia,pins = "lc", "ls"; - nvidia,pull = <2>; + nvidia,pull = ; }; conf_ld0 { nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", @@ -243,22 +243,22 @@ "lhp1", "lhp2", "lhs", "lm0", "lpp", "lpw0", "lpw2", "lsc0", "lsc1", "lspi", "lvp1", "lvs", "pmc", "sdb"; - nvidia,tristate = <0>; + nvidia,tristate = ; }; conf_ld17_0 { nvidia,pins = "ld17_0", "ld19_18", "ld21_20", "ld23_22"; - nvidia,pull = <1>; + nvidia,pull = ; }; drive_sdio1 { nvidia,pins = "drive_sdio1"; - nvidia,high-speed-mode = <0>; - nvidia,schmitt = <1>; - nvidia,low-power-mode = <3>; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,low-power-mode = ; nvidia,pull-down-strength = <31>; nvidia,pull-up-strength = <31>; - nvidia,slew-rate-rising = <3>; - nvidia,slew-rate-falling = <3>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; }; }; diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts index 00ba97a..813b04e 100644 --- a/arch/arm/boot/dts/tegra20-whistler.dts +++ b/arch/arm/boot/dts/tegra20-whistler.dts @@ -190,8 +190,8 @@ "kbcf", "sdc", "sdd", "spie", "spig", "spih", "uaa", "uab", "uad", "uca", "ucb"; - nvidia,pull = <2>; - nvidia,tristate = <0>; + nvidia,pull = ; + nvidia,tristate = ; }; conf_atd { nvidia,pins = "atd", "ate", "cdev1", "csus", @@ -199,54 +199,54 @@ "dtf", "gpu", "gpu7", "gpv", "i2cp", "rm", "sdio1", "slxa", "slxc", "slxd", "slxk", "spdi", "spdo", "uac", "uda"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = ; + nvidia,tristate = ; }; conf_cdev2 { nvidia,pins = "cdev2", "spia", "spib"; - nvidia,pull = <1>; - nvidia,tristate = <1>; + nvidia,pull = ; + nvidia,tristate = ; }; conf_ck32 { nvidia,pins = "ck32", "ddrc", "lc", "pmca", "pmcb", "pmcc", "pmcd", "xm2c", "xm2d"; - nvidia,pull = <0>; + nvidia,pull = ; }; conf_crtp { nvidia,pins = "crtp"; - nvidia,pull = <0>; - nvidia,tristate = <1>; + nvidia,pull = ; + nvidia,tristate = ; }; conf_dta { nvidia,pins = "dta", "dtb", "dtc", "dtd", "spid", "spif"; - nvidia,pull = <1>; - nvidia,tristate = <0>; + nvidia,pull = ; + nvidia,tristate = ; }; conf_gme { nvidia,pins = "gme", "owc", "pta", "spic"; - nvidia,pull = <2>; - nvidia,tristate = <1>; + nvidia,pull = ; + nvidia,tristate = ; }; conf_ld17_0 { nvidia,pins = "ld17_0", "ld19_18", "ld21_20", "ld23_22"; - nvidia,pull = <1>; + nvidia,pull = ; }; conf_ls { nvidia,pins = "ls", "pmce"; - nvidia,pull = <2>; + nvidia,pull = ; }; drive_dap1 { nvidia,pins = "drive_dap1"; - nvidia,high-speed-mode = <0>; - nvidia,schmitt = <1>; - nvidia,low-power-mode = <0>; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,low-power-mode = ; nvidia,pull-down-strength = <0>; nvidia,pull-up-strength = <0>; - nvidia,slew-rate-rising = <0>; - nvidia,slew-rate-falling = <0>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; }; }; }; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 648c494..480ecda 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -1,5 +1,6 @@ #include #include +#include #include #include "skeleton.dtsi" -- cgit v1.1 From a47c662aad72cbabdb0e8df6c25c47c68b400e40 Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Thu, 5 Dec 2013 16:14:09 +0530 Subject: ARM: tegra: convert dts files of Tegra30 platforms to use pinctrl defines Use Tegra pinconrol dt-binding macro to set the values of different pinmux properties of Tegra30 platforms. Signed-off-by: Laxman Dewangan Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra30-beaver.dts | 34 ++++++++++++++--------------- arch/arm/boot/dts/tegra30-cardhu.dtsi | 40 +++++++++++++++++------------------ arch/arm/boot/dts/tegra30.dtsi | 1 + 3 files changed, 38 insertions(+), 37 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index 3ad193c..7e8562a 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -52,8 +52,8 @@ sdmmc1_clk_pz0 { nvidia,pins = "sdmmc1_clk_pz0"; nvidia,function = "sdmmc1"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = ; + nvidia,tristate = ; }; sdmmc1_cmd_pz1 { nvidia,pins = "sdmmc1_cmd_pz1", @@ -62,14 +62,14 @@ "sdmmc1_dat2_py5", "sdmmc1_dat3_py4"; nvidia,function = "sdmmc1"; - nvidia,pull = <2>; - nvidia,tristate = <0>; + nvidia,pull = ; + nvidia,tristate = ; }; sdmmc3_clk_pa6 { nvidia,pins = "sdmmc3_clk_pa6"; nvidia,function = "sdmmc3"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = ; + nvidia,tristate = ; }; sdmmc3_cmd_pa7 { nvidia,pins = "sdmmc3_cmd_pa7", @@ -78,15 +78,15 @@ "sdmmc3_dat2_pb5", "sdmmc3_dat3_pb4"; nvidia,function = "sdmmc3"; - nvidia,pull = <2>; - nvidia,tristate = <0>; + nvidia,pull = ; + nvidia,tristate = ; }; sdmmc4_clk_pcc4 { nvidia,pins = "sdmmc4_clk_pcc4", "sdmmc4_rst_n_pcc3"; nvidia,function = "sdmmc4"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = ; + nvidia,tristate = ; }; sdmmc4_dat0_paa0 { nvidia,pins = "sdmmc4_dat0_paa0", @@ -98,8 +98,8 @@ "sdmmc4_dat6_paa6", "sdmmc4_dat7_paa7"; nvidia,function = "sdmmc4"; - nvidia,pull = <2>; - nvidia,tristate = <0>; + nvidia,pull = ; + nvidia,tristate = ; }; dap2_fs_pa2 { nvidia,pins = "dap2_fs_pa2", @@ -107,18 +107,18 @@ "dap2_din_pa4", "dap2_dout_pa5"; nvidia,function = "i2s1"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = ; + nvidia,tristate = ; }; pex_l1_prsnt_n_pdd4 { nvidia,pins = "pex_l1_prsnt_n_pdd4", "pex_l1_clkreq_n_pdd6"; - nvidia,pull = <2>; + nvidia,pull = ; }; sdio3 { nvidia,pins = "drive_sdio3"; - nvidia,high-speed-mode = <0>; - nvidia,schmitt = <0>; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; nvidia,pull-down-strength = <46>; nvidia,pull-up-strength = <42>; nvidia,slew-rate-rising = <1>; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index 748b4ba..f3aab9e 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -59,8 +59,8 @@ sdmmc1_clk_pz0 { nvidia,pins = "sdmmc1_clk_pz0"; nvidia,function = "sdmmc1"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = ; + nvidia,tristate = ; }; sdmmc1_cmd_pz1 { nvidia,pins = "sdmmc1_cmd_pz1", @@ -69,14 +69,14 @@ "sdmmc1_dat2_py5", "sdmmc1_dat3_py4"; nvidia,function = "sdmmc1"; - nvidia,pull = <2>; - nvidia,tristate = <0>; + nvidia,pull = ; + nvidia,tristate = ; }; sdmmc3_clk_pa6 { nvidia,pins = "sdmmc3_clk_pa6"; nvidia,function = "sdmmc3"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = ; + nvidia,tristate = ; }; sdmmc3_cmd_pa7 { nvidia,pins = "sdmmc3_cmd_pa7", @@ -85,15 +85,15 @@ "sdmmc3_dat2_pb5", "sdmmc3_dat3_pb4"; nvidia,function = "sdmmc3"; - nvidia,pull = <2>; - nvidia,tristate = <0>; + nvidia,pull = ; + nvidia,tristate = ; }; sdmmc4_clk_pcc4 { nvidia,pins = "sdmmc4_clk_pcc4", "sdmmc4_rst_n_pcc3"; nvidia,function = "sdmmc4"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = ; + nvidia,tristate = ; }; sdmmc4_dat0_paa0 { nvidia,pins = "sdmmc4_dat0_paa0", @@ -105,8 +105,8 @@ "sdmmc4_dat6_paa6", "sdmmc4_dat7_paa7"; nvidia,function = "sdmmc4"; - nvidia,pull = <2>; - nvidia,tristate = <0>; + nvidia,pull = ; + nvidia,tristate = ; }; dap2_fs_pa2 { nvidia,pins = "dap2_fs_pa2", @@ -114,17 +114,17 @@ "dap2_din_pa4", "dap2_dout_pa5"; nvidia,function = "i2s1"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = ; + nvidia,tristate = ; }; sdio3 { nvidia,pins = "drive_sdio3"; - nvidia,high-speed-mode = <0>; - nvidia,schmitt = <0>; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; nvidia,pull-down-strength = <46>; nvidia,pull-up-strength = <42>; - nvidia,slew-rate-rising = <1>; - nvidia,slew-rate-falling = <1>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; }; uart3_txd_pw6 { nvidia,pins = "uart3_txd_pw6", @@ -132,8 +132,8 @@ "uart3_rts_n_pc0", "uart3_rxd_pw7"; nvidia,function = "uartc"; - nvidia,pull = <0>; - nvidia,tristate = <0>; + nvidia,pull = ; + nvidia,tristate = ; }; }; }; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 829eb4b..ee5e9d8 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -1,5 +1,6 @@ #include #include +#include #include #include "skeleton.dtsi" -- cgit v1.1 From c7ac2b7b1e4d85fe13a52e10f6c3164d778eb550 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Fri, 6 Dec 2013 13:51:47 +0100 Subject: ARM: tegra: correct Colibri T20 regulator settings Set the parent of the regulators LDO2 to LDO9 according to the schematic. Set the base voltage to 3.3V, there is only 3.3V on the module itself. Set the Core and CPU voltage to the specified voltages of 1.2V and 1.0V respectivly. LDO6 should deliver 2.85V. The attached peripherals were not in use so far. Signed-off-by: Stefan Agner Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra20-colibri-512.dtsi | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi index 7792637..81c2c90 100644 --- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi @@ -233,15 +233,15 @@ #gpio-cells = <2>; gpio-controller; - sys-supply = <&vdd_5v0_reg>; + sys-supply = <&vdd_3v3_reg>; vin-sm0-supply = <&sys_reg>; vin-sm1-supply = <&sys_reg>; vin-sm2-supply = <&sys_reg>; vinldo01-supply = <&sm2_reg>; - vinldo23-supply = <&sm2_reg>; - vinldo4-supply = <&sm2_reg>; - vinldo678-supply = <&sm2_reg>; - vinldo9-supply = <&sm2_reg>; + vinldo23-supply = <&vdd_3v3_reg>; + vinldo4-supply = <&vdd_3v3_reg>; + vinldo678-supply = <&vdd_3v3_reg>; + vinldo9-supply = <&vdd_3v3_reg>; regulators { #address-cells = <1>; @@ -258,8 +258,8 @@ reg = <1>; regulator-compatible = "sm0"; regulator-name = "vdd_sm0,vdd_core"; - regulator-min-microvolt = <1275000>; - regulator-max-microvolt = <1275000>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; regulator-always-on; }; @@ -267,8 +267,8 @@ reg = <2>; regulator-compatible = "sm1"; regulator-name = "vdd_sm1,vdd_cpu"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; regulator-always-on; }; @@ -324,8 +324,8 @@ reg = <10>; regulator-compatible = "ldo6"; regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; }; hdmi_vdd_reg: regulator@11 { @@ -484,12 +484,12 @@ #address-cells = <1>; #size-cells = <0>; - vdd_5v0_reg: regulator@100 { + vdd_3v3_reg: regulator@100 { compatible = "regulator-fixed"; reg = <100>; - regulator-name = "vdd_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; + regulator-name = "vdd_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; regulator-always-on; }; -- cgit v1.1 From 4b20bcbea191c441208e6794f0432100f57bea2e Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Mon, 9 Dec 2013 16:03:51 +0530 Subject: ARM: tegra: add default pinctrl nodes for Venice2 Add the default pinmux configuration for the Tegra124 based Venice2 platform. Signed-off-by: Laxman Dewangan Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124-venice2.dts | 337 +++++++++++++++++++++++++++++++++ arch/arm/boot/dts/tegra124.dtsi | 1 + 2 files changed, 338 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 7302e7d..616759c 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -10,6 +10,343 @@ reg = <0x80000000 0x80000000>; }; + pinmux: pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_default>; + + pinmux_default: common { + dap_mclk1_pw4 { + nvidia,pins = "dap_mclk1_pw4"; + nvidia,function = "extperiph1"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + dap1_din_pn1 { + nvidia,pins = "dap1_din_pn1", + "dap1_dout_pn2", + "dap1_fs_pn0", + "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + dap2_din_pa4 { + nvidia,pins = "dap2_din_pa4", + "dap2_dout_pa5", + "dap2_fs_pa2", + "dap2_sclk_pa3"; + nvidia,function = "i2s1"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + dvfs_pwm_px0 { + nvidia,pins = "dvfs_pwm_px0"; + nvidia,function = "cldvfs"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + dvfs_clk_px2 { + nvidia,pins = "dvfs_clk_px2"; + nvidia,function = "cldvfs"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0", + "ulpi_dir_py1", + "ulpi_nxt_py2", + "ulpi_stp_py3"; + nvidia,function = "spi1"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + cam_i2c_scl_pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,lock = ; + nvidia,open-drain = ; + }; + gen2_i2c_scl_pt5 { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,lock = ; + nvidia,open-drain = ; + }; + pg4 { + nvidia,pins = "pg4", + "pg5", + "pg6", + "pg7", + "pi3"; + nvidia,function = "spi4"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + ph0 { + nvidia,pins = "ph0"; + nvidia,function = "pwm0"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + ph1 { + nvidia,pins = "ph1"; + nvidia,function = "pwm1"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0", + "sdmmc1_cmd_pz1", + "sdmmc1_dat0_py7", + "sdmmc1_dat1_py6", + "sdmmc1_dat2_py5", + "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4", + "sdmmc3_clk_lb_out_pee4", + "sdmmc3_clk_lb_in_pee5"; + nvidia,function = "sdmmc3"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + sdmmc4_cmd_pt7 { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + pwr_i2c_scl_pz6 { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,open-drain = ; + }; + jtag_rtck { + nvidia,pins = "jtag_rtck"; + nvidia,function = "rtck"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + clk_32k_in { + nvidia,pins = "clk_32k_in"; + nvidia,function = "clk"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + core_pwr_req { + nvidia,pins = "core_pwr_req"; + nvidia,function = "pwron"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + cpu_pwr_req { + nvidia,pins = "cpu_pwr_req"; + nvidia,function = "cpu"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + pwr_int_n { + nvidia,pins = "pwr_int_n"; + nvidia,function = "pmi"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + reset_out_n { + nvidia,pins = "reset_out_n"; + nvidia,function = "reset_out_n"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + clk3_out_pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + dap4_din_pp5 { + nvidia,pins = "dap4_din_pp5", + "dap4_dout_pp6", + "dap4_fs_pp4", + "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + gen1_i2c_sda_pc5 { + nvidia,pins = "gen1_i2c_sda_pc5", + "gen1_i2c_scl_pc4"; + nvidia,function = "i2c1"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,lock = ; + nvidia,open-drain = ; + }; + pu0 { + nvidia,pins = "pu0", + "pu1", + "pu2", + "pu3"; + nvidia,function = "uarta"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + uart2_cts_n_pj5 { + nvidia,pins = "uart2_cts_n_pj5", + "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + uart2_rxd_pc3 { + nvidia,pins = "uart2_rxd_pc3", + "uart2_txd_pc2"; + nvidia,function = "irda"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + uart3_cts_n_pa1 { + nvidia,pins = "uart3_cts_n_pa1", + "uart3_rts_n_pc0", + "uart3_rxd_pw7", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + hdmi_cec_pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,open-drain = ; + }; + ddc_scl_pv4 { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + usb_vbus_en0_pn4 { + nvidia,pins = "usb_vbus_en0_pn4"; + nvidia,function = "usb"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,lock = ; + nvidia,open-drain = ; + }; + usb_vbus_en1_pn5 { + nvidia,pins = "usb_vbus_en1_pn5"; + nvidia,function = "usb"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,lock = ; + nvidia,open-drain = ; + }; + drive_sdio1 { + nvidia,pins = "drive_sdio1"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,low-power-mode = ; + nvidia,pull-down-strength = <32>; + nvidia,pull-up-strength = <42>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + drive_sdio3 { + nvidia,pins = "drive_sdio3"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,low-power-mode = ; + nvidia,pull-down-strength = <20>; + nvidia,pull-up-strength = <36>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + drive_gma { + nvidia,pins = "drive_gma"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,low-power-mode = ; + nvidia,pull-down-strength = <1>; + nvidia,pull-up-strength = <2>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + nvidia,drive-type = <1>; + }; + }; + }; + serial@70006000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 45d8f11..6fd4959 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -1,5 +1,6 @@ #include #include +#include #include #include "skeleton.dtsi" -- cgit v1.1 From 4ffb93857656a988ceb79473390a7cb1afd01d35 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 12 Dec 2013 14:40:30 -0700 Subject: ARM: tegra: fix pinctrl misconfiguration on Venice2 Other boards use PULL_NONE for their debug UART pins, and without this change, the board doesn't accept any serial input. Don't set the I2S port pins to tristate mode, or no audio signal will be sent out. Fixes: 605ae5804385 ("ARM: tegra: add default pinctrl nodes for Venice2") Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124-venice2.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 616759c..b31e187 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -40,7 +40,7 @@ nvidia,function = "i2s1"; nvidia,enable-input = ; nvidia,pull = ; - nvidia,tristate = ; + nvidia,tristate = ; }; dvfs_pwm_px0 { nvidia,pins = "dvfs_pwm_px0"; @@ -250,7 +250,7 @@ "pu3"; nvidia,function = "uarta"; nvidia,enable-input = ; - nvidia,pull = ; + nvidia,pull = ; nvidia,tristate = ; }; uart2_cts_n_pj5 { -- cgit v1.1 From f5cb19b496300e6b4f8e4da119cc4bf959ab1baa Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 13 Dec 2013 17:25:04 +0100 Subject: ARM: tegra: Fix misconfiguration of pin PH2 on Venice2 This pin needs to be configured in pull-down, non-tristate mode in order for the backlight to work correctly. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124-venice2.dts | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index b31e187..d6bb25c 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -111,6 +111,13 @@ nvidia,pull = ; nvidia,tristate = ; }; + ph2 { + nvidia,pins = "ph2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; sdmmc1_clk_pz0 { nvidia,pins = "sdmmc1_clk_pz0", "sdmmc1_cmd_pz1", -- cgit v1.1 From 9f1ac5606a008f4849208ebfe818f979619dced0 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 13 Dec 2013 17:24:05 +0100 Subject: ARM: tegra: Add SPI controller nodes for Tegra124 The SPI controllers on Tegra124 are compatible with those found on the Tegra114 SoC. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124.dtsi | 90 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 6fd4959..ec0698a 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -277,6 +277,96 @@ status = "disabled"; }; + spi@7000d400 { + compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; + reg = <0x7000d400 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_SBC1>; + clock-names = "spi"; + resets = <&tegra_car 41>; + reset-names = "spi"; + dmas = <&apbdma 15>, <&apbdma 15>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi@7000d600 { + compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; + reg = <0x7000d600 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_SBC2>; + clock-names = "spi"; + resets = <&tegra_car 44>; + reset-names = "spi"; + dmas = <&apbdma 16>, <&apbdma 16>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi@7000d800 { + compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; + reg = <0x7000d800 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_SBC3>; + clock-names = "spi"; + resets = <&tegra_car 46>; + reset-names = "spi"; + dmas = <&apbdma 17>, <&apbdma 17>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi@7000da00 { + compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; + reg = <0x7000da00 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_SBC4>; + clock-names = "spi"; + resets = <&tegra_car 68>; + reset-names = "spi"; + dmas = <&apbdma 18>, <&apbdma 18>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi@7000dc00 { + compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; + reg = <0x7000dc00 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_SBC5>; + clock-names = "spi"; + resets = <&tegra_car 104>; + reset-names = "spi"; + dmas = <&apbdma 27>, <&apbdma 27>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi@7000de00 { + compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; + reg = <0x7000de00 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_SBC6>; + clock-names = "spi"; + resets = <&tegra_car 105>; + reset-names = "spi"; + dmas = <&apbdma 28>, <&apbdma 28>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + rtc@7000e000 { compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; reg = <0x7000e000 0x100>; -- cgit v1.1 From 553c0a200e2082686fd9b829b77f7df6ebae14e9 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 9 Dec 2013 14:43:59 -0700 Subject: ARM: tegra: set up /aliases entries for RTCs This ensures that the PMIC RTC provides the system time, rather than the on-SoC RTC, which is not battery-backed. tegra124-venice2.dts isn't touched yet since we haven't added any off- SoC RTC device to its device tree. Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra114-dalmore.dts | 5 +++++ arch/arm/boot/dts/tegra20-colibri-512.dtsi | 5 +++++ arch/arm/boot/dts/tegra20-harmony.dts | 5 +++++ arch/arm/boot/dts/tegra20-paz00.dts | 5 +++++ arch/arm/boot/dts/tegra20-seaboard.dts | 5 +++++ arch/arm/boot/dts/tegra20-tamonten.dtsi | 5 +++++ arch/arm/boot/dts/tegra20-trimslice.dts | 5 +++++ arch/arm/boot/dts/tegra20-ventana.dts | 5 +++++ arch/arm/boot/dts/tegra20-whistler.dts | 5 +++++ arch/arm/boot/dts/tegra30-beaver.dts | 5 +++++ arch/arm/boot/dts/tegra30-cardhu.dtsi | 5 +++++ 11 files changed, 55 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index 88be40c..ca44859 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -7,6 +7,11 @@ model = "NVIDIA Tegra114 Dalmore evaluation board"; compatible = "nvidia,dalmore", "nvidia,tegra114"; + aliases { + rtc0 = "/i2c@7000d000/tps65913@58"; + rtc1 = "/rtc@7000e000"; + }; + memory { reg = <0x80000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi index 81c2c90..61bc393 100644 --- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi @@ -4,6 +4,11 @@ model = "Toradex Colibri T20 512MB"; compatible = "toradex,colibri_t20-512", "nvidia,tegra20"; + aliases { + rtc0 = "/i2c@7000d000/tps6586x@34"; + rtc1 = "/rtc@7000e000"; + }; + memory { reg = <0x00000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index b02653d..6145f26 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -7,6 +7,11 @@ model = "NVIDIA Tegra20 Harmony evaluation board"; compatible = "nvidia,harmony", "nvidia,tegra20"; + aliases { + rtc0 = "/i2c@7000d000/tps6586x@34"; + rtc1 = "/rtc@7000e000"; + }; + memory { reg = <0x00000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 02923fb..c7cd8e6 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -7,6 +7,11 @@ model = "Toshiba AC100 / Dynabook AZ"; compatible = "compal,paz00", "nvidia,tegra20"; + aliases { + rtc0 = "/i2c@7000d000/tps6586x@34"; + rtc1 = "/rtc@7000e000"; + }; + memory { reg = <0x00000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index 1204738..a11b6e7 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -7,6 +7,11 @@ model = "NVIDIA Seaboard"; compatible = "nvidia,seaboard", "nvidia,tegra20"; + aliases { + rtc0 = "/i2c@7000d000/tps6586x@34"; + rtc1 = "/rtc@7000e000"; + }; + memory { reg = <0x00000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi index eb2f9aa..a1b0d96 100644 --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -4,6 +4,11 @@ model = "Avionic Design Tamonten SOM"; compatible = "ad,tamonten", "nvidia,tegra20"; + aliases { + rtc0 = "/i2c@7000d000/tps6586x@34"; + rtc1 = "/rtc@7000e000"; + }; + memory { reg = <0x00000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index ec36faf..216fa6d 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -7,6 +7,11 @@ model = "Compulab TrimSlice board"; compatible = "compulab,trimslice", "nvidia,tegra20"; + aliases { + rtc0 = "/i2c@7000c500/rtc@56"; + rtc1 = "/rtc@7000e000"; + }; + memory { reg = <0x00000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index 0d83062..571d12e 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -7,6 +7,11 @@ model = "NVIDIA Tegra20 Ventana evaluation board"; compatible = "nvidia,ventana", "nvidia,tegra20"; + aliases { + rtc0 = "/i2c@7000d000/tps6586x@34"; + rtc1 = "/rtc@7000e000"; + }; + memory { reg = <0x00000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts index 813b04e..1843725 100644 --- a/arch/arm/boot/dts/tegra20-whistler.dts +++ b/arch/arm/boot/dts/tegra20-whistler.dts @@ -7,6 +7,11 @@ model = "NVIDIA Tegra20 Whistler evaluation board"; compatible = "nvidia,whistler", "nvidia,tegra20"; + aliases { + rtc0 = "/i2c@7000d000/max8907@3c"; + rtc1 = "/rtc@7000e000"; + }; + memory { reg = <0x00000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index 7e8562a..d36c821 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -6,6 +6,11 @@ model = "NVIDIA Tegra30 Beaver evaluation board"; compatible = "nvidia,beaver", "nvidia,tegra30"; + aliases { + rtc0 = "/i2c@7000d000/tps65911@2d"; + rtc1 = "/rtc@7000e000"; + }; + memory { reg = <0x80000000 0x7ff00000>; }; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index f3aab9e..dfcc18a 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -27,6 +27,11 @@ model = "NVIDIA Tegra30 Cardhu evaluation board"; compatible = "nvidia,cardhu", "nvidia,tegra30"; + aliases { + rtc0 = "/i2c@7000d000/tps6586x@34"; + rtc1 = "/rtc@7000e000"; + }; + memory { reg = <0x80000000 0x40000000>; }; -- cgit v1.1 From aeb193606d44bd37b2178c6b2b6f25ff679656a3 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 11 Dec 2013 03:48:17 +0100 Subject: ARM: shmobile: armadillo: dts: Add PWM backlight power supply Commit 22ceeee16eb8f0d04de3ef43a5174fb30ec18af9 ("pwm-backlight: Add power supply support") added a mandatory power supply for the PWM backlight. Add a fixed 5V regulator and reference it for the backlight power supply. Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts index 6d6fd3d..4705759 100644 --- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts @@ -63,6 +63,15 @@ enable-active-high; }; + reg_5p0v: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "fixed-5.0V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + leds { compatible = "gpio-leds"; led1 { @@ -86,6 +95,7 @@ default-brightness-level = <9>; pinctrl-0 = <&backlight_pins>; pinctrl-names = "default"; + power-supply = <®_5p0v>; }; sound { -- cgit v1.1 From a0c9efe65e00bd0a9b5b5814f6b3012d61f966f9 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 11 Dec 2013 03:48:18 +0100 Subject: ARM: shmobile: armadillo: dts: Add PWM backlight enable GPIO The Armadillo 800 EVA panel module has a backlight enable signal connected to GPIO 61. Report this in the backlight DT node. Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts index 4705759..e916aae 100644 --- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts @@ -96,6 +96,7 @@ pinctrl-0 = <&backlight_pins>; pinctrl-names = "default"; power-supply = <®_5p0v>; + enable-gpios = <&pfc 61 GPIO_ACTIVE_HIGH>; }; sound { -- cgit v1.1 From defc82eabf962b83ac9e112238baa895890645ea Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 11 Dec 2013 04:26:27 +0100 Subject: ARM: shmobile: r8a73a4: Specify PFC interrupts in DT Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a73a4.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index 6b7ce89..62d0211 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -288,6 +288,22 @@ reg = <0 0xe6050000 0 0x9000>; gpio-controller; #gpio-cells = <2>; + interrupts-extended = + <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>, + <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>, + <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>, + <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>, + <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>, + <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>, + <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>, + <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>, + <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>, + <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>, + <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>, + <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>, + <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>, + <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>, + <&irqc1 24 0>, <&irqc1 25 0>; }; sdhi0: sd@ee100000 { -- cgit v1.1 From 778de006538d932b96c58dd3a43f9e4ef5060940 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 11 Dec 2013 04:26:28 +0100 Subject: ARM: shmobile: r8a7740: Specify PFC interrupts in DT Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7740.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index 2782f64..8280884 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -155,6 +155,15 @@ <0xe605800c 0x20>; gpio-controller; #gpio-cells = <2>; + interrupts-extended = + <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>, + <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>, + <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>, + <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>, + <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>, + <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>, + <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>, + <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>; }; tpu: pwm@e6600000 { -- cgit v1.1 From aba76d286e8cccb05b3a4c23833faaee171a6c5d Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 11 Dec 2013 04:26:29 +0100 Subject: ARM: shmobile: sh73a0: Specify PFC interrupts in DT Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/sh73a0.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index c460dd2..b7bd3b9 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -242,6 +242,15 @@ <0xe605801c 0x1c>; gpio-controller; #gpio-cells = <2>; + interrupts-extended = + <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>, + <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>, + <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>, + <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>, + <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>, + <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>, + <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>, + <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>; }; sh_fsi2: sound@ec230000 { -- cgit v1.1 From 90c2434daa0b8c7ec2b75fcb182436813e9120bd Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 11 Dec 2013 04:26:30 +0100 Subject: ARM: shmobile: armadillo: dts: Add gpio-keys device The board had 4 buttons connected to GPIOs, add a corresponding gpio-keys device. Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- .../boot/dts/r8a7740-armadillo800eva-reference.dts | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts index e916aae..95a849b 100644 --- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts @@ -72,6 +72,35 @@ regulator-boot-on; }; + gpio-keys { + compatible = "gpio-keys"; + + power-key { + gpios = <&pfc 99 GPIO_ACTIVE_LOW>; + linux,code = <116>; + label = "SW3"; + gpio-key,wakeup; + }; + + back-key { + gpios = <&pfc 100 GPIO_ACTIVE_LOW>; + linux,code = <158>; + label = "SW4"; + }; + + menu-key { + gpios = <&pfc 97 GPIO_ACTIVE_LOW>; + linux,code = <139>; + label = "SW5"; + }; + + home-key { + gpios = <&pfc 98 GPIO_ACTIVE_LOW>; + linux,code = <102>; + label = "SW6"; + }; + }; + leds { compatible = "gpio-leds"; led1 { -- cgit v1.1 From 22a1f59547e1e63cd18ee1ddb32fa2d8ab591a22 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 11 Dec 2013 15:05:14 +0100 Subject: ARM: shmobile: r8a7790: Add clocks Declare all core clocks and DIV6 clocks, as well as all MSTP clocks currently used by r8a7790 boards. Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 318 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 318 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 0e4d5b5..8dccbe7 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -8,6 +8,7 @@ * kind, whether express or implied. */ +#include #include #include @@ -287,4 +288,321 @@ cap-sd-highspeed; status = "disabled"; }; + + clocks { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* External root clock */ + extal_clk: extal_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overriden by the board. */ + clock-frequency = <0>; + clock-output-names = "extal"; + }; + + /* Special CPG clocks */ + cpg_clocks: cpg_clocks@e6150000 { + compatible = "renesas,r8a7790-cpg-clocks", + "renesas,rcar-gen2-cpg-clocks"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>; + #clock-cells = <1>; + clock-output-names = "main", "pll0", "pll1", "pll3", + "lb", "qspi", "sdh", "sd0", "sd1", + "z"; + }; + + /* Variable factor clocks */ + sd2_clk: sd2_clk@e6150078 { + compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150078 0 4>; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-output-names = "sd2"; + }; + sd3_clk: sd3_clk@e615007c { + compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe615007c 0 4>; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-output-names = "sd3"; + }; + mmc0_clk: mmc0_clk@e6150240 { + compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150240 0 4>; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-output-names = "mmc0"; + }; + mmc1_clk: mmc1_clk@e6150244 { + compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150244 0 4>; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-output-names = "mmc1"; + }; + ssp_clk: ssp_clk@e6150248 { + compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150248 0 4>; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-output-names = "ssp"; + }; + ssprs_clk: ssprs_clk@e615024c { + compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe615024c 0 4>; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-output-names = "ssprs"; + }; + + /* Fixed factor clocks */ + pll1_div2_clk: pll1_div2_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "pll1_div2"; + }; + z2_clk: z2_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "z2"; + }; + zg_clk: zg_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <3>; + clock-mult = <1>; + clock-output-names = "zg"; + }; + zx_clk: zx_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <3>; + clock-mult = <1>; + clock-output-names = "zx"; + }; + zs_clk: zs_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <6>; + clock-mult = <1>; + clock-output-names = "zs"; + }; + hp_clk: hp_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <12>; + clock-mult = <1>; + clock-output-names = "hp"; + }; + i_clk: i_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "i"; + }; + b_clk: b_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <12>; + clock-mult = <1>; + clock-output-names = "b"; + }; + p_clk: p_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <24>; + clock-mult = <1>; + clock-output-names = "p"; + }; + cl_clk: cl_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <48>; + clock-mult = <1>; + clock-output-names = "cl"; + }; + m2_clk: m2_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + clock-output-names = "m2"; + }; + imp_clk: imp_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + clock-output-names = "imp"; + }; + rclk_clk: rclk_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <(48 * 1024)>; + clock-mult = <1>; + clock-output-names = "rclk"; + }; + oscclk_clk: oscclk_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <(12 * 1024)>; + clock-mult = <1>; + clock-output-names = "oscclk"; + }; + zb3_clk: zb3_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL3>; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + clock-output-names = "zb3"; + }; + zb3d2_clk: zb3d2_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL3>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + clock-output-names = "zb3d2"; + }; + ddr_clk: ddr_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL3>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + clock-output-names = "ddr"; + }; + mp_clk: mp_clk { + compatible = "fixed-factor-clock"; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-div = <15>; + clock-mult = <1>; + clock-output-names = "mp"; + }; + cp_clk: cp_clk { + compatible = "fixed-factor-clock"; + clocks = <&extal_clk>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "cp"; + }; + + /* Gate clocks */ + mstp1_clks: mstp1_clks@e6150134 { + compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; + clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, + <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, + <&zs_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 + R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 + R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_RT R8A7790_CLK_VSP1_SY + >; + clock-output-names = + "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", + "vsp1-du0", "vsp1-rt", "vsp1-sy"; + }; + mstp2_clks: mstp2_clks@e6150138 { + compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; + clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, + <&mp_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0 + R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1 R8A7790_CLK_SCIFB2 + >; + clock-output-names = + "scifa2", "scifa1", "scifa0", "scifb0", "scifb1", + "scifb2"; + }; + mstp3_clks: mstp3_clks@e615013c { + compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; + clocks = <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>, + <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, + <&mmc0_clk>, <&rclk_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3 + R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 + R8A7790_CLK_MMCIF0 R8A7790_CLK_CMT1 + >; + clock-output-names = + "tpu0", "mmcif1", "sdhi3", "sdhi2", + "sdhi1", "sdhi0", "mmcif0", "cmt1"; + }; + mstp5_clks: mstp5_clks@e6150144 { + compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; + clocks = <&extal_clk>, <&p_clk>; + #clock-cells = <1>; + renesas,clock-indices = ; + clock-output-names = "thermal", "pwm"; + }; + mstp7_clks: mstp7_clks@e615014c { + compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; + clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, + <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, + <&zx_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1 + R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0 + R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0 + R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0 + >; + clock-output-names = + "ehci", "hsusb", "hscif1", "hscif0", "scif1", + "scif0", "du2", "du1", "du0", "lvds1", "lvds0"; + }; + mstp8_clks: mstp8_clks@e6150990 { + compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; + clocks = <&p_clk>; + #clock-cells = <1>; + renesas,clock-indices = ; + clock-output-names = "ether"; + }; + mstp9_clks: mstp9_clks@e6150994 { + compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; + clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_I2C3 + R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0 + >; + clock-output-names = "rcan1", "rcan0", "i2c3", "i2c2", "i2c1", "i2c0"; + }; + }; }; -- cgit v1.1 From 72197ca7a1cb1cea5615c879f638d5d457c0b2e2 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 11 Dec 2013 15:05:15 +0100 Subject: ARM: shmobile: r8a7790: Reference clocks Reference clocks using a "clocks" property in all nodes corresponding to devices that require a clock. Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 8dccbe7..71ec31c 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -197,6 +197,7 @@ reg = <0 0xe6508000 0 0x40>; interrupt-parent = <&gic>; interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_I2C0>; status = "disabled"; }; @@ -207,6 +208,7 @@ reg = <0 0xe6518000 0 0x40>; interrupt-parent = <&gic>; interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_I2C1>; status = "disabled"; }; @@ -217,6 +219,7 @@ reg = <0 0xe6530000 0 0x40>; interrupt-parent = <&gic>; interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_I2C2>; status = "disabled"; }; @@ -227,6 +230,7 @@ reg = <0 0xe6540000 0 0x40>; interrupt-parent = <&gic>; interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_I2C3>; status = "disabled"; }; @@ -235,6 +239,7 @@ reg = <0 0xee200000 0 0x80>; interrupt-parent = <&gic>; interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>; reg-io-width = <4>; status = "disabled"; }; @@ -244,6 +249,7 @@ reg = <0 0xee220000 0 0x80>; interrupt-parent = <&gic>; interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>; reg-io-width = <4>; status = "disabled"; }; @@ -258,6 +264,7 @@ reg = <0 0xee100000 0 0x100>; interrupt-parent = <&gic>; interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_SDHI0>; cap-sd-highspeed; status = "disabled"; }; @@ -267,6 +274,7 @@ reg = <0 0xee120000 0 0x100>; interrupt-parent = <&gic>; interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_SDHI1>; cap-sd-highspeed; status = "disabled"; }; @@ -276,6 +284,7 @@ reg = <0 0xee140000 0 0x100>; interrupt-parent = <&gic>; interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_SDHI2>; cap-sd-highspeed; status = "disabled"; }; @@ -285,6 +294,7 @@ reg = <0 0xee160000 0 0x100>; interrupt-parent = <&gic>; interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_SDHI3>; cap-sd-highspeed; status = "disabled"; }; -- cgit v1.1 From 59e79895b95892863617ce630fbda467f2470575 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 11 Dec 2013 15:05:16 +0100 Subject: ARM: shmobile: r8a7791: Add clocks Declare all core clocks and DIV6 clocks, as well as all MSTP clocks currently used by r8a7791 boards. Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 313 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 313 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index a349aff..0a82192 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -9,6 +9,7 @@ * kind, whether express or implied. */ +#include #include #include @@ -183,4 +184,316 @@ reg = <0 0xe6060000 0 0x250>; #gpio-range-cells = <3>; }; + + clocks { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* External root clock */ + extal_clk: extal_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overriden by the board. */ + clock-frequency = <0>; + clock-output-names = "extal"; + }; + + /* Special CPG clocks */ + cpg_clocks: cpg_clocks@e6150000 { + compatible = "renesas,r8a7791-cpg-clocks", + "renesas,rcar-gen2-cpg-clocks"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>; + #clock-cells = <1>; + clock-output-names = "main", "pll0", "pll1", "pll3", + "lb", "qspi", "sdh", "sd0", "z"; + }; + + /* Variable factor clocks */ + sd1_clk: sd2_clk@e6150078 { + compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150078 0 4>; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-output-names = "sd1"; + }; + sd2_clk: sd3_clk@e615007c { + compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe615007c 0 4>; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-output-names = "sd2"; + }; + mmc0_clk: mmc0_clk@e6150240 { + compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150240 0 4>; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-output-names = "mmc0"; + }; + ssp_clk: ssp_clk@e6150248 { + compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150248 0 4>; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-output-names = "ssp"; + }; + ssprs_clk: ssprs_clk@e615024c { + compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe615024c 0 4>; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-output-names = "ssprs"; + }; + + /* Fixed factor clocks */ + pll1_div2_clk: pll1_div2_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "pll1_div2"; + }; + zg_clk: zg_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <3>; + clock-mult = <1>; + clock-output-names = "zg"; + }; + zx_clk: zx_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <3>; + clock-mult = <1>; + clock-output-names = "zx"; + }; + zs_clk: zs_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <6>; + clock-mult = <1>; + clock-output-names = "zs"; + }; + hp_clk: hp_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <12>; + clock-mult = <1>; + clock-output-names = "hp"; + }; + i_clk: i_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "i"; + }; + b_clk: b_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <12>; + clock-mult = <1>; + clock-output-names = "b"; + }; + p_clk: p_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <24>; + clock-mult = <1>; + clock-output-names = "p"; + }; + cl_clk: cl_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <48>; + clock-mult = <1>; + clock-output-names = "cl"; + }; + m2_clk: m2_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + clock-output-names = "m2"; + }; + imp_clk: imp_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + clock-output-names = "imp"; + }; + rclk_clk: rclk_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <(48 * 1024)>; + clock-mult = <1>; + clock-output-names = "rclk"; + }; + oscclk_clk: oscclk_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <(12 * 1024)>; + clock-mult = <1>; + clock-output-names = "oscclk"; + }; + zb3_clk: zb3_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL3>; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + clock-output-names = "zb3"; + }; + zb3d2_clk: zb3d2_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL3>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + clock-output-names = "zb3d2"; + }; + ddr_clk: ddr_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL3>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + clock-output-names = "ddr"; + }; + mp_clk: mp_clk { + compatible = "fixed-factor-clock"; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-div = <15>; + clock-mult = <1>; + clock-output-names = "mp"; + }; + cp_clk: cp_clk { + compatible = "fixed-factor-clock"; + clocks = <&extal_clk>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "cp"; + }; + + /* Gate clocks */ + mstp1_clks: mstp1_clks@e6150134 { + compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; + clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, + <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 + R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 + R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_SY + >; + clock-output-names = + "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", + "vsp1-du0", "vsp1-sy"; + }; + mstp2_clks: mstp2_clks@e6150138 { + compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; + clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, + <&mp_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0 + R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1 R8A7791_CLK_SCIFB2 + >; + clock-output-names = + "scifa2", "scifa1", "scifa0", "scifb0", "scifb1", + "scifb2"; + }; + mstp3_clks: mstp3_clks@e615013c { + compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; + clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, + <&cpg_clocks R8A7791_CLK_SD0>, <&mmc0_clk>, <&rclk_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 + R8A7791_CLK_SDHI0 R8A7791_CLK_MMCIF0 R8A7791_CLK_CMT1 + >; + clock-output-names = + "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0", "cmt1"; + }; + mstp5_clks: mstp5_clks@e6150144 { + compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; + clocks = <&extal_clk>, <&p_clk>; + #clock-cells = <1>; + renesas,clock-indices = ; + clock-output-names = "thermal", "pwm"; + }; + mstp7_clks: mstp7_clks@e615014c { + compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; + clocks = <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, + <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, + <&zx_clk>, <&zx_clk>, <&zx_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5 + R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0 + R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1 + R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0 + R8A7791_CLK_LVDS0 + >; + clock-output-names = + "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0", + "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0"; + }; + mstp8_clks: mstp8_clks@e6150990 { + compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; + clocks = <&p_clk>; + #clock-cells = <1>; + renesas,clock-indices = ; + clock-output-names = "ether"; + }; + mstp9_clks: mstp9_clks@e6150994 { + compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; + clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, + <&p_clk>, <&p_clk>, <&p_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_I2C4 + R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2 + R8A7791_CLK_I2C1 R8A7791_CLK_I2C0 + >; + clock-output-names = + "rcan1", "rcan0", "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", + "i2c0"; + }; + mstp11_clks: mstp11_clks@e615099c { + compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; + clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5 + >; + clock-output-names = "scifa3", "scifa4", "scifa5"; + }; + }; }; -- cgit v1.1 From 39fa511b8cd96395ee788267a16b8d3b20ac56e2 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 11 Dec 2013 15:13:47 +0100 Subject: ARM: shmobile: Sync Lager DTS with Lager reference DTS Copy the device nodes from Lager reference into the Lager device tree file. This will allow us to use a single DTS file regarless of kernel configuration. In case of legacy C board code the device nodes may or may not be used, but in the multiplatform case all the DT device nodes are used. Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790-lager.dts | 53 +++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 10e6a08..67a6939 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -10,6 +10,7 @@ /dts-v1/; #include "r8a7790.dtsi" +#include / { model = "Lager"; @@ -33,4 +34,56 @@ #address-cells = <1>; #size-cells = <1>; }; + + leds { + compatible = "gpio-leds"; + led6 { + gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; + }; + led7 { + gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>; + }; + led8 { + gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; + }; + }; + + fixedregulator3v3: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&pfc { + pinctrl-0 = <&scif0_pins &scif1_pins>; + pinctrl-names = "default"; + + scif0_pins: serial0 { + renesas,groups = "scif0_data"; + renesas,function = "scif0"; + }; + + scif1_pins: serial1 { + renesas,groups = "scif1_data"; + renesas,function = "scif1"; + }; + + mmc1_pins: mmc1 { + renesas,groups = "mmc1_data8", "mmc1_ctrl"; + renesas,function = "mmc1"; + }; +}; + +&mmcif1 { + pinctrl-0 = <&mmc1_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&fixedregulator3v3>; + bus-width = <8>; + non-removable; + status = "okay"; }; -- cgit v1.1 From f8e2535d988a7945fa2c11214d55c20c73c60840 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 11 Dec 2013 15:13:48 +0100 Subject: ARM: shmobile: Sync Koelsch DTS with Koelsch reference DTS Copy the device nodes from Koelsch reference into the Koeslch device tree file. This will allow us to use a single DTS file regarless of kernel configuration. In case of legacy C board code the device nodes may or may not be used, but in the multiplatform case all the DT device nodes are used. Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791-koelsch.dts | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index c4e8b3a..d431f31 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -11,6 +11,7 @@ /dts-v1/; #include "r8a7791.dtsi" +#include / { model = "Koelsch"; @@ -29,4 +30,32 @@ #address-cells = <1>; #size-cells = <1>; }; + + leds { + compatible = "gpio-leds"; + led6 { + gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; + }; + led7 { + gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; + }; + led8 { + gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&pfc { + pinctrl-0 = <&scif0_pins &scif1_pins>; + pinctrl-names = "default"; + + scif0_pins: serial0 { + renesas,groups = "scif0_data_d"; + renesas,function = "scif0"; + }; + + scif1_pins: serial1 { + renesas,groups = "scif1_data_d"; + renesas,function = "scif1"; + }; }; -- cgit v1.1 From 62e43056ad5f584f8af83267c901f65e667e3657 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 11 Dec 2013 15:13:49 +0100 Subject: ARM: shmobile: lager: Specify external clock frequency in DT The external crystal frequency is 20MHz on the Lager board. Specify it in the device tree. Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790-lager.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 67a6939..57569cb 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -58,6 +58,10 @@ }; }; +&extal_clk { + clock-frequency = <20000000>; +}; + &pfc { pinctrl-0 = <&scif0_pins &scif1_pins>; pinctrl-names = "default"; -- cgit v1.1 From fcf0c725cb38f7d55a89e6f87183afee90a3846d Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 11 Dec 2013 15:13:50 +0100 Subject: ARM: shmobile: koelsch: Specify external clock frequency in DT The external crystal frequency is 20MHz on the Koelsch board. Specify it in the device tree. Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791-koelsch.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index d431f31..fd556c3 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -45,6 +45,10 @@ }; }; +&extal_clk { + clock-frequency = <20000000>; +}; + &pfc { pinctrl-0 = <&scif0_pins &scif1_pins>; pinctrl-names = "default"; -- cgit v1.1 From 2b4baad03854ab23ce9a4c073e3795ac29985132 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 17 Oct 2013 17:22:16 +0200 Subject: ARM: shmobile: Remove Lager reference DTS Now that the DTS file r8a7790-lager.dts can be used with board-lager.c and board-lager-reference.c, proceed with removing r8a7790-lager-reference.dts. Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790-lager-reference.dts | 89 --------------------------- 1 file changed, 89 deletions(-) delete mode 100644 arch/arm/boot/dts/r8a7790-lager-reference.dts (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7790-lager-reference.dts b/arch/arm/boot/dts/r8a7790-lager-reference.dts deleted file mode 100644 index dfedc0e..0000000 --- a/arch/arm/boot/dts/r8a7790-lager-reference.dts +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Device Tree Source for the Lager board - * - * Copyright (C) 2013 Renesas Solutions Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/dts-v1/; -#include "r8a7790.dtsi" -#include - -/ { - model = "Lager"; - compatible = "renesas,lager-reference", "renesas,r8a7790"; - - chosen { - bootargs = "console=ttySC6,115200 ignore_loglevel rw"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0 0x40000000 0 0x80000000>; - }; - - memory@180000000 { - device_type = "memory"; - reg = <1 0x80000000 0 0x80000000>; - }; - - lbsc { - #address-cells = <1>; - #size-cells = <1>; - }; - - leds { - compatible = "gpio-leds"; - led6 { - gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; - }; - led7 { - gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>; - }; - led8 { - gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; - }; - }; - - fixedregulator3v3: fixedregulator@0 { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&pfc { - pinctrl-0 = <&scif0_pins &scif1_pins>; - pinctrl-names = "default"; - - scif0_pins: serial0 { - renesas,groups = "scif0_data"; - renesas,function = "scif0"; - }; - - scif1_pins: serial1 { - renesas,groups = "scif1_data"; - renesas,function = "scif1"; - }; - - mmc1_pins: mmc1 { - renesas,groups = "mmc1_data8", "mmc1_ctrl"; - renesas,function = "mmc1"; - }; -}; - -&mmcif1 { - pinctrl-0 = <&mmc1_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&fixedregulator3v3>; - bus-width = <8>; - non-removable; - status = "okay"; -}; -- cgit v1.1 From 365c483f190fea03971b3eca8d68406f425777b5 Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Wed, 18 Dec 2013 18:22:58 +0530 Subject: ARM: tegra: fix missing pincontrol configuration for Venice2 Compare the initial population of default pinmux configuration of Venice2 with the chrome branch and add/fix the missing configurations. Signed-off-by: Laxman Dewangan Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124-venice2.dts | 308 ++++++++++++++++++++++++++++----- 1 file changed, 260 insertions(+), 48 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index d6bb25c..6bc4e07 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -23,34 +23,40 @@ nvidia,tristate = ; }; dap1_din_pn1 { - nvidia,pins = "dap1_din_pn1", - "dap1_dout_pn2", + nvidia,pins = "dap1_din_pn1"; + nvidia,function = "i2s0"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + dap1_dout_pn2 { + nvidia,pins = "dap1_dout_pn2", "dap1_fs_pn0", "dap1_sclk_pn3"; nvidia,function = "i2s0"; - nvidia,enable-input = ; + nvidia,enable-input = ; nvidia,pull = ; nvidia,tristate = ; }; dap2_din_pa4 { - nvidia,pins = "dap2_din_pa4", - "dap2_dout_pa5", - "dap2_fs_pa2", - "dap2_sclk_pa3"; + nvidia,pins = "dap2_din_pa4"; nvidia,function = "i2s1"; nvidia,enable-input = ; nvidia,pull = ; nvidia,tristate = ; }; - dvfs_pwm_px0 { - nvidia,pins = "dvfs_pwm_px0"; - nvidia,function = "cldvfs"; + dap2_dout_pa5 { + nvidia,pins = "dap2_dout_pa5", + "dap2_fs_pa2", + "dap2_sclk_pa3"; + nvidia,function = "i2s1"; nvidia,enable-input = ; nvidia,pull = ; - nvidia,tristate = ; + nvidia,tristate = ; }; - dvfs_clk_px2 { - nvidia,pins = "dvfs_clk_px2"; + dvfs_pwm_px0 { + nvidia,pins = "dvfs_pwm_px0", + "dvfs_clk_px2"; nvidia,function = "cldvfs"; nvidia,enable-input = ; nvidia,pull = ; @@ -58,12 +64,18 @@ }; ulpi_clk_py0 { nvidia,pins = "ulpi_clk_py0", - "ulpi_dir_py1", "ulpi_nxt_py2", "ulpi_stp_py3"; nvidia,function = "spi1"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + ulpi_dir_py1 { + nvidia,pins = "ulpi_dir_py1"; + nvidia,function = "spi1"; nvidia,enable-input = ; - nvidia,pull = ; + nvidia,pull = ; nvidia,tristate = ; }; cam_i2c_scl_pbb1 { @@ -90,19 +102,18 @@ nvidia,pins = "pg4", "pg5", "pg6", - "pg7", "pi3"; nvidia,function = "spi4"; nvidia,enable-input = ; nvidia,pull = ; nvidia,tristate = ; }; - ph0 { - nvidia,pins = "ph0"; - nvidia,function = "pwm0"; + pg7 { + nvidia,pins = "pg7"; + nvidia,function = "spi4"; nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; + nvidia,pull = ; + nvidia,tristate = ; }; ph1 { nvidia,pins = "ph1"; @@ -111,12 +122,14 @@ nvidia,pull = ; nvidia,tristate = ; }; - ph2 { - nvidia,pins = "ph2"; - nvidia,function = "gmi"; - nvidia,pull = ; + pk0 { + nvidia,pins = "pk0", + "kb_row15_ps7", + "clk_32k_out_pa0"; + nvidia,function = "soc"; + nvidia,pull = ; nvidia,tristate = ; - nvidia,enable-input = ; + nvidia,enable-input = ; }; sdmmc1_clk_pz0 { nvidia,pins = "sdmmc1_clk_pz0", @@ -130,6 +143,17 @@ nvidia,pull = ; nvidia,tristate = ; }; + sdmmc1_cmd_pz1 { + nvidia,pins = "sdmmc1_cmd_pz1", + "sdmmc1_dat0_py7", + "sdmmc1_dat1_py6", + "sdmmc1_dat2_py5", + "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; sdmmc3_clk_pa6 { nvidia,pins = "sdmmc3_clk_pa6"; nvidia,function = "sdmmc3"; @@ -179,6 +203,7 @@ nvidia,enable-input = ; nvidia,pull = ; nvidia,tristate = ; + nvidia,lock = ; nvidia,open-drain = ; }; jtag_rtck { @@ -231,12 +256,18 @@ nvidia,tristate = ; }; dap4_din_pp5 { - nvidia,pins = "dap4_din_pp5", - "dap4_dout_pp6", + nvidia,pins = "dap4_din_pp5"; + nvidia,function = "i2s3"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + dap4_dout_pp6 { + nvidia,pins = "dap4_dout_pp6", "dap4_fs_pp4", "dap4_sclk_pp7"; nvidia,function = "i2s3"; - nvidia,enable-input = ; + nvidia,enable-input = ; nvidia,pull = ; nvidia,tristate = ; }; @@ -248,51 +279,67 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,lock = ; - nvidia,open-drain = ; + nvidia,open-drain = ; }; - pu0 { - nvidia,pins = "pu0", - "pu1", - "pu2", - "pu3"; - nvidia,function = "uarta"; + uart2_cts_n_pj5 { + nvidia,pins = "uart2_cts_n_pj5"; + nvidia,function = "uartb"; nvidia,enable-input = ; nvidia,pull = ; nvidia,tristate = ; }; - uart2_cts_n_pj5 { - nvidia,pins = "uart2_cts_n_pj5", - "uart2_rts_n_pj6"; + uart2_rts_n_pj6 { + nvidia,pins = "uart2_rts_n_pj6"; nvidia,function = "uartb"; - nvidia,enable-input = ; + nvidia,enable-input = ; nvidia,pull = ; nvidia,tristate = ; }; uart2_rxd_pc3 { - nvidia,pins = "uart2_rxd_pc3", - "uart2_txd_pc2"; + nvidia,pins = "uart2_rxd_pc3"; nvidia,function = "irda"; nvidia,enable-input = ; nvidia,pull = ; nvidia,tristate = ; }; + uart2_txd_pc2 { + nvidia,pins = "uart2_txd_pc2"; + nvidia,function = "irda"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; uart3_cts_n_pa1 { nvidia,pins = "uart3_cts_n_pa1", - "uart3_rts_n_pc0", - "uart3_rxd_pw7", - "uart3_txd_pw6"; + "uart3_rxd_pw7"; nvidia,function = "uartc"; nvidia,enable-input = ; nvidia,pull = ; nvidia,tristate = ; }; + uart3_rts_n_pc0 { + nvidia,pins = "uart3_rts_n_pc0", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; hdmi_cec_pee3 { nvidia,pins = "hdmi_cec_pee3"; nvidia,function = "cec"; nvidia,enable-input = ; nvidia,pull = ; nvidia,tristate = ; - nvidia,open-drain = ; + nvidia,lock = ; + nvidia,open-drain = ; + }; + hdmi_int_pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "rsvd1"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; }; ddc_scl_pv4 { nvidia,pins = "ddc_scl_pv4", @@ -301,6 +348,52 @@ nvidia,enable-input = ; nvidia,pull = ; nvidia,tristate = ; + nvidia,lock = ; + nvidia,rcv-sel = ; + }; + pj7 { + nvidia,pins = "pj7", + "pk7"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pb0 { + nvidia,pins = "pb0", + "pb1"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph0 { + nvidia,pins = "ph0"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row10_ps2 { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row9_ps1 { + nvidia,pins = "kb_row9_ps1"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row6_pr6 { + nvidia,pins = "kb_row6_pr6"; + nvidia,function = "displaya_alt"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; }; usb_vbus_en0_pn4 { nvidia,pins = "usb_vbus_en0_pn4"; @@ -309,7 +402,7 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,lock = ; - nvidia,open-drain = ; + nvidia,open-drain = ; }; usb_vbus_en1_pn5 { nvidia,pins = "usb_vbus_en1_pn5"; @@ -318,7 +411,7 @@ nvidia,pull = ; nvidia,tristate = ; nvidia,lock = ; - nvidia,open-drain = ; + nvidia,open-drain = ; }; drive_sdio1 { nvidia,pins = "drive_sdio1"; @@ -351,6 +444,125 @@ nvidia,slew-rate-falling = ; nvidia,drive-type = <1>; }; + als_irq_l { + nvidia,pins = "gpio_x3_aud_px3"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + codec_irq_l { + nvidia,pins = "ph4"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_bl_en { + nvidia,pins = "ph2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + touch_irq_l { + nvidia,pins = "gpio_w3_aud_pw3"; + nvidia,function = "spi6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + tpm_davint_l { + nvidia,pins = "ph6"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ts_irq_l { + nvidia,pins = "pk2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ts_reset_l { + nvidia,pins = "pk4"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ts_shdn_l { + nvidia,pins = "pk1"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph7 { + nvidia,pins = "ph7"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col0_ap { + nvidia,pins = "kb_col0_pq0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lid_open { + nvidia,pins = "kb_row4_pr4"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + en_vdd_sd { + nvidia,pins = "kb_row0_pr0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ac_ok { + nvidia,pins = "pj0"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sensor_irq_l { + nvidia,pins = "pi6"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + wifi_en { + nvidia,pins = "gpio_x7_aud_px7"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + wifi_rst_l { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "dap"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + hp_det_l { + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "spi3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; }; }; -- cgit v1.1 From fcacaba7326628e854865f59b169d3054e27b77f Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Wed, 18 Dec 2013 18:22:59 +0530 Subject: ARM: tegra: add ams AS3722 device to Venice2 DT Add ams AS3722 entry for gpio/pincontrol and regulators to venice2 DT. Signed-off-by: Laxman Dewangan Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124-venice2.dts | 297 ++++++++++++++++++++++++++++++++- 1 file changed, 296 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 6bc4e07..a9f0df9 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -603,7 +603,201 @@ i2c@7000d000 { status = "okay"; - clock-frequency = <100000>; + clock-frequency = <400000>; + + as3722: as3722@40 { + compatible = "ams,as3722"; + reg = <0x40>; + interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; + + #interrupt-cells = <2>; + interrupt-controller; + + gpio-controller; + #gpio-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&as3722_default>; + + as3722_default: pinmux { + gpio0 { + pins = "gpio0"; + function = "gpio"; + bias-pull-down; + }; + + gpio1_2_4_7 { + pins = "gpio1", "gpio2", "gpio4", "gpio7"; + function = "gpio"; + bias-pull-up; + }; + + gpio3_6 { + pins = "gpio3", "gpio6"; + bias-high-impedance; + }; + + gpio5 { + pins = "gpio5"; + function = "clk32k-out"; + }; + }; + + regulators { + vsup-sd2-supply = <&vdd_ac_bat_reg>; + vsup-sd3-supply = <&vdd_ac_bat_reg>; + vsup-sd4-supply = <&vdd_ac_bat_reg>; + vsup-sd5-supply = <&vdd_ac_bat_reg>; + vin-ldo0-supply = <&as3722_sd2>; + vin-ldo1-6-supply = <&vdd_ac_bat_reg>; + vin-ldo2-5-7-supply = <&as3722_sd5>; + vin-ldo3-4-supply = <&vdd_ac_bat_reg>; + vin-ldo9-10-supply = <&vdd_ac_bat_reg>; + vin-ldo11-supply = <&vdd_ac_bat_reg>; + + sd0 { + regulator-name = "vdd-cpu"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1400000>; + regulator-min-microamp = <3500000>; + regulator-max-microamp = <3500000>; + regulator-always-on; + regulator-boot-on; + ams,external-control = <2>; + }; + + sd1 { + regulator-name = "vdd-core"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-min-microamp = <2500000>; + regulator-max-microamp = <2500000>; + regulator-always-on; + regulator-boot-on; + ams,external-control = <1>; + }; + + as3722_sd2: sd2 { + regulator-name = "vddio-ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + sd3 { + regulator-name = "vddio-ddr-2phase"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + sd4 { + regulator-name = "avdd-pex-sata"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-boot-on; + regulator-always-on; + }; + + as3722_sd5: sd5 { + regulator-name = "vddio-sys"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + sd6 { + regulator-name = "vdd-gpu"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <1200000>; + regulator-min-microamp = <3500000>; + regulator-max-microamp = <3500000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo0 { + regulator-name = "avdd_pll"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-boot-on; + regulator-always-on; + ams,external-control = <1>; + }; + + ldo1 { + regulator-name = "run-cam-1.8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo2 { + regulator-name = "gen-avdd,vddio-hsic"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3 { + regulator-name = "vdd-rtc"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + ams,enable-tracking; + }; + + ldo4 { + regulator-name = "vdd-cam"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5 { + regulator-name = "vdd-cam-front"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo6 { + regulator-name = "vddio-sdmmc3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo7 { + regulator-name = "vdd-cam-rear"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + ldo9 { + regulator-name = "vdd-touch"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo10 { + regulator-name = "vdd-cam-af"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo11 { + regulator-name = "vpp-fuse"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; }; pmc@7000e400 { @@ -648,6 +842,107 @@ }; }; + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vdd_ac_bat_reg: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "vdd_ac_bat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + vdd_3v3_reg: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "vdd_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&as3722 1 GPIO_ACTIVE_HIGH>; + }; + + vdd_3v3_modem_reg: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "vdd-modem-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&as3722 2 GPIO_ACTIVE_HIGH>; + }; + + vdd_hdmi_5v0_reg: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "vdd-hdmi-5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; + }; + + vdd_bl_reg: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "vdd-bl"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_LOW>; + }; + + vdd_ts_sw_5v0: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "vdd_ts_sw"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_LOW>; + }; + + usb1_vbus_reg: regulator@6 { + compatible = "regulator-fixed"; + reg = <6>; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; + gpio-open-drain; + }; + + usb3_vbus_reg: regulator@7 { + compatible = "regulator-fixed"; + reg = <7>; + regulator-name = "usb3_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; + gpio-open-drain; + }; + + panel_3v3_reg: regulator@8 { + compatible = "regulator-fixed"; + reg = <8>; + regulator-name = "panel_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&as3722 4 GPIO_ACTIVE_HIGH>; + }; + }; + sound { compatible = "nvidia,tegra-audio-max98090-venice2", "nvidia,tegra-audio-max98090"; -- cgit v1.1 From b1afa7822da4b8f49f003cc3a494d524907c1d3d Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 19 Dec 2013 11:32:15 -0700 Subject: ARM: tegra: set up /aliases for RTCs on Venice2 This ensures that the PMIC RTC provides the system time, rather than the on-SoC RTC, which is not battery-backed. Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124-venice2.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index a9f0df9..e6b3e97 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -6,6 +6,11 @@ model = "NVIDIA Tegra124 Venice2"; compatible = "nvidia,venice2", "nvidia,tegra124"; + aliases { + rtc0 = "/i2c@7000d000/as3722@40"; + rtc1 = "/rtc@7000e000"; + }; + memory { reg = <0x80000000 0x80000000>; }; -- cgit v1.1 From 1d4e06894824514a2854b252d49c63b81779aec7 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 19 Dec 2013 16:59:25 +0100 Subject: ARM: tegra: Enable LVDS on Harmony Add backlight and panel nodes for the Harmony TFT LCD panel. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra20-harmony.dts | 36 +++++++++++++++++++++++++++++++++-- 1 file changed, 34 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index 6145f26..3fb1f50 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -17,6 +17,14 @@ }; host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + + nvidia,panel = <&panel>; + }; + }; + hdmi@54280000 { status = "okay"; @@ -261,6 +269,10 @@ status = "okay"; }; + pwm: pwm@7000a000 { + status = "okay"; + }; + i2c@7000c000 { status = "okay"; clock-frequency = <400000>; @@ -606,6 +618,17 @@ bus-width = <8>; }; + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(B, 5) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_bl_reg>; + pwms = <&pwm 0 5000000>; + + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + clocks { compatible = "simple-bus"; #address-cells = <1>; @@ -630,6 +653,15 @@ }; }; + panel: panel { + compatible = "auo,b101aw03", "simple-panel"; + + power-supply = <&vdd_pnl_reg>; + enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; + + backlight = <&backlight>; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -673,7 +705,7 @@ enable-active-high; }; - regulator@4 { + vdd_pnl_reg: regulator@4 { compatible = "regulator-fixed"; reg = <4>; regulator-name = "vdd_pnl"; @@ -683,7 +715,7 @@ enable-active-high; }; - regulator@5 { + vdd_bl_reg: regulator@5 { compatible = "regulator-fixed"; reg = <5>; regulator-name = "vdd_bl"; -- cgit v1.1 From 02b1fea2e4afba9a9b0b088d46afa62c9ff904bd Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 19 Dec 2013 16:59:26 +0100 Subject: ARM: tegra: Enable LVDS on Cardhu Add backlight and panel nodes for the Cardhu 10.1" WXGA TFT LCD panel. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra30-cardhu.dtsi | 37 ++++++++++++++++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index dfcc18a..9104224 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -56,6 +56,16 @@ }; }; + host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + + nvidia,panel = <&panel>; + }; + }; + }; + pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -152,7 +162,11 @@ status = "okay"; }; - i2c@7000c000 { + pwm@7000a000 { + status = "okay"; + }; + + panelddc: i2c@7000c000 { status = "okay"; clock-frequency = <100000>; }; @@ -372,6 +386,17 @@ status = "okay"; }; + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_bl_reg>; + pwms = <&pwm 0 5000000>; + + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + clocks { compatible = "simple-bus"; #address-cells = <1>; @@ -385,6 +410,16 @@ }; }; + panel: panel { + compatible = "chunghwa,claa101wb01", "simple-panel"; + ddc-i2c-bus = <&panelddc>; + + power-supply = <&vdd_pnl1_reg>; + enable-gpios = <&gpio TEGRA_GPIO(L, 2) GPIO_ACTIVE_HIGH>; + + backlight = <&backlight>; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; -- cgit v1.1 From f3ab052786e98b23f326bc28ec43b793495c9b6c Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Thu, 19 Dec 2013 11:59:17 +0800 Subject: ARM: at91: add PWM device node Add PWM device node for AT91 series SoC. Signed-off-by: Bo Shen Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/at91sam9263.dtsi | 9 +++++++++ arch/arm/boot/dts/at91sam9g45.dtsi | 9 +++++++++ arch/arm/boot/dts/at91sam9n12.dtsi | 9 +++++++++ arch/arm/boot/dts/at91sam9x5.dtsi | 9 +++++++++ arch/arm/boot/dts/sama5d3.dtsi | 10 ++++++++++ 5 files changed, 46 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index 22e255a..c8fa9b9 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi @@ -30,6 +30,7 @@ i2c0 = &i2c0; ssc0 = &ssc0; ssc1 = &ssc1; + pwm0 = &pwm0; }; cpus { #address-cells = <0>; @@ -575,6 +576,14 @@ pinctrl-0 = <&pinctrl_spi1>; status = "disabled"; }; + + pwm0: pwm@fffb8000 { + compatible = "atmel,at91sam9rl-pwm"; + reg = <0xfffb8000 0x300>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 4>; + #pwm-cells = <3>; + status = "disabled"; + }; }; fb0: fb@0x00700000 { diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index d7af9ec..ef0857c 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -37,6 +37,7 @@ i2c1 = &i2c1; ssc0 = &ssc0; ssc1 = &ssc1; + pwm0 = &pwm0; }; cpus { #address-cells = <0>; @@ -670,6 +671,14 @@ }; }; + pwm0: pwm@fffb8000 { + compatible = "atmel,at91sam9rl-pwm"; + reg = <0xfffb8000 0x300>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>; + #pwm-cells = <3>; + status = "disabled"; + }; + mmc0: mmc@fff80000 { compatible = "atmel,hsmci"; reg = <0xfff80000 0x600>; diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index 6224f9f..7248270 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -33,6 +33,7 @@ i2c0 = &i2c0; i2c1 = &i2c1; ssc0 = &ssc0; + pwm0 = &pwm0; }; cpus { #address-cells = <0>; @@ -542,6 +543,14 @@ reg = <0xfffffe40 0x10>; status = "disabled"; }; + + pwm0: pwm@f8034000 { + compatible = "atmel,at91sam9rl-pwm"; + reg = <0xf8034000 0x300>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; + #pwm-cells = <3>; + status = "disabled"; + }; }; nand0: nand@40000000 { diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index 40267a1..6e5e9cf 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -35,6 +35,7 @@ i2c1 = &i2c1; i2c2 = &i2c2; ssc0 = &ssc0; + pwm0 = &pwm0; }; cpus { #address-cells = <0>; @@ -762,6 +763,14 @@ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; status = "disabled"; }; + + pwm0: pwm@f8034000 { + compatible = "atmel,at91sam9rl-pwm"; + reg = <0xf8034000 0x300>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; + #pwm-cells = <3>; + status = "disabled"; + }; }; nand0: nand@40000000 { diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 070c5c3..7bd226c 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -37,6 +37,7 @@ i2c2 = &i2c2; ssc0 = &ssc0; ssc1 = &ssc1; + pwm0 = &pwm0; }; cpus { #address-cells = <1>; @@ -179,6 +180,15 @@ status = "disabled"; }; + pwm0: pwm@f002c000 { + compatible = "atmel,sama5d3-pwm"; + reg = <0xf002c000 0x300>; + interrupts = <28 IRQ_TYPE_LEVEL_HIGH 4>; + #pwm-cells = <3>; + clocks = <&pwm_clk>; + status = "disabled"; + }; + isi: isi@f0034000 { compatible = "atmel,at91sam9g45-isi"; reg = <0xf0034000 0x4000>; -- cgit v1.1 From eed972987bc52b75afd58d0bfb5f605a82c8502a Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Thu, 19 Dec 2013 11:59:18 +0800 Subject: ARM: at91: at91sam9m10g45ek: switch to PWM leds The d6 and d7 is connected to PWM, we can use PWM to control it, so switch to PWM leds. Signed-off-by: Bo Shen Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/at91sam9m10g45ek.dts | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts index 7b76dbd..7ff665a 100644 --- a/arch/arm/boot/dts/at91sam9m10g45ek.dts +++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts @@ -105,6 +105,14 @@ AT91_PIOD 29 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD29 gpio WP pin pull up */ }; }; + + pwm0 { + pinctrl_pwm_leds: pwm-led { + atmel,pins = + ; /* PD31 periph B */ + }; + }; }; spi0: spi@fffa4000{ @@ -121,6 +129,13 @@ atmel,vbus-gpio = <&pioB 19 GPIO_ACTIVE_HIGH>; status = "okay"; }; + + pwm0: pwm@fffb8000 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_leds>; + }; }; fb0: fb@0x00500000 { @@ -194,16 +209,22 @@ gpios = <&pioD 30 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; + }; + + pwmleds { + compatible = "pwm-leds"; d6 { label = "d6"; - gpios = <&pioD 0 GPIO_ACTIVE_LOW>; + pwms = <&pwm0 3 5000 0>; + max-brightness = <255>; linux,default-trigger = "nand-disk"; }; d7 { label = "d7"; - gpios = <&pioD 31 GPIO_ACTIVE_LOW>; + pwms = <&pwm0 1 5000 0>; + max-brightness = <255>; linux,default-trigger = "mmc0"; }; }; -- cgit v1.1 From 4df4f446ef881a351ebf50107f2ac6ddb557ab46 Mon Sep 17 00:00:00 2001 From: Boris BREZILLON Date: Thu, 19 Dec 2013 16:11:13 +0100 Subject: ARM: at91/dt: add clk properties to sama5d3 SHA device node Signed-off-by: Boris BREZILLON Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/sama5d3.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 7bd226c..321e24b 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -350,6 +350,8 @@ interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>; dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(17)>; dma-names = "tx"; + clocks = <&sha_clk>; + clock-names = "sha_clk"; }; aes@f8038000 { -- cgit v1.1 From f68cd3565b11b8d7e99d47d3f4e9d6032b6f25d3 Mon Sep 17 00:00:00 2001 From: Boris BREZILLON Date: Thu, 19 Dec 2013 16:11:14 +0100 Subject: ARM: at91/dt: add clk properties to sama5d3 AES device node Signed-off-by: Boris BREZILLON Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/sama5d3.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 321e24b..d969c86 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -361,6 +361,8 @@ dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(18)>, <&dma1 2 AT91_DMA_CFG_PER_ID(19)>; dma-names = "tx", "rx"; + clocks = <&aes_clk>; + clock-names = "aes_clk"; }; tdes@f803c000 { -- cgit v1.1 From 45e5c2cb6bc1c52c7134f898ea326a422dd75761 Mon Sep 17 00:00:00 2001 From: Boris BREZILLON Date: Thu, 19 Dec 2013 16:11:15 +0100 Subject: ARM: at91/dt: add clk properties to sama5d3 TDES device node Signed-off-by: Boris BREZILLON Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/sama5d3.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index d969c86..a1758e9 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -372,6 +372,8 @@ dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(20)>, <&dma1 2 AT91_DMA_CFG_PER_ID(21)>; dma-names = "tx", "rx"; + clocks = <&tdes_clk>; + clock-names = "tdes_clk"; }; dma0: dma-controller@ffffe600 { -- cgit v1.1 From e3d04d179c84931c4b27bab82b623119c0423f66 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 19 Dec 2013 16:59:27 +0100 Subject: ARM: tegra: Add MIPI calibration DT entries for Tegra114 Add a device node for the MIPI calibration block on Tegra114. There is no need to disable it by default because it only enables the clock while performing calibration and therefore shouldn't be consuming any power when unused. Signed-off-by: Thierry Reding [swarren, add unit address to new DT node name] Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra114.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index ae855ec..89a9401 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -480,6 +480,13 @@ }; }; + mipi: mipi@700e3000 { + compatible = "nvidia,tegra114-mipi"; + reg = <0x700e3000 0x100>; + clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>; + #nvidia,mipi-calibrate-cells = <1>; + }; + sdhci@78000000 { compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; reg = <0x78000000 0x200>; -- cgit v1.1 From 65344b936e807cb9f14be64d56b785eafb348842 Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Thu, 19 Dec 2013 16:59:28 +0100 Subject: ARM: tegra: Add host1x, DC and HDMI to Tegra114 device tree Add host1x, DC (display controller) and HDMI devices to Tegra114 device tree. Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra114.dtsi | 57 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 89a9401..2fd7f90 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -16,6 +16,63 @@ serial3 = &uartd; }; + host1x@50000000 { + compatible = "nvidia,tegra114-host1x", "simple-bus"; + reg = <0x50000000 0x00028000>; + interrupts = , /* syncpt */ + ; /* general */ + clocks = <&tegra_car TEGRA114_CLK_HOST1X>; + resets = <&tegra_car 28>; + reset-names = "host1x"; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x54000000 0x54000000 0x01000000>; + + dc@54200000 { + compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc"; + reg = <0x54200000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_DISP1>, + <&tegra_car TEGRA114_CLK_PLL_P>; + clock-names = "dc", "parent"; + resets = <&tegra_car 27>; + reset-names = "dc"; + + rgb { + status = "disabled"; + }; + }; + + dc@54240000 { + compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc"; + reg = <0x54240000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_DISP2>, + <&tegra_car TEGRA114_CLK_PLL_P>; + clock-names = "dc", "parent"; + resets = <&tegra_car 26>; + reset-names = "dc"; + + rgb { + status = "disabled"; + }; + }; + + hdmi@54280000 { + compatible = "nvidia,tegra114-hdmi"; + reg = <0x54280000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_HDMI>, + <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>; + clock-names = "hdmi", "parent"; + resets = <&tegra_car 51>; + reset-names = "hdmi"; + status = "disabled"; + }; + }; + gic: interrupt-controller@50041000 { compatible = "arm,cortex-a15-gic"; #interrupt-cells = <3>; -- cgit v1.1 From 7e4ba90fb9dd86a489856528ea43c93e4c750618 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 19 Dec 2013 16:59:29 +0100 Subject: ARM: tegra: Add Tegra114 DSI support Add device tree nodes for the DSI controllers found on Tegra114 SoCs. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra114.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 2fd7f90..8583b05 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -71,6 +71,38 @@ reset-names = "hdmi"; status = "disabled"; }; + + dsi@54300000 { + compatible = "nvidia,tegra114-dsi"; + reg = <0x54300000 0x00040000>; + clocks = <&tegra_car TEGRA114_CLK_DSIA>, + <&tegra_car TEGRA114_CLK_DSIALP>, + <&tegra_car TEGRA114_CLK_PLL_D_OUT0>; + clock-names = "dsi", "lp", "parent"; + resets = <&tegra_car 48>; + reset-names = "dsi"; + nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */ + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + + dsi@54400000 { + compatible = "nvidia,tegra114-dsi"; + reg = <0x54400000 0x00040000>; + clocks = <&tegra_car TEGRA114_CLK_DSIB>, + <&tegra_car TEGRA114_CLK_DSIBLP>, + <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>; + clock-names = "dsi", "lp", "parent"; + resets = <&tegra_car 82>; + reset-names = "dsi"; + nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */ + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; }; gic: interrupt-controller@50041000 { -- cgit v1.1 From 5648b260cf2d752b958864295dd83004c3220271 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 19 Dec 2013 16:59:30 +0100 Subject: ARM: tegra: Add Tegra114 gr2d support Add the device tree for the gr2d hardware found on Tegra114 SoCs. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra114.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 8583b05..2faecc6 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -30,6 +30,15 @@ ranges = <0x54000000 0x54000000 0x01000000>; + gr2d@54140000 { + compatible = "nvidia,tegra114-gr2d", "nvidia,tegra20-gr2d"; + reg = <0x54140000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_GR2D>; + resets = <&tegra_car 21>; + reset-names = "2d"; + }; + dc@54200000 { compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc"; reg = <0x54200000 0x00040000>; -- cgit v1.1 From 032f11f3ace8501f5c7c602deaa1cc25f1110513 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 19 Dec 2013 16:59:31 +0100 Subject: ARM: tegra: Add Tegra114 gr3d support Add the gr3d device tree node. The gr3d block on Tegra114 is backwards- compatible with the one on Tegra20. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra114.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 2faecc6..389e987 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -39,6 +39,14 @@ reset-names = "2d"; }; + gr3d@54180000 { + compatible = "nvidia,tegra114-gr3d", "nvidia,tegra20-gr3d"; + reg = <0x54180000 0x00040000>; + clocks = <&tegra_car TEGRA114_CLK_GR3D>; + resets = <&tegra_car 24>; + reset-names = "3d"; + }; + dc@54200000 { compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc"; reg = <0x54200000 0x00040000>; -- cgit v1.1 From 48b901171cbfdbed059acb92fdea7064bbbcd680 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 19 Dec 2013 16:59:32 +0100 Subject: ARM: tegra: Enable DSI support on Dalmore Dalmore has a 10.1" WUXGA panel connected to one of the DSI outputs of the Tegra114. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra114-dalmore.dts | 44 ++++++++++++++++++++++++---------- 1 file changed, 32 insertions(+), 12 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index ca44859..512922f 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -16,6 +16,21 @@ reg = <0x80000000 0x40000000>; }; + host1x@50000000 { + dsi@54300000 { + status = "okay"; + + panel@0 { + compatible = "panasonic,vvx10f004b00", + "simple-panel"; + reg = <0>; + + power-supply = <&avdd_lcd_reg>; + backlight = <&backlight>; + }; + }; + }; + pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -723,6 +738,10 @@ status = "okay"; }; + pwm@7000a000 { + status = "okay"; + }; + i2c@7000c000 { status = "okay"; clock-frequency = <100000>; @@ -811,7 +830,7 @@ regulator-boot-on; }; - fet1 { + vdd_bl_reg: fet1 { regulator-name = "vdd-lcd-bl"; }; @@ -819,7 +838,7 @@ regulator-name = "vdd-modem-3v3"; }; - fet4 { + avdd_lcd_reg: fet4 { regulator-name = "avdd-lcd"; }; @@ -1089,6 +1108,17 @@ vbus-supply = <&usb3_vbus_reg>; }; + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_bl_reg>; + pwms = <&pwm 1 1000000>; + + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + clocks { compatible = "simple-bus"; #address-cells = <1>; @@ -1155,16 +1185,6 @@ gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>; }; - lcd_bl_en_reg: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "lcd_bl_en"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; - }; - usb1_vbus_reg: regulator@3 { compatible = "regulator-fixed"; reg = <3>; -- cgit v1.1 From f044d6fa2345c32d32cff2024e93763749756656 Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Thu, 19 Dec 2013 16:59:33 +0100 Subject: ARM: tegra: Enable HDMI support on Dalmore Add HDMI node to the Dalmore device tree and hook up the VDD and PLL regulators as well as the I2C adapter used for DDC and the GPIO used for hotplug detection. Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra114-dalmore.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index 512922f..73aecfb 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -17,6 +17,17 @@ }; host1x@50000000 { + hdmi@54280000 { + status = "okay"; + + vdd-supply = <&vdd_hdmi_reg>; + pll-supply = <&palmas_smps3_reg>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = + <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + }; + dsi@54300000 { status = "okay"; @@ -773,6 +784,10 @@ }; }; + hdmi_ddc: i2c@7000c700 { + status = "okay"; + }; + i2c@7000d000 { status = "okay"; clock-frequency = <400000>; -- cgit v1.1 From 49a9b0be292c095ac28bd81c1011d14e8437b72d Mon Sep 17 00:00:00 2001 From: Arnaud Ebalard Date: Thu, 19 Dec 2013 23:02:05 +0100 Subject: ARM: mvebu: Enable ISL12057 RTC chip in ReadyNAS 102 .dts file Now that support for Intersil ISL12057 RTC chip is available upstream, let's enable it in NETGEAR ReadyNAS 102 .dts file so that the device stop believing it's the 70's. Signed-off-by: Arnaud Ebalard Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-370-netgear-rn102.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts index 6a7383f..651aeb5 100644 --- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts +++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts @@ -122,6 +122,11 @@ clock-frequency = <100000>; status = "okay"; + isl12057: isl12057@68 { + compatible = "isl,isl12057"; + reg = <0x68>; + }; + g762: g762@3e { compatible = "gmt,g762"; reg = <0x3e>; -- cgit v1.1 From c0d1c266a1cc1b7256ade6ad7d92ecb1a9f4895b Mon Sep 17 00:00:00 2001 From: Arnaud Ebalard Date: Thu, 19 Dec 2013 23:02:15 +0100 Subject: ARM: mvebu: Enable ISL12057 RTC chip in ReadyNAS 104 .dts file Now that support for Intersil ISL12057 RTC chip is available upstream, let's enable it in NETGEAR ReadyNAS 104 .dts file so that the device stop believing it's the 70's. Signed-off-by: Arnaud Ebalard Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-370-netgear-rn104.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/armada-370-netgear-rn104.dts index 272e2e2..4e27587 100644 --- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts +++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts @@ -117,6 +117,11 @@ clock-frequency = <100000>; status = "okay"; + isl12057: isl12057@68 { + compatible = "isl,isl12057"; + reg = <0x68>; + }; + g762: g762@3e { compatible = "gmt,g762"; reg = <0x3e>; -- cgit v1.1 From 797090dfca7fbdd69752425693eda19b28cb5db5 Mon Sep 17 00:00:00 2001 From: Arnaud Ebalard Date: Thu, 19 Dec 2013 23:02:27 +0100 Subject: ARM: mvebu: Enable ISL12057 RTC chip in ReadyNAS 2120 .dts file Now that support for Intersil ISL12057 RTC chip is available upstream, let's enable it in NETGEAR ReadyNAS 2120 .dts file so that the device stop believing it's the 70's. Signed-off-by: Arnaud Ebalard Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-xp-netgear-rn2120.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts index f048b4e..ff049ee 100644 --- a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts +++ b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts @@ -174,6 +174,11 @@ clock-frequency = <400000>; status = "okay"; + isl12057: isl12057@68 { + compatible = "isl,isl12057"; + reg = <0x68>; + }; + /* Controller for rear fan #1 of 3 (Protechnic * MGT4012XB-O20, 8000RPM) near eSATA port */ g762_fan1: g762@3e { -- cgit v1.1 From fd6441ec0ff9803e405df70a7cae784f2c9be204 Mon Sep 17 00:00:00 2001 From: Eric Brower Date: Thu, 19 Dec 2013 18:08:52 -0800 Subject: ARM: tegra: modify Tegra30 USB2 default phy_type to UTMI Modify Tegra30 default USB2 phy_type to UTMI; this matches power-on-reset defaults and is expected to be the common case. The current implementation is likely an incorrect carry-over from Tegra20, where USB2 does default to ULPI. Signed-off-by: Eric Brower Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra30.dtsi | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index ee5e9d8..ed8e770 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -785,7 +785,7 @@ compatible = "nvidia,tegra30-ehci", "usb-ehci"; reg = <0x7d004000 0x4000>; interrupts = ; - phy_type = "ulpi"; + phy_type = "utmi"; clocks = <&tegra_car TEGRA30_CLK_USB2>; resets = <&tegra_car 58>; reset-names = "usb"; @@ -795,12 +795,23 @@ phy2: usb-phy@7d004000 { compatible = "nvidia,tegra30-usb-phy"; - reg = <0x7d004000 0x4000>; - phy_type = "ulpi"; + reg = <0x7d004000 0x4000 0x7d000000 0x4000>; + phy_type = "utmi"; clocks = <&tegra_car TEGRA30_CLK_USB2>, <&tegra_car TEGRA30_CLK_PLL_U>, - <&tegra_car TEGRA30_CLK_CDEV2>; - clock-names = "reg", "pll_u", "ulpi-link"; + <&tegra_car TEGRA30_CLK_USBD>; + clock-names = "reg", "pll_u", "utmi-pads"; + nvidia,hssync-start-delay = <9>; + nvidia,idle-wait-delay = <17>; + nvidia,elastic-limit = <16>; + nvidia,term-range-adj = <6>; + nvidia,xcvr-setup = <51>; + nvidia.xcvr-setup-use-fuses; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + nvidia,xcvr-hsslew = <32>; + nvidia,hssquelch-level = <2>; + nvidia,hsdiscon-level = <5>; status = "disabled"; }; -- cgit v1.1 From 4c696500bcb8a2bab8651321cf648f2fe7868f63 Mon Sep 17 00:00:00 2001 From: Eric Brower Date: Thu, 19 Dec 2013 18:08:53 -0800 Subject: ARM: tegra: enable USB2 on Tegra30 Beaver Enable USB2 on Beaver, exposed via the mini-PCIe connector. Signed-off-by: Eric Brower Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra30-beaver.dts | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index d36c821..e93fe45b 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -333,6 +333,15 @@ non-removable; }; + usb@7d004000 { + status = "okay"; + }; + + phy2: usb-phy@7d004000 { + vbus-supply = <&sys_3v3_reg>; + status = "okay"; + }; + usb@7d008000 { status = "okay"; }; -- cgit v1.1 From 146db0eae8a9c7eabb374dbaac1c52a3f0ac61e4 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 19 Dec 2013 17:06:19 +0100 Subject: ARM: tegra: Enable Venice2 keyboard The keyboard on Venice2 is attached to the ChromeOS embedded controller. Add the corresponding device tree nodes and use the MATRIX_KEY define to encode keycodes. Signed-off-by: Rhyland Klein Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124-venice2.dts | 107 +++++++++++++++++++++++++++++++++ 1 file changed, 107 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index e6b3e97..ab7ca65 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -1,5 +1,6 @@ /dts-v1/; +#include #include "tegra124.dtsi" / { @@ -805,6 +806,112 @@ }; }; + spi@7000d400 { + status = "okay"; + + cros-ec@0 { + compatible = "google,cros-ec-spi"; + spi-max-frequency = <4000000>; + interrupt-parent = <&gpio>; + interrupts = ; + reg = <0>; + + google,cros-ec-spi-msg-delay = <2000>; + + cros-ec-keyb { + compatible = "google,cros-ec-keyb"; + keypad,num-rows = <8>; + keypad,num-columns = <13>; + google,needs-ghost-filter; + + linux,keymap = < + MATRIX_KEY(0x00, 0x01, KEY_LEFTMETA) + MATRIX_KEY(0x00, 0x02, KEY_F1) + MATRIX_KEY(0x00, 0x03, KEY_B) + MATRIX_KEY(0x00, 0x04, KEY_F10) + MATRIX_KEY(0x00, 0x06, KEY_N) + MATRIX_KEY(0x00, 0x08, KEY_EQUAL) + MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT) + + MATRIX_KEY(0x01, 0x01, KEY_ESC) + MATRIX_KEY(0x01, 0x02, KEY_F4) + MATRIX_KEY(0x01, 0x03, KEY_G) + MATRIX_KEY(0x01, 0x04, KEY_F7) + MATRIX_KEY(0x01, 0x06, KEY_H) + MATRIX_KEY(0x01, 0x08, KEY_APOSTROPHE) + MATRIX_KEY(0x01, 0x09, KEY_F9) + MATRIX_KEY(0x01, 0x0b, KEY_BACKSPACE) + + MATRIX_KEY(0x02, 0x00, KEY_LEFTCTRL) + MATRIX_KEY(0x02, 0x01, KEY_TAB) + MATRIX_KEY(0x02, 0x02, KEY_F3) + MATRIX_KEY(0x02, 0x03, KEY_T) + MATRIX_KEY(0x02, 0x04, KEY_F6) + MATRIX_KEY(0x02, 0x05, KEY_RIGHTBRACE) + MATRIX_KEY(0x02, 0x06, KEY_Y) + MATRIX_KEY(0x02, 0x07, KEY_102ND) + MATRIX_KEY(0x02, 0x08, KEY_LEFTBRACE) + MATRIX_KEY(0x02, 0x09, KEY_F8) + + MATRIX_KEY(0x03, 0x01, KEY_GRAVE) + MATRIX_KEY(0x03, 0x02, KEY_F2) + MATRIX_KEY(0x03, 0x03, KEY_5) + MATRIX_KEY(0x03, 0x04, KEY_F5) + MATRIX_KEY(0x03, 0x06, KEY_6) + MATRIX_KEY(0x03, 0x08, KEY_MINUS) + MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH) + + MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL) + MATRIX_KEY(0x04, 0x01, KEY_A) + MATRIX_KEY(0x04, 0x02, KEY_D) + MATRIX_KEY(0x04, 0x03, KEY_F) + MATRIX_KEY(0x04, 0x04, KEY_S) + MATRIX_KEY(0x04, 0x05, KEY_K) + MATRIX_KEY(0x04, 0x06, KEY_J) + MATRIX_KEY(0x04, 0x08, KEY_SEMICOLON) + MATRIX_KEY(0x04, 0x09, KEY_L) + MATRIX_KEY(0x04, 0x0a, KEY_BACKSLASH) + MATRIX_KEY(0x04, 0x0b, KEY_ENTER) + + MATRIX_KEY(0x05, 0x01, KEY_Z) + MATRIX_KEY(0x05, 0x02, KEY_C) + MATRIX_KEY(0x05, 0x03, KEY_V) + MATRIX_KEY(0x05, 0x04, KEY_X) + MATRIX_KEY(0x05, 0x05, KEY_COMMA) + MATRIX_KEY(0x05, 0x06, KEY_M) + MATRIX_KEY(0x05, 0x07, KEY_LEFTSHIFT) + MATRIX_KEY(0x05, 0x08, KEY_SLASH) + MATRIX_KEY(0x05, 0x09, KEY_DOT) + MATRIX_KEY(0x05, 0x0b, KEY_SPACE) + + MATRIX_KEY(0x06, 0x01, KEY_1) + MATRIX_KEY(0x06, 0x02, KEY_3) + MATRIX_KEY(0x06, 0x03, KEY_4) + MATRIX_KEY(0x06, 0x04, KEY_2) + MATRIX_KEY(0x06, 0x05, KEY_8) + MATRIX_KEY(0x06, 0x06, KEY_7) + MATRIX_KEY(0x06, 0x08, KEY_0) + MATRIX_KEY(0x06, 0x09, KEY_9) + MATRIX_KEY(0x06, 0x0a, KEY_LEFTALT) + MATRIX_KEY(0x06, 0x0b, KEY_DOWN) + MATRIX_KEY(0x06, 0x0c, KEY_RIGHT) + + MATRIX_KEY(0x07, 0x01, KEY_Q) + MATRIX_KEY(0x07, 0x02, KEY_E) + MATRIX_KEY(0x07, 0x03, KEY_R) + MATRIX_KEY(0x07, 0x04, KEY_W) + MATRIX_KEY(0x07, 0x05, KEY_I) + MATRIX_KEY(0x07, 0x06, KEY_U) + MATRIX_KEY(0x07, 0x07, KEY_RIGHTSHIFT) + MATRIX_KEY(0x07, 0x08, KEY_P) + MATRIX_KEY(0x07, 0x09, KEY_O) + MATRIX_KEY(0x07, 0x0b, KEY_UP) + MATRIX_KEY(0x07, 0x0c, KEY_LEFT) + >; + }; + }; + }; + pmc@7000e400 { nvidia,invert-interrupt; nvidia,suspend-mode = <1>; -- cgit v1.1 From 3f748d44503bd7ead26acf938f5a0bf845cea515 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 19 Dec 2013 17:06:20 +0100 Subject: ARM: tegra: Enable power key on Venice2 Contrary to the rest of the keyboard, which is connected to the ChromeOS embedded controller, the power key is hooked up to a GPIO. Add a device tree node to handle it. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124-venice2.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index ab7ca65..c6dcef5 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -954,6 +954,18 @@ }; }; + gpio-keys { + compatible = "gpio-keys"; + + power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + gpio-key,wakeup; + }; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; -- cgit v1.1 From e318853379f9c3cfaebc05a90cde9f6ac992be14 Mon Sep 17 00:00:00 2001 From: Padmavathi Venna Date: Thu, 19 Dec 2013 02:32:41 +0900 Subject: ARM: dts: Add DMA controller node info on Exynos5420 This patch adds dma controller node info on Exynos5420. Exynos5420 has adma for audio IPs. As adma clk is dependent on audss clk provider that will be added later. Signed-off-by: Padmavathi Venna Signed-off-by: Leela Krishna Amudala Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5420.dtsi | 52 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 76f4e0b..b802b24 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -271,6 +271,58 @@ status = "okay"; }; + amba { + #address-cells = <1>; + #size-cells = <1>; + compatible = "arm,amba-bus"; + interrupt-parent = <&gic>; + ranges; + + pdma0: pdma@121A0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x121A0000 0x1000>; + interrupts = <0 34 0>; + clocks = <&clock 362>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + + pdma1: pdma@121B0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x121B0000 0x1000>; + interrupts = <0 35 0>; + clocks = <&clock 363>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + + mdma0: mdma@10800000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x10800000 0x1000>; + interrupts = <0 33 0>; + clocks = <&clock 473>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <1>; + }; + + mdma1: mdma@11C10000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x11C10000 0x1000>; + interrupts = <0 124 0>; + clocks = <&clock 442>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <1>; + }; + }; + serial@12C00000 { clocks = <&clock 257>, <&clock 128>; clock-names = "uart", "clk_uart_baud0"; -- cgit v1.1 From e84a2d91e11d510f9553363dbf98eab4cf29460f Mon Sep 17 00:00:00 2001 From: Leela Krishna Amudala Date: Thu, 19 Dec 2013 02:36:37 +0900 Subject: ARM: dts: Add SPI nodes to the exynos5420 device tree file Add SPI device tree nodes to Exynos5420 SoC Signed-off-by: Doug Anderson Signed-off-by: Leela Krishna Amudala Reviewed-by: Andrew Bresticker Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5420.dtsi | 51 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index b802b24..be546f4 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -43,6 +43,9 @@ i2c10 = &hsi2c_10; gsc0 = &gsc_0; gsc1 = &gsc_1; + spi0 = &spi_0; + spi1 = &spi_1; + spi2 = &spi_2; }; cpus { @@ -323,6 +326,54 @@ }; }; + spi_0: spi@12d20000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x12d20000 0x100>; + interrupts = <0 66 0>; + dmas = <&pdma0 5 + &pdma0 4>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_bus>; + clocks = <&clock 271>, <&clock 135>; + clock-names = "spi", "spi_busclk0"; + status = "disabled"; + }; + + spi_1: spi@12d30000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x12d30000 0x100>; + interrupts = <0 67 0>; + dmas = <&pdma1 5 + &pdma1 4>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_bus>; + clocks = <&clock 272>, <&clock 136>; + clock-names = "spi", "spi_busclk0"; + status = "disabled"; + }; + + spi_2: spi@12d40000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x12d40000 0x100>; + interrupts = <0 68 0>; + dmas = <&pdma0 7 + &pdma0 6>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_bus>; + clocks = <&clock 273>, <&clock 137>; + clock-names = "spi", "spi_busclk0"; + status = "disabled"; + }; + serial@12C00000 { clocks = <&clock 257>, <&clock 128>; clock-names = "uart", "clk_uart_baud0"; -- cgit v1.1 From 022cf308de246d67b5df966c9ef6b5bd3ab75053 Mon Sep 17 00:00:00 2001 From: Leela Krishna Amudala Date: Thu, 19 Dec 2013 02:41:02 +0900 Subject: ARM: dts: add pwm DT nodes to Exynos5250 and Exynos5420 Add the device-tree binding for the PWM controller to Exynos5250 and Exynos5420 Signed-off-by: Andrew Bresticker Signed-off-by: Olof Johansson Signed-off-by: Leela Krishna Amudala Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5250.dtsi | 9 +++++++++ arch/arm/boot/dts/exynos5420.dtsi | 9 +++++++++ 2 files changed, 18 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 54dbd82..108739a 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -548,6 +548,15 @@ }; }; + pwm: pwm@12dd0000 { + compatible = "samsung,exynos4210-pwm"; + reg = <0x12dd0000 0x100>; + samsung,pwm-outputs = <0>, <1>, <2>, <3>; + #pwm-cells = <3>; + clocks = <&clock 311>; + clock-names = "timers"; + }; + amba { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index be546f4..1c1a6a0 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -394,6 +394,15 @@ clock-names = "uart", "clk_uart_baud0"; }; + pwm: pwm@12dd0000 { + compatible = "samsung,exynos4210-pwm"; + reg = <0x12dd0000 0x100>; + samsung,pwm-outputs = <0>, <1>, <2>, <3>; + #pwm-cells = <3>; + clocks = <&clock 279>; + clock-names = "timers"; + }; + dp_phy: video-phy@10040728 { compatible = "samsung,exynos5250-dp-video-phy"; reg = <0x10040728 4>; -- cgit v1.1 From 1b35bb80d830afc05cc36a5dfc2ecc5ad281168e Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Thu, 19 Dec 2013 03:17:39 +0900 Subject: ARM: dts: Drop interrupt controller properties from MCT nodes for exynos4 SoCs MCT is not an interrupt controller and so there is no point for device tree nodes representing it to contain interrupt-controller and #interrupt-cells properties. Signed-off-by: Tomasz Figa Acked-by: Kyungmin Park Reviewed-by: Sylwester Nawrocki Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos4210.dtsi | 2 -- arch/arm/boot/dts/exynos4212.dtsi | 2 -- arch/arm/boot/dts/exynos4412.dtsi | 2 -- 3 files changed, 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 057d682..1a6440ae6 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -51,8 +51,6 @@ mct@10050000 { compatible = "samsung,exynos4210-mct"; reg = <0x10050000 0x800>; - interrupt-controller; - #interrups-cells = <2>; interrupt-parent = <&mct_map>; interrupts = <0 0>, <1 0>, <2 0>, <3 0>, <4 0>, <5 0>; diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi index 6f34d7f..028752e 100644 --- a/arch/arm/boot/dts/exynos4212.dtsi +++ b/arch/arm/boot/dts/exynos4212.dtsi @@ -38,8 +38,6 @@ mct@10050000 { compatible = "samsung,exynos4412-mct"; reg = <0x10050000 0x800>; - interrupt-controller; - #interrups-cells = <2>; interrupt-parent = <&mct_map>; interrupts = <0 0>, <1 0>, <2 0>, <3 0>, <4 0>, <5 0>; diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index 85812bd..5bb2c18 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -38,8 +38,6 @@ mct@10050000 { compatible = "samsung,exynos4412-mct"; reg = <0x10050000 0x800>; - interrupt-controller; - #interrups-cells = <2>; interrupt-parent = <&mct_map>; interrupts = <0 0>, <1 0>, <2 0>, <3 0>, <4 0>, <5 0>, <6 0>, <7 0>; -- cgit v1.1 From 39e596f095a103176cfd7a54fd53c0fb9d6b8952 Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Thu, 19 Dec 2013 03:17:43 +0900 Subject: ARM: dts: Move MCT node to exynos4x12.dtsi For MCT block compatible with "samsung,exynos4412-mct", that uses PPI interrupts for local timers, only one local interrupt needs to be specified, since it is a per-processor interrupt. This allows moving MCT node of Exynos4x12 SoCs back to common exynos4x12.dtsi, since they have the same set of interrupts to be specified, which was the only difference. Signed-off-by: Tomasz Figa Acked-by: Kyungmin Park Reviewed-by: Sylwester Nawrocki Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos4212.dtsi | 20 -------------------- arch/arm/boot/dts/exynos4412.dtsi | 24 ------------------------ arch/arm/boot/dts/exynos4x12.dtsi | 20 ++++++++++++++++++++ 3 files changed, 20 insertions(+), 44 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi index 028752e..443b8a2 100644 --- a/arch/arm/boot/dts/exynos4212.dtsi +++ b/arch/arm/boot/dts/exynos4212.dtsi @@ -34,24 +34,4 @@ <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, <0 107 0>, <0 108 0>; }; - - mct@10050000 { - compatible = "samsung,exynos4412-mct"; - reg = <0x10050000 0x800>; - interrupt-parent = <&mct_map>; - interrupts = <0 0>, <1 0>, <2 0>, <3 0>, - <4 0>, <5 0>; - - mct_map: mct-map { - #interrupt-cells = <2>; - #address-cells = <0>; - #size-cells = <0>; - interrupt-map = <0x0 0 &gic 0 57 0>, - <0x1 0 &combiner 12 5>, - <0x2 0 &combiner 12 6>, - <0x3 0 &combiner 12 7>, - <0x4 0 &gic 1 12 0>, - <0x5 0 &gic 1 12 0>; - }; - }; }; diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index 5bb2c18..19918d6 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -35,28 +35,4 @@ <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>; }; - mct@10050000 { - compatible = "samsung,exynos4412-mct"; - reg = <0x10050000 0x800>; - interrupt-parent = <&mct_map>; - interrupts = <0 0>, <1 0>, <2 0>, <3 0>, - <4 0>, <5 0>, <6 0>, <7 0>; - clocks = <&clock 3>, <&clock 344>; - clock-names = "fin_pll", "mct"; - - mct_map: mct-map { - #interrupt-cells = <2>; - #address-cells = <0>; - #size-cells = <0>; - interrupt-map = <0x0 0 &gic 0 57 0>, - <0x1 0 &combiner 12 5>, - <0x2 0 &combiner 12 6>, - <0x3 0 &combiner 12 7>, - <0x4 0 &gic 1 12 0>, - <0x5 0 &gic 1 12 0>, - <0x6 0 &gic 1 12 0>, - <0x7 0 &gic 1 12 0>; - }; - }; - }; diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi index 1917c82..59127a9 100644 --- a/arch/arm/boot/dts/exynos4x12.dtsi +++ b/arch/arm/boot/dts/exynos4x12.dtsi @@ -42,6 +42,26 @@ #clock-cells = <1>; }; + mct@10050000 { + compatible = "samsung,exynos4412-mct"; + reg = <0x10050000 0x800>; + interrupt-parent = <&mct_map>; + interrupts = <0 0>, <1 0>, <2 0>, <3 0>, <4 0>; + clocks = <&clock 3>, <&clock 344>; + clock-names = "fin_pll", "mct"; + + mct_map: mct-map { + #interrupt-cells = <2>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = <0x0 0 &gic 0 57 0>, + <0x1 0 &combiner 12 5>, + <0x2 0 &combiner 12 6>, + <0x3 0 &combiner 12 7>, + <0x4 0 &gic 1 12 0>; + }; + }; + pinctrl_0: pinctrl@11400000 { compatible = "samsung,exynos4x12-pinctrl"; reg = <0x11400000 0x1000>; -- cgit v1.1 From 84ee1c150665c69b678b5d23d8e4c65478d6275f Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Thu, 19 Dec 2013 03:17:49 +0900 Subject: ARM: dts: Simplify MCT interrupt map for exynos4 SoCs There is no need to use two cells for interrupt specifiers inside the MCT interrupt map, so this patch simplifies the map to use one cell. Signed-off-by: Tomasz Figa Acked-by: Kyungmin Park Reviewed-by: Sylwester Nawrocki Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos4210.dtsi | 17 ++++++++--------- arch/arm/boot/dts/exynos4x12.dtsi | 14 +++++++------- 2 files changed, 15 insertions(+), 16 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 1a6440ae6..b0fee69 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -52,21 +52,20 @@ compatible = "samsung,exynos4210-mct"; reg = <0x10050000 0x800>; interrupt-parent = <&mct_map>; - interrupts = <0 0>, <1 0>, <2 0>, <3 0>, - <4 0>, <5 0>; + interrupts = <0>, <1>, <2>, <3>, <4>, <5>; clocks = <&clock 3>, <&clock 344>; clock-names = "fin_pll", "mct"; mct_map: mct-map { - #interrupt-cells = <2>; + #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = <0x0 0 &gic 0 57 0>, - <0x1 0 &gic 0 69 0>, - <0x2 0 &combiner 12 6>, - <0x3 0 &combiner 12 7>, - <0x4 0 &gic 0 42 0>, - <0x5 0 &gic 0 48 0>; + interrupt-map = <0 &gic 0 57 0>, + <1 &gic 0 69 0>, + <2 &combiner 12 6>, + <3 &combiner 12 7>, + <4 &gic 0 42 0>, + <5 &gic 0 48 0>; }; }; diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi index 59127a9..5c412aa 100644 --- a/arch/arm/boot/dts/exynos4x12.dtsi +++ b/arch/arm/boot/dts/exynos4x12.dtsi @@ -46,19 +46,19 @@ compatible = "samsung,exynos4412-mct"; reg = <0x10050000 0x800>; interrupt-parent = <&mct_map>; - interrupts = <0 0>, <1 0>, <2 0>, <3 0>, <4 0>; + interrupts = <0>, <1>, <2>, <3>, <4>; clocks = <&clock 3>, <&clock 344>; clock-names = "fin_pll", "mct"; mct_map: mct-map { - #interrupt-cells = <2>; + #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; - interrupt-map = <0x0 0 &gic 0 57 0>, - <0x1 0 &combiner 12 5>, - <0x2 0 &combiner 12 6>, - <0x3 0 &combiner 12 7>, - <0x4 0 &gic 1 12 0>; + interrupt-map = <0 &gic 0 57 0>, + <1 &combiner 12 5>, + <2 &combiner 12 6>, + <3 &combiner 12 7>, + <4 &gic 1 12 0>; }; }; -- cgit v1.1 From 0572b725368ae6d4b9791f183121fc70f84a035b Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Thu, 19 Dec 2013 03:17:54 +0900 Subject: ARM: dts: Fix missing spaces after labels for exynos For consistency with other device tree nodes, this patch adds missing spaces after node labels. Signed-off-by: Tomasz Figa Acked-by: Kyungmin Park Reviewed-by: Sylwester Nawrocki Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos4.dtsi | 4 ++-- arch/arm/boot/dts/exynos4210.dtsi | 4 ++-- arch/arm/boot/dts/exynos4212.dtsi | 2 +- arch/arm/boot/dts/exynos4412.dtsi | 2 +- arch/arm/boot/dts/exynos5.dtsi | 4 ++-- arch/arm/boot/dts/exynos5250-smdk5250.dts | 6 +++--- arch/arm/boot/dts/exynos5440.dtsi | 2 +- 7 files changed, 12 insertions(+), 12 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index c2a9964..08452e1 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -85,14 +85,14 @@ reg = <0x10023CE0 0x20>; }; - gic:interrupt-controller@10490000 { + gic: interrupt-controller@10490000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; reg = <0x10490000 0x1000>, <0x10480000 0x100>; }; - combiner:interrupt-controller@10440000 { + combiner: interrupt-controller@10440000 { compatible = "samsung,exynos4210-combiner"; #interrupt-cells = <2>; interrupt-controller; diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index b0fee69..48ecd7a 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -36,11 +36,11 @@ reg = <0x10023CA0 0x20>; }; - gic:interrupt-controller@10490000 { + gic: interrupt-controller@10490000 { cpu-offset = <0x8000>; }; - combiner:interrupt-controller@10440000 { + combiner: interrupt-controller@10440000 { samsung,combiner-nr = <16>; interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi index 443b8a2..94a43f9 100644 --- a/arch/arm/boot/dts/exynos4212.dtsi +++ b/arch/arm/boot/dts/exynos4212.dtsi @@ -22,7 +22,7 @@ / { compatible = "samsung,exynos4212"; - gic:interrupt-controller@10490000 { + gic: interrupt-controller@10490000 { cpu-offset = <0x8000>; }; diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index 19918d6..87b339c7 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -22,7 +22,7 @@ / { compatible = "samsung,exynos4412"; - gic:interrupt-controller@10490000 { + gic: interrupt-controller@10490000 { cpu-offset = <0x4000>; }; diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi index e52b038..258dca4 100644 --- a/arch/arm/boot/dts/exynos5.dtsi +++ b/arch/arm/boot/dts/exynos5.dtsi @@ -23,7 +23,7 @@ reg = <0x10000000 0x100>; }; - combiner:interrupt-controller@10440000 { + combiner: interrupt-controller@10440000 { compatible = "samsung,exynos4210-combiner"; #interrupt-cells = <2>; interrupt-controller; @@ -39,7 +39,7 @@ <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; }; - gic:interrupt-controller@10481000 { + gic: interrupt-controller@10481000 { compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 13746df..3f80c23 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -37,7 +37,7 @@ }; }; - vdd:fixed-regulator@0 { + vdd: fixed-regulator@0 { compatible = "regulator-fixed"; regulator-name = "vdd-supply"; regulator-min-microvolt = <1800000>; @@ -45,7 +45,7 @@ regulator-always-on; }; - dbvdd:fixed-regulator@1 { + dbvdd: fixed-regulator@1 { compatible = "regulator-fixed"; regulator-name = "dbvdd-supply"; regulator-min-microvolt = <3300000>; @@ -53,7 +53,7 @@ regulator-always-on; }; - spkvdd:fixed-regulator@2 { + spkvdd: fixed-regulator@2 { compatible = "regulator-fixed"; regulator-name = "spkvdd-supply"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi index 8da1070..02a0a12 100644 --- a/arch/arm/boot/dts/exynos5440.dtsi +++ b/arch/arm/boot/dts/exynos5440.dtsi @@ -29,7 +29,7 @@ #clock-cells = <1>; }; - gic:interrupt-controller@2E0000 { + gic: interrupt-controller@2E0000 { compatible = "arm,cortex-a15-gic"; #interrupt-cells = <3>; interrupt-controller; -- cgit v1.1 From e8dd3ee3297dff68827699540a1a93132dccf6e2 Mon Sep 17 00:00:00 2001 From: Yuvaraj Kumar C D Date: Thu, 19 Dec 2013 04:31:19 +0900 Subject: ARM: dts: Fix status property of mmc nodes for snow board Commit e908d5c5 ("ARM: dts: change status property of dwmmc nodes for exynos5250") missed out handling the exynos5250 snow dts file. Signed-off-by: Abhilash Kesavan Signed-off-by: Yuvaraj Kumar C D Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/cros5250-common.dtsi | 4 ---- arch/arm/boot/dts/exynos5250-snow.dts | 9 +++++++++ 2 files changed, 9 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/cros5250-common.dtsi b/arch/arm/boot/dts/cros5250-common.dtsi index 03cb897..2dd70e9 100644 --- a/arch/arm/boot/dts/cros5250-common.dtsi +++ b/arch/arm/boot/dts/cros5250-common.dtsi @@ -246,10 +246,6 @@ }; }; - mmc@12210000 { - status = "disabled"; - }; - mmc@12220000 { num-slots = <1>; supports-highspeed; diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts index 582e78d..4c9a023 100644 --- a/arch/arm/boot/dts/exynos5250-snow.dts +++ b/arch/arm/boot/dts/exynos5250-snow.dts @@ -172,11 +172,20 @@ }; }; + mmc@12200000 { + status = "okay"; + }; + + mmc@12220000 { + status = "okay"; + }; + /* * On Snow we've got SIP WiFi and so can keep drive strengths low to * reduce EMI. */ mmc@12230000 { + status = "okay"; slot@0 { pinctrl-names = "default"; pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>; -- cgit v1.1 From 655de648323f633d450032ecd9494995a0759f19 Mon Sep 17 00:00:00 2001 From: Naveen Krishna Chatradhi Date: Sat, 21 Dec 2013 05:59:49 +0900 Subject: ARM: dts: Add device nodes for TMU blocks for exynos5420 Exynos5420 SoC has per core thermal management unit. 5 TMU channels 4 for CPUs and 5th for GPU. This patch adds the device tree nodes to the DT device list. Nodes carry the misplaced second base address and the second clock to access the misplaced base address. Signed-off-by: Leela Krishna Amudala Signed-off-by: Naveen Krishna Chatradhi Signed-off-by: Andrew Bresticker Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5420.dtsi | 40 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 1c1a6a0..11dd202 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -612,4 +612,44 @@ clock-names = "gscl"; samsung,power-domain = <&gsc_pd>; }; + + tmu_cpu0: tmu@10060000 { + compatible = "samsung,exynos5420-tmu"; + reg = <0x10060000 0x100>; + interrupts = <0 65 0>; + clocks = <&clock 318>; + clock-names = "tmu_apbif"; + }; + + tmu_cpu1: tmu@10064000 { + compatible = "samsung,exynos5420-tmu"; + reg = <0x10064000 0x100>; + interrupts = <0 183 0>; + clocks = <&clock 318>; + clock-names = "tmu_apbif"; + }; + + tmu_cpu2: tmu@10068000 { + compatible = "samsung,exynos5420-tmu-ext-triminfo"; + reg = <0x10068000 0x100>, <0x1006c000 0x4>; + interrupts = <0 184 0>; + clocks = <&clock 318>, <&clock 318>; + clock-names = "tmu_apbif", "tmu_triminfo_apbif"; + }; + + tmu_cpu3: tmu@1006c000 { + compatible = "samsung,exynos5420-tmu-ext-triminfo"; + reg = <0x1006c000 0x100>, <0x100a0000 0x4>; + interrupts = <0 185 0>; + clocks = <&clock 318>, <&clock 319>; + clock-names = "tmu_apbif", "tmu_triminfo_apbif"; + }; + + tmu_gpu: tmu@100a0000 { + compatible = "samsung,exynos5420-tmu-ext-triminfo"; + reg = <0x100a0000 0x100>, <0x10068000 0x4>; + interrupts = <0 215 0>; + clocks = <&clock 319>, <&clock 318>; + clock-names = "tmu_apbif", "tmu_triminfo_apbif"; + }; }; -- cgit v1.1 From 24b714f8d17127af0d33b242c2b5653686adf61b Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Sat, 21 Dec 2013 07:24:26 +0900 Subject: ARM: dts: Add CODEC MCLK for SMDK5250 There is a 16.934MHz fixed rate clock connected to MCLK1 on the CODEC, add this to the device tree bindings. Signed-off-by: Mark Brown Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5250-smdk5250.dts | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 3f80c23..f079c4c 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -77,6 +77,9 @@ gpio-controller; #gpio-cells = <2>; + clocks = <&codec_mclk>; + clock-names = "MCLK1"; + AVDD2-supply = <&vdd>; CPVDD-supply = <&vdd>; DBVDD-supply = <&dbvdd>; @@ -271,5 +274,11 @@ compatible = "samsung,clock-xxti"; clock-frequency = <24000000>; }; + + codec_mclk: codec-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16934000>; + }; }; }; -- cgit v1.1 From fae93f7cdde2ac987e4b23276b043d9456e821b0 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Sat, 21 Dec 2013 08:31:30 +0900 Subject: ARM: dts: Leave Exynos5250 SPI controller disabled by default Rather than requiring each board to explicitly disable the SPI controllers it is not using instead require boards to enable those that they are using. This is less work overall since normally at most one of the controllers is in use and avoids issues caused by inappropriate pinmuxing. Signed-off-by: Mark Brown Acked-by: Tomasz Figa Reviewed-by: Doug Anderson Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/cros5250-common.dtsi | 9 +-------- arch/arm/boot/dts/exynos5250-arndale.dts | 12 ------------ arch/arm/boot/dts/exynos5250-smdk5250.dts | 6 ++---- arch/arm/boot/dts/exynos5250.dtsi | 3 +++ 4 files changed, 6 insertions(+), 24 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/cros5250-common.dtsi b/arch/arm/boot/dts/cros5250-common.dtsi index 2dd70e9..ddaa61a 100644 --- a/arch/arm/boot/dts/cros5250-common.dtsi +++ b/arch/arm/boot/dts/cros5250-common.dtsi @@ -279,19 +279,12 @@ }; }; - spi_0: spi@12d20000 { - status = "disabled"; - }; - spi_1: spi@12d30000 { + status = "okay"; samsung,spi-src-clk = <0>; num-cs = <1>; }; - spi_2: spi@12d40000 { - status = "disabled"; - }; - hdmi { hpd-gpio = <&gpx3 7 0>; }; diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index 6e30c39..a1b88c9 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -428,18 +428,6 @@ status = "okay"; }; - spi_0: spi@12d20000 { - status = "disabled"; - }; - - spi_1: spi@12d30000 { - status = "disabled"; - }; - - spi_2: spi@12d40000 { - status = "disabled"; - }; - gpio_keys { compatible = "gpio-keys"; diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index f079c4c..66be827 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -184,6 +184,8 @@ }; spi_1: spi@12d30000 { + status = "okay"; + w25q80bw@0 { #address-cells = <1>; #size-cells = <1>; @@ -209,10 +211,6 @@ }; }; - spi_2: spi@12d40000 { - status = "disabled"; - }; - hdmi { hpd-gpio = <&gpx3 7 0>; }; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 108739a..14c4f63 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -351,6 +351,7 @@ spi_0: spi@12d20000 { compatible = "samsung,exynos4210-spi"; + status = "disabled"; reg = <0x12d20000 0x100>; interrupts = <0 66 0>; dmas = <&pdma0 5 @@ -366,6 +367,7 @@ spi_1: spi@12d30000 { compatible = "samsung,exynos4210-spi"; + status = "disabled"; reg = <0x12d30000 0x100>; interrupts = <0 67 0>; dmas = <&pdma1 5 @@ -381,6 +383,7 @@ spi_2: spi@12d40000 { compatible = "samsung,exynos4210-spi"; + status = "disabled"; reg = <0x12d40000 0x100>; interrupts = <0 68 0>; dmas = <&pdma0 7 -- cgit v1.1 From 6ad8ebffde8c06fd91f84968650864c29d70b43e Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Sat, 21 Dec 2013 08:33:23 +0900 Subject: ARM: dts: Disable I2C controllers by default on Exynos5250 Ensure that unused I2C controllers are not activated, causing problems due to inappropriate pinmuxing or similar, by marking the controllers as disabled by default and requiring boards to explicitly enable those that are in use. Signed-off-by: Mark Brown Acked-by: Tomasz Figa Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/cros5250-common.dtsi | 12 ++++++++---- arch/arm/boot/dts/exynos5250-arndale.dts | 32 ++++++++----------------------- arch/arm/boot/dts/exynos5250-smdk5250.dts | 25 +++++------------------- arch/arm/boot/dts/exynos5250.dtsi | 10 ++++++++++ 4 files changed, 31 insertions(+), 48 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/cros5250-common.dtsi b/arch/arm/boot/dts/cros5250-common.dtsi index ddaa61a..a826f0f 100644 --- a/arch/arm/boot/dts/cros5250-common.dtsi +++ b/arch/arm/boot/dts/cros5250-common.dtsi @@ -30,6 +30,7 @@ }; i2c@12C60000 { + status = "okay"; samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <378000>; @@ -173,6 +174,7 @@ }; i2c@12C70000 { + status = "okay"; samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <378000>; @@ -186,6 +188,7 @@ }; i2c@12C80000 { + status = "okay"; samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>; @@ -196,30 +199,31 @@ }; i2c@12C90000 { + status = "okay"; samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>; }; i2c@12CA0000 { + status = "okay"; samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>; }; i2c@12CB0000 { + status = "okay"; samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>; }; - i2c@12CC0000 { - status = "disabled"; - }; - i2c@12CD0000 { + status = "okay"; samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>; }; i2c@12CE0000 { + status = "okay"; samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <378000>; diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index a1b88c9..b42e658 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -34,6 +34,7 @@ samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <20000>; samsung,i2c-slave-addr = <0x66>; + status = "okay"; s5m8767_pmic@66 { compatible = "samsung,s5m8767-pmic"; @@ -321,11 +322,9 @@ }; }; - i2c@12C70000 { - status = "disabled"; - }; - i2c@12C80000 { + status = "okay"; + samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>; samsung,i2c-slave-addr = <0x50>; @@ -337,7 +336,10 @@ }; i2c@12C90000 { + status = "okay"; + wm1811a@1a { + compatible = "wlf,wm1811"; reg = <0x1a>; @@ -355,23 +357,9 @@ }; }; - i2c@12CA0000 { - status = "disabled"; - }; - - i2c@12CB0000 { - status = "disabled"; - }; - - i2c@12CC0000 { - status = "disabled"; - }; - - i2c@12CD0000 { - status = "disabled"; - }; - i2c@12CE0000 { + status = "okay"; + samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>; samsung,i2c-slave-addr = <0x38>; @@ -382,10 +370,6 @@ }; }; - i2c@121D0000 { - status = "disabled"; - }; - mmc_0: mmc@12200000 { status = "okay"; num-slots = <1>; diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 66be827..3e69837 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -30,6 +30,7 @@ i2c@12C60000 { samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <20000>; + status = "okay"; eeprom@50 { compatible = "samsung,s524ad0xd1"; @@ -64,6 +65,7 @@ i2c@12C70000 { samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <20000>; + status = "okay"; eeprom@51 { compatible = "samsung,s524ad0xd1"; @@ -92,6 +94,7 @@ samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <40000>; samsung,i2c-slave-addr = <0x38>; + status = "okay"; sata-phy { compatible = "samsung,sata-phy"; @@ -106,6 +109,7 @@ i2c@12C80000 { samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>; + status = "okay"; hdmiddc@50 { compatible = "samsung,exynos4210-hdmiddc"; @@ -113,29 +117,10 @@ }; }; - i2c@12C90000 { - status = "disabled"; - }; - - i2c@12CA0000 { - status = "disabled"; - }; - - i2c@12CB0000 { - status = "disabled"; - }; - - i2c@12CC0000 { - status = "disabled"; - }; - - i2c@12CD0000 { - status = "disabled"; - }; - i2c@12CE0000 { samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>; + status = "okay"; hdmiphy@38 { compatible = "samsung,exynos4212-hdmiphy"; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 14c4f63..c341e55 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -244,6 +244,7 @@ clock-names = "i2c"; pinctrl-names = "default"; pinctrl-0 = <&i2c0_bus>; + status = "disabled"; }; i2c_1: i2c@12C70000 { @@ -256,6 +257,7 @@ clock-names = "i2c"; pinctrl-names = "default"; pinctrl-0 = <&i2c1_bus>; + status = "disabled"; }; i2c_2: i2c@12C80000 { @@ -268,6 +270,7 @@ clock-names = "i2c"; pinctrl-names = "default"; pinctrl-0 = <&i2c2_bus>; + status = "disabled"; }; i2c_3: i2c@12C90000 { @@ -280,6 +283,7 @@ clock-names = "i2c"; pinctrl-names = "default"; pinctrl-0 = <&i2c3_bus>; + status = "disabled"; }; i2c_4: i2c@12CA0000 { @@ -292,6 +296,7 @@ clock-names = "i2c"; pinctrl-names = "default"; pinctrl-0 = <&i2c4_bus>; + status = "disabled"; }; i2c_5: i2c@12CB0000 { @@ -304,6 +309,7 @@ clock-names = "i2c"; pinctrl-names = "default"; pinctrl-0 = <&i2c5_bus>; + status = "disabled"; }; i2c_6: i2c@12CC0000 { @@ -316,6 +322,7 @@ clock-names = "i2c"; pinctrl-names = "default"; pinctrl-0 = <&i2c6_bus>; + status = "disabled"; }; i2c_7: i2c@12CD0000 { @@ -328,6 +335,7 @@ clock-names = "i2c"; pinctrl-names = "default"; pinctrl-0 = <&i2c7_bus>; + status = "disabled"; }; i2c_8: i2c@12CE0000 { @@ -338,6 +346,7 @@ #size-cells = <0>; clocks = <&clock 302>; clock-names = "i2c"; + status = "disabled"; }; i2c@121D0000 { @@ -347,6 +356,7 @@ #size-cells = <0>; clocks = <&clock 288>; clock-names = "i2c"; + status = "disabled"; }; spi_0: spi@12d20000 { -- cgit v1.1 From a22d060e3299ce672258d00070fa0ed398c035c5 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Sat, 21 Dec 2013 10:09:25 +0900 Subject: ARM: dts: Rename Exynos5250 ChromeOS common file to have exynos prefix Make it easier to notice the common file for ChromeOS devices based on the Exynos5250 by giving it the exynos5250 prefix that the boards have. Signed-off-by: Mark Brown Acked-by: Tomasz Figa Reviewed-by: Doug Anderson Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/cros5250-common.dtsi | 306 -------------------------- arch/arm/boot/dts/exynos5250-cros-common.dtsi | 306 ++++++++++++++++++++++++++ arch/arm/boot/dts/exynos5250-snow.dts | 2 +- 3 files changed, 307 insertions(+), 307 deletions(-) delete mode 100644 arch/arm/boot/dts/cros5250-common.dtsi create mode 100644 arch/arm/boot/dts/exynos5250-cros-common.dtsi (limited to 'arch') diff --git a/arch/arm/boot/dts/cros5250-common.dtsi b/arch/arm/boot/dts/cros5250-common.dtsi deleted file mode 100644 index a826f0f..0000000 --- a/arch/arm/boot/dts/cros5250-common.dtsi +++ /dev/null @@ -1,306 +0,0 @@ -/* - * Common device tree include for all Exynos 5250 boards based off of Daisy. - * - * Copyright (c) 2012 Google, Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/ { - aliases { - }; - - memory { - reg = <0x40000000 0x80000000>; - }; - - chosen { - }; - - pinctrl@11400000 { - /* - * Disabled pullups since external part has its own pullups and - * double-pulling gets us out of spec in some cases. - */ - i2c2_bus: i2c2-bus { - samsung,pin-pud = <0>; - }; - }; - - i2c@12C60000 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <378000>; - - max77686@09 { - compatible = "maxim,max77686"; - reg = <0x09>; - - voltage-regulators { - ldo1_reg: LDO1 { - regulator-name = "P1.0V_LDO_OUT1"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "P1.8V_LDO_OUT2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "P1.8V_LDO_OUT3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo7_reg: LDO7 { - regulator-name = "P1.1V_LDO_OUT7"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo8_reg: LDO8 { - regulator-name = "P1.0V_LDO_OUT8"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo10_reg: LDO10 { - regulator-name = "P1.8V_LDO_OUT10"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo12_reg: LDO12 { - regulator-name = "P3.0V_LDO_OUT12"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - ldo14_reg: LDO14 { - regulator-name = "P1.8V_LDO_OUT14"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo15_reg: LDO15 { - regulator-name = "P1.0V_LDO_OUT15"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo16_reg: LDO16 { - regulator-name = "P1.8V_LDO_OUT16"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - buck5_reg: BUCK5 { - regulator-name = "P1.8V_BUCK_OUT5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - buck6_reg: BUCK6 { - regulator-name = "P1.35V_BUCK_OUT6"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - buck7_reg: BUCK7 { - regulator-name = "P2.0V_BUCK_OUT7"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - buck8_reg: BUCK8 { - regulator-name = "P2.85V_BUCK_OUT8"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - }; - }; - }; - - i2c@12C70000 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <378000>; - - trackpad { - reg = <0x67>; - compatible = "cypress,cyapa"; - interrupts = <2 0>; - interrupt-parent = <&gpx1>; - wakeup-source; - }; - }; - - i2c@12C80000 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - - hdmiddc@50 { - compatible = "samsung,exynos4210-hdmiddc"; - reg = <0x50>; - }; - }; - - i2c@12C90000 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - }; - - i2c@12CA0000 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - }; - - i2c@12CB0000 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - }; - - i2c@12CD0000 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - }; - - i2c@12CE0000 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <378000>; - - hdmiphy@38 { - compatible = "samsung,exynos4212-hdmiphy"; - reg = <0x38>; - }; - }; - - mmc@12200000 { - num-slots = <1>; - supports-highspeed; - broken-cd; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>; - - slot@0 { - reg = <0>; - bus-width = <8>; - }; - }; - - mmc@12220000 { - num-slots = <1>; - supports-highspeed; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; - - slot@0 { - reg = <0>; - bus-width = <4>; - wp-gpios = <&gpc2 1 0>; - }; - }; - - mmc@12230000 { - num-slots = <1>; - supports-highspeed; - broken-cd; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - /* See board-specific dts files for pin setup */ - - slot@0 { - reg = <0>; - bus-width = <4>; - }; - }; - - spi_1: spi@12d30000 { - status = "okay"; - samsung,spi-src-clk = <0>; - num-cs = <1>; - }; - - hdmi { - hpd-gpio = <&gpx3 7 0>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power { - label = "Power"; - gpios = <&gpx1 3 1>; - linux,code = <116>; /* KEY_POWER */ - gpio-key,wakeup; - }; - }; -}; diff --git a/arch/arm/boot/dts/exynos5250-cros-common.dtsi b/arch/arm/boot/dts/exynos5250-cros-common.dtsi new file mode 100644 index 0000000..a826f0f --- /dev/null +++ b/arch/arm/boot/dts/exynos5250-cros-common.dtsi @@ -0,0 +1,306 @@ +/* + * Common device tree include for all Exynos 5250 boards based off of Daisy. + * + * Copyright (c) 2012 Google, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/ { + aliases { + }; + + memory { + reg = <0x40000000 0x80000000>; + }; + + chosen { + }; + + pinctrl@11400000 { + /* + * Disabled pullups since external part has its own pullups and + * double-pulling gets us out of spec in some cases. + */ + i2c2_bus: i2c2-bus { + samsung,pin-pud = <0>; + }; + }; + + i2c@12C60000 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <378000>; + + max77686@09 { + compatible = "maxim,max77686"; + reg = <0x09>; + + voltage-regulators { + ldo1_reg: LDO1 { + regulator-name = "P1.0V_LDO_OUT1"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "P1.8V_LDO_OUT2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "P1.8V_LDO_OUT3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo7_reg: LDO7 { + regulator-name = "P1.1V_LDO_OUT7"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + ldo8_reg: LDO8 { + regulator-name = "P1.0V_LDO_OUT8"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo10_reg: LDO10 { + regulator-name = "P1.8V_LDO_OUT10"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo12_reg: LDO12 { + regulator-name = "P3.0V_LDO_OUT12"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + ldo14_reg: LDO14 { + regulator-name = "P1.8V_LDO_OUT14"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo15_reg: LDO15 { + regulator-name = "P1.0V_LDO_OUT15"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo16_reg: LDO16 { + regulator-name = "P1.8V_LDO_OUT16"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + buck1_reg: BUCK1 { + regulator-name = "vdd_mif"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + buck2_reg: BUCK2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + buck3_reg: BUCK3 { + regulator-name = "vdd_int"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + buck4_reg: BUCK4 { + regulator-name = "vdd_g3d"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + buck5_reg: BUCK5 { + regulator-name = "P1.8V_BUCK_OUT5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + buck6_reg: BUCK6 { + regulator-name = "P1.35V_BUCK_OUT6"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + buck7_reg: BUCK7 { + regulator-name = "P2.0V_BUCK_OUT7"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + }; + + buck8_reg: BUCK8 { + regulator-name = "P2.85V_BUCK_OUT8"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + }; + }; + }; + + i2c@12C70000 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <378000>; + + trackpad { + reg = <0x67>; + compatible = "cypress,cyapa"; + interrupts = <2 0>; + interrupt-parent = <&gpx1>; + wakeup-source; + }; + }; + + i2c@12C80000 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; + + hdmiddc@50 { + compatible = "samsung,exynos4210-hdmiddc"; + reg = <0x50>; + }; + }; + + i2c@12C90000 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; + }; + + i2c@12CA0000 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; + }; + + i2c@12CB0000 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; + }; + + i2c@12CD0000 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; + }; + + i2c@12CE0000 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <378000>; + + hdmiphy@38 { + compatible = "samsung,exynos4212-hdmiphy"; + reg = <0x38>; + }; + }; + + mmc@12200000 { + num-slots = <1>; + supports-highspeed; + broken-cd; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>; + + slot@0 { + reg = <0>; + bus-width = <8>; + }; + }; + + mmc@12220000 { + num-slots = <1>; + supports-highspeed; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; + + slot@0 { + reg = <0>; + bus-width = <4>; + wp-gpios = <&gpc2 1 0>; + }; + }; + + mmc@12230000 { + num-slots = <1>; + supports-highspeed; + broken-cd; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + /* See board-specific dts files for pin setup */ + + slot@0 { + reg = <0>; + bus-width = <4>; + }; + }; + + spi_1: spi@12d30000 { + status = "okay"; + samsung,spi-src-clk = <0>; + num-cs = <1>; + }; + + hdmi { + hpd-gpio = <&gpx3 7 0>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + power { + label = "Power"; + gpios = <&gpx1 3 1>; + linux,code = <116>; /* KEY_POWER */ + gpio-key,wakeup; + }; + }; +}; diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts index 4c9a023..7e45eea 100644 --- a/arch/arm/boot/dts/exynos5250-snow.dts +++ b/arch/arm/boot/dts/exynos5250-snow.dts @@ -10,7 +10,7 @@ /dts-v1/; #include "exynos5250.dtsi" -#include "cros5250-common.dtsi" +#include "exynos5250-cros-common.dtsi" / { model = "Google Snow"; -- cgit v1.1 From 0ad82cd81b00d9a7c6d183ef955947b5bc5eef9e Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Tue, 17 Dec 2013 21:21:52 +0100 Subject: Phy: Add DT nodes on kirkwood and Dove for the SATA PHY Add nodes for the two SATA PHYs on kirkwood. Add node for the one SATA PHY on Dove. Add pHandles to the PHYs in the sata nodes. Signed-off-by: Andrew Lunn Acked-by: Kishon Vijay Abraham I Signed-off-by: Jason Cooper --- arch/arm/boot/dts/dove.dtsi | 11 +++++++++++ arch/arm/boot/dts/kirkwood-6281.dtsi | 2 ++ arch/arm/boot/dts/kirkwood-6282.dtsi | 2 ++ arch/arm/boot/dts/kirkwood.dtsi | 18 ++++++++++++++++++ 4 files changed, 33 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index 852db28..8de1031 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -336,10 +336,21 @@ reg = <0xa0000 0x2400>; interrupts = <62>; clocks = <&gate_clk 3>; + phys = <&sata_phy0>; + phy-names = "port0"; nr-ports = <1>; status = "disabled"; }; + sata_phy0: sata-phy@a2000 { + compatible = "marvell,mvebu-sata-phy"; + reg = <0xa2000 0x0334>; + clocks = <&gate_clk 3>; + clock-names = "sata"; + #phy-cells = <0>; + status = "ok"; + }; + audio0: audio-controller@b0000 { compatible = "marvell,dove-audio"; reg = <0xb0000 0x2210>; diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi index e4e1968..416d96e 100644 --- a/arch/arm/boot/dts/kirkwood-6281.dtsi +++ b/arch/arm/boot/dts/kirkwood-6281.dtsi @@ -89,6 +89,8 @@ interrupts = <21>; clocks = <&gate_clk 14>, <&gate_clk 15>; clock-names = "0", "1"; + phys = <&sata_phy0>, <&sata_phy1>; + phy-names = "port0", "port1"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi index f010c21..a4fec04 100644 --- a/arch/arm/boot/dts/kirkwood-6282.dtsi +++ b/arch/arm/boot/dts/kirkwood-6282.dtsi @@ -117,6 +117,8 @@ interrupts = <21>; clocks = <&gate_clk 14>, <&gate_clk 15>; clock-names = "0", "1"; + phys = <&sata_phy0>, <&sata_phy1>; + phy-names = "port0", "port1"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index 1da94c1..81e6c40 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -284,5 +284,23 @@ /* set phy-handle property in board file */ }; }; + + sata_phy0: sata-phy@82000 { + compatible = "marvell,mvebu-sata-phy"; + reg = <0x82000 0x0334>; + clocks = <&gate_clk 14>; + clock-names = "sata"; + #phy-cells = <0>; + status = "ok"; + }; + + sata_phy1: sata-phy@84000 { + compatible = "marvell,mvebu-sata-phy"; + reg = <0x84000 0x0334>; + clocks = <&gate_clk 15>; + clock-names = "sata"; + #phy-cells = <0>; + status = "ok"; + }; }; }; -- cgit v1.1 From d8e0a2b65a78f97901fb9a1da08a79f50d7fc25a Mon Sep 17 00:00:00 2001 From: Jason Cooper Date: Sun, 22 Dec 2013 17:16:36 +0000 Subject: ARM: kirkwood: 6282: sort DT nodes by address We recently sorted the nodes in dove, orion5x, kirkwood, and armada 370/xp. However, I missed this file. -6281 is fine. Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood-6282.dtsi | 35 +++++++++++++++++------------------ 1 file changed, 17 insertions(+), 18 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi index a4fec04..2902e0d 100644 --- a/arch/arm/boot/dts/kirkwood-6282.dtsi +++ b/arch/arm/boot/dts/kirkwood-6282.dtsi @@ -104,6 +104,12 @@ }; }; + thermal@10078 { + compatible = "marvell,kirkwood-thermal"; + reg = <0x10078 0x4>; + status = "okay"; + }; + rtc@10300 { compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; reg = <0x10300 0x20>; @@ -111,6 +117,17 @@ clocks = <&gate_clk 7>; }; + i2c@11100 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11100 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <32>; + clock-frequency = <100000>; + clocks = <&gate_clk 7>; + status = "disabled"; + }; + sata@80000 { compatible = "marvell,orion-sata"; reg = <0x80000 0x5000>; @@ -135,23 +152,5 @@ cap-mmc-highspeed; status = "disabled"; }; - - thermal@10078 { - compatible = "marvell,kirkwood-thermal"; - reg = <0x10078 0x4>; - status = "okay"; - }; - - i2c@11100 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11100 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <32>; - clock-frequency = <100000>; - clocks = <&gate_clk 7>; - status = "disabled"; - }; - }; }; -- cgit v1.1 From 448e7edefa929104c77fe1a1cce4aa8ffc77d291 Mon Sep 17 00:00:00 2001 From: Jonas Jensen Date: Wed, 18 Dec 2013 13:58:46 +0100 Subject: ARM: moxart: add MOXA ART SoC device tree files Add a generic (dtsi) include file for MOXA ART SoCs. Also add a file for UC-7112-LX. Signed-off-by: Jonas Jensen Acked-by: Arnd Bergmann Signed-off-by: Olof Johansson --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/moxart-uc7112lx.dts | 109 ++++++++++++++++++++++++ arch/arm/boot/dts/moxart.dtsi | 154 ++++++++++++++++++++++++++++++++++ 3 files changed, 264 insertions(+) create mode 100644 arch/arm/boot/dts/moxart-uc7112lx.dts create mode 100644 arch/arm/boot/dts/moxart.dtsi (limited to 'arch') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 38e04b6..25d708c 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -108,6 +108,7 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \ kirkwood-ts219-6281.dtb \ kirkwood-ts219-6282.dtb dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb +dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb dtb-$(CONFIG_ARCH_MSM) += qcom-msm8660-surf.dtb \ qcom-msm8960-cdp.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \ diff --git a/arch/arm/boot/dts/moxart-uc7112lx.dts b/arch/arm/boot/dts/moxart-uc7112lx.dts new file mode 100644 index 0000000..90749d5 --- /dev/null +++ b/arch/arm/boot/dts/moxart-uc7112lx.dts @@ -0,0 +1,109 @@ +/* moxart-uc7112lx.dts - Device Tree file for MOXA UC-7112-LX + * + * Copyright (C) 2013 Jonas Jensen + * + * Licensed under GPLv2 or later. + */ + +/dts-v1/; +/include/ "moxart.dtsi" + +/ { + model = "MOXA UC-7112-LX"; + compatible = "moxa,moxart-uc-7112-lx", "moxa,moxart"; + + memory { + device_type = "memory"; + reg = <0x0 0x2000000>; + }; + + flash@80000000,0 { + compatible = "numonyx,js28f128", "cfi-flash"; + reg = <0x80000000 0x1000000>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "bootloader"; + reg = <0x0 0x40000>; + }; + partition@40000 { + label = "linux kernel"; + reg = <0x40000 0x1C0000>; + }; + partition@200000 { + label = "root filesystem"; + reg = <0x200000 0x800000>; + }; + partition@a00000 { + label = "user filesystem"; + reg = <0xa00000 0x600000>; + }; + }; + + leds { + compatible = "gpio-leds"; + user-led { + label = "ready-led"; + gpios = <&gpio 27 0x1>; + default-state = "on"; + linux,default-trigger = "default-on"; + }; + }; + + gpio_keys_polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <500>; + button@25 { + label = "GPIO Reset"; + linux,code = <116>; + gpios = <&gpio 25 1>; + }; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/mmcblk0p1 rw rootwait"; + }; +}; + +&clk_pll { + clocks = <&ref12>; +}; + +&sdhci { + status = "okay"; +}; + +&mdio0 { + status = "okay"; + + ethphy0: ethernet-phy@1 { + device_type = "ethernet-phy"; + compatible = "moxa,moxart-rtl8201cp", "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&mdio1 { + status = "okay"; + + ethphy1: ethernet-phy@1 { + device_type = "ethernet-phy"; + compatible = "moxa,moxart-rtl8201cp", "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&mac0 { + status = "okay"; +}; + +&mac1 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/moxart.dtsi b/arch/arm/boot/dts/moxart.dtsi new file mode 100644 index 0000000..da1d8ef --- /dev/null +++ b/arch/arm/boot/dts/moxart.dtsi @@ -0,0 +1,154 @@ +/* moxart.dtsi - Device Tree Include file for MOXA ART family SoC + * + * Copyright (C) 2013 Jonas Jensen + * + * Licensed under GPLv2 or later. + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "moxa,moxart"; + model = "MOXART"; + interrupt-parent = <&intc>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "faraday,fa526"; + reg = <0>; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + ref12: ref12M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x90000000 0x10000000>; + ranges; + + intc: interrupt-controller@98800000 { + compatible = "moxa,moxart-ic"; + reg = <0x98800000 0x38>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-mask = <0x00080000>; + }; + + clk_pll: clk_pll@98100000 { + compatible = "moxa,moxart-pll-clock"; + #clock-cells = <0>; + reg = <0x98100000 0x34>; + }; + + clk_apb: clk_apb@98100000 { + compatible = "moxa,moxart-apb-clock"; + #clock-cells = <0>; + reg = <0x98100000 0x34>; + clocks = <&clk_pll>; + }; + + timer: timer@98400000 { + compatible = "moxa,moxart-timer"; + reg = <0x98400000 0x42>; + interrupts = <19 1>; + clocks = <&clk_apb>; + }; + + gpio: gpio@98700000 { + gpio-controller; + #gpio-cells = <2>; + compatible = "moxa,moxart-gpio"; + reg = <0x98700000 0xC>; + }; + + rtc: rtc { + compatible = "moxa,moxart-rtc"; + gpio-rtc-sclk = <&gpio 5 0>; + gpio-rtc-data = <&gpio 6 0>; + gpio-rtc-reset = <&gpio 7 0>; + }; + + dma: dma@90500000 { + compatible = "moxa,moxart-dma"; + reg = <0x90500080 0x40>; + interrupts = <24 0>; + #dma-cells = <1>; + }; + + watchdog: watchdog@98500000 { + compatible = "moxa,moxart-watchdog"; + reg = <0x98500000 0x10>; + clocks = <&clk_apb>; + }; + + sdhci: sdhci@98e00000 { + compatible = "moxa,moxart-sdhci"; + reg = <0x98e00000 0x5C>; + interrupts = <5 0>; + clocks = <&clk_apb>; + dmas = <&dma 5>, + <&dma 5>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + mdio0: mdio@90900090 { + compatible = "moxa,moxart-mdio"; + reg = <0x90900090 0x8>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + mdio1: mdio@92000090 { + compatible = "moxa,moxart-mdio"; + reg = <0x92000090 0x8>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + mac0: mac@90900000 { + compatible = "moxa,moxart-mac"; + reg = <0x90900000 0x90>; + interrupts = <25 0>; + phy-handle = <ðphy0>; + phy-mode = "mii"; + status = "disabled"; + }; + + mac1: mac@92000000 { + compatible = "moxa,moxart-mac"; + reg = <0x92000000 0x90>; + interrupts = <27 0>; + phy-handle = <ðphy1>; + phy-mode = "mii"; + status = "disabled"; + }; + + uart0: uart@98200000 { + compatible = "ns16550a"; + reg = <0x98200000 0x20>; + interrupts = <31 8>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <14745600>; + status = "disabled"; + }; + }; +}; -- cgit v1.1 From 82f7c2065a363cd3c0c84d3c9b59ee47897c5ebb Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 19 Dec 2013 16:28:43 +0100 Subject: ARM: shmobile: Remove Koelsch reference DTS Now that the DTS file r8a7790-koelsch.dts can be used with board-koelsch.c and board-koelsch-reference.c, proceed with removing r8a7790-koelsch-reference.dts. Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/Makefile | 1 - 1 file changed, 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 909d910..5839077 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -225,7 +225,6 @@ dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += emev2-kzm9d.dtb \ r8a7779-marzen.dtb \ r8a7779-marzen-reference.dtb \ r8a7791-koelsch.dtb \ - r8a7791-koelsch-reference.dtb \ r8a7790-lager.dtb \ r8a7790-lager-reference.dtb \ sh73a0-kzm9g.dtb \ -- cgit v1.1 From 9d90951a39205206a46609055717af9bfb436e4d Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 19 Dec 2013 16:51:01 +0100 Subject: ARM: shmobile: r8a7790: Add MSIOF clocks in device tree Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 71ec31c..9c9a992 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -524,6 +524,14 @@ }; /* Gate clocks */ + mstp0_clks: mstp0_clks@e6150130 { + compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; + clocks = <&mp_clk>; + #clock-cells = <1>; + renesas,clock-indices = ; + clock-output-names = "msiof0"; + }; mstp1_clks: mstp1_clks@e6150134 { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; @@ -544,15 +552,16 @@ compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, - <&mp_clk>; + <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>; #clock-cells = <1>; renesas,clock-indices = < R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0 - R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1 R8A7790_CLK_SCIFB2 + R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1 + R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2 >; clock-output-names = - "scifa2", "scifa1", "scifa0", "scifb0", "scifb1", - "scifb2"; + "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", + "scifb1", "msiof1", "msiof3", "scifb2"; }; mstp3_clks: mstp3_clks@e615013c { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; -- cgit v1.1 From cded80f869aef94853e056ab9c21e305b0c26138 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 19 Dec 2013 16:51:02 +0100 Subject: ARM: shmobile: r8a7791: Add MSIOF clocks in device tree Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 0a82192..6a29341 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -394,6 +394,14 @@ }; /* Gate clocks */ + mstp0_clks: mstp0_clks@e6150130 { + compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; + clocks = <&mp_clk>; + #clock-cells = <1>; + renesas,clock-indices = ; + clock-output-names = "msiof0"; + }; mstp1_clks: mstp1_clks@e6150134 { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; @@ -413,15 +421,16 @@ compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, - <&mp_clk>; + <&mp_clk>, <&mp_clk>, <&mp_clk>; #clock-cells = <1>; renesas,clock-indices = < R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0 - R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1 R8A7791_CLK_SCIFB2 + R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1 + R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2 >; clock-output-names = - "scifa2", "scifa1", "scifa0", "scifb0", "scifb1", - "scifb2"; + "scifa2", "scifa1", "scifa0", "misof2", "scifb0", + "scifb1", "msiof1", "scifb2"; }; mstp3_clks: mstp3_clks@e615013c { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; -- cgit v1.1 From 91b56ca10a3cf4999bae5f8b8e7e2723bf4b1363 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 19 Dec 2013 16:51:03 +0100 Subject: ARM: shmobile: r8a7790: Add QSPI module clock in device tree Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 9c9a992..a179125 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -615,13 +615,16 @@ mstp9_clks: mstp9_clks@e6150994 { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; - clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>; + clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, + <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>; #clock-cells = <1>; renesas,clock-indices = < - R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_I2C3 - R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0 + R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD + R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 + R8A7790_CLK_I2C0 >; - clock-output-names = "rcan1", "rcan0", "i2c3", "i2c2", "i2c1", "i2c0"; + clock-output-names = + "rcan1", "rcan0", "qspi_mod", "i2c3", "i2c2", "i2c1", "i2c0"; }; }; }; -- cgit v1.1 From ec71f55216db1b3da68e284840cb3ac3d5ed4965 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 19 Dec 2013 16:51:04 +0100 Subject: ARM: shmobile: r8a7791: Add QSPI module clock in device tree Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 6a29341..19c6550 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -482,17 +482,18 @@ mstp9_clks: mstp9_clks@e6150994 { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; - clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, - <&p_clk>, <&p_clk>, <&p_clk>; + clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, + <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, + <&p_clk>; #clock-cells = <1>; renesas,clock-indices = < - R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_I2C4 - R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2 - R8A7791_CLK_I2C1 R8A7791_CLK_I2C0 + R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD + R8A7791_CLK_I2C4 R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 + R8A7791_CLK_I2C2 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0 >; clock-output-names = - "rcan1", "rcan0", "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", - "i2c0"; + "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c4", "i2c3", + "i2c2", "i2c1", "i2c0"; }; mstp11_clks: mstp11_clks@e615099c { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; -- cgit v1.1 From 6dea2c1ebc6fc43852fd6125d75a75da223ff707 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 19 Dec 2013 16:51:05 +0100 Subject: ARM: shmobile: r8a7790: Add SSI clocks in device tree Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index a179125..c5417da 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -626,5 +626,25 @@ clock-output-names = "rcan1", "rcan0", "qspi_mod", "i2c3", "i2c2", "i2c1", "i2c0"; }; + mstp10_clks: mstp10_clks@e6150998 { + compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; + clocks = <&p_clk>, <&mstp10_clks R8A7790_CLK_SSI>, + <&mstp10_clks R8A7790_CLK_SSI>, <&mstp10_clks R8A7790_CLK_SSI>, + <&mstp10_clks R8A7790_CLK_SSI>, <&mstp10_clks R8A7790_CLK_SSI>, + <&mstp10_clks R8A7790_CLK_SSI>, <&mstp10_clks R8A7790_CLK_SSI>, + <&mstp10_clks R8A7790_CLK_SSI>, <&mstp10_clks R8A7790_CLK_SSI>, + <&mstp10_clks R8A7790_CLK_SSI>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7790_CLK_SSI R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 + R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5 + R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 + R8A7790_CLK_SSI1 R8A7790_CLK_SSI0 + >; + clock-output-names = + "ssi", "ssi9", "ssi8", "ssi7", "ssi6", "ssi5", + "ssi4", "ssi3", "ssi2", "ssi1", "ssi0"; + }; }; }; -- cgit v1.1 From b652896b02df3dfde3a68957cce01f2aa4585842 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 19 Dec 2013 16:51:06 +0100 Subject: ARM: shmobile: r8a7791: Add SSI clocks in device tree Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 19c6550..e92c1f7 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -495,6 +495,26 @@ "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0"; }; + mstp10_clks: mstp10_clks@e6150998 { + compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; + clocks = <&p_clk>, <&mstp10_clks R8A7791_CLK_SSI>, + <&mstp10_clks R8A7791_CLK_SSI>, <&mstp10_clks R8A7791_CLK_SSI>, + <&mstp10_clks R8A7791_CLK_SSI>, <&mstp10_clks R8A7791_CLK_SSI>, + <&mstp10_clks R8A7791_CLK_SSI>, <&mstp10_clks R8A7791_CLK_SSI>, + <&mstp10_clks R8A7791_CLK_SSI>, <&mstp10_clks R8A7791_CLK_SSI>, + <&mstp10_clks R8A7791_CLK_SSI>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7791_CLK_SSI R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 + R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5 + R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 + R8A7791_CLK_SSI1 R8A7791_CLK_SSI0 + >; + clock-output-names = + "ssi", "ssi9", "ssi8", "ssi7", "ssi6", "ssi5", + "ssi4", "ssi3", "ssi2", "ssi1", "ssi0"; + }; mstp11_clks: mstp11_clks@e615099c { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; -- cgit v1.1 From 72c3e2295c1955b9d188dbaf910bc67a4dc2e3e5 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 23 Dec 2013 09:48:10 +0100 Subject: ARM: mvebu: fix register length for Armada XP PMSU The per-CPU PMSU registers documented in the datasheet start at 0x22100 and the last register for CPU3 is at 0x22428. However, the DT informations use <0x22100 0x430>, which makes the region end at 0x22530 and not 0x22430. Moreover, looking at the datasheet, we can see that the registers for CPU0 start at 0x22100, for CPU1 at 0x22200, for CPU2 at 0x22300 and for CPU3 at 0x22400. It seems clear that 0x100 bytes of registers have been used per CPU. Therefore, this commit reduces the length of the PMSU per-CPU register area from the incorrect 0x430 bytes to a more logical 0x400 bytes. Signed-off-by: Thomas Petazzoni Acked-by: Gregory CLEMENT Acked-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-xp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index 4919fb8..b8b84a2 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi @@ -113,7 +113,7 @@ armada-370-xp-pmsu@22000 { compatible = "marvell,armada-370-xp-pmsu"; - reg = <0x22100 0x430>, <0x20800 0x20>; + reg = <0x22100 0x400>, <0x20800 0x20>; }; eth2: ethernet@30000 { -- cgit v1.1 From e38cd3ae6e6f2bd5d376bc146d9f129402b82158 Mon Sep 17 00:00:00 2001 From: Maxime Hadjinlian Date: Tue, 24 Dec 2013 13:53:18 +0100 Subject: ARM: Kirkwood: Add 6192 DTSI file This file is mainly a copy of kirkwood-6281.dtsi. The pinctrl seems to be the same. These platforms differs only with their CPU, memory capabilities and the number of GPIO available (36 on 6192, 50 on 6281). Signed-off-by: Maxime Hadjinlian Acked-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood-6192.dtsi | 107 +++++++++++++++++++++++++++++++++++ 1 file changed, 107 insertions(+) create mode 100644 arch/arm/boot/dts/kirkwood-6192.dtsi (limited to 'arch') diff --git a/arch/arm/boot/dts/kirkwood-6192.dtsi b/arch/arm/boot/dts/kirkwood-6192.dtsi new file mode 100644 index 0000000..3916937 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-6192.dtsi @@ -0,0 +1,107 @@ +/ { + mbus { + pcie-controller { + compatible = "marvell,kirkwood-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x00 0xff>; + + ranges = + <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 + 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ + 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; + + pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &intc 9>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gate_clk 2>; + status = "disabled"; + }; + }; + }; + + ocp@f1000000 { + pinctrl: pinctrl@10000 { + compatible = "marvell,88f6192-pinctrl"; + reg = <0x10000 0x20>; + + pmx_nand: pmx-nand { + marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", + "mpp4", "mpp5", "mpp18", + "mpp19"; + marvell,function = "nand"; + }; + pmx_sata0: pmx-sata0 { + marvell,pins = "mpp5", "mpp21", "mpp23"; + marvell,function = "sata0"; + }; + pmx_sata1: pmx-sata1 { + marvell,pins = "mpp4", "mpp20", "mpp22"; + marvell,function = "sata1"; + }; + pmx_spi: pmx-spi { + marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3"; + marvell,function = "spi"; + }; + pmx_twsi0: pmx-twsi0 { + marvell,pins = "mpp8", "mpp9"; + marvell,function = "twsi0"; + }; + pmx_uart0: pmx-uart0 { + marvell,pins = "mpp10", "mpp11"; + marvell,function = "uart0"; + }; + pmx_uart1: pmx-uart1 { + marvell,pins = "mpp13", "mpp14"; + marvell,function = "uart1"; + }; + pmx_sdio: pmx-sdio { + marvell,pins = "mpp12", "mpp13", "mpp14", + "mpp15", "mpp16", "mpp17"; + marvell,function = "sdio"; + }; + }; + + rtc@10300 { + compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; + reg = <0x10300 0x20>; + interrupts = <53>; + clocks = <&gate_clk 7>; + }; + + sata@80000 { + compatible = "marvell,orion-sata"; + reg = <0x80000 0x5000>; + interrupts = <21>; + clocks = <&gate_clk 14>, <&gate_clk 15>; + clock-names = "0", "1"; + status = "disabled"; + }; + + mvsdio@90000 { + compatible = "marvell,orion-sdio"; + reg = <0x90000 0x200>; + interrupts = <28>; + clocks = <&gate_clk 4>; + bus-width = <4>; + cap-sdio-irq; + cap-sd-highspeed; + cap-mmc-highspeed; + status = "disabled"; + }; + }; +}; -- cgit v1.1 From 2cc64b5655da65bbb6a760a722b5ab1f53f92cf7 Mon Sep 17 00:00:00 2001 From: Maxime Hadjinlian Date: Tue, 24 Dec 2013 13:53:19 +0100 Subject: ARM: Kirkwood: DT board setup for LaPlug This patch adds DT board setup for the LaCie NAS LaPlug. Chipset list: - CPU MARVELL 88FR131 800Mhz - SDRAM memory: 128MB DDR2-800 400Mhz - 1 Ethernet Gigabit port (PHY MARVELL 88E1318) - 1 Mini PCI-Express port - 1 NAND 512 MB - 1 push button - 2 LEDs (red and blue) - 4 USB Ports Signed-off-by: Maxime Hadjinlian Acked-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/kirkwood-laplug.dts | 175 ++++++++++++++++++++++++++++++++++ 2 files changed, 176 insertions(+) create mode 100644 arch/arm/boot/dts/kirkwood-laplug.dts (limited to 'arch') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index adcc606..0906780 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -85,6 +85,7 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \ kirkwood-iomega_ix2_200.dtb \ kirkwood-is2.dtb \ kirkwood-km_kirkwood.dtb \ + kirkwood-laplug.dtb \ kirkwood-lschlv2.dtb \ kirkwood-lsxhl.dtb \ kirkwood-mplcec4.dtb \ diff --git a/arch/arm/boot/dts/kirkwood-laplug.dts b/arch/arm/boot/dts/kirkwood-laplug.dts new file mode 100644 index 0000000..c9e82ef --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-laplug.dts @@ -0,0 +1,175 @@ +/* + * Copyright (C) 2013 Maxime Hadjinlian + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include +#include +#include "kirkwood.dtsi" +#include "kirkwood-6192.dtsi" + +/ { + model = "LaCie LaPlug"; + compatible = "lacie,laplug", "marvell,kirkwood-88f6192", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; /* 128 MB */ + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + }; + + mbus { + pcie-controller { + status = "okay"; + pcie@1,0 { + status = "okay"; + }; + }; + }; + + ocp@f1000000 { + serial@12000 { + pinctrl-0 = <&pmx_uart0>; + pinctrl-names = "default"; + status = "okay"; + }; + + i2c@11000 { + pinctrl-0 = <&pmx_twsi0>; + pinctrl-names = "default"; + status = "okay"; + + eeprom@50 { + compatible = "at,24c04"; + pagesize = <16>; + reg = <0x50>; + }; + }; + + pinctrl: pinctrl@10000 { + pmx_usb_power_enable: pmx-usb-power-enable { + marvell,pins = "mpp14"; + marvell,function = "gpio"; + }; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + button@1{ + label = "Power push button"; + linux,code = ; + gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + red-fail { + label = "laplug_v2:red:power"; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + }; + blue-power { + label = "laplug_v2:blue:power"; + gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + }; + + gpio_poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_usb_power_enable>; + pinctrl-names = "default"; + + usb_power_back1: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "USB Power Back 1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>; + }; + + usb_power_back2: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "USB Power Back 2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 28 GPIO_ACTIVE_HIGH>; + }; + + usb_power_front: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "USB Power Front"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&nand { + /* Total size : 512MB */ + status = "okay"; + pinctrl-0 = <&pmx_nand>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x100000>; /* 1MB */ + read-only; + }; + + partition@100000 { + label = "uImage"; + reg = <0x100000 0x1000000>; /* 16MB */ + }; + + partition@1100000 { + label = "rootfs"; + reg = <0x1100000 0x1EF00000>; /* 495MB */ + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + device_type = "ethernet-phy"; + reg = <0>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; -- cgit v1.1 From 4d0810257a7f1d040526a6dc5bde5a4737994a7e Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Thu, 26 Dec 2013 14:15:47 +0900 Subject: Revert "ARM: shmobile: r8a7790: Add SSI clocks in device tree" This reverts commit 6dea2c1ebc6fc43852fd6125d75a75da223ff707. Unfortunately this commit prevents multiplatform from booting to the point where a serial console is available. Revert it while a solution is sought. Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 20 -------------------- 1 file changed, 20 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index c5417da..a179125 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -626,25 +626,5 @@ clock-output-names = "rcan1", "rcan0", "qspi_mod", "i2c3", "i2c2", "i2c1", "i2c0"; }; - mstp10_clks: mstp10_clks@e6150998 { - compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; - clocks = <&p_clk>, <&mstp10_clks R8A7790_CLK_SSI>, - <&mstp10_clks R8A7790_CLK_SSI>, <&mstp10_clks R8A7790_CLK_SSI>, - <&mstp10_clks R8A7790_CLK_SSI>, <&mstp10_clks R8A7790_CLK_SSI>, - <&mstp10_clks R8A7790_CLK_SSI>, <&mstp10_clks R8A7790_CLK_SSI>, - <&mstp10_clks R8A7790_CLK_SSI>, <&mstp10_clks R8A7790_CLK_SSI>, - <&mstp10_clks R8A7790_CLK_SSI>; - #clock-cells = <1>; - renesas,clock-indices = < - R8A7790_CLK_SSI R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 - R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5 - R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 - R8A7790_CLK_SSI1 R8A7790_CLK_SSI0 - >; - clock-output-names = - "ssi", "ssi9", "ssi8", "ssi7", "ssi6", "ssi5", - "ssi4", "ssi3", "ssi2", "ssi1", "ssi0"; - }; }; }; -- cgit v1.1 From 3effae8c26f451a9d572255c08dfbe342dd1dc98 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Thu, 26 Dec 2013 14:16:54 +0900 Subject: Revert "ARM: shmobile: r8a7791: Add SSI clocks in device tree" This reverts commit b652896b02df3dfde3a68957cce01f2aa4585842. Unfortunately this commit prevents multiplatform from booting to the point where a serial console is available. Revert it while a solution is sought. Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 20 -------------------- 1 file changed, 20 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index e92c1f7..19c6550 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -495,26 +495,6 @@ "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0"; }; - mstp10_clks: mstp10_clks@e6150998 { - compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; - clocks = <&p_clk>, <&mstp10_clks R8A7791_CLK_SSI>, - <&mstp10_clks R8A7791_CLK_SSI>, <&mstp10_clks R8A7791_CLK_SSI>, - <&mstp10_clks R8A7791_CLK_SSI>, <&mstp10_clks R8A7791_CLK_SSI>, - <&mstp10_clks R8A7791_CLK_SSI>, <&mstp10_clks R8A7791_CLK_SSI>, - <&mstp10_clks R8A7791_CLK_SSI>, <&mstp10_clks R8A7791_CLK_SSI>, - <&mstp10_clks R8A7791_CLK_SSI>; - #clock-cells = <1>; - renesas,clock-indices = < - R8A7791_CLK_SSI R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 - R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5 - R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 - R8A7791_CLK_SSI1 R8A7791_CLK_SSI0 - >; - clock-output-names = - "ssi", "ssi9", "ssi8", "ssi7", "ssi6", "ssi5", - "ssi4", "ssi3", "ssi2", "ssi1", "ssi0"; - }; mstp11_clks: mstp11_clks@e615099c { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; -- cgit v1.1 From ec5589f7a33956ea3671d198ff170dc51ff2145d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= Date: Mon, 23 Dec 2013 00:32:35 -0300 Subject: ARM: sunxi: add PLL4 support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit adds the PLL4 definition to the sun4i, sun5i and sun7i device trees. PLL4 is compatible with PLL1. Signed-off-by: Emilio López Acked-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10.dtsi | 7 +++++++ arch/arm/boot/dts/sun5i-a10s.dtsi | 7 +++++++ arch/arm/boot/dts/sun5i-a13.dtsi | 7 +++++++ arch/arm/boot/dts/sun7i-a20.dtsi | 7 +++++++ 4 files changed, 28 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 319cc6b..a6c1cae 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -66,6 +66,13 @@ clocks = <&osc24M>; }; + pll4: pll4@01c20018 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-pll1-clk"; + reg = <0x01c20018 0x4>; + clocks = <&osc24M>; + }; + /* dummy is 200M */ cpu: cpu@01c20054 { #clock-cells = <0>; diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index 5247674..c3f4eed 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@ -63,6 +63,13 @@ clocks = <&osc24M>; }; + pll4: pll4@01c20018 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-pll1-clk"; + reg = <0x01c20018 0x4>; + clocks = <&osc24M>; + }; + /* dummy is 200M */ cpu: cpu@01c20054 { #clock-cells = <0>; diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi index ce8ef2a..8c4a9c3 100644 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi @@ -67,6 +67,13 @@ clocks = <&osc24M>; }; + pll4: pll4@01c20018 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-pll1-clk"; + reg = <0x01c20018 0x4>; + clocks = <&osc24M>; + }; + /* dummy is 200M */ cpu: cpu@01c20054 { #clock-cells = <0>; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index e46cfed..e4a5d37 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -62,6 +62,13 @@ clocks = <&osc24M>; }; + pll4: pll4@01c20018 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-pll1-clk"; + reg = <0x01c20018 0x4>; + clocks = <&osc24M>; + }; + /* * This is a dummy clock, to be used as placeholder on * other mux clocks when a specific parent clock is not -- cgit v1.1 From c3e5e66b65a57df8025cbf59801d9c357cf807ea Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= Date: Mon, 23 Dec 2013 00:32:38 -0300 Subject: ARM: sunxi: add PLL5 and PLL6 support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit adds PLL5 and PLL6 nodes to the sun4i, sun5i and sun7i device trees. Signed-off-by: Emilio López Acked-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10.dtsi | 19 +++++++++++++++++-- arch/arm/boot/dts/sun5i-a10s.dtsi | 19 +++++++++++++++++-- arch/arm/boot/dts/sun5i-a13.dtsi | 19 +++++++++++++++++-- arch/arm/boot/dts/sun7i-a20.dtsi | 28 ++++++++++++++++------------ 4 files changed, 67 insertions(+), 18 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index a6c1cae..5e2fc45 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -73,6 +73,22 @@ clocks = <&osc24M>; }; + pll5: pll5@01c20020 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-pll5-clk"; + reg = <0x01c20020 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll5_ddr", "pll5_other"; + }; + + pll6: pll6@01c20028 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-pll6-clk"; + reg = <0x01c20028 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll6_sata", "pll6_other", "pll6"; + }; + /* dummy is 200M */ cpu: cpu@01c20054 { #clock-cells = <0>; @@ -138,12 +154,11 @@ "apb0_ir1", "apb0_keypad"; }; - /* dummy is pll62 */ apb1_mux: apb1_mux@01c20058 { #clock-cells = <0>; compatible = "allwinner,sun4i-apb1-mux-clk"; reg = <0x01c20058 0x4>; - clocks = <&osc24M>, <&dummy>, <&osc32k>; + clocks = <&osc24M>, <&pll6 1>, <&osc32k>; }; apb1: apb1@01c20058 { diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index c3f4eed..b29412a 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@ -70,6 +70,22 @@ clocks = <&osc24M>; }; + pll5: pll5@01c20020 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-pll5-clk"; + reg = <0x01c20020 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll5_ddr", "pll5_other"; + }; + + pll6: pll6@01c20028 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-pll6-clk"; + reg = <0x01c20028 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll6_sata", "pll6_other", "pll6"; + }; + /* dummy is 200M */ cpu: cpu@01c20054 { #clock-cells = <0>; @@ -130,12 +146,11 @@ "apb0_ir", "apb0_keypad"; }; - /* dummy is pll62 */ apb1_mux: apb1_mux@01c20058 { #clock-cells = <0>; compatible = "allwinner,sun4i-apb1-mux-clk"; reg = <0x01c20058 0x4>; - clocks = <&osc24M>, <&dummy>, <&osc32k>; + clocks = <&osc24M>, <&pll6 1>, <&osc32k>; }; apb1: apb1@01c20058 { diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi index 8c4a9c3..cded3c7 100644 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi @@ -74,6 +74,22 @@ clocks = <&osc24M>; }; + pll5: pll5@01c20020 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-pll5-clk"; + reg = <0x01c20020 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll5_ddr", "pll5_other"; + }; + + pll6: pll6@01c20028 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-pll6-clk"; + reg = <0x01c20028 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll6_sata", "pll6_other", "pll6"; + }; + /* dummy is 200M */ cpu: cpu@01c20054 { #clock-cells = <0>; @@ -132,12 +148,11 @@ clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir"; }; - /* dummy is pll6 */ apb1_mux: apb1_mux@01c20058 { #clock-cells = <0>; compatible = "allwinner,sun4i-apb1-mux-clk"; reg = <0x01c20058 0x4>; - clocks = <&osc24M>, <&dummy>, <&osc32k>; + clocks = <&osc24M>, <&pll6 1>, <&osc32k>; }; apb1: apb1@01c20058 { diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index e4a5d37..a6cd039 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -69,23 +69,27 @@ clocks = <&osc24M>; }; - /* - * This is a dummy clock, to be used as placeholder on - * other mux clocks when a specific parent clock is not - * yet implemented. It should be dropped when the driver - * is complete. - */ - pll6: pll6 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; + pll5: pll5@01c20020 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-pll5-clk"; + reg = <0x01c20020 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll5_ddr", "pll5_other"; + }; + + pll6: pll6@01c20028 { + #clock-cells = <1>; + compatible = "allwinner,sun4i-pll6-clk"; + reg = <0x01c20028 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll6_sata", "pll6_other", "pll6"; }; cpu: cpu@01c20054 { #clock-cells = <0>; compatible = "allwinner,sun4i-cpu-clk"; reg = <0x01c20054 0x4>; - clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6>; + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>; }; axi: axi@01c20054 { @@ -144,7 +148,7 @@ #clock-cells = <0>; compatible = "allwinner,sun4i-apb1-mux-clk"; reg = <0x01c20058 0x4>; - clocks = <&osc24M>, <&pll6>, <&osc32k>; + clocks = <&osc24M>, <&pll6 1>, <&osc32k>; }; apb1: apb1@01c20058 { -- cgit v1.1 From 4b756ffb58a62ed8661126ca1b3209e2cf436852 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= Date: Mon, 23 Dec 2013 00:32:41 -0300 Subject: ARM: sun4i: dt: mod0 clocks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit adds all the mod0 clocks present on sun4i to its device tree Signed-off-by: Emilio López Acked-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10.dtsi | 120 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 5e2fc45..8aa9c97 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -180,6 +180,126 @@ "apb1_uart4", "apb1_uart5", "apb1_uart6", "apb1_uart7"; }; + + nand_clk: clk@01c20080 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20080 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "nand"; + }; + + ms_clk: clk@01c20084 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20084 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ms"; + }; + + mmc0_clk: clk@01c20088 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20088 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc0"; + }; + + mmc1_clk: clk@01c2008c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c2008c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc1"; + }; + + mmc2_clk: clk@01c20090 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20090 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc2"; + }; + + mmc3_clk: clk@01c20094 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20094 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc3"; + }; + + ts_clk: clk@01c20098 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20098 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ts"; + }; + + ss_clk: clk@01c2009c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c2009c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ss"; + }; + + spi0_clk: clk@01c200a0 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200a0 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "spi0"; + }; + + spi1_clk: clk@01c200a4 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200a4 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "spi1"; + }; + + spi2_clk: clk@01c200a8 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200a8 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "spi2"; + }; + + pata_clk: clk@01c200ac { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200ac 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "pata"; + }; + + ir0_clk: clk@01c200b0 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200b0 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ir0"; + }; + + ir1_clk: clk@01c200b4 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200b4 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ir1"; + }; + + spi3_clk: clk@01c200d4 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200d4 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "spi3"; + }; }; soc@01c00000 { -- cgit v1.1 From 8dc36bffd9c38f6a29542f3e833c2511c82666f1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= Date: Mon, 23 Dec 2013 00:32:42 -0300 Subject: ARM: sun5i: dt: mod0 clocks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit adds all the mod0 clocks available on A10 and A13. The list has been constructed by looking at the Allwinner code release for A10S and A13. Signed-off-by: Emilio López Acked-by: Maxime Ripard --- arch/arm/boot/dts/sun5i-a10s.dtsi | 88 +++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/sun5i-a13.dtsi | 88 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 176 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index b29412a..6de7d70 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@ -169,6 +169,94 @@ "apb1_i2c2", "apb1_uart0", "apb1_uart1", "apb1_uart2", "apb1_uart3"; }; + + nand_clk: clk@01c20080 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20080 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "nand"; + }; + + ms_clk: clk@01c20084 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20084 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ms"; + }; + + mmc0_clk: clk@01c20088 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20088 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc0"; + }; + + mmc1_clk: clk@01c2008c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c2008c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc1"; + }; + + mmc2_clk: clk@01c20090 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20090 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc2"; + }; + + ts_clk: clk@01c20098 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20098 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ts"; + }; + + ss_clk: clk@01c2009c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c2009c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ss"; + }; + + spi0_clk: clk@01c200a0 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200a0 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "spi0"; + }; + + spi1_clk: clk@01c200a4 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200a4 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "spi1"; + }; + + spi2_clk: clk@01c200a8 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200a8 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "spi2"; + }; + + ir0_clk: clk@01c200b0 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200b0 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ir0"; + }; }; soc@01c00000 { diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi index cded3c7..c46ac65 100644 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi @@ -170,6 +170,94 @@ clock-output-names = "apb1_i2c0", "apb1_i2c1", "apb1_i2c2", "apb1_uart1", "apb1_uart3"; }; + + nand_clk: clk@01c20080 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20080 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "nand"; + }; + + ms_clk: clk@01c20084 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20084 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ms"; + }; + + mmc0_clk: clk@01c20088 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20088 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc0"; + }; + + mmc1_clk: clk@01c2008c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c2008c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc1"; + }; + + mmc2_clk: clk@01c20090 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20090 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc2"; + }; + + ts_clk: clk@01c20098 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20098 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ts"; + }; + + ss_clk: clk@01c2009c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c2009c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ss"; + }; + + spi0_clk: clk@01c200a0 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200a0 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "spi0"; + }; + + spi1_clk: clk@01c200a4 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200a4 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "spi1"; + }; + + spi2_clk: clk@01c200a8 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200a8 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "spi2"; + }; + + ir0_clk: clk@01c200b0 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200b0 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ir0"; + }; }; soc@01c00000 { -- cgit v1.1 From 1c92b95b1ede437b674bd322265a1055b97c0d22 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= Date: Mon, 23 Dec 2013 00:32:43 -0300 Subject: ARM: sun7i: dt: mod0 clocks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit adds all the mod0 clocks available on A20 to its device tree. This list was created by looking at AW's code release. Signed-off-by: Emilio López Acked-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 120 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index a6cd039..bc99953 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -170,6 +170,126 @@ "apb1_uart2", "apb1_uart3", "apb1_uart4", "apb1_uart5", "apb1_uart6", "apb1_uart7"; }; + + nand_clk: clk@01c20080 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20080 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "nand"; + }; + + ms_clk: clk@01c20084 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20084 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ms"; + }; + + mmc0_clk: clk@01c20088 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20088 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc0"; + }; + + mmc1_clk: clk@01c2008c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c2008c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc1"; + }; + + mmc2_clk: clk@01c20090 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20090 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc2"; + }; + + mmc3_clk: clk@01c20094 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20094 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mmc3"; + }; + + ts_clk: clk@01c20098 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c20098 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ts"; + }; + + ss_clk: clk@01c2009c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c2009c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ss"; + }; + + spi0_clk: clk@01c200a0 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200a0 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "spi0"; + }; + + spi1_clk: clk@01c200a4 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200a4 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "spi1"; + }; + + spi2_clk: clk@01c200a8 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200a8 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "spi2"; + }; + + pata_clk: clk@01c200ac { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200ac 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "pata"; + }; + + ir0_clk: clk@01c200b0 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200b0 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ir0"; + }; + + ir1_clk: clk@01c200b4 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200b4 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "ir1"; + }; + + spi3_clk: clk@01c200d4 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c200d4 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "spi3"; + }; }; soc@01c00000 { -- cgit v1.1 From 118c07aedad55de8be81845e6d6429d266906b7d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= Date: Mon, 23 Dec 2013 00:32:44 -0300 Subject: ARM: sunxi: dt: add nodes for the mbus clock MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit mbus is the memory bus clock, and it is present on both sun5i and sun7i machines. Its register layout is compatible with the mod0 one. Signed-off-by: Emilio López Acked-by: Maxime Ripard --- arch/arm/boot/dts/sun5i-a10s.dtsi | 8 ++++++++ arch/arm/boot/dts/sun5i-a13.dtsi | 8 ++++++++ arch/arm/boot/dts/sun7i-a20.dtsi | 8 ++++++++ 3 files changed, 24 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index 6de7d70..e053db9 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@ -257,6 +257,14 @@ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "ir0"; }; + + mbus_clk: clk@01c2015c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c2015c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mbus"; + }; }; soc@01c00000 { diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi index c46ac65..227be94 100644 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi @@ -258,6 +258,14 @@ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "ir0"; }; + + mbus_clk: clk@01c2015c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c2015c 0x4>; + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; + clock-output-names = "mbus"; + }; }; soc@01c00000 { diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index bc99953..ee68196 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -290,6 +290,14 @@ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "spi3"; }; + + mbus_clk: clk@01c2015c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-mod0-clk"; + reg = <0x01c2015c 0x4>; + clocks = <&osc24M>, <&pll6 2>, <&pll5 1>; + clock-output-names = "mbus"; + }; }; soc@01c00000 { -- cgit v1.1 From 10b302a297aee952949423aaec0749b757f34950 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Sun, 17 Nov 2013 10:03:04 +0100 Subject: ARM: sun4i: dt: Move the aliases to the DTSI The aliases are shared across boards are really belong to the DTSI. Move them there. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10-a1000.dts | 4 ---- arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 5 ----- arch/arm/boot/dts/sun4i-a10.dtsi | 2 ++ 3 files changed, 2 insertions(+), 9 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts index eb4d73b..d4b081d 100644 --- a/arch/arm/boot/dts/sun4i-a10-a1000.dts +++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts @@ -18,10 +18,6 @@ model = "Mele A1000"; compatible = "mele,a1000", "allwinner,sun4i-a10"; - aliases { - serial0 = &uart0; - }; - soc@01c00000 { emac: ethernet@01c0b000 { pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts index 425a7db..f1c77e0 100644 --- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts +++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts @@ -17,11 +17,6 @@ model = "Cubietech Cubieboard"; compatible = "cubietech,a10-cubieboard", "allwinner,sun4i-a10"; - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - chosen { bootargs = "earlyprintk console=ttyS0,115200"; }; diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 3ba2b46..0adbbe3 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -17,6 +17,8 @@ aliases { ethernet0 = &emac; + serial0 = &uart0; + serial1 = &uart1; }; cpus { -- cgit v1.1 From a537d8fe3044e2f1503bbd67b00612d4bfb294e8 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Sun, 17 Nov 2013 10:05:22 +0100 Subject: ARM: sun4i: dt: Remove chosen nodes The chosen nodes are nowadays pretty useless, since they will be overriden by the bootloader anyway. We can thus safely remove them. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 4 ---- arch/arm/boot/dts/sun4i-a10-hackberry.dts | 4 ---- arch/arm/boot/dts/sun4i-a10-mini-xplus.dts | 4 ---- arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 4 ---- 4 files changed, 16 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts index f1c77e0..b139ee6 100644 --- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts +++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts @@ -17,10 +17,6 @@ model = "Cubietech Cubieboard"; compatible = "cubietech,a10-cubieboard", "allwinner,sun4i-a10"; - chosen { - bootargs = "earlyprintk console=ttyS0,115200"; - }; - soc@01c00000 { emac: ethernet@01c0b000 { pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts index b3ae51f..3a1595f 100644 --- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts +++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts @@ -18,10 +18,6 @@ model = "Miniand Hackberry"; compatible = "miniand,hackberry", "allwinner,sun4i-a10"; - chosen { - bootargs = "earlyprintk console=ttyS0,115200"; - }; - soc@01c00000 { emac: ethernet@01c0b000 { pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts index 0c1447c..70b3323 100644 --- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts +++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts @@ -18,10 +18,6 @@ model = "PineRiver Mini X-Plus"; compatible = "pineriver,mini-xplus", "allwinner,sun4i-a10"; - chosen { - bootargs = "earlyprintk console=ttyS0,115200"; - }; - soc@01c00000 { uart0: serial@01c28000 { pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts index 9e508dc..a4ba5ff 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts @@ -18,10 +18,6 @@ model = "Olimex A13-Olinuxino"; compatible = "olimex,a13-olinuxino", "allwinner,sun5i-a13"; - chosen { - bootargs = "earlyprintk console=ttyS0,115200"; - }; - soc@01c00000 { pinctrl@01c20800 { led_pins_olinuxino: led_pins@0 { -- cgit v1.1 From 57c8839c938707ad6980fa8c13f8ba29cdcc5449 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Tue, 31 Dec 2013 17:20:50 +0100 Subject: ARM: dts: sun4i: Add rtp controller node Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 0adbbe3..040bb0e 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -425,6 +425,12 @@ reg = <0x01c23800 0x10>; }; + rtp: rtp@01c25000 { + compatible = "allwinner,sun4i-ts"; + reg = <0x01c25000 0x100>; + interrupts = <29>; + }; + uart0: serial@01c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; -- cgit v1.1 From f65c93a0dadb39a198fa77b4ff43e1bd8d0531fe Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Tue, 31 Dec 2013 17:20:51 +0100 Subject: ARM: dts: sun5i: Add rtp controller node Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i-a10s.dtsi | 6 ++++++ arch/arm/boot/dts/sun5i-a13.dtsi | 6 ++++++ 2 files changed, 12 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index 50f34fd..9bb3a0d 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@ -382,6 +382,12 @@ reg = <0x01c23800 0x10>; }; + rtp: rtp@01c25000 { + compatible = "allwinner,sun4i-ts"; + reg = <0x01c25000 0x100>; + interrupts = <29>; + }; + uart0: serial@01c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi index 227be94..4dee971 100644 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi @@ -345,6 +345,12 @@ reg = <0x01c23800 0x10>; }; + rtp: rtp@01c25000 { + compatible = "allwinner,sun4i-ts"; + reg = <0x01c25000 0x100>; + interrupts = <29>; + }; + uart1: serial@01c28400 { compatible = "snps,dw-apb-uart"; reg = <0x01c28400 0x400>; -- cgit v1.1 From 00f7ed8d892f3370b6ae83d026cb7d22894ec15b Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Tue, 31 Dec 2013 17:20:52 +0100 Subject: ARM: dts: sun7i: Add rtp controller node Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 534f1f0..5cf371d 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -419,6 +419,12 @@ reg = <0x01c23800 0x200>; }; + rtp: rtp@01c25000 { + compatible = "allwinner,sun4i-ts"; + reg = <0x01c25000 0x100>; + interrupts = <0 29 4>; + }; + uart0: serial@01c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; -- cgit v1.1 From f2e0759e904676b27204bb35cdd18ddb2d03d8b1 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 1 Jan 2014 10:30:50 +0800 Subject: ARM: dts: sun7i: Add pin muxing options for clock outputs This patch adds the clock output pin options on the A20. The 2 pins can output a configurable clock to be used by external modules. This is used on the CubieTruck, to supply a 32768 Hz low power clock to the onboard Wifi+BT module. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 5cf371d..898b021 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -389,6 +389,20 @@ allwinner,drive = <0>; allwinner,pull = <0>; }; + + clk_out_a_pins_a: clk_out_a@0 { + allwinner,pins = "PI12"; + allwinner,function = "clk_out_a"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + clk_out_b_pins_a: clk_out_b@0 { + allwinner,pins = "PI13"; + allwinner,function = "clk_out_b"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; }; timer@01c20c00 { -- cgit v1.1 From 673fac742946bcb7cc43b9e67459862d6c4a8a6c Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 1 Jan 2014 10:30:47 +0800 Subject: ARM: dts: sun7i: Change 32768 Hz oscillator node name to clk@N style Device tree naming conventions state that node names should match the nodes function. Change external low speed oscillator node name to match. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 898b021..edad6f1 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -53,10 +53,11 @@ clock-frequency = <24000000>; }; - osc32k: osc32k { + osc32k: clk@0 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; + clock-output-names = "osc32k"; }; pll1: pll1@01c20000 { -- cgit v1.1 From 0aff0370cbffeadc14456556b904c80e30b3717e Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 1 Jan 2014 10:30:48 +0800 Subject: ARM: dts: sun7i: external clock outputs This commit adds the two external clock outputs available on A20 to its device tree. A dummy fixed factor clock is also added to serve as the first input of the clock outputs, which according to AW's A20 user manual, is the 24MHz oscillator divided by 750. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index edad6f1..0d54998 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -303,6 +303,34 @@ clocks = <&osc24M>, <&pll6 2>, <&pll5 1>; clock-output-names = "mbus"; }; + + /* + * Dummy clock used by output clocks + */ + osc24M_32k: clk@1 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <750>; + clock-mult = <1>; + clocks = <&osc24M>; + clock-output-names = "osc24M_32k"; + }; + + clk_out_a: clk@01c201f0 { + #clock-cells = <0>; + compatible = "allwinner,sun7i-a20-out-clk"; + reg = <0x01c201f0 0x4>; + clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; + clock-output-names = "clk_out_a"; + }; + + clk_out_b: clk@01c201f4 { + #clock-cells = <0>; + compatible = "allwinner,sun7i-a20-out-clk"; + reg = <0x01c201f4 0x4>; + clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>; + clock-output-names = "clk_out_b"; + }; }; soc@01c00000 { -- cgit v1.1 From 74e848f63371392d305b68efa9d4d94048dab294 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Fri, 20 Dec 2013 11:09:18 -0800 Subject: ARM: dts: MSM8974: Add restart node Add the restart node so we can reboot the device. Signed-off-by: Stephen Boyd Signed-off-by: David Brown Signed-off-by: Olof Johansson --- arch/arm/boot/dts/qcom-msm8974.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 2ebb4f0..df18637 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -29,5 +29,10 @@ <1 1 0xf08>; clock-frequency = <19200000>; }; + + restart@fc4ab000 { + compatible = "qcom,pshold"; + reg = <0xfc4ab000 0x4>; + }; }; }; -- cgit v1.1 From 47c5a5d6fd5839946c948563573cd9de077a91bb Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Fri, 20 Dec 2013 11:09:19 -0800 Subject: ARM: dts: MSM8974: Add MMIO architected timer node Add the mmio architected timer node. Signed-off-by: Stephen Boyd Signed-off-by: David Brown Signed-off-by: Olof Johansson --- arch/arm/boot/dts/qcom-msm8974.dtsi | 59 +++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index df18637..6ac9496 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -30,6 +30,65 @@ clock-frequency = <19200000>; }; + timer@f9020000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0xf9020000 0x1000>; + clock-frequency = <19200000>; + + frame@f9021000 { + frame-number = <0>; + interrupts = <0 8 0x4>, + <0 7 0x4>; + reg = <0xf9021000 0x1000>, + <0xf9022000 0x1000>; + }; + + frame@f9023000 { + frame-number = <1>; + interrupts = <0 9 0x4>; + reg = <0xf9023000 0x1000>; + status = "disabled"; + }; + + frame@f9024000 { + frame-number = <2>; + interrupts = <0 10 0x4>; + reg = <0xf9024000 0x1000>; + status = "disabled"; + }; + + frame@f9025000 { + frame-number = <3>; + interrupts = <0 11 0x4>; + reg = <0xf9025000 0x1000>; + status = "disabled"; + }; + + frame@f9026000 { + frame-number = <4>; + interrupts = <0 12 0x4>; + reg = <0xf9026000 0x1000>; + status = "disabled"; + }; + + frame@f9027000 { + frame-number = <5>; + interrupts = <0 13 0x4>; + reg = <0xf9027000 0x1000>; + status = "disabled"; + }; + + frame@f9028000 { + frame-number = <6>; + interrupts = <0 14 0x4>; + reg = <0xf9028000 0x1000>; + status = "disabled"; + }; + }; + restart@fc4ab000 { compatible = "qcom,pshold"; reg = <0xfc4ab000 0x4>; -- cgit v1.1 From 5631e7f4e29b1ebf3d856614c0b5876463857da6 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 26 Dec 2013 19:43:10 -0700 Subject: ARM: bcm2835: add USB controller to device tree The BCM2835 SoC contains a DWC2 USB controller. Add this to the DT. Set up the pin controller to fully enable the USB controller on the Raspberry Pi. The GPIO setup works because the default output value for GPIO 6 (LAN_RUN/n_reset) just happens to be 1, which enables the USB/LAN chip. Note that you'll need a U-Boot which enables power to the USB controller; search for U-Boot patch "ARM: rpi_b: power on SDHCI and USB HW modules". Signed-off-by: Stephen Warren Signed-off-by: Olof Johansson --- arch/arm/boot/dts/bcm2835-rpi-b.dts | 9 +++++++-- arch/arm/boot/dts/bcm2835.dtsi | 6 ++++++ 2 files changed, 13 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts index 6e9deb7..2a3b1c1 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts @@ -23,10 +23,15 @@ &gpio { pinctrl-names = "default"; - pinctrl-0 = <&alt0 &alt3>; + pinctrl-0 = <&gpioout &alt0 &alt3>; + + gpioout: gpioout { + brcm,pins = <6>; + brcm,function = <1>; /* GPIO out */ + }; alt0: alt0 { - brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11 14 15 40 45>; + brcm,pins = <0 1 2 3 4 5 7 8 9 10 11 14 15 40 45>; brcm,function = <4>; /* alt0 */ }; diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi index aa537ed..b021c96 100644 --- a/arch/arm/boot/dts/bcm2835.dtsi +++ b/arch/arm/boot/dts/bcm2835.dtsi @@ -107,6 +107,12 @@ clocks = <&clk_mmc>; status = "disabled"; }; + + usb { + compatible = "brcm,bcm2835-usb"; + reg = <0x7e980000 0x10000>; + interrupts = <1 9>; + }; }; clocks { -- cgit v1.1 From 9dd51c9f778199d343ae55db8a7d084e27501211 Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Thu, 12 Dec 2013 07:32:39 +0900 Subject: ARM: dts: Add initial support for Arndale Octa board Arndale Octa board is based on Exynos5420 SoC. This patch adds the basic support required for booting it through DT. Signed-off-by: Sachin Kamat Reviewed-by: Tomasz Figa Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/exynos5420-arndale-octa.dts | 66 +++++++++++++++++++++++++++ 2 files changed, 67 insertions(+) create mode 100644 arch/arm/boot/dts/exynos5420-arndale-octa.dts (limited to 'arch') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index d57c1a6..8a90624 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -63,6 +63,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ exynos5250-arndale.dtb \ exynos5250-smdk5250.dtb \ exynos5250-snow.dtb \ + exynos5420-arndale-octa.dtb \ exynos5420-smdk5420.dtb \ exynos5440-sd5v1.dtb \ exynos5440-ssdk5440.dtb diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts new file mode 100644 index 0000000..7340745 --- /dev/null +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts @@ -0,0 +1,66 @@ +/* + * Samsung's Exynos5420 based Arndale Octa board device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/dts-v1/; +#include "exynos5420.dtsi" + +/ { + model = "Insignal Arndale Octa evaluation board based on EXYNOS5420"; + compatible = "insignal,arndale-octa", "samsung,exynos5420"; + + memory { + reg = <0x20000000 0x80000000>; + }; + + chosen { + bootargs = "console=ttySAC3,115200"; + }; + + fixed-rate-clocks { + oscclk { + compatible = "samsung,exynos5420-oscclk"; + clock-frequency = <24000000>; + }; + }; + + mmc@12200000 { + status = "okay"; + broken-cd; + supports-highspeed; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <0 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; + + slot@0 { + reg = <0>; + bus-width = <8>; + }; + }; + + mmc@12220000 { + status = "okay"; + supports-highspeed; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; + + slot@0 { + reg = <0>; + bus-width = <4>; + }; + }; +}; -- cgit v1.1 From b67a55125f1413902f7db6d167a8d9e4154386bf Mon Sep 17 00:00:00 2001 From: Alex Ling Date: Thu, 19 Dec 2013 05:34:26 +0900 Subject: ARM: dts: add support for EXYNOS4412 based TINY4412 board Add a minimal board dts file for EXYNOS4412 based FriendlyARM's TINY4412 board. This patch including support peripherals like UART, SD card on SDMMC2 port and GPIO connected LEDs. Signed-off-by: Alex Ling Reviewed-by: Tomasz Figa Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/exynos4412-tiny4412.dts | 93 +++++++++++++++++++++++++++++++ 2 files changed, 94 insertions(+) create mode 100644 arch/arm/boot/dts/exynos4412-tiny4412.dts (limited to 'arch') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 8a90624..fa70ea2 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -59,6 +59,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ exynos4412-odroidx.dtb \ exynos4412-origen.dtb \ exynos4412-smdk4412.dtb \ + exynos4412-tiny4412.dtb \ exynos4412-trats2.dtb \ exynos5250-arndale.dtb \ exynos5250-smdk5250.dtb \ diff --git a/arch/arm/boot/dts/exynos4412-tiny4412.dts b/arch/arm/boot/dts/exynos4412-tiny4412.dts new file mode 100644 index 0000000..0a98312 --- /dev/null +++ b/arch/arm/boot/dts/exynos4412-tiny4412.dts @@ -0,0 +1,93 @@ +/* + * FriendlyARM's Exynos4412 based TINY4412 board device tree source + * + * Copyright (c) 2013 Alex Ling + * + * Device tree source file for FriendlyARM's TINY4412 board which is based on + * Samsung's Exynos4412 SoC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/dts-v1/; +#include "exynos4412.dtsi" + +/ { + model = "FriendlyARM TINY4412 board based on Exynos4412"; + compatible = "friendlyarm,tiny4412", "samsung,exynos4412"; + + memory { + reg = <0x40000000 0x40000000>; + }; + + leds { + compatible = "gpio-leds"; + + led1 { + label = "led1"; + gpios = <&gpm4 0 1>; + default-state = "off"; + linux,default-trigger = "heartbeat"; + }; + + led2 { + label = "led2"; + gpios = <&gpm4 1 1>; + default-state = "off"; + }; + + led3 { + label = "led3"; + gpios = <&gpm4 2 1>; + default-state = "off"; + }; + + led4 { + label = "led4"; + gpios = <&gpm4 3 1>; + default-state = "off"; + linux,default-trigger = "mmc0"; + }; + }; + + rtc@10070000 { + status = "okay"; + }; + + sdhci@12530000 { + bus-width = <4>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; + pinctrl-names = "default"; + status = "okay"; + }; + + serial@13800000 { + status = "okay"; + }; + + serial@13810000 { + status = "okay"; + }; + + serial@13820000 { + status = "okay"; + }; + + serial@13830000 { + status = "okay"; + }; + + fixed-rate-clocks { + xxti { + compatible = "samsung,clock-xxti"; + clock-frequency = <0>; + }; + + xusbxti { + compatible = "samsung,clock-xusbxti"; + clock-frequency = <24000000>; + }; + }; +}; -- cgit v1.1 From 6267355f0e513bed9a5009924abc7a1e7de22ab3 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 6 Jan 2014 13:58:12 +0800 Subject: arm: sun7i: cubietruck: Enable the i2c controllers The Cubietruck makes use of the first three i2c controllers found on the Allwinner A20; i2c-0 is used internally for the PMIC, i2c-1 is exposed on the board headers, and i2c-2 is used for DDC on the VGA connector. This patch enables them in the device tree. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts index 8a1009d..f9dcb61 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts @@ -33,6 +33,24 @@ pinctrl-0 = <&uart0_pins_a>; status = "okay"; }; + + i2c0: i2c@01c2ac00 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + }; + + i2c1: i2c@01c2b000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; + }; + + i2c2: i2c@01c2b400 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; + }; }; leds { -- cgit v1.1 From 9a21e55d77ab909b36c2c730e5a1e1d1a9a57c5e Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Mon, 6 Jan 2014 20:54:43 -0600 Subject: ARM: dts: socfpga: update L2 tag and data latency Sets the appropriate L2-cache latencies for the SOCFPGA platform. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index f936476..efcc38a 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -467,6 +467,8 @@ interrupts = <0 38 0x04>; cache-unified; cache-level = <2>; + arm,tag-latency = <1 1 1>; + arm,data-latency = <2 1 1>; }; /* Local timer */ -- cgit v1.1 From 672ef909e9b10933dc676c87d1bdeaabfcc11dda Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Wed, 8 Jan 2014 12:01:26 -0600 Subject: ARM: dts: socfpga: add pl330 clock The pl330 dmac won't be added to the list of amba devices, as it doesn't have a clock entry. Add the clock. Signed-off-by: Steffen Trumtrar Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index efcc38a..537f1a5 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -79,6 +79,8 @@ #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <32>; + clocks = <&l4_main_clk>; + clock-names = "apb_pclk"; }; }; -- cgit v1.1 From 794f8b21a386703646496442693398c770a7e1df Mon Sep 17 00:00:00 2001 From: Barry Song Date: Thu, 9 Jan 2014 12:02:53 +0800 Subject: ARM: dts: sirf: add lost clocks for cphifbg This patch adds lost clocks property(index 42) for cphifbg node in prima2 and atlas6 dtsi. Signed-off-by: Barry Song --- arch/arm/boot/dts/atlas6.dtsi | 1 + arch/arm/boot/dts/prima2.dtsi | 1 + 2 files changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi index 978bab4..f303a6c 100644 --- a/arch/arm/boot/dts/atlas6.dtsi +++ b/arch/arm/boot/dts/atlas6.dtsi @@ -69,6 +69,7 @@ cphifbg@88030000 { compatible = "sirf,prima2-cphifbg"; reg = <0x88030000 0x1000>; + clocks = <&clks 42>; }; }; diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi index daee5894..de3cfa5 100644 --- a/arch/arm/boot/dts/prima2.dtsi +++ b/arch/arm/boot/dts/prima2.dtsi @@ -80,6 +80,7 @@ cphifbg@88030000 { compatible = "sirf,prima2-cphifbg"; reg = <0x88030000 0x1000>; + clocks = <&clks 42>; }; }; -- cgit v1.1 From 7f97c303450135b2c6daee02891d8fcb752b1a11 Mon Sep 17 00:00:00 2001 From: Bin Shi Date: Thu, 9 Jan 2014 12:08:46 +0800 Subject: ARM: dts: sirf: add lost bus_width, clock and status for sdhci some nodes missed bus_width, clocks and status properties, here we fix them in prima2 and atlas6 dtsi. Signed-off-by: Bin Shi Signed-off-by: Barry Song --- arch/arm/boot/dts/atlas6.dtsi | 4 ++++ arch/arm/boot/dts/prima2.dtsi | 13 +++++++++++++ 2 files changed, 17 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi index f303a6c..0f1821a 100644 --- a/arch/arm/boot/dts/atlas6.dtsi +++ b/arch/arm/boot/dts/atlas6.dtsi @@ -637,6 +637,7 @@ reg = <0x56100000 0x100000>; interrupts = <38>; status = "disabled"; + bus-width = <4>; clocks = <&clks 36>; }; @@ -646,6 +647,7 @@ reg = <0x56200000 0x100000>; interrupts = <23>; status = "disabled"; + bus-width = <4>; clocks = <&clks 37>; }; @@ -655,6 +657,7 @@ reg = <0x56300000 0x100000>; interrupts = <23>; status = "disabled"; + bus-width = <4>; clocks = <&clks 37>; }; @@ -664,6 +667,7 @@ reg = <0x56500000 0x100000>; interrupts = <39>; status = "disabled"; + bus-width = <4>; clocks = <&clks 38>; }; diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi index de3cfa5..8cea924 100644 --- a/arch/arm/boot/dts/prima2.dtsi +++ b/arch/arm/boot/dts/prima2.dtsi @@ -649,6 +649,9 @@ compatible = "sirf,prima2-sdhc"; reg = <0x56000000 0x100000>; interrupts = <38>; + status = "disabled"; + bus-width = <8>; + clocks = <&clks 36>; }; sd1: sdhci@56100000 { @@ -656,6 +659,9 @@ compatible = "sirf,prima2-sdhc"; reg = <0x56100000 0x100000>; interrupts = <38>; + status = "disabled"; + bus-width = <4>; + clocks = <&clks 36>; }; sd2: sdhci@56200000 { @@ -663,6 +669,8 @@ compatible = "sirf,prima2-sdhc"; reg = <0x56200000 0x100000>; interrupts = <23>; + status = "disabled"; + clocks = <&clks 37>; }; sd3: sdhci@56300000 { @@ -670,6 +678,8 @@ compatible = "sirf,prima2-sdhc"; reg = <0x56300000 0x100000>; interrupts = <23>; + status = "disabled"; + clocks = <&clks 37>; }; sd4: sdhci@56400000 { @@ -677,6 +687,8 @@ compatible = "sirf,prima2-sdhc"; reg = <0x56400000 0x100000>; interrupts = <39>; + status = "disabled"; + clocks = <&clks 38>; }; sd5: sdhci@56500000 { @@ -684,6 +696,7 @@ compatible = "sirf,prima2-sdhc"; reg = <0x56500000 0x100000>; interrupts = <39>; + clocks = <&clks 38>; }; pci-copy@57900000 { -- cgit v1.1 From 683659f3e0428ecf80d099b3b9e208d7c09fcfb9 Mon Sep 17 00:00:00 2001 From: Rongjun Ying Date: Thu, 9 Jan 2014 12:14:37 +0800 Subject: ARM: dts: sirf: add clock, frequence-voltage table for CPU0 prima2 and atlas6 uses cpufreq_cpu0, here we put related clock, operation points in dtsi. Signed-off-by: Rongjun Ying Signed-off-by: Barry Song --- arch/arm/boot/dts/atlas6.dtsi | 9 +++++++++ arch/arm/boot/dts/prima2.dtsi | 9 +++++++++ 2 files changed, 18 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi index 0f1821a..2b5d678 100644 --- a/arch/arm/boot/dts/atlas6.dtsi +++ b/arch/arm/boot/dts/atlas6.dtsi @@ -27,6 +27,15 @@ timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; + clocks = <&clks 12>; + operating-points = < + /* kHz uV */ + 200000 1025000 + 400000 1025000 + 600000 1050000 + 800000 1100000 + >; + clock-latency = <150000>; }; }; diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi index 8cea924..0942f9a 100644 --- a/arch/arm/boot/dts/prima2.dtsi +++ b/arch/arm/boot/dts/prima2.dtsi @@ -29,6 +29,15 @@ timebase-frequency = <0>; bus-frequency = <0>; clock-frequency = <0>; + clocks = <&clks 12>; + operating-points = < + /* kHz uV */ + 200000 1025000 + 400000 1025000 + 664000 1050000 + 800000 1100000 + >; + clock-latency = <150000>; }; }; -- cgit v1.1 From 423ef7914e2d3bd1121f54a8b2146e7076f59562 Mon Sep 17 00:00:00 2001 From: Xianglong Du Date: Thu, 9 Jan 2014 12:23:09 +0800 Subject: ARM: dts: sirf: add lost minigpsrtc device node This patch adds lost minigpsrtc device node for prima2 and atlas6, which is behind rtc-iobg and whose offset is 2000. Signed-off-by: Xianglong Du Signed-off-by: Barry Song --- arch/arm/boot/dts/atlas6.dtsi | 6 ++++++ arch/arm/boot/dts/prima2.dtsi | 6 ++++++ 2 files changed, 12 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi index 2b5d678..bc2d449 100644 --- a/arch/arm/boot/dts/atlas6.dtsi +++ b/arch/arm/boot/dts/atlas6.dtsi @@ -711,6 +711,12 @@ interrupts = <52 53 54>; }; + minigpsrtc@2000 { + compatible = "sirf,prima2-minigpsrtc"; + reg = <0x2000 0x1000>; + interrupts = <54>; + }; + pwrc@3000 { compatible = "sirf,prima2-pwrc"; reg = <0x3000 0x1000>; diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi index 0942f9a..00a4b20 100644 --- a/arch/arm/boot/dts/prima2.dtsi +++ b/arch/arm/boot/dts/prima2.dtsi @@ -739,6 +739,12 @@ interrupts = <52 53 54>; }; + minigpsrtc@2000 { + compatible = "sirf,prima2-minigpsrtc"; + reg = <0x2000 0x1000>; + interrupts = <54>; + }; + pwrc@3000 { compatible = "sirf,prima2-pwrc"; reg = <0x3000 0x1000>; -- cgit v1.1 From ec2b50cad1cf6e80b86eccae40404827161b94c5 Mon Sep 17 00:00:00 2001 From: Qipan Li Date: Fri, 3 Jan 2014 10:59:23 +0800 Subject: ARM: dts: SiRF: add lost usp1_uart_nostreamctrl pin group for atlas6 this patch adds lost usp1_uart_nostreamctrl pin group for atlas6, which matches with the change in drivers/pinctrl/sirf/pinctrl-atlas6.c. Signed-off-by: Qipan Li Signed-off-by: Barry Song --- arch/arm/boot/dts/atlas6.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi index bc2d449..f8674bc 100644 --- a/arch/arm/boot/dts/atlas6.dtsi +++ b/arch/arm/boot/dts/atlas6.dtsi @@ -556,6 +556,12 @@ sirf,function = "usp1"; }; }; + usp1_uart_nostreamctrl_pins_a: usp1@1 { + usp1 { + sirf,pins = "usp1_uart_nostreamctrl_grp"; + sirf,function = "usp1_uart_nostreamctrl"; + }; + }; usb0_upli_drvbus_pins_a: usb0_upli_drvbus@0 { usb0_upli_drvbus { sirf,pins = "usb0_upli_drvbusgrp"; -- cgit v1.1 From 73f68c01f468f072776d98f6bbf7fb367a1f2540 Mon Sep 17 00:00:00 2001 From: Rongjun Ying Date: Fri, 3 Jan 2014 10:59:26 +0800 Subject: ARM: dts: SiRF: add pin group for USP0 with only RX or TX frame sync add pin groups for USP0 only holding one of TX and RX frame sync. this patch matches with the change in drivers/pinctrl/sirf. Signed-off-by: Rongjun Ying Signed-off-by: Barry Song --- arch/arm/boot/dts/prima2.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi index 00a4b20..0e21993 100644 --- a/arch/arm/boot/dts/prima2.dtsi +++ b/arch/arm/boot/dts/prima2.dtsi @@ -550,6 +550,18 @@ "usp0_uart_nostreamctrl"; }; }; + usp0_only_utfs_pins_a: usp0@2 { + usp0 { + sirf,pins = "usp0_only_utfs_grp"; + sirf,function = "usp0_only_utfs"; + }; + }; + usp0_only_urfs_pins_a: usp0@3 { + usp0 { + sirf,pins = "usp0_only_urfs_grp"; + sirf,function = "usp0_only_urfs"; + }; + }; usp1_pins_a: usp1@0 { usp1 { sirf,pins = "usp1grp"; -- cgit v1.1