From 0f2c9f20e4e339de30cfd5613dfa9505e7b9c58b Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 28 Mar 2012 19:22:30 +0900 Subject: ARM: mach-shmobile: Introduce shmobile_setup_delay() Add the function shmobile_setup_delay() to let platforms configure their maximum loops per jiffy delay. With this jiffies calculation done the dependency on early timer is removed. In the future this allows us to assign timers using the regular driver model via the device tree. Signed-off-by: Magnus Damm Signed-off-by: Rafael J. Wysocki --- arch/arm/mach-shmobile/include/mach/common.h | 2 ++ arch/arm/mach-shmobile/timer.c | 17 +++++++++++++++++ 2 files changed, 19 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index 83ad3fe..cc1d735 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -3,6 +3,8 @@ extern void shmobile_earlytimer_init(void); extern struct sys_timer shmobile_timer; +extern void shmobile_setup_delay(unsigned int max_cpu_core_mhz, + unsigned int mult, unsigned int div); struct twd_local_timer; void shmobile_twd_init(struct twd_local_timer *twd_local_timer); extern void shmobile_setup_console(void); diff --git a/arch/arm/mach-shmobile/timer.c b/arch/arm/mach-shmobile/timer.c index 2fba5f3..599e008 100644 --- a/arch/arm/mach-shmobile/timer.c +++ b/arch/arm/mach-shmobile/timer.c @@ -19,9 +19,26 @@ * */ #include +#include #include #include +void __init shmobile_setup_delay(unsigned int max_cpu_core_mhz, + unsigned int mult, unsigned int div) +{ + /* calculate a worst-case loops-per-jiffy value + * based on maximum cpu core mhz setting and the + * __delay() implementation in arch/arm/lib/delay.S + * + * this will result in a longer delay than expected + * when the cpu core runs on lower frequencies. + */ + + unsigned int value = (1000000 * mult) / (HZ * div); + + lpj_fine = max_cpu_core_mhz * value; +} + static void __init shmobile_late_time_init(void) { /* -- cgit v1.1 From d7e7e4ffc64f700e876a9f3b2727febaa2041221 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 28 Mar 2012 19:22:46 +0900 Subject: ARM: mach-shmobile: Introduce INTC_IRQ_PINS_16H Add INTC_IRQ_PINS_16H to allow broken out support of the the high 16 external interrupt pins. On SoCs with 32 external interrupt pins the interrupt vectors for the low 16 and the high 16 interrupt pins are sparesly populated. The low 16 are at 0x0200 and high 16 are at 0x3200 which with current macros results in a separation of 384 linux interrupts. This sparse population makes it unsuitable with a single IRQ domain to cover the full IRQ range, so this macro breaks out the 32 pins into two separate 16 bit controllers to allow two independent INTC instances with two separate IRQ domains. Signed-off-by: Magnus Damm Signed-off-by: Rafael J. Wysocki --- arch/arm/mach-shmobile/include/mach/intc.h | 44 ++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/include/mach/intc.h b/arch/arm/mach-shmobile/include/mach/intc.h index 8b22258..a5603c7 100644 --- a/arch/arm/mach-shmobile/include/mach/intc.h +++ b/arch/arm/mach-shmobile/include/mach/intc.h @@ -142,6 +142,50 @@ static struct intc_desc p ## _desc __initdata = { \ p ## _sense_registers, p ## _ack_registers) \ } +#define INTC_IRQ_PINS_16H(p, base, vect, str) \ + \ +static struct resource p ## _resources[] __initdata = { \ + [0] = { \ + .start = base, \ + .end = base + 0x64, \ + .flags = IORESOURCE_MEM, \ + }, \ +}; \ + \ +enum { \ + p ## _UNUSED = 0, \ + INTC_IRQ_PINS_ENUM_16H(p), \ +}; \ + \ +static struct intc_vect p ## _vectors[] __initdata = { \ + INTC_IRQ_PINS_VECT_16H(p, vect), \ +}; \ + \ +static struct intc_mask_reg p ## _mask_registers[] __initdata = { \ + INTC_IRQ_PINS_MASK_16H(p, base), \ +}; \ + \ +static struct intc_prio_reg p ## _prio_registers[] __initdata = { \ + INTC_IRQ_PINS_PRIO_16H(p, base), \ +}; \ + \ +static struct intc_sense_reg p ## _sense_registers[] __initdata = { \ + INTC_IRQ_PINS_SENSE_16H(p, base), \ +}; \ + \ +static struct intc_mask_reg p ## _ack_registers[] __initdata = { \ + INTC_IRQ_PINS_ACK_16H(p, base), \ +}; \ + \ +static struct intc_desc p ## _desc __initdata = { \ + .name = str, \ + .resource = p ## _resources, \ + .num_resources = ARRAY_SIZE(p ## _resources), \ + .hw = INTC_HW_DESC(p ## _vectors, NULL, \ + p ## _mask_registers, p ## _prio_registers, \ + p ## _sense_registers, p ## _ack_registers) \ +} + #define INTC_IRQ_PINS_32(p, base, vect, str) \ \ static struct resource p ## _resources[] __initdata = { \ -- cgit v1.1 From 1ee8299a9ec1ce5137a044c7768293007b9a3267 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 28 Mar 2012 19:22:54 +0900 Subject: ARM: mach-shmobile: Use 0x3400 as INTCS vector offset Update mach-shmobile to use 0x3400 as INTCS_VECT_BASE. Since the ARM architecture a little while back added support for 10 bit irqs we can now undo the previously merged commit 9b7c23adb350a108737a993c9c781463c1439dc6 and use 0x3400 as INTCS vector base. This change is necessary to avoid overlapping of interrupt ranges so separate IRQ domains can be used for different INTC instances. Without this fix the vectors used by various INTC instances are overlapping on for instance sh7372 which works at the moment but breaks upcoming IRQ domain support. Signed-off-by: Magnus Damm Signed-off-by: Rafael J. Wysocki --- arch/arm/mach-shmobile/include/mach/irqs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h index 4e686cc2..06a5da3 100644 --- a/arch/arm/mach-shmobile/include/mach/irqs.h +++ b/arch/arm/mach-shmobile/include/mach/irqs.h @@ -7,7 +7,7 @@ #define gic_spi(nr) ((nr) + 32) /* INTCS */ -#define INTCS_VECT_BASE 0x2200 +#define INTCS_VECT_BASE 0x3400 #define INTCS_VECT(n, vect) INTC_VECT((n), INTCS_VECT_BASE + (vect)) #define intcs_evt2irq(evt) evt2irq(INTCS_VECT_BASE + (evt)) -- cgit v1.1 From 2ff6530c065814035df505ae8a6ddf461b3441d3 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 28 Mar 2012 19:23:03 +0900 Subject: ARM: mach-shmobile: Use INTC_IRQ_PINS_16H on sh7372 Use INTC_IRQ_PINS_16H on sh7372 to have two separate interrupt controllers for the external IRQ pins. This is preparation work for future IRQ domain support. Signed-off-by: Magnus Damm Signed-off-by: Rafael J. Wysocki --- arch/arm/mach-shmobile/intc-sh7372.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c index 6447e0a..0ba8b7b 100644 --- a/arch/arm/mach-shmobile/intc-sh7372.c +++ b/arch/arm/mach-shmobile/intc-sh7372.c @@ -305,8 +305,12 @@ static DECLARE_INTC_DESC(intca_desc, "sh7372-intca", intca_mask_registers, intca_prio_registers, NULL); -INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000, - INTC_VECT, "sh7372-intca-irq-pins"); +INTC_IRQ_PINS_16(intca_irq_pins_lo, 0xe6900000, + INTC_VECT, "sh7372-intca-irq-lo"); + +INTC_IRQ_PINS_16H(intca_irq_pins_hi, 0xe6900000, + INTC_VECT, "sh7372-intca-irq-hi"); + enum { UNUSED_INTCS = 0, ENABLED_INTCS, @@ -563,7 +567,8 @@ void __init sh7372_init_irq(void) intcs_ffd5 = ioremap_nocache(0xffd50000, PAGE_SIZE); register_intc_controller(&intca_desc); - register_intc_controller(&intca_irq_pins_desc); + register_intc_controller(&intca_irq_pins_lo_desc); + register_intc_controller(&intca_irq_pins_hi_desc); register_intc_controller(&intcs_desc); /* demux using INTEVTSA */ -- cgit v1.1 From 012f825f13d8e5f1007d1f604517dba1b9a5586e Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 28 Mar 2012 19:23:11 +0900 Subject: ARM: mach-shmobile: Rework sh7372 INTCS demuxer V2 This patch is the sh7372 INTC demux rework V2. Updates the sh7372 INTCS demuxer to not hook into the INTCA interrupt controller. The mask register for the chained INTCS interrupt source happens to be located in the INTCS register range instead of the INTCA as expected. To allow each INTCA and INTCS interrupt controller to work in their own IRQ range this patch moves the INTCS vector away. Needed for future IRQ domain support. Signed-off-by: Magnus Damm Signed-off-by: Rafael J. Wysocki --- arch/arm/mach-shmobile/intc-sh7372.c | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c index 0ba8b7b..2587a22 100644 --- a/arch/arm/mach-shmobile/intc-sh7372.c +++ b/arch/arm/mach-shmobile/intc-sh7372.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -315,8 +316,6 @@ enum { UNUSED_INTCS = 0, ENABLED_INTCS, - INTCS, - /* interrupt sources INTCS */ /* IRQ0S - IRQ31S */ @@ -430,8 +429,6 @@ static struct intc_vect intcs_vectors[] = { INTCS_VECT(CPORTS2R, 0x1a20), /* CEC */ INTCS_VECT(JPU6E, 0x1a80), - - INTC_VECT(INTCS, 0xf80), }; static struct intc_group intcs_groups[] __initdata = { @@ -494,9 +491,6 @@ static struct intc_mask_reg intcs_mask_registers[] = { { 0xffd5019c, 0xffd501dc, 8, /* IMR7SA3 / IMCR7SA3 */ { MFIS2_INTCS, CPORTS2R, 0, 0, JPU6E, 0, 0, 0 } }, - { 0xffd20104, 0, 16, /* INTAMASK */ - { 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, INTCS } }, }; /* Priority is needed for INTCA to receive the INTCS interrupt */ @@ -561,6 +555,7 @@ static void __iomem *intcs_ffd5; void __init sh7372_init_irq(void) { void __iomem *intevtsa; + int n; intcs_ffd2 = ioremap_nocache(0xffd20000, PAGE_SIZE); intevtsa = intcs_ffd2 + 0x100; @@ -571,9 +566,19 @@ void __init sh7372_init_irq(void) register_intc_controller(&intca_irq_pins_hi_desc); register_intc_controller(&intcs_desc); + /* setup dummy cascade chip for INTCS */ + n = evt2irq(0xf80); + irq_alloc_desc_at(n, numa_node_id()); + irq_set_chip_and_handler_name(n, &dummy_irq_chip, + handle_level_irq, "level"); + set_irq_flags(n, IRQF_VALID); /* yuck */ + /* demux using INTEVTSA */ - irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa); - irq_set_chained_handler(evt2irq(0xf80), intcs_demux); + irq_set_handler_data(n, (void *)intevtsa); + irq_set_chained_handler(n, intcs_demux); + + /* unmask INTCS in INTAMASK */ + iowrite16(0, intcs_ffd2 + 0x104); } static unsigned short ffd2[0x200]; -- cgit v1.1 From 3b7b70552afe351a8bd8fff1eb2d60aab2206576 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 28 Mar 2012 15:53:40 +0900 Subject: ARM: mach-shmobile: sh7372 generic board support via DT V2 Add generic DT board support for the sh7372 SoC V2. SCIF serial ports and timers are kept as regular platform devices. Other on-chip and on-board devices should be configured via the device tree. Tested on the mackerel board via kexec using a zImage kernel with an appended dtb. At this point there is no interrupt controller support in place but such code will be added over time when proper IRQ domain support has been added to INTC. Signed-off-by: Magnus Damm Signed-off-by: Rafael J. Wysocki --- arch/arm/boot/dts/sh7372.dtsi | 21 +++++++++++++++ arch/arm/mach-shmobile/setup-sh7372.c | 48 +++++++++++++++++++++++++++++++++++ 2 files changed, 69 insertions(+) create mode 100644 arch/arm/boot/dts/sh7372.dtsi (limited to 'arch') diff --git a/arch/arm/boot/dts/sh7372.dtsi b/arch/arm/boot/dts/sh7372.dtsi new file mode 100644 index 0000000..677fc60 --- /dev/null +++ b/arch/arm/boot/dts/sh7372.dtsi @@ -0,0 +1,21 @@ +/* + * Device Tree Source for the sh7372 SoC + * + * Copyright (C) 2012 Renesas Solutions Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "renesas,sh7372"; + + cpus { + cpu@0 { + compatible = "arm,cortex-a8"; + }; + }; +}; diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c index 2fe8f83..4c7fece 100644 --- a/arch/arm/mach-shmobile/setup-sh7372.c +++ b/arch/arm/mach-shmobile/setup-sh7372.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -1092,3 +1093,50 @@ void __init sh7372_add_early_devices(void) /* override timer setup with soc-specific code */ shmobile_timer.init = sh7372_earlytimer_init; } + +#ifdef CONFIG_USE_OF + +void __init sh7372_add_early_devices_dt(void) +{ + shmobile_setup_delay(800, 1, 3); /* Cortex-A8 @ 800MHz */ + + early_platform_add_devices(sh7372_early_devices, + ARRAY_SIZE(sh7372_early_devices)); + + /* setup early console here as well */ + shmobile_setup_console(); +} + +static const struct of_dev_auxdata sh7372_auxdata_lookup[] __initconst = { + { } +}; + +void __init sh7372_add_standard_devices_dt(void) +{ + /* clocks are setup late during boot in the case of DT */ + sh7372_clock_init(); + + platform_add_devices(sh7372_early_devices, + ARRAY_SIZE(sh7372_early_devices)); + + of_platform_populate(NULL, of_default_bus_match_table, + sh7372_auxdata_lookup, NULL); +} + +static const char *sh7372_boards_compat_dt[] __initdata = { + "renesas,sh7372", + NULL, +}; + +DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)") + .map_io = sh7372_map_io, + .init_early = sh7372_add_early_devices_dt, + .nr_irqs = NR_IRQS_LEGACY, + .init_irq = sh7372_init_irq, + .handle_irq = shmobile_handle_irq_intc, + .init_machine = sh7372_add_standard_devices_dt, + .timer = &shmobile_timer, + .dt_compat = sh7372_boards_compat_dt, +MACHINE_END + +#endif /* CONFIG_USE_OF */ -- cgit v1.1