From 5707b24a50b40582226618c56692af932db9fe02 Mon Sep 17 00:00:00 2001 From: Aristeu Rozanski Date: Thu, 9 Jul 2009 22:21:13 -0300 Subject: pci: Add a probing code that seeks for an specific bus This patch adds a probing code that seeks for an specific pci bus. It still needs testing, but it is hoped that this will help to identify the memory controller with Xeon 55xx series. Signed-off-by: Aristeu Sergio Signed-off-by: Mauro Carvalho Chehab --- arch/x86/pci/legacy.c | 42 +++++++++++++++++++++++++----------------- 1 file changed, 25 insertions(+), 17 deletions(-) (limited to 'arch/x86/pci') diff --git a/arch/x86/pci/legacy.c b/arch/x86/pci/legacy.c index 0db5eaf..c734c27 100644 --- a/arch/x86/pci/legacy.c +++ b/arch/x86/pci/legacy.c @@ -11,28 +11,14 @@ */ static void __devinit pcibios_fixup_peer_bridges(void) { - int n, devfn; - long node; + int n; if (pcibios_last_bus <= 0 || pcibios_last_bus > 0xff) return; DBG("PCI: Peer bridge fixup\n"); - for (n=0; n <= pcibios_last_bus; n++) { - u32 l; - if (pci_find_bus(0, n)) - continue; - node = get_mp_bus_to_node(n); - for (devfn = 0; devfn < 256; devfn += 8) { - if (!raw_pci_read(0, n, devfn, PCI_VENDOR_ID, 2, &l) && - l != 0x0000 && l != 0xffff) { - DBG("Found device at %02x:%02x [%04x]\n", n, devfn, l); - printk(KERN_INFO "PCI: Discovered peer bus %02x\n", n); - pci_scan_bus_on_node(n, &pci_root_ops, node); - break; - } - } - } + for (n=0; n <= pcibios_last_bus; n++) + pcibios_scan_specific_bus(n); } int __init pci_legacy_init(void) @@ -49,6 +35,28 @@ int __init pci_legacy_init(void) return 0; } +EXPORT_SYMBOL_GPL(pci_legacy_init); + +void pcibios_scan_specific_bus(int busn) +{ + int devfn; + long node; + u32 l; + + if (pci_find_bus(0, busn)) + return; + + node = get_mp_bus_to_node(busn); + for (devfn = 0; devfn < 256; devfn += 8) { + if (!raw_pci_read(0, busn, devfn, PCI_VENDOR_ID, 2, &l) && + l != 0x0000 && l != 0xffff) { + DBG("Found device at %02x:%02x [%04x]\n", busn, devfn, l); + printk(KERN_INFO "PCI: Discovered peer bus %02x\n", busn); + pci_scan_bus_on_node(busn, &pci_root_ops, node); + return; + } + } +} int __init pci_subsys_init(void) { -- cgit v1.1 From d1fd4fb69eeeb7db0693df58b9116db498d5bfe1 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Fri, 10 Jul 2009 18:39:53 -0300 Subject: i7core_edac: Add a code to probe Xeon 55xx bus This code changes the detection procedure of i7core_edac. Instead of directly probing for MC registers, it probes for another register found on Nehalem. If found, it tries to pick the first MC PCI BUS. This should work fine with Xeon 35xx, but, on Xeon 55xx, this is at bus 254 and 255 that are not properly detected by the non-legacy PCI methods. The new detection code scans specifically at buses 254 and 255 for the Xeon 55xx devices. This code has not tested yet. After working, a change at the code will be needed, since the i7core is not yet ready for working with 2 sets of MC. Signed-off-by: Mauro Carvalho Chehab --- arch/x86/pci/legacy.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/x86/pci') diff --git a/arch/x86/pci/legacy.c b/arch/x86/pci/legacy.c index c734c27..d6cc2ed 100644 --- a/arch/x86/pci/legacy.c +++ b/arch/x86/pci/legacy.c @@ -57,6 +57,7 @@ void pcibios_scan_specific_bus(int busn) } } } +EXPORT_SYMBOL_GPL(pcibios_scan_specific_bus); int __init pci_subsys_init(void) { -- cgit v1.1 From 4f7b9e7cbe68c97dbe1266709ecfc8b807b0d0ee Mon Sep 17 00:00:00 2001 From: Stephen Rothwell Date: Fri, 4 Dec 2009 16:49:34 -0200 Subject: i7core_edac: do not export static functions Signed-off-by: Stephen Rothwell Signed-off-by: Mauro Carvalho Chehab --- arch/x86/pci/legacy.c | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/x86/pci') diff --git a/arch/x86/pci/legacy.c b/arch/x86/pci/legacy.c index d6cc2ed..8d460ea 100644 --- a/arch/x86/pci/legacy.c +++ b/arch/x86/pci/legacy.c @@ -35,7 +35,6 @@ int __init pci_legacy_init(void) return 0; } -EXPORT_SYMBOL_GPL(pci_legacy_init); void pcibios_scan_specific_bus(int busn) { -- cgit v1.1