From f50b153b1966230e78034d5ab1641ca4bb5db56d Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Sat, 16 Apr 2005 15:24:22 -0700 Subject: [PATCH] ppc32: Support 36-bit physical addressing on e500 To add support for 36-bit physical addressing on e500 the following changes have been made. The changes are generalized to support any physical address size larger than 32-bits: * Allow FSL Book-E parts to use a 64-bit PTE, it is 44-bits of pfn, 20-bits of flags. * Introduced new CPU feature (CPU_FTR_BIG_PHYS) to allow runtime handling of updating hardware register (SPRN_MAS7) which holds the upper 32-bits of physical address that will be written into the TLB. This is useful since not all e500 cores support 36-bit physical addressing. * Currently have a pass through implementation of fixup_bigphys_addr * Moved _PAGE_DIRTY in the 64-bit PTE case to free room for three additional storage attributes that may exist in future FSL Book-E cores and updated fault handler to copy these bits into the hardware TLBs. Signed-off-by: Kumar Gala Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/ppc/Kconfig | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) (limited to 'arch/ppc/Kconfig') diff --git a/arch/ppc/Kconfig b/arch/ppc/Kconfig index 813c6c9..74aa1e9 100644 --- a/arch/ppc/Kconfig +++ b/arch/ppc/Kconfig @@ -98,13 +98,19 @@ config FSL_BOOKE config PTE_64BIT bool - depends on 44x - default y + depends on 44x || E500 + default y if 44x + default y if E500 && PHYS_64BIT config PHYS_64BIT - bool - depends on 44x - default y + bool 'Large physical address support' if E500 + depends on 44x || E500 + default y if 44x + ---help--- + This option enables kernel support for larger than 32-bit physical + addresses. This features is not be available on all e500 cores. + + If in doubt, say N here. config ALTIVEC bool "AltiVec Support" -- cgit v1.1